IEMInternal.h@ 62145

Last change on this file since 62145 was 62076, checked in by vboxsync, 8 years ago
IEM: Make use of the direct CPUMCTX access (VMCPU_INCL_CPUM_GST_CTX).
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1	/* $Id: IEMInternal.h 62076 2016-07-06 16:37:04Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___IEMInternal_h
19	#define ___IEMInternal_h
20
21	#include <VBox/vmm/cpum.h>
22	#include <VBox/vmm/iem.h>
23	#include <VBox/vmm/stam.h>
24	#include <VBox/param.h>
25
26	#include <setjmp.h>
27
28
29	RT_C_DECLS_BEGIN
30
31
32	/** @defgroup grp_iem_int Internals
33	* @ingroup grp_iem
34	* @internal
35	* @{
36	*/
37
38	/** For expanding symbol in slickedit and other products tagging and
39	* crossreferencing IEM symbols. */
40	#ifndef IEM_STATIC
41	# define IEM_STATIC static
42	#endif
43
44	/** @def IEM_VERIFICATION_MODE_FULL
45	* Shorthand for:
46	* defined(IEM_VERIFICATION_MODE) && !defined(IEM_VERIFICATION_MODE_MINIMAL)
47	*/
48	#if (defined(IEM_VERIFICATION_MODE) && !defined(IEM_VERIFICATION_MODE_MINIMAL) && !defined(IEM_VERIFICATION_MODE_FULL)) \
49	\|\| defined(DOXYGEN_RUNNING)
50	# define IEM_VERIFICATION_MODE_FULL
51	#endif
52
53
54	/** @def IEM_CFG_TARGET_CPU
55	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
56	*
57	* By default we allow this to be configured by the user via the
58	* CPUM/GuestCpuName config string, but this comes at a slight cost during
59	* decoding. So, for applications of this code where there is no need to
60	* be dynamic wrt target CPU, just modify this define.
61	*/
62	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
63	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
64	#endif
65
66
67
68	/** Finish and move to types.h */
69	typedef union
70	{
71	uint32_t u32;
72	} RTFLOAT32U;
73	typedef RTFLOAT32U *PRTFLOAT32U;
74	typedef RTFLOAT32U const *PCRTFLOAT32U;
75
76
77	/**
78	* Extended operand mode that includes a representation of 8-bit.
79	*
80	* This is used for packing down modes when invoking some C instruction
81	* implementations.
82	*/
83	typedef enum IEMMODEX
84	{
85	IEMMODEX_16BIT = IEMMODE_16BIT,
86	IEMMODEX_32BIT = IEMMODE_32BIT,
87	IEMMODEX_64BIT = IEMMODE_64BIT,
88	IEMMODEX_8BIT
89	} IEMMODEX;
90	AssertCompileSize(IEMMODEX, 4);
91
92
93	/**
94	* Branch types.
95	*/
96	typedef enum IEMBRANCH
97	{
98	IEMBRANCH_JUMP = 1,
99	IEMBRANCH_CALL,
100	IEMBRANCH_TRAP,
101	IEMBRANCH_SOFTWARE_INT,
102	IEMBRANCH_HARDWARE_INT
103	} IEMBRANCH;
104	AssertCompileSize(IEMBRANCH, 4);
105
106
107	/**
108	* A FPU result.
109	*/
110	typedef struct IEMFPURESULT
111	{
112	/** The output value. */
113	RTFLOAT80U r80Result;
114	/** The output status. */
115	uint16_t FSW;
116	} IEMFPURESULT;
117	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
118	/** Pointer to a FPU result. */
119	typedef IEMFPURESULT *PIEMFPURESULT;
120	/** Pointer to a const FPU result. */
121	typedef IEMFPURESULT const *PCIEMFPURESULT;
122
123
124	/**
125	* A FPU result consisting of two output values and FSW.
126	*/
127	typedef struct IEMFPURESULTTWO
128	{
129	/** The first output value. */
130	RTFLOAT80U r80Result1;
131	/** The output status. */
132	uint16_t FSW;
133	/** The second output value. */
134	RTFLOAT80U r80Result2;
135	} IEMFPURESULTTWO;
136	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
137	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
138	/** Pointer to a FPU result consisting of two output values and FSW. */
139	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
140	/** Pointer to a const FPU result consisting of two output values and FSW. */
141	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
142
143
144
145	#ifdef IEM_VERIFICATION_MODE_FULL
146
147	/**
148	* Verification event type.
149	*/
150	typedef enum IEMVERIFYEVENT
151	{
152	IEMVERIFYEVENT_INVALID = 0,
153	IEMVERIFYEVENT_IOPORT_READ,
154	IEMVERIFYEVENT_IOPORT_WRITE,
155	IEMVERIFYEVENT_IOPORT_STR_READ,
156	IEMVERIFYEVENT_IOPORT_STR_WRITE,
157	IEMVERIFYEVENT_RAM_WRITE,
158	IEMVERIFYEVENT_RAM_READ
159	} IEMVERIFYEVENT;
160
161	/** Checks if the event type is a RAM read or write. */
162	# define IEMVERIFYEVENT_IS_RAM(a_enmType) ((a_enmType) == IEMVERIFYEVENT_RAM_WRITE \|\| (a_enmType) == IEMVERIFYEVENT_RAM_READ)
163
164	/**
165	* Verification event record.
166	*/
167	typedef struct IEMVERIFYEVTREC
168	{
169	/** Pointer to the next record in the list. */
170	struct IEMVERIFYEVTREC *pNext;
171	/** The event type. */
172	IEMVERIFYEVENT enmEvent;
173	/** The event data. */
174	union
175	{
176	/** IEMVERIFYEVENT_IOPORT_READ */
177	struct
178	{
179	RTIOPORT Port;
180	uint8_t cbValue;
181	} IOPortRead;
182
183	/** IEMVERIFYEVENT_IOPORT_WRITE */
184	struct
185	{
186	RTIOPORT Port;
187	uint8_t cbValue;
188	uint32_t u32Value;
189	} IOPortWrite;
190
191	/** IEMVERIFYEVENT_IOPORT_STR_READ */
192	struct
193	{
194	RTIOPORT Port;
195	uint8_t cbValue;
196	RTGCUINTREG cTransfers;
197	} IOPortStrRead;
198
199	/** IEMVERIFYEVENT_IOPORT_STR_WRITE */
200	struct
201	{
202	RTIOPORT Port;
203	uint8_t cbValue;
204	RTGCUINTREG cTransfers;
205	} IOPortStrWrite;
206
207	/** IEMVERIFYEVENT_RAM_READ */
208	struct
209	{
210	RTGCPHYS GCPhys;
211	uint32_t cb;
212	} RamRead;
213
214	/** IEMVERIFYEVENT_RAM_WRITE */
215	struct
216	{
217	RTGCPHYS GCPhys;
218	uint32_t cb;
219	uint8_t ab[512];
220	} RamWrite;
221	} u;
222	} IEMVERIFYEVTREC;
223	/** Pointer to an IEM event verification records. */
224	typedef IEMVERIFYEVTREC *PIEMVERIFYEVTREC;
225
226	#endif /* IEM_VERIFICATION_MODE_FULL */
227
228
229	/**
230	* IEM TLB entry.
231	*
232	* Lookup assembly:
233	* @code{.asm}
234	; Calculate tag.
235	mov rax, [VA]
236	shl rax, 16
237	shr rax, 16 + X86_PAGE_SHIFT
238	or rax, [uTlbRevision]
239
240	; Do indexing.
241	movzx ecx, al
242	lea rcx, [pTlbEntries + rcx]
243
244	; Check tag.
245	cmp [rcx + IEMTLBENTRY.uTag], rax
246	jne .TlbMiss
247
248	; Check access.
249	movsx rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
250	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
251	cmp rax, [uTlbPhysRev]
252	jne .TlbMiss
253
254	; Calc address and we're done.
255	mov eax, X86_PAGE_OFFSET_MASK
256	and eax, [VA]
257	or rax, [rcx + IEMTLBENTRY.pMappingR3]
258	%ifdef VBOX_WITH_STATISTICS
259	inc qword [cTlbHits]
260	%endif
261	jmp .Done
262
263	.TlbMiss:
264	mov r8d, ACCESS_FLAGS
265	mov rdx, [VA]
266	mov rcx, [pVCpu]
267	call iemTlbTypeMiss
268	.Done:
269
270	@endcode
271	*
272	*/
273	typedef struct IEMTLBENTRY
274	{
275	/** The TLB entry tag.
276	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits.
277	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
278	*
279	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
280	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
281	* revision wraps around though, the tags needs to be zeroed.
282	*
283	* @note Try use SHRD instruction? After seeing
284	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
285	*/
286	uint64_t uTag;
287	/** Access flags and physical TLB revision.
288	*
289	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
290	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
291	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
292	* - Bit 3 - pgm phys/virt - not directly writable.
293	* - Bit 4 - pgm phys page - not directly readable.
294	* - Bit 5 - currently unused.
295	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
296	* - Bit 7 - tlb entry - pMappingR3 member not valid.
297	* - Bits 63 thru 8 are used for the physical TLB revision number.
298	*
299	* We're using complemented bit meanings here because it makes it easy to check
300	* whether special action is required. For instance a user mode write access
301	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
302	* non-zero result would mean special handling needed because either it wasn't
303	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
304	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
305	* need to check any PTE flag.
306	*/
307	uint64_t fFlagsAndPhysRev;
308	/** The guest physical page address. */
309	uint64_t GCPhys;
310	/** Pointer to the ring-3 mapping (possibly also valid in ring-0). */
311	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
312	R3PTRTYPE(uint8_t *) pMappingR3;
313	#else
314	R3R0PTRTYPE(uint8_t *) pMappingR3;
315	#endif
316	#if HC_ARCH_BITS == 32
317	uint32_t u32Padding1;
318	#endif
319	} IEMTLBENTRY;
320	AssertCompileSize(IEMTLBENTRY, 32);
321
322	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
323	* @{ */
324	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
325	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
326	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
327	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
328	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
329	#define IEMTLBE_F_UNUSED RT_BIT_64(5) /*< Currently unused. /
330	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
331	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
332	/** @} */
333
334
335	/**
336	* An IEM TLB.
337	*
338	* We've got two of these, one for data and one for instructions.
339	*/
340	typedef struct IEMTLB
341	{
342	/** The TLB entries.
343	* We've choosen 256 because that way we can obtain the result directly from a
344	* 8-bit register without an additional AND instruction. */
345	IEMTLBENTRY aEntries[256];
346	/** The TLB revision.
347	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
348	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
349	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
350	* (The revision zero indicates an invalid TLB entry.)
351	*
352	* The initial value is choosen to cause an early wraparound. */
353	uint64_t uTlbRevision;
354	/** The TLB physical address revision - shadow of PGM variable.
355	*
356	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
357	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
358	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
359	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
360	*
361	* The initial value is choosen to cause an early wraparound. */
362	uint64_t volatile uTlbPhysRev;
363
364	/* Statistics: */
365
366	/** TLB hits (VBOX_WITH_STATISTICS only). */
367	uint64_t cTlbHits;
368	/** TLB misses. */
369	uint32_t cTlbMisses;
370	/** TLB misses because of tag mismatch. */
371	uint32_t cTlbMissesTag;
372	/** TLB misses because of virtual access violation. */
373	uint32_t cTlbMissesVirtAccess;
374	/** TLB misses because of dirty bit. */
375	uint32_t cTlbMissesDirty;
376	/** TLB misses because of MMIO */
377	uint32_t cTlbMissesMmio;
378	/** TLB misses because of write access handlers. */
379	uint32_t cTlbMissesWriteHandler;
380	/** TLB misses because no r3(/r0) mapping. */
381	uint32_t cTlbMissesMapping;
382	/** Alignment padding. */
383	uint32_t au32Padding[3];
384	} IEMTLB;
385	AssertCompileSizeAlignment(IEMTLB, 64);
386
387
388	/**
389	* The per-CPU IEM state.
390	*/
391	typedef struct IEMCPU
392	{
393	/** Pointer to the CPU context - ring-3 context. */
394	R3PTRTYPE(PCPUMCTX) pCtxR3;
395	/** Pointer to the CPU context - ring-0 context. */
396	R0PTRTYPE(PCPUMCTX) pCtxR0;
397	/** Pointer to the CPU context - raw-mode context. */
398	RCPTRTYPE(PCPUMCTX) pCtxRC;
399
400	/** Info status code that needs to be propagated to the IEM caller.
401	* This cannot be passed internally, as it would complicate all success
402	* checks within the interpreter making the code larger and almost impossible
403	* to get right. Instead, we'll store status codes to pass on here. Each
404	* source of these codes will perform appropriate sanity checks. */
405	int32_t rcPassUp;
406
407	/** The current CPU execution mode (CS). */
408	IEMMODE enmCpuMode;
409	/** The CPL. */
410	uint8_t uCpl;
411
412	/** Whether to bypass access handlers or not. */
413	bool fBypassHandlers;
414	/** Indicates that we're interpreting patch code - RC only! */
415	bool fInPatchCode;
416
417	/** @name Decoder state.
418	* @{ */
419	/** The current offset into abOpcodes. */
420	uint8_t offOpcode;
421	/** The size of what has currently been fetched into abOpcodes. */
422	uint8_t cbOpcode;
423
424	/** The effective segment register (X86_SREG_XXX). */
425	uint8_t iEffSeg;
426
427	/** The extra REX ModR/M register field bit (REX.R << 3). */
428	uint8_t uRexReg;
429	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
430	* (REX.B << 3). */
431	uint8_t uRexB;
432	/** The prefix mask (IEM_OP_PRF_XXX). */
433	uint32_t fPrefixes;
434	/** The extra REX SIB index field bit (REX.X << 3). */
435	uint8_t uRexIndex;
436
437	/** Offset into abOpcodes where the FPU instruction starts.
438	* Only set by the FPU escape opcodes (0xd8-0xdf) and used later on when the
439	* instruction result is committed. */
440	uint8_t offFpuOpcode;
441
442	/** Explicit alignment padding. */
443	uint8_t abAlignment1[2];
444
445	/** The effective operand mode . */
446	IEMMODE enmEffOpSize;
447	/** The default addressing mode . */
448	IEMMODE enmDefAddrMode;
449	/** The effective addressing mode . */
450	IEMMODE enmEffAddrMode;
451	/** The default operand mode . */
452	IEMMODE enmDefOpSize;
453
454	/** The opcode bytes. */
455	uint8_t abOpcode[15];
456	/** Explicit alignment padding. */
457	uint8_t abAlignment2[HC_ARCH_BITS == 64 ? 5 : 5];
458	/** @} */
459
460	/** The flags of the current exception / interrupt. */
461	uint32_t fCurXcpt;
462	/** The current exception / interrupt. */
463	uint8_t uCurXcpt;
464	/** Exception / interrupt recursion depth. */
465	int8_t cXcptRecursions;
466
467	/** The number of active guest memory mappings. */
468	uint8_t cActiveMappings;
469	/** The next unused mapping index. */
470	uint8_t iNextMapping;
471	/** Records for tracking guest memory mappings. */
472	struct
473	{
474	/** The address of the mapped bytes. */
475	void *pv;
476	#if defined(IN_RC) && HC_ARCH_BITS == 64
477	uint32_t u32Alignment3; /*< Alignment padding. /
478	#endif
479	/** The access flags (IEM_ACCESS_XXX).
480	* IEM_ACCESS_INVALID if the entry is unused. */
481	uint32_t fAccess;
482	#if HC_ARCH_BITS == 64
483	uint32_t u32Alignment4; /*< Alignment padding. /
484	#endif
485	} aMemMappings[3];
486
487	/** Locking records for the mapped memory. */
488	union
489	{
490	PGMPAGEMAPLOCK Lock;
491	uint64_t au64Padding[2];
492	} aMemMappingLocks[3];
493
494	/** Bounce buffer info.
495	* This runs in parallel to aMemMappings. */
496	struct
497	{
498	/** The physical address of the first byte. */
499	RTGCPHYS GCPhysFirst;
500	/** The physical address of the second page. */
501	RTGCPHYS GCPhysSecond;
502	/** The number of bytes in the first page. */
503	uint16_t cbFirst;
504	/** The number of bytes in the second page. */
505	uint16_t cbSecond;
506	/** Whether it's unassigned memory. */
507	bool fUnassigned;
508	/** Explicit alignment padding. */
509	bool afAlignment5[3];
510	} aMemBbMappings[3];
511
512	/** Bounce buffer storage.
513	* This runs in parallel to aMemMappings and aMemBbMappings. */
514	struct
515	{
516	uint8_t ab[512];
517	} aBounceBuffers[3];
518
519
520	/** Pointer set jump buffer - ring-3 context. */
521	R3PTRTYPE(jmp_buf *) pJmpBufR3;
522	/** Pointer set jump buffer - ring-0 context. */
523	R0PTRTYPE(jmp_buf *) pJmpBufR0;
524	/** Pointer set jump buffer - raw-mode context. */
525	RCPTRTYPE(jmp_buf *) pJmpBufRC;
526
527
528	/** @name Statistics
529	* @{ */
530	/** The number of instructions we've executed. */
531	uint32_t cInstructions;
532	/** The number of potential exits. */
533	uint32_t cPotentialExits;
534	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
535	* This may contain uncommitted writes. */
536	uint32_t cbWritten;
537	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
538	uint32_t cRetInstrNotImplemented;
539	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
540	uint32_t cRetAspectNotImplemented;
541	/** Counts informational statuses returned (other than VINF_SUCCESS). */
542	uint32_t cRetInfStatuses;
543	/** Counts other error statuses returned. */
544	uint32_t cRetErrStatuses;
545	/** Number of times rcPassUp has been used. */
546	uint32_t cRetPassUpStatus;
547	/** Number of times RZ left with instruction commit pending for ring-3. */
548	uint32_t cPendingCommit;
549	/** Number of long jumps. */
550	uint32_t cLongJumps;
551	uint32_t uPadding; /*< Alignment padding. /
552	#ifdef IEM_VERIFICATION_MODE_FULL
553	/** The Number of I/O port reads that has been performed. */
554	uint32_t cIOReads;
555	/** The Number of I/O port writes that has been performed. */
556	uint32_t cIOWrites;
557	/** Set if no comparison to REM is currently performed.
558	* This is used to skip past really slow bits. */
559	bool fNoRem;
560	/** Saved fNoRem flag used by #iemInitExec and #iemUninitExec. */
561	bool fNoRemSavedByExec;
562	/** Indicates that RAX and RDX differences should be ignored since RDTSC
563	* and RDTSCP are timing sensitive. */
564	bool fIgnoreRaxRdx;
565	/** Indicates that a MOVS instruction with overlapping source and destination
566	* was executed, causing the memory write records to be incorrrect. */
567	bool fOverlappingMovs;
568	/** Set if there are problematic memory accesses (MMIO, write monitored, ++). */
569	bool fProblematicMemory;
570	/** This is used to communicate a CPL changed caused by IEMInjectTrap that
571	* CPUM doesn't yet reflect. */
572	uint8_t uInjectCpl;
573	/** To prevent EMR3HmSingleInstruction from triggering endless recursion via
574	* emR3ExecuteInstruction and iemExecVerificationModeCheck. */
575	uint8_t cVerifyDepth;
576	bool afAlignment2[2];
577	/** Mask of undefined eflags.
578	* The verifier will any difference in these flags. */
579	uint32_t fUndefinedEFlags;
580	/** The CS of the instruction being interpreted. */
581	RTSEL uOldCs;
582	/** The RIP of the instruction being interpreted. */
583	uint64_t uOldRip;
584	/** The physical address corresponding to abOpcodes[0]. */
585	RTGCPHYS GCPhysOpcodes;
586	#endif
587	/** @} */
588
589	/** @name Target CPU information.
590	* @{ */
591	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
592	/** The target CPU. */
593	uint32_t uTargetCpu;
594	#else
595	uint32_t u32TargetCpuPadding;
596	#endif
597	/** The CPU vendor. */
598	CPUMCPUVENDOR enmCpuVendor;
599	/** @} */
600
601	/** @name Host CPU information.
602	* @{ */
603	/** The CPU vendor. */
604	CPUMCPUVENDOR enmHostCpuVendor;
605	/** @} */
606
607	uint32_t au32Alignment6[HC_ARCH_BITS == 64 ? 1 + 4 + 8 : 1 + 2 + 4]; /*< Alignment padding. /
608
609	/** Data TLB.
610	* @remarks Must be 64-byte aligned. */
611	IEMTLB DataTlb;
612	/** Instruction TLB.
613	* @remarks Must be 64-byte aligned. */
614	IEMTLB CodeTlb;
615
616	#ifdef IEM_VERIFICATION_MODE_FULL
617	/** The event verification records for what IEM did (LIFO). */
618	R3PTRTYPE(PIEMVERIFYEVTREC) pIemEvtRecHead;
619	/** Insertion point for pIemEvtRecHead. */
620	R3PTRTYPE(PIEMVERIFYEVTREC *) ppIemEvtRecNext;
621	/** The event verification records for what the other party did (FIFO). */
622	R3PTRTYPE(PIEMVERIFYEVTREC) pOtherEvtRecHead;
623	/** Insertion point for pOtherEvtRecHead. */
624	R3PTRTYPE(PIEMVERIFYEVTREC *) ppOtherEvtRecNext;
625	/** List of free event records. */
626	R3PTRTYPE(PIEMVERIFYEVTREC) pFreeEvtRec;
627	#endif
628	} IEMCPU;
629	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
630	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
631	/** Pointer to the per-CPU IEM state. */
632	typedef IEMCPU *PIEMCPU;
633	/** Pointer to the const per-CPU IEM state. */
634	typedef IEMCPU const *PCIEMCPU;
635
636
637	/** @def IEM_GET_CTX
638	* Gets the guest CPU context for the calling EMT.
639	* @returns PCPUMCTX
640	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
641	*/
642	#if !defined(IEM_VERIFICATION_MODE_FULL) && !defined(IEM_VERIFICATION_MODE) \
643	&& !defined(IEM_VERIFICATION_MODE_MINIMAL) && defined(VMCPU_INCL_CPUM_GST_CTX)
644	# define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
645	#else
646	# define IEM_GET_CTX(a_pVCpu) ((a_pVCpu)->iem.s.CTX_SUFF(pCtx))
647	#endif
648
649	/** Gets the current IEMTARGETCPU value.
650	* @returns IEMTARGETCPU value.
651	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
652	*/
653	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
654	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
655	#else
656	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
657	#endif
658
659	/** @name IEM_ACCESS_XXX - Access details.
660	* @{ */
661	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
662	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
663	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
664	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
665	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
666	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
667	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
668	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
669	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
670	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
671	/** The writes are partial, so if initialize the bounce buffer with the
672	* orignal RAM content. */
673	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
674	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
675	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
676	/** Bounce buffer with ring-3 write pending, first page. */
677	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
678	/** Bounce buffer with ring-3 write pending, second page. */
679	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
680	/** Valid bit mask. */
681	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00000fff)
682	/** Read+write data alias. */
683	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
684	/** Write data alias. */
685	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
686	/** Read data alias. */
687	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
688	/** Instruction fetch alias. */
689	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
690	/** Stack write alias. */
691	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
692	/** Stack read alias. */
693	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
694	/** Stack read+write alias. */
695	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
696	/** Read system table alias. */
697	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
698	/** Read+write system table alias. */
699	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
700	/** @} */
701
702	/** @name Prefix constants (IEMCPU::fPrefixes)
703	* @{ */
704	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
705	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
706	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
707	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
708	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
709	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
710	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
711
712	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
713	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
714	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
715
716	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
717	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
718	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
719
720	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
721	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
722	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
723	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
724	/** Mask with all the REX prefix flags.
725	* This is generally for use when needing to undo the REX prefixes when they
726	* are followed legacy prefixes and therefore does not immediately preceed
727	* the first opcode byte.
728	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
729	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
730	/** @} */
731
732	/** @name Opcode forms
733	* @{ */
734	/** ModR/M: reg, r/m */
735	#define IEMOPFORM_RM 0
736	/** ModR/M: reg, r/m (register) */
737	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
738	/** ModR/M: reg, r/m (memory) */
739	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
740	/** ModR/M: r/m, reg */
741	#define IEMOPFORM_MR 1
742	/** ModR/M: r/m (register), reg */
743	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
744	/** ModR/M: r/m (memory), reg */
745	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
746	/** ModR/M: r/m only */
747	#define IEMOPFORM_M 2
748	/** ModR/M: r/m only (register). */
749	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
750	/** ModR/M: r/m only (memory). */
751	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
752	/** ModR/M: reg only */
753	#define IEMOPFORM_R 3
754
755	/** Fixed register instruction, no R/M. */
756	#define IEMOPFORM_FIXED 4
757
758	/** The r/m is a register. */
759	#define IEMOPFORM_MOD3 RT_BIT_32(8)
760	/** The r/m is a memory access. */
761	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
762	/** @} */
763
764	/**
765	* Possible hardware task switch sources.
766	*/
767	typedef enum IEMTASKSWITCH
768	{
769	/** Task switch caused by an interrupt/exception. */
770	IEMTASKSWITCH_INT_XCPT = 1,
771	/** Task switch caused by a far CALL. */
772	IEMTASKSWITCH_CALL,
773	/** Task switch caused by a far JMP. */
774	IEMTASKSWITCH_JUMP,
775	/** Task switch caused by an IRET. */
776	IEMTASKSWITCH_IRET
777	} IEMTASKSWITCH;
778	AssertCompileSize(IEMTASKSWITCH, 4);
779
780
781	/**
782	* Tests if verification mode is enabled.
783	*
784	* This expands to @c false when IEM_VERIFICATION_MODE is not defined and
785	* should therefore cause the compiler to eliminate the verification branch
786	* of an if statement. */
787	#ifdef IEM_VERIFICATION_MODE_FULL
788	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
789	#elif defined(IEM_VERIFICATION_MODE_MINIMAL)
790	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (true)
791	#else
792	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (false)
793	#endif
794
795	/**
796	* Tests if full verification mode is enabled.
797	*
798	* This expands to @c false when IEM_VERIFICATION_MODE_FULL is not defined and
799	* should therefore cause the compiler to eliminate the verification branch
800	* of an if statement. */
801	#ifdef IEM_VERIFICATION_MODE_FULL
802	# define IEM_FULL_VERIFICATION_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
803	#else
804	# define IEM_FULL_VERIFICATION_ENABLED(a_pVCpu) (false)
805	#endif
806
807	/**
808	* Tests if full verification mode is enabled again REM.
809	*
810	* This expands to @c false when IEM_VERIFICATION_MODE_FULL is not defined and
811	* should therefore cause the compiler to eliminate the verification branch
812	* of an if statement. */
813	#ifdef IEM_VERIFICATION_MODE_FULL
814	# ifdef IEM_VERIFICATION_MODE_FULL_HM
815	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem && !HMIsEnabled((a_pVCpu)->CTX_SUFF(pVM)))
816	# else
817	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
818	# endif
819	#else
820	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (false)
821	#endif
822
823	/** @def IEM_VERIFICATION_MODE
824	* Indicates that one of the verfication modes are enabled.
825	*/
826	#if (defined(IEM_VERIFICATION_MODE_FULL) \|\| defined(IEM_VERIFICATION_MODE_MINIMAL)) && !defined(IEM_VERIFICATION_MODE) \
827	\|\| defined(DOXYGEN_RUNNING)
828	# define IEM_VERIFICATION_MODE
829	#endif
830
831	/**
832	* Indicates to the verifier that the given flag set is undefined.
833	*
834	* Can be invoked again to add more flags.
835	*
836	* This is a NOOP if the verifier isn't compiled in.
837	*/
838	#ifdef IEM_VERIFICATION_MODE_FULL
839	# define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { pVCpu->iem.s.fUndefinedEFlags \|= (a_fEfl); } while (0)
840	#else
841	# define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
842	#endif
843
844
845	/** @def IEM_DECL_IMPL_TYPE
846	* For typedef'ing an instruction implementation function.
847	*
848	* @param a_RetType The return type.
849	* @param a_Name The name of the type.
850	* @param a_ArgList The argument list enclosed in parentheses.
851	*/
852
853	/** @def IEM_DECL_IMPL_DEF
854	* For defining an instruction implementation function.
855	*
856	* @param a_RetType The return type.
857	* @param a_Name The name of the type.
858	* @param a_ArgList The argument list enclosed in parentheses.
859	*/
860
861	#if defined(__GNUC__) && defined(RT_ARCH_X86)
862	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
863	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
864	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
865	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
866
867	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
868	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
869	a_RetType (__fastcall a_Name) a_ArgList
870	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
871	a_RetType __fastcall a_Name a_ArgList
872
873	#else
874	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
875	a_RetType (VBOXCALL a_Name) a_ArgList
876	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
877	a_RetType VBOXCALL a_Name a_ArgList
878
879	#endif
880
881	/** @name Arithmetic assignment operations on bytes (binary).
882	* @{ */
883	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
884	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
885	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
886	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
887	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
888	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
889	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
890	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
891	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
892	/** @} */
893
894	/** @name Arithmetic assignment operations on words (binary).
895	* @{ */
896	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
897	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
898	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
899	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
900	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
901	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
902	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
903	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
904	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
905	/** @} */
906
907	/** @name Arithmetic assignment operations on double words (binary).
908	* @{ */
909	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
910	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
911	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
912	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
913	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
914	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
915	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
916	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
917	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
918	/** @} */
919
920	/** @name Arithmetic assignment operations on quad words (binary).
921	* @{ */
922	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
923	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
924	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
925	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
926	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
927	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
928	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
929	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
930	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
931	/** @} */
932
933	/** @name Compare operations (thrown in with the binary ops).
934	* @{ */
935	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
936	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
937	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
938	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
939	/** @} */
940
941	/** @name Test operations (thrown in with the binary ops).
942	* @{ */
943	FNIEMAIMPLBINU8 iemAImpl_test_u8;
944	FNIEMAIMPLBINU16 iemAImpl_test_u16;
945	FNIEMAIMPLBINU32 iemAImpl_test_u32;
946	FNIEMAIMPLBINU64 iemAImpl_test_u64;
947	/** @} */
948
949	/** @name Bit operations operations (thrown in with the binary ops).
950	* @{ */
951	FNIEMAIMPLBINU16 iemAImpl_bt_u16, iemAImpl_bt_u16_locked;
952	FNIEMAIMPLBINU32 iemAImpl_bt_u32, iemAImpl_bt_u32_locked;
953	FNIEMAIMPLBINU64 iemAImpl_bt_u64, iemAImpl_bt_u64_locked;
954	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
955	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
956	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
957	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
958	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
959	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
960	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
961	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
962	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
963	/** @} */
964
965	/** @name Exchange memory with register operations.
966	* @{ */
967	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8, (uint8_t pu8Mem, uint8_t pu8Reg));
968	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16,(uint16_t pu16Mem, uint16_t pu16Reg));
969	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32,(uint32_t pu32Mem, uint32_t pu32Reg));
970	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64,(uint64_t pu64Mem, uint64_t pu64Reg));
971	/** @} */
972
973	/** @name Exchange and add operations.
974	* @{ */
975	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
976	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
977	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
978	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
979	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
980	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
981	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
982	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
983	/** @} */
984
985	/** @name Compare and exchange.
986	* @{ */
987	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
988	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
989	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
990	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
991	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
992	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
993	#ifdef RT_ARCH_X86
994	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
995	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
996	#else
997	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
998	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
999	#endif
1000	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1001	uint32_t *pEFlags));
1002	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1003	uint32_t *pEFlags));
1004	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U *pu128Dst, PRTUINT128U pu64RaxRdx, PRTUINT128U pu64RbxRcx,
1005	uint32_t *pEFlags));
1006	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U *pu128Dst, PRTUINT128U pu64RaxRdx, PRTUINT128U pu64RbxRcx,
1007	uint32_t *pEFlags));
1008	/** @} */
1009
1010	/** @name Memory ordering
1011	* @{ */
1012	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1013	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1014	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1015	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1016	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1017	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1018	/** @} */
1019
1020	/** @name Double precision shifts
1021	* @{ */
1022	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1023	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1024	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1025	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1026	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1027	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1028	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16;
1029	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32;
1030	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64;
1031	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16;
1032	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32;
1033	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64;
1034	/** @} */
1035
1036
1037	/** @name Bit search operations (thrown in with the binary ops).
1038	* @{ */
1039	FNIEMAIMPLBINU16 iemAImpl_bsf_u16;
1040	FNIEMAIMPLBINU32 iemAImpl_bsf_u32;
1041	FNIEMAIMPLBINU64 iemAImpl_bsf_u64;
1042	FNIEMAIMPLBINU16 iemAImpl_bsr_u16;
1043	FNIEMAIMPLBINU32 iemAImpl_bsr_u32;
1044	FNIEMAIMPLBINU64 iemAImpl_bsr_u64;
1045	/** @} */
1046
1047	/** @name Signed multiplication operations (thrown in with the binary ops).
1048	* @{ */
1049	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16;
1050	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32;
1051	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64;
1052	/** @} */
1053
1054	/** @name Arithmetic assignment operations on bytes (unary).
1055	* @{ */
1056	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1057	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1058	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1059	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1060	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1061	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1062	/** @} */
1063
1064	/** @name Arithmetic assignment operations on words (unary).
1065	* @{ */
1066	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1067	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1068	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1069	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1070	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1071	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1072	/** @} */
1073
1074	/** @name Arithmetic assignment operations on double words (unary).
1075	* @{ */
1076	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1077	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1078	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1079	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1080	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1081	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1082	/** @} */
1083
1084	/** @name Arithmetic assignment operations on quad words (unary).
1085	* @{ */
1086	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1087	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1088	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1089	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1090	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1091	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1092	/** @} */
1093
1094
1095	/** @name Shift operations on bytes (Group 2).
1096	* @{ */
1097	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1098	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1099	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8;
1100	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8;
1101	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8;
1102	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8;
1103	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8;
1104	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8;
1105	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8;
1106	/** @} */
1107
1108	/** @name Shift operations on words (Group 2).
1109	* @{ */
1110	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1111	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1112	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16;
1113	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16;
1114	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16;
1115	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16;
1116	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16;
1117	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16;
1118	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16;
1119	/** @} */
1120
1121	/** @name Shift operations on double words (Group 2).
1122	* @{ */
1123	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1124	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1125	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32;
1126	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32;
1127	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32;
1128	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32;
1129	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32;
1130	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32;
1131	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32;
1132	/** @} */
1133
1134	/** @name Shift operations on words (Group 2).
1135	* @{ */
1136	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1137	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1138	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64;
1139	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64;
1140	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64;
1141	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64;
1142	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64;
1143	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64;
1144	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64;
1145	/** @} */
1146
1147	/** @name Multiplication and division operations.
1148	* @{ */
1149	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1150	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1151	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_imul_u8;
1152	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_idiv_u8;
1153
1154	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1155	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1156	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_imul_u16;
1157	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_idiv_u16;
1158
1159	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1160	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1161	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_imul_u32;
1162	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_idiv_u32;
1163
1164	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1165	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1166	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_imul_u64;
1167	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_idiv_u64;
1168	/** @} */
1169
1170	/** @name Byte Swap.
1171	* @{ */
1172	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1173	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1174	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1175	/** @} */
1176
1177	/** @name Misc.
1178	* @{ */
1179	FNIEMAIMPLBINU16 iemAImpl_arpl;
1180	/** @} */
1181
1182
1183	/** @name FPU operations taking a 32-bit float argument
1184	* @{ */
1185	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1186	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1187	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1188
1189	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1190	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1191	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1192
1193	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1194	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1195	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1196	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1197	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1198	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1199	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1200
1201	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1202	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1203	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1204	/** @} */
1205
1206	/** @name FPU operations taking a 64-bit float argument
1207	* @{ */
1208	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1209	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1210	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1211
1212	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1213	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1214	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1215	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1216	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1217	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1218
1219	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1220	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1221	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1222	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1223	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1224	/** @} */
1225
1226	/** @name FPU operations taking a 80-bit float argument
1227	* @{ */
1228	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1229	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1230	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1231	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1232	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1233	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1234	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1235	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1236	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1237	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1238	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1239	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1240
1241	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80;
1242	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80;
1243
1244	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1245	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1246	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1247	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1248	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1249
1250	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1251	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1252	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1253	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1254	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1255
1256	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1257	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1258	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1259	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1260	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80;
1261	FNIEMAIMPLFPUR80UNARY iemAImpl_fyl2x_r80;
1262	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1263	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1264	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80;
1265	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80;
1266
1267	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1268	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1269	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1270	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1271
1272	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1273	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1274	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1275	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1276	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1277	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1278	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1279	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1280	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1281
1282	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1283	PCRTFLOAT80U pr80Val));
1284	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1285	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80;
1286	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1287	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80;
1288
1289	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1290	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1291	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1292
1293	/** @} */
1294
1295	/** @name FPU operations taking a 16-bit signed integer argument
1296	* @{ */
1297	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1298	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1299	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1300
1301	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1302	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1303	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1304	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1305	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1306	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1307
1308	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1309	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1310
1311	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1312	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1313	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1314	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1315	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1316	/** @} */
1317
1318	/** @name FPU operations taking a 32-bit signed integer argument
1319	* @{ */
1320	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1321	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1322	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1323
1324	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1325	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1326	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1327	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1328	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1329	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1330
1331	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1332	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1333
1334	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1335	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1336	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1337	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1338	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1339	/** @} */
1340
1341	/** @name FPU operations taking a 64-bit signed integer argument
1342	* @{ */
1343	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1344	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1345	typedef FNIEMAIMPLFPUI64 *PFNIEMAIMPLFPUI64;
1346
1347	FNIEMAIMPLFPUI64 iemAImpl_fiadd_r80_by_i64;
1348	FNIEMAIMPLFPUI64 iemAImpl_fimul_r80_by_i64;
1349	FNIEMAIMPLFPUI64 iemAImpl_fisub_r80_by_i64;
1350	FNIEMAIMPLFPUI64 iemAImpl_fisubr_r80_by_i64;
1351	FNIEMAIMPLFPUI64 iemAImpl_fidiv_r80_by_i64;
1352	FNIEMAIMPLFPUI64 iemAImpl_fidivr_r80_by_i64;
1353
1354	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1355	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1356
1357	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1358	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1359	int64_t *pi64Val, PCRTFLOAT80U pr80Val));
1360	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1361	int64_t *pi32Val, PCRTFLOAT80U pr80Val));
1362	/** @} */
1363
1364
1365	/** Temporary type representing a 256-bit vector register. */
1366	typedef struct {uint64_t au64[4]; } IEMVMM256;
1367	/** Temporary type pointing to a 256-bit vector register. */
1368	typedef IEMVMM256 *PIEMVMM256;
1369	/** Temporary type pointing to a const 256-bit vector register. */
1370	typedef IEMVMM256 *PCIEMVMM256;
1371
1372
1373	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1374	* @{ */
1375	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1376	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1377	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, uint128_t pu128Dst, uint128_t const pu128Src));
1378	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1379	FNIEMAIMPLMEDIAF2U64 iemAImpl_pxor_u64, iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1380	FNIEMAIMPLMEDIAF2U128 iemAImpl_pxor_u128, iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1381	/** @} */
1382
1383	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1384	* @{ */
1385	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src));
1386	typedef FNIEMAIMPLMEDIAF1L1U64 *PFNIEMAIMPLMEDIAF1L1U64;
1387	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U128,(PCX86FXSTATE pFpuState, uint128_t pu128Dst, uint64_t const pu64Src));
1388	typedef FNIEMAIMPLMEDIAF1L1U128 *PFNIEMAIMPLMEDIAF1L1U128;
1389	FNIEMAIMPLMEDIAF1L1U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1390	FNIEMAIMPLMEDIAF1L1U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1391	/** @} */
1392
1393	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
1394	* @{ */
1395	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1396	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF1H1U64;
1397	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U128,(PCX86FXSTATE pFpuState, uint128_t pu128Dst, uint128_t const pu128Src));
1398	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF1H1U128;
1399	FNIEMAIMPLMEDIAF1H1U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
1400	FNIEMAIMPLMEDIAF1H1U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
1401	/** @} */
1402
1403	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
1404	* @{ */
1405	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUF,(PCX86FXSTATE pFpuState, uint128_t *pu128Dst,
1406	uint128_t const *pu128Src, uint8_t bEvil));
1407	typedef FNIEMAIMPLMEDIAPSHUF *PFNIEMAIMPLMEDIAPSHUF;
1408	FNIEMAIMPLMEDIAPSHUF iemAImpl_pshufhw, iemAImpl_pshuflw, iemAImpl_pshufd;
1409	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil));
1410	/** @} */
1411
1412	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
1413	* @{ */
1414	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1415	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint128_t const pu128Src));
1416	/** @} */
1417
1418
1419
1420	/** @name Function tables.
1421	* @{
1422	*/
1423
1424	/**
1425	* Function table for a binary operator providing implementation based on
1426	* operand size.
1427	*/
1428	typedef struct IEMOPBINSIZES
1429	{
1430	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
1431	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
1432	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
1433	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
1434	} IEMOPBINSIZES;
1435	/** Pointer to a binary operator function table. */
1436	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
1437
1438
1439	/**
1440	* Function table for a unary operator providing implementation based on
1441	* operand size.
1442	*/
1443	typedef struct IEMOPUNARYSIZES
1444	{
1445	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
1446	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
1447	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
1448	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
1449	} IEMOPUNARYSIZES;
1450	/** Pointer to a unary operator function table. */
1451	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
1452
1453
1454	/**
1455	* Function table for a shift operator providing implementation based on
1456	* operand size.
1457	*/
1458	typedef struct IEMOPSHIFTSIZES
1459	{
1460	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
1461	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
1462	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
1463	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
1464	} IEMOPSHIFTSIZES;
1465	/** Pointer to a shift operator function table. */
1466	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
1467
1468
1469	/**
1470	* Function table for a multiplication or division operation.
1471	*/
1472	typedef struct IEMOPMULDIVSIZES
1473	{
1474	PFNIEMAIMPLMULDIVU8 pfnU8;
1475	PFNIEMAIMPLMULDIVU16 pfnU16;
1476	PFNIEMAIMPLMULDIVU32 pfnU32;
1477	PFNIEMAIMPLMULDIVU64 pfnU64;
1478	} IEMOPMULDIVSIZES;
1479	/** Pointer to a multiplication or division operation function table. */
1480	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
1481
1482
1483	/**
1484	* Function table for a double precision shift operator providing implementation
1485	* based on operand size.
1486	*/
1487	typedef struct IEMOPSHIFTDBLSIZES
1488	{
1489	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
1490	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
1491	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
1492	} IEMOPSHIFTDBLSIZES;
1493	/** Pointer to a double precision shift function table. */
1494	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
1495
1496
1497	/**
1498	* Function table for media instruction taking two full sized media registers,
1499	* optionally the 2nd being a memory reference (only modifying the first op.)
1500	*/
1501	typedef struct IEMOPMEDIAF2
1502	{
1503	PFNIEMAIMPLMEDIAF2U64 pfnU64;
1504	PFNIEMAIMPLMEDIAF2U128 pfnU128;
1505	} IEMOPMEDIAF2;
1506	/** Pointer to a media operation function table for full sized ops. */
1507	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
1508
1509	/**
1510	* Function table for media instruction taking taking one full and one lower
1511	* half media register.
1512	*/
1513	typedef struct IEMOPMEDIAF1L1
1514	{
1515	PFNIEMAIMPLMEDIAF1L1U64 pfnU64;
1516	PFNIEMAIMPLMEDIAF1L1U128 pfnU128;
1517	} IEMOPMEDIAF1L1;
1518	/** Pointer to a media operation function table for lowhalf+lowhalf -> full. */
1519	typedef IEMOPMEDIAF1L1 const *PCIEMOPMEDIAF1L1;
1520
1521	/**
1522	* Function table for media instruction taking taking one full and one high half
1523	* media register.
1524	*/
1525	typedef struct IEMOPMEDIAF1H1
1526	{
1527	PFNIEMAIMPLMEDIAF1H1U64 pfnU64;
1528	PFNIEMAIMPLMEDIAF1H1U128 pfnU128;
1529	} IEMOPMEDIAF1H1;
1530	/** Pointer to a media operation function table for hihalf+hihalf -> full. */
1531	typedef IEMOPMEDIAF1H1 const *PCIEMOPMEDIAF1H1;
1532
1533
1534	/** @} */
1535
1536
1537	/** @name C instruction implementations for anything slightly complicated.
1538	* @{ */
1539
1540	/**
1541	* For typedef'ing or declaring a C instruction implementation function taking
1542	* no extra arguments.
1543	*
1544	* @param a_Name The name of the type.
1545	*/
1546	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
1547	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1548	/**
1549	* For defining a C instruction implementation function taking no extra
1550	* arguments.
1551	*
1552	* @param a_Name The name of the function
1553	*/
1554	# define IEM_CIMPL_DEF_0(a_Name) \
1555	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1556	/**
1557	* For calling a C instruction implementation function taking no extra
1558	* arguments.
1559	*
1560	* This special call macro adds default arguments to the call and allow us to
1561	* change these later.
1562	*
1563	* @param a_fn The name of the function.
1564	*/
1565	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
1566
1567	/**
1568	* For typedef'ing or declaring a C instruction implementation function taking
1569	* one extra argument.
1570	*
1571	* @param a_Name The name of the type.
1572	* @param a_Type0 The argument type.
1573	* @param a_Arg0 The argument name.
1574	*/
1575	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
1576	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1577	/**
1578	* For defining a C instruction implementation function taking one extra
1579	* argument.
1580	*
1581	* @param a_Name The name of the function
1582	* @param a_Type0 The argument type.
1583	* @param a_Arg0 The argument name.
1584	*/
1585	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
1586	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1587	/**
1588	* For calling a C instruction implementation function taking one extra
1589	* argument.
1590	*
1591	* This special call macro adds default arguments to the call and allow us to
1592	* change these later.
1593	*
1594	* @param a_fn The name of the function.
1595	* @param a0 The name of the 1st argument.
1596	*/
1597	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
1598
1599	/**
1600	* For typedef'ing or declaring a C instruction implementation function taking
1601	* two extra arguments.
1602	*
1603	* @param a_Name The name of the type.
1604	* @param a_Type0 The type of the 1st argument
1605	* @param a_Arg0 The name of the 1st argument.
1606	* @param a_Type1 The type of the 2nd argument.
1607	* @param a_Arg1 The name of the 2nd argument.
1608	*/
1609	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1610	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1611	/**
1612	* For defining a C instruction implementation function taking two extra
1613	* arguments.
1614	*
1615	* @param a_Name The name of the function.
1616	* @param a_Type0 The type of the 1st argument
1617	* @param a_Arg0 The name of the 1st argument.
1618	* @param a_Type1 The type of the 2nd argument.
1619	* @param a_Arg1 The name of the 2nd argument.
1620	*/
1621	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1622	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1623	/**
1624	* For calling a C instruction implementation function taking two extra
1625	* arguments.
1626	*
1627	* This special call macro adds default arguments to the call and allow us to
1628	* change these later.
1629	*
1630	* @param a_fn The name of the function.
1631	* @param a0 The name of the 1st argument.
1632	* @param a1 The name of the 2nd argument.
1633	*/
1634	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
1635
1636	/**
1637	* For typedef'ing or declaring a C instruction implementation function taking
1638	* three extra arguments.
1639	*
1640	* @param a_Name The name of the type.
1641	* @param a_Type0 The type of the 1st argument
1642	* @param a_Arg0 The name of the 1st argument.
1643	* @param a_Type1 The type of the 2nd argument.
1644	* @param a_Arg1 The name of the 2nd argument.
1645	* @param a_Type2 The type of the 3rd argument.
1646	* @param a_Arg2 The name of the 3rd argument.
1647	*/
1648	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1649	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1650	/**
1651	* For defining a C instruction implementation function taking three extra
1652	* arguments.
1653	*
1654	* @param a_Name The name of the function.
1655	* @param a_Type0 The type of the 1st argument
1656	* @param a_Arg0 The name of the 1st argument.
1657	* @param a_Type1 The type of the 2nd argument.
1658	* @param a_Arg1 The name of the 2nd argument.
1659	* @param a_Type2 The type of the 3rd argument.
1660	* @param a_Arg2 The name of the 3rd argument.
1661	*/
1662	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1663	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1664	/**
1665	* For calling a C instruction implementation function taking three extra
1666	* arguments.
1667	*
1668	* This special call macro adds default arguments to the call and allow us to
1669	* change these later.
1670	*
1671	* @param a_fn The name of the function.
1672	* @param a0 The name of the 1st argument.
1673	* @param a1 The name of the 2nd argument.
1674	* @param a2 The name of the 3rd argument.
1675	*/
1676	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
1677
1678
1679	/**
1680	* For typedef'ing or declaring a C instruction implementation function taking
1681	* four extra arguments.
1682	*
1683	* @param a_Name The name of the type.
1684	* @param a_Type0 The type of the 1st argument
1685	* @param a_Arg0 The name of the 1st argument.
1686	* @param a_Type1 The type of the 2nd argument.
1687	* @param a_Arg1 The name of the 2nd argument.
1688	* @param a_Type2 The type of the 3rd argument.
1689	* @param a_Arg2 The name of the 3rd argument.
1690	* @param a_Type3 The type of the 4th argument.
1691	* @param a_Arg3 The name of the 4th argument.
1692	*/
1693	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1694	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
1695	/**
1696	* For defining a C instruction implementation function taking four extra
1697	* arguments.
1698	*
1699	* @param a_Name The name of the function.
1700	* @param a_Type0 The type of the 1st argument
1701	* @param a_Arg0 The name of the 1st argument.
1702	* @param a_Type1 The type of the 2nd argument.
1703	* @param a_Arg1 The name of the 2nd argument.
1704	* @param a_Type2 The type of the 3rd argument.
1705	* @param a_Arg2 The name of the 3rd argument.
1706	* @param a_Type3 The type of the 4th argument.
1707	* @param a_Arg3 The name of the 4th argument.
1708	*/
1709	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1710	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1711	a_Type2 a_Arg2, a_Type3 a_Arg3))
1712	/**
1713	* For calling a C instruction implementation function taking four extra
1714	* arguments.
1715	*
1716	* This special call macro adds default arguments to the call and allow us to
1717	* change these later.
1718	*
1719	* @param a_fn The name of the function.
1720	* @param a0 The name of the 1st argument.
1721	* @param a1 The name of the 2nd argument.
1722	* @param a2 The name of the 3rd argument.
1723	* @param a3 The name of the 4th argument.
1724	*/
1725	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
1726
1727
1728	/**
1729	* For typedef'ing or declaring a C instruction implementation function taking
1730	* five extra arguments.
1731	*
1732	* @param a_Name The name of the type.
1733	* @param a_Type0 The type of the 1st argument
1734	* @param a_Arg0 The name of the 1st argument.
1735	* @param a_Type1 The type of the 2nd argument.
1736	* @param a_Arg1 The name of the 2nd argument.
1737	* @param a_Type2 The type of the 3rd argument.
1738	* @param a_Arg2 The name of the 3rd argument.
1739	* @param a_Type3 The type of the 4th argument.
1740	* @param a_Arg3 The name of the 4th argument.
1741	* @param a_Type4 The type of the 5th argument.
1742	* @param a_Arg4 The name of the 5th argument.
1743	*/
1744	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1745	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1746	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1747	a_Type3 a_Arg3, a_Type4 a_Arg4))
1748	/**
1749	* For defining a C instruction implementation function taking five extra
1750	* arguments.
1751	*
1752	* @param a_Name The name of the function.
1753	* @param a_Type0 The type of the 1st argument
1754	* @param a_Arg0 The name of the 1st argument.
1755	* @param a_Type1 The type of the 2nd argument.
1756	* @param a_Arg1 The name of the 2nd argument.
1757	* @param a_Type2 The type of the 3rd argument.
1758	* @param a_Arg2 The name of the 3rd argument.
1759	* @param a_Type3 The type of the 4th argument.
1760	* @param a_Arg3 The name of the 4th argument.
1761	* @param a_Type4 The type of the 5th argument.
1762	* @param a_Arg4 The name of the 5th argument.
1763	*/
1764	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1765	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1766	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1767	a_Type3 a_Arg3, a_Type4 a_Arg4))
1768	/**
1769	* For calling a C instruction implementation function taking five extra
1770	* arguments.
1771	*
1772	* This special call macro adds default arguments to the call and allow us to
1773	* change these later.
1774	*
1775	* @param a_fn The name of the function.
1776	* @param a0 The name of the 1st argument.
1777	* @param a1 The name of the 2nd argument.
1778	* @param a2 The name of the 3rd argument.
1779	* @param a3 The name of the 4th argument.
1780	* @param a4 The name of the 5th argument.
1781	*/
1782	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
1783
1784	/** @} */
1785
1786
1787	/** @} */
1788
1789	RT_C_DECLS_END
1790
1791	#endif
1792

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 62145

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