IEMInternal.h@ 66345

Last change on this file since 66345 was 66321, checked in by vboxsync, 8 years ago
IEM: Implemented movddup Vdq,Wdq (f2 0f 12).
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1	/* $Id: IEMInternal.h 66321 2017-03-29 07:30:33Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___IEMInternal_h
19	#define ___IEMInternal_h
20
21	#include <VBox/vmm/cpum.h>
22	#include <VBox/vmm/iem.h>
23	#include <VBox/vmm/stam.h>
24	#include <VBox/param.h>
25
26	#include <setjmp.h>
27
28
29	RT_C_DECLS_BEGIN
30
31
32	/** @defgroup grp_iem_int Internals
33	* @ingroup grp_iem
34	* @internal
35	* @{
36	*/
37
38	/** For expanding symbol in slickedit and other products tagging and
39	* crossreferencing IEM symbols. */
40	#ifndef IEM_STATIC
41	# define IEM_STATIC static
42	#endif
43
44	/** @def IEM_VERIFICATION_MODE_FULL
45	* Shorthand for:
46	* defined(IEM_VERIFICATION_MODE) && !defined(IEM_VERIFICATION_MODE_MINIMAL)
47	*/
48	#if (defined(IEM_VERIFICATION_MODE) && !defined(IEM_VERIFICATION_MODE_MINIMAL) && !defined(IEM_VERIFICATION_MODE_FULL)) \
49	\|\| defined(DOXYGEN_RUNNING)
50	# define IEM_VERIFICATION_MODE_FULL
51	#endif
52
53
54	/** @def IEM_CFG_TARGET_CPU
55	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
56	*
57	* By default we allow this to be configured by the user via the
58	* CPUM/GuestCpuName config string, but this comes at a slight cost during
59	* decoding. So, for applications of this code where there is no need to
60	* be dynamic wrt target CPU, just modify this define.
61	*/
62	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
63	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
64	#endif
65
66
67	//#define IEM_WITH_CODE_TLB// - work in progress
68
69
70	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
71	/** Instruction statistics. */
72	typedef struct IEMINSTRSTATS
73	{
74	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
75	# include "IEMInstructionStatisticsTmpl.h"
76	# undef IEM_DO_INSTR_STAT
77	} IEMINSTRSTATS;
78	#else
79	struct IEMINSTRSTATS;
80	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
81	#endif
82	/** Pointer to IEM instruction statistics. */
83	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
84
85	/** Finish and move to types.h */
86	typedef union
87	{
88	uint32_t u32;
89	} RTFLOAT32U;
90	typedef RTFLOAT32U *PRTFLOAT32U;
91	typedef RTFLOAT32U const *PCRTFLOAT32U;
92
93
94	/**
95	* Extended operand mode that includes a representation of 8-bit.
96	*
97	* This is used for packing down modes when invoking some C instruction
98	* implementations.
99	*/
100	typedef enum IEMMODEX
101	{
102	IEMMODEX_16BIT = IEMMODE_16BIT,
103	IEMMODEX_32BIT = IEMMODE_32BIT,
104	IEMMODEX_64BIT = IEMMODE_64BIT,
105	IEMMODEX_8BIT
106	} IEMMODEX;
107	AssertCompileSize(IEMMODEX, 4);
108
109
110	/**
111	* Branch types.
112	*/
113	typedef enum IEMBRANCH
114	{
115	IEMBRANCH_JUMP = 1,
116	IEMBRANCH_CALL,
117	IEMBRANCH_TRAP,
118	IEMBRANCH_SOFTWARE_INT,
119	IEMBRANCH_HARDWARE_INT
120	} IEMBRANCH;
121	AssertCompileSize(IEMBRANCH, 4);
122
123
124	/**
125	* A FPU result.
126	*/
127	typedef struct IEMFPURESULT
128	{
129	/** The output value. */
130	RTFLOAT80U r80Result;
131	/** The output status. */
132	uint16_t FSW;
133	} IEMFPURESULT;
134	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
135	/** Pointer to a FPU result. */
136	typedef IEMFPURESULT *PIEMFPURESULT;
137	/** Pointer to a const FPU result. */
138	typedef IEMFPURESULT const *PCIEMFPURESULT;
139
140
141	/**
142	* A FPU result consisting of two output values and FSW.
143	*/
144	typedef struct IEMFPURESULTTWO
145	{
146	/** The first output value. */
147	RTFLOAT80U r80Result1;
148	/** The output status. */
149	uint16_t FSW;
150	/** The second output value. */
151	RTFLOAT80U r80Result2;
152	} IEMFPURESULTTWO;
153	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
154	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
155	/** Pointer to a FPU result consisting of two output values and FSW. */
156	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
157	/** Pointer to a const FPU result consisting of two output values and FSW. */
158	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
159
160
161
162	#ifdef IEM_VERIFICATION_MODE_FULL
163
164	/**
165	* Verification event type.
166	*/
167	typedef enum IEMVERIFYEVENT
168	{
169	IEMVERIFYEVENT_INVALID = 0,
170	IEMVERIFYEVENT_IOPORT_READ,
171	IEMVERIFYEVENT_IOPORT_WRITE,
172	IEMVERIFYEVENT_IOPORT_STR_READ,
173	IEMVERIFYEVENT_IOPORT_STR_WRITE,
174	IEMVERIFYEVENT_RAM_WRITE,
175	IEMVERIFYEVENT_RAM_READ
176	} IEMVERIFYEVENT;
177
178	/** Checks if the event type is a RAM read or write. */
179	# define IEMVERIFYEVENT_IS_RAM(a_enmType) ((a_enmType) == IEMVERIFYEVENT_RAM_WRITE \|\| (a_enmType) == IEMVERIFYEVENT_RAM_READ)
180
181	/**
182	* Verification event record.
183	*/
184	typedef struct IEMVERIFYEVTREC
185	{
186	/** Pointer to the next record in the list. */
187	struct IEMVERIFYEVTREC *pNext;
188	/** The event type. */
189	IEMVERIFYEVENT enmEvent;
190	/** The event data. */
191	union
192	{
193	/** IEMVERIFYEVENT_IOPORT_READ */
194	struct
195	{
196	RTIOPORT Port;
197	uint8_t cbValue;
198	} IOPortRead;
199
200	/** IEMVERIFYEVENT_IOPORT_WRITE */
201	struct
202	{
203	RTIOPORT Port;
204	uint8_t cbValue;
205	uint32_t u32Value;
206	} IOPortWrite;
207
208	/** IEMVERIFYEVENT_IOPORT_STR_READ */
209	struct
210	{
211	RTIOPORT Port;
212	uint8_t cbValue;
213	RTGCUINTREG cTransfers;
214	} IOPortStrRead;
215
216	/** IEMVERIFYEVENT_IOPORT_STR_WRITE */
217	struct
218	{
219	RTIOPORT Port;
220	uint8_t cbValue;
221	RTGCUINTREG cTransfers;
222	} IOPortStrWrite;
223
224	/** IEMVERIFYEVENT_RAM_READ */
225	struct
226	{
227	RTGCPHYS GCPhys;
228	uint32_t cb;
229	} RamRead;
230
231	/** IEMVERIFYEVENT_RAM_WRITE */
232	struct
233	{
234	RTGCPHYS GCPhys;
235	uint32_t cb;
236	uint8_t ab[512];
237	} RamWrite;
238	} u;
239	} IEMVERIFYEVTREC;
240	/** Pointer to an IEM event verification records. */
241	typedef IEMVERIFYEVTREC *PIEMVERIFYEVTREC;
242
243	#endif /* IEM_VERIFICATION_MODE_FULL */
244
245
246	/**
247	* IEM TLB entry.
248	*
249	* Lookup assembly:
250	* @code{.asm}
251	; Calculate tag.
252	mov rax, [VA]
253	shl rax, 16
254	shr rax, 16 + X86_PAGE_SHIFT
255	or rax, [uTlbRevision]
256
257	; Do indexing.
258	movzx ecx, al
259	lea rcx, [pTlbEntries + rcx]
260
261	; Check tag.
262	cmp [rcx + IEMTLBENTRY.uTag], rax
263	jne .TlbMiss
264
265	; Check access.
266	movsx rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
267	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
268	cmp rax, [uTlbPhysRev]
269	jne .TlbMiss
270
271	; Calc address and we're done.
272	mov eax, X86_PAGE_OFFSET_MASK
273	and eax, [VA]
274	or rax, [rcx + IEMTLBENTRY.pMappingR3]
275	%ifdef VBOX_WITH_STATISTICS
276	inc qword [cTlbHits]
277	%endif
278	jmp .Done
279
280	.TlbMiss:
281	mov r8d, ACCESS_FLAGS
282	mov rdx, [VA]
283	mov rcx, [pVCpu]
284	call iemTlbTypeMiss
285	.Done:
286
287	@endcode
288	*
289	*/
290	typedef struct IEMTLBENTRY
291	{
292	/** The TLB entry tag.
293	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits.
294	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
295	*
296	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
297	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
298	* revision wraps around though, the tags needs to be zeroed.
299	*
300	* @note Try use SHRD instruction? After seeing
301	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
302	*/
303	uint64_t uTag;
304	/** Access flags and physical TLB revision.
305	*
306	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
307	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
308	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
309	* - Bit 3 - pgm phys/virt - not directly writable.
310	* - Bit 4 - pgm phys page - not directly readable.
311	* - Bit 5 - currently unused.
312	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
313	* - Bit 7 - tlb entry - pMappingR3 member not valid.
314	* - Bits 63 thru 8 are used for the physical TLB revision number.
315	*
316	* We're using complemented bit meanings here because it makes it easy to check
317	* whether special action is required. For instance a user mode write access
318	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
319	* non-zero result would mean special handling needed because either it wasn't
320	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
321	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
322	* need to check any PTE flag.
323	*/
324	uint64_t fFlagsAndPhysRev;
325	/** The guest physical page address. */
326	uint64_t GCPhys;
327	/** Pointer to the ring-3 mapping (possibly also valid in ring-0). */
328	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
329	R3PTRTYPE(uint8_t *) pbMappingR3;
330	#else
331	R3R0PTRTYPE(uint8_t *) pbMappingR3;
332	#endif
333	#if HC_ARCH_BITS == 32
334	uint32_t u32Padding1;
335	#endif
336	} IEMTLBENTRY;
337	AssertCompileSize(IEMTLBENTRY, 32);
338	/** Pointer to an IEM TLB entry. */
339	typedef IEMTLBENTRY *PIEMTLBENTRY;
340
341	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
342	* @{ */
343	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
344	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
345	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
346	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
347	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
348	#define IEMTLBE_F_PATCH_CODE RT_BIT_64(5) /*< Code TLB: Patch code (PATM). /
349	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
350	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
351	#define IEMTLBE_F_PHYS_REV UINT64_C(0xffffffffffffff00) /*< Physical revision mask. /
352	/** @} */
353
354
355	/**
356	* An IEM TLB.
357	*
358	* We've got two of these, one for data and one for instructions.
359	*/
360	typedef struct IEMTLB
361	{
362	/** The TLB entries.
363	* We've choosen 256 because that way we can obtain the result directly from a
364	* 8-bit register without an additional AND instruction. */
365	IEMTLBENTRY aEntries[256];
366	/** The TLB revision.
367	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
368	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
369	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
370	* (The revision zero indicates an invalid TLB entry.)
371	*
372	* The initial value is choosen to cause an early wraparound. */
373	uint64_t uTlbRevision;
374	/** The TLB physical address revision - shadow of PGM variable.
375	*
376	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
377	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
378	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
379	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
380	*
381	* The initial value is choosen to cause an early wraparound. */
382	uint64_t volatile uTlbPhysRev;
383
384	/* Statistics: */
385
386	/** TLB hits (VBOX_WITH_STATISTICS only). */
387	uint64_t cTlbHits;
388	/** TLB misses. */
389	uint32_t cTlbMisses;
390	/** Slow read path. */
391	uint32_t cTlbSlowReadPath;
392	#if 0
393	/** TLB misses because of tag mismatch. */
394	uint32_t cTlbMissesTag;
395	/** TLB misses because of virtual access violation. */
396	uint32_t cTlbMissesVirtAccess;
397	/** TLB misses because of dirty bit. */
398	uint32_t cTlbMissesDirty;
399	/** TLB misses because of MMIO */
400	uint32_t cTlbMissesMmio;
401	/** TLB misses because of write access handlers. */
402	uint32_t cTlbMissesWriteHandler;
403	/** TLB misses because no r3(/r0) mapping. */
404	uint32_t cTlbMissesMapping;
405	#endif
406	/** Alignment padding. */
407	uint32_t au32Padding[3+5];
408	} IEMTLB;
409	AssertCompileSizeAlignment(IEMTLB, 64);
410	/** IEMTLB::uTlbRevision increment. */
411	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
412	/** IEMTLB::uTlbPhysRev increment. */
413	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(8)
414
415
416	/**
417	* The per-CPU IEM state.
418	*/
419	typedef struct IEMCPU
420	{
421	/** Info status code that needs to be propagated to the IEM caller.
422	* This cannot be passed internally, as it would complicate all success
423	* checks within the interpreter making the code larger and almost impossible
424	* to get right. Instead, we'll store status codes to pass on here. Each
425	* source of these codes will perform appropriate sanity checks. */
426	int32_t rcPassUp; /* 0x00 */
427
428	/** The current CPU execution mode (CS). */
429	IEMMODE enmCpuMode; /* 0x04 */
430	/** The CPL. */
431	uint8_t uCpl; /* 0x05 */
432
433	/** Whether to bypass access handlers or not. */
434	bool fBypassHandlers; /* 0x06 */
435	/** Indicates that we're interpreting patch code - RC only! */
436	bool fInPatchCode; /* 0x07 */
437
438	/** @name Decoder state.
439	* @{ */
440	#ifdef IEM_WITH_CODE_TLB
441	/** The offset of the next instruction byte. */
442	uint32_t offInstrNextByte; /* 0x08 */
443	/** The number of bytes available at pbInstrBuf for the current instruction.
444	* This takes the max opcode length into account so that doesn't need to be
445	* checked separately. */
446	uint32_t cbInstrBuf; /* 0x0c */
447	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
448	* This can be NULL if the page isn't mappable for some reason, in which
449	* case we'll do fallback stuff.
450	*
451	* If we're executing an instruction from a user specified buffer,
452	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
453	* aligned pointer but pointer to the user data.
454	*
455	* For instructions crossing pages, this will start on the first page and be
456	* advanced to the next page by the time we've decoded the instruction. This
457	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
458	*/
459	uint8_t const pbInstrBuf; / 0x10 */
460	# if ARCH_BITS == 32
461	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
462	# endif
463	/** The program counter corresponding to pbInstrBuf.
464	* This is set to a non-canonical address when we need to invalidate it. */
465	uint64_t uInstrBufPc; /* 0x18 */
466	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
467	* This takes the CS segment limit into account. */
468	uint16_t cbInstrBufTotal; /* 0x20 */
469	/** Offset into pbInstrBuf of the first byte of the current instruction.
470	* Can be negative to efficiently handle cross page instructions. */
471	int16_t offCurInstrStart; /* 0x22 */
472
473	/** The prefix mask (IEM_OP_PRF_XXX). */
474	uint32_t fPrefixes; /* 0x24 */
475	/** The extra REX ModR/M register field bit (REX.R << 3). */
476	uint8_t uRexReg; /* 0x28 */
477	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
478	* (REX.B << 3). */
479	uint8_t uRexB; /* 0x29 */
480	/** The extra REX SIB index field bit (REX.X << 3). */
481	uint8_t uRexIndex; /* 0x2a */
482
483	/** The effective segment register (X86_SREG_XXX). */
484	uint8_t iEffSeg; /* 0x2b */
485
486	#else
487	/** The size of what has currently been fetched into abOpcodes. */
488	uint8_t cbOpcode; /* 0x08 */
489	/** The current offset into abOpcodes. */
490	uint8_t offOpcode; /* 0x09 */
491
492	/** The effective segment register (X86_SREG_XXX). */
493	uint8_t iEffSeg; /* 0x0a */
494
495	/** The extra REX ModR/M register field bit (REX.R << 3). */
496	uint8_t uRexReg; /* 0x0b */
497	/** The prefix mask (IEM_OP_PRF_XXX). */
498	uint32_t fPrefixes; /* 0x0c */
499	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
500	* (REX.B << 3). */
501	uint8_t uRexB; /* 0x10 */
502	/** The extra REX SIB index field bit (REX.X << 3). */
503	uint8_t uRexIndex; /* 0x11 */
504
505	#endif
506
507	/** The effective operand mode. */
508	IEMMODE enmEffOpSize; /* 0x2c, 0x12 */
509	/** The default addressing mode. */
510	IEMMODE enmDefAddrMode; /* 0x2d, 0x13 */
511	/** The effective addressing mode. */
512	IEMMODE enmEffAddrMode; /* 0x2e, 0x14 */
513	/** The default operand mode. */
514	IEMMODE enmDefOpSize; /* 0x2f, 0x15 */
515
516	/** Prefix index (VEX.pp) for two byte and three byte tables. */
517	uint8_t idxPrefix; /* 0x30, 0x16 */
518	/** 3rd VEX/EVEX/XOP register. */
519	uint8_t uVex3rdReg; /* 0x31, 0x17 */
520	/** The VEX/EVEX/XOP length field. */
521	uint8_t uVexLength; /* 0x32, 0x18 */
522	/** Additional EVEX stuff. */
523	uint8_t fEvexStuff; /* 0x33, 0x19 */
524
525	/** The FPU opcode (FOP). */
526	uint16_t uFpuOpcode; /* 0x34, 0x1a */
527
528	/** Explicit alignment padding. */
529	#ifdef IEM_WITH_CODE_TLB
530	uint8_t abAlignment2a[2]; /* 0x36 */
531	#endif
532
533	/** The opcode bytes. */
534	uint8_t abOpcode[15]; /* 0x48, 0x1c */
535	/** Explicit alignment padding. */
536	#ifdef IEM_WITH_CODE_TLB
537	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
538	#else
539	uint8_t abAlignment2c[0x48 - 0x2b]; /* 0x2b */
540	#endif
541	/** @} */
542
543
544	/** The flags of the current exception / interrupt. */
545	uint32_t fCurXcpt; /* 0x48, 0x48 */
546	/** The current exception / interrupt. */
547	uint8_t uCurXcpt;
548	/** Exception / interrupt recursion depth. */
549	int8_t cXcptRecursions;
550
551	/** The number of active guest memory mappings. */
552	uint8_t cActiveMappings;
553	/** The next unused mapping index. */
554	uint8_t iNextMapping;
555	/** Records for tracking guest memory mappings. */
556	struct
557	{
558	/** The address of the mapped bytes. */
559	void *pv;
560	#if defined(IN_RC) && HC_ARCH_BITS == 64
561	uint32_t u32Alignment3; /*< Alignment padding. /
562	#endif
563	/** The access flags (IEM_ACCESS_XXX).
564	* IEM_ACCESS_INVALID if the entry is unused. */
565	uint32_t fAccess;
566	#if HC_ARCH_BITS == 64
567	uint32_t u32Alignment4; /*< Alignment padding. /
568	#endif
569	} aMemMappings[3];
570
571	/** Locking records for the mapped memory. */
572	union
573	{
574	PGMPAGEMAPLOCK Lock;
575	uint64_t au64Padding[2];
576	} aMemMappingLocks[3];
577
578	/** Bounce buffer info.
579	* This runs in parallel to aMemMappings. */
580	struct
581	{
582	/** The physical address of the first byte. */
583	RTGCPHYS GCPhysFirst;
584	/** The physical address of the second page. */
585	RTGCPHYS GCPhysSecond;
586	/** The number of bytes in the first page. */
587	uint16_t cbFirst;
588	/** The number of bytes in the second page. */
589	uint16_t cbSecond;
590	/** Whether it's unassigned memory. */
591	bool fUnassigned;
592	/** Explicit alignment padding. */
593	bool afAlignment5[3];
594	} aMemBbMappings[3];
595
596	/** Bounce buffer storage.
597	* This runs in parallel to aMemMappings and aMemBbMappings. */
598	struct
599	{
600	uint8_t ab[512];
601	} aBounceBuffers[3];
602
603
604	/** Pointer set jump buffer - ring-3 context. */
605	R3PTRTYPE(jmp_buf *) pJmpBufR3;
606	/** Pointer set jump buffer - ring-0 context. */
607	R0PTRTYPE(jmp_buf *) pJmpBufR0;
608	/** Pointer set jump buffer - raw-mode context. */
609	RCPTRTYPE(jmp_buf *) pJmpBufRC;
610
611	/** @name Statistics
612	* @{ */
613	/** The number of instructions we've executed. */
614	uint32_t cInstructions;
615	/** The number of potential exits. */
616	uint32_t cPotentialExits;
617	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
618	* This may contain uncommitted writes. */
619	uint32_t cbWritten;
620	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
621	uint32_t cRetInstrNotImplemented;
622	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
623	uint32_t cRetAspectNotImplemented;
624	/** Counts informational statuses returned (other than VINF_SUCCESS). */
625	uint32_t cRetInfStatuses;
626	/** Counts other error statuses returned. */
627	uint32_t cRetErrStatuses;
628	/** Number of times rcPassUp has been used. */
629	uint32_t cRetPassUpStatus;
630	/** Number of times RZ left with instruction commit pending for ring-3. */
631	uint32_t cPendingCommit;
632	/** Number of long jumps. */
633	uint32_t cLongJumps;
634	uint32_t uAlignment6; /*< Alignment padding. /
635	#ifdef IEM_VERIFICATION_MODE_FULL
636	/** The Number of I/O port reads that has been performed. */
637	uint32_t cIOReads;
638	/** The Number of I/O port writes that has been performed. */
639	uint32_t cIOWrites;
640	/** Set if no comparison to REM is currently performed.
641	* This is used to skip past really slow bits. */
642	bool fNoRem;
643	/** Saved fNoRem flag used by #iemInitExec and #iemUninitExec. */
644	bool fNoRemSavedByExec;
645	/** Indicates that RAX and RDX differences should be ignored since RDTSC
646	* and RDTSCP are timing sensitive. */
647	bool fIgnoreRaxRdx;
648	/** Indicates that a MOVS instruction with overlapping source and destination
649	* was executed, causing the memory write records to be incorrrect. */
650	bool fOverlappingMovs;
651	/** Set if there are problematic memory accesses (MMIO, write monitored, ++). */
652	bool fProblematicMemory;
653	/** This is used to communicate a CPL changed caused by IEMInjectTrap that
654	* CPUM doesn't yet reflect. */
655	uint8_t uInjectCpl;
656	/** To prevent EMR3HmSingleInstruction from triggering endless recursion via
657	* emR3ExecuteInstruction and iemExecVerificationModeCheck. */
658	uint8_t cVerifyDepth;
659	bool afAlignment7[2];
660	/** Mask of undefined eflags.
661	* The verifier will any difference in these flags. */
662	uint32_t fUndefinedEFlags;
663	/** The CS of the instruction being interpreted. */
664	RTSEL uOldCs;
665	/** The RIP of the instruction being interpreted. */
666	uint64_t uOldRip;
667	/** The physical address corresponding to abOpcodes[0]. */
668	RTGCPHYS GCPhysOpcodes;
669	#endif
670	/** @} */
671
672	/** @name Target CPU information.
673	* @{ */
674	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
675	/** The target CPU. */
676	uint32_t uTargetCpu;
677	#else
678	uint32_t u32TargetCpuPadding;
679	#endif
680	/** The CPU vendor. */
681	CPUMCPUVENDOR enmCpuVendor;
682	/** @} */
683
684	/** @name Host CPU information.
685	* @{ */
686	/** The CPU vendor. */
687	CPUMCPUVENDOR enmHostCpuVendor;
688	/** @} */
689
690	uint32_t au32Alignment8[HC_ARCH_BITS == 64 ? 1 + 2 + 4 + 8 : 1 + 2 + 4]; /*< Alignment padding. /
691
692	/** Data TLB.
693	* @remarks Must be 64-byte aligned. */
694	IEMTLB DataTlb;
695	/** Instruction TLB.
696	* @remarks Must be 64-byte aligned. */
697	IEMTLB CodeTlb;
698
699	/** Pointer to the CPU context - ring-3 context.
700	* @todo put inside IEM_VERIFICATION_MODE_FULL++. */
701	R3PTRTYPE(PCPUMCTX) pCtxR3;
702	/** Pointer to the CPU context - ring-0 context. */
703	R0PTRTYPE(PCPUMCTX) pCtxR0;
704	/** Pointer to the CPU context - raw-mode context. */
705	RCPTRTYPE(PCPUMCTX) pCtxRC;
706
707	/** Pointer to instruction statistics for raw-mode context (same as R0). */
708	RCPTRTYPE(PIEMINSTRSTATS) pStatsRC;
709	/** Pointer to instruction statistics for ring-0 context (same as RC). */
710	R0PTRTYPE(PIEMINSTRSTATS) pStatsR0;
711	/** Pointer to instruction statistics for non-ring-3 code. */
712	R3PTRTYPE(PIEMINSTRSTATS) pStatsCCR3;
713	/** Pointer to instruction statistics for ring-3 context. */
714	R3PTRTYPE(PIEMINSTRSTATS) pStatsR3;
715
716	#ifdef IEM_VERIFICATION_MODE_FULL
717	/** The event verification records for what IEM did (LIFO). */
718	R3PTRTYPE(PIEMVERIFYEVTREC) pIemEvtRecHead;
719	/** Insertion point for pIemEvtRecHead. */
720	R3PTRTYPE(PIEMVERIFYEVTREC *) ppIemEvtRecNext;
721	/** The event verification records for what the other party did (FIFO). */
722	R3PTRTYPE(PIEMVERIFYEVTREC) pOtherEvtRecHead;
723	/** Insertion point for pOtherEvtRecHead. */
724	R3PTRTYPE(PIEMVERIFYEVTREC *) ppOtherEvtRecNext;
725	/** List of free event records. */
726	R3PTRTYPE(PIEMVERIFYEVTREC) pFreeEvtRec;
727	#endif
728	} IEMCPU;
729	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
730	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
731	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
732	/** Pointer to the per-CPU IEM state. */
733	typedef IEMCPU *PIEMCPU;
734	/** Pointer to the const per-CPU IEM state. */
735	typedef IEMCPU const *PCIEMCPU;
736
737
738	/** @def IEM_GET_CTX
739	* Gets the guest CPU context for the calling EMT.
740	* @returns PCPUMCTX
741	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
742	*/
743	#if !defined(IEM_VERIFICATION_MODE_FULL) && !defined(IEM_VERIFICATION_MODE) \
744	&& !defined(IEM_VERIFICATION_MODE_MINIMAL) && defined(VMCPU_INCL_CPUM_GST_CTX)
745	# define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
746	#else
747	# define IEM_GET_CTX(a_pVCpu) ((a_pVCpu)->iem.s.CTX_SUFF(pCtx))
748	#endif
749
750	/** Gets the current IEMTARGETCPU value.
751	* @returns IEMTARGETCPU value.
752	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
753	*/
754	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
755	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
756	#else
757	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
758	#endif
759
760	/** @def Gets the instruction length. */
761	#ifdef IEM_WITH_CODE_TLB
762	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
763	#else
764	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
765	#endif
766
767
768	/** @name IEM_ACCESS_XXX - Access details.
769	* @{ */
770	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
771	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
772	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
773	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
774	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
775	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
776	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
777	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
778	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
779	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
780	/** The writes are partial, so if initialize the bounce buffer with the
781	* orignal RAM content. */
782	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
783	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
784	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
785	/** Bounce buffer with ring-3 write pending, first page. */
786	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
787	/** Bounce buffer with ring-3 write pending, second page. */
788	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
789	/** Valid bit mask. */
790	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00000fff)
791	/** Read+write data alias. */
792	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
793	/** Write data alias. */
794	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
795	/** Read data alias. */
796	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
797	/** Instruction fetch alias. */
798	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
799	/** Stack write alias. */
800	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
801	/** Stack read alias. */
802	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
803	/** Stack read+write alias. */
804	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
805	/** Read system table alias. */
806	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
807	/** Read+write system table alias. */
808	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
809	/** @} */
810
811	/** @name Prefix constants (IEMCPU::fPrefixes)
812	* @{ */
813	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
814	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
815	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
816	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
817	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
818	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
819	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
820
821	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
822	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
823	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
824
825	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
826	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
827	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
828
829	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
830	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
831	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
832	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
833	/** Mask with all the REX prefix flags.
834	* This is generally for use when needing to undo the REX prefixes when they
835	* are followed legacy prefixes and therefore does not immediately preceed
836	* the first opcode byte.
837	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
838	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
839
840	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
841	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
842	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
843	/** @} */
844
845	/** @name IEMOPFORM_XXX - Opcode forms
846	* @note These are ORed together with IEMOPHINT_XXX.
847	* @{ */
848	/** ModR/M: reg, r/m */
849	#define IEMOPFORM_RM 0
850	/** ModR/M: reg, r/m (register) */
851	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
852	/** ModR/M: reg, r/m (memory) */
853	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
854	/** ModR/M: r/m, reg */
855	#define IEMOPFORM_MR 1
856	/** ModR/M: r/m (register), reg */
857	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
858	/** ModR/M: r/m (memory), reg */
859	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
860	/** ModR/M: r/m only */
861	#define IEMOPFORM_M 2
862	/** ModR/M: r/m only (register). */
863	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
864	/** ModR/M: r/m only (memory). */
865	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
866	/** ModR/M: reg only */
867	#define IEMOPFORM_R 3
868
869	/** ModR/M + VEX.vvvv: reg, vvvv, r/m */
870	#define IEMOPFORM_RVM 4
871
872	/** ModR/M + VEX.vvvv: r/m, vvvv, reg */
873	#define IEMOPFORM_MVR 5
874
875	/** Fixed register instruction, no R/M. */
876	#define IEMOPFORM_FIXED 6
877
878	/** The r/m is a register. */
879	#define IEMOPFORM_MOD3 RT_BIT_32(8)
880	/** The r/m is a memory access. */
881	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
882	/** @} */
883
884	/** @name IEMOPHINT_XXX - Additional Opcode Hints
885	* @note These are ORed together with IEMOPFORM_XXX.
886	* @{ */
887	/** Both the operand size prefixes are ignored. */
888	#define IEMOPHINT_IGNORES_OP_SIZE RT_BIT_32(10)
889	/** Allowed with the lock prefix. */
890	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
891	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
892	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
893	/** @} */
894
895	/**
896	* Possible hardware task switch sources.
897	*/
898	typedef enum IEMTASKSWITCH
899	{
900	/** Task switch caused by an interrupt/exception. */
901	IEMTASKSWITCH_INT_XCPT = 1,
902	/** Task switch caused by a far CALL. */
903	IEMTASKSWITCH_CALL,
904	/** Task switch caused by a far JMP. */
905	IEMTASKSWITCH_JUMP,
906	/** Task switch caused by an IRET. */
907	IEMTASKSWITCH_IRET
908	} IEMTASKSWITCH;
909	AssertCompileSize(IEMTASKSWITCH, 4);
910
911
912	/**
913	* Tests if verification mode is enabled.
914	*
915	* This expands to @c false when IEM_VERIFICATION_MODE is not defined and
916	* should therefore cause the compiler to eliminate the verification branch
917	* of an if statement. */
918	#ifdef IEM_VERIFICATION_MODE_FULL
919	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
920	#elif defined(IEM_VERIFICATION_MODE_MINIMAL)
921	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (true)
922	#else
923	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (false)
924	#endif
925
926	/**
927	* Tests if full verification mode is enabled.
928	*
929	* This expands to @c false when IEM_VERIFICATION_MODE_FULL is not defined and
930	* should therefore cause the compiler to eliminate the verification branch
931	* of an if statement. */
932	#ifdef IEM_VERIFICATION_MODE_FULL
933	# define IEM_FULL_VERIFICATION_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
934	#else
935	# define IEM_FULL_VERIFICATION_ENABLED(a_pVCpu) (false)
936	#endif
937
938	/**
939	* Tests if full verification mode is enabled again REM.
940	*
941	* This expands to @c false when IEM_VERIFICATION_MODE_FULL is not defined and
942	* should therefore cause the compiler to eliminate the verification branch
943	* of an if statement. */
944	#ifdef IEM_VERIFICATION_MODE_FULL
945	# ifdef IEM_VERIFICATION_MODE_FULL_HM
946	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem && !HMIsEnabled((a_pVCpu)->CTX_SUFF(pVM)))
947	# else
948	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
949	# endif
950	#else
951	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (false)
952	#endif
953
954	/** @def IEM_VERIFICATION_MODE
955	* Indicates that one of the verfication modes are enabled.
956	*/
957	#if (defined(IEM_VERIFICATION_MODE_FULL) \|\| defined(IEM_VERIFICATION_MODE_MINIMAL)) && !defined(IEM_VERIFICATION_MODE) \
958	\|\| defined(DOXYGEN_RUNNING)
959	# define IEM_VERIFICATION_MODE
960	#endif
961
962	/**
963	* Indicates to the verifier that the given flag set is undefined.
964	*
965	* Can be invoked again to add more flags.
966	*
967	* This is a NOOP if the verifier isn't compiled in.
968	*/
969	#ifdef IEM_VERIFICATION_MODE_FULL
970	# define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { pVCpu->iem.s.fUndefinedEFlags \|= (a_fEfl); } while (0)
971	#else
972	# define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
973	#endif
974
975
976	/** @def IEM_DECL_IMPL_TYPE
977	* For typedef'ing an instruction implementation function.
978	*
979	* @param a_RetType The return type.
980	* @param a_Name The name of the type.
981	* @param a_ArgList The argument list enclosed in parentheses.
982	*/
983
984	/** @def IEM_DECL_IMPL_DEF
985	* For defining an instruction implementation function.
986	*
987	* @param a_RetType The return type.
988	* @param a_Name The name of the type.
989	* @param a_ArgList The argument list enclosed in parentheses.
990	*/
991
992	#if defined(__GNUC__) && defined(RT_ARCH_X86)
993	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
994	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
995	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
996	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
997
998	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
999	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1000	a_RetType (__fastcall a_Name) a_ArgList
1001	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1002	a_RetType __fastcall a_Name a_ArgList
1003
1004	#else
1005	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1006	a_RetType (VBOXCALL a_Name) a_ArgList
1007	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1008	a_RetType VBOXCALL a_Name a_ArgList
1009
1010	#endif
1011
1012	/** @name Arithmetic assignment operations on bytes (binary).
1013	* @{ */
1014	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1015	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1016	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1017	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1018	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1019	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1020	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1021	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1022	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1023	/** @} */
1024
1025	/** @name Arithmetic assignment operations on words (binary).
1026	* @{ */
1027	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1028	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1029	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1030	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1031	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1032	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1033	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1034	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1035	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1036	/** @} */
1037
1038	/** @name Arithmetic assignment operations on double words (binary).
1039	* @{ */
1040	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1041	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1042	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1043	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1044	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1045	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1046	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1047	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1048	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1049	/** @} */
1050
1051	/** @name Arithmetic assignment operations on quad words (binary).
1052	* @{ */
1053	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1054	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1055	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1056	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1057	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1058	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1059	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1060	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1061	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1062	/** @} */
1063
1064	/** @name Compare operations (thrown in with the binary ops).
1065	* @{ */
1066	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1067	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1068	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1069	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1070	/** @} */
1071
1072	/** @name Test operations (thrown in with the binary ops).
1073	* @{ */
1074	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1075	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1076	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1077	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1078	/** @} */
1079
1080	/** @name Bit operations operations (thrown in with the binary ops).
1081	* @{ */
1082	FNIEMAIMPLBINU16 iemAImpl_bt_u16, iemAImpl_bt_u16_locked;
1083	FNIEMAIMPLBINU32 iemAImpl_bt_u32, iemAImpl_bt_u32_locked;
1084	FNIEMAIMPLBINU64 iemAImpl_bt_u64, iemAImpl_bt_u64_locked;
1085	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1086	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1087	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1088	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1089	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1090	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1091	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1092	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1093	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1094	/** @} */
1095
1096	/** @name Exchange memory with register operations.
1097	* @{ */
1098	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8, (uint8_t pu8Mem, uint8_t pu8Reg));
1099	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16,(uint16_t pu16Mem, uint16_t pu16Reg));
1100	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32,(uint32_t pu32Mem, uint32_t pu32Reg));
1101	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64,(uint64_t pu64Mem, uint64_t pu64Reg));
1102	/** @} */
1103
1104	/** @name Exchange and add operations.
1105	* @{ */
1106	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1107	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1108	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1109	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1110	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1111	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1112	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1113	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1114	/** @} */
1115
1116	/** @name Compare and exchange.
1117	* @{ */
1118	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1119	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1120	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1121	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1122	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1123	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1124	#ifdef RT_ARCH_X86
1125	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1126	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1127	#else
1128	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1129	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1130	#endif
1131	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1132	uint32_t *pEFlags));
1133	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1134	uint32_t *pEFlags));
1135	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1136	uint32_t *pEFlags));
1137	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1138	uint32_t *pEFlags));
1139	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1140	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1141	/** @} */
1142
1143	/** @name Memory ordering
1144	* @{ */
1145	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1146	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1147	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1148	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1149	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1150	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1151	/** @} */
1152
1153	/** @name Double precision shifts
1154	* @{ */
1155	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1156	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1157	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1158	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1159	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1160	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1161	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16;
1162	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32;
1163	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64;
1164	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16;
1165	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32;
1166	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64;
1167	/** @} */
1168
1169
1170	/** @name Bit search operations (thrown in with the binary ops).
1171	* @{ */
1172	FNIEMAIMPLBINU16 iemAImpl_bsf_u16;
1173	FNIEMAIMPLBINU32 iemAImpl_bsf_u32;
1174	FNIEMAIMPLBINU64 iemAImpl_bsf_u64;
1175	FNIEMAIMPLBINU16 iemAImpl_bsr_u16;
1176	FNIEMAIMPLBINU32 iemAImpl_bsr_u32;
1177	FNIEMAIMPLBINU64 iemAImpl_bsr_u64;
1178	/** @} */
1179
1180	/** @name Signed multiplication operations (thrown in with the binary ops).
1181	* @{ */
1182	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16;
1183	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32;
1184	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64;
1185	/** @} */
1186
1187	/** @name Arithmetic assignment operations on bytes (unary).
1188	* @{ */
1189	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1190	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1191	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1192	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1193	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1194	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1195	/** @} */
1196
1197	/** @name Arithmetic assignment operations on words (unary).
1198	* @{ */
1199	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1200	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1201	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1202	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1203	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1204	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1205	/** @} */
1206
1207	/** @name Arithmetic assignment operations on double words (unary).
1208	* @{ */
1209	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1210	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1211	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1212	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1213	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1214	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1215	/** @} */
1216
1217	/** @name Arithmetic assignment operations on quad words (unary).
1218	* @{ */
1219	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1220	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1221	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1222	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1223	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1224	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1225	/** @} */
1226
1227
1228	/** @name Shift operations on bytes (Group 2).
1229	* @{ */
1230	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1231	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1232	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8;
1233	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8;
1234	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8;
1235	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8;
1236	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8;
1237	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8;
1238	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8;
1239	/** @} */
1240
1241	/** @name Shift operations on words (Group 2).
1242	* @{ */
1243	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1244	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1245	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16;
1246	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16;
1247	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16;
1248	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16;
1249	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16;
1250	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16;
1251	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16;
1252	/** @} */
1253
1254	/** @name Shift operations on double words (Group 2).
1255	* @{ */
1256	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1257	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1258	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32;
1259	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32;
1260	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32;
1261	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32;
1262	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32;
1263	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32;
1264	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32;
1265	/** @} */
1266
1267	/** @name Shift operations on words (Group 2).
1268	* @{ */
1269	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1270	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1271	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64;
1272	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64;
1273	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64;
1274	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64;
1275	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64;
1276	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64;
1277	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64;
1278	/** @} */
1279
1280	/** @name Multiplication and division operations.
1281	* @{ */
1282	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1283	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1284	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_imul_u8;
1285	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_idiv_u8;
1286
1287	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1288	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1289	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_imul_u16;
1290	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_idiv_u16;
1291
1292	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1293	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1294	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_imul_u32;
1295	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_idiv_u32;
1296
1297	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1298	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1299	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_imul_u64;
1300	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_idiv_u64;
1301	/** @} */
1302
1303	/** @name Byte Swap.
1304	* @{ */
1305	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1306	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1307	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1308	/** @} */
1309
1310	/** @name Misc.
1311	* @{ */
1312	FNIEMAIMPLBINU16 iemAImpl_arpl;
1313	/** @} */
1314
1315
1316	/** @name FPU operations taking a 32-bit float argument
1317	* @{ */
1318	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1319	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1320	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1321
1322	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1323	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1324	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1325
1326	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1327	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1328	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1329	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1330	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1331	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1332	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1333
1334	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1335	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1336	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1337	/** @} */
1338
1339	/** @name FPU operations taking a 64-bit float argument
1340	* @{ */
1341	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1342	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1343	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1344
1345	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1346	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1347	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1348	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1349	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1350	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1351
1352	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1353	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1354	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1355	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1356	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1357	/** @} */
1358
1359	/** @name FPU operations taking a 80-bit float argument
1360	* @{ */
1361	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1362	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1363	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1364	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1365	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1366	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1367	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1368	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1369	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1370	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1371	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1372	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1373
1374	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80;
1375	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80;
1376	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80;
1377
1378	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1379	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1380	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1381	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1382	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1383
1384	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1385	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1386	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1387	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1388	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1389
1390	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1391	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1392	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1393	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1394	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80;
1395	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1396	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1397	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80;
1398	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80;
1399
1400	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1401	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1402	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1403	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1404
1405	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1406	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1407	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1408	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1409	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1410	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1411	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1412	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1413	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1414
1415	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1416	PCRTFLOAT80U pr80Val));
1417	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1418	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80;
1419	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1420	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80;
1421
1422	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1423	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1424	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1425
1426	/** @} */
1427
1428	/** @name FPU operations taking a 16-bit signed integer argument
1429	* @{ */
1430	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1431	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1432	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1433
1434	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1435	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1436	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1437	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1438	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1439	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1440
1441	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1442	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1443
1444	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1445	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1446	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1447	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1448	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1449	/** @} */
1450
1451	/** @name FPU operations taking a 32-bit signed integer argument
1452	* @{ */
1453	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1454	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1455	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1456
1457	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1458	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1459	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1460	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1461	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1462	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1463
1464	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1465	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1466
1467	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1468	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1469	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1470	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1471	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1472	/** @} */
1473
1474	/** @name FPU operations taking a 64-bit signed integer argument
1475	* @{ */
1476	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1477	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1478	typedef FNIEMAIMPLFPUI64 *PFNIEMAIMPLFPUI64;
1479
1480	FNIEMAIMPLFPUI64 iemAImpl_fiadd_r80_by_i64;
1481	FNIEMAIMPLFPUI64 iemAImpl_fimul_r80_by_i64;
1482	FNIEMAIMPLFPUI64 iemAImpl_fisub_r80_by_i64;
1483	FNIEMAIMPLFPUI64 iemAImpl_fisubr_r80_by_i64;
1484	FNIEMAIMPLFPUI64 iemAImpl_fidiv_r80_by_i64;
1485	FNIEMAIMPLFPUI64 iemAImpl_fidivr_r80_by_i64;
1486
1487	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1488	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1489
1490	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1491	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1492	int64_t *pi64Val, PCRTFLOAT80U pr80Val));
1493	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1494	int64_t *pi32Val, PCRTFLOAT80U pr80Val));
1495	/** @} */
1496
1497
1498	/** Temporary type representing a 256-bit vector register. */
1499	typedef struct {uint64_t au64[4]; } IEMVMM256;
1500	/** Temporary type pointing to a 256-bit vector register. */
1501	typedef IEMVMM256 *PIEMVMM256;
1502	/** Temporary type pointing to a const 256-bit vector register. */
1503	typedef IEMVMM256 *PCIEMVMM256;
1504
1505
1506	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1507	* @{ */
1508	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1509	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1510	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1511	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1512	FNIEMAIMPLMEDIAF2U64 iemAImpl_pxor_u64, iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1513	FNIEMAIMPLMEDIAF2U128 iemAImpl_pxor_u128, iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1514	/** @} */
1515
1516	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1517	* @{ */
1518	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src));
1519	typedef FNIEMAIMPLMEDIAF1L1U64 *PFNIEMAIMPLMEDIAF1L1U64;
1520	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src));
1521	typedef FNIEMAIMPLMEDIAF1L1U128 *PFNIEMAIMPLMEDIAF1L1U128;
1522	FNIEMAIMPLMEDIAF1L1U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1523	FNIEMAIMPLMEDIAF1L1U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1524	/** @} */
1525
1526	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
1527	* @{ */
1528	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1529	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF1H1U64;
1530	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1531	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF1H1U128;
1532	FNIEMAIMPLMEDIAF1H1U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
1533	FNIEMAIMPLMEDIAF1H1U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
1534	/** @} */
1535
1536	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
1537	* @{ */
1538	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUF,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst,
1539	PCRTUINT128U pu128Src, uint8_t bEvil));
1540	typedef FNIEMAIMPLMEDIAPSHUF *PFNIEMAIMPLMEDIAPSHUF;
1541	FNIEMAIMPLMEDIAPSHUF iemAImpl_pshufhw, iemAImpl_pshuflw, iemAImpl_pshufd;
1542	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil));
1543	/** @} */
1544
1545	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
1546	* @{ */
1547	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1548	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src));
1549	/** @} */
1550
1551	/** @name Media (SSE/MMX/AVX) operation: Sort this later
1552	* @{ */
1553	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1554	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc));
1555	/** @} */
1556
1557
1558	/** @name Function tables.
1559	* @{
1560	*/
1561
1562	/**
1563	* Function table for a binary operator providing implementation based on
1564	* operand size.
1565	*/
1566	typedef struct IEMOPBINSIZES
1567	{
1568	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
1569	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
1570	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
1571	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
1572	} IEMOPBINSIZES;
1573	/** Pointer to a binary operator function table. */
1574	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
1575
1576
1577	/**
1578	* Function table for a unary operator providing implementation based on
1579	* operand size.
1580	*/
1581	typedef struct IEMOPUNARYSIZES
1582	{
1583	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
1584	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
1585	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
1586	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
1587	} IEMOPUNARYSIZES;
1588	/** Pointer to a unary operator function table. */
1589	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
1590
1591
1592	/**
1593	* Function table for a shift operator providing implementation based on
1594	* operand size.
1595	*/
1596	typedef struct IEMOPSHIFTSIZES
1597	{
1598	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
1599	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
1600	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
1601	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
1602	} IEMOPSHIFTSIZES;
1603	/** Pointer to a shift operator function table. */
1604	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
1605
1606
1607	/**
1608	* Function table for a multiplication or division operation.
1609	*/
1610	typedef struct IEMOPMULDIVSIZES
1611	{
1612	PFNIEMAIMPLMULDIVU8 pfnU8;
1613	PFNIEMAIMPLMULDIVU16 pfnU16;
1614	PFNIEMAIMPLMULDIVU32 pfnU32;
1615	PFNIEMAIMPLMULDIVU64 pfnU64;
1616	} IEMOPMULDIVSIZES;
1617	/** Pointer to a multiplication or division operation function table. */
1618	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
1619
1620
1621	/**
1622	* Function table for a double precision shift operator providing implementation
1623	* based on operand size.
1624	*/
1625	typedef struct IEMOPSHIFTDBLSIZES
1626	{
1627	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
1628	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
1629	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
1630	} IEMOPSHIFTDBLSIZES;
1631	/** Pointer to a double precision shift function table. */
1632	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
1633
1634
1635	/**
1636	* Function table for media instruction taking two full sized media registers,
1637	* optionally the 2nd being a memory reference (only modifying the first op.)
1638	*/
1639	typedef struct IEMOPMEDIAF2
1640	{
1641	PFNIEMAIMPLMEDIAF2U64 pfnU64;
1642	PFNIEMAIMPLMEDIAF2U128 pfnU128;
1643	} IEMOPMEDIAF2;
1644	/** Pointer to a media operation function table for full sized ops. */
1645	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
1646
1647	/**
1648	* Function table for media instruction taking taking one full and one lower
1649	* half media register.
1650	*/
1651	typedef struct IEMOPMEDIAF1L1
1652	{
1653	PFNIEMAIMPLMEDIAF1L1U64 pfnU64;
1654	PFNIEMAIMPLMEDIAF1L1U128 pfnU128;
1655	} IEMOPMEDIAF1L1;
1656	/** Pointer to a media operation function table for lowhalf+lowhalf -> full. */
1657	typedef IEMOPMEDIAF1L1 const *PCIEMOPMEDIAF1L1;
1658
1659	/**
1660	* Function table for media instruction taking taking one full and one high half
1661	* media register.
1662	*/
1663	typedef struct IEMOPMEDIAF1H1
1664	{
1665	PFNIEMAIMPLMEDIAF1H1U64 pfnU64;
1666	PFNIEMAIMPLMEDIAF1H1U128 pfnU128;
1667	} IEMOPMEDIAF1H1;
1668	/** Pointer to a media operation function table for hihalf+hihalf -> full. */
1669	typedef IEMOPMEDIAF1H1 const *PCIEMOPMEDIAF1H1;
1670
1671
1672	/** @} */
1673
1674
1675	/** @name C instruction implementations for anything slightly complicated.
1676	* @{ */
1677
1678	/**
1679	* For typedef'ing or declaring a C instruction implementation function taking
1680	* no extra arguments.
1681	*
1682	* @param a_Name The name of the type.
1683	*/
1684	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
1685	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1686	/**
1687	* For defining a C instruction implementation function taking no extra
1688	* arguments.
1689	*
1690	* @param a_Name The name of the function
1691	*/
1692	# define IEM_CIMPL_DEF_0(a_Name) \
1693	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1694	/**
1695	* For calling a C instruction implementation function taking no extra
1696	* arguments.
1697	*
1698	* This special call macro adds default arguments to the call and allow us to
1699	* change these later.
1700	*
1701	* @param a_fn The name of the function.
1702	*/
1703	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
1704
1705	/**
1706	* For typedef'ing or declaring a C instruction implementation function taking
1707	* one extra argument.
1708	*
1709	* @param a_Name The name of the type.
1710	* @param a_Type0 The argument type.
1711	* @param a_Arg0 The argument name.
1712	*/
1713	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
1714	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1715	/**
1716	* For defining a C instruction implementation function taking one extra
1717	* argument.
1718	*
1719	* @param a_Name The name of the function
1720	* @param a_Type0 The argument type.
1721	* @param a_Arg0 The argument name.
1722	*/
1723	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
1724	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1725	/**
1726	* For calling a C instruction implementation function taking one extra
1727	* argument.
1728	*
1729	* This special call macro adds default arguments to the call and allow us to
1730	* change these later.
1731	*
1732	* @param a_fn The name of the function.
1733	* @param a0 The name of the 1st argument.
1734	*/
1735	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
1736
1737	/**
1738	* For typedef'ing or declaring a C instruction implementation function taking
1739	* two extra arguments.
1740	*
1741	* @param a_Name The name of the type.
1742	* @param a_Type0 The type of the 1st argument
1743	* @param a_Arg0 The name of the 1st argument.
1744	* @param a_Type1 The type of the 2nd argument.
1745	* @param a_Arg1 The name of the 2nd argument.
1746	*/
1747	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1748	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1749	/**
1750	* For defining a C instruction implementation function taking two extra
1751	* arguments.
1752	*
1753	* @param a_Name The name of the function.
1754	* @param a_Type0 The type of the 1st argument
1755	* @param a_Arg0 The name of the 1st argument.
1756	* @param a_Type1 The type of the 2nd argument.
1757	* @param a_Arg1 The name of the 2nd argument.
1758	*/
1759	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1760	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1761	/**
1762	* For calling a C instruction implementation function taking two extra
1763	* arguments.
1764	*
1765	* This special call macro adds default arguments to the call and allow us to
1766	* change these later.
1767	*
1768	* @param a_fn The name of the function.
1769	* @param a0 The name of the 1st argument.
1770	* @param a1 The name of the 2nd argument.
1771	*/
1772	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
1773
1774	/**
1775	* For typedef'ing or declaring a C instruction implementation function taking
1776	* three extra arguments.
1777	*
1778	* @param a_Name The name of the type.
1779	* @param a_Type0 The type of the 1st argument
1780	* @param a_Arg0 The name of the 1st argument.
1781	* @param a_Type1 The type of the 2nd argument.
1782	* @param a_Arg1 The name of the 2nd argument.
1783	* @param a_Type2 The type of the 3rd argument.
1784	* @param a_Arg2 The name of the 3rd argument.
1785	*/
1786	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1787	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1788	/**
1789	* For defining a C instruction implementation function taking three extra
1790	* arguments.
1791	*
1792	* @param a_Name The name of the function.
1793	* @param a_Type0 The type of the 1st argument
1794	* @param a_Arg0 The name of the 1st argument.
1795	* @param a_Type1 The type of the 2nd argument.
1796	* @param a_Arg1 The name of the 2nd argument.
1797	* @param a_Type2 The type of the 3rd argument.
1798	* @param a_Arg2 The name of the 3rd argument.
1799	*/
1800	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1801	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1802	/**
1803	* For calling a C instruction implementation function taking three extra
1804	* arguments.
1805	*
1806	* This special call macro adds default arguments to the call and allow us to
1807	* change these later.
1808	*
1809	* @param a_fn The name of the function.
1810	* @param a0 The name of the 1st argument.
1811	* @param a1 The name of the 2nd argument.
1812	* @param a2 The name of the 3rd argument.
1813	*/
1814	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
1815
1816
1817	/**
1818	* For typedef'ing or declaring a C instruction implementation function taking
1819	* four extra arguments.
1820	*
1821	* @param a_Name The name of the type.
1822	* @param a_Type0 The type of the 1st argument
1823	* @param a_Arg0 The name of the 1st argument.
1824	* @param a_Type1 The type of the 2nd argument.
1825	* @param a_Arg1 The name of the 2nd argument.
1826	* @param a_Type2 The type of the 3rd argument.
1827	* @param a_Arg2 The name of the 3rd argument.
1828	* @param a_Type3 The type of the 4th argument.
1829	* @param a_Arg3 The name of the 4th argument.
1830	*/
1831	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1832	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
1833	/**
1834	* For defining a C instruction implementation function taking four extra
1835	* arguments.
1836	*
1837	* @param a_Name The name of the function.
1838	* @param a_Type0 The type of the 1st argument
1839	* @param a_Arg0 The name of the 1st argument.
1840	* @param a_Type1 The type of the 2nd argument.
1841	* @param a_Arg1 The name of the 2nd argument.
1842	* @param a_Type2 The type of the 3rd argument.
1843	* @param a_Arg2 The name of the 3rd argument.
1844	* @param a_Type3 The type of the 4th argument.
1845	* @param a_Arg3 The name of the 4th argument.
1846	*/
1847	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1848	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1849	a_Type2 a_Arg2, a_Type3 a_Arg3))
1850	/**
1851	* For calling a C instruction implementation function taking four extra
1852	* arguments.
1853	*
1854	* This special call macro adds default arguments to the call and allow us to
1855	* change these later.
1856	*
1857	* @param a_fn The name of the function.
1858	* @param a0 The name of the 1st argument.
1859	* @param a1 The name of the 2nd argument.
1860	* @param a2 The name of the 3rd argument.
1861	* @param a3 The name of the 4th argument.
1862	*/
1863	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
1864
1865
1866	/**
1867	* For typedef'ing or declaring a C instruction implementation function taking
1868	* five extra arguments.
1869	*
1870	* @param a_Name The name of the type.
1871	* @param a_Type0 The type of the 1st argument
1872	* @param a_Arg0 The name of the 1st argument.
1873	* @param a_Type1 The type of the 2nd argument.
1874	* @param a_Arg1 The name of the 2nd argument.
1875	* @param a_Type2 The type of the 3rd argument.
1876	* @param a_Arg2 The name of the 3rd argument.
1877	* @param a_Type3 The type of the 4th argument.
1878	* @param a_Arg3 The name of the 4th argument.
1879	* @param a_Type4 The type of the 5th argument.
1880	* @param a_Arg4 The name of the 5th argument.
1881	*/
1882	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1883	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1884	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1885	a_Type3 a_Arg3, a_Type4 a_Arg4))
1886	/**
1887	* For defining a C instruction implementation function taking five extra
1888	* arguments.
1889	*
1890	* @param a_Name The name of the function.
1891	* @param a_Type0 The type of the 1st argument
1892	* @param a_Arg0 The name of the 1st argument.
1893	* @param a_Type1 The type of the 2nd argument.
1894	* @param a_Arg1 The name of the 2nd argument.
1895	* @param a_Type2 The type of the 3rd argument.
1896	* @param a_Arg2 The name of the 3rd argument.
1897	* @param a_Type3 The type of the 4th argument.
1898	* @param a_Arg3 The name of the 4th argument.
1899	* @param a_Type4 The type of the 5th argument.
1900	* @param a_Arg4 The name of the 5th argument.
1901	*/
1902	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1903	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1904	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1905	a_Type3 a_Arg3, a_Type4 a_Arg4))
1906	/**
1907	* For calling a C instruction implementation function taking five extra
1908	* arguments.
1909	*
1910	* This special call macro adds default arguments to the call and allow us to
1911	* change these later.
1912	*
1913	* @param a_fn The name of the function.
1914	* @param a0 The name of the 1st argument.
1915	* @param a1 The name of the 2nd argument.
1916	* @param a2 The name of the 3rd argument.
1917	* @param a3 The name of the 4th argument.
1918	* @param a4 The name of the 5th argument.
1919	*/
1920	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
1921
1922	/** @} */
1923
1924
1925	/** @} */
1926
1927	RT_C_DECLS_END
1928
1929	#endif
1930

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 66345

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