IEMInternal.h@ 66901

Last change on this file since 66901 was 66901, checked in by vboxsync, 8 years ago
IEM: Implemented vmovss Vss,Hss,Wss (VEX.F3.0F 10 mod=11) and vmovss Vss,Wss (VEX.F3.0F 10 mod!=33).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 83.7 KB

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1	/* $Id: IEMInternal.h 66901 2017-05-15 22:41:07Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___IEMInternal_h
19	#define ___IEMInternal_h
20
21	#include <VBox/vmm/cpum.h>
22	#include <VBox/vmm/iem.h>
23	#include <VBox/vmm/stam.h>
24	#include <VBox/param.h>
25
26	#include <setjmp.h>
27
28
29	RT_C_DECLS_BEGIN
30
31
32	/** @defgroup grp_iem_int Internals
33	* @ingroup grp_iem
34	* @internal
35	* @{
36	*/
37
38	/** For expanding symbol in slickedit and other products tagging and
39	* crossreferencing IEM symbols. */
40	#ifndef IEM_STATIC
41	# define IEM_STATIC static
42	#endif
43
44	/** @def IEM_WITH_3DNOW
45	* Includes the 3DNow decoding. */
46	#define IEM_WITH_3DNOW
47
48	/** @def IEM_WITH_THREE_0F_38
49	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
50	#define IEM_WITH_THREE_0F_38
51
52	/** @def IEM_WITH_THREE_0F_3A
53	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
54	#define IEM_WITH_THREE_0F_3A
55
56	/** @def IEM_WITH_VEX
57	* Includes the VEX decoding. */
58	#define IEM_WITH_VEX
59
60
61	/** @def IEM_VERIFICATION_MODE_FULL
62	* Shorthand for:
63	* defined(IEM_VERIFICATION_MODE) && !defined(IEM_VERIFICATION_MODE_MINIMAL)
64	*/
65	#if (defined(IEM_VERIFICATION_MODE) && !defined(IEM_VERIFICATION_MODE_MINIMAL) && !defined(IEM_VERIFICATION_MODE_FULL)) \
66	\|\| defined(DOXYGEN_RUNNING)
67	# define IEM_VERIFICATION_MODE_FULL
68	#endif
69
70
71	/** @def IEM_CFG_TARGET_CPU
72	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
73	*
74	* By default we allow this to be configured by the user via the
75	* CPUM/GuestCpuName config string, but this comes at a slight cost during
76	* decoding. So, for applications of this code where there is no need to
77	* be dynamic wrt target CPU, just modify this define.
78	*/
79	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
80	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
81	#endif
82
83
84	//#define IEM_WITH_CODE_TLB// - work in progress
85
86
87	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
88	/** Instruction statistics. */
89	typedef struct IEMINSTRSTATS
90	{
91	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
92	# include "IEMInstructionStatisticsTmpl.h"
93	# undef IEM_DO_INSTR_STAT
94	} IEMINSTRSTATS;
95	#else
96	struct IEMINSTRSTATS;
97	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
98	#endif
99	/** Pointer to IEM instruction statistics. */
100	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
101
102	/** Finish and move to types.h */
103	typedef union
104	{
105	uint32_t u32;
106	} RTFLOAT32U;
107	typedef RTFLOAT32U *PRTFLOAT32U;
108	typedef RTFLOAT32U const *PCRTFLOAT32U;
109
110
111	/**
112	* Extended operand mode that includes a representation of 8-bit.
113	*
114	* This is used for packing down modes when invoking some C instruction
115	* implementations.
116	*/
117	typedef enum IEMMODEX
118	{
119	IEMMODEX_16BIT = IEMMODE_16BIT,
120	IEMMODEX_32BIT = IEMMODE_32BIT,
121	IEMMODEX_64BIT = IEMMODE_64BIT,
122	IEMMODEX_8BIT
123	} IEMMODEX;
124	AssertCompileSize(IEMMODEX, 4);
125
126
127	/**
128	* Branch types.
129	*/
130	typedef enum IEMBRANCH
131	{
132	IEMBRANCH_JUMP = 1,
133	IEMBRANCH_CALL,
134	IEMBRANCH_TRAP,
135	IEMBRANCH_SOFTWARE_INT,
136	IEMBRANCH_HARDWARE_INT
137	} IEMBRANCH;
138	AssertCompileSize(IEMBRANCH, 4);
139
140
141	/**
142	* INT instruction types.
143	*/
144	typedef enum IEMINT
145	{
146	/** INT n instruction (opcode 0xcd imm). */
147	IEMINT_INTN = 0,
148	/** Single byte INT3 instruction (opcode 0xcc). */
149	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
150	/** Single byte INTO instruction (opcode 0xce). */
151	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
152	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
153	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
154	} IEMINT;
155	AssertCompileSize(IEMINT, 4);
156
157
158	/**
159	* A FPU result.
160	*/
161	typedef struct IEMFPURESULT
162	{
163	/** The output value. */
164	RTFLOAT80U r80Result;
165	/** The output status. */
166	uint16_t FSW;
167	} IEMFPURESULT;
168	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
169	/** Pointer to a FPU result. */
170	typedef IEMFPURESULT *PIEMFPURESULT;
171	/** Pointer to a const FPU result. */
172	typedef IEMFPURESULT const *PCIEMFPURESULT;
173
174
175	/**
176	* A FPU result consisting of two output values and FSW.
177	*/
178	typedef struct IEMFPURESULTTWO
179	{
180	/** The first output value. */
181	RTFLOAT80U r80Result1;
182	/** The output status. */
183	uint16_t FSW;
184	/** The second output value. */
185	RTFLOAT80U r80Result2;
186	} IEMFPURESULTTWO;
187	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
188	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
189	/** Pointer to a FPU result consisting of two output values and FSW. */
190	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
191	/** Pointer to a const FPU result consisting of two output values and FSW. */
192	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
193
194
195
196	#ifdef IEM_VERIFICATION_MODE_FULL
197
198	/**
199	* Verification event type.
200	*/
201	typedef enum IEMVERIFYEVENT
202	{
203	IEMVERIFYEVENT_INVALID = 0,
204	IEMVERIFYEVENT_IOPORT_READ,
205	IEMVERIFYEVENT_IOPORT_WRITE,
206	IEMVERIFYEVENT_IOPORT_STR_READ,
207	IEMVERIFYEVENT_IOPORT_STR_WRITE,
208	IEMVERIFYEVENT_RAM_WRITE,
209	IEMVERIFYEVENT_RAM_READ
210	} IEMVERIFYEVENT;
211
212	/** Checks if the event type is a RAM read or write. */
213	# define IEMVERIFYEVENT_IS_RAM(a_enmType) ((a_enmType) == IEMVERIFYEVENT_RAM_WRITE \|\| (a_enmType) == IEMVERIFYEVENT_RAM_READ)
214
215	/**
216	* Verification event record.
217	*/
218	typedef struct IEMVERIFYEVTREC
219	{
220	/** Pointer to the next record in the list. */
221	struct IEMVERIFYEVTREC *pNext;
222	/** The event type. */
223	IEMVERIFYEVENT enmEvent;
224	/** The event data. */
225	union
226	{
227	/** IEMVERIFYEVENT_IOPORT_READ */
228	struct
229	{
230	RTIOPORT Port;
231	uint8_t cbValue;
232	} IOPortRead;
233
234	/** IEMVERIFYEVENT_IOPORT_WRITE */
235	struct
236	{
237	RTIOPORT Port;
238	uint8_t cbValue;
239	uint32_t u32Value;
240	} IOPortWrite;
241
242	/** IEMVERIFYEVENT_IOPORT_STR_READ */
243	struct
244	{
245	RTIOPORT Port;
246	uint8_t cbValue;
247	RTGCUINTREG cTransfers;
248	} IOPortStrRead;
249
250	/** IEMVERIFYEVENT_IOPORT_STR_WRITE */
251	struct
252	{
253	RTIOPORT Port;
254	uint8_t cbValue;
255	RTGCUINTREG cTransfers;
256	} IOPortStrWrite;
257
258	/** IEMVERIFYEVENT_RAM_READ */
259	struct
260	{
261	RTGCPHYS GCPhys;
262	uint32_t cb;
263	} RamRead;
264
265	/** IEMVERIFYEVENT_RAM_WRITE */
266	struct
267	{
268	RTGCPHYS GCPhys;
269	uint32_t cb;
270	uint8_t ab[512];
271	} RamWrite;
272	} u;
273	} IEMVERIFYEVTREC;
274	/** Pointer to an IEM event verification records. */
275	typedef IEMVERIFYEVTREC *PIEMVERIFYEVTREC;
276
277	#endif /* IEM_VERIFICATION_MODE_FULL */
278
279
280	/**
281	* IEM TLB entry.
282	*
283	* Lookup assembly:
284	* @code{.asm}
285	; Calculate tag.
286	mov rax, [VA]
287	shl rax, 16
288	shr rax, 16 + X86_PAGE_SHIFT
289	or rax, [uTlbRevision]
290
291	; Do indexing.
292	movzx ecx, al
293	lea rcx, [pTlbEntries + rcx]
294
295	; Check tag.
296	cmp [rcx + IEMTLBENTRY.uTag], rax
297	jne .TlbMiss
298
299	; Check access.
300	movsx rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
301	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
302	cmp rax, [uTlbPhysRev]
303	jne .TlbMiss
304
305	; Calc address and we're done.
306	mov eax, X86_PAGE_OFFSET_MASK
307	and eax, [VA]
308	or rax, [rcx + IEMTLBENTRY.pMappingR3]
309	%ifdef VBOX_WITH_STATISTICS
310	inc qword [cTlbHits]
311	%endif
312	jmp .Done
313
314	.TlbMiss:
315	mov r8d, ACCESS_FLAGS
316	mov rdx, [VA]
317	mov rcx, [pVCpu]
318	call iemTlbTypeMiss
319	.Done:
320
321	@endcode
322	*
323	*/
324	typedef struct IEMTLBENTRY
325	{
326	/** The TLB entry tag.
327	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits.
328	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
329	*
330	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
331	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
332	* revision wraps around though, the tags needs to be zeroed.
333	*
334	* @note Try use SHRD instruction? After seeing
335	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
336	*/
337	uint64_t uTag;
338	/** Access flags and physical TLB revision.
339	*
340	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
341	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
342	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
343	* - Bit 3 - pgm phys/virt - not directly writable.
344	* - Bit 4 - pgm phys page - not directly readable.
345	* - Bit 5 - currently unused.
346	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
347	* - Bit 7 - tlb entry - pMappingR3 member not valid.
348	* - Bits 63 thru 8 are used for the physical TLB revision number.
349	*
350	* We're using complemented bit meanings here because it makes it easy to check
351	* whether special action is required. For instance a user mode write access
352	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
353	* non-zero result would mean special handling needed because either it wasn't
354	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
355	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
356	* need to check any PTE flag.
357	*/
358	uint64_t fFlagsAndPhysRev;
359	/** The guest physical page address. */
360	uint64_t GCPhys;
361	/** Pointer to the ring-3 mapping (possibly also valid in ring-0). */
362	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
363	R3PTRTYPE(uint8_t *) pbMappingR3;
364	#else
365	R3R0PTRTYPE(uint8_t *) pbMappingR3;
366	#endif
367	#if HC_ARCH_BITS == 32
368	uint32_t u32Padding1;
369	#endif
370	} IEMTLBENTRY;
371	AssertCompileSize(IEMTLBENTRY, 32);
372	/** Pointer to an IEM TLB entry. */
373	typedef IEMTLBENTRY *PIEMTLBENTRY;
374
375	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
376	* @{ */
377	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
378	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
379	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
380	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
381	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
382	#define IEMTLBE_F_PATCH_CODE RT_BIT_64(5) /*< Code TLB: Patch code (PATM). /
383	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
384	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
385	#define IEMTLBE_F_PHYS_REV UINT64_C(0xffffffffffffff00) /*< Physical revision mask. /
386	/** @} */
387
388
389	/**
390	* An IEM TLB.
391	*
392	* We've got two of these, one for data and one for instructions.
393	*/
394	typedef struct IEMTLB
395	{
396	/** The TLB entries.
397	* We've choosen 256 because that way we can obtain the result directly from a
398	* 8-bit register without an additional AND instruction. */
399	IEMTLBENTRY aEntries[256];
400	/** The TLB revision.
401	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
402	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
403	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
404	* (The revision zero indicates an invalid TLB entry.)
405	*
406	* The initial value is choosen to cause an early wraparound. */
407	uint64_t uTlbRevision;
408	/** The TLB physical address revision - shadow of PGM variable.
409	*
410	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
411	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
412	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
413	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
414	*
415	* The initial value is choosen to cause an early wraparound. */
416	uint64_t volatile uTlbPhysRev;
417
418	/* Statistics: */
419
420	/** TLB hits (VBOX_WITH_STATISTICS only). */
421	uint64_t cTlbHits;
422	/** TLB misses. */
423	uint32_t cTlbMisses;
424	/** Slow read path. */
425	uint32_t cTlbSlowReadPath;
426	#if 0
427	/** TLB misses because of tag mismatch. */
428	uint32_t cTlbMissesTag;
429	/** TLB misses because of virtual access violation. */
430	uint32_t cTlbMissesVirtAccess;
431	/** TLB misses because of dirty bit. */
432	uint32_t cTlbMissesDirty;
433	/** TLB misses because of MMIO */
434	uint32_t cTlbMissesMmio;
435	/** TLB misses because of write access handlers. */
436	uint32_t cTlbMissesWriteHandler;
437	/** TLB misses because no r3(/r0) mapping. */
438	uint32_t cTlbMissesMapping;
439	#endif
440	/** Alignment padding. */
441	uint32_t au32Padding[3+5];
442	} IEMTLB;
443	AssertCompileSizeAlignment(IEMTLB, 64);
444	/** IEMTLB::uTlbRevision increment. */
445	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
446	/** IEMTLB::uTlbPhysRev increment. */
447	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(8)
448
449
450	/**
451	* The per-CPU IEM state.
452	*/
453	typedef struct IEMCPU
454	{
455	/** Info status code that needs to be propagated to the IEM caller.
456	* This cannot be passed internally, as it would complicate all success
457	* checks within the interpreter making the code larger and almost impossible
458	* to get right. Instead, we'll store status codes to pass on here. Each
459	* source of these codes will perform appropriate sanity checks. */
460	int32_t rcPassUp; /* 0x00 */
461
462	/** The current CPU execution mode (CS). */
463	IEMMODE enmCpuMode; /* 0x04 */
464	/** The CPL. */
465	uint8_t uCpl; /* 0x05 */
466
467	/** Whether to bypass access handlers or not. */
468	bool fBypassHandlers; /* 0x06 */
469	/** Indicates that we're interpreting patch code - RC only! */
470	bool fInPatchCode; /* 0x07 */
471
472	/** @name Decoder state.
473	* @{ */
474	#ifdef IEM_WITH_CODE_TLB
475	/** The offset of the next instruction byte. */
476	uint32_t offInstrNextByte; /* 0x08 */
477	/** The number of bytes available at pbInstrBuf for the current instruction.
478	* This takes the max opcode length into account so that doesn't need to be
479	* checked separately. */
480	uint32_t cbInstrBuf; /* 0x0c */
481	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
482	* This can be NULL if the page isn't mappable for some reason, in which
483	* case we'll do fallback stuff.
484	*
485	* If we're executing an instruction from a user specified buffer,
486	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
487	* aligned pointer but pointer to the user data.
488	*
489	* For instructions crossing pages, this will start on the first page and be
490	* advanced to the next page by the time we've decoded the instruction. This
491	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
492	*/
493	uint8_t const pbInstrBuf; / 0x10 */
494	# if ARCH_BITS == 32
495	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
496	# endif
497	/** The program counter corresponding to pbInstrBuf.
498	* This is set to a non-canonical address when we need to invalidate it. */
499	uint64_t uInstrBufPc; /* 0x18 */
500	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
501	* This takes the CS segment limit into account. */
502	uint16_t cbInstrBufTotal; /* 0x20 */
503	/** Offset into pbInstrBuf of the first byte of the current instruction.
504	* Can be negative to efficiently handle cross page instructions. */
505	int16_t offCurInstrStart; /* 0x22 */
506
507	/** The prefix mask (IEM_OP_PRF_XXX). */
508	uint32_t fPrefixes; /* 0x24 */
509	/** The extra REX ModR/M register field bit (REX.R << 3). */
510	uint8_t uRexReg; /* 0x28 */
511	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
512	* (REX.B << 3). */
513	uint8_t uRexB; /* 0x29 */
514	/** The extra REX SIB index field bit (REX.X << 3). */
515	uint8_t uRexIndex; /* 0x2a */
516
517	/** The effective segment register (X86_SREG_XXX). */
518	uint8_t iEffSeg; /* 0x2b */
519
520	#else
521	/** The size of what has currently been fetched into abOpcode. */
522	uint8_t cbOpcode; /* 0x08 */
523	/** The current offset into abOpcode. */
524	uint8_t offOpcode; /* 0x09 */
525
526	/** The effective segment register (X86_SREG_XXX). */
527	uint8_t iEffSeg; /* 0x0a */
528
529	/** The extra REX ModR/M register field bit (REX.R << 3). */
530	uint8_t uRexReg; /* 0x0b */
531	/** The prefix mask (IEM_OP_PRF_XXX). */
532	uint32_t fPrefixes; /* 0x0c */
533	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
534	* (REX.B << 3). */
535	uint8_t uRexB; /* 0x10 */
536	/** The extra REX SIB index field bit (REX.X << 3). */
537	uint8_t uRexIndex; /* 0x11 */
538
539	#endif
540
541	/** The effective operand mode. */
542	IEMMODE enmEffOpSize; /* 0x2c, 0x12 */
543	/** The default addressing mode. */
544	IEMMODE enmDefAddrMode; /* 0x2d, 0x13 */
545	/** The effective addressing mode. */
546	IEMMODE enmEffAddrMode; /* 0x2e, 0x14 */
547	/** The default operand mode. */
548	IEMMODE enmDefOpSize; /* 0x2f, 0x15 */
549
550	/** Prefix index (VEX.pp) for two byte and three byte tables. */
551	uint8_t idxPrefix; /* 0x30, 0x16 */
552	/** 3rd VEX/EVEX/XOP register. */
553	uint8_t uVex3rdReg; /* 0x31, 0x17 */
554	/** The VEX/EVEX/XOP length field. */
555	uint8_t uVexLength; /* 0x32, 0x18 */
556	/** Additional EVEX stuff. */
557	uint8_t fEvexStuff; /* 0x33, 0x19 */
558
559	/** The FPU opcode (FOP). */
560	uint16_t uFpuOpcode; /* 0x34, 0x1a */
561
562	/** Explicit alignment padding. */
563	#ifdef IEM_WITH_CODE_TLB
564	uint8_t abAlignment2a[2]; /* 0x36 */
565	#endif
566
567	/** The opcode bytes. */
568	uint8_t abOpcode[15]; /* 0x48, 0x1c */
569	/** Explicit alignment padding. */
570	#ifdef IEM_WITH_CODE_TLB
571	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
572	#else
573	uint8_t abAlignment2c[0x48 - 0x2b]; /* 0x2b */
574	#endif
575	/** @} */
576
577
578	/** The flags of the current exception / interrupt. */
579	uint32_t fCurXcpt; /* 0x48, 0x48 */
580	/** The current exception / interrupt. */
581	uint8_t uCurXcpt;
582	/** Exception / interrupt recursion depth. */
583	int8_t cXcptRecursions;
584
585	/** The number of active guest memory mappings. */
586	uint8_t cActiveMappings;
587	/** The next unused mapping index. */
588	uint8_t iNextMapping;
589	/** Records for tracking guest memory mappings. */
590	struct
591	{
592	/** The address of the mapped bytes. */
593	void *pv;
594	#if defined(IN_RC) && HC_ARCH_BITS == 64
595	uint32_t u32Alignment3; /*< Alignment padding. /
596	#endif
597	/** The access flags (IEM_ACCESS_XXX).
598	* IEM_ACCESS_INVALID if the entry is unused. */
599	uint32_t fAccess;
600	#if HC_ARCH_BITS == 64
601	uint32_t u32Alignment4; /*< Alignment padding. /
602	#endif
603	} aMemMappings[3];
604
605	/** Locking records for the mapped memory. */
606	union
607	{
608	PGMPAGEMAPLOCK Lock;
609	uint64_t au64Padding[2];
610	} aMemMappingLocks[3];
611
612	/** Bounce buffer info.
613	* This runs in parallel to aMemMappings. */
614	struct
615	{
616	/** The physical address of the first byte. */
617	RTGCPHYS GCPhysFirst;
618	/** The physical address of the second page. */
619	RTGCPHYS GCPhysSecond;
620	/** The number of bytes in the first page. */
621	uint16_t cbFirst;
622	/** The number of bytes in the second page. */
623	uint16_t cbSecond;
624	/** Whether it's unassigned memory. */
625	bool fUnassigned;
626	/** Explicit alignment padding. */
627	bool afAlignment5[3];
628	} aMemBbMappings[3];
629
630	/** Bounce buffer storage.
631	* This runs in parallel to aMemMappings and aMemBbMappings. */
632	struct
633	{
634	uint8_t ab[512];
635	} aBounceBuffers[3];
636
637
638	/** Pointer set jump buffer - ring-3 context. */
639	R3PTRTYPE(jmp_buf *) pJmpBufR3;
640	/** Pointer set jump buffer - ring-0 context. */
641	R0PTRTYPE(jmp_buf *) pJmpBufR0;
642	/** Pointer set jump buffer - raw-mode context. */
643	RCPTRTYPE(jmp_buf *) pJmpBufRC;
644
645	/** @todo Should move this near @a fCurXcpt later. */
646	/** The error code for the current exception / interrupt. */
647	uint32_t uCurXcptErr;
648	/** The CR2 for the current exception / interrupt. */
649	uint64_t uCurXcptCr2;
650
651	/** @name Statistics
652	* @{ */
653	/** The number of instructions we've executed. */
654	uint32_t cInstructions;
655	/** The number of potential exits. */
656	uint32_t cPotentialExits;
657	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
658	* This may contain uncommitted writes. */
659	uint32_t cbWritten;
660	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
661	uint32_t cRetInstrNotImplemented;
662	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
663	uint32_t cRetAspectNotImplemented;
664	/** Counts informational statuses returned (other than VINF_SUCCESS). */
665	uint32_t cRetInfStatuses;
666	/** Counts other error statuses returned. */
667	uint32_t cRetErrStatuses;
668	/** Number of times rcPassUp has been used. */
669	uint32_t cRetPassUpStatus;
670	/** Number of times RZ left with instruction commit pending for ring-3. */
671	uint32_t cPendingCommit;
672	/** Number of long jumps. */
673	uint32_t cLongJumps;
674	uint32_t uAlignment6; /*< Alignment padding. /
675	#ifdef IEM_VERIFICATION_MODE_FULL
676	/** The Number of I/O port reads that has been performed. */
677	uint32_t cIOReads;
678	/** The Number of I/O port writes that has been performed. */
679	uint32_t cIOWrites;
680	/** Set if no comparison to REM is currently performed.
681	* This is used to skip past really slow bits. */
682	bool fNoRem;
683	/** Saved fNoRem flag used by #iemInitExec and #iemUninitExec. */
684	bool fNoRemSavedByExec;
685	/** Indicates that RAX and RDX differences should be ignored since RDTSC
686	* and RDTSCP are timing sensitive. */
687	bool fIgnoreRaxRdx;
688	/** Indicates that a MOVS instruction with overlapping source and destination
689	* was executed, causing the memory write records to be incorrrect. */
690	bool fOverlappingMovs;
691	/** Set if there are problematic memory accesses (MMIO, write monitored, ++). */
692	bool fProblematicMemory;
693	/** This is used to communicate a CPL changed caused by IEMInjectTrap that
694	* CPUM doesn't yet reflect. */
695	uint8_t uInjectCpl;
696	/** To prevent EMR3HmSingleInstruction from triggering endless recursion via
697	* emR3ExecuteInstruction and iemExecVerificationModeCheck. */
698	uint8_t cVerifyDepth;
699	bool afAlignment7[2];
700	/** Mask of undefined eflags.
701	* The verifier will any difference in these flags. */
702	uint32_t fUndefinedEFlags;
703	/** The CS of the instruction being interpreted. */
704	RTSEL uOldCs;
705	/** The RIP of the instruction being interpreted. */
706	uint64_t uOldRip;
707	/** The physical address corresponding to abOpcodes[0]. */
708	RTGCPHYS GCPhysOpcodes;
709	#endif
710	/** @} */
711
712	/** @name Target CPU information.
713	* @{ */
714	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
715	/** The target CPU. */
716	uint32_t uTargetCpu;
717	#else
718	uint32_t u32TargetCpuPadding;
719	#endif
720	/** The CPU vendor. */
721	CPUMCPUVENDOR enmCpuVendor;
722	/** @} */
723
724	/** @name Host CPU information.
725	* @{ */
726	/** The CPU vendor. */
727	CPUMCPUVENDOR enmHostCpuVendor;
728	/** @} */
729
730	uint32_t au32Alignment8[HC_ARCH_BITS == 64 ? 4 + 8 : 4]; /*< Alignment padding. /
731
732	/** Data TLB.
733	* @remarks Must be 64-byte aligned. */
734	IEMTLB DataTlb;
735	/** Instruction TLB.
736	* @remarks Must be 64-byte aligned. */
737	IEMTLB CodeTlb;
738
739	/** Pointer to the CPU context - ring-3 context.
740	* @todo put inside IEM_VERIFICATION_MODE_FULL++. */
741	R3PTRTYPE(PCPUMCTX) pCtxR3;
742	/** Pointer to the CPU context - ring-0 context. */
743	R0PTRTYPE(PCPUMCTX) pCtxR0;
744	/** Pointer to the CPU context - raw-mode context. */
745	RCPTRTYPE(PCPUMCTX) pCtxRC;
746
747	/** Pointer to instruction statistics for raw-mode context (same as R0). */
748	RCPTRTYPE(PIEMINSTRSTATS) pStatsRC;
749	/** Pointer to instruction statistics for ring-0 context (same as RC). */
750	R0PTRTYPE(PIEMINSTRSTATS) pStatsR0;
751	/** Pointer to instruction statistics for non-ring-3 code. */
752	R3PTRTYPE(PIEMINSTRSTATS) pStatsCCR3;
753	/** Pointer to instruction statistics for ring-3 context. */
754	R3PTRTYPE(PIEMINSTRSTATS) pStatsR3;
755
756	#ifdef IEM_VERIFICATION_MODE_FULL
757	/** The event verification records for what IEM did (LIFO). */
758	R3PTRTYPE(PIEMVERIFYEVTREC) pIemEvtRecHead;
759	/** Insertion point for pIemEvtRecHead. */
760	R3PTRTYPE(PIEMVERIFYEVTREC *) ppIemEvtRecNext;
761	/** The event verification records for what the other party did (FIFO). */
762	R3PTRTYPE(PIEMVERIFYEVTREC) pOtherEvtRecHead;
763	/** Insertion point for pOtherEvtRecHead. */
764	R3PTRTYPE(PIEMVERIFYEVTREC *) ppOtherEvtRecNext;
765	/** List of free event records. */
766	R3PTRTYPE(PIEMVERIFYEVTREC) pFreeEvtRec;
767	#endif
768	} IEMCPU;
769	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
770	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
771	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
772	/** Pointer to the per-CPU IEM state. */
773	typedef IEMCPU *PIEMCPU;
774	/** Pointer to the const per-CPU IEM state. */
775	typedef IEMCPU const *PCIEMCPU;
776
777
778	/** @def IEM_GET_CTX
779	* Gets the guest CPU context for the calling EMT.
780	* @returns PCPUMCTX
781	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
782	*/
783	#if !defined(IEM_VERIFICATION_MODE_FULL) && !defined(IEM_VERIFICATION_MODE) \
784	&& !defined(IEM_VERIFICATION_MODE_MINIMAL) && defined(VMCPU_INCL_CPUM_GST_CTX)
785	# define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
786	#else
787	# define IEM_GET_CTX(a_pVCpu) ((a_pVCpu)->iem.s.CTX_SUFF(pCtx))
788	#endif
789
790	/** Gets the current IEMTARGETCPU value.
791	* @returns IEMTARGETCPU value.
792	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
793	*/
794	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
795	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
796	#else
797	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
798	#endif
799
800	/** @def Gets the instruction length. */
801	#ifdef IEM_WITH_CODE_TLB
802	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
803	#else
804	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
805	#endif
806
807
808	/** @name IEM_ACCESS_XXX - Access details.
809	* @{ */
810	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
811	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
812	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
813	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
814	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
815	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
816	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
817	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
818	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
819	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
820	/** The writes are partial, so if initialize the bounce buffer with the
821	* orignal RAM content. */
822	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
823	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
824	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
825	/** Bounce buffer with ring-3 write pending, first page. */
826	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
827	/** Bounce buffer with ring-3 write pending, second page. */
828	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
829	/** Valid bit mask. */
830	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00000fff)
831	/** Read+write data alias. */
832	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
833	/** Write data alias. */
834	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
835	/** Read data alias. */
836	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
837	/** Instruction fetch alias. */
838	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
839	/** Stack write alias. */
840	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
841	/** Stack read alias. */
842	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
843	/** Stack read+write alias. */
844	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
845	/** Read system table alias. */
846	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
847	/** Read+write system table alias. */
848	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
849	/** @} */
850
851	/** @name Prefix constants (IEMCPU::fPrefixes)
852	* @{ */
853	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
854	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
855	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
856	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
857	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
858	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
859	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
860
861	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
862	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
863	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
864
865	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
866	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
867	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
868
869	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
870	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
871	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
872	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
873	/** Mask with all the REX prefix flags.
874	* This is generally for use when needing to undo the REX prefixes when they
875	* are followed legacy prefixes and therefore does not immediately preceed
876	* the first opcode byte.
877	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
878	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
879
880	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
881	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
882	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
883	/** @} */
884
885	/** @name IEMOPFORM_XXX - Opcode forms
886	* @note These are ORed together with IEMOPHINT_XXX.
887	* @{ */
888	/** ModR/M: reg, r/m */
889	#define IEMOPFORM_RM 0
890	/** ModR/M: reg, r/m (register) */
891	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
892	/** ModR/M: reg, r/m (memory) */
893	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
894	/** ModR/M: r/m, reg */
895	#define IEMOPFORM_MR 1
896	/** ModR/M: r/m (register), reg */
897	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
898	/** ModR/M: r/m (memory), reg */
899	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
900	/** ModR/M: r/m only */
901	#define IEMOPFORM_M 2
902	/** ModR/M: r/m only (register). */
903	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
904	/** ModR/M: r/m only (memory). */
905	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
906	/** ModR/M: reg only */
907	#define IEMOPFORM_R 3
908
909	/** VEX+ModR/M: reg, r/m */
910	#define IEMOPFORM_VEX_RM 4
911	/** VEX+ModR/M: reg, r/m (register) */
912	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
913	/** VEX+ModR/M: reg, r/m (memory) */
914	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
915	#define IEMOPFORM_VEX_XM IEMOPFORM_VEX_RM_MEM
916	/** VEX+ModR/M: r/m, reg */
917	#define IEMOPFORM_VEX_MR 5
918	/** VEX+ModR/M: r/m (register), reg */
919	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
920	/** VEX+ModR/M: r/m (memory), reg */
921	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
922	/** VEX+ModR/M: r/m only */
923	#define IEMOPFORM_VEX_M 6
924	/** VEX+ModR/M: r/m only (register). */
925	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
926	/** VEX+ModR/M: r/m only (memory). */
927	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
928	/** VEX+ModR/M: reg only */
929	#define IEMOPFORM_VEX_R 7
930	/** VEX+ModR/M: reg, vvvv, r/m */
931	#define IEMOPFORM_VEX_RVM 8
932	/** VEX+ModR/M: r/m, vvvv, reg */
933	#define IEMOPFORM_VEX_MVR 9
934
935	/** Fixed register instruction, no R/M. */
936	#define IEMOPFORM_FIXED 16
937
938	/** The r/m is a register. */
939	#define IEMOPFORM_MOD3 RT_BIT_32(8)
940	/** The r/m is a memory access. */
941	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
942	/** @} */
943
944	/** @name IEMOPHINT_XXX - Additional Opcode Hints
945	* @note These are ORed together with IEMOPFORM_XXX.
946	* @{ */
947	/** Both the operand size prefixes are ignored. */
948	#define IEMOPHINT_IGNORES_OP_SIZE RT_BIT_32(10)
949	/** Allowed with the lock prefix. */
950	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
951	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
952	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
953	/** @} */
954
955	/**
956	* Possible hardware task switch sources.
957	*/
958	typedef enum IEMTASKSWITCH
959	{
960	/** Task switch caused by an interrupt/exception. */
961	IEMTASKSWITCH_INT_XCPT = 1,
962	/** Task switch caused by a far CALL. */
963	IEMTASKSWITCH_CALL,
964	/** Task switch caused by a far JMP. */
965	IEMTASKSWITCH_JUMP,
966	/** Task switch caused by an IRET. */
967	IEMTASKSWITCH_IRET
968	} IEMTASKSWITCH;
969	AssertCompileSize(IEMTASKSWITCH, 4);
970
971	/**
972	* Possible CrX load (write) sources.
973	*/
974	typedef enum IEMACCESSCRX
975	{
976	/** CrX access caused by 'mov crX' instruction. */
977	IEMACCESSCRX_MOV_CRX,
978	/** CrX (CR0) write caused by 'lmsw' instruction. */
979	IEMACCESSCRX_LMSW,
980	/** CrX (CR0) write caused by 'clts' instruction. */
981	IEMACCESSCRX_CLTS,
982	/** CrX (CR0) read caused by 'smsw' instruction. */
983	IEMACCESSCRX_SMSW
984	} IEMACCESSCRX;
985
986	/**
987	* Tests if verification mode is enabled.
988	*
989	* This expands to @c false when IEM_VERIFICATION_MODE is not defined and
990	* should therefore cause the compiler to eliminate the verification branch
991	* of an if statement. */
992	#ifdef IEM_VERIFICATION_MODE_FULL
993	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
994	#elif defined(IEM_VERIFICATION_MODE_MINIMAL)
995	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (true)
996	#else
997	# define IEM_VERIFICATION_ENABLED(a_pVCpu) (false)
998	#endif
999
1000	/**
1001	* Tests if full verification mode is enabled.
1002	*
1003	* This expands to @c false when IEM_VERIFICATION_MODE_FULL is not defined and
1004	* should therefore cause the compiler to eliminate the verification branch
1005	* of an if statement. */
1006	#ifdef IEM_VERIFICATION_MODE_FULL
1007	# define IEM_FULL_VERIFICATION_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
1008	#else
1009	# define IEM_FULL_VERIFICATION_ENABLED(a_pVCpu) (false)
1010	#endif
1011
1012	/**
1013	* Tests if full verification mode is enabled again REM.
1014	*
1015	* This expands to @c false when IEM_VERIFICATION_MODE_FULL is not defined and
1016	* should therefore cause the compiler to eliminate the verification branch
1017	* of an if statement. */
1018	#ifdef IEM_VERIFICATION_MODE_FULL
1019	# ifdef IEM_VERIFICATION_MODE_FULL_HM
1020	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem && !HMIsEnabled((a_pVCpu)->CTX_SUFF(pVM)))
1021	# else
1022	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (!(a_pVCpu)->iem.s.fNoRem)
1023	# endif
1024	#else
1025	# define IEM_FULL_VERIFICATION_REM_ENABLED(a_pVCpu) (false)
1026	#endif
1027
1028	/** @def IEM_VERIFICATION_MODE
1029	* Indicates that one of the verfication modes are enabled.
1030	*/
1031	#if (defined(IEM_VERIFICATION_MODE_FULL) \|\| defined(IEM_VERIFICATION_MODE_MINIMAL)) && !defined(IEM_VERIFICATION_MODE) \
1032	\|\| defined(DOXYGEN_RUNNING)
1033	# define IEM_VERIFICATION_MODE
1034	#endif
1035
1036	/**
1037	* Indicates to the verifier that the given flag set is undefined.
1038	*
1039	* Can be invoked again to add more flags.
1040	*
1041	* This is a NOOP if the verifier isn't compiled in.
1042	*/
1043	#ifdef IEM_VERIFICATION_MODE_FULL
1044	# define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { pVCpu->iem.s.fUndefinedEFlags \|= (a_fEfl); } while (0)
1045	#else
1046	# define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1047	#endif
1048
1049
1050	/** @def IEM_DECL_IMPL_TYPE
1051	* For typedef'ing an instruction implementation function.
1052	*
1053	* @param a_RetType The return type.
1054	* @param a_Name The name of the type.
1055	* @param a_ArgList The argument list enclosed in parentheses.
1056	*/
1057
1058	/** @def IEM_DECL_IMPL_DEF
1059	* For defining an instruction implementation function.
1060	*
1061	* @param a_RetType The return type.
1062	* @param a_Name The name of the type.
1063	* @param a_ArgList The argument list enclosed in parentheses.
1064	*/
1065
1066	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1067	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1068	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1069	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1070	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1071
1072	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1073	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1074	a_RetType (__fastcall a_Name) a_ArgList
1075	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1076	a_RetType __fastcall a_Name a_ArgList
1077
1078	#else
1079	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1080	a_RetType (VBOXCALL a_Name) a_ArgList
1081	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1082	a_RetType VBOXCALL a_Name a_ArgList
1083
1084	#endif
1085
1086	/** @name Arithmetic assignment operations on bytes (binary).
1087	* @{ */
1088	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1089	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1090	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1091	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1092	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1093	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1094	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1095	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1096	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1097	/** @} */
1098
1099	/** @name Arithmetic assignment operations on words (binary).
1100	* @{ */
1101	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1102	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1103	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1104	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1105	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1106	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1107	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1108	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1109	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1110	/** @} */
1111
1112	/** @name Arithmetic assignment operations on double words (binary).
1113	* @{ */
1114	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1115	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1116	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1117	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1118	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1119	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1120	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1121	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1122	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1123	/** @} */
1124
1125	/** @name Arithmetic assignment operations on quad words (binary).
1126	* @{ */
1127	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1128	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1129	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1130	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1131	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1132	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1133	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1134	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1135	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1136	/** @} */
1137
1138	/** @name Compare operations (thrown in with the binary ops).
1139	* @{ */
1140	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1141	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1142	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1143	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1144	/** @} */
1145
1146	/** @name Test operations (thrown in with the binary ops).
1147	* @{ */
1148	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1149	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1150	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1151	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1152	/** @} */
1153
1154	/** @name Bit operations operations (thrown in with the binary ops).
1155	* @{ */
1156	FNIEMAIMPLBINU16 iemAImpl_bt_u16, iemAImpl_bt_u16_locked;
1157	FNIEMAIMPLBINU32 iemAImpl_bt_u32, iemAImpl_bt_u32_locked;
1158	FNIEMAIMPLBINU64 iemAImpl_bt_u64, iemAImpl_bt_u64_locked;
1159	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1160	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1161	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1162	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1163	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1164	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1165	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1166	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1167	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1168	/** @} */
1169
1170	/** @name Exchange memory with register operations.
1171	* @{ */
1172	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8, (uint8_t pu8Mem, uint8_t pu8Reg));
1173	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16,(uint16_t pu16Mem, uint16_t pu16Reg));
1174	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32,(uint32_t pu32Mem, uint32_t pu32Reg));
1175	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64,(uint64_t pu64Mem, uint64_t pu64Reg));
1176	/** @} */
1177
1178	/** @name Exchange and add operations.
1179	* @{ */
1180	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1181	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1182	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1183	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1184	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1185	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1186	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1187	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1188	/** @} */
1189
1190	/** @name Compare and exchange.
1191	* @{ */
1192	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1193	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1194	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1195	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1196	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1197	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1198	#ifdef RT_ARCH_X86
1199	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1200	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1201	#else
1202	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1203	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1204	#endif
1205	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1206	uint32_t *pEFlags));
1207	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1208	uint32_t *pEFlags));
1209	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1210	uint32_t *pEFlags));
1211	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1212	uint32_t *pEFlags));
1213	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1214	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1215	/** @} */
1216
1217	/** @name Memory ordering
1218	* @{ */
1219	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1220	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1221	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1222	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1223	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1224	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1225	/** @} */
1226
1227	/** @name Double precision shifts
1228	* @{ */
1229	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1230	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1231	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1232	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1233	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1234	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1235	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16;
1236	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32;
1237	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64;
1238	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16;
1239	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32;
1240	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64;
1241	/** @} */
1242
1243
1244	/** @name Bit search operations (thrown in with the binary ops).
1245	* @{ */
1246	FNIEMAIMPLBINU16 iemAImpl_bsf_u16;
1247	FNIEMAIMPLBINU32 iemAImpl_bsf_u32;
1248	FNIEMAIMPLBINU64 iemAImpl_bsf_u64;
1249	FNIEMAIMPLBINU16 iemAImpl_bsr_u16;
1250	FNIEMAIMPLBINU32 iemAImpl_bsr_u32;
1251	FNIEMAIMPLBINU64 iemAImpl_bsr_u64;
1252	/** @} */
1253
1254	/** @name Signed multiplication operations (thrown in with the binary ops).
1255	* @{ */
1256	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16;
1257	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32;
1258	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64;
1259	/** @} */
1260
1261	/** @name Arithmetic assignment operations on bytes (unary).
1262	* @{ */
1263	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1264	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1265	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1266	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1267	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1268	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1269	/** @} */
1270
1271	/** @name Arithmetic assignment operations on words (unary).
1272	* @{ */
1273	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1274	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1275	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1276	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1277	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1278	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1279	/** @} */
1280
1281	/** @name Arithmetic assignment operations on double words (unary).
1282	* @{ */
1283	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1284	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1285	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1286	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1287	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1288	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1289	/** @} */
1290
1291	/** @name Arithmetic assignment operations on quad words (unary).
1292	* @{ */
1293	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1294	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1295	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1296	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1297	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1298	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1299	/** @} */
1300
1301
1302	/** @name Shift operations on bytes (Group 2).
1303	* @{ */
1304	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1305	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1306	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8;
1307	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8;
1308	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8;
1309	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8;
1310	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8;
1311	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8;
1312	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8;
1313	/** @} */
1314
1315	/** @name Shift operations on words (Group 2).
1316	* @{ */
1317	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1318	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1319	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16;
1320	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16;
1321	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16;
1322	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16;
1323	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16;
1324	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16;
1325	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16;
1326	/** @} */
1327
1328	/** @name Shift operations on double words (Group 2).
1329	* @{ */
1330	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1331	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1332	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32;
1333	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32;
1334	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32;
1335	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32;
1336	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32;
1337	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32;
1338	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32;
1339	/** @} */
1340
1341	/** @name Shift operations on words (Group 2).
1342	* @{ */
1343	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1344	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1345	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64;
1346	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64;
1347	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64;
1348	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64;
1349	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64;
1350	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64;
1351	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64;
1352	/** @} */
1353
1354	/** @name Multiplication and division operations.
1355	* @{ */
1356	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1357	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1358	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_imul_u8;
1359	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_idiv_u8;
1360
1361	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1362	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1363	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_imul_u16;
1364	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_idiv_u16;
1365
1366	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1367	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1368	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_imul_u32;
1369	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_idiv_u32;
1370
1371	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1372	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1373	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_imul_u64;
1374	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_idiv_u64;
1375	/** @} */
1376
1377	/** @name Byte Swap.
1378	* @{ */
1379	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1380	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1381	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1382	/** @} */
1383
1384	/** @name Misc.
1385	* @{ */
1386	FNIEMAIMPLBINU16 iemAImpl_arpl;
1387	/** @} */
1388
1389
1390	/** @name FPU operations taking a 32-bit float argument
1391	* @{ */
1392	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1393	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1394	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1395
1396	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1397	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1398	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1399
1400	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1401	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1402	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1403	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1404	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1405	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1406	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1407
1408	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1409	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1410	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1411	/** @} */
1412
1413	/** @name FPU operations taking a 64-bit float argument
1414	* @{ */
1415	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1416	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1417	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1418
1419	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1420	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1421	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1422	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1423	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1424	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1425
1426	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1427	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1428	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1429	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1430	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1431	/** @} */
1432
1433	/** @name FPU operations taking a 80-bit float argument
1434	* @{ */
1435	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1436	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1437	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1438	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1439	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1440	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1441	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1442	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1443	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1444	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1445	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1446	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1447
1448	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80;
1449	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80;
1450	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80;
1451
1452	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1453	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1454	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1455	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1456	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1457
1458	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1459	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1460	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1461	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1462	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1463
1464	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1465	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1466	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1467	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1468	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80;
1469	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1470	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1471	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80;
1472	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80;
1473
1474	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1475	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1476	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1477	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1478
1479	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1480	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1481	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1482	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1483	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1484	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1485	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1486	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1487	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1488
1489	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1490	PCRTFLOAT80U pr80Val));
1491	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1492	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80;
1493	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1494	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80;
1495
1496	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1497	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1498	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1499
1500	/** @} */
1501
1502	/** @name FPU operations taking a 16-bit signed integer argument
1503	* @{ */
1504	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1505	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1506	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1507
1508	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1509	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1510	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1511	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1512	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1513	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1514
1515	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1516	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1517
1518	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1519	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1520	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1521	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1522	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1523	/** @} */
1524
1525	/** @name FPU operations taking a 32-bit signed integer argument
1526	* @{ */
1527	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1528	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1529	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1530
1531	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1532	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1533	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1534	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1535	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1536	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1537
1538	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1539	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1540
1541	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1542	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1543	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1544	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1545	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1546	/** @} */
1547
1548	/** @name FPU operations taking a 64-bit signed integer argument
1549	* @{ */
1550	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1551	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1552	typedef FNIEMAIMPLFPUI64 *PFNIEMAIMPLFPUI64;
1553
1554	FNIEMAIMPLFPUI64 iemAImpl_fiadd_r80_by_i64;
1555	FNIEMAIMPLFPUI64 iemAImpl_fimul_r80_by_i64;
1556	FNIEMAIMPLFPUI64 iemAImpl_fisub_r80_by_i64;
1557	FNIEMAIMPLFPUI64 iemAImpl_fisubr_r80_by_i64;
1558	FNIEMAIMPLFPUI64 iemAImpl_fidiv_r80_by_i64;
1559	FNIEMAIMPLFPUI64 iemAImpl_fidivr_r80_by_i64;
1560
1561	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1562	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1563
1564	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1565	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1566	int64_t *pi64Val, PCRTFLOAT80U pr80Val));
1567	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1568	int64_t *pi32Val, PCRTFLOAT80U pr80Val));
1569	/** @} */
1570
1571
1572	/** Temporary type representing a 256-bit vector register. */
1573	typedef struct {uint64_t au64[4]; } IEMVMM256;
1574	/** Temporary type pointing to a 256-bit vector register. */
1575	typedef IEMVMM256 *PIEMVMM256;
1576	/** Temporary type pointing to a const 256-bit vector register. */
1577	typedef IEMVMM256 *PCIEMVMM256;
1578
1579
1580	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1581	* @{ */
1582	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1583	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1584	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1585	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1586	FNIEMAIMPLMEDIAF2U64 iemAImpl_pxor_u64, iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1587	FNIEMAIMPLMEDIAF2U128 iemAImpl_pxor_u128, iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1588	/** @} */
1589
1590	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1591	* @{ */
1592	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src));
1593	typedef FNIEMAIMPLMEDIAF1L1U64 *PFNIEMAIMPLMEDIAF1L1U64;
1594	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src));
1595	typedef FNIEMAIMPLMEDIAF1L1U128 *PFNIEMAIMPLMEDIAF1L1U128;
1596	FNIEMAIMPLMEDIAF1L1U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1597	FNIEMAIMPLMEDIAF1L1U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1598	/** @} */
1599
1600	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
1601	* @{ */
1602	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1603	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF1H1U64;
1604	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1605	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF1H1U128;
1606	FNIEMAIMPLMEDIAF1H1U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
1607	FNIEMAIMPLMEDIAF1H1U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
1608	/** @} */
1609
1610	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
1611	* @{ */
1612	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUF,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst,
1613	PCRTUINT128U pu128Src, uint8_t bEvil));
1614	typedef FNIEMAIMPLMEDIAPSHUF *PFNIEMAIMPLMEDIAPSHUF;
1615	FNIEMAIMPLMEDIAPSHUF iemAImpl_pshufhw, iemAImpl_pshuflw, iemAImpl_pshufd;
1616	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil));
1617	/** @} */
1618
1619	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
1620	* @{ */
1621	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1622	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src));
1623	/** @} */
1624
1625	/** @name Media (SSE/MMX/AVX) operation: Sort this later
1626	* @{ */
1627	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1628	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1629	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc));
1630	/** @} */
1631
1632
1633	/** @name Function tables.
1634	* @{
1635	*/
1636
1637	/**
1638	* Function table for a binary operator providing implementation based on
1639	* operand size.
1640	*/
1641	typedef struct IEMOPBINSIZES
1642	{
1643	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
1644	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
1645	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
1646	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
1647	} IEMOPBINSIZES;
1648	/** Pointer to a binary operator function table. */
1649	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
1650
1651
1652	/**
1653	* Function table for a unary operator providing implementation based on
1654	* operand size.
1655	*/
1656	typedef struct IEMOPUNARYSIZES
1657	{
1658	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
1659	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
1660	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
1661	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
1662	} IEMOPUNARYSIZES;
1663	/** Pointer to a unary operator function table. */
1664	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
1665
1666
1667	/**
1668	* Function table for a shift operator providing implementation based on
1669	* operand size.
1670	*/
1671	typedef struct IEMOPSHIFTSIZES
1672	{
1673	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
1674	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
1675	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
1676	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
1677	} IEMOPSHIFTSIZES;
1678	/** Pointer to a shift operator function table. */
1679	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
1680
1681
1682	/**
1683	* Function table for a multiplication or division operation.
1684	*/
1685	typedef struct IEMOPMULDIVSIZES
1686	{
1687	PFNIEMAIMPLMULDIVU8 pfnU8;
1688	PFNIEMAIMPLMULDIVU16 pfnU16;
1689	PFNIEMAIMPLMULDIVU32 pfnU32;
1690	PFNIEMAIMPLMULDIVU64 pfnU64;
1691	} IEMOPMULDIVSIZES;
1692	/** Pointer to a multiplication or division operation function table. */
1693	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
1694
1695
1696	/**
1697	* Function table for a double precision shift operator providing implementation
1698	* based on operand size.
1699	*/
1700	typedef struct IEMOPSHIFTDBLSIZES
1701	{
1702	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
1703	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
1704	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
1705	} IEMOPSHIFTDBLSIZES;
1706	/** Pointer to a double precision shift function table. */
1707	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
1708
1709
1710	/**
1711	* Function table for media instruction taking two full sized media registers,
1712	* optionally the 2nd being a memory reference (only modifying the first op.)
1713	*/
1714	typedef struct IEMOPMEDIAF2
1715	{
1716	PFNIEMAIMPLMEDIAF2U64 pfnU64;
1717	PFNIEMAIMPLMEDIAF2U128 pfnU128;
1718	} IEMOPMEDIAF2;
1719	/** Pointer to a media operation function table for full sized ops. */
1720	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
1721
1722	/**
1723	* Function table for media instruction taking taking one full and one lower
1724	* half media register.
1725	*/
1726	typedef struct IEMOPMEDIAF1L1
1727	{
1728	PFNIEMAIMPLMEDIAF1L1U64 pfnU64;
1729	PFNIEMAIMPLMEDIAF1L1U128 pfnU128;
1730	} IEMOPMEDIAF1L1;
1731	/** Pointer to a media operation function table for lowhalf+lowhalf -> full. */
1732	typedef IEMOPMEDIAF1L1 const *PCIEMOPMEDIAF1L1;
1733
1734	/**
1735	* Function table for media instruction taking taking one full and one high half
1736	* media register.
1737	*/
1738	typedef struct IEMOPMEDIAF1H1
1739	{
1740	PFNIEMAIMPLMEDIAF1H1U64 pfnU64;
1741	PFNIEMAIMPLMEDIAF1H1U128 pfnU128;
1742	} IEMOPMEDIAF1H1;
1743	/** Pointer to a media operation function table for hihalf+hihalf -> full. */
1744	typedef IEMOPMEDIAF1H1 const *PCIEMOPMEDIAF1H1;
1745
1746
1747	/** @} */
1748
1749
1750	/** @name C instruction implementations for anything slightly complicated.
1751	* @{ */
1752
1753	/**
1754	* For typedef'ing or declaring a C instruction implementation function taking
1755	* no extra arguments.
1756	*
1757	* @param a_Name The name of the type.
1758	*/
1759	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
1760	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1761	/**
1762	* For defining a C instruction implementation function taking no extra
1763	* arguments.
1764	*
1765	* @param a_Name The name of the function
1766	*/
1767	# define IEM_CIMPL_DEF_0(a_Name) \
1768	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1769	/**
1770	* For calling a C instruction implementation function taking no extra
1771	* arguments.
1772	*
1773	* This special call macro adds default arguments to the call and allow us to
1774	* change these later.
1775	*
1776	* @param a_fn The name of the function.
1777	*/
1778	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
1779
1780	/**
1781	* For typedef'ing or declaring a C instruction implementation function taking
1782	* one extra argument.
1783	*
1784	* @param a_Name The name of the type.
1785	* @param a_Type0 The argument type.
1786	* @param a_Arg0 The argument name.
1787	*/
1788	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
1789	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1790	/**
1791	* For defining a C instruction implementation function taking one extra
1792	* argument.
1793	*
1794	* @param a_Name The name of the function
1795	* @param a_Type0 The argument type.
1796	* @param a_Arg0 The argument name.
1797	*/
1798	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
1799	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1800	/**
1801	* For calling a C instruction implementation function taking one extra
1802	* argument.
1803	*
1804	* This special call macro adds default arguments to the call and allow us to
1805	* change these later.
1806	*
1807	* @param a_fn The name of the function.
1808	* @param a0 The name of the 1st argument.
1809	*/
1810	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
1811
1812	/**
1813	* For typedef'ing or declaring a C instruction implementation function taking
1814	* two extra arguments.
1815	*
1816	* @param a_Name The name of the type.
1817	* @param a_Type0 The type of the 1st argument
1818	* @param a_Arg0 The name of the 1st argument.
1819	* @param a_Type1 The type of the 2nd argument.
1820	* @param a_Arg1 The name of the 2nd argument.
1821	*/
1822	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1823	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1824	/**
1825	* For defining a C instruction implementation function taking two extra
1826	* arguments.
1827	*
1828	* @param a_Name The name of the function.
1829	* @param a_Type0 The type of the 1st argument
1830	* @param a_Arg0 The name of the 1st argument.
1831	* @param a_Type1 The type of the 2nd argument.
1832	* @param a_Arg1 The name of the 2nd argument.
1833	*/
1834	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1835	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1836	/**
1837	* For calling a C instruction implementation function taking two extra
1838	* arguments.
1839	*
1840	* This special call macro adds default arguments to the call and allow us to
1841	* change these later.
1842	*
1843	* @param a_fn The name of the function.
1844	* @param a0 The name of the 1st argument.
1845	* @param a1 The name of the 2nd argument.
1846	*/
1847	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
1848
1849	/**
1850	* For typedef'ing or declaring a C instruction implementation function taking
1851	* three extra arguments.
1852	*
1853	* @param a_Name The name of the type.
1854	* @param a_Type0 The type of the 1st argument
1855	* @param a_Arg0 The name of the 1st argument.
1856	* @param a_Type1 The type of the 2nd argument.
1857	* @param a_Arg1 The name of the 2nd argument.
1858	* @param a_Type2 The type of the 3rd argument.
1859	* @param a_Arg2 The name of the 3rd argument.
1860	*/
1861	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1862	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1863	/**
1864	* For defining a C instruction implementation function taking three extra
1865	* arguments.
1866	*
1867	* @param a_Name The name of the function.
1868	* @param a_Type0 The type of the 1st argument
1869	* @param a_Arg0 The name of the 1st argument.
1870	* @param a_Type1 The type of the 2nd argument.
1871	* @param a_Arg1 The name of the 2nd argument.
1872	* @param a_Type2 The type of the 3rd argument.
1873	* @param a_Arg2 The name of the 3rd argument.
1874	*/
1875	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1876	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1877	/**
1878	* For calling a C instruction implementation function taking three extra
1879	* arguments.
1880	*
1881	* This special call macro adds default arguments to the call and allow us to
1882	* change these later.
1883	*
1884	* @param a_fn The name of the function.
1885	* @param a0 The name of the 1st argument.
1886	* @param a1 The name of the 2nd argument.
1887	* @param a2 The name of the 3rd argument.
1888	*/
1889	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
1890
1891
1892	/**
1893	* For typedef'ing or declaring a C instruction implementation function taking
1894	* four extra arguments.
1895	*
1896	* @param a_Name The name of the type.
1897	* @param a_Type0 The type of the 1st argument
1898	* @param a_Arg0 The name of the 1st argument.
1899	* @param a_Type1 The type of the 2nd argument.
1900	* @param a_Arg1 The name of the 2nd argument.
1901	* @param a_Type2 The type of the 3rd argument.
1902	* @param a_Arg2 The name of the 3rd argument.
1903	* @param a_Type3 The type of the 4th argument.
1904	* @param a_Arg3 The name of the 4th argument.
1905	*/
1906	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1907	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
1908	/**
1909	* For defining a C instruction implementation function taking four extra
1910	* arguments.
1911	*
1912	* @param a_Name The name of the function.
1913	* @param a_Type0 The type of the 1st argument
1914	* @param a_Arg0 The name of the 1st argument.
1915	* @param a_Type1 The type of the 2nd argument.
1916	* @param a_Arg1 The name of the 2nd argument.
1917	* @param a_Type2 The type of the 3rd argument.
1918	* @param a_Arg2 The name of the 3rd argument.
1919	* @param a_Type3 The type of the 4th argument.
1920	* @param a_Arg3 The name of the 4th argument.
1921	*/
1922	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1923	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1924	a_Type2 a_Arg2, a_Type3 a_Arg3))
1925	/**
1926	* For calling a C instruction implementation function taking four extra
1927	* arguments.
1928	*
1929	* This special call macro adds default arguments to the call and allow us to
1930	* change these later.
1931	*
1932	* @param a_fn The name of the function.
1933	* @param a0 The name of the 1st argument.
1934	* @param a1 The name of the 2nd argument.
1935	* @param a2 The name of the 3rd argument.
1936	* @param a3 The name of the 4th argument.
1937	*/
1938	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
1939
1940
1941	/**
1942	* For typedef'ing or declaring a C instruction implementation function taking
1943	* five extra arguments.
1944	*
1945	* @param a_Name The name of the type.
1946	* @param a_Type0 The type of the 1st argument
1947	* @param a_Arg0 The name of the 1st argument.
1948	* @param a_Type1 The type of the 2nd argument.
1949	* @param a_Arg1 The name of the 2nd argument.
1950	* @param a_Type2 The type of the 3rd argument.
1951	* @param a_Arg2 The name of the 3rd argument.
1952	* @param a_Type3 The type of the 4th argument.
1953	* @param a_Arg3 The name of the 4th argument.
1954	* @param a_Type4 The type of the 5th argument.
1955	* @param a_Arg4 The name of the 5th argument.
1956	*/
1957	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1958	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1959	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1960	a_Type3 a_Arg3, a_Type4 a_Arg4))
1961	/**
1962	* For defining a C instruction implementation function taking five extra
1963	* arguments.
1964	*
1965	* @param a_Name The name of the function.
1966	* @param a_Type0 The type of the 1st argument
1967	* @param a_Arg0 The name of the 1st argument.
1968	* @param a_Type1 The type of the 2nd argument.
1969	* @param a_Arg1 The name of the 2nd argument.
1970	* @param a_Type2 The type of the 3rd argument.
1971	* @param a_Arg2 The name of the 3rd argument.
1972	* @param a_Type3 The type of the 4th argument.
1973	* @param a_Arg3 The name of the 4th argument.
1974	* @param a_Type4 The type of the 5th argument.
1975	* @param a_Arg4 The name of the 5th argument.
1976	*/
1977	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1978	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1979	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1980	a_Type3 a_Arg3, a_Type4 a_Arg4))
1981	/**
1982	* For calling a C instruction implementation function taking five extra
1983	* arguments.
1984	*
1985	* This special call macro adds default arguments to the call and allow us to
1986	* change these later.
1987	*
1988	* @param a_fn The name of the function.
1989	* @param a0 The name of the 1st argument.
1990	* @param a1 The name of the 2nd argument.
1991	* @param a2 The name of the 3rd argument.
1992	* @param a3 The name of the 4th argument.
1993	* @param a4 The name of the 5th argument.
1994	*/
1995	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
1996
1997	/** @} */
1998
1999
2000	/** @} */
2001
2002	RT_C_DECLS_END
2003
2004	#endif
2005

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 66901

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