IEMInternal.h@ 73016

Last change on this file since 73016 was 72866, checked in by vboxsync, 6 years ago
IEM,CPUM: Can use LogRel in ring-0 too now and have it go to VBox.log.
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1	/* $Id: IEMInternal.h 72866 2018-07-04 10:42:51Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___IEMInternal_h
19	#define ___IEMInternal_h
20
21	#include <VBox/vmm/cpum.h>
22	#include <VBox/vmm/iem.h>
23	#include <VBox/vmm/stam.h>
24	#include <VBox/param.h>
25
26	#include <setjmp.h>
27
28
29	RT_C_DECLS_BEGIN
30
31
32	/** @defgroup grp_iem_int Internals
33	* @ingroup grp_iem
34	* @internal
35	* @{
36	*/
37
38	/** For expanding symbol in slickedit and other products tagging and
39	* crossreferencing IEM symbols. */
40	#ifndef IEM_STATIC
41	# define IEM_STATIC static
42	#endif
43
44	/** @def IEM_WITH_3DNOW
45	* Includes the 3DNow decoding. */
46	#define IEM_WITH_3DNOW
47
48	/** @def IEM_WITH_THREE_0F_38
49	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
50	#define IEM_WITH_THREE_0F_38
51
52	/** @def IEM_WITH_THREE_0F_3A
53	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
54	#define IEM_WITH_THREE_0F_3A
55
56	/** @def IEM_WITH_VEX
57	* Includes the VEX decoding. */
58	#define IEM_WITH_VEX
59
60	/** @def IEM_CFG_TARGET_CPU
61	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
62	*
63	* By default we allow this to be configured by the user via the
64	* CPUM/GuestCpuName config string, but this comes at a slight cost during
65	* decoding. So, for applications of this code where there is no need to
66	* be dynamic wrt target CPU, just modify this define.
67	*/
68	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
69	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
70	#endif
71
72
73	//#define IEM_WITH_CODE_TLB// - work in progress
74
75
76	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
77	/** Instruction statistics. */
78	typedef struct IEMINSTRSTATS
79	{
80	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
81	# include "IEMInstructionStatisticsTmpl.h"
82	# undef IEM_DO_INSTR_STAT
83	} IEMINSTRSTATS;
84	#else
85	struct IEMINSTRSTATS;
86	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
87	#endif
88	/** Pointer to IEM instruction statistics. */
89	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
90
91	/** Finish and move to types.h */
92	typedef union
93	{
94	uint32_t u32;
95	} RTFLOAT32U;
96	typedef RTFLOAT32U *PRTFLOAT32U;
97	typedef RTFLOAT32U const *PCRTFLOAT32U;
98
99
100	/**
101	* Extended operand mode that includes a representation of 8-bit.
102	*
103	* This is used for packing down modes when invoking some C instruction
104	* implementations.
105	*/
106	typedef enum IEMMODEX
107	{
108	IEMMODEX_16BIT = IEMMODE_16BIT,
109	IEMMODEX_32BIT = IEMMODE_32BIT,
110	IEMMODEX_64BIT = IEMMODE_64BIT,
111	IEMMODEX_8BIT
112	} IEMMODEX;
113	AssertCompileSize(IEMMODEX, 4);
114
115
116	/**
117	* Branch types.
118	*/
119	typedef enum IEMBRANCH
120	{
121	IEMBRANCH_JUMP = 1,
122	IEMBRANCH_CALL,
123	IEMBRANCH_TRAP,
124	IEMBRANCH_SOFTWARE_INT,
125	IEMBRANCH_HARDWARE_INT
126	} IEMBRANCH;
127	AssertCompileSize(IEMBRANCH, 4);
128
129
130	/**
131	* INT instruction types.
132	*/
133	typedef enum IEMINT
134	{
135	/** INT n instruction (opcode 0xcd imm). */
136	IEMINT_INTN = 0,
137	/** Single byte INT3 instruction (opcode 0xcc). */
138	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
139	/** Single byte INTO instruction (opcode 0xce). */
140	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
141	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
142	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
143	} IEMINT;
144	AssertCompileSize(IEMINT, 4);
145
146
147	/**
148	* A FPU result.
149	*/
150	typedef struct IEMFPURESULT
151	{
152	/** The output value. */
153	RTFLOAT80U r80Result;
154	/** The output status. */
155	uint16_t FSW;
156	} IEMFPURESULT;
157	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
158	/** Pointer to a FPU result. */
159	typedef IEMFPURESULT *PIEMFPURESULT;
160	/** Pointer to a const FPU result. */
161	typedef IEMFPURESULT const *PCIEMFPURESULT;
162
163
164	/**
165	* A FPU result consisting of two output values and FSW.
166	*/
167	typedef struct IEMFPURESULTTWO
168	{
169	/** The first output value. */
170	RTFLOAT80U r80Result1;
171	/** The output status. */
172	uint16_t FSW;
173	/** The second output value. */
174	RTFLOAT80U r80Result2;
175	} IEMFPURESULTTWO;
176	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
177	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
178	/** Pointer to a FPU result consisting of two output values and FSW. */
179	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
180	/** Pointer to a const FPU result consisting of two output values and FSW. */
181	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
182
183
184	/**
185	* IEM TLB entry.
186	*
187	* Lookup assembly:
188	* @code{.asm}
189	; Calculate tag.
190	mov rax, [VA]
191	shl rax, 16
192	shr rax, 16 + X86_PAGE_SHIFT
193	or rax, [uTlbRevision]
194
195	; Do indexing.
196	movzx ecx, al
197	lea rcx, [pTlbEntries + rcx]
198
199	; Check tag.
200	cmp [rcx + IEMTLBENTRY.uTag], rax
201	jne .TlbMiss
202
203	; Check access.
204	movsx rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
205	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
206	cmp rax, [uTlbPhysRev]
207	jne .TlbMiss
208
209	; Calc address and we're done.
210	mov eax, X86_PAGE_OFFSET_MASK
211	and eax, [VA]
212	or rax, [rcx + IEMTLBENTRY.pMappingR3]
213	%ifdef VBOX_WITH_STATISTICS
214	inc qword [cTlbHits]
215	%endif
216	jmp .Done
217
218	.TlbMiss:
219	mov r8d, ACCESS_FLAGS
220	mov rdx, [VA]
221	mov rcx, [pVCpu]
222	call iemTlbTypeMiss
223	.Done:
224
225	@endcode
226	*
227	*/
228	typedef struct IEMTLBENTRY
229	{
230	/** The TLB entry tag.
231	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits.
232	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
233	*
234	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
235	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
236	* revision wraps around though, the tags needs to be zeroed.
237	*
238	* @note Try use SHRD instruction? After seeing
239	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
240	*/
241	uint64_t uTag;
242	/** Access flags and physical TLB revision.
243	*
244	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
245	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
246	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
247	* - Bit 3 - pgm phys/virt - not directly writable.
248	* - Bit 4 - pgm phys page - not directly readable.
249	* - Bit 5 - currently unused.
250	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
251	* - Bit 7 - tlb entry - pMappingR3 member not valid.
252	* - Bits 63 thru 8 are used for the physical TLB revision number.
253	*
254	* We're using complemented bit meanings here because it makes it easy to check
255	* whether special action is required. For instance a user mode write access
256	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
257	* non-zero result would mean special handling needed because either it wasn't
258	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
259	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
260	* need to check any PTE flag.
261	*/
262	uint64_t fFlagsAndPhysRev;
263	/** The guest physical page address. */
264	uint64_t GCPhys;
265	/** Pointer to the ring-3 mapping (possibly also valid in ring-0). */
266	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
267	R3PTRTYPE(uint8_t *) pbMappingR3;
268	#else
269	R3R0PTRTYPE(uint8_t *) pbMappingR3;
270	#endif
271	#if HC_ARCH_BITS == 32
272	uint32_t u32Padding1;
273	#endif
274	} IEMTLBENTRY;
275	AssertCompileSize(IEMTLBENTRY, 32);
276	/** Pointer to an IEM TLB entry. */
277	typedef IEMTLBENTRY *PIEMTLBENTRY;
278
279	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
280	* @{ */
281	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
282	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
283	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
284	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
285	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
286	#define IEMTLBE_F_PATCH_CODE RT_BIT_64(5) /*< Code TLB: Patch code (PATM). /
287	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
288	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
289	#define IEMTLBE_F_PHYS_REV UINT64_C(0xffffffffffffff00) /*< Physical revision mask. /
290	/** @} */
291
292
293	/**
294	* An IEM TLB.
295	*
296	* We've got two of these, one for data and one for instructions.
297	*/
298	typedef struct IEMTLB
299	{
300	/** The TLB entries.
301	* We've choosen 256 because that way we can obtain the result directly from a
302	* 8-bit register without an additional AND instruction. */
303	IEMTLBENTRY aEntries[256];
304	/** The TLB revision.
305	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
306	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
307	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
308	* (The revision zero indicates an invalid TLB entry.)
309	*
310	* The initial value is choosen to cause an early wraparound. */
311	uint64_t uTlbRevision;
312	/** The TLB physical address revision - shadow of PGM variable.
313	*
314	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
315	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
316	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
317	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
318	*
319	* The initial value is choosen to cause an early wraparound. */
320	uint64_t volatile uTlbPhysRev;
321
322	/* Statistics: */
323
324	/** TLB hits (VBOX_WITH_STATISTICS only). */
325	uint64_t cTlbHits;
326	/** TLB misses. */
327	uint32_t cTlbMisses;
328	/** Slow read path. */
329	uint32_t cTlbSlowReadPath;
330	#if 0
331	/** TLB misses because of tag mismatch. */
332	uint32_t cTlbMissesTag;
333	/** TLB misses because of virtual access violation. */
334	uint32_t cTlbMissesVirtAccess;
335	/** TLB misses because of dirty bit. */
336	uint32_t cTlbMissesDirty;
337	/** TLB misses because of MMIO */
338	uint32_t cTlbMissesMmio;
339	/** TLB misses because of write access handlers. */
340	uint32_t cTlbMissesWriteHandler;
341	/** TLB misses because no r3(/r0) mapping. */
342	uint32_t cTlbMissesMapping;
343	#endif
344	/** Alignment padding. */
345	uint32_t au32Padding[3+5];
346	} IEMTLB;
347	AssertCompileSizeAlignment(IEMTLB, 64);
348	/** IEMTLB::uTlbRevision increment. */
349	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
350	/** IEMTLB::uTlbPhysRev increment. */
351	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(8)
352
353
354	/**
355	* The per-CPU IEM state.
356	*/
357	typedef struct IEMCPU
358	{
359	/** Info status code that needs to be propagated to the IEM caller.
360	* This cannot be passed internally, as it would complicate all success
361	* checks within the interpreter making the code larger and almost impossible
362	* to get right. Instead, we'll store status codes to pass on here. Each
363	* source of these codes will perform appropriate sanity checks. */
364	int32_t rcPassUp; /* 0x00 */
365
366	/** The current CPU execution mode (CS). */
367	IEMMODE enmCpuMode; /* 0x04 */
368	/** The CPL. */
369	uint8_t uCpl; /* 0x05 */
370
371	/** Whether to bypass access handlers or not. */
372	bool fBypassHandlers; /* 0x06 */
373	/** Indicates that we're interpreting patch code - RC only! */
374	bool fInPatchCode; /* 0x07 */
375
376	/** @name Decoder state.
377	* @{ */
378	#ifdef IEM_WITH_CODE_TLB
379	/** The offset of the next instruction byte. */
380	uint32_t offInstrNextByte; /* 0x08 */
381	/** The number of bytes available at pbInstrBuf for the current instruction.
382	* This takes the max opcode length into account so that doesn't need to be
383	* checked separately. */
384	uint32_t cbInstrBuf; /* 0x0c */
385	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
386	* This can be NULL if the page isn't mappable for some reason, in which
387	* case we'll do fallback stuff.
388	*
389	* If we're executing an instruction from a user specified buffer,
390	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
391	* aligned pointer but pointer to the user data.
392	*
393	* For instructions crossing pages, this will start on the first page and be
394	* advanced to the next page by the time we've decoded the instruction. This
395	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
396	*/
397	uint8_t const pbInstrBuf; / 0x10 */
398	# if ARCH_BITS == 32
399	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
400	# endif
401	/** The program counter corresponding to pbInstrBuf.
402	* This is set to a non-canonical address when we need to invalidate it. */
403	uint64_t uInstrBufPc; /* 0x18 */
404	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
405	* This takes the CS segment limit into account. */
406	uint16_t cbInstrBufTotal; /* 0x20 */
407	/** Offset into pbInstrBuf of the first byte of the current instruction.
408	* Can be negative to efficiently handle cross page instructions. */
409	int16_t offCurInstrStart; /* 0x22 */
410
411	/** The prefix mask (IEM_OP_PRF_XXX). */
412	uint32_t fPrefixes; /* 0x24 */
413	/** The extra REX ModR/M register field bit (REX.R << 3). */
414	uint8_t uRexReg; /* 0x28 */
415	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
416	* (REX.B << 3). */
417	uint8_t uRexB; /* 0x29 */
418	/** The extra REX SIB index field bit (REX.X << 3). */
419	uint8_t uRexIndex; /* 0x2a */
420
421	/** The effective segment register (X86_SREG_XXX). */
422	uint8_t iEffSeg; /* 0x2b */
423
424	#else
425	/** The size of what has currently been fetched into abOpcode. */
426	uint8_t cbOpcode; /* 0x08 */
427	/** The current offset into abOpcode. */
428	uint8_t offOpcode; /* 0x09 */
429
430	/** The effective segment register (X86_SREG_XXX). */
431	uint8_t iEffSeg; /* 0x0a */
432
433	/** The extra REX ModR/M register field bit (REX.R << 3). */
434	uint8_t uRexReg; /* 0x0b */
435	/** The prefix mask (IEM_OP_PRF_XXX). */
436	uint32_t fPrefixes; /* 0x0c */
437	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
438	* (REX.B << 3). */
439	uint8_t uRexB; /* 0x10 */
440	/** The extra REX SIB index field bit (REX.X << 3). */
441	uint8_t uRexIndex; /* 0x11 */
442
443	#endif
444
445	/** The effective operand mode. */
446	IEMMODE enmEffOpSize; /* 0x2c, 0x12 */
447	/** The default addressing mode. */
448	IEMMODE enmDefAddrMode; /* 0x2d, 0x13 */
449	/** The effective addressing mode. */
450	IEMMODE enmEffAddrMode; /* 0x2e, 0x14 */
451	/** The default operand mode. */
452	IEMMODE enmDefOpSize; /* 0x2f, 0x15 */
453
454	/** Prefix index (VEX.pp) for two byte and three byte tables. */
455	uint8_t idxPrefix; /* 0x30, 0x16 */
456	/** 3rd VEX/EVEX/XOP register.
457	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
458	uint8_t uVex3rdReg; /* 0x31, 0x17 */
459	/** The VEX/EVEX/XOP length field. */
460	uint8_t uVexLength; /* 0x32, 0x18 */
461	/** Additional EVEX stuff. */
462	uint8_t fEvexStuff; /* 0x33, 0x19 */
463
464	/** The FPU opcode (FOP). */
465	uint16_t uFpuOpcode; /* 0x34, 0x1a */
466
467	/** Explicit alignment padding. */
468	#ifdef IEM_WITH_CODE_TLB
469	uint8_t abAlignment2a[2]; /* 0x36 */
470	#endif
471
472	/** The opcode bytes. */
473	uint8_t abOpcode[15]; /* 0x48, 0x1c */
474	/** Explicit alignment padding. */
475	#ifdef IEM_WITH_CODE_TLB
476	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
477	#else
478	uint8_t abAlignment2c[0x48 - 0x2b]; /* 0x2b */
479	#endif
480	/** @} */
481
482
483	/** The flags of the current exception / interrupt. */
484	uint32_t fCurXcpt; /* 0x48, 0x48 */
485	/** The current exception / interrupt. */
486	uint8_t uCurXcpt;
487	/** Exception / interrupt recursion depth. */
488	int8_t cXcptRecursions;
489
490	/** The number of active guest memory mappings. */
491	uint8_t cActiveMappings;
492	/** The next unused mapping index. */
493	uint8_t iNextMapping;
494	/** Records for tracking guest memory mappings. */
495	struct
496	{
497	/** The address of the mapped bytes. */
498	void *pv;
499	#if defined(IN_RC) && HC_ARCH_BITS == 64
500	uint32_t u32Alignment3; /*< Alignment padding. /
501	#endif
502	/** The access flags (IEM_ACCESS_XXX).
503	* IEM_ACCESS_INVALID if the entry is unused. */
504	uint32_t fAccess;
505	#if HC_ARCH_BITS == 64
506	uint32_t u32Alignment4; /*< Alignment padding. /
507	#endif
508	} aMemMappings[3];
509
510	/** Locking records for the mapped memory. */
511	union
512	{
513	PGMPAGEMAPLOCK Lock;
514	uint64_t au64Padding[2];
515	} aMemMappingLocks[3];
516
517	/** Bounce buffer info.
518	* This runs in parallel to aMemMappings. */
519	struct
520	{
521	/** The physical address of the first byte. */
522	RTGCPHYS GCPhysFirst;
523	/** The physical address of the second page. */
524	RTGCPHYS GCPhysSecond;
525	/** The number of bytes in the first page. */
526	uint16_t cbFirst;
527	/** The number of bytes in the second page. */
528	uint16_t cbSecond;
529	/** Whether it's unassigned memory. */
530	bool fUnassigned;
531	/** Explicit alignment padding. */
532	bool afAlignment5[3];
533	} aMemBbMappings[3];
534
535	/** Bounce buffer storage.
536	* This runs in parallel to aMemMappings and aMemBbMappings. */
537	struct
538	{
539	uint8_t ab[512];
540	} aBounceBuffers[3];
541
542
543	/** Pointer set jump buffer - ring-3 context. */
544	R3PTRTYPE(jmp_buf *) pJmpBufR3;
545	/** Pointer set jump buffer - ring-0 context. */
546	R0PTRTYPE(jmp_buf *) pJmpBufR0;
547	/** Pointer set jump buffer - raw-mode context. */
548	RCPTRTYPE(jmp_buf *) pJmpBufRC;
549
550	/** @todo Should move this near @a fCurXcpt later. */
551	/** The error code for the current exception / interrupt. */
552	uint32_t uCurXcptErr;
553	/** The CR2 for the current exception / interrupt. */
554	uint64_t uCurXcptCr2;
555
556	/** @name Statistics
557	* @{ */
558	/** The number of instructions we've executed. */
559	uint32_t cInstructions;
560	/** The number of potential exits. */
561	uint32_t cPotentialExits;
562	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
563	* This may contain uncommitted writes. */
564	uint32_t cbWritten;
565	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
566	uint32_t cRetInstrNotImplemented;
567	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
568	uint32_t cRetAspectNotImplemented;
569	/** Counts informational statuses returned (other than VINF_SUCCESS). */
570	uint32_t cRetInfStatuses;
571	/** Counts other error statuses returned. */
572	uint32_t cRetErrStatuses;
573	/** Number of times rcPassUp has been used. */
574	uint32_t cRetPassUpStatus;
575	/** Number of times RZ left with instruction commit pending for ring-3. */
576	uint32_t cPendingCommit;
577	/** Number of long jumps. */
578	uint32_t cLongJumps;
579	uint32_t uAlignment6; /*< Alignment padding. /
580	/** @} */
581
582	/** @name Target CPU information.
583	* @{ */
584	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
585	/** The target CPU. */
586	uint32_t uTargetCpu;
587	#else
588	uint32_t u32TargetCpuPadding;
589	#endif
590	/** The CPU vendor. */
591	CPUMCPUVENDOR enmCpuVendor;
592	/** @} */
593
594	/** @name Host CPU information.
595	* @{ */
596	/** The CPU vendor. */
597	CPUMCPUVENDOR enmHostCpuVendor;
598	/** @} */
599
600	/** Counts RDMSR \#GP(0) LogRel(). */
601	uint8_t cLogRelRdMsr;
602	/** Counts WRMSR \#GP(0) LogRel(). */
603	uint8_t cLogRelWrMsr;
604	/** Alignment padding. */
605	uint8_t abAlignment8[HC_ARCH_BITS == 64 ? 46 : 14];
606
607	/** Data TLB.
608	* @remarks Must be 64-byte aligned. */
609	IEMTLB DataTlb;
610	/** Instruction TLB.
611	* @remarks Must be 64-byte aligned. */
612	IEMTLB CodeTlb;
613
614	/** Pointer to instruction statistics for raw-mode context (same as R0). */
615	RCPTRTYPE(PIEMINSTRSTATS) pStatsRC;
616	/** Alignment padding. */
617	RTRCPTR RCPtrPadding;
618	/** Pointer to instruction statistics for ring-0 context (same as RC). */
619	R0PTRTYPE(PIEMINSTRSTATS) pStatsR0;
620	/** Pointer to instruction statistics for non-ring-3 code. */
621	R3PTRTYPE(PIEMINSTRSTATS) pStatsCCR3;
622	/** Pointer to instruction statistics for ring-3 context. */
623	R3PTRTYPE(PIEMINSTRSTATS) pStatsR3;
624	} IEMCPU;
625	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
626	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
627	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
628	/** Pointer to the per-CPU IEM state. */
629	typedef IEMCPU *PIEMCPU;
630	/** Pointer to the const per-CPU IEM state. */
631	typedef IEMCPU const *PCIEMCPU;
632
633
634	/** @def IEM_GET_CTX
635	* Gets the guest CPU context for the calling EMT.
636	* @returns PCPUMCTX
637	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
638	*/
639	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
640
641	/** @def IEM_CTX_ASSERT
642	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
643	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
644	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
645	*/
646	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
647	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
648	(a_fExtrnMbz)))
649
650	/** @def IEM_CTX_IMPORT_RET
651	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
652	*
653	* Will call the keep to import the bits as needed.
654	*
655	* Returns on import failure.
656	*
657	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
658	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
659	*/
660	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
661	do { \
662	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
663	{ /* likely */ } \
664	else \
665	{ \
666	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
667	AssertRCReturn(rcCtxImport, rcCtxImport); \
668	} \
669	} while (0)
670
671	/** @def IEM_CTX_IMPORT_NORET
672	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
673	*
674	* Will call the keep to import the bits as needed.
675	*
676	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
677	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
678	*/
679	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
680	do { \
681	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
682	{ /* likely */ } \
683	else \
684	{ \
685	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
686	AssertLogRelRC(rcCtxImport); \
687	} \
688	} while (0)
689
690	/** @def IEM_CTX_IMPORT_JMP
691	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
692	*
693	* Will call the keep to import the bits as needed.
694	*
695	* Jumps on import failure.
696	*
697	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
698	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
699	*/
700	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
701	do { \
702	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
703	{ /* likely */ } \
704	else \
705	{ \
706	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
707	AssertRCStmt(rcCtxImport, longjmp(*pVCpu->iem.s.CTX_SUFF(pJmpBuf), rcCtxImport)); \
708	} \
709	} while (0)
710
711
712
713	/** Gets the current IEMTARGETCPU value.
714	* @returns IEMTARGETCPU value.
715	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
716	*/
717	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
718	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
719	#else
720	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
721	#endif
722
723	/** @def Gets the instruction length. */
724	#ifdef IEM_WITH_CODE_TLB
725	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
726	#else
727	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
728	#endif
729
730
731	/** @name IEM_ACCESS_XXX - Access details.
732	* @{ */
733	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
734	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
735	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
736	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
737	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
738	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
739	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
740	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
741	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
742	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
743	/** The writes are partial, so if initialize the bounce buffer with the
744	* orignal RAM content. */
745	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
746	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
747	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
748	/** Bounce buffer with ring-3 write pending, first page. */
749	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
750	/** Bounce buffer with ring-3 write pending, second page. */
751	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
752	/** Valid bit mask. */
753	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00000fff)
754	/** Read+write data alias. */
755	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
756	/** Write data alias. */
757	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
758	/** Read data alias. */
759	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
760	/** Instruction fetch alias. */
761	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
762	/** Stack write alias. */
763	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
764	/** Stack read alias. */
765	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
766	/** Stack read+write alias. */
767	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
768	/** Read system table alias. */
769	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
770	/** Read+write system table alias. */
771	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
772	/** @} */
773
774	/** @name Prefix constants (IEMCPU::fPrefixes)
775	* @{ */
776	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
777	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
778	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
779	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
780	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
781	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
782	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
783
784	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
785	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
786	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
787
788	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
789	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
790	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
791
792	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
793	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
794	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
795	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
796	/** Mask with all the REX prefix flags.
797	* This is generally for use when needing to undo the REX prefixes when they
798	* are followed legacy prefixes and therefore does not immediately preceed
799	* the first opcode byte.
800	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
801	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
802
803	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
804	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
805	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
806	/** @} */
807
808	/** @name IEMOPFORM_XXX - Opcode forms
809	* @note These are ORed together with IEMOPHINT_XXX.
810	* @{ */
811	/** ModR/M: reg, r/m */
812	#define IEMOPFORM_RM 0
813	/** ModR/M: reg, r/m (register) */
814	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
815	/** ModR/M: reg, r/m (memory) */
816	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
817	/** ModR/M: r/m, reg */
818	#define IEMOPFORM_MR 1
819	/** ModR/M: r/m (register), reg */
820	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
821	/** ModR/M: r/m (memory), reg */
822	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
823	/** ModR/M: r/m only */
824	#define IEMOPFORM_M 2
825	/** ModR/M: r/m only (register). */
826	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
827	/** ModR/M: r/m only (memory). */
828	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
829	/** ModR/M: reg only */
830	#define IEMOPFORM_R 3
831
832	/** VEX+ModR/M: reg, r/m */
833	#define IEMOPFORM_VEX_RM 4
834	/** VEX+ModR/M: reg, r/m (register) */
835	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
836	/** VEX+ModR/M: reg, r/m (memory) */
837	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
838	/** VEX+ModR/M: r/m, reg */
839	#define IEMOPFORM_VEX_MR 5
840	/** VEX+ModR/M: r/m (register), reg */
841	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
842	/** VEX+ModR/M: r/m (memory), reg */
843	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
844	/** VEX+ModR/M: r/m only */
845	#define IEMOPFORM_VEX_M 6
846	/** VEX+ModR/M: r/m only (register). */
847	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
848	/** VEX+ModR/M: r/m only (memory). */
849	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
850	/** VEX+ModR/M: reg only */
851	#define IEMOPFORM_VEX_R 7
852	/** VEX+ModR/M: reg, vvvv, r/m */
853	#define IEMOPFORM_VEX_RVM 8
854	/** VEX+ModR/M: reg, vvvv, r/m (register). */
855	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
856	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
857	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
858	/** VEX+ModR/M: r/m, vvvv, reg */
859	#define IEMOPFORM_VEX_MVR 9
860	/** VEX+ModR/M: r/m, vvvv, reg (register) */
861	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
862	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
863	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
864
865	/** Fixed register instruction, no R/M. */
866	#define IEMOPFORM_FIXED 16
867
868	/** The r/m is a register. */
869	#define IEMOPFORM_MOD3 RT_BIT_32(8)
870	/** The r/m is a memory access. */
871	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
872	/** @} */
873
874	/** @name IEMOPHINT_XXX - Additional Opcode Hints
875	* @note These are ORed together with IEMOPFORM_XXX.
876	* @{ */
877	/** Ignores the operand size prefix (66h). */
878	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
879	/** Ignores REX.W (aka WIG). */
880	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
881	/** Both the operand size prefixes (66h + REX.W) are ignored. */
882	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
883	/** Allowed with the lock prefix. */
884	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
885	/** The VEX.L value is ignored (aka LIG). */
886	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
887	/** The VEX.L value must be zero (i.e. 128-bit width only). */
888	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
889
890	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
891	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
892	/** @} */
893
894	/**
895	* Possible hardware task switch sources.
896	*/
897	typedef enum IEMTASKSWITCH
898	{
899	/** Task switch caused by an interrupt/exception. */
900	IEMTASKSWITCH_INT_XCPT = 1,
901	/** Task switch caused by a far CALL. */
902	IEMTASKSWITCH_CALL,
903	/** Task switch caused by a far JMP. */
904	IEMTASKSWITCH_JUMP,
905	/** Task switch caused by an IRET. */
906	IEMTASKSWITCH_IRET
907	} IEMTASKSWITCH;
908	AssertCompileSize(IEMTASKSWITCH, 4);
909
910	/**
911	* Possible CrX load (write) sources.
912	*/
913	typedef enum IEMACCESSCRX
914	{
915	/** CrX access caused by 'mov crX' instruction. */
916	IEMACCESSCRX_MOV_CRX,
917	/** CrX (CR0) write caused by 'lmsw' instruction. */
918	IEMACCESSCRX_LMSW,
919	/** CrX (CR0) write caused by 'clts' instruction. */
920	IEMACCESSCRX_CLTS,
921	/** CrX (CR0) read caused by 'smsw' instruction. */
922	IEMACCESSCRX_SMSW
923	} IEMACCESSCRX;
924
925
926	/**
927	* Indicates to the verifier that the given flag set is undefined.
928	*
929	* Can be invoked again to add more flags.
930	*
931	* This is a NOOP if the verifier isn't compiled in.
932	*
933	* @note We're temporarily keeping this until code is converted to new
934	* disassembler style opcode handling.
935	*/
936	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
937
938
939	/** @def IEM_DECL_IMPL_TYPE
940	* For typedef'ing an instruction implementation function.
941	*
942	* @param a_RetType The return type.
943	* @param a_Name The name of the type.
944	* @param a_ArgList The argument list enclosed in parentheses.
945	*/
946
947	/** @def IEM_DECL_IMPL_DEF
948	* For defining an instruction implementation function.
949	*
950	* @param a_RetType The return type.
951	* @param a_Name The name of the type.
952	* @param a_ArgList The argument list enclosed in parentheses.
953	*/
954
955	#if defined(__GNUC__) && defined(RT_ARCH_X86)
956	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
957	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
958	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
959	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
960
961	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
962	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
963	a_RetType (__fastcall a_Name) a_ArgList
964	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
965	a_RetType __fastcall a_Name a_ArgList
966
967	#else
968	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
969	a_RetType (VBOXCALL a_Name) a_ArgList
970	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
971	a_RetType VBOXCALL a_Name a_ArgList
972
973	#endif
974
975	/** @name Arithmetic assignment operations on bytes (binary).
976	* @{ */
977	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
978	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
979	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
980	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
981	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
982	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
983	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
984	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
985	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
986	/** @} */
987
988	/** @name Arithmetic assignment operations on words (binary).
989	* @{ */
990	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
991	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
992	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
993	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
994	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
995	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
996	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
997	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
998	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
999	/** @} */
1000
1001	/** @name Arithmetic assignment operations on double words (binary).
1002	* @{ */
1003	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1004	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1005	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1006	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1007	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1008	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1009	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1010	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1011	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1012	/** @} */
1013
1014	/** @name Arithmetic assignment operations on quad words (binary).
1015	* @{ */
1016	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1017	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1018	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1019	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1020	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1021	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1022	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1023	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1024	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1025	/** @} */
1026
1027	/** @name Compare operations (thrown in with the binary ops).
1028	* @{ */
1029	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1030	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1031	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1032	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1033	/** @} */
1034
1035	/** @name Test operations (thrown in with the binary ops).
1036	* @{ */
1037	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1038	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1039	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1040	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1041	/** @} */
1042
1043	/** @name Bit operations operations (thrown in with the binary ops).
1044	* @{ */
1045	FNIEMAIMPLBINU16 iemAImpl_bt_u16, iemAImpl_bt_u16_locked;
1046	FNIEMAIMPLBINU32 iemAImpl_bt_u32, iemAImpl_bt_u32_locked;
1047	FNIEMAIMPLBINU64 iemAImpl_bt_u64, iemAImpl_bt_u64_locked;
1048	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1049	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1050	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1051	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1052	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1053	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1054	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1055	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1056	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1057	/** @} */
1058
1059	/** @name Exchange memory with register operations.
1060	* @{ */
1061	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8, (uint8_t pu8Mem, uint8_t pu8Reg));
1062	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16,(uint16_t pu16Mem, uint16_t pu16Reg));
1063	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32,(uint32_t pu32Mem, uint32_t pu32Reg));
1064	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64,(uint64_t pu64Mem, uint64_t pu64Reg));
1065	/** @} */
1066
1067	/** @name Exchange and add operations.
1068	* @{ */
1069	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1070	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1071	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1072	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1073	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1074	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1075	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1076	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1077	/** @} */
1078
1079	/** @name Compare and exchange.
1080	* @{ */
1081	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1082	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1083	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1084	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1085	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1086	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1087	#ifdef RT_ARCH_X86
1088	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1089	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1090	#else
1091	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1092	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1093	#endif
1094	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1095	uint32_t *pEFlags));
1096	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1097	uint32_t *pEFlags));
1098	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1099	uint32_t *pEFlags));
1100	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1101	uint32_t *pEFlags));
1102	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1103	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1104	/** @} */
1105
1106	/** @name Memory ordering
1107	* @{ */
1108	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1109	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1110	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1111	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1112	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1113	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1114	/** @} */
1115
1116	/** @name Double precision shifts
1117	* @{ */
1118	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1119	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1120	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1121	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1122	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1123	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1124	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16;
1125	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32;
1126	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64;
1127	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16;
1128	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32;
1129	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64;
1130	/** @} */
1131
1132
1133	/** @name Bit search operations (thrown in with the binary ops).
1134	* @{ */
1135	FNIEMAIMPLBINU16 iemAImpl_bsf_u16;
1136	FNIEMAIMPLBINU32 iemAImpl_bsf_u32;
1137	FNIEMAIMPLBINU64 iemAImpl_bsf_u64;
1138	FNIEMAIMPLBINU16 iemAImpl_bsr_u16;
1139	FNIEMAIMPLBINU32 iemAImpl_bsr_u32;
1140	FNIEMAIMPLBINU64 iemAImpl_bsr_u64;
1141	/** @} */
1142
1143	/** @name Signed multiplication operations (thrown in with the binary ops).
1144	* @{ */
1145	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16;
1146	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32;
1147	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64;
1148	/** @} */
1149
1150	/** @name Arithmetic assignment operations on bytes (unary).
1151	* @{ */
1152	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1153	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1154	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1155	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1156	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1157	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1158	/** @} */
1159
1160	/** @name Arithmetic assignment operations on words (unary).
1161	* @{ */
1162	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1163	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1164	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1165	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1166	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1167	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1168	/** @} */
1169
1170	/** @name Arithmetic assignment operations on double words (unary).
1171	* @{ */
1172	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1173	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1174	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1175	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1176	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1177	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1178	/** @} */
1179
1180	/** @name Arithmetic assignment operations on quad words (unary).
1181	* @{ */
1182	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1183	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1184	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1185	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1186	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1187	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1188	/** @} */
1189
1190
1191	/** @name Shift operations on bytes (Group 2).
1192	* @{ */
1193	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1194	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1195	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8;
1196	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8;
1197	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8;
1198	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8;
1199	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8;
1200	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8;
1201	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8;
1202	/** @} */
1203
1204	/** @name Shift operations on words (Group 2).
1205	* @{ */
1206	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1207	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1208	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16;
1209	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16;
1210	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16;
1211	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16;
1212	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16;
1213	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16;
1214	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16;
1215	/** @} */
1216
1217	/** @name Shift operations on double words (Group 2).
1218	* @{ */
1219	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1220	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1221	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32;
1222	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32;
1223	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32;
1224	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32;
1225	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32;
1226	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32;
1227	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32;
1228	/** @} */
1229
1230	/** @name Shift operations on words (Group 2).
1231	* @{ */
1232	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1233	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1234	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64;
1235	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64;
1236	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64;
1237	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64;
1238	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64;
1239	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64;
1240	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64;
1241	/** @} */
1242
1243	/** @name Multiplication and division operations.
1244	* @{ */
1245	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1246	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1247	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_imul_u8;
1248	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_idiv_u8;
1249
1250	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1251	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1252	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_imul_u16;
1253	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_idiv_u16;
1254
1255	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1256	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1257	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_imul_u32;
1258	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_idiv_u32;
1259
1260	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1261	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1262	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_imul_u64;
1263	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_idiv_u64;
1264	/** @} */
1265
1266	/** @name Byte Swap.
1267	* @{ */
1268	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1269	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1270	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1271	/** @} */
1272
1273	/** @name Misc.
1274	* @{ */
1275	FNIEMAIMPLBINU16 iemAImpl_arpl;
1276	/** @} */
1277
1278
1279	/** @name FPU operations taking a 32-bit float argument
1280	* @{ */
1281	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1282	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1283	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1284
1285	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1286	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1287	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1288
1289	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1290	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1291	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1292	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1293	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1294	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1295	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1296
1297	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1298	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1299	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1300	/** @} */
1301
1302	/** @name FPU operations taking a 64-bit float argument
1303	* @{ */
1304	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1305	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1306	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1307
1308	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1309	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1310	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1311	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1312	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1313	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1314
1315	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1316	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1317	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1318	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1319	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1320	/** @} */
1321
1322	/** @name FPU operations taking a 80-bit float argument
1323	* @{ */
1324	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1325	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1326	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1327	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1328	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1329	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1330	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1331	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1332	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1333	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1334	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1335	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1336
1337	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80;
1338	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80;
1339	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80;
1340
1341	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1342	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1343	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1344	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1345	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1346
1347	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1348	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1349	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1350	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1351	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1352
1353	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1354	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1355	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1356	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1357	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80;
1358	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1359	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1360	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80;
1361	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80;
1362
1363	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1364	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1365	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1366	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1367
1368	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1369	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1370	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1371	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1372	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1373	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1374	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1375	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1376	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1377
1378	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1379	PCRTFLOAT80U pr80Val));
1380	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1381	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80;
1382	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1383	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80;
1384
1385	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1386	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1387	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1388
1389	/** @} */
1390
1391	/** @name FPU operations taking a 16-bit signed integer argument
1392	* @{ */
1393	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1394	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1395	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1396
1397	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1398	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1399	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1400	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1401	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1402	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1403
1404	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1405	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1406
1407	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1408	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1409	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1410	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1411	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1412	/** @} */
1413
1414	/** @name FPU operations taking a 32-bit signed integer argument
1415	* @{ */
1416	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1417	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1418	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1419
1420	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1421	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1422	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1423	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1424	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1425	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1426
1427	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1428	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1429
1430	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1431	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1432	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1433	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1434	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1435	/** @} */
1436
1437	/** @name FPU operations taking a 64-bit signed integer argument
1438	* @{ */
1439	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1440	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1441	typedef FNIEMAIMPLFPUI64 *PFNIEMAIMPLFPUI64;
1442
1443	FNIEMAIMPLFPUI64 iemAImpl_fiadd_r80_by_i64;
1444	FNIEMAIMPLFPUI64 iemAImpl_fimul_r80_by_i64;
1445	FNIEMAIMPLFPUI64 iemAImpl_fisub_r80_by_i64;
1446	FNIEMAIMPLFPUI64 iemAImpl_fisubr_r80_by_i64;
1447	FNIEMAIMPLFPUI64 iemAImpl_fidiv_r80_by_i64;
1448	FNIEMAIMPLFPUI64 iemAImpl_fidivr_r80_by_i64;
1449
1450	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1451	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1452
1453	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1454	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1455	int64_t *pi64Val, PCRTFLOAT80U pr80Val));
1456	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1457	int64_t *pi32Val, PCRTFLOAT80U pr80Val));
1458	/** @} */
1459
1460
1461	/** Temporary type representing a 256-bit vector register. */
1462	typedef struct {uint64_t au64[4]; } IEMVMM256;
1463	/** Temporary type pointing to a 256-bit vector register. */
1464	typedef IEMVMM256 *PIEMVMM256;
1465	/** Temporary type pointing to a const 256-bit vector register. */
1466	typedef IEMVMM256 *PCIEMVMM256;
1467
1468
1469	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1470	* @{ */
1471	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1472	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1473	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1474	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1475	FNIEMAIMPLMEDIAF2U64 iemAImpl_pxor_u64, iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1476	FNIEMAIMPLMEDIAF2U128 iemAImpl_pxor_u128, iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1477	/** @} */
1478
1479	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1480	* @{ */
1481	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src));
1482	typedef FNIEMAIMPLMEDIAF1L1U64 *PFNIEMAIMPLMEDIAF1L1U64;
1483	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src));
1484	typedef FNIEMAIMPLMEDIAF1L1U128 *PFNIEMAIMPLMEDIAF1L1U128;
1485	FNIEMAIMPLMEDIAF1L1U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1486	FNIEMAIMPLMEDIAF1L1U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1487	/** @} */
1488
1489	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
1490	* @{ */
1491	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1492	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF1H1U64;
1493	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1494	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF1H1U128;
1495	FNIEMAIMPLMEDIAF1H1U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
1496	FNIEMAIMPLMEDIAF1H1U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
1497	/** @} */
1498
1499	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
1500	* @{ */
1501	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUF,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst,
1502	PCRTUINT128U pu128Src, uint8_t bEvil));
1503	typedef FNIEMAIMPLMEDIAPSHUF *PFNIEMAIMPLMEDIAPSHUF;
1504	FNIEMAIMPLMEDIAPSHUF iemAImpl_pshufhw, iemAImpl_pshuflw, iemAImpl_pshufd;
1505	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil));
1506	/** @} */
1507
1508	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
1509	* @{ */
1510	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1511	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src));
1512	/** @} */
1513
1514	/** @name Media (SSE/MMX/AVX) operation: Sort this later
1515	* @{ */
1516	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1517	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1518	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc));
1519
1520	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1521	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1522	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1523	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1524
1525	/** @} */
1526
1527
1528	/** @name Function tables.
1529	* @{
1530	*/
1531
1532	/**
1533	* Function table for a binary operator providing implementation based on
1534	* operand size.
1535	*/
1536	typedef struct IEMOPBINSIZES
1537	{
1538	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
1539	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
1540	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
1541	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
1542	} IEMOPBINSIZES;
1543	/** Pointer to a binary operator function table. */
1544	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
1545
1546
1547	/**
1548	* Function table for a unary operator providing implementation based on
1549	* operand size.
1550	*/
1551	typedef struct IEMOPUNARYSIZES
1552	{
1553	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
1554	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
1555	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
1556	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
1557	} IEMOPUNARYSIZES;
1558	/** Pointer to a unary operator function table. */
1559	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
1560
1561
1562	/**
1563	* Function table for a shift operator providing implementation based on
1564	* operand size.
1565	*/
1566	typedef struct IEMOPSHIFTSIZES
1567	{
1568	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
1569	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
1570	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
1571	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
1572	} IEMOPSHIFTSIZES;
1573	/** Pointer to a shift operator function table. */
1574	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
1575
1576
1577	/**
1578	* Function table for a multiplication or division operation.
1579	*/
1580	typedef struct IEMOPMULDIVSIZES
1581	{
1582	PFNIEMAIMPLMULDIVU8 pfnU8;
1583	PFNIEMAIMPLMULDIVU16 pfnU16;
1584	PFNIEMAIMPLMULDIVU32 pfnU32;
1585	PFNIEMAIMPLMULDIVU64 pfnU64;
1586	} IEMOPMULDIVSIZES;
1587	/** Pointer to a multiplication or division operation function table. */
1588	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
1589
1590
1591	/**
1592	* Function table for a double precision shift operator providing implementation
1593	* based on operand size.
1594	*/
1595	typedef struct IEMOPSHIFTDBLSIZES
1596	{
1597	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
1598	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
1599	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
1600	} IEMOPSHIFTDBLSIZES;
1601	/** Pointer to a double precision shift function table. */
1602	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
1603
1604
1605	/**
1606	* Function table for media instruction taking two full sized media registers,
1607	* optionally the 2nd being a memory reference (only modifying the first op.)
1608	*/
1609	typedef struct IEMOPMEDIAF2
1610	{
1611	PFNIEMAIMPLMEDIAF2U64 pfnU64;
1612	PFNIEMAIMPLMEDIAF2U128 pfnU128;
1613	} IEMOPMEDIAF2;
1614	/** Pointer to a media operation function table for full sized ops. */
1615	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
1616
1617	/**
1618	* Function table for media instruction taking taking one full and one lower
1619	* half media register.
1620	*/
1621	typedef struct IEMOPMEDIAF1L1
1622	{
1623	PFNIEMAIMPLMEDIAF1L1U64 pfnU64;
1624	PFNIEMAIMPLMEDIAF1L1U128 pfnU128;
1625	} IEMOPMEDIAF1L1;
1626	/** Pointer to a media operation function table for lowhalf+lowhalf -> full. */
1627	typedef IEMOPMEDIAF1L1 const *PCIEMOPMEDIAF1L1;
1628
1629	/**
1630	* Function table for media instruction taking taking one full and one high half
1631	* media register.
1632	*/
1633	typedef struct IEMOPMEDIAF1H1
1634	{
1635	PFNIEMAIMPLMEDIAF1H1U64 pfnU64;
1636	PFNIEMAIMPLMEDIAF1H1U128 pfnU128;
1637	} IEMOPMEDIAF1H1;
1638	/** Pointer to a media operation function table for hihalf+hihalf -> full. */
1639	typedef IEMOPMEDIAF1H1 const *PCIEMOPMEDIAF1H1;
1640
1641
1642	/** @} */
1643
1644
1645	/** @name C instruction implementations for anything slightly complicated.
1646	* @{ */
1647
1648	/**
1649	* For typedef'ing or declaring a C instruction implementation function taking
1650	* no extra arguments.
1651	*
1652	* @param a_Name The name of the type.
1653	*/
1654	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
1655	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1656	/**
1657	* For defining a C instruction implementation function taking no extra
1658	* arguments.
1659	*
1660	* @param a_Name The name of the function
1661	*/
1662	# define IEM_CIMPL_DEF_0(a_Name) \
1663	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1664	/**
1665	* For calling a C instruction implementation function taking no extra
1666	* arguments.
1667	*
1668	* This special call macro adds default arguments to the call and allow us to
1669	* change these later.
1670	*
1671	* @param a_fn The name of the function.
1672	*/
1673	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
1674
1675	/**
1676	* For typedef'ing or declaring a C instruction implementation function taking
1677	* one extra argument.
1678	*
1679	* @param a_Name The name of the type.
1680	* @param a_Type0 The argument type.
1681	* @param a_Arg0 The argument name.
1682	*/
1683	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
1684	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1685	/**
1686	* For defining a C instruction implementation function taking one extra
1687	* argument.
1688	*
1689	* @param a_Name The name of the function
1690	* @param a_Type0 The argument type.
1691	* @param a_Arg0 The argument name.
1692	*/
1693	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
1694	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1695	/**
1696	* For calling a C instruction implementation function taking one extra
1697	* argument.
1698	*
1699	* This special call macro adds default arguments to the call and allow us to
1700	* change these later.
1701	*
1702	* @param a_fn The name of the function.
1703	* @param a0 The name of the 1st argument.
1704	*/
1705	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
1706
1707	/**
1708	* For typedef'ing or declaring a C instruction implementation function taking
1709	* two extra arguments.
1710	*
1711	* @param a_Name The name of the type.
1712	* @param a_Type0 The type of the 1st argument
1713	* @param a_Arg0 The name of the 1st argument.
1714	* @param a_Type1 The type of the 2nd argument.
1715	* @param a_Arg1 The name of the 2nd argument.
1716	*/
1717	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1718	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1719	/**
1720	* For defining a C instruction implementation function taking two extra
1721	* arguments.
1722	*
1723	* @param a_Name The name of the function.
1724	* @param a_Type0 The type of the 1st argument
1725	* @param a_Arg0 The name of the 1st argument.
1726	* @param a_Type1 The type of the 2nd argument.
1727	* @param a_Arg1 The name of the 2nd argument.
1728	*/
1729	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1730	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1731	/**
1732	* For calling a C instruction implementation function taking two extra
1733	* arguments.
1734	*
1735	* This special call macro adds default arguments to the call and allow us to
1736	* change these later.
1737	*
1738	* @param a_fn The name of the function.
1739	* @param a0 The name of the 1st argument.
1740	* @param a1 The name of the 2nd argument.
1741	*/
1742	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
1743
1744	/**
1745	* For typedef'ing or declaring a C instruction implementation function taking
1746	* three extra arguments.
1747	*
1748	* @param a_Name The name of the type.
1749	* @param a_Type0 The type of the 1st argument
1750	* @param a_Arg0 The name of the 1st argument.
1751	* @param a_Type1 The type of the 2nd argument.
1752	* @param a_Arg1 The name of the 2nd argument.
1753	* @param a_Type2 The type of the 3rd argument.
1754	* @param a_Arg2 The name of the 3rd argument.
1755	*/
1756	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1757	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1758	/**
1759	* For defining a C instruction implementation function taking three extra
1760	* arguments.
1761	*
1762	* @param a_Name The name of the function.
1763	* @param a_Type0 The type of the 1st argument
1764	* @param a_Arg0 The name of the 1st argument.
1765	* @param a_Type1 The type of the 2nd argument.
1766	* @param a_Arg1 The name of the 2nd argument.
1767	* @param a_Type2 The type of the 3rd argument.
1768	* @param a_Arg2 The name of the 3rd argument.
1769	*/
1770	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1771	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1772	/**
1773	* For calling a C instruction implementation function taking three extra
1774	* arguments.
1775	*
1776	* This special call macro adds default arguments to the call and allow us to
1777	* change these later.
1778	*
1779	* @param a_fn The name of the function.
1780	* @param a0 The name of the 1st argument.
1781	* @param a1 The name of the 2nd argument.
1782	* @param a2 The name of the 3rd argument.
1783	*/
1784	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
1785
1786
1787	/**
1788	* For typedef'ing or declaring a C instruction implementation function taking
1789	* four extra arguments.
1790	*
1791	* @param a_Name The name of the type.
1792	* @param a_Type0 The type of the 1st argument
1793	* @param a_Arg0 The name of the 1st argument.
1794	* @param a_Type1 The type of the 2nd argument.
1795	* @param a_Arg1 The name of the 2nd argument.
1796	* @param a_Type2 The type of the 3rd argument.
1797	* @param a_Arg2 The name of the 3rd argument.
1798	* @param a_Type3 The type of the 4th argument.
1799	* @param a_Arg3 The name of the 4th argument.
1800	*/
1801	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1802	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
1803	/**
1804	* For defining a C instruction implementation function taking four extra
1805	* arguments.
1806	*
1807	* @param a_Name The name of the function.
1808	* @param a_Type0 The type of the 1st argument
1809	* @param a_Arg0 The name of the 1st argument.
1810	* @param a_Type1 The type of the 2nd argument.
1811	* @param a_Arg1 The name of the 2nd argument.
1812	* @param a_Type2 The type of the 3rd argument.
1813	* @param a_Arg2 The name of the 3rd argument.
1814	* @param a_Type3 The type of the 4th argument.
1815	* @param a_Arg3 The name of the 4th argument.
1816	*/
1817	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1818	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1819	a_Type2 a_Arg2, a_Type3 a_Arg3))
1820	/**
1821	* For calling a C instruction implementation function taking four extra
1822	* arguments.
1823	*
1824	* This special call macro adds default arguments to the call and allow us to
1825	* change these later.
1826	*
1827	* @param a_fn The name of the function.
1828	* @param a0 The name of the 1st argument.
1829	* @param a1 The name of the 2nd argument.
1830	* @param a2 The name of the 3rd argument.
1831	* @param a3 The name of the 4th argument.
1832	*/
1833	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
1834
1835
1836	/**
1837	* For typedef'ing or declaring a C instruction implementation function taking
1838	* five extra arguments.
1839	*
1840	* @param a_Name The name of the type.
1841	* @param a_Type0 The type of the 1st argument
1842	* @param a_Arg0 The name of the 1st argument.
1843	* @param a_Type1 The type of the 2nd argument.
1844	* @param a_Arg1 The name of the 2nd argument.
1845	* @param a_Type2 The type of the 3rd argument.
1846	* @param a_Arg2 The name of the 3rd argument.
1847	* @param a_Type3 The type of the 4th argument.
1848	* @param a_Arg3 The name of the 4th argument.
1849	* @param a_Type4 The type of the 5th argument.
1850	* @param a_Arg4 The name of the 5th argument.
1851	*/
1852	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1853	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1854	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1855	a_Type3 a_Arg3, a_Type4 a_Arg4))
1856	/**
1857	* For defining a C instruction implementation function taking five extra
1858	* arguments.
1859	*
1860	* @param a_Name The name of the function.
1861	* @param a_Type0 The type of the 1st argument
1862	* @param a_Arg0 The name of the 1st argument.
1863	* @param a_Type1 The type of the 2nd argument.
1864	* @param a_Arg1 The name of the 2nd argument.
1865	* @param a_Type2 The type of the 3rd argument.
1866	* @param a_Arg2 The name of the 3rd argument.
1867	* @param a_Type3 The type of the 4th argument.
1868	* @param a_Arg3 The name of the 4th argument.
1869	* @param a_Type4 The type of the 5th argument.
1870	* @param a_Arg4 The name of the 5th argument.
1871	*/
1872	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1873	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1874	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1875	a_Type3 a_Arg3, a_Type4 a_Arg4))
1876	/**
1877	* For calling a C instruction implementation function taking five extra
1878	* arguments.
1879	*
1880	* This special call macro adds default arguments to the call and allow us to
1881	* change these later.
1882	*
1883	* @param a_fn The name of the function.
1884	* @param a0 The name of the 1st argument.
1885	* @param a1 The name of the 2nd argument.
1886	* @param a2 The name of the 3rd argument.
1887	* @param a3 The name of the 4th argument.
1888	* @param a4 The name of the 5th argument.
1889	*/
1890	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
1891
1892	/** @} */
1893
1894
1895	/** @} */
1896
1897	RT_C_DECLS_END
1898
1899	#endif
1900

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 73016

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