IEMInternal.h@ 74442

Last change on this file since 74442 was 73555, checked in by vboxsync, 6 years ago
IEM: Added IEM_OPCODE_GET_NEXT_RM and associated IEMCPU::offModRm. bugref:9180
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 81.4 KB

Line
1	/* $Id: IEMInternal.h 73555 2018-08-08 08:49:36Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___IEMInternal_h
19	#define ___IEMInternal_h
20
21	#include <VBox/vmm/cpum.h>
22	#include <VBox/vmm/iem.h>
23	#include <VBox/vmm/stam.h>
24	#include <VBox/param.h>
25
26	#include <setjmp.h>
27
28
29	RT_C_DECLS_BEGIN
30
31
32	/** @defgroup grp_iem_int Internals
33	* @ingroup grp_iem
34	* @internal
35	* @{
36	*/
37
38	/** For expanding symbol in slickedit and other products tagging and
39	* crossreferencing IEM symbols. */
40	#ifndef IEM_STATIC
41	# define IEM_STATIC static
42	#endif
43
44	/** @def IEM_WITH_3DNOW
45	* Includes the 3DNow decoding. */
46	#define IEM_WITH_3DNOW
47
48	/** @def IEM_WITH_THREE_0F_38
49	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
50	#define IEM_WITH_THREE_0F_38
51
52	/** @def IEM_WITH_THREE_0F_3A
53	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
54	#define IEM_WITH_THREE_0F_3A
55
56	/** @def IEM_WITH_VEX
57	* Includes the VEX decoding. */
58	#define IEM_WITH_VEX
59
60	/** @def IEM_CFG_TARGET_CPU
61	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
62	*
63	* By default we allow this to be configured by the user via the
64	* CPUM/GuestCpuName config string, but this comes at a slight cost during
65	* decoding. So, for applications of this code where there is no need to
66	* be dynamic wrt target CPU, just modify this define.
67	*/
68	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
69	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
70	#endif
71
72
73	//#define IEM_WITH_CODE_TLB// - work in progress
74
75
76	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
77	/** Instruction statistics. */
78	typedef struct IEMINSTRSTATS
79	{
80	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
81	# include "IEMInstructionStatisticsTmpl.h"
82	# undef IEM_DO_INSTR_STAT
83	} IEMINSTRSTATS;
84	#else
85	struct IEMINSTRSTATS;
86	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
87	#endif
88	/** Pointer to IEM instruction statistics. */
89	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
90
91	/** Finish and move to types.h */
92	typedef union
93	{
94	uint32_t u32;
95	} RTFLOAT32U;
96	typedef RTFLOAT32U *PRTFLOAT32U;
97	typedef RTFLOAT32U const *PCRTFLOAT32U;
98
99
100	/**
101	* Extended operand mode that includes a representation of 8-bit.
102	*
103	* This is used for packing down modes when invoking some C instruction
104	* implementations.
105	*/
106	typedef enum IEMMODEX
107	{
108	IEMMODEX_16BIT = IEMMODE_16BIT,
109	IEMMODEX_32BIT = IEMMODE_32BIT,
110	IEMMODEX_64BIT = IEMMODE_64BIT,
111	IEMMODEX_8BIT
112	} IEMMODEX;
113	AssertCompileSize(IEMMODEX, 4);
114
115
116	/**
117	* Branch types.
118	*/
119	typedef enum IEMBRANCH
120	{
121	IEMBRANCH_JUMP = 1,
122	IEMBRANCH_CALL,
123	IEMBRANCH_TRAP,
124	IEMBRANCH_SOFTWARE_INT,
125	IEMBRANCH_HARDWARE_INT
126	} IEMBRANCH;
127	AssertCompileSize(IEMBRANCH, 4);
128
129
130	/**
131	* INT instruction types.
132	*/
133	typedef enum IEMINT
134	{
135	/** INT n instruction (opcode 0xcd imm). */
136	IEMINT_INTN = 0,
137	/** Single byte INT3 instruction (opcode 0xcc). */
138	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
139	/** Single byte INTO instruction (opcode 0xce). */
140	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
141	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
142	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
143	} IEMINT;
144	AssertCompileSize(IEMINT, 4);
145
146
147	/**
148	* A FPU result.
149	*/
150	typedef struct IEMFPURESULT
151	{
152	/** The output value. */
153	RTFLOAT80U r80Result;
154	/** The output status. */
155	uint16_t FSW;
156	} IEMFPURESULT;
157	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
158	/** Pointer to a FPU result. */
159	typedef IEMFPURESULT *PIEMFPURESULT;
160	/** Pointer to a const FPU result. */
161	typedef IEMFPURESULT const *PCIEMFPURESULT;
162
163
164	/**
165	* A FPU result consisting of two output values and FSW.
166	*/
167	typedef struct IEMFPURESULTTWO
168	{
169	/** The first output value. */
170	RTFLOAT80U r80Result1;
171	/** The output status. */
172	uint16_t FSW;
173	/** The second output value. */
174	RTFLOAT80U r80Result2;
175	} IEMFPURESULTTWO;
176	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
177	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
178	/** Pointer to a FPU result consisting of two output values and FSW. */
179	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
180	/** Pointer to a const FPU result consisting of two output values and FSW. */
181	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
182
183
184	/**
185	* IEM TLB entry.
186	*
187	* Lookup assembly:
188	* @code{.asm}
189	; Calculate tag.
190	mov rax, [VA]
191	shl rax, 16
192	shr rax, 16 + X86_PAGE_SHIFT
193	or rax, [uTlbRevision]
194
195	; Do indexing.
196	movzx ecx, al
197	lea rcx, [pTlbEntries + rcx]
198
199	; Check tag.
200	cmp [rcx + IEMTLBENTRY.uTag], rax
201	jne .TlbMiss
202
203	; Check access.
204	movsx rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
205	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
206	cmp rax, [uTlbPhysRev]
207	jne .TlbMiss
208
209	; Calc address and we're done.
210	mov eax, X86_PAGE_OFFSET_MASK
211	and eax, [VA]
212	or rax, [rcx + IEMTLBENTRY.pMappingR3]
213	%ifdef VBOX_WITH_STATISTICS
214	inc qword [cTlbHits]
215	%endif
216	jmp .Done
217
218	.TlbMiss:
219	mov r8d, ACCESS_FLAGS
220	mov rdx, [VA]
221	mov rcx, [pVCpu]
222	call iemTlbTypeMiss
223	.Done:
224
225	@endcode
226	*
227	*/
228	typedef struct IEMTLBENTRY
229	{
230	/** The TLB entry tag.
231	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits.
232	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
233	*
234	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
235	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
236	* revision wraps around though, the tags needs to be zeroed.
237	*
238	* @note Try use SHRD instruction? After seeing
239	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
240	*/
241	uint64_t uTag;
242	/** Access flags and physical TLB revision.
243	*
244	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
245	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
246	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
247	* - Bit 3 - pgm phys/virt - not directly writable.
248	* - Bit 4 - pgm phys page - not directly readable.
249	* - Bit 5 - currently unused.
250	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
251	* - Bit 7 - tlb entry - pMappingR3 member not valid.
252	* - Bits 63 thru 8 are used for the physical TLB revision number.
253	*
254	* We're using complemented bit meanings here because it makes it easy to check
255	* whether special action is required. For instance a user mode write access
256	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
257	* non-zero result would mean special handling needed because either it wasn't
258	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
259	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
260	* need to check any PTE flag.
261	*/
262	uint64_t fFlagsAndPhysRev;
263	/** The guest physical page address. */
264	uint64_t GCPhys;
265	/** Pointer to the ring-3 mapping (possibly also valid in ring-0). */
266	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
267	R3PTRTYPE(uint8_t *) pbMappingR3;
268	#else
269	R3R0PTRTYPE(uint8_t *) pbMappingR3;
270	#endif
271	#if HC_ARCH_BITS == 32
272	uint32_t u32Padding1;
273	#endif
274	} IEMTLBENTRY;
275	AssertCompileSize(IEMTLBENTRY, 32);
276	/** Pointer to an IEM TLB entry. */
277	typedef IEMTLBENTRY *PIEMTLBENTRY;
278
279	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
280	* @{ */
281	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
282	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
283	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
284	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
285	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
286	#define IEMTLBE_F_PATCH_CODE RT_BIT_64(5) /*< Code TLB: Patch code (PATM). /
287	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
288	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
289	#define IEMTLBE_F_PHYS_REV UINT64_C(0xffffffffffffff00) /*< Physical revision mask. /
290	/** @} */
291
292
293	/**
294	* An IEM TLB.
295	*
296	* We've got two of these, one for data and one for instructions.
297	*/
298	typedef struct IEMTLB
299	{
300	/** The TLB entries.
301	* We've choosen 256 because that way we can obtain the result directly from a
302	* 8-bit register without an additional AND instruction. */
303	IEMTLBENTRY aEntries[256];
304	/** The TLB revision.
305	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
306	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
307	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
308	* (The revision zero indicates an invalid TLB entry.)
309	*
310	* The initial value is choosen to cause an early wraparound. */
311	uint64_t uTlbRevision;
312	/** The TLB physical address revision - shadow of PGM variable.
313	*
314	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
315	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
316	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
317	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
318	*
319	* The initial value is choosen to cause an early wraparound. */
320	uint64_t volatile uTlbPhysRev;
321
322	/* Statistics: */
323
324	/** TLB hits (VBOX_WITH_STATISTICS only). */
325	uint64_t cTlbHits;
326	/** TLB misses. */
327	uint32_t cTlbMisses;
328	/** Slow read path. */
329	uint32_t cTlbSlowReadPath;
330	#if 0
331	/** TLB misses because of tag mismatch. */
332	uint32_t cTlbMissesTag;
333	/** TLB misses because of virtual access violation. */
334	uint32_t cTlbMissesVirtAccess;
335	/** TLB misses because of dirty bit. */
336	uint32_t cTlbMissesDirty;
337	/** TLB misses because of MMIO */
338	uint32_t cTlbMissesMmio;
339	/** TLB misses because of write access handlers. */
340	uint32_t cTlbMissesWriteHandler;
341	/** TLB misses because no r3(/r0) mapping. */
342	uint32_t cTlbMissesMapping;
343	#endif
344	/** Alignment padding. */
345	uint32_t au32Padding[3+5];
346	} IEMTLB;
347	AssertCompileSizeAlignment(IEMTLB, 64);
348	/** IEMTLB::uTlbRevision increment. */
349	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
350	/** IEMTLB::uTlbPhysRev increment. */
351	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(8)
352
353
354	/**
355	* The per-CPU IEM state.
356	*/
357	typedef struct IEMCPU
358	{
359	/** Info status code that needs to be propagated to the IEM caller.
360	* This cannot be passed internally, as it would complicate all success
361	* checks within the interpreter making the code larger and almost impossible
362	* to get right. Instead, we'll store status codes to pass on here. Each
363	* source of these codes will perform appropriate sanity checks. */
364	int32_t rcPassUp; /* 0x00 */
365
366	/** The current CPU execution mode (CS). */
367	IEMMODE enmCpuMode; /* 0x04 */
368	/** The CPL. */
369	uint8_t uCpl; /* 0x05 */
370
371	/** Whether to bypass access handlers or not. */
372	bool fBypassHandlers; /* 0x06 */
373	/** Indicates that we're interpreting patch code - RC only! */
374	bool fInPatchCode; /* 0x07 */
375
376	/** @name Decoder state.
377	* @{ */
378	#ifdef IEM_WITH_CODE_TLB
379	/** The offset of the next instruction byte. */
380	uint32_t offInstrNextByte; /* 0x08 */
381	/** The number of bytes available at pbInstrBuf for the current instruction.
382	* This takes the max opcode length into account so that doesn't need to be
383	* checked separately. */
384	uint32_t cbInstrBuf; /* 0x0c */
385	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
386	* This can be NULL if the page isn't mappable for some reason, in which
387	* case we'll do fallback stuff.
388	*
389	* If we're executing an instruction from a user specified buffer,
390	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
391	* aligned pointer but pointer to the user data.
392	*
393	* For instructions crossing pages, this will start on the first page and be
394	* advanced to the next page by the time we've decoded the instruction. This
395	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
396	*/
397	uint8_t const pbInstrBuf; / 0x10 */
398	# if ARCH_BITS == 32
399	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
400	# endif
401	/** The program counter corresponding to pbInstrBuf.
402	* This is set to a non-canonical address when we need to invalidate it. */
403	uint64_t uInstrBufPc; /* 0x18 */
404	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
405	* This takes the CS segment limit into account. */
406	uint16_t cbInstrBufTotal; /* 0x20 */
407	/** Offset into pbInstrBuf of the first byte of the current instruction.
408	* Can be negative to efficiently handle cross page instructions. */
409	int16_t offCurInstrStart; /* 0x22 */
410
411	/** The prefix mask (IEM_OP_PRF_XXX). */
412	uint32_t fPrefixes; /* 0x24 */
413	/** The extra REX ModR/M register field bit (REX.R << 3). */
414	uint8_t uRexReg; /* 0x28 */
415	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
416	* (REX.B << 3). */
417	uint8_t uRexB; /* 0x29 */
418	/** The extra REX SIB index field bit (REX.X << 3). */
419	uint8_t uRexIndex; /* 0x2a */
420
421	/** The effective segment register (X86_SREG_XXX). */
422	uint8_t iEffSeg; /* 0x2b */
423
424	/** The offset of the ModR/M byte relative to the start of the instruction. */
425	uint8_t offModRm; /* 0x2c */
426	#else
427	/** The size of what has currently been fetched into abOpcode. */
428	uint8_t cbOpcode; /* 0x08 */
429	/** The current offset into abOpcode. */
430	uint8_t offOpcode; /* 0x09 */
431	/** The offset of the ModR/M byte relative to the start of the instruction. */
432	uint8_t offModRm; /* 0x0a */
433
434	/** The effective segment register (X86_SREG_XXX). */
435	uint8_t iEffSeg; /* 0x0b */
436
437	/** The prefix mask (IEM_OP_PRF_XXX). */
438	uint32_t fPrefixes; /* 0x0c */
439	/** The extra REX ModR/M register field bit (REX.R << 3). */
440	uint8_t uRexReg; /* 0x10 */
441	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
442	* (REX.B << 3). */
443	uint8_t uRexB; /* 0x11 */
444	/** The extra REX SIB index field bit (REX.X << 3). */
445	uint8_t uRexIndex; /* 0x12 */
446
447	#endif
448
449	/** The effective operand mode. */
450	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
451	/** The default addressing mode. */
452	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
453	/** The effective addressing mode. */
454	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
455	/** The default operand mode. */
456	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
457
458	/** Prefix index (VEX.pp) for two byte and three byte tables. */
459	uint8_t idxPrefix; /* 0x31, 0x17 */
460	/** 3rd VEX/EVEX/XOP register.
461	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
462	uint8_t uVex3rdReg; /* 0x32, 0x18 */
463	/** The VEX/EVEX/XOP length field. */
464	uint8_t uVexLength; /* 0x33, 0x19 */
465	/** Additional EVEX stuff. */
466	uint8_t fEvexStuff; /* 0x34, 0x1a */
467
468	/** Explicit alignment padding. */
469	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
470	/** The FPU opcode (FOP). */
471	uint16_t uFpuOpcode; /* 0x36, 0x1c */
472	#ifndef IEM_WITH_CODE_TLB
473	/** Explicit alignment padding. */
474	uint8_t abAlignment2b[2]; /* 0x1e */
475	#endif
476
477	/** The opcode bytes. */
478	uint8_t abOpcode[15]; /* 0x48, 0x20 */
479	/** Explicit alignment padding. */
480	#ifdef IEM_WITH_CODE_TLB
481	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
482	#else
483	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
484	#endif
485	/** @} */
486
487
488	/** The flags of the current exception / interrupt. */
489	uint32_t fCurXcpt; /* 0x48, 0x48 */
490	/** The current exception / interrupt. */
491	uint8_t uCurXcpt;
492	/** Exception / interrupt recursion depth. */
493	int8_t cXcptRecursions;
494
495	/** The number of active guest memory mappings. */
496	uint8_t cActiveMappings;
497	/** The next unused mapping index. */
498	uint8_t iNextMapping;
499	/** Records for tracking guest memory mappings. */
500	struct
501	{
502	/** The address of the mapped bytes. */
503	void *pv;
504	#if defined(IN_RC) && HC_ARCH_BITS == 64
505	uint32_t u32Alignment3; /*< Alignment padding. /
506	#endif
507	/** The access flags (IEM_ACCESS_XXX).
508	* IEM_ACCESS_INVALID if the entry is unused. */
509	uint32_t fAccess;
510	#if HC_ARCH_BITS == 64
511	uint32_t u32Alignment4; /*< Alignment padding. /
512	#endif
513	} aMemMappings[3];
514
515	/** Locking records for the mapped memory. */
516	union
517	{
518	PGMPAGEMAPLOCK Lock;
519	uint64_t au64Padding[2];
520	} aMemMappingLocks[3];
521
522	/** Bounce buffer info.
523	* This runs in parallel to aMemMappings. */
524	struct
525	{
526	/** The physical address of the first byte. */
527	RTGCPHYS GCPhysFirst;
528	/** The physical address of the second page. */
529	RTGCPHYS GCPhysSecond;
530	/** The number of bytes in the first page. */
531	uint16_t cbFirst;
532	/** The number of bytes in the second page. */
533	uint16_t cbSecond;
534	/** Whether it's unassigned memory. */
535	bool fUnassigned;
536	/** Explicit alignment padding. */
537	bool afAlignment5[3];
538	} aMemBbMappings[3];
539
540	/** Bounce buffer storage.
541	* This runs in parallel to aMemMappings and aMemBbMappings. */
542	struct
543	{
544	uint8_t ab[512];
545	} aBounceBuffers[3];
546
547
548	/** Pointer set jump buffer - ring-3 context. */
549	R3PTRTYPE(jmp_buf *) pJmpBufR3;
550	/** Pointer set jump buffer - ring-0 context. */
551	R0PTRTYPE(jmp_buf *) pJmpBufR0;
552	/** Pointer set jump buffer - raw-mode context. */
553	RCPTRTYPE(jmp_buf *) pJmpBufRC;
554
555	/** @todo Should move this near @a fCurXcpt later. */
556	/** The error code for the current exception / interrupt. */
557	uint32_t uCurXcptErr;
558	/** The CR2 for the current exception / interrupt. */
559	uint64_t uCurXcptCr2;
560
561	/** @name Statistics
562	* @{ */
563	/** The number of instructions we've executed. */
564	uint32_t cInstructions;
565	/** The number of potential exits. */
566	uint32_t cPotentialExits;
567	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
568	* This may contain uncommitted writes. */
569	uint32_t cbWritten;
570	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
571	uint32_t cRetInstrNotImplemented;
572	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
573	uint32_t cRetAspectNotImplemented;
574	/** Counts informational statuses returned (other than VINF_SUCCESS). */
575	uint32_t cRetInfStatuses;
576	/** Counts other error statuses returned. */
577	uint32_t cRetErrStatuses;
578	/** Number of times rcPassUp has been used. */
579	uint32_t cRetPassUpStatus;
580	/** Number of times RZ left with instruction commit pending for ring-3. */
581	uint32_t cPendingCommit;
582	/** Number of long jumps. */
583	uint32_t cLongJumps;
584	uint32_t uAlignment6; /*< Alignment padding. /
585	/** @} */
586
587	/** @name Target CPU information.
588	* @{ */
589	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
590	/** The target CPU. */
591	uint32_t uTargetCpu;
592	#else
593	uint32_t u32TargetCpuPadding;
594	#endif
595	/** The CPU vendor. */
596	CPUMCPUVENDOR enmCpuVendor;
597	/** @} */
598
599	/** @name Host CPU information.
600	* @{ */
601	/** The CPU vendor. */
602	CPUMCPUVENDOR enmHostCpuVendor;
603	/** @} */
604
605	/** Counts RDMSR \#GP(0) LogRel(). */
606	uint8_t cLogRelRdMsr;
607	/** Counts WRMSR \#GP(0) LogRel(). */
608	uint8_t cLogRelWrMsr;
609	/** Alignment padding. */
610	uint8_t abAlignment8[HC_ARCH_BITS == 64 ? 46 : 14];
611
612	/** Data TLB.
613	* @remarks Must be 64-byte aligned. */
614	IEMTLB DataTlb;
615	/** Instruction TLB.
616	* @remarks Must be 64-byte aligned. */
617	IEMTLB CodeTlb;
618
619	/** Pointer to instruction statistics for raw-mode context (same as R0). */
620	RCPTRTYPE(PIEMINSTRSTATS) pStatsRC;
621	/** Alignment padding. */
622	RTRCPTR RCPtrPadding;
623	/** Pointer to instruction statistics for ring-0 context (same as RC). */
624	R0PTRTYPE(PIEMINSTRSTATS) pStatsR0;
625	/** Pointer to instruction statistics for non-ring-3 code. */
626	R3PTRTYPE(PIEMINSTRSTATS) pStatsCCR3;
627	/** Pointer to instruction statistics for ring-3 context. */
628	R3PTRTYPE(PIEMINSTRSTATS) pStatsR3;
629	} IEMCPU;
630	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
631	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
632	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
633	/** Pointer to the per-CPU IEM state. */
634	typedef IEMCPU *PIEMCPU;
635	/** Pointer to the const per-CPU IEM state. */
636	typedef IEMCPU const *PCIEMCPU;
637
638
639	/** @def IEM_GET_CTX
640	* Gets the guest CPU context for the calling EMT.
641	* @returns PCPUMCTX
642	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
643	*/
644	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
645
646	/** @def IEM_CTX_ASSERT
647	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
648	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
649	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
650	*/
651	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
652	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
653	(a_fExtrnMbz)))
654
655	/** @def IEM_CTX_IMPORT_RET
656	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
657	*
658	* Will call the keep to import the bits as needed.
659	*
660	* Returns on import failure.
661	*
662	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
663	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
664	*/
665	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
666	do { \
667	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
668	{ /* likely */ } \
669	else \
670	{ \
671	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
672	AssertRCReturn(rcCtxImport, rcCtxImport); \
673	} \
674	} while (0)
675
676	/** @def IEM_CTX_IMPORT_NORET
677	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
678	*
679	* Will call the keep to import the bits as needed.
680	*
681	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
682	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
683	*/
684	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
685	do { \
686	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
687	{ /* likely */ } \
688	else \
689	{ \
690	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
691	AssertLogRelRC(rcCtxImport); \
692	} \
693	} while (0)
694
695	/** @def IEM_CTX_IMPORT_JMP
696	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
697	*
698	* Will call the keep to import the bits as needed.
699	*
700	* Jumps on import failure.
701	*
702	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
703	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
704	*/
705	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
706	do { \
707	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
708	{ /* likely */ } \
709	else \
710	{ \
711	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
712	AssertRCStmt(rcCtxImport, longjmp(*pVCpu->iem.s.CTX_SUFF(pJmpBuf), rcCtxImport)); \
713	} \
714	} while (0)
715
716
717
718	/** Gets the current IEMTARGETCPU value.
719	* @returns IEMTARGETCPU value.
720	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
721	*/
722	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
723	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
724	#else
725	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
726	#endif
727
728	/** @def Gets the instruction length. */
729	#ifdef IEM_WITH_CODE_TLB
730	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
731	#else
732	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
733	#endif
734
735
736	/** @name IEM_ACCESS_XXX - Access details.
737	* @{ */
738	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
739	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
740	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
741	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
742	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
743	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
744	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
745	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
746	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
747	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
748	/** The writes are partial, so if initialize the bounce buffer with the
749	* orignal RAM content. */
750	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
751	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
752	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
753	/** Bounce buffer with ring-3 write pending, first page. */
754	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
755	/** Bounce buffer with ring-3 write pending, second page. */
756	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
757	/** Valid bit mask. */
758	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00000fff)
759	/** Read+write data alias. */
760	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
761	/** Write data alias. */
762	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
763	/** Read data alias. */
764	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
765	/** Instruction fetch alias. */
766	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
767	/** Stack write alias. */
768	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
769	/** Stack read alias. */
770	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
771	/** Stack read+write alias. */
772	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
773	/** Read system table alias. */
774	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
775	/** Read+write system table alias. */
776	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
777	/** @} */
778
779	/** @name Prefix constants (IEMCPU::fPrefixes)
780	* @{ */
781	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
782	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
783	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
784	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
785	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
786	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
787	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
788
789	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
790	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
791	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
792
793	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
794	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
795	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
796
797	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
798	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
799	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
800	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
801	/** Mask with all the REX prefix flags.
802	* This is generally for use when needing to undo the REX prefixes when they
803	* are followed legacy prefixes and therefore does not immediately preceed
804	* the first opcode byte.
805	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
806	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
807
808	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
809	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
810	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
811	/** @} */
812
813	/** @name IEMOPFORM_XXX - Opcode forms
814	* @note These are ORed together with IEMOPHINT_XXX.
815	* @{ */
816	/** ModR/M: reg, r/m */
817	#define IEMOPFORM_RM 0
818	/** ModR/M: reg, r/m (register) */
819	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
820	/** ModR/M: reg, r/m (memory) */
821	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
822	/** ModR/M: r/m, reg */
823	#define IEMOPFORM_MR 1
824	/** ModR/M: r/m (register), reg */
825	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
826	/** ModR/M: r/m (memory), reg */
827	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
828	/** ModR/M: r/m only */
829	#define IEMOPFORM_M 2
830	/** ModR/M: r/m only (register). */
831	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
832	/** ModR/M: r/m only (memory). */
833	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
834	/** ModR/M: reg only */
835	#define IEMOPFORM_R 3
836
837	/** VEX+ModR/M: reg, r/m */
838	#define IEMOPFORM_VEX_RM 4
839	/** VEX+ModR/M: reg, r/m (register) */
840	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
841	/** VEX+ModR/M: reg, r/m (memory) */
842	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
843	/** VEX+ModR/M: r/m, reg */
844	#define IEMOPFORM_VEX_MR 5
845	/** VEX+ModR/M: r/m (register), reg */
846	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
847	/** VEX+ModR/M: r/m (memory), reg */
848	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
849	/** VEX+ModR/M: r/m only */
850	#define IEMOPFORM_VEX_M 6
851	/** VEX+ModR/M: r/m only (register). */
852	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
853	/** VEX+ModR/M: r/m only (memory). */
854	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
855	/** VEX+ModR/M: reg only */
856	#define IEMOPFORM_VEX_R 7
857	/** VEX+ModR/M: reg, vvvv, r/m */
858	#define IEMOPFORM_VEX_RVM 8
859	/** VEX+ModR/M: reg, vvvv, r/m (register). */
860	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
861	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
862	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
863	/** VEX+ModR/M: r/m, vvvv, reg */
864	#define IEMOPFORM_VEX_MVR 9
865	/** VEX+ModR/M: r/m, vvvv, reg (register) */
866	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
867	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
868	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
869
870	/** Fixed register instruction, no R/M. */
871	#define IEMOPFORM_FIXED 16
872
873	/** The r/m is a register. */
874	#define IEMOPFORM_MOD3 RT_BIT_32(8)
875	/** The r/m is a memory access. */
876	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
877	/** @} */
878
879	/** @name IEMOPHINT_XXX - Additional Opcode Hints
880	* @note These are ORed together with IEMOPFORM_XXX.
881	* @{ */
882	/** Ignores the operand size prefix (66h). */
883	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
884	/** Ignores REX.W (aka WIG). */
885	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
886	/** Both the operand size prefixes (66h + REX.W) are ignored. */
887	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
888	/** Allowed with the lock prefix. */
889	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
890	/** The VEX.L value is ignored (aka LIG). */
891	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
892	/** The VEX.L value must be zero (i.e. 128-bit width only). */
893	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
894
895	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
896	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
897	/** @} */
898
899	/**
900	* Possible hardware task switch sources.
901	*/
902	typedef enum IEMTASKSWITCH
903	{
904	/** Task switch caused by an interrupt/exception. */
905	IEMTASKSWITCH_INT_XCPT = 1,
906	/** Task switch caused by a far CALL. */
907	IEMTASKSWITCH_CALL,
908	/** Task switch caused by a far JMP. */
909	IEMTASKSWITCH_JUMP,
910	/** Task switch caused by an IRET. */
911	IEMTASKSWITCH_IRET
912	} IEMTASKSWITCH;
913	AssertCompileSize(IEMTASKSWITCH, 4);
914
915	/**
916	* Possible CrX load (write) sources.
917	*/
918	typedef enum IEMACCESSCRX
919	{
920	/** CrX access caused by 'mov crX' instruction. */
921	IEMACCESSCRX_MOV_CRX,
922	/** CrX (CR0) write caused by 'lmsw' instruction. */
923	IEMACCESSCRX_LMSW,
924	/** CrX (CR0) write caused by 'clts' instruction. */
925	IEMACCESSCRX_CLTS,
926	/** CrX (CR0) read caused by 'smsw' instruction. */
927	IEMACCESSCRX_SMSW
928	} IEMACCESSCRX;
929
930
931	/**
932	* Indicates to the verifier that the given flag set is undefined.
933	*
934	* Can be invoked again to add more flags.
935	*
936	* This is a NOOP if the verifier isn't compiled in.
937	*
938	* @note We're temporarily keeping this until code is converted to new
939	* disassembler style opcode handling.
940	*/
941	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
942
943
944	/** @def IEM_DECL_IMPL_TYPE
945	* For typedef'ing an instruction implementation function.
946	*
947	* @param a_RetType The return type.
948	* @param a_Name The name of the type.
949	* @param a_ArgList The argument list enclosed in parentheses.
950	*/
951
952	/** @def IEM_DECL_IMPL_DEF
953	* For defining an instruction implementation function.
954	*
955	* @param a_RetType The return type.
956	* @param a_Name The name of the type.
957	* @param a_ArgList The argument list enclosed in parentheses.
958	*/
959
960	#if defined(__GNUC__) && defined(RT_ARCH_X86)
961	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
962	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
963	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
964	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
965
966	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
967	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
968	a_RetType (__fastcall a_Name) a_ArgList
969	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
970	a_RetType __fastcall a_Name a_ArgList
971
972	#else
973	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
974	a_RetType (VBOXCALL a_Name) a_ArgList
975	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
976	a_RetType VBOXCALL a_Name a_ArgList
977
978	#endif
979
980	/** @name Arithmetic assignment operations on bytes (binary).
981	* @{ */
982	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
983	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
984	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
985	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
986	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
987	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
988	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
989	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
990	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
991	/** @} */
992
993	/** @name Arithmetic assignment operations on words (binary).
994	* @{ */
995	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
996	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
997	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
998	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
999	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1000	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1001	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1002	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1003	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1004	/** @} */
1005
1006	/** @name Arithmetic assignment operations on double words (binary).
1007	* @{ */
1008	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1009	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1010	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1011	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1012	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1013	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1014	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1015	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1016	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1017	/** @} */
1018
1019	/** @name Arithmetic assignment operations on quad words (binary).
1020	* @{ */
1021	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1022	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1023	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1024	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1025	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1026	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1027	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1028	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1029	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1030	/** @} */
1031
1032	/** @name Compare operations (thrown in with the binary ops).
1033	* @{ */
1034	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1035	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1036	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1037	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1038	/** @} */
1039
1040	/** @name Test operations (thrown in with the binary ops).
1041	* @{ */
1042	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1043	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1044	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1045	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1046	/** @} */
1047
1048	/** @name Bit operations operations (thrown in with the binary ops).
1049	* @{ */
1050	FNIEMAIMPLBINU16 iemAImpl_bt_u16, iemAImpl_bt_u16_locked;
1051	FNIEMAIMPLBINU32 iemAImpl_bt_u32, iemAImpl_bt_u32_locked;
1052	FNIEMAIMPLBINU64 iemAImpl_bt_u64, iemAImpl_bt_u64_locked;
1053	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1054	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1055	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1056	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1057	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1058	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1059	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1060	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1061	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1062	/** @} */
1063
1064	/** @name Exchange memory with register operations.
1065	* @{ */
1066	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8, (uint8_t pu8Mem, uint8_t pu8Reg));
1067	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16,(uint16_t pu16Mem, uint16_t pu16Reg));
1068	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32,(uint32_t pu32Mem, uint32_t pu32Reg));
1069	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64,(uint64_t pu64Mem, uint64_t pu64Reg));
1070	/** @} */
1071
1072	/** @name Exchange and add operations.
1073	* @{ */
1074	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1075	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1076	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1077	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1078	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1079	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1080	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1081	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1082	/** @} */
1083
1084	/** @name Compare and exchange.
1085	* @{ */
1086	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1087	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1088	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1089	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1090	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1091	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1092	#ifdef RT_ARCH_X86
1093	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1094	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1095	#else
1096	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1097	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1098	#endif
1099	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1100	uint32_t *pEFlags));
1101	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1102	uint32_t *pEFlags));
1103	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1104	uint32_t *pEFlags));
1105	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1106	uint32_t *pEFlags));
1107	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1108	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1109	/** @} */
1110
1111	/** @name Memory ordering
1112	* @{ */
1113	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1114	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1115	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1116	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1117	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1118	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1119	/** @} */
1120
1121	/** @name Double precision shifts
1122	* @{ */
1123	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1124	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1125	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1126	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1127	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1128	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1129	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16;
1130	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32;
1131	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64;
1132	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16;
1133	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32;
1134	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64;
1135	/** @} */
1136
1137
1138	/** @name Bit search operations (thrown in with the binary ops).
1139	* @{ */
1140	FNIEMAIMPLBINU16 iemAImpl_bsf_u16;
1141	FNIEMAIMPLBINU32 iemAImpl_bsf_u32;
1142	FNIEMAIMPLBINU64 iemAImpl_bsf_u64;
1143	FNIEMAIMPLBINU16 iemAImpl_bsr_u16;
1144	FNIEMAIMPLBINU32 iemAImpl_bsr_u32;
1145	FNIEMAIMPLBINU64 iemAImpl_bsr_u64;
1146	/** @} */
1147
1148	/** @name Signed multiplication operations (thrown in with the binary ops).
1149	* @{ */
1150	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16;
1151	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32;
1152	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64;
1153	/** @} */
1154
1155	/** @name Arithmetic assignment operations on bytes (unary).
1156	* @{ */
1157	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1158	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1159	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1160	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1161	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1162	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1163	/** @} */
1164
1165	/** @name Arithmetic assignment operations on words (unary).
1166	* @{ */
1167	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1168	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1169	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1170	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1171	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1172	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1173	/** @} */
1174
1175	/** @name Arithmetic assignment operations on double words (unary).
1176	* @{ */
1177	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1178	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1179	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1180	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1181	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1182	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1183	/** @} */
1184
1185	/** @name Arithmetic assignment operations on quad words (unary).
1186	* @{ */
1187	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1188	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1189	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1190	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1191	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1192	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1193	/** @} */
1194
1195
1196	/** @name Shift operations on bytes (Group 2).
1197	* @{ */
1198	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1199	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1200	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8;
1201	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8;
1202	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8;
1203	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8;
1204	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8;
1205	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8;
1206	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8;
1207	/** @} */
1208
1209	/** @name Shift operations on words (Group 2).
1210	* @{ */
1211	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1212	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1213	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16;
1214	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16;
1215	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16;
1216	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16;
1217	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16;
1218	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16;
1219	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16;
1220	/** @} */
1221
1222	/** @name Shift operations on double words (Group 2).
1223	* @{ */
1224	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1225	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1226	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32;
1227	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32;
1228	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32;
1229	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32;
1230	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32;
1231	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32;
1232	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32;
1233	/** @} */
1234
1235	/** @name Shift operations on words (Group 2).
1236	* @{ */
1237	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1238	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1239	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64;
1240	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64;
1241	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64;
1242	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64;
1243	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64;
1244	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64;
1245	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64;
1246	/** @} */
1247
1248	/** @name Multiplication and division operations.
1249	* @{ */
1250	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1251	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1252	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_imul_u8;
1253	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_idiv_u8;
1254
1255	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1256	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1257	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_imul_u16;
1258	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_idiv_u16;
1259
1260	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1261	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1262	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_imul_u32;
1263	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_idiv_u32;
1264
1265	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1266	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1267	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_imul_u64;
1268	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_idiv_u64;
1269	/** @} */
1270
1271	/** @name Byte Swap.
1272	* @{ */
1273	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1274	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1275	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1276	/** @} */
1277
1278	/** @name Misc.
1279	* @{ */
1280	FNIEMAIMPLBINU16 iemAImpl_arpl;
1281	/** @} */
1282
1283
1284	/** @name FPU operations taking a 32-bit float argument
1285	* @{ */
1286	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1287	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1288	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1289
1290	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1291	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1292	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1293
1294	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1295	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1296	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1297	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1298	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1299	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1300	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1301
1302	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1303	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1304	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1305	/** @} */
1306
1307	/** @name FPU operations taking a 64-bit float argument
1308	* @{ */
1309	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1310	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1311	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1312
1313	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1314	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1315	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1316	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1317	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1318	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1319
1320	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1321	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1322	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1323	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1324	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1325	/** @} */
1326
1327	/** @name FPU operations taking a 80-bit float argument
1328	* @{ */
1329	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1330	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1331	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1332	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1333	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1334	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1335	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1336	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1337	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1338	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1339	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1340	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1341
1342	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80;
1343	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80;
1344	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80;
1345
1346	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1347	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1348	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1349	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1350	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1351
1352	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1353	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1354	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1355	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1356	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1357
1358	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1359	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1360	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1361	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1362	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80;
1363	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1364	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1365	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80;
1366	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80;
1367
1368	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1369	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1370	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1371	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1372
1373	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1374	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1375	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1376	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1377	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1378	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1379	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1380	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1381	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1382
1383	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1384	PCRTFLOAT80U pr80Val));
1385	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1386	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80;
1387	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1388	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80;
1389
1390	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1391	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1392	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1393
1394	/** @} */
1395
1396	/** @name FPU operations taking a 16-bit signed integer argument
1397	* @{ */
1398	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1399	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1400	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1401
1402	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1403	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1404	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1405	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1406	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1407	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1408
1409	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1410	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1411
1412	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1413	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1414	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1415	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1416	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1417	/** @} */
1418
1419	/** @name FPU operations taking a 32-bit signed integer argument
1420	* @{ */
1421	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1422	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1423	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1424
1425	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1426	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1427	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1428	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1429	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1430	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1431
1432	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1433	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1434
1435	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1436	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1437	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1438	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1439	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1440	/** @} */
1441
1442	/** @name FPU operations taking a 64-bit signed integer argument
1443	* @{ */
1444	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1445	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1446	typedef FNIEMAIMPLFPUI64 *PFNIEMAIMPLFPUI64;
1447
1448	FNIEMAIMPLFPUI64 iemAImpl_fiadd_r80_by_i64;
1449	FNIEMAIMPLFPUI64 iemAImpl_fimul_r80_by_i64;
1450	FNIEMAIMPLFPUI64 iemAImpl_fisub_r80_by_i64;
1451	FNIEMAIMPLFPUI64 iemAImpl_fisubr_r80_by_i64;
1452	FNIEMAIMPLFPUI64 iemAImpl_fidiv_r80_by_i64;
1453	FNIEMAIMPLFPUI64 iemAImpl_fidivr_r80_by_i64;
1454
1455	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1456	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1457
1458	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1459	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1460	int64_t *pi64Val, PCRTFLOAT80U pr80Val));
1461	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1462	int64_t *pi32Val, PCRTFLOAT80U pr80Val));
1463	/** @} */
1464
1465
1466	/** Temporary type representing a 256-bit vector register. */
1467	typedef struct {uint64_t au64[4]; } IEMVMM256;
1468	/** Temporary type pointing to a 256-bit vector register. */
1469	typedef IEMVMM256 *PIEMVMM256;
1470	/** Temporary type pointing to a const 256-bit vector register. */
1471	typedef IEMVMM256 *PCIEMVMM256;
1472
1473
1474	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1475	* @{ */
1476	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1477	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1478	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1479	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1480	FNIEMAIMPLMEDIAF2U64 iemAImpl_pxor_u64, iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1481	FNIEMAIMPLMEDIAF2U128 iemAImpl_pxor_u128, iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1482	/** @} */
1483
1484	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1485	* @{ */
1486	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src));
1487	typedef FNIEMAIMPLMEDIAF1L1U64 *PFNIEMAIMPLMEDIAF1L1U64;
1488	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src));
1489	typedef FNIEMAIMPLMEDIAF1L1U128 *PFNIEMAIMPLMEDIAF1L1U128;
1490	FNIEMAIMPLMEDIAF1L1U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1491	FNIEMAIMPLMEDIAF1L1U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1492	/** @} */
1493
1494	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
1495	* @{ */
1496	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1497	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF1H1U64;
1498	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1499	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF1H1U128;
1500	FNIEMAIMPLMEDIAF1H1U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
1501	FNIEMAIMPLMEDIAF1H1U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
1502	/** @} */
1503
1504	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
1505	* @{ */
1506	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUF,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst,
1507	PCRTUINT128U pu128Src, uint8_t bEvil));
1508	typedef FNIEMAIMPLMEDIAPSHUF *PFNIEMAIMPLMEDIAPSHUF;
1509	FNIEMAIMPLMEDIAPSHUF iemAImpl_pshufhw, iemAImpl_pshuflw, iemAImpl_pshufd;
1510	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil));
1511	/** @} */
1512
1513	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
1514	* @{ */
1515	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1516	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src));
1517	/** @} */
1518
1519	/** @name Media (SSE/MMX/AVX) operation: Sort this later
1520	* @{ */
1521	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1522	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1523	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc));
1524
1525	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1526	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1527	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1528	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1529
1530	/** @} */
1531
1532
1533	/** @name Function tables.
1534	* @{
1535	*/
1536
1537	/**
1538	* Function table for a binary operator providing implementation based on
1539	* operand size.
1540	*/
1541	typedef struct IEMOPBINSIZES
1542	{
1543	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
1544	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
1545	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
1546	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
1547	} IEMOPBINSIZES;
1548	/** Pointer to a binary operator function table. */
1549	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
1550
1551
1552	/**
1553	* Function table for a unary operator providing implementation based on
1554	* operand size.
1555	*/
1556	typedef struct IEMOPUNARYSIZES
1557	{
1558	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
1559	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
1560	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
1561	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
1562	} IEMOPUNARYSIZES;
1563	/** Pointer to a unary operator function table. */
1564	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
1565
1566
1567	/**
1568	* Function table for a shift operator providing implementation based on
1569	* operand size.
1570	*/
1571	typedef struct IEMOPSHIFTSIZES
1572	{
1573	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
1574	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
1575	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
1576	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
1577	} IEMOPSHIFTSIZES;
1578	/** Pointer to a shift operator function table. */
1579	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
1580
1581
1582	/**
1583	* Function table for a multiplication or division operation.
1584	*/
1585	typedef struct IEMOPMULDIVSIZES
1586	{
1587	PFNIEMAIMPLMULDIVU8 pfnU8;
1588	PFNIEMAIMPLMULDIVU16 pfnU16;
1589	PFNIEMAIMPLMULDIVU32 pfnU32;
1590	PFNIEMAIMPLMULDIVU64 pfnU64;
1591	} IEMOPMULDIVSIZES;
1592	/** Pointer to a multiplication or division operation function table. */
1593	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
1594
1595
1596	/**
1597	* Function table for a double precision shift operator providing implementation
1598	* based on operand size.
1599	*/
1600	typedef struct IEMOPSHIFTDBLSIZES
1601	{
1602	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
1603	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
1604	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
1605	} IEMOPSHIFTDBLSIZES;
1606	/** Pointer to a double precision shift function table. */
1607	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
1608
1609
1610	/**
1611	* Function table for media instruction taking two full sized media registers,
1612	* optionally the 2nd being a memory reference (only modifying the first op.)
1613	*/
1614	typedef struct IEMOPMEDIAF2
1615	{
1616	PFNIEMAIMPLMEDIAF2U64 pfnU64;
1617	PFNIEMAIMPLMEDIAF2U128 pfnU128;
1618	} IEMOPMEDIAF2;
1619	/** Pointer to a media operation function table for full sized ops. */
1620	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
1621
1622	/**
1623	* Function table for media instruction taking taking one full and one lower
1624	* half media register.
1625	*/
1626	typedef struct IEMOPMEDIAF1L1
1627	{
1628	PFNIEMAIMPLMEDIAF1L1U64 pfnU64;
1629	PFNIEMAIMPLMEDIAF1L1U128 pfnU128;
1630	} IEMOPMEDIAF1L1;
1631	/** Pointer to a media operation function table for lowhalf+lowhalf -> full. */
1632	typedef IEMOPMEDIAF1L1 const *PCIEMOPMEDIAF1L1;
1633
1634	/**
1635	* Function table for media instruction taking taking one full and one high half
1636	* media register.
1637	*/
1638	typedef struct IEMOPMEDIAF1H1
1639	{
1640	PFNIEMAIMPLMEDIAF1H1U64 pfnU64;
1641	PFNIEMAIMPLMEDIAF1H1U128 pfnU128;
1642	} IEMOPMEDIAF1H1;
1643	/** Pointer to a media operation function table for hihalf+hihalf -> full. */
1644	typedef IEMOPMEDIAF1H1 const *PCIEMOPMEDIAF1H1;
1645
1646
1647	/** @} */
1648
1649
1650	/** @name C instruction implementations for anything slightly complicated.
1651	* @{ */
1652
1653	/**
1654	* For typedef'ing or declaring a C instruction implementation function taking
1655	* no extra arguments.
1656	*
1657	* @param a_Name The name of the type.
1658	*/
1659	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
1660	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1661	/**
1662	* For defining a C instruction implementation function taking no extra
1663	* arguments.
1664	*
1665	* @param a_Name The name of the function
1666	*/
1667	# define IEM_CIMPL_DEF_0(a_Name) \
1668	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1669	/**
1670	* For calling a C instruction implementation function taking no extra
1671	* arguments.
1672	*
1673	* This special call macro adds default arguments to the call and allow us to
1674	* change these later.
1675	*
1676	* @param a_fn The name of the function.
1677	*/
1678	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
1679
1680	/**
1681	* For typedef'ing or declaring a C instruction implementation function taking
1682	* one extra argument.
1683	*
1684	* @param a_Name The name of the type.
1685	* @param a_Type0 The argument type.
1686	* @param a_Arg0 The argument name.
1687	*/
1688	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
1689	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1690	/**
1691	* For defining a C instruction implementation function taking one extra
1692	* argument.
1693	*
1694	* @param a_Name The name of the function
1695	* @param a_Type0 The argument type.
1696	* @param a_Arg0 The argument name.
1697	*/
1698	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
1699	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1700	/**
1701	* For calling a C instruction implementation function taking one extra
1702	* argument.
1703	*
1704	* This special call macro adds default arguments to the call and allow us to
1705	* change these later.
1706	*
1707	* @param a_fn The name of the function.
1708	* @param a0 The name of the 1st argument.
1709	*/
1710	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
1711
1712	/**
1713	* For typedef'ing or declaring a C instruction implementation function taking
1714	* two extra arguments.
1715	*
1716	* @param a_Name The name of the type.
1717	* @param a_Type0 The type of the 1st argument
1718	* @param a_Arg0 The name of the 1st argument.
1719	* @param a_Type1 The type of the 2nd argument.
1720	* @param a_Arg1 The name of the 2nd argument.
1721	*/
1722	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1723	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1724	/**
1725	* For defining a C instruction implementation function taking two extra
1726	* arguments.
1727	*
1728	* @param a_Name The name of the function.
1729	* @param a_Type0 The type of the 1st argument
1730	* @param a_Arg0 The name of the 1st argument.
1731	* @param a_Type1 The type of the 2nd argument.
1732	* @param a_Arg1 The name of the 2nd argument.
1733	*/
1734	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1735	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1736	/**
1737	* For calling a C instruction implementation function taking two extra
1738	* arguments.
1739	*
1740	* This special call macro adds default arguments to the call and allow us to
1741	* change these later.
1742	*
1743	* @param a_fn The name of the function.
1744	* @param a0 The name of the 1st argument.
1745	* @param a1 The name of the 2nd argument.
1746	*/
1747	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
1748
1749	/**
1750	* For typedef'ing or declaring a C instruction implementation function taking
1751	* three extra arguments.
1752	*
1753	* @param a_Name The name of the type.
1754	* @param a_Type0 The type of the 1st argument
1755	* @param a_Arg0 The name of the 1st argument.
1756	* @param a_Type1 The type of the 2nd argument.
1757	* @param a_Arg1 The name of the 2nd argument.
1758	* @param a_Type2 The type of the 3rd argument.
1759	* @param a_Arg2 The name of the 3rd argument.
1760	*/
1761	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1762	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1763	/**
1764	* For defining a C instruction implementation function taking three extra
1765	* arguments.
1766	*
1767	* @param a_Name The name of the function.
1768	* @param a_Type0 The type of the 1st argument
1769	* @param a_Arg0 The name of the 1st argument.
1770	* @param a_Type1 The type of the 2nd argument.
1771	* @param a_Arg1 The name of the 2nd argument.
1772	* @param a_Type2 The type of the 3rd argument.
1773	* @param a_Arg2 The name of the 3rd argument.
1774	*/
1775	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1776	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1777	/**
1778	* For calling a C instruction implementation function taking three extra
1779	* arguments.
1780	*
1781	* This special call macro adds default arguments to the call and allow us to
1782	* change these later.
1783	*
1784	* @param a_fn The name of the function.
1785	* @param a0 The name of the 1st argument.
1786	* @param a1 The name of the 2nd argument.
1787	* @param a2 The name of the 3rd argument.
1788	*/
1789	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
1790
1791
1792	/**
1793	* For typedef'ing or declaring a C instruction implementation function taking
1794	* four extra arguments.
1795	*
1796	* @param a_Name The name of the type.
1797	* @param a_Type0 The type of the 1st argument
1798	* @param a_Arg0 The name of the 1st argument.
1799	* @param a_Type1 The type of the 2nd argument.
1800	* @param a_Arg1 The name of the 2nd argument.
1801	* @param a_Type2 The type of the 3rd argument.
1802	* @param a_Arg2 The name of the 3rd argument.
1803	* @param a_Type3 The type of the 4th argument.
1804	* @param a_Arg3 The name of the 4th argument.
1805	*/
1806	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1807	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
1808	/**
1809	* For defining a C instruction implementation function taking four extra
1810	* arguments.
1811	*
1812	* @param a_Name The name of the function.
1813	* @param a_Type0 The type of the 1st argument
1814	* @param a_Arg0 The name of the 1st argument.
1815	* @param a_Type1 The type of the 2nd argument.
1816	* @param a_Arg1 The name of the 2nd argument.
1817	* @param a_Type2 The type of the 3rd argument.
1818	* @param a_Arg2 The name of the 3rd argument.
1819	* @param a_Type3 The type of the 4th argument.
1820	* @param a_Arg3 The name of the 4th argument.
1821	*/
1822	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1823	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1824	a_Type2 a_Arg2, a_Type3 a_Arg3))
1825	/**
1826	* For calling a C instruction implementation function taking four extra
1827	* arguments.
1828	*
1829	* This special call macro adds default arguments to the call and allow us to
1830	* change these later.
1831	*
1832	* @param a_fn The name of the function.
1833	* @param a0 The name of the 1st argument.
1834	* @param a1 The name of the 2nd argument.
1835	* @param a2 The name of the 3rd argument.
1836	* @param a3 The name of the 4th argument.
1837	*/
1838	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
1839
1840
1841	/**
1842	* For typedef'ing or declaring a C instruction implementation function taking
1843	* five extra arguments.
1844	*
1845	* @param a_Name The name of the type.
1846	* @param a_Type0 The type of the 1st argument
1847	* @param a_Arg0 The name of the 1st argument.
1848	* @param a_Type1 The type of the 2nd argument.
1849	* @param a_Arg1 The name of the 2nd argument.
1850	* @param a_Type2 The type of the 3rd argument.
1851	* @param a_Arg2 The name of the 3rd argument.
1852	* @param a_Type3 The type of the 4th argument.
1853	* @param a_Arg3 The name of the 4th argument.
1854	* @param a_Type4 The type of the 5th argument.
1855	* @param a_Arg4 The name of the 5th argument.
1856	*/
1857	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1858	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1859	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1860	a_Type3 a_Arg3, a_Type4 a_Arg4))
1861	/**
1862	* For defining a C instruction implementation function taking five extra
1863	* arguments.
1864	*
1865	* @param a_Name The name of the function.
1866	* @param a_Type0 The type of the 1st argument
1867	* @param a_Arg0 The name of the 1st argument.
1868	* @param a_Type1 The type of the 2nd argument.
1869	* @param a_Arg1 The name of the 2nd argument.
1870	* @param a_Type2 The type of the 3rd argument.
1871	* @param a_Arg2 The name of the 3rd argument.
1872	* @param a_Type3 The type of the 4th argument.
1873	* @param a_Arg3 The name of the 4th argument.
1874	* @param a_Type4 The type of the 5th argument.
1875	* @param a_Arg4 The name of the 5th argument.
1876	*/
1877	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1878	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1879	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1880	a_Type3 a_Arg3, a_Type4 a_Arg4))
1881	/**
1882	* For calling a C instruction implementation function taking five extra
1883	* arguments.
1884	*
1885	* This special call macro adds default arguments to the call and allow us to
1886	* change these later.
1887	*
1888	* @param a_fn The name of the function.
1889	* @param a0 The name of the 1st argument.
1890	* @param a1 The name of the 2nd argument.
1891	* @param a2 The name of the 3rd argument.
1892	* @param a3 The name of the 4th argument.
1893	* @param a4 The name of the 5th argument.
1894	*/
1895	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
1896
1897	/** @} */
1898
1899
1900	/** @} */
1901
1902	RT_C_DECLS_END
1903
1904	#endif
1905

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 74442

Download in other formats: