IEMInternal.h@ 80055

Last change on this file since 80055 was 80055, checked in by vboxsync, 5 years ago
Main: Kicking out raw-mode - CPUMRaw*. bugref:9517
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1	/* $Id: IEMInternal.h 80055 2019-07-29 21:36:45Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
19	#define VMM_INCLUDED_SRC_include_IEMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/vmm/cpum.h>
25	#include <VBox/vmm/iem.h>
26	#include <VBox/vmm/pgm.h>
27	#include <VBox/vmm/stam.h>
28	#include <VBox/param.h>
29
30	#include <setjmp.h>
31
32
33	RT_C_DECLS_BEGIN
34
35
36	/** @defgroup grp_iem_int Internals
37	* @ingroup grp_iem
38	* @internal
39	* @{
40	*/
41
42	/** For expanding symbol in slickedit and other products tagging and
43	* crossreferencing IEM symbols. */
44	#ifndef IEM_STATIC
45	# define IEM_STATIC static
46	#endif
47
48	/** @def IEM_WITH_3DNOW
49	* Includes the 3DNow decoding. */
50	#define IEM_WITH_3DNOW
51
52	/** @def IEM_WITH_THREE_0F_38
53	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
54	#define IEM_WITH_THREE_0F_38
55
56	/** @def IEM_WITH_THREE_0F_3A
57	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
58	#define IEM_WITH_THREE_0F_3A
59
60	/** @def IEM_WITH_VEX
61	* Includes the VEX decoding. */
62	#define IEM_WITH_VEX
63
64	/** @def IEM_CFG_TARGET_CPU
65	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
66	*
67	* By default we allow this to be configured by the user via the
68	* CPUM/GuestCpuName config string, but this comes at a slight cost during
69	* decoding. So, for applications of this code where there is no need to
70	* be dynamic wrt target CPU, just modify this define.
71	*/
72	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
73	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
74	#endif
75
76
77	//#define IEM_WITH_CODE_TLB// - work in progress
78
79
80	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
81	/** Instruction statistics. */
82	typedef struct IEMINSTRSTATS
83	{
84	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
85	# include "IEMInstructionStatisticsTmpl.h"
86	# undef IEM_DO_INSTR_STAT
87	} IEMINSTRSTATS;
88	#else
89	struct IEMINSTRSTATS;
90	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
91	#endif
92	/** Pointer to IEM instruction statistics. */
93	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
94
95	/** Finish and move to types.h */
96	typedef union
97	{
98	uint32_t u32;
99	} RTFLOAT32U;
100	typedef RTFLOAT32U *PRTFLOAT32U;
101	typedef RTFLOAT32U const *PCRTFLOAT32U;
102
103
104	/**
105	* Extended operand mode that includes a representation of 8-bit.
106	*
107	* This is used for packing down modes when invoking some C instruction
108	* implementations.
109	*/
110	typedef enum IEMMODEX
111	{
112	IEMMODEX_16BIT = IEMMODE_16BIT,
113	IEMMODEX_32BIT = IEMMODE_32BIT,
114	IEMMODEX_64BIT = IEMMODE_64BIT,
115	IEMMODEX_8BIT
116	} IEMMODEX;
117	AssertCompileSize(IEMMODEX, 4);
118
119
120	/**
121	* Branch types.
122	*/
123	typedef enum IEMBRANCH
124	{
125	IEMBRANCH_JUMP = 1,
126	IEMBRANCH_CALL,
127	IEMBRANCH_TRAP,
128	IEMBRANCH_SOFTWARE_INT,
129	IEMBRANCH_HARDWARE_INT
130	} IEMBRANCH;
131	AssertCompileSize(IEMBRANCH, 4);
132
133
134	/**
135	* INT instruction types.
136	*/
137	typedef enum IEMINT
138	{
139	/** INT n instruction (opcode 0xcd imm). */
140	IEMINT_INTN = 0,
141	/** Single byte INT3 instruction (opcode 0xcc). */
142	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
143	/** Single byte INTO instruction (opcode 0xce). */
144	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
145	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
146	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
147	} IEMINT;
148	AssertCompileSize(IEMINT, 4);
149
150
151	/**
152	* A FPU result.
153	*/
154	typedef struct IEMFPURESULT
155	{
156	/** The output value. */
157	RTFLOAT80U r80Result;
158	/** The output status. */
159	uint16_t FSW;
160	} IEMFPURESULT;
161	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
162	/** Pointer to a FPU result. */
163	typedef IEMFPURESULT *PIEMFPURESULT;
164	/** Pointer to a const FPU result. */
165	typedef IEMFPURESULT const *PCIEMFPURESULT;
166
167
168	/**
169	* A FPU result consisting of two output values and FSW.
170	*/
171	typedef struct IEMFPURESULTTWO
172	{
173	/** The first output value. */
174	RTFLOAT80U r80Result1;
175	/** The output status. */
176	uint16_t FSW;
177	/** The second output value. */
178	RTFLOAT80U r80Result2;
179	} IEMFPURESULTTWO;
180	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
181	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
182	/** Pointer to a FPU result consisting of two output values and FSW. */
183	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
184	/** Pointer to a const FPU result consisting of two output values and FSW. */
185	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
186
187
188	/**
189	* IEM TLB entry.
190	*
191	* Lookup assembly:
192	* @code{.asm}
193	; Calculate tag.
194	mov rax, [VA]
195	shl rax, 16
196	shr rax, 16 + X86_PAGE_SHIFT
197	or rax, [uTlbRevision]
198
199	; Do indexing.
200	movzx ecx, al
201	lea rcx, [pTlbEntries + rcx]
202
203	; Check tag.
204	cmp [rcx + IEMTLBENTRY.uTag], rax
205	jne .TlbMiss
206
207	; Check access.
208	movsx rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
209	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
210	cmp rax, [uTlbPhysRev]
211	jne .TlbMiss
212
213	; Calc address and we're done.
214	mov eax, X86_PAGE_OFFSET_MASK
215	and eax, [VA]
216	or rax, [rcx + IEMTLBENTRY.pMappingR3]
217	%ifdef VBOX_WITH_STATISTICS
218	inc qword [cTlbHits]
219	%endif
220	jmp .Done
221
222	.TlbMiss:
223	mov r8d, ACCESS_FLAGS
224	mov rdx, [VA]
225	mov rcx, [pVCpu]
226	call iemTlbTypeMiss
227	.Done:
228
229	@endcode
230	*
231	*/
232	typedef struct IEMTLBENTRY
233	{
234	/** The TLB entry tag.
235	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits.
236	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
237	*
238	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
239	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
240	* revision wraps around though, the tags needs to be zeroed.
241	*
242	* @note Try use SHRD instruction? After seeing
243	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
244	*/
245	uint64_t uTag;
246	/** Access flags and physical TLB revision.
247	*
248	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
249	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
250	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
251	* - Bit 3 - pgm phys/virt - not directly writable.
252	* - Bit 4 - pgm phys page - not directly readable.
253	* - Bit 5 - currently unused.
254	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
255	* - Bit 7 - tlb entry - pMappingR3 member not valid.
256	* - Bits 63 thru 8 are used for the physical TLB revision number.
257	*
258	* We're using complemented bit meanings here because it makes it easy to check
259	* whether special action is required. For instance a user mode write access
260	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
261	* non-zero result would mean special handling needed because either it wasn't
262	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
263	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
264	* need to check any PTE flag.
265	*/
266	uint64_t fFlagsAndPhysRev;
267	/** The guest physical page address. */
268	uint64_t GCPhys;
269	/** Pointer to the ring-3 mapping (possibly also valid in ring-0). */
270	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
271	R3PTRTYPE(uint8_t *) pbMappingR3;
272	#else
273	R3R0PTRTYPE(uint8_t *) pbMappingR3;
274	#endif
275	#if HC_ARCH_BITS == 32
276	uint32_t u32Padding1;
277	#endif
278	} IEMTLBENTRY;
279	AssertCompileSize(IEMTLBENTRY, 32);
280	/** Pointer to an IEM TLB entry. */
281	typedef IEMTLBENTRY *PIEMTLBENTRY;
282
283	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
284	* @{ */
285	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
286	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
287	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
288	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
289	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
290	#define IEMTLBE_F_PATCH_CODE RT_BIT_64(5) /*< Code TLB: Patch code (PATM). /
291	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
292	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
293	#define IEMTLBE_F_PHYS_REV UINT64_C(0xffffffffffffff00) /*< Physical revision mask. /
294	/** @} */
295
296
297	/**
298	* An IEM TLB.
299	*
300	* We've got two of these, one for data and one for instructions.
301	*/
302	typedef struct IEMTLB
303	{
304	/** The TLB entries.
305	* We've choosen 256 because that way we can obtain the result directly from a
306	* 8-bit register without an additional AND instruction. */
307	IEMTLBENTRY aEntries[256];
308	/** The TLB revision.
309	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
310	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
311	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
312	* (The revision zero indicates an invalid TLB entry.)
313	*
314	* The initial value is choosen to cause an early wraparound. */
315	uint64_t uTlbRevision;
316	/** The TLB physical address revision - shadow of PGM variable.
317	*
318	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
319	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
320	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
321	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
322	*
323	* The initial value is choosen to cause an early wraparound. */
324	uint64_t volatile uTlbPhysRev;
325
326	/* Statistics: */
327
328	/** TLB hits (VBOX_WITH_STATISTICS only). */
329	uint64_t cTlbHits;
330	/** TLB misses. */
331	uint32_t cTlbMisses;
332	/** Slow read path. */
333	uint32_t cTlbSlowReadPath;
334	#if 0
335	/** TLB misses because of tag mismatch. */
336	uint32_t cTlbMissesTag;
337	/** TLB misses because of virtual access violation. */
338	uint32_t cTlbMissesVirtAccess;
339	/** TLB misses because of dirty bit. */
340	uint32_t cTlbMissesDirty;
341	/** TLB misses because of MMIO */
342	uint32_t cTlbMissesMmio;
343	/** TLB misses because of write access handlers. */
344	uint32_t cTlbMissesWriteHandler;
345	/** TLB misses because no r3(/r0) mapping. */
346	uint32_t cTlbMissesMapping;
347	#endif
348	/** Alignment padding. */
349	uint32_t au32Padding[3+5];
350	} IEMTLB;
351	AssertCompileSizeAlignment(IEMTLB, 64);
352	/** IEMTLB::uTlbRevision increment. */
353	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
354	/** IEMTLB::uTlbPhysRev increment. */
355	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(8)
356
357
358	/**
359	* The per-CPU IEM state.
360	*/
361	typedef struct IEMCPU
362	{
363	/** Info status code that needs to be propagated to the IEM caller.
364	* This cannot be passed internally, as it would complicate all success
365	* checks within the interpreter making the code larger and almost impossible
366	* to get right. Instead, we'll store status codes to pass on here. Each
367	* source of these codes will perform appropriate sanity checks. */
368	int32_t rcPassUp; /* 0x00 */
369
370	/** The current CPU execution mode (CS). */
371	IEMMODE enmCpuMode; /* 0x04 */
372	/** The CPL. */
373	uint8_t uCpl; /* 0x05 */
374
375	/** Whether to bypass access handlers or not. */
376	bool fBypassHandlers; /* 0x06 */
377	bool fUnusedWasInPatchCode; /* 0x07 */
378
379	/** @name Decoder state.
380	* @{ */
381	#ifdef IEM_WITH_CODE_TLB
382	/** The offset of the next instruction byte. */
383	uint32_t offInstrNextByte; /* 0x08 */
384	/** The number of bytes available at pbInstrBuf for the current instruction.
385	* This takes the max opcode length into account so that doesn't need to be
386	* checked separately. */
387	uint32_t cbInstrBuf; /* 0x0c */
388	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
389	* This can be NULL if the page isn't mappable for some reason, in which
390	* case we'll do fallback stuff.
391	*
392	* If we're executing an instruction from a user specified buffer,
393	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
394	* aligned pointer but pointer to the user data.
395	*
396	* For instructions crossing pages, this will start on the first page and be
397	* advanced to the next page by the time we've decoded the instruction. This
398	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
399	*/
400	uint8_t const pbInstrBuf; / 0x10 */
401	# if ARCH_BITS == 32
402	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
403	# endif
404	/** The program counter corresponding to pbInstrBuf.
405	* This is set to a non-canonical address when we need to invalidate it. */
406	uint64_t uInstrBufPc; /* 0x18 */
407	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
408	* This takes the CS segment limit into account. */
409	uint16_t cbInstrBufTotal; /* 0x20 */
410	/** Offset into pbInstrBuf of the first byte of the current instruction.
411	* Can be negative to efficiently handle cross page instructions. */
412	int16_t offCurInstrStart; /* 0x22 */
413
414	/** The prefix mask (IEM_OP_PRF_XXX). */
415	uint32_t fPrefixes; /* 0x24 */
416	/** The extra REX ModR/M register field bit (REX.R << 3). */
417	uint8_t uRexReg; /* 0x28 */
418	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
419	* (REX.B << 3). */
420	uint8_t uRexB; /* 0x29 */
421	/** The extra REX SIB index field bit (REX.X << 3). */
422	uint8_t uRexIndex; /* 0x2a */
423
424	/** The effective segment register (X86_SREG_XXX). */
425	uint8_t iEffSeg; /* 0x2b */
426
427	/** The offset of the ModR/M byte relative to the start of the instruction. */
428	uint8_t offModRm; /* 0x2c */
429	#else
430	/** The size of what has currently been fetched into abOpcode. */
431	uint8_t cbOpcode; /* 0x08 */
432	/** The current offset into abOpcode. */
433	uint8_t offOpcode; /* 0x09 */
434	/** The offset of the ModR/M byte relative to the start of the instruction. */
435	uint8_t offModRm; /* 0x0a */
436
437	/** The effective segment register (X86_SREG_XXX). */
438	uint8_t iEffSeg; /* 0x0b */
439
440	/** The prefix mask (IEM_OP_PRF_XXX). */
441	uint32_t fPrefixes; /* 0x0c */
442	/** The extra REX ModR/M register field bit (REX.R << 3). */
443	uint8_t uRexReg; /* 0x10 */
444	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
445	* (REX.B << 3). */
446	uint8_t uRexB; /* 0x11 */
447	/** The extra REX SIB index field bit (REX.X << 3). */
448	uint8_t uRexIndex; /* 0x12 */
449
450	#endif
451
452	/** The effective operand mode. */
453	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
454	/** The default addressing mode. */
455	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
456	/** The effective addressing mode. */
457	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
458	/** The default operand mode. */
459	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
460
461	/** Prefix index (VEX.pp) for two byte and three byte tables. */
462	uint8_t idxPrefix; /* 0x31, 0x17 */
463	/** 3rd VEX/EVEX/XOP register.
464	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
465	uint8_t uVex3rdReg; /* 0x32, 0x18 */
466	/** The VEX/EVEX/XOP length field. */
467	uint8_t uVexLength; /* 0x33, 0x19 */
468	/** Additional EVEX stuff. */
469	uint8_t fEvexStuff; /* 0x34, 0x1a */
470
471	/** Explicit alignment padding. */
472	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
473	/** The FPU opcode (FOP). */
474	uint16_t uFpuOpcode; /* 0x36, 0x1c */
475	#ifndef IEM_WITH_CODE_TLB
476	/** Explicit alignment padding. */
477	uint8_t abAlignment2b[2]; /* 0x1e */
478	#endif
479
480	/** The opcode bytes. */
481	uint8_t abOpcode[15]; /* 0x48, 0x20 */
482	/** Explicit alignment padding. */
483	#ifdef IEM_WITH_CODE_TLB
484	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
485	#else
486	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
487	#endif
488	/** @} */
489
490
491	/** The flags of the current exception / interrupt. */
492	uint32_t fCurXcpt; /* 0x48, 0x48 */
493	/** The current exception / interrupt. */
494	uint8_t uCurXcpt;
495	/** Exception / interrupt recursion depth. */
496	int8_t cXcptRecursions;
497
498	/** The number of active guest memory mappings. */
499	uint8_t cActiveMappings;
500	/** The next unused mapping index. */
501	uint8_t iNextMapping;
502	/** Records for tracking guest memory mappings. */
503	struct
504	{
505	/** The address of the mapped bytes. */
506	void *pv;
507	#if defined(IN_RC) && HC_ARCH_BITS == 64
508	uint32_t u32Alignment3; /*< Alignment padding. /
509	#endif
510	/** The access flags (IEM_ACCESS_XXX).
511	* IEM_ACCESS_INVALID if the entry is unused. */
512	uint32_t fAccess;
513	#if HC_ARCH_BITS == 64
514	uint32_t u32Alignment4; /*< Alignment padding. /
515	#endif
516	} aMemMappings[3];
517
518	/** Locking records for the mapped memory. */
519	union
520	{
521	PGMPAGEMAPLOCK Lock;
522	uint64_t au64Padding[2];
523	} aMemMappingLocks[3];
524
525	/** Bounce buffer info.
526	* This runs in parallel to aMemMappings. */
527	struct
528	{
529	/** The physical address of the first byte. */
530	RTGCPHYS GCPhysFirst;
531	/** The physical address of the second page. */
532	RTGCPHYS GCPhysSecond;
533	/** The number of bytes in the first page. */
534	uint16_t cbFirst;
535	/** The number of bytes in the second page. */
536	uint16_t cbSecond;
537	/** Whether it's unassigned memory. */
538	bool fUnassigned;
539	/** Explicit alignment padding. */
540	bool afAlignment5[3];
541	} aMemBbMappings[3];
542
543	/** Bounce buffer storage.
544	* This runs in parallel to aMemMappings and aMemBbMappings. */
545	struct
546	{
547	uint8_t ab[512];
548	} aBounceBuffers[3];
549
550
551	/** Pointer set jump buffer - ring-3 context. */
552	R3PTRTYPE(jmp_buf *) pJmpBufR3;
553	/** Pointer set jump buffer - ring-0 context. */
554	R0PTRTYPE(jmp_buf *) pJmpBufR0;
555	/** Pointer set jump buffer - raw-mode context. */
556	RCPTRTYPE(jmp_buf *) pJmpBufRC;
557
558	/** @todo Should move this near @a fCurXcpt later. */
559	/** The error code for the current exception / interrupt. */
560	uint32_t uCurXcptErr;
561	/** The CR2 for the current exception / interrupt. */
562	uint64_t uCurXcptCr2;
563	/** The VMX APIC-access page handler type. */
564	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
565
566	/** @name Statistics
567	* @{ */
568	/** The number of instructions we've executed. */
569	uint32_t cInstructions;
570	/** The number of potential exits. */
571	uint32_t cPotentialExits;
572	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
573	* This may contain uncommitted writes. */
574	uint32_t cbWritten;
575	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
576	uint32_t cRetInstrNotImplemented;
577	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
578	uint32_t cRetAspectNotImplemented;
579	/** Counts informational statuses returned (other than VINF_SUCCESS). */
580	uint32_t cRetInfStatuses;
581	/** Counts other error statuses returned. */
582	uint32_t cRetErrStatuses;
583	/** Number of times rcPassUp has been used. */
584	uint32_t cRetPassUpStatus;
585	/** Number of times RZ left with instruction commit pending for ring-3. */
586	uint32_t cPendingCommit;
587	/** Number of long jumps. */
588	uint32_t cLongJumps;
589	/** @} */
590
591	/** @name Target CPU information.
592	* @{ */
593	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
594	/** The target CPU. */
595	uint32_t uTargetCpu;
596	#else
597	uint32_t u32TargetCpuPadding;
598	#endif
599	/** The CPU vendor. */
600	CPUMCPUVENDOR enmCpuVendor;
601	/** @} */
602
603	/** @name Host CPU information.
604	* @{ */
605	/** The CPU vendor. */
606	CPUMCPUVENDOR enmHostCpuVendor;
607	/** @} */
608
609	/** Counts RDMSR \#GP(0) LogRel(). */
610	uint8_t cLogRelRdMsr;
611	/** Counts WRMSR \#GP(0) LogRel(). */
612	uint8_t cLogRelWrMsr;
613	/** Alignment padding. */
614	uint8_t abAlignment8[HC_ARCH_BITS == 64 ? 46 : 14];
615
616	/** Data TLB.
617	* @remarks Must be 64-byte aligned. */
618	IEMTLB DataTlb;
619	/** Instruction TLB.
620	* @remarks Must be 64-byte aligned. */
621	IEMTLB CodeTlb;
622
623	/** Pointer to instruction statistics for raw-mode context (same as R0). */
624	RCPTRTYPE(PIEMINSTRSTATS) pStatsRC;
625	/** Alignment padding. */
626	RTRCPTR RCPtrPadding;
627	/** Pointer to instruction statistics for ring-0 context (same as RC). */
628	R0PTRTYPE(PIEMINSTRSTATS) pStatsR0;
629	/** Pointer to instruction statistics for non-ring-3 code. */
630	R3PTRTYPE(PIEMINSTRSTATS) pStatsCCR3;
631	/** Pointer to instruction statistics for ring-3 context. */
632	R3PTRTYPE(PIEMINSTRSTATS) pStatsR3;
633	} IEMCPU;
634	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
635	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
636	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
637	/** Pointer to the per-CPU IEM state. */
638	typedef IEMCPU *PIEMCPU;
639	/** Pointer to the const per-CPU IEM state. */
640	typedef IEMCPU const *PCIEMCPU;
641
642
643	/** @def IEM_GET_CTX
644	* Gets the guest CPU context for the calling EMT.
645	* @returns PCPUMCTX
646	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
647	*/
648	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
649
650	/** @def IEM_CTX_ASSERT
651	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
652	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
653	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
654	*/
655	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
656	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
657	(a_fExtrnMbz)))
658
659	/** @def IEM_CTX_IMPORT_RET
660	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
661	*
662	* Will call the keep to import the bits as needed.
663	*
664	* Returns on import failure.
665	*
666	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
667	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
668	*/
669	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
670	do { \
671	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
672	{ /* likely */ } \
673	else \
674	{ \
675	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
676	AssertRCReturn(rcCtxImport, rcCtxImport); \
677	} \
678	} while (0)
679
680	/** @def IEM_CTX_IMPORT_NORET
681	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
682	*
683	* Will call the keep to import the bits as needed.
684	*
685	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
686	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
687	*/
688	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
689	do { \
690	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
691	{ /* likely */ } \
692	else \
693	{ \
694	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
695	AssertLogRelRC(rcCtxImport); \
696	} \
697	} while (0)
698
699	/** @def IEM_CTX_IMPORT_JMP
700	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
701	*
702	* Will call the keep to import the bits as needed.
703	*
704	* Jumps on import failure.
705	*
706	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
707	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
708	*/
709	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
710	do { \
711	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
712	{ /* likely */ } \
713	else \
714	{ \
715	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
716	AssertRCStmt(rcCtxImport, longjmp(*pVCpu->iem.s.CTX_SUFF(pJmpBuf), rcCtxImport)); \
717	} \
718	} while (0)
719
720
721
722	/** Gets the current IEMTARGETCPU value.
723	* @returns IEMTARGETCPU value.
724	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
725	*/
726	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
727	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
728	#else
729	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
730	#endif
731
732	/** @def Gets the instruction length. */
733	#ifdef IEM_WITH_CODE_TLB
734	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
735	#else
736	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
737	#endif
738
739
740	/** @name IEM_ACCESS_XXX - Access details.
741	* @{ */
742	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
743	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
744	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
745	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
746	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
747	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
748	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
749	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
750	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
751	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
752	/** The writes are partial, so if initialize the bounce buffer with the
753	* orignal RAM content. */
754	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
755	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
756	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
757	/** Bounce buffer with ring-3 write pending, first page. */
758	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
759	/** Bounce buffer with ring-3 write pending, second page. */
760	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
761	/** Valid bit mask. */
762	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00000fff)
763	/** Read+write data alias. */
764	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
765	/** Write data alias. */
766	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
767	/** Read data alias. */
768	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
769	/** Instruction fetch alias. */
770	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
771	/** Stack write alias. */
772	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
773	/** Stack read alias. */
774	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
775	/** Stack read+write alias. */
776	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
777	/** Read system table alias. */
778	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
779	/** Read+write system table alias. */
780	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
781	/** @} */
782
783	/** @name Prefix constants (IEMCPU::fPrefixes)
784	* @{ */
785	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
786	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
787	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
788	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
789	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
790	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
791	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
792
793	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
794	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
795	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
796
797	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
798	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
799	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
800
801	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
802	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
803	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
804	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
805	/** Mask with all the REX prefix flags.
806	* This is generally for use when needing to undo the REX prefixes when they
807	* are followed legacy prefixes and therefore does not immediately preceed
808	* the first opcode byte.
809	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
810	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
811
812	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
813	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
814	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
815	/** @} */
816
817	/** @name IEMOPFORM_XXX - Opcode forms
818	* @note These are ORed together with IEMOPHINT_XXX.
819	* @{ */
820	/** ModR/M: reg, r/m */
821	#define IEMOPFORM_RM 0
822	/** ModR/M: reg, r/m (register) */
823	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
824	/** ModR/M: reg, r/m (memory) */
825	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
826	/** ModR/M: r/m, reg */
827	#define IEMOPFORM_MR 1
828	/** ModR/M: r/m (register), reg */
829	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
830	/** ModR/M: r/m (memory), reg */
831	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
832	/** ModR/M: r/m only */
833	#define IEMOPFORM_M 2
834	/** ModR/M: r/m only (register). */
835	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
836	/** ModR/M: r/m only (memory). */
837	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
838	/** ModR/M: reg only */
839	#define IEMOPFORM_R 3
840
841	/** VEX+ModR/M: reg, r/m */
842	#define IEMOPFORM_VEX_RM 4
843	/** VEX+ModR/M: reg, r/m (register) */
844	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
845	/** VEX+ModR/M: reg, r/m (memory) */
846	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
847	/** VEX+ModR/M: r/m, reg */
848	#define IEMOPFORM_VEX_MR 5
849	/** VEX+ModR/M: r/m (register), reg */
850	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
851	/** VEX+ModR/M: r/m (memory), reg */
852	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
853	/** VEX+ModR/M: r/m only */
854	#define IEMOPFORM_VEX_M 6
855	/** VEX+ModR/M: r/m only (register). */
856	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
857	/** VEX+ModR/M: r/m only (memory). */
858	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
859	/** VEX+ModR/M: reg only */
860	#define IEMOPFORM_VEX_R 7
861	/** VEX+ModR/M: reg, vvvv, r/m */
862	#define IEMOPFORM_VEX_RVM 8
863	/** VEX+ModR/M: reg, vvvv, r/m (register). */
864	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
865	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
866	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
867	/** VEX+ModR/M: r/m, vvvv, reg */
868	#define IEMOPFORM_VEX_MVR 9
869	/** VEX+ModR/M: r/m, vvvv, reg (register) */
870	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
871	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
872	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
873
874	/** Fixed register instruction, no R/M. */
875	#define IEMOPFORM_FIXED 16
876
877	/** The r/m is a register. */
878	#define IEMOPFORM_MOD3 RT_BIT_32(8)
879	/** The r/m is a memory access. */
880	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
881	/** @} */
882
883	/** @name IEMOPHINT_XXX - Additional Opcode Hints
884	* @note These are ORed together with IEMOPFORM_XXX.
885	* @{ */
886	/** Ignores the operand size prefix (66h). */
887	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
888	/** Ignores REX.W (aka WIG). */
889	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
890	/** Both the operand size prefixes (66h + REX.W) are ignored. */
891	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
892	/** Allowed with the lock prefix. */
893	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
894	/** The VEX.L value is ignored (aka LIG). */
895	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
896	/** The VEX.L value must be zero (i.e. 128-bit width only). */
897	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
898
899	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
900	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
901	/** @} */
902
903	/**
904	* Possible hardware task switch sources.
905	*/
906	typedef enum IEMTASKSWITCH
907	{
908	/** Task switch caused by an interrupt/exception. */
909	IEMTASKSWITCH_INT_XCPT = 1,
910	/** Task switch caused by a far CALL. */
911	IEMTASKSWITCH_CALL,
912	/** Task switch caused by a far JMP. */
913	IEMTASKSWITCH_JUMP,
914	/** Task switch caused by an IRET. */
915	IEMTASKSWITCH_IRET
916	} IEMTASKSWITCH;
917	AssertCompileSize(IEMTASKSWITCH, 4);
918
919	/**
920	* Possible CrX load (write) sources.
921	*/
922	typedef enum IEMACCESSCRX
923	{
924	/** CrX access caused by 'mov crX' instruction. */
925	IEMACCESSCRX_MOV_CRX,
926	/** CrX (CR0) write caused by 'lmsw' instruction. */
927	IEMACCESSCRX_LMSW,
928	/** CrX (CR0) write caused by 'clts' instruction. */
929	IEMACCESSCRX_CLTS,
930	/** CrX (CR0) read caused by 'smsw' instruction. */
931	IEMACCESSCRX_SMSW
932	} IEMACCESSCRX;
933
934	# ifdef VBOX_WITH_NESTED_HWVIRT_VMX
935	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
936	# endif
937
938	/**
939	* Indicates to the verifier that the given flag set is undefined.
940	*
941	* Can be invoked again to add more flags.
942	*
943	* This is a NOOP if the verifier isn't compiled in.
944	*
945	* @note We're temporarily keeping this until code is converted to new
946	* disassembler style opcode handling.
947	*/
948	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
949
950
951	/** @def IEM_DECL_IMPL_TYPE
952	* For typedef'ing an instruction implementation function.
953	*
954	* @param a_RetType The return type.
955	* @param a_Name The name of the type.
956	* @param a_ArgList The argument list enclosed in parentheses.
957	*/
958
959	/** @def IEM_DECL_IMPL_DEF
960	* For defining an instruction implementation function.
961	*
962	* @param a_RetType The return type.
963	* @param a_Name The name of the type.
964	* @param a_ArgList The argument list enclosed in parentheses.
965	*/
966
967	#if defined(__GNUC__) && defined(RT_ARCH_X86)
968	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
969	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
970	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
971	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
972
973	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
974	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
975	a_RetType (__fastcall a_Name) a_ArgList
976	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
977	a_RetType __fastcall a_Name a_ArgList
978
979	#else
980	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
981	a_RetType (VBOXCALL a_Name) a_ArgList
982	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
983	a_RetType VBOXCALL a_Name a_ArgList
984
985	#endif
986
987	/** @name Arithmetic assignment operations on bytes (binary).
988	* @{ */
989	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
990	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
991	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
992	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
993	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
994	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
995	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
996	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
997	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
998	/** @} */
999
1000	/** @name Arithmetic assignment operations on words (binary).
1001	* @{ */
1002	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1003	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1004	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1005	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1006	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1007	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1008	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1009	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1010	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1011	/** @} */
1012
1013	/** @name Arithmetic assignment operations on double words (binary).
1014	* @{ */
1015	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1016	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1017	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1018	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1019	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1020	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1021	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1022	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1023	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1024	/** @} */
1025
1026	/** @name Arithmetic assignment operations on quad words (binary).
1027	* @{ */
1028	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1029	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1030	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1031	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1032	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1033	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1034	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1035	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1036	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1037	/** @} */
1038
1039	/** @name Compare operations (thrown in with the binary ops).
1040	* @{ */
1041	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1042	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1043	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1044	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1045	/** @} */
1046
1047	/** @name Test operations (thrown in with the binary ops).
1048	* @{ */
1049	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1050	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1051	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1052	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1053	/** @} */
1054
1055	/** @name Bit operations operations (thrown in with the binary ops).
1056	* @{ */
1057	FNIEMAIMPLBINU16 iemAImpl_bt_u16, iemAImpl_bt_u16_locked;
1058	FNIEMAIMPLBINU32 iemAImpl_bt_u32, iemAImpl_bt_u32_locked;
1059	FNIEMAIMPLBINU64 iemAImpl_bt_u64, iemAImpl_bt_u64_locked;
1060	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1061	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1062	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1063	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1064	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1065	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1066	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1067	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1068	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1069	/** @} */
1070
1071	/** @name Exchange memory with register operations.
1072	* @{ */
1073	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8, (uint8_t pu8Mem, uint8_t pu8Reg));
1074	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16,(uint16_t pu16Mem, uint16_t pu16Reg));
1075	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32,(uint32_t pu32Mem, uint32_t pu32Reg));
1076	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64,(uint64_t pu64Mem, uint64_t pu64Reg));
1077	/** @} */
1078
1079	/** @name Exchange and add operations.
1080	* @{ */
1081	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1082	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1083	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1084	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1085	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1086	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1087	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1088	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1089	/** @} */
1090
1091	/** @name Compare and exchange.
1092	* @{ */
1093	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1094	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1095	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1096	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1097	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1098	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1099	#ifdef RT_ARCH_X86
1100	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1101	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1102	#else
1103	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1104	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1105	#endif
1106	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1107	uint32_t *pEFlags));
1108	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1109	uint32_t *pEFlags));
1110	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1111	uint32_t *pEFlags));
1112	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1113	uint32_t *pEFlags));
1114	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1115	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1116	/** @} */
1117
1118	/** @name Memory ordering
1119	* @{ */
1120	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1121	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1122	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1123	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1124	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1125	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1126	/** @} */
1127
1128	/** @name Double precision shifts
1129	* @{ */
1130	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1131	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1132	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1133	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1134	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1135	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1136	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16;
1137	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32;
1138	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64;
1139	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16;
1140	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32;
1141	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64;
1142	/** @} */
1143
1144
1145	/** @name Bit search operations (thrown in with the binary ops).
1146	* @{ */
1147	FNIEMAIMPLBINU16 iemAImpl_bsf_u16;
1148	FNIEMAIMPLBINU32 iemAImpl_bsf_u32;
1149	FNIEMAIMPLBINU64 iemAImpl_bsf_u64;
1150	FNIEMAIMPLBINU16 iemAImpl_bsr_u16;
1151	FNIEMAIMPLBINU32 iemAImpl_bsr_u32;
1152	FNIEMAIMPLBINU64 iemAImpl_bsr_u64;
1153	/** @} */
1154
1155	/** @name Signed multiplication operations (thrown in with the binary ops).
1156	* @{ */
1157	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16;
1158	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32;
1159	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64;
1160	/** @} */
1161
1162	/** @name Arithmetic assignment operations on bytes (unary).
1163	* @{ */
1164	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1165	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1166	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1167	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1168	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1169	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1170	/** @} */
1171
1172	/** @name Arithmetic assignment operations on words (unary).
1173	* @{ */
1174	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1175	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1176	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1177	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1178	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1179	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1180	/** @} */
1181
1182	/** @name Arithmetic assignment operations on double words (unary).
1183	* @{ */
1184	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1185	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1186	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1187	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1188	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1189	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1190	/** @} */
1191
1192	/** @name Arithmetic assignment operations on quad words (unary).
1193	* @{ */
1194	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1195	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1196	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1197	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1198	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1199	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1200	/** @} */
1201
1202
1203	/** @name Shift operations on bytes (Group 2).
1204	* @{ */
1205	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1206	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1207	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8;
1208	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8;
1209	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8;
1210	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8;
1211	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8;
1212	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8;
1213	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8;
1214	/** @} */
1215
1216	/** @name Shift operations on words (Group 2).
1217	* @{ */
1218	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1219	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1220	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16;
1221	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16;
1222	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16;
1223	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16;
1224	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16;
1225	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16;
1226	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16;
1227	/** @} */
1228
1229	/** @name Shift operations on double words (Group 2).
1230	* @{ */
1231	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1232	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1233	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32;
1234	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32;
1235	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32;
1236	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32;
1237	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32;
1238	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32;
1239	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32;
1240	/** @} */
1241
1242	/** @name Shift operations on words (Group 2).
1243	* @{ */
1244	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1245	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1246	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64;
1247	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64;
1248	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64;
1249	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64;
1250	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64;
1251	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64;
1252	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64;
1253	/** @} */
1254
1255	/** @name Multiplication and division operations.
1256	* @{ */
1257	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1258	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1259	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_imul_u8;
1260	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_idiv_u8;
1261
1262	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1263	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1264	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_imul_u16;
1265	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_idiv_u16;
1266
1267	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1268	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1269	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_imul_u32;
1270	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_idiv_u32;
1271
1272	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1273	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1274	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_imul_u64;
1275	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_idiv_u64;
1276	/** @} */
1277
1278	/** @name Byte Swap.
1279	* @{ */
1280	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1281	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1282	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1283	/** @} */
1284
1285	/** @name Misc.
1286	* @{ */
1287	FNIEMAIMPLBINU16 iemAImpl_arpl;
1288	/** @} */
1289
1290
1291	/** @name FPU operations taking a 32-bit float argument
1292	* @{ */
1293	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1294	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1295	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1296
1297	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1298	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1299	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1300
1301	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1302	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1303	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1304	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1305	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1306	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1307	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1308
1309	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1310	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1311	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1312	/** @} */
1313
1314	/** @name FPU operations taking a 64-bit float argument
1315	* @{ */
1316	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1317	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1318	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1319
1320	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1321	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1322	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1323	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1324	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1325	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1326
1327	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1328	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1329	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1330	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1331	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1332	/** @} */
1333
1334	/** @name FPU operations taking a 80-bit float argument
1335	* @{ */
1336	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1337	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1338	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1339	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1340	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1341	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1342	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1343	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1344	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1345	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1346	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1347	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1348
1349	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80;
1350	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80;
1351	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80;
1352
1353	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1354	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1355	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1356	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1357	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1358
1359	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1360	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1361	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1362	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1363	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1364
1365	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1366	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1367	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1368	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1369	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80;
1370	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1371	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1372	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80;
1373	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80;
1374
1375	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1376	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1377	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1378	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1379
1380	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1381	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1382	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1383	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1384	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1385	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1386	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1387	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1388	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1389
1390	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1391	PCRTFLOAT80U pr80Val));
1392	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1393	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80;
1394	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1395	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80;
1396
1397	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1398	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1399	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1400
1401	/** @} */
1402
1403	/** @name FPU operations taking a 16-bit signed integer argument
1404	* @{ */
1405	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1406	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1407	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1408
1409	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1410	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1411	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1412	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1413	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1414	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1415
1416	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1417	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1418
1419	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1420	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1421	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1422	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1423	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1424	/** @} */
1425
1426	/** @name FPU operations taking a 32-bit signed integer argument
1427	* @{ */
1428	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1429	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1430	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1431
1432	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1433	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1434	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1435	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1436	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1437	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1438
1439	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1440	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1441
1442	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1443	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1444	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1445	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1446	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1447	/** @} */
1448
1449	/** @name FPU operations taking a 64-bit signed integer argument
1450	* @{ */
1451	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1452	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1453	typedef FNIEMAIMPLFPUI64 *PFNIEMAIMPLFPUI64;
1454
1455	FNIEMAIMPLFPUI64 iemAImpl_fiadd_r80_by_i64;
1456	FNIEMAIMPLFPUI64 iemAImpl_fimul_r80_by_i64;
1457	FNIEMAIMPLFPUI64 iemAImpl_fisub_r80_by_i64;
1458	FNIEMAIMPLFPUI64 iemAImpl_fisubr_r80_by_i64;
1459	FNIEMAIMPLFPUI64 iemAImpl_fidiv_r80_by_i64;
1460	FNIEMAIMPLFPUI64 iemAImpl_fidivr_r80_by_i64;
1461
1462	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1463	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1464
1465	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1466	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1467	int64_t *pi64Val, PCRTFLOAT80U pr80Val));
1468	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1469	int64_t *pi32Val, PCRTFLOAT80U pr80Val));
1470	/** @} */
1471
1472
1473	/** Temporary type representing a 256-bit vector register. */
1474	typedef struct {uint64_t au64[4]; } IEMVMM256;
1475	/** Temporary type pointing to a 256-bit vector register. */
1476	typedef IEMVMM256 *PIEMVMM256;
1477	/** Temporary type pointing to a const 256-bit vector register. */
1478	typedef IEMVMM256 *PCIEMVMM256;
1479
1480
1481	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1482	* @{ */
1483	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1484	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1485	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1486	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1487	FNIEMAIMPLMEDIAF2U64 iemAImpl_pxor_u64, iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1488	FNIEMAIMPLMEDIAF2U128 iemAImpl_pxor_u128, iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1489	/** @} */
1490
1491	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1492	* @{ */
1493	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src));
1494	typedef FNIEMAIMPLMEDIAF1L1U64 *PFNIEMAIMPLMEDIAF1L1U64;
1495	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src));
1496	typedef FNIEMAIMPLMEDIAF1L1U128 *PFNIEMAIMPLMEDIAF1L1U128;
1497	FNIEMAIMPLMEDIAF1L1U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1498	FNIEMAIMPLMEDIAF1L1U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1499	/** @} */
1500
1501	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
1502	* @{ */
1503	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1504	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF1H1U64;
1505	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1506	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF1H1U128;
1507	FNIEMAIMPLMEDIAF1H1U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
1508	FNIEMAIMPLMEDIAF1H1U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
1509	/** @} */
1510
1511	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
1512	* @{ */
1513	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUF,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst,
1514	PCRTUINT128U pu128Src, uint8_t bEvil));
1515	typedef FNIEMAIMPLMEDIAPSHUF *PFNIEMAIMPLMEDIAPSHUF;
1516	FNIEMAIMPLMEDIAPSHUF iemAImpl_pshufhw, iemAImpl_pshuflw, iemAImpl_pshufd;
1517	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil));
1518	/** @} */
1519
1520	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
1521	* @{ */
1522	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1523	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src));
1524	/** @} */
1525
1526	/** @name Media (SSE/MMX/AVX) operation: Sort this later
1527	* @{ */
1528	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1529	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1530	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc));
1531
1532	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1533	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1534	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1535	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1536
1537	/** @} */
1538
1539
1540	/** @name Function tables.
1541	* @{
1542	*/
1543
1544	/**
1545	* Function table for a binary operator providing implementation based on
1546	* operand size.
1547	*/
1548	typedef struct IEMOPBINSIZES
1549	{
1550	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
1551	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
1552	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
1553	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
1554	} IEMOPBINSIZES;
1555	/** Pointer to a binary operator function table. */
1556	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
1557
1558
1559	/**
1560	* Function table for a unary operator providing implementation based on
1561	* operand size.
1562	*/
1563	typedef struct IEMOPUNARYSIZES
1564	{
1565	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
1566	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
1567	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
1568	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
1569	} IEMOPUNARYSIZES;
1570	/** Pointer to a unary operator function table. */
1571	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
1572
1573
1574	/**
1575	* Function table for a shift operator providing implementation based on
1576	* operand size.
1577	*/
1578	typedef struct IEMOPSHIFTSIZES
1579	{
1580	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
1581	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
1582	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
1583	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
1584	} IEMOPSHIFTSIZES;
1585	/** Pointer to a shift operator function table. */
1586	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
1587
1588
1589	/**
1590	* Function table for a multiplication or division operation.
1591	*/
1592	typedef struct IEMOPMULDIVSIZES
1593	{
1594	PFNIEMAIMPLMULDIVU8 pfnU8;
1595	PFNIEMAIMPLMULDIVU16 pfnU16;
1596	PFNIEMAIMPLMULDIVU32 pfnU32;
1597	PFNIEMAIMPLMULDIVU64 pfnU64;
1598	} IEMOPMULDIVSIZES;
1599	/** Pointer to a multiplication or division operation function table. */
1600	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
1601
1602
1603	/**
1604	* Function table for a double precision shift operator providing implementation
1605	* based on operand size.
1606	*/
1607	typedef struct IEMOPSHIFTDBLSIZES
1608	{
1609	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
1610	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
1611	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
1612	} IEMOPSHIFTDBLSIZES;
1613	/** Pointer to a double precision shift function table. */
1614	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
1615
1616
1617	/**
1618	* Function table for media instruction taking two full sized media registers,
1619	* optionally the 2nd being a memory reference (only modifying the first op.)
1620	*/
1621	typedef struct IEMOPMEDIAF2
1622	{
1623	PFNIEMAIMPLMEDIAF2U64 pfnU64;
1624	PFNIEMAIMPLMEDIAF2U128 pfnU128;
1625	} IEMOPMEDIAF2;
1626	/** Pointer to a media operation function table for full sized ops. */
1627	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
1628
1629	/**
1630	* Function table for media instruction taking taking one full and one lower
1631	* half media register.
1632	*/
1633	typedef struct IEMOPMEDIAF1L1
1634	{
1635	PFNIEMAIMPLMEDIAF1L1U64 pfnU64;
1636	PFNIEMAIMPLMEDIAF1L1U128 pfnU128;
1637	} IEMOPMEDIAF1L1;
1638	/** Pointer to a media operation function table for lowhalf+lowhalf -> full. */
1639	typedef IEMOPMEDIAF1L1 const *PCIEMOPMEDIAF1L1;
1640
1641	/**
1642	* Function table for media instruction taking taking one full and one high half
1643	* media register.
1644	*/
1645	typedef struct IEMOPMEDIAF1H1
1646	{
1647	PFNIEMAIMPLMEDIAF1H1U64 pfnU64;
1648	PFNIEMAIMPLMEDIAF1H1U128 pfnU128;
1649	} IEMOPMEDIAF1H1;
1650	/** Pointer to a media operation function table for hihalf+hihalf -> full. */
1651	typedef IEMOPMEDIAF1H1 const *PCIEMOPMEDIAF1H1;
1652
1653
1654	/** @} */
1655
1656
1657	/** @name C instruction implementations for anything slightly complicated.
1658	* @{ */
1659
1660	/**
1661	* For typedef'ing or declaring a C instruction implementation function taking
1662	* no extra arguments.
1663	*
1664	* @param a_Name The name of the type.
1665	*/
1666	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
1667	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1668	/**
1669	* For defining a C instruction implementation function taking no extra
1670	* arguments.
1671	*
1672	* @param a_Name The name of the function
1673	*/
1674	# define IEM_CIMPL_DEF_0(a_Name) \
1675	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr))
1676	/**
1677	* For calling a C instruction implementation function taking no extra
1678	* arguments.
1679	*
1680	* This special call macro adds default arguments to the call and allow us to
1681	* change these later.
1682	*
1683	* @param a_fn The name of the function.
1684	*/
1685	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
1686
1687	/**
1688	* For typedef'ing or declaring a C instruction implementation function taking
1689	* one extra argument.
1690	*
1691	* @param a_Name The name of the type.
1692	* @param a_Type0 The argument type.
1693	* @param a_Arg0 The argument name.
1694	*/
1695	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
1696	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1697	/**
1698	* For defining a C instruction implementation function taking one extra
1699	* argument.
1700	*
1701	* @param a_Name The name of the function
1702	* @param a_Type0 The argument type.
1703	* @param a_Arg0 The argument name.
1704	*/
1705	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
1706	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1707	/**
1708	* For calling a C instruction implementation function taking one extra
1709	* argument.
1710	*
1711	* This special call macro adds default arguments to the call and allow us to
1712	* change these later.
1713	*
1714	* @param a_fn The name of the function.
1715	* @param a0 The name of the 1st argument.
1716	*/
1717	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
1718
1719	/**
1720	* For typedef'ing or declaring a C instruction implementation function taking
1721	* two extra arguments.
1722	*
1723	* @param a_Name The name of the type.
1724	* @param a_Type0 The type of the 1st argument
1725	* @param a_Arg0 The name of the 1st argument.
1726	* @param a_Type1 The type of the 2nd argument.
1727	* @param a_Arg1 The name of the 2nd argument.
1728	*/
1729	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1730	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1731	/**
1732	* For defining a C instruction implementation function taking two extra
1733	* arguments.
1734	*
1735	* @param a_Name The name of the function.
1736	* @param a_Type0 The type of the 1st argument
1737	* @param a_Arg0 The name of the 1st argument.
1738	* @param a_Type1 The type of the 2nd argument.
1739	* @param a_Arg1 The name of the 2nd argument.
1740	*/
1741	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1742	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1743	/**
1744	* For calling a C instruction implementation function taking two extra
1745	* arguments.
1746	*
1747	* This special call macro adds default arguments to the call and allow us to
1748	* change these later.
1749	*
1750	* @param a_fn The name of the function.
1751	* @param a0 The name of the 1st argument.
1752	* @param a1 The name of the 2nd argument.
1753	*/
1754	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
1755
1756	/**
1757	* For typedef'ing or declaring a C instruction implementation function taking
1758	* three extra arguments.
1759	*
1760	* @param a_Name The name of the type.
1761	* @param a_Type0 The type of the 1st argument
1762	* @param a_Arg0 The name of the 1st argument.
1763	* @param a_Type1 The type of the 2nd argument.
1764	* @param a_Arg1 The name of the 2nd argument.
1765	* @param a_Type2 The type of the 3rd argument.
1766	* @param a_Arg2 The name of the 3rd argument.
1767	*/
1768	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1769	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1770	/**
1771	* For defining a C instruction implementation function taking three extra
1772	* arguments.
1773	*
1774	* @param a_Name The name of the function.
1775	* @param a_Type0 The type of the 1st argument
1776	* @param a_Arg0 The name of the 1st argument.
1777	* @param a_Type1 The type of the 2nd argument.
1778	* @param a_Arg1 The name of the 2nd argument.
1779	* @param a_Type2 The type of the 3rd argument.
1780	* @param a_Arg2 The name of the 3rd argument.
1781	*/
1782	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1783	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1784	/**
1785	* For calling a C instruction implementation function taking three extra
1786	* arguments.
1787	*
1788	* This special call macro adds default arguments to the call and allow us to
1789	* change these later.
1790	*
1791	* @param a_fn The name of the function.
1792	* @param a0 The name of the 1st argument.
1793	* @param a1 The name of the 2nd argument.
1794	* @param a2 The name of the 3rd argument.
1795	*/
1796	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
1797
1798
1799	/**
1800	* For typedef'ing or declaring a C instruction implementation function taking
1801	* four extra arguments.
1802	*
1803	* @param a_Name The name of the type.
1804	* @param a_Type0 The type of the 1st argument
1805	* @param a_Arg0 The name of the 1st argument.
1806	* @param a_Type1 The type of the 2nd argument.
1807	* @param a_Arg1 The name of the 2nd argument.
1808	* @param a_Type2 The type of the 3rd argument.
1809	* @param a_Arg2 The name of the 3rd argument.
1810	* @param a_Type3 The type of the 4th argument.
1811	* @param a_Arg3 The name of the 4th argument.
1812	*/
1813	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1814	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
1815	/**
1816	* For defining a C instruction implementation function taking four extra
1817	* arguments.
1818	*
1819	* @param a_Name The name of the function.
1820	* @param a_Type0 The type of the 1st argument
1821	* @param a_Arg0 The name of the 1st argument.
1822	* @param a_Type1 The type of the 2nd argument.
1823	* @param a_Arg1 The name of the 2nd argument.
1824	* @param a_Type2 The type of the 3rd argument.
1825	* @param a_Arg2 The name of the 3rd argument.
1826	* @param a_Type3 The type of the 4th argument.
1827	* @param a_Arg3 The name of the 4th argument.
1828	*/
1829	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1830	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1831	a_Type2 a_Arg2, a_Type3 a_Arg3))
1832	/**
1833	* For calling a C instruction implementation function taking four extra
1834	* arguments.
1835	*
1836	* This special call macro adds default arguments to the call and allow us to
1837	* change these later.
1838	*
1839	* @param a_fn The name of the function.
1840	* @param a0 The name of the 1st argument.
1841	* @param a1 The name of the 2nd argument.
1842	* @param a2 The name of the 3rd argument.
1843	* @param a3 The name of the 4th argument.
1844	*/
1845	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
1846
1847
1848	/**
1849	* For typedef'ing or declaring a C instruction implementation function taking
1850	* five extra arguments.
1851	*
1852	* @param a_Name The name of the type.
1853	* @param a_Type0 The type of the 1st argument
1854	* @param a_Arg0 The name of the 1st argument.
1855	* @param a_Type1 The type of the 2nd argument.
1856	* @param a_Arg1 The name of the 2nd argument.
1857	* @param a_Type2 The type of the 3rd argument.
1858	* @param a_Arg2 The name of the 3rd argument.
1859	* @param a_Type3 The type of the 4th argument.
1860	* @param a_Arg3 The name of the 4th argument.
1861	* @param a_Type4 The type of the 5th argument.
1862	* @param a_Arg4 The name of the 5th argument.
1863	*/
1864	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1865	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1866	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1867	a_Type3 a_Arg3, a_Type4 a_Arg4))
1868	/**
1869	* For defining a C instruction implementation function taking five extra
1870	* arguments.
1871	*
1872	* @param a_Name The name of the function.
1873	* @param a_Type0 The type of the 1st argument
1874	* @param a_Arg0 The name of the 1st argument.
1875	* @param a_Type1 The type of the 2nd argument.
1876	* @param a_Arg1 The name of the 2nd argument.
1877	* @param a_Type2 The type of the 3rd argument.
1878	* @param a_Arg2 The name of the 3rd argument.
1879	* @param a_Type3 The type of the 4th argument.
1880	* @param a_Arg3 The name of the 4th argument.
1881	* @param a_Type4 The type of the 5th argument.
1882	* @param a_Arg4 The name of the 5th argument.
1883	*/
1884	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1885	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPU pVCpu, uint8_t cbInstr, \
1886	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1887	a_Type3 a_Arg3, a_Type4 a_Arg4))
1888	/**
1889	* For calling a C instruction implementation function taking five extra
1890	* arguments.
1891	*
1892	* This special call macro adds default arguments to the call and allow us to
1893	* change these later.
1894	*
1895	* @param a_fn The name of the function.
1896	* @param a0 The name of the 1st argument.
1897	* @param a1 The name of the 2nd argument.
1898	* @param a2 The name of the 3rd argument.
1899	* @param a3 The name of the 4th argument.
1900	* @param a4 The name of the 5th argument.
1901	*/
1902	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
1903
1904	/** @} */
1905
1906
1907	/** @} */
1908
1909	RT_C_DECLS_END
1910
1911	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
1912

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 80055

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