IEMInternal.h@ 94163

Last change on this file since 94163 was 94163, checked in by vboxsync, 3 years ago
VMM/IEM: Try deal with basic Intel/AMD EFLAGS difference for shifts (intel side tests). bugref:9898
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1	/* $Id: IEMInternal.h 94163 2022-03-11 00:56:22Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
19	#define VMM_INCLUDED_SRC_include_IEMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/vmm/cpum.h>
25	#include <VBox/vmm/iem.h>
26	#include <VBox/vmm/pgm.h>
27	#include <VBox/vmm/stam.h>
28	#include <VBox/param.h>
29
30	#include <setjmp.h>
31
32
33	RT_C_DECLS_BEGIN
34
35
36	/** @defgroup grp_iem_int Internals
37	* @ingroup grp_iem
38	* @internal
39	* @{
40	*/
41
42	/** For expanding symbol in slickedit and other products tagging and
43	* crossreferencing IEM symbols. */
44	#ifndef IEM_STATIC
45	# define IEM_STATIC static
46	#endif
47
48	/** @def IEM_WITH_3DNOW
49	* Includes the 3DNow decoding. */
50	#define IEM_WITH_3DNOW
51
52	/** @def IEM_WITH_THREE_0F_38
53	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
54	#define IEM_WITH_THREE_0F_38
55
56	/** @def IEM_WITH_THREE_0F_3A
57	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
58	#define IEM_WITH_THREE_0F_3A
59
60	/** @def IEM_WITH_VEX
61	* Includes the VEX decoding. */
62	#define IEM_WITH_VEX
63
64	/** @def IEM_CFG_TARGET_CPU
65	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
66	*
67	* By default we allow this to be configured by the user via the
68	* CPUM/GuestCpuName config string, but this comes at a slight cost during
69	* decoding. So, for applications of this code where there is no need to
70	* be dynamic wrt target CPU, just modify this define.
71	*/
72	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
73	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
74	#endif
75
76
77	//#define IEM_WITH_CODE_TLB// - work in progress
78
79
80	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
81	/** Instruction statistics. */
82	typedef struct IEMINSTRSTATS
83	{
84	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
85	# include "IEMInstructionStatisticsTmpl.h"
86	# undef IEM_DO_INSTR_STAT
87	} IEMINSTRSTATS;
88	#else
89	struct IEMINSTRSTATS;
90	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
91	#endif
92	/** Pointer to IEM instruction statistics. */
93	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
94
95	/** Finish and move to types.h */
96	typedef union
97	{
98	uint32_t u32;
99	} RTFLOAT32U;
100	typedef RTFLOAT32U *PRTFLOAT32U;
101	typedef RTFLOAT32U const *PCRTFLOAT32U;
102
103
104	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::idxTargetCpuEflFlavour
105	* @{ */
106	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
107	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
108	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
109	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
110	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
111	/** Selects the right variant from a_aArray.
112	* pVCpu is implicit in the caller context. */
113	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
114	(a_aArray[pVCpu->iem.s.idxTargetCpuEflFlavour & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
115	/** @} */
116
117
118	/**
119	* Extended operand mode that includes a representation of 8-bit.
120	*
121	* This is used for packing down modes when invoking some C instruction
122	* implementations.
123	*/
124	typedef enum IEMMODEX
125	{
126	IEMMODEX_16BIT = IEMMODE_16BIT,
127	IEMMODEX_32BIT = IEMMODE_32BIT,
128	IEMMODEX_64BIT = IEMMODE_64BIT,
129	IEMMODEX_8BIT
130	} IEMMODEX;
131	AssertCompileSize(IEMMODEX, 4);
132
133
134	/**
135	* Branch types.
136	*/
137	typedef enum IEMBRANCH
138	{
139	IEMBRANCH_JUMP = 1,
140	IEMBRANCH_CALL,
141	IEMBRANCH_TRAP,
142	IEMBRANCH_SOFTWARE_INT,
143	IEMBRANCH_HARDWARE_INT
144	} IEMBRANCH;
145	AssertCompileSize(IEMBRANCH, 4);
146
147
148	/**
149	* INT instruction types.
150	*/
151	typedef enum IEMINT
152	{
153	/** INT n instruction (opcode 0xcd imm). */
154	IEMINT_INTN = 0,
155	/** Single byte INT3 instruction (opcode 0xcc). */
156	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
157	/** Single byte INTO instruction (opcode 0xce). */
158	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
159	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
160	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
161	} IEMINT;
162	AssertCompileSize(IEMINT, 4);
163
164
165	/**
166	* A FPU result.
167	*/
168	typedef struct IEMFPURESULT
169	{
170	/** The output value. */
171	RTFLOAT80U r80Result;
172	/** The output status. */
173	uint16_t FSW;
174	} IEMFPURESULT;
175	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
176	/** Pointer to a FPU result. */
177	typedef IEMFPURESULT *PIEMFPURESULT;
178	/** Pointer to a const FPU result. */
179	typedef IEMFPURESULT const *PCIEMFPURESULT;
180
181
182	/**
183	* A FPU result consisting of two output values and FSW.
184	*/
185	typedef struct IEMFPURESULTTWO
186	{
187	/** The first output value. */
188	RTFLOAT80U r80Result1;
189	/** The output status. */
190	uint16_t FSW;
191	/** The second output value. */
192	RTFLOAT80U r80Result2;
193	} IEMFPURESULTTWO;
194	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
195	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
196	/** Pointer to a FPU result consisting of two output values and FSW. */
197	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
198	/** Pointer to a const FPU result consisting of two output values and FSW. */
199	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
200
201
202	/**
203	* IEM TLB entry.
204	*
205	* Lookup assembly:
206	* @code{.asm}
207	; Calculate tag.
208	mov rax, [VA]
209	shl rax, 16
210	shr rax, 16 + X86_PAGE_SHIFT
211	or rax, [uTlbRevision]
212
213	; Do indexing.
214	movzx ecx, al
215	lea rcx, [pTlbEntries + rcx]
216
217	; Check tag.
218	cmp [rcx + IEMTLBENTRY.uTag], rax
219	jne .TlbMiss
220
221	; Check access.
222	movsx rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
223	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
224	cmp rax, [uTlbPhysRev]
225	jne .TlbMiss
226
227	; Calc address and we're done.
228	mov eax, X86_PAGE_OFFSET_MASK
229	and eax, [VA]
230	or rax, [rcx + IEMTLBENTRY.pMappingR3]
231	%ifdef VBOX_WITH_STATISTICS
232	inc qword [cTlbHits]
233	%endif
234	jmp .Done
235
236	.TlbMiss:
237	mov r8d, ACCESS_FLAGS
238	mov rdx, [VA]
239	mov rcx, [pVCpu]
240	call iemTlbTypeMiss
241	.Done:
242
243	@endcode
244	*
245	*/
246	typedef struct IEMTLBENTRY
247	{
248	/** The TLB entry tag.
249	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits.
250	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
251	*
252	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
253	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
254	* revision wraps around though, the tags needs to be zeroed.
255	*
256	* @note Try use SHRD instruction? After seeing
257	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
258	*/
259	uint64_t uTag;
260	/** Access flags and physical TLB revision.
261	*
262	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
263	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
264	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
265	* - Bit 3 - pgm phys/virt - not directly writable.
266	* - Bit 4 - pgm phys page - not directly readable.
267	* - Bit 5 - currently unused.
268	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
269	* - Bit 7 - tlb entry - pMappingR3 member not valid.
270	* - Bits 63 thru 8 are used for the physical TLB revision number.
271	*
272	* We're using complemented bit meanings here because it makes it easy to check
273	* whether special action is required. For instance a user mode write access
274	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
275	* non-zero result would mean special handling needed because either it wasn't
276	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
277	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
278	* need to check any PTE flag.
279	*/
280	uint64_t fFlagsAndPhysRev;
281	/** The guest physical page address. */
282	uint64_t GCPhys;
283	/** Pointer to the ring-3 mapping (possibly also valid in ring-0). */
284	R3PTRTYPE(uint8_t *) pbMappingR3;
285	#if HC_ARCH_BITS == 32
286	uint32_t u32Padding1;
287	#endif
288	} IEMTLBENTRY;
289	AssertCompileSize(IEMTLBENTRY, 32);
290	/** Pointer to an IEM TLB entry. */
291	typedef IEMTLBENTRY *PIEMTLBENTRY;
292
293	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
294	* @{ */
295	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
296	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
297	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
298	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
299	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
300	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(5) /*< Page tables: Not dirty (needs to be made dirty on write). /
301	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(6) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
302	#define IEMTLBE_F_PHYS_REV UINT64_C(0xffffffffffffff00) /*< Physical revision mask. /
303	/** @} */
304
305
306	/**
307	* An IEM TLB.
308	*
309	* We've got two of these, one for data and one for instructions.
310	*/
311	typedef struct IEMTLB
312	{
313	/** The TLB entries.
314	* We've choosen 256 because that way we can obtain the result directly from a
315	* 8-bit register without an additional AND instruction. */
316	IEMTLBENTRY aEntries[256];
317	/** The TLB revision.
318	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
319	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
320	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
321	* (The revision zero indicates an invalid TLB entry.)
322	*
323	* The initial value is choosen to cause an early wraparound. */
324	uint64_t uTlbRevision;
325	/** The TLB physical address revision - shadow of PGM variable.
326	*
327	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
328	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
329	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
330	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
331	*
332	* The initial value is choosen to cause an early wraparound. */
333	uint64_t volatile uTlbPhysRev;
334
335	/* Statistics: */
336
337	/** TLB hits (VBOX_WITH_STATISTICS only). */
338	uint64_t cTlbHits;
339	/** TLB misses. */
340	uint32_t cTlbMisses;
341	/** Slow read path. */
342	uint32_t cTlbSlowReadPath;
343	#if 0
344	/** TLB misses because of tag mismatch. */
345	uint32_t cTlbMissesTag;
346	/** TLB misses because of virtual access violation. */
347	uint32_t cTlbMissesVirtAccess;
348	/** TLB misses because of dirty bit. */
349	uint32_t cTlbMissesDirty;
350	/** TLB misses because of MMIO */
351	uint32_t cTlbMissesMmio;
352	/** TLB misses because of write access handlers. */
353	uint32_t cTlbMissesWriteHandler;
354	/** TLB misses because no r3(/r0) mapping. */
355	uint32_t cTlbMissesMapping;
356	#endif
357	/** Alignment padding. */
358	uint32_t au32Padding[3+5];
359	} IEMTLB;
360	AssertCompileSizeAlignment(IEMTLB, 64);
361	/** IEMTLB::uTlbRevision increment. */
362	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
363	/** IEMTLB::uTlbPhysRev increment. */
364	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(8)
365
366
367	/**
368	* The per-CPU IEM state.
369	*/
370	typedef struct IEMCPU
371	{
372	/** Info status code that needs to be propagated to the IEM caller.
373	* This cannot be passed internally, as it would complicate all success
374	* checks within the interpreter making the code larger and almost impossible
375	* to get right. Instead, we'll store status codes to pass on here. Each
376	* source of these codes will perform appropriate sanity checks. */
377	int32_t rcPassUp; /* 0x00 */
378
379	/** The current CPU execution mode (CS). */
380	IEMMODE enmCpuMode; /* 0x04 */
381	/** The CPL. */
382	uint8_t uCpl; /* 0x05 */
383
384	/** Whether to bypass access handlers or not. */
385	bool fBypassHandlers; /* 0x06 */
386	/** Whether to disregard the lock prefix (implied or not). */
387	bool fDisregardLock; /* 0x07 */
388
389	/** @name Decoder state.
390	* @{ */
391	#ifdef IEM_WITH_CODE_TLB
392	/** The offset of the next instruction byte. */
393	uint32_t offInstrNextByte; /* 0x08 */
394	/** The number of bytes available at pbInstrBuf for the current instruction.
395	* This takes the max opcode length into account so that doesn't need to be
396	* checked separately. */
397	uint32_t cbInstrBuf; /* 0x0c */
398	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
399	* This can be NULL if the page isn't mappable for some reason, in which
400	* case we'll do fallback stuff.
401	*
402	* If we're executing an instruction from a user specified buffer,
403	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
404	* aligned pointer but pointer to the user data.
405	*
406	* For instructions crossing pages, this will start on the first page and be
407	* advanced to the next page by the time we've decoded the instruction. This
408	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
409	*/
410	uint8_t const pbInstrBuf; / 0x10 */
411	# if ARCH_BITS == 32
412	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
413	# endif
414	/** The program counter corresponding to pbInstrBuf.
415	* This is set to a non-canonical address when we need to invalidate it. */
416	uint64_t uInstrBufPc; /* 0x18 */
417	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
418	* This takes the CS segment limit into account. */
419	uint16_t cbInstrBufTotal; /* 0x20 */
420	/** Offset into pbInstrBuf of the first byte of the current instruction.
421	* Can be negative to efficiently handle cross page instructions. */
422	int16_t offCurInstrStart; /* 0x22 */
423
424	/** The prefix mask (IEM_OP_PRF_XXX). */
425	uint32_t fPrefixes; /* 0x24 */
426	/** The extra REX ModR/M register field bit (REX.R << 3). */
427	uint8_t uRexReg; /* 0x28 */
428	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
429	* (REX.B << 3). */
430	uint8_t uRexB; /* 0x29 */
431	/** The extra REX SIB index field bit (REX.X << 3). */
432	uint8_t uRexIndex; /* 0x2a */
433
434	/** The effective segment register (X86_SREG_XXX). */
435	uint8_t iEffSeg; /* 0x2b */
436
437	/** The offset of the ModR/M byte relative to the start of the instruction. */
438	uint8_t offModRm; /* 0x2c */
439	#else
440	/** The size of what has currently been fetched into abOpcode. */
441	uint8_t cbOpcode; /* 0x08 */
442	/** The current offset into abOpcode. */
443	uint8_t offOpcode; /* 0x09 */
444	/** The offset of the ModR/M byte relative to the start of the instruction. */
445	uint8_t offModRm; /* 0x0a */
446
447	/** The effective segment register (X86_SREG_XXX). */
448	uint8_t iEffSeg; /* 0x0b */
449
450	/** The prefix mask (IEM_OP_PRF_XXX). */
451	uint32_t fPrefixes; /* 0x0c */
452	/** The extra REX ModR/M register field bit (REX.R << 3). */
453	uint8_t uRexReg; /* 0x10 */
454	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
455	* (REX.B << 3). */
456	uint8_t uRexB; /* 0x11 */
457	/** The extra REX SIB index field bit (REX.X << 3). */
458	uint8_t uRexIndex; /* 0x12 */
459
460	#endif
461
462	/** The effective operand mode. */
463	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
464	/** The default addressing mode. */
465	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
466	/** The effective addressing mode. */
467	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
468	/** The default operand mode. */
469	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
470
471	/** Prefix index (VEX.pp) for two byte and three byte tables. */
472	uint8_t idxPrefix; /* 0x31, 0x17 */
473	/** 3rd VEX/EVEX/XOP register.
474	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
475	uint8_t uVex3rdReg; /* 0x32, 0x18 */
476	/** The VEX/EVEX/XOP length field. */
477	uint8_t uVexLength; /* 0x33, 0x19 */
478	/** Additional EVEX stuff. */
479	uint8_t fEvexStuff; /* 0x34, 0x1a */
480
481	/** Explicit alignment padding. */
482	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
483	/** The FPU opcode (FOP). */
484	uint16_t uFpuOpcode; /* 0x36, 0x1c */
485	#ifndef IEM_WITH_CODE_TLB
486	/** Explicit alignment padding. */
487	uint8_t abAlignment2b[2]; /* 0x1e */
488	#endif
489
490	/** The opcode bytes. */
491	uint8_t abOpcode[15]; /* 0x48, 0x20 */
492	/** Explicit alignment padding. */
493	#ifdef IEM_WITH_CODE_TLB
494	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
495	#else
496	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
497	#endif
498	/** @} */
499
500
501	/** The flags of the current exception / interrupt. */
502	uint32_t fCurXcpt; /* 0x48, 0x48 */
503	/** The current exception / interrupt. */
504	uint8_t uCurXcpt;
505	/** Exception / interrupt recursion depth. */
506	int8_t cXcptRecursions;
507
508	/** The number of active guest memory mappings. */
509	uint8_t cActiveMappings;
510	/** The next unused mapping index. */
511	uint8_t iNextMapping;
512	/** Records for tracking guest memory mappings. */
513	struct
514	{
515	/** The address of the mapped bytes. */
516	void *pv;
517	/** The access flags (IEM_ACCESS_XXX).
518	* IEM_ACCESS_INVALID if the entry is unused. */
519	uint32_t fAccess;
520	#if HC_ARCH_BITS == 64
521	uint32_t u32Alignment4; /*< Alignment padding. /
522	#endif
523	} aMemMappings[3];
524
525	/** Locking records for the mapped memory. */
526	union
527	{
528	PGMPAGEMAPLOCK Lock;
529	uint64_t au64Padding[2];
530	} aMemMappingLocks[3];
531
532	/** Bounce buffer info.
533	* This runs in parallel to aMemMappings. */
534	struct
535	{
536	/** The physical address of the first byte. */
537	RTGCPHYS GCPhysFirst;
538	/** The physical address of the second page. */
539	RTGCPHYS GCPhysSecond;
540	/** The number of bytes in the first page. */
541	uint16_t cbFirst;
542	/** The number of bytes in the second page. */
543	uint16_t cbSecond;
544	/** Whether it's unassigned memory. */
545	bool fUnassigned;
546	/** Explicit alignment padding. */
547	bool afAlignment5[3];
548	} aMemBbMappings[3];
549
550	/** Bounce buffer storage.
551	* This runs in parallel to aMemMappings and aMemBbMappings. */
552	struct
553	{
554	uint8_t ab[512];
555	} aBounceBuffers[3];
556
557
558	/** Pointer set jump buffer - ring-3 context. */
559	R3PTRTYPE(jmp_buf *) pJmpBufR3;
560	/** Pointer set jump buffer - ring-0 context. */
561	R0PTRTYPE(jmp_buf *) pJmpBufR0;
562
563	/** @todo Should move this near @a fCurXcpt later. */
564	/** The CR2 for the current exception / interrupt. */
565	uint64_t uCurXcptCr2;
566	/** The error code for the current exception / interrupt. */
567	uint32_t uCurXcptErr;
568
569	/** @name Statistics
570	* @{ */
571	/** The number of instructions we've executed. */
572	uint32_t cInstructions;
573	/** The number of potential exits. */
574	uint32_t cPotentialExits;
575	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
576	* This may contain uncommitted writes. */
577	uint32_t cbWritten;
578	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
579	uint32_t cRetInstrNotImplemented;
580	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
581	uint32_t cRetAspectNotImplemented;
582	/** Counts informational statuses returned (other than VINF_SUCCESS). */
583	uint32_t cRetInfStatuses;
584	/** Counts other error statuses returned. */
585	uint32_t cRetErrStatuses;
586	/** Number of times rcPassUp has been used. */
587	uint32_t cRetPassUpStatus;
588	/** Number of times RZ left with instruction commit pending for ring-3. */
589	uint32_t cPendingCommit;
590	/** Number of long jumps. */
591	uint32_t cLongJumps;
592	/** @} */
593
594	/** @name Target CPU information.
595	* @{ */
596	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
597	/** The target CPU. */
598	uint8_t uTargetCpu;
599	#else
600	uint8_t bTargetCpuPadding;
601	#endif
602	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
603	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values. This is for instance used for the
604	* BSF & BSR instructions where AMD and Intel CPUs produce different EFLAGS. */
605	uint8_t idxTargetCpuEflFlavour;
606
607	/** The CPU vendor. */
608	CPUMCPUVENDOR enmCpuVendor;
609	/** @} */
610
611	/** @name Host CPU information.
612	* @{ */
613	/** The CPU vendor. */
614	CPUMCPUVENDOR enmHostCpuVendor;
615	/** @} */
616
617	/** Counts RDMSR \#GP(0) LogRel(). */
618	uint8_t cLogRelRdMsr;
619	/** Counts WRMSR \#GP(0) LogRel(). */
620	uint8_t cLogRelWrMsr;
621	/** Alignment padding. */
622	uint8_t abAlignment8[50];
623
624	/** Data TLB.
625	* @remarks Must be 64-byte aligned. */
626	IEMTLB DataTlb;
627	/** Instruction TLB.
628	* @remarks Must be 64-byte aligned. */
629	IEMTLB CodeTlb;
630
631	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
632	/** Instruction statistics for ring-0/raw-mode. */
633	IEMINSTRSTATS StatsRZ;
634	/** Instruction statistics for ring-3. */
635	IEMINSTRSTATS StatsR3;
636	#endif
637	} IEMCPU;
638	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
639	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
640	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
641	/** Pointer to the per-CPU IEM state. */
642	typedef IEMCPU *PIEMCPU;
643	/** Pointer to the const per-CPU IEM state. */
644	typedef IEMCPU const *PCIEMCPU;
645
646
647	/** @def IEM_GET_CTX
648	* Gets the guest CPU context for the calling EMT.
649	* @returns PCPUMCTX
650	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
651	*/
652	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
653
654	/** @def IEM_CTX_ASSERT
655	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
656	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
657	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
658	*/
659	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
660	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
661	(a_fExtrnMbz)))
662
663	/** @def IEM_CTX_IMPORT_RET
664	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
665	*
666	* Will call the keep to import the bits as needed.
667	*
668	* Returns on import failure.
669	*
670	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
671	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
672	*/
673	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
674	do { \
675	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
676	{ /* likely */ } \
677	else \
678	{ \
679	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
680	AssertRCReturn(rcCtxImport, rcCtxImport); \
681	} \
682	} while (0)
683
684	/** @def IEM_CTX_IMPORT_NORET
685	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
686	*
687	* Will call the keep to import the bits as needed.
688	*
689	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
690	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
691	*/
692	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
693	do { \
694	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
695	{ /* likely */ } \
696	else \
697	{ \
698	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
699	AssertLogRelRC(rcCtxImport); \
700	} \
701	} while (0)
702
703	/** @def IEM_CTX_IMPORT_JMP
704	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
705	*
706	* Will call the keep to import the bits as needed.
707	*
708	* Jumps on import failure.
709	*
710	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
711	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
712	*/
713	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
714	do { \
715	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
716	{ /* likely */ } \
717	else \
718	{ \
719	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
720	AssertRCStmt(rcCtxImport, longjmp(*pVCpu->iem.s.CTX_SUFF(pJmpBuf), rcCtxImport)); \
721	} \
722	} while (0)
723
724
725
726	/** @def IEM_GET_TARGET_CPU
727	* Gets the current IEMTARGETCPU value.
728	* @returns IEMTARGETCPU value.
729	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
730	*/
731	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
732	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
733	#else
734	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
735	#endif
736
737	/** @def IEM_GET_INSTR_LEN
738	* Gets the instruction length. */
739	#ifdef IEM_WITH_CODE_TLB
740	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
741	#else
742	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
743	#endif
744
745
746	/**
747	* Shared per-VM IEM data.
748	*/
749	typedef struct IEM
750	{
751	/** The VMX APIC-access page handler type. */
752	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
753	} IEM;
754
755
756
757	/** @name IEM_ACCESS_XXX - Access details.
758	* @{ */
759	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
760	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
761	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
762	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
763	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
764	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
765	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
766	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
767	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
768	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
769	/** The writes are partial, so if initialize the bounce buffer with the
770	* orignal RAM content. */
771	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
772	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
773	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
774	/** Bounce buffer with ring-3 write pending, first page. */
775	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
776	/** Bounce buffer with ring-3 write pending, second page. */
777	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
778	/** Valid bit mask. */
779	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00000fff)
780	/** Read+write data alias. */
781	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
782	/** Write data alias. */
783	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
784	/** Read data alias. */
785	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
786	/** Instruction fetch alias. */
787	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
788	/** Stack write alias. */
789	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
790	/** Stack read alias. */
791	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
792	/** Stack read+write alias. */
793	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
794	/** Read system table alias. */
795	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
796	/** Read+write system table alias. */
797	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
798	/** @} */
799
800	/** @name Prefix constants (IEMCPU::fPrefixes)
801	* @{ */
802	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
803	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
804	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
805	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
806	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
807	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
808	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
809
810	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
811	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
812	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
813
814	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
815	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
816	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
817
818	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
819	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
820	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
821	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
822	/** Mask with all the REX prefix flags.
823	* This is generally for use when needing to undo the REX prefixes when they
824	* are followed legacy prefixes and therefore does not immediately preceed
825	* the first opcode byte.
826	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
827	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
828
829	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
830	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
831	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
832	/** @} */
833
834	/** @name IEMOPFORM_XXX - Opcode forms
835	* @note These are ORed together with IEMOPHINT_XXX.
836	* @{ */
837	/** ModR/M: reg, r/m */
838	#define IEMOPFORM_RM 0
839	/** ModR/M: reg, r/m (register) */
840	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
841	/** ModR/M: reg, r/m (memory) */
842	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
843	/** ModR/M: r/m, reg */
844	#define IEMOPFORM_MR 1
845	/** ModR/M: r/m (register), reg */
846	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
847	/** ModR/M: r/m (memory), reg */
848	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
849	/** ModR/M: r/m only */
850	#define IEMOPFORM_M 2
851	/** ModR/M: r/m only (register). */
852	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
853	/** ModR/M: r/m only (memory). */
854	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
855	/** ModR/M: reg only */
856	#define IEMOPFORM_R 3
857
858	/** VEX+ModR/M: reg, r/m */
859	#define IEMOPFORM_VEX_RM 4
860	/** VEX+ModR/M: reg, r/m (register) */
861	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
862	/** VEX+ModR/M: reg, r/m (memory) */
863	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
864	/** VEX+ModR/M: r/m, reg */
865	#define IEMOPFORM_VEX_MR 5
866	/** VEX+ModR/M: r/m (register), reg */
867	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
868	/** VEX+ModR/M: r/m (memory), reg */
869	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
870	/** VEX+ModR/M: r/m only */
871	#define IEMOPFORM_VEX_M 6
872	/** VEX+ModR/M: r/m only (register). */
873	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
874	/** VEX+ModR/M: r/m only (memory). */
875	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
876	/** VEX+ModR/M: reg only */
877	#define IEMOPFORM_VEX_R 7
878	/** VEX+ModR/M: reg, vvvv, r/m */
879	#define IEMOPFORM_VEX_RVM 8
880	/** VEX+ModR/M: reg, vvvv, r/m (register). */
881	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
882	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
883	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
884	/** VEX+ModR/M: r/m, vvvv, reg */
885	#define IEMOPFORM_VEX_MVR 9
886	/** VEX+ModR/M: r/m, vvvv, reg (register) */
887	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
888	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
889	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
890
891	/** Fixed register instruction, no R/M. */
892	#define IEMOPFORM_FIXED 16
893
894	/** The r/m is a register. */
895	#define IEMOPFORM_MOD3 RT_BIT_32(8)
896	/** The r/m is a memory access. */
897	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
898	/** @} */
899
900	/** @name IEMOPHINT_XXX - Additional Opcode Hints
901	* @note These are ORed together with IEMOPFORM_XXX.
902	* @{ */
903	/** Ignores the operand size prefix (66h). */
904	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
905	/** Ignores REX.W (aka WIG). */
906	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
907	/** Both the operand size prefixes (66h + REX.W) are ignored. */
908	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
909	/** Allowed with the lock prefix. */
910	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
911	/** The VEX.L value is ignored (aka LIG). */
912	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
913	/** The VEX.L value must be zero (i.e. 128-bit width only). */
914	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
915
916	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
917	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
918	/** @} */
919
920	/**
921	* Possible hardware task switch sources.
922	*/
923	typedef enum IEMTASKSWITCH
924	{
925	/** Task switch caused by an interrupt/exception. */
926	IEMTASKSWITCH_INT_XCPT = 1,
927	/** Task switch caused by a far CALL. */
928	IEMTASKSWITCH_CALL,
929	/** Task switch caused by a far JMP. */
930	IEMTASKSWITCH_JUMP,
931	/** Task switch caused by an IRET. */
932	IEMTASKSWITCH_IRET
933	} IEMTASKSWITCH;
934	AssertCompileSize(IEMTASKSWITCH, 4);
935
936	/**
937	* Possible CrX load (write) sources.
938	*/
939	typedef enum IEMACCESSCRX
940	{
941	/** CrX access caused by 'mov crX' instruction. */
942	IEMACCESSCRX_MOV_CRX,
943	/** CrX (CR0) write caused by 'lmsw' instruction. */
944	IEMACCESSCRX_LMSW,
945	/** CrX (CR0) write caused by 'clts' instruction. */
946	IEMACCESSCRX_CLTS,
947	/** CrX (CR0) read caused by 'smsw' instruction. */
948	IEMACCESSCRX_SMSW
949	} IEMACCESSCRX;
950
951	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
952	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
953	*
954	* These flags provide further context to SLAT page-walk failures that could not be
955	* determined by PGM (e.g, PGM is not privy to memory access permissions).
956	*
957	* @{
958	*/
959	/** Translating a nested-guest linear address failed accessing a nested-guest
960	* physical address. */
961	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
962	/** Translating a nested-guest linear address failed accessing a
963	* paging-structure entry or updating accessed/dirty bits. */
964	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
965	/** @} */
966
967	PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
968	# ifndef IN_RING3
969	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
970	# endif
971	#endif
972
973	/**
974	* Indicates to the verifier that the given flag set is undefined.
975	*
976	* Can be invoked again to add more flags.
977	*
978	* This is a NOOP if the verifier isn't compiled in.
979	*
980	* @note We're temporarily keeping this until code is converted to new
981	* disassembler style opcode handling.
982	*/
983	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
984
985
986	/** @def IEM_DECL_IMPL_TYPE
987	* For typedef'ing an instruction implementation function.
988	*
989	* @param a_RetType The return type.
990	* @param a_Name The name of the type.
991	* @param a_ArgList The argument list enclosed in parentheses.
992	*/
993
994	/** @def IEM_DECL_IMPL_DEF
995	* For defining an instruction implementation function.
996	*
997	* @param a_RetType The return type.
998	* @param a_Name The name of the type.
999	* @param a_ArgList The argument list enclosed in parentheses.
1000	*/
1001
1002	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1003	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1004	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1005	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1006	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1007
1008	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1009	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1010	a_RetType (__fastcall a_Name) a_ArgList
1011	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1012	a_RetType __fastcall a_Name a_ArgList
1013
1014	#else
1015	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1016	a_RetType (VBOXCALL a_Name) a_ArgList
1017	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1018	a_RetType VBOXCALL a_Name a_ArgList
1019
1020	#endif
1021
1022	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1023	RT_C_DECLS_BEGIN
1024	extern uint8_t const g_afParity[256];
1025	RT_C_DECLS_END
1026
1027
1028	/** @name Arithmetic assignment operations on bytes (binary).
1029	* @{ */
1030	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1031	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1032	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1033	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1034	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1035	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1036	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1037	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1038	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1039	/** @} */
1040
1041	/** @name Arithmetic assignment operations on words (binary).
1042	* @{ */
1043	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1044	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1045	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1046	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1047	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1048	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1049	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1050	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1051	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1052	/** @} */
1053
1054	/** @name Arithmetic assignment operations on double words (binary).
1055	* @{ */
1056	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1057	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1058	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1059	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1060	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1061	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1062	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1063	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1064	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1065	/** @} */
1066
1067	/** @name Arithmetic assignment operations on quad words (binary).
1068	* @{ */
1069	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1070	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1071	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1072	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1073	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1074	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1075	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1076	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1077	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1078	/** @} */
1079
1080	/** @name Compare operations (thrown in with the binary ops).
1081	* @{ */
1082	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1083	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1084	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1085	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1086	/** @} */
1087
1088	/** @name Test operations (thrown in with the binary ops).
1089	* @{ */
1090	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1091	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1092	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1093	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1094	/** @} */
1095
1096	/** @name Bit operations operations (thrown in with the binary ops).
1097	* @{ */
1098	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1099	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1100	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1101	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1102	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1103	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1104	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1105	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1106	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1107	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1108	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1109	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1110	/** @} */
1111
1112	/** @name Exchange memory with register operations.
1113	* @{ */
1114	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1115	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1116	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1117	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1118	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1119	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1120	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1121	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1122	/** @} */
1123
1124	/** @name Exchange and add operations.
1125	* @{ */
1126	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1127	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1128	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1129	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1130	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1131	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1132	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1133	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1134	/** @} */
1135
1136	/** @name Compare and exchange.
1137	* @{ */
1138	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1139	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1140	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1141	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1142	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1143	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1144	#if ARCH_BITS == 32
1145	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1146	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1147	#else
1148	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1149	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1150	#endif
1151	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1152	uint32_t *pEFlags));
1153	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1154	uint32_t *pEFlags));
1155	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1156	uint32_t *pEFlags));
1157	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1158	uint32_t *pEFlags));
1159	#ifndef RT_ARCH_ARM64
1160	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1161	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1162	#endif
1163	/** @} */
1164
1165	/** @name Memory ordering
1166	* @{ */
1167	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1168	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1169	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1170	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1171	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1172	#ifndef RT_ARCH_ARM64
1173	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1174	#endif
1175	/** @} */
1176
1177	/** @name Double precision shifts
1178	* @{ */
1179	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1180	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1181	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1182	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1183	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1184	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1185	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1186	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1187	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1188	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1189	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1190	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1191	/** @} */
1192
1193
1194	/** @name Bit search operations (thrown in with the binary ops).
1195	* @{ */
1196	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1197	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1198	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1199	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1200	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1201	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1202	/** @} */
1203
1204	/** @name Signed multiplication operations (thrown in with the binary ops).
1205	* @{ */
1206	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1207	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1208	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1209	/** @} */
1210
1211	/** @name Arithmetic assignment operations on bytes (unary).
1212	* @{ */
1213	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1214	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1215	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1216	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1217	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1218	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1219	/** @} */
1220
1221	/** @name Arithmetic assignment operations on words (unary).
1222	* @{ */
1223	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1224	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1225	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1226	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1227	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1228	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1229	/** @} */
1230
1231	/** @name Arithmetic assignment operations on double words (unary).
1232	* @{ */
1233	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1234	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1235	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1236	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1237	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1238	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1239	/** @} */
1240
1241	/** @name Arithmetic assignment operations on quad words (unary).
1242	* @{ */
1243	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1244	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1245	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1246	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1247	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1248	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1249	/** @} */
1250
1251
1252	/** @name Shift operations on bytes (Group 2).
1253	* @{ */
1254	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1255	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1256	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1257	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1258	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1259	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1260	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1261	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1262	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1263	/** @} */
1264
1265	/** @name Shift operations on words (Group 2).
1266	* @{ */
1267	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1268	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1269	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1270	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1271	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1272	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1273	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1274	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1275	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1276	/** @} */
1277
1278	/** @name Shift operations on double words (Group 2).
1279	* @{ */
1280	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1281	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1282	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1283	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1284	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1285	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1286	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1287	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1288	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1289	/** @} */
1290
1291	/** @name Shift operations on words (Group 2).
1292	* @{ */
1293	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1294	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1295	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1296	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1297	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1298	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1299	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1300	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1301	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1302	/** @} */
1303
1304	/** @name Multiplication and division operations.
1305	* @{ */
1306	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1307	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1308	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1309	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1310	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1311	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1312
1313	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1314	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1315	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1316	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1317	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1318	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1319
1320	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1321	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1322	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1323	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1324	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1325	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1326
1327	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1328	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1329	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1330	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1331	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1332	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1333	/** @} */
1334
1335	/** @name Byte Swap.
1336	* @{ */
1337	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1338	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1339	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1340	/** @} */
1341
1342	/** @name Misc.
1343	* @{ */
1344	FNIEMAIMPLBINU16 iemAImpl_arpl;
1345	/** @} */
1346
1347
1348	/** @name FPU operations taking a 32-bit float argument
1349	* @{ */
1350	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1351	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1352	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1353
1354	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1355	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1356	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1357
1358	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1359	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1360	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1361	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1362	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1363	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1364	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1365
1366	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1367	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1368	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1369	/** @} */
1370
1371	/** @name FPU operations taking a 64-bit float argument
1372	* @{ */
1373	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1374	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1375	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1376
1377	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1378	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1379	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1380	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1381	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1382	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1383
1384	IEM_DECL_IMPL_DEF(void, iemAImpl_fcom_r80_by_r64,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1385	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1386	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1387	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1388	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1389	/** @} */
1390
1391	/** @name FPU operations taking a 80-bit float argument
1392	* @{ */
1393	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1394	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1395	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1396	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1397	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1398	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1399	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1400	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1401	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1402	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1403	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1404	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1405
1406	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80;
1407	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80;
1408	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80;
1409
1410	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1411	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1412	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1413	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1414	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1415
1416	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1417	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1418	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1419	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1420	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1421
1422	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1423	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1424	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1425	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1426	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80;
1427	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1428	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1429	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80;
1430	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80;
1431
1432	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1433	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1434	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1435	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1436
1437	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1438	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1439	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1440	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1441	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1442	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1443	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1444	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1445	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1446
1447	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1448	PCRTFLOAT80U pr80Val));
1449	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1450	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80;
1451	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1452	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80;
1453
1454	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1455	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1456	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1457
1458	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
1459	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1460	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
1461
1462	/** @} */
1463
1464	/** @name FPU operations taking a 16-bit signed integer argument
1465	* @{ */
1466	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1467	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1468	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1469
1470	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1471	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1472	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1473	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1474	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1475	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1476
1477	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1478	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1479
1480	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i16_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1481	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1482	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1483	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i16,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1484	int16_t *pi16Val, PCRTFLOAT80U pr80Val));
1485	/** @} */
1486
1487	/** @name FPU operations taking a 32-bit signed integer argument
1488	* @{ */
1489	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1490	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1491	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1492
1493	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1494	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1495	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1496	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1497	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1498	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1499
1500	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1501	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1502
1503	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i32_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1504	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1505	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1506	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1507	int32_t *pi32Val, PCRTFLOAT80U pr80Val));
1508	/** @} */
1509
1510	/** @name FPU operations taking a 64-bit signed integer argument
1511	* @{ */
1512	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1513	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1514	typedef FNIEMAIMPLFPUI64 *PFNIEMAIMPLFPUI64;
1515
1516	FNIEMAIMPLFPUI64 iemAImpl_fiadd_r80_by_i64;
1517	FNIEMAIMPLFPUI64 iemAImpl_fimul_r80_by_i64;
1518	FNIEMAIMPLFPUI64 iemAImpl_fisub_r80_by_i64;
1519	FNIEMAIMPLFPUI64 iemAImpl_fisubr_r80_by_i64;
1520	FNIEMAIMPLFPUI64 iemAImpl_fidiv_r80_by_i64;
1521	FNIEMAIMPLFPUI64 iemAImpl_fidivr_r80_by_i64;
1522
1523	IEM_DECL_IMPL_DEF(void, iemAImpl_ficom_r80_by_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1524	PCRTFLOAT80U pr80Val1, int64_t const *pi64Val2));
1525
1526	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_i64_to_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1527	IEM_DECL_IMPL_DEF(void, iemAImpl_fist_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1528	int64_t *pi64Val, PCRTFLOAT80U pr80Val));
1529	IEM_DECL_IMPL_DEF(void, iemAImpl_fistt_r80_to_i64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1530	int64_t *pi32Val, PCRTFLOAT80U pr80Val));
1531	/** @} */
1532
1533
1534	/** Temporary type representing a 256-bit vector register. */
1535	typedef struct {uint64_t au64[4]; } IEMVMM256;
1536	/** Temporary type pointing to a 256-bit vector register. */
1537	typedef IEMVMM256 *PIEMVMM256;
1538	/** Temporary type pointing to a const 256-bit vector register. */
1539	typedef IEMVMM256 *PCIEMVMM256;
1540
1541
1542	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1543	* @{ */
1544	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1545	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1546	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1547	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1548	FNIEMAIMPLMEDIAF2U64 iemAImpl_pxor_u64, iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1549	FNIEMAIMPLMEDIAF2U128 iemAImpl_pxor_u128, iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1550	/** @} */
1551
1552	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1553	* @{ */
1554	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src));
1555	typedef FNIEMAIMPLMEDIAF1L1U64 *PFNIEMAIMPLMEDIAF1L1U64;
1556	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src));
1557	typedef FNIEMAIMPLMEDIAF1L1U128 *PFNIEMAIMPLMEDIAF1L1U128;
1558	FNIEMAIMPLMEDIAF1L1U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1559	FNIEMAIMPLMEDIAF1L1U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1560	/** @} */
1561
1562	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
1563	* @{ */
1564	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1565	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF1H1U64;
1566	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1567	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF1H1U128;
1568	FNIEMAIMPLMEDIAF1H1U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
1569	FNIEMAIMPLMEDIAF1H1U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
1570	/** @} */
1571
1572	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
1573	* @{ */
1574	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUF,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst,
1575	PCRTUINT128U pu128Src, uint8_t bEvil));
1576	typedef FNIEMAIMPLMEDIAPSHUF *PFNIEMAIMPLMEDIAPSHUF;
1577	FNIEMAIMPLMEDIAPSHUF iemAImpl_pshufhw, iemAImpl_pshuflw, iemAImpl_pshufd;
1578	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil));
1579	/** @} */
1580
1581	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
1582	* @{ */
1583	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1584	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src));
1585	/** @} */
1586
1587	/** @name Media (SSE/MMX/AVX) operation: Sort this later
1588	* @{ */
1589	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1590	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1591	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc));
1592
1593	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1594	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1595	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1596	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1597
1598	/** @} */
1599
1600
1601	/** @name Function tables.
1602	* @{
1603	*/
1604
1605	/**
1606	* Function table for a binary operator providing implementation based on
1607	* operand size.
1608	*/
1609	typedef struct IEMOPBINSIZES
1610	{
1611	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
1612	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
1613	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
1614	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
1615	} IEMOPBINSIZES;
1616	/** Pointer to a binary operator function table. */
1617	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
1618
1619
1620	/**
1621	* Function table for a unary operator providing implementation based on
1622	* operand size.
1623	*/
1624	typedef struct IEMOPUNARYSIZES
1625	{
1626	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
1627	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
1628	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
1629	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
1630	} IEMOPUNARYSIZES;
1631	/** Pointer to a unary operator function table. */
1632	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
1633
1634
1635	/**
1636	* Function table for a shift operator providing implementation based on
1637	* operand size.
1638	*/
1639	typedef struct IEMOPSHIFTSIZES
1640	{
1641	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
1642	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
1643	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
1644	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
1645	} IEMOPSHIFTSIZES;
1646	/** Pointer to a shift operator function table. */
1647	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
1648
1649
1650	/**
1651	* Function table for a multiplication or division operation.
1652	*/
1653	typedef struct IEMOPMULDIVSIZES
1654	{
1655	PFNIEMAIMPLMULDIVU8 pfnU8;
1656	PFNIEMAIMPLMULDIVU16 pfnU16;
1657	PFNIEMAIMPLMULDIVU32 pfnU32;
1658	PFNIEMAIMPLMULDIVU64 pfnU64;
1659	} IEMOPMULDIVSIZES;
1660	/** Pointer to a multiplication or division operation function table. */
1661	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
1662
1663
1664	/**
1665	* Function table for a double precision shift operator providing implementation
1666	* based on operand size.
1667	*/
1668	typedef struct IEMOPSHIFTDBLSIZES
1669	{
1670	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
1671	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
1672	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
1673	} IEMOPSHIFTDBLSIZES;
1674	/** Pointer to a double precision shift function table. */
1675	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
1676
1677
1678	/**
1679	* Function table for media instruction taking two full sized media registers,
1680	* optionally the 2nd being a memory reference (only modifying the first op.)
1681	*/
1682	typedef struct IEMOPMEDIAF2
1683	{
1684	PFNIEMAIMPLMEDIAF2U64 pfnU64;
1685	PFNIEMAIMPLMEDIAF2U128 pfnU128;
1686	} IEMOPMEDIAF2;
1687	/** Pointer to a media operation function table for full sized ops. */
1688	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
1689
1690	/**
1691	* Function table for media instruction taking taking one full and one lower
1692	* half media register.
1693	*/
1694	typedef struct IEMOPMEDIAF1L1
1695	{
1696	PFNIEMAIMPLMEDIAF1L1U64 pfnU64;
1697	PFNIEMAIMPLMEDIAF1L1U128 pfnU128;
1698	} IEMOPMEDIAF1L1;
1699	/** Pointer to a media operation function table for lowhalf+lowhalf -> full. */
1700	typedef IEMOPMEDIAF1L1 const *PCIEMOPMEDIAF1L1;
1701
1702	/**
1703	* Function table for media instruction taking taking one full and one high half
1704	* media register.
1705	*/
1706	typedef struct IEMOPMEDIAF1H1
1707	{
1708	PFNIEMAIMPLMEDIAF1H1U64 pfnU64;
1709	PFNIEMAIMPLMEDIAF1H1U128 pfnU128;
1710	} IEMOPMEDIAF1H1;
1711	/** Pointer to a media operation function table for hihalf+hihalf -> full. */
1712	typedef IEMOPMEDIAF1H1 const *PCIEMOPMEDIAF1H1;
1713
1714
1715	/** @} */
1716
1717
1718	/** @name C instruction implementations for anything slightly complicated.
1719	* @{ */
1720
1721	/**
1722	* For typedef'ing or declaring a C instruction implementation function taking
1723	* no extra arguments.
1724	*
1725	* @param a_Name The name of the type.
1726	*/
1727	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
1728	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
1729	/**
1730	* For defining a C instruction implementation function taking no extra
1731	* arguments.
1732	*
1733	* @param a_Name The name of the function
1734	*/
1735	# define IEM_CIMPL_DEF_0(a_Name) \
1736	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
1737	/**
1738	* For calling a C instruction implementation function taking no extra
1739	* arguments.
1740	*
1741	* This special call macro adds default arguments to the call and allow us to
1742	* change these later.
1743	*
1744	* @param a_fn The name of the function.
1745	*/
1746	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
1747
1748	/**
1749	* For typedef'ing or declaring a C instruction implementation function taking
1750	* one extra argument.
1751	*
1752	* @param a_Name The name of the type.
1753	* @param a_Type0 The argument type.
1754	* @param a_Arg0 The argument name.
1755	*/
1756	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
1757	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1758	/**
1759	* For defining a C instruction implementation function taking one extra
1760	* argument.
1761	*
1762	* @param a_Name The name of the function
1763	* @param a_Type0 The argument type.
1764	* @param a_Arg0 The argument name.
1765	*/
1766	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
1767	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1768	/**
1769	* For calling a C instruction implementation function taking one extra
1770	* argument.
1771	*
1772	* This special call macro adds default arguments to the call and allow us to
1773	* change these later.
1774	*
1775	* @param a_fn The name of the function.
1776	* @param a0 The name of the 1st argument.
1777	*/
1778	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
1779
1780	/**
1781	* For typedef'ing or declaring a C instruction implementation function taking
1782	* two extra arguments.
1783	*
1784	* @param a_Name The name of the type.
1785	* @param a_Type0 The type of the 1st argument
1786	* @param a_Arg0 The name of the 1st argument.
1787	* @param a_Type1 The type of the 2nd argument.
1788	* @param a_Arg1 The name of the 2nd argument.
1789	*/
1790	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1791	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1792	/**
1793	* For defining a C instruction implementation function taking two extra
1794	* arguments.
1795	*
1796	* @param a_Name The name of the function.
1797	* @param a_Type0 The type of the 1st argument
1798	* @param a_Arg0 The name of the 1st argument.
1799	* @param a_Type1 The type of the 2nd argument.
1800	* @param a_Arg1 The name of the 2nd argument.
1801	*/
1802	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1803	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1804	/**
1805	* For calling a C instruction implementation function taking two extra
1806	* arguments.
1807	*
1808	* This special call macro adds default arguments to the call and allow us to
1809	* change these later.
1810	*
1811	* @param a_fn The name of the function.
1812	* @param a0 The name of the 1st argument.
1813	* @param a1 The name of the 2nd argument.
1814	*/
1815	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
1816
1817	/**
1818	* For typedef'ing or declaring a C instruction implementation function taking
1819	* three extra arguments.
1820	*
1821	* @param a_Name The name of the type.
1822	* @param a_Type0 The type of the 1st argument
1823	* @param a_Arg0 The name of the 1st argument.
1824	* @param a_Type1 The type of the 2nd argument.
1825	* @param a_Arg1 The name of the 2nd argument.
1826	* @param a_Type2 The type of the 3rd argument.
1827	* @param a_Arg2 The name of the 3rd argument.
1828	*/
1829	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1830	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1831	/**
1832	* For defining a C instruction implementation function taking three extra
1833	* arguments.
1834	*
1835	* @param a_Name The name of the function.
1836	* @param a_Type0 The type of the 1st argument
1837	* @param a_Arg0 The name of the 1st argument.
1838	* @param a_Type1 The type of the 2nd argument.
1839	* @param a_Arg1 The name of the 2nd argument.
1840	* @param a_Type2 The type of the 3rd argument.
1841	* @param a_Arg2 The name of the 3rd argument.
1842	*/
1843	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1844	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1845	/**
1846	* For calling a C instruction implementation function taking three extra
1847	* arguments.
1848	*
1849	* This special call macro adds default arguments to the call and allow us to
1850	* change these later.
1851	*
1852	* @param a_fn The name of the function.
1853	* @param a0 The name of the 1st argument.
1854	* @param a1 The name of the 2nd argument.
1855	* @param a2 The name of the 3rd argument.
1856	*/
1857	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
1858
1859
1860	/**
1861	* For typedef'ing or declaring a C instruction implementation function taking
1862	* four extra arguments.
1863	*
1864	* @param a_Name The name of the type.
1865	* @param a_Type0 The type of the 1st argument
1866	* @param a_Arg0 The name of the 1st argument.
1867	* @param a_Type1 The type of the 2nd argument.
1868	* @param a_Arg1 The name of the 2nd argument.
1869	* @param a_Type2 The type of the 3rd argument.
1870	* @param a_Arg2 The name of the 3rd argument.
1871	* @param a_Type3 The type of the 4th argument.
1872	* @param a_Arg3 The name of the 4th argument.
1873	*/
1874	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1875	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
1876	/**
1877	* For defining a C instruction implementation function taking four extra
1878	* arguments.
1879	*
1880	* @param a_Name The name of the function.
1881	* @param a_Type0 The type of the 1st argument
1882	* @param a_Arg0 The name of the 1st argument.
1883	* @param a_Type1 The type of the 2nd argument.
1884	* @param a_Arg1 The name of the 2nd argument.
1885	* @param a_Type2 The type of the 3rd argument.
1886	* @param a_Arg2 The name of the 3rd argument.
1887	* @param a_Type3 The type of the 4th argument.
1888	* @param a_Arg3 The name of the 4th argument.
1889	*/
1890	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1891	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1892	a_Type2 a_Arg2, a_Type3 a_Arg3))
1893	/**
1894	* For calling a C instruction implementation function taking four extra
1895	* arguments.
1896	*
1897	* This special call macro adds default arguments to the call and allow us to
1898	* change these later.
1899	*
1900	* @param a_fn The name of the function.
1901	* @param a0 The name of the 1st argument.
1902	* @param a1 The name of the 2nd argument.
1903	* @param a2 The name of the 3rd argument.
1904	* @param a3 The name of the 4th argument.
1905	*/
1906	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
1907
1908
1909	/**
1910	* For typedef'ing or declaring a C instruction implementation function taking
1911	* five extra arguments.
1912	*
1913	* @param a_Name The name of the type.
1914	* @param a_Type0 The type of the 1st argument
1915	* @param a_Arg0 The name of the 1st argument.
1916	* @param a_Type1 The type of the 2nd argument.
1917	* @param a_Arg1 The name of the 2nd argument.
1918	* @param a_Type2 The type of the 3rd argument.
1919	* @param a_Arg2 The name of the 3rd argument.
1920	* @param a_Type3 The type of the 4th argument.
1921	* @param a_Arg3 The name of the 4th argument.
1922	* @param a_Type4 The type of the 5th argument.
1923	* @param a_Arg4 The name of the 5th argument.
1924	*/
1925	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1926	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
1927	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1928	a_Type3 a_Arg3, a_Type4 a_Arg4))
1929	/**
1930	* For defining a C instruction implementation function taking five extra
1931	* arguments.
1932	*
1933	* @param a_Name The name of the function.
1934	* @param a_Type0 The type of the 1st argument
1935	* @param a_Arg0 The name of the 1st argument.
1936	* @param a_Type1 The type of the 2nd argument.
1937	* @param a_Arg1 The name of the 2nd argument.
1938	* @param a_Type2 The type of the 3rd argument.
1939	* @param a_Arg2 The name of the 3rd argument.
1940	* @param a_Type3 The type of the 4th argument.
1941	* @param a_Arg3 The name of the 4th argument.
1942	* @param a_Type4 The type of the 5th argument.
1943	* @param a_Arg4 The name of the 5th argument.
1944	*/
1945	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1946	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
1947	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1948	a_Type3 a_Arg3, a_Type4 a_Arg4))
1949	/**
1950	* For calling a C instruction implementation function taking five extra
1951	* arguments.
1952	*
1953	* This special call macro adds default arguments to the call and allow us to
1954	* change these later.
1955	*
1956	* @param a_fn The name of the function.
1957	* @param a0 The name of the 1st argument.
1958	* @param a1 The name of the 2nd argument.
1959	* @param a2 The name of the 3rd argument.
1960	* @param a3 The name of the 4th argument.
1961	* @param a4 The name of the 5th argument.
1962	*/
1963	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
1964
1965	/** @} */
1966
1967
1968	/** @} */
1969
1970	RT_C_DECLS_END
1971
1972	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
1973

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