IEMInternal.h@ 94842

Last change on this file since 94842 was 94842, checked in by vboxsync, 3 years ago
VMM/IEM: Arm build fixes. bugref:9898
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1	/* $Id: IEMInternal.h 94842 2022-05-05 10:38:40Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
19	#define VMM_INCLUDED_SRC_include_IEMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/vmm/cpum.h>
25	#include <VBox/vmm/iem.h>
26	#include <VBox/vmm/pgm.h>
27	#include <VBox/vmm/stam.h>
28	#include <VBox/param.h>
29
30	#include <setjmp.h>
31
32
33	RT_C_DECLS_BEGIN
34
35
36	/** @defgroup grp_iem_int Internals
37	* @ingroup grp_iem
38	* @internal
39	* @{
40	*/
41
42	/** For expanding symbol in slickedit and other products tagging and
43	* crossreferencing IEM symbols. */
44	#ifndef IEM_STATIC
45	# define IEM_STATIC static
46	#endif
47
48	/** @def IEM_WITH_SETJMP
49	* Enables alternative status code handling using setjmps.
50	*
51	* This adds a bit of expense via the setjmp() call since it saves all the
52	* non-volatile registers. However, it eliminates return code checks and allows
53	* for more optimal return value passing (return regs instead of stack buffer).
54	*/
55	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
56	# define IEM_WITH_SETJMP
57	#endif
58
59	#define IEM_IMPLEMENTS_TASKSWITCH
60
61	/** @def IEM_WITH_3DNOW
62	* Includes the 3DNow decoding. */
63	#define IEM_WITH_3DNOW
64
65	/** @def IEM_WITH_THREE_0F_38
66	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
67	#define IEM_WITH_THREE_0F_38
68
69	/** @def IEM_WITH_THREE_0F_3A
70	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
71	#define IEM_WITH_THREE_0F_3A
72
73	/** @def IEM_WITH_VEX
74	* Includes the VEX decoding. */
75	#define IEM_WITH_VEX
76
77	/** @def IEM_CFG_TARGET_CPU
78	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
79	*
80	* By default we allow this to be configured by the user via the
81	* CPUM/GuestCpuName config string, but this comes at a slight cost during
82	* decoding. So, for applications of this code where there is no need to
83	* be dynamic wrt target CPU, just modify this define.
84	*/
85	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
86	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
87	#endif
88
89	//#define IEM_WITH_CODE_TLB // - work in progress
90	//#define IEM_WITH_DATA_TLB // - work in progress
91
92
93	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
94	* Use unaligned accesses instead of elaborate byte assembly. */
95	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
96	# define IEM_USE_UNALIGNED_DATA_ACCESS
97	#endif
98
99	//#define IEM_LOG_MEMORY_WRITES
100
101	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
102	/** Instruction statistics. */
103	typedef struct IEMINSTRSTATS
104	{
105	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
106	# include "IEMInstructionStatisticsTmpl.h"
107	# undef IEM_DO_INSTR_STAT
108	} IEMINSTRSTATS;
109	#else
110	struct IEMINSTRSTATS;
111	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
112	#endif
113	/** Pointer to IEM instruction statistics. */
114	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
115
116
117	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::idxTargetCpuEflFlavour
118	* @{ */
119	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
120	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
121	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
122	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
123	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
124	/** Selects the right variant from a_aArray.
125	* pVCpu is implicit in the caller context. */
126	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
127	(a_aArray[pVCpu->iem.s.idxTargetCpuEflFlavour & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
128	/** @} */
129
130
131	/**
132	* Extended operand mode that includes a representation of 8-bit.
133	*
134	* This is used for packing down modes when invoking some C instruction
135	* implementations.
136	*/
137	typedef enum IEMMODEX
138	{
139	IEMMODEX_16BIT = IEMMODE_16BIT,
140	IEMMODEX_32BIT = IEMMODE_32BIT,
141	IEMMODEX_64BIT = IEMMODE_64BIT,
142	IEMMODEX_8BIT
143	} IEMMODEX;
144	AssertCompileSize(IEMMODEX, 4);
145
146
147	/**
148	* Branch types.
149	*/
150	typedef enum IEMBRANCH
151	{
152	IEMBRANCH_JUMP = 1,
153	IEMBRANCH_CALL,
154	IEMBRANCH_TRAP,
155	IEMBRANCH_SOFTWARE_INT,
156	IEMBRANCH_HARDWARE_INT
157	} IEMBRANCH;
158	AssertCompileSize(IEMBRANCH, 4);
159
160
161	/**
162	* INT instruction types.
163	*/
164	typedef enum IEMINT
165	{
166	/** INT n instruction (opcode 0xcd imm). */
167	IEMINT_INTN = 0,
168	/** Single byte INT3 instruction (opcode 0xcc). */
169	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
170	/** Single byte INTO instruction (opcode 0xce). */
171	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
172	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
173	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
174	} IEMINT;
175	AssertCompileSize(IEMINT, 4);
176
177
178	/**
179	* A FPU result.
180	*/
181	typedef struct IEMFPURESULT
182	{
183	/** The output value. */
184	RTFLOAT80U r80Result;
185	/** The output status. */
186	uint16_t FSW;
187	} IEMFPURESULT;
188	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
189	/** Pointer to a FPU result. */
190	typedef IEMFPURESULT *PIEMFPURESULT;
191	/** Pointer to a const FPU result. */
192	typedef IEMFPURESULT const *PCIEMFPURESULT;
193
194
195	/**
196	* A FPU result consisting of two output values and FSW.
197	*/
198	typedef struct IEMFPURESULTTWO
199	{
200	/** The first output value. */
201	RTFLOAT80U r80Result1;
202	/** The output status. */
203	uint16_t FSW;
204	/** The second output value. */
205	RTFLOAT80U r80Result2;
206	} IEMFPURESULTTWO;
207	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
208	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
209	/** Pointer to a FPU result consisting of two output values and FSW. */
210	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
211	/** Pointer to a const FPU result consisting of two output values and FSW. */
212	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
213
214
215	/**
216	* IEM TLB entry.
217	*
218	* Lookup assembly:
219	* @code{.asm}
220	; Calculate tag.
221	mov rax, [VA]
222	shl rax, 16
223	shr rax, 16 + X86_PAGE_SHIFT
224	or rax, [uTlbRevision]
225
226	; Do indexing.
227	movzx ecx, al
228	lea rcx, [pTlbEntries + rcx]
229
230	; Check tag.
231	cmp [rcx + IEMTLBENTRY.uTag], rax
232	jne .TlbMiss
233
234	; Check access.
235	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
236	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
237	cmp rax, [uTlbPhysRev]
238	jne .TlbMiss
239
240	; Calc address and we're done.
241	mov eax, X86_PAGE_OFFSET_MASK
242	and eax, [VA]
243	or rax, [rcx + IEMTLBENTRY.pMappingR3]
244	%ifdef VBOX_WITH_STATISTICS
245	inc qword [cTlbHits]
246	%endif
247	jmp .Done
248
249	.TlbMiss:
250	mov r8d, ACCESS_FLAGS
251	mov rdx, [VA]
252	mov rcx, [pVCpu]
253	call iemTlbTypeMiss
254	.Done:
255
256	@endcode
257	*
258	*/
259	typedef struct IEMTLBENTRY
260	{
261	/** The TLB entry tag.
262	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
263	* is ASSUMING a virtual address width of 48 bits.
264	*
265	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
266	*
267	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
268	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
269	* revision wraps around though, the tags needs to be zeroed.
270	*
271	* @note Try use SHRD instruction? After seeing
272	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
273	*
274	* @todo This will need to be reorganized for 57-bit wide virtual address and
275	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
276	* have to move the TLB entry versioning entirely to the
277	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
278	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
279	* consumed by PCID and ASID (12 + 6 = 18).
280	*/
281	uint64_t uTag;
282	/** Access flags and physical TLB revision.
283	*
284	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
285	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
286	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
287	* - Bit 3 - pgm phys/virt - not directly writable.
288	* - Bit 4 - pgm phys page - not directly readable.
289	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
290	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
291	* - Bit 7 - tlb entry - pMappingR3 member not valid.
292	* - Bits 63 thru 8 are used for the physical TLB revision number.
293	*
294	* We're using complemented bit meanings here because it makes it easy to check
295	* whether special action is required. For instance a user mode write access
296	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
297	* non-zero result would mean special handling needed because either it wasn't
298	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
299	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
300	* need to check any PTE flag.
301	*/
302	uint64_t fFlagsAndPhysRev;
303	/** The guest physical page address. */
304	uint64_t GCPhys;
305	/** Pointer to the ring-3 mapping. */
306	R3PTRTYPE(uint8_t *) pbMappingR3;
307	#if HC_ARCH_BITS == 32
308	uint32_t u32Padding1;
309	#endif
310	} IEMTLBENTRY;
311	AssertCompileSize(IEMTLBENTRY, 32);
312	/** Pointer to an IEM TLB entry. */
313	typedef IEMTLBENTRY *PIEMTLBENTRY;
314
315	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
316	* @{ */
317	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
318	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
319	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
320	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
321	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
322	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
323	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
324	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
325	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
326	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
327	/** @} */
328
329
330	/**
331	* An IEM TLB.
332	*
333	* We've got two of these, one for data and one for instructions.
334	*/
335	typedef struct IEMTLB
336	{
337	/** The TLB entries.
338	* We've choosen 256 because that way we can obtain the result directly from a
339	* 8-bit register without an additional AND instruction. */
340	IEMTLBENTRY aEntries[256];
341	/** The TLB revision.
342	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
343	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
344	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
345	* (The revision zero indicates an invalid TLB entry.)
346	*
347	* The initial value is choosen to cause an early wraparound. */
348	uint64_t uTlbRevision;
349	/** The TLB physical address revision - shadow of PGM variable.
350	*
351	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
352	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
353	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
354	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
355	*
356	* The initial value is choosen to cause an early wraparound. */
357	uint64_t volatile uTlbPhysRev;
358
359	/* Statistics: */
360
361	/** TLB hits (VBOX_WITH_STATISTICS only). */
362	uint64_t cTlbHits;
363	/** TLB misses. */
364	uint32_t cTlbMisses;
365	/** Slow read path. */
366	uint32_t cTlbSlowReadPath;
367	#if 0
368	/** TLB misses because of tag mismatch. */
369	uint32_t cTlbMissesTag;
370	/** TLB misses because of virtual access violation. */
371	uint32_t cTlbMissesVirtAccess;
372	/** TLB misses because of dirty bit. */
373	uint32_t cTlbMissesDirty;
374	/** TLB misses because of MMIO */
375	uint32_t cTlbMissesMmio;
376	/** TLB misses because of write access handlers. */
377	uint32_t cTlbMissesWriteHandler;
378	/** TLB misses because no r3(/r0) mapping. */
379	uint32_t cTlbMissesMapping;
380	#endif
381	/** Alignment padding. */
382	uint32_t au32Padding[3+5];
383	} IEMTLB;
384	AssertCompileSizeAlignment(IEMTLB, 64);
385	/** IEMTLB::uTlbRevision increment. */
386	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
387	/** IEMTLB::uTlbRevision mask. */
388	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
389	/** IEMTLB::uTlbPhysRev increment.
390	* @sa IEMTLBE_F_PHYS_REV */
391	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
392
393
394	/**
395	* The per-CPU IEM state.
396	*/
397	typedef struct IEMCPU
398	{
399	/** Info status code that needs to be propagated to the IEM caller.
400	* This cannot be passed internally, as it would complicate all success
401	* checks within the interpreter making the code larger and almost impossible
402	* to get right. Instead, we'll store status codes to pass on here. Each
403	* source of these codes will perform appropriate sanity checks. */
404	int32_t rcPassUp; /* 0x00 */
405
406	/** The current CPU execution mode (CS). */
407	IEMMODE enmCpuMode; /* 0x04 */
408	/** The CPL. */
409	uint8_t uCpl; /* 0x05 */
410
411	/** Whether to bypass access handlers or not. */
412	bool fBypassHandlers; /* 0x06 */
413	/** Whether to disregard the lock prefix (implied or not). */
414	bool fDisregardLock; /* 0x07 */
415
416	/** @name Decoder state.
417	* @{ */
418	#ifdef IEM_WITH_CODE_TLB
419	/** The offset of the next instruction byte. */
420	uint32_t offInstrNextByte; /* 0x08 */
421	/** The number of bytes available at pbInstrBuf for the current instruction.
422	* This takes the max opcode length into account so that doesn't need to be
423	* checked separately. */
424	uint32_t cbInstrBuf; /* 0x0c */
425	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
426	* This can be NULL if the page isn't mappable for some reason, in which
427	* case we'll do fallback stuff.
428	*
429	* If we're executing an instruction from a user specified buffer,
430	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
431	* aligned pointer but pointer to the user data.
432	*
433	* For instructions crossing pages, this will start on the first page and be
434	* advanced to the next page by the time we've decoded the instruction. This
435	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
436	*/
437	uint8_t const pbInstrBuf; / 0x10 */
438	# if ARCH_BITS == 32
439	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
440	# endif
441	/** The program counter corresponding to pbInstrBuf.
442	* This is set to a non-canonical address when we need to invalidate it. */
443	uint64_t uInstrBufPc; /* 0x18 */
444	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
445	* This takes the CS segment limit into account. */
446	uint16_t cbInstrBufTotal; /* 0x20 */
447	/** Offset into pbInstrBuf of the first byte of the current instruction.
448	* Can be negative to efficiently handle cross page instructions. */
449	int16_t offCurInstrStart; /* 0x22 */
450
451	/** The prefix mask (IEM_OP_PRF_XXX). */
452	uint32_t fPrefixes; /* 0x24 */
453	/** The extra REX ModR/M register field bit (REX.R << 3). */
454	uint8_t uRexReg; /* 0x28 */
455	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
456	* (REX.B << 3). */
457	uint8_t uRexB; /* 0x29 */
458	/** The extra REX SIB index field bit (REX.X << 3). */
459	uint8_t uRexIndex; /* 0x2a */
460
461	/** The effective segment register (X86_SREG_XXX). */
462	uint8_t iEffSeg; /* 0x2b */
463
464	/** The offset of the ModR/M byte relative to the start of the instruction. */
465	uint8_t offModRm; /* 0x2c */
466	#else
467	/** The size of what has currently been fetched into abOpcode. */
468	uint8_t cbOpcode; /* 0x08 */
469	/** The current offset into abOpcode. */
470	uint8_t offOpcode; /* 0x09 */
471	/** The offset of the ModR/M byte relative to the start of the instruction. */
472	uint8_t offModRm; /* 0x0a */
473
474	/** The effective segment register (X86_SREG_XXX). */
475	uint8_t iEffSeg; /* 0x0b */
476
477	/** The prefix mask (IEM_OP_PRF_XXX). */
478	uint32_t fPrefixes; /* 0x0c */
479	/** The extra REX ModR/M register field bit (REX.R << 3). */
480	uint8_t uRexReg; /* 0x10 */
481	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
482	* (REX.B << 3). */
483	uint8_t uRexB; /* 0x11 */
484	/** The extra REX SIB index field bit (REX.X << 3). */
485	uint8_t uRexIndex; /* 0x12 */
486
487	#endif
488
489	/** The effective operand mode. */
490	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
491	/** The default addressing mode. */
492	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
493	/** The effective addressing mode. */
494	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
495	/** The default operand mode. */
496	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
497
498	/** Prefix index (VEX.pp) for two byte and three byte tables. */
499	uint8_t idxPrefix; /* 0x31, 0x17 */
500	/** 3rd VEX/EVEX/XOP register.
501	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
502	uint8_t uVex3rdReg; /* 0x32, 0x18 */
503	/** The VEX/EVEX/XOP length field. */
504	uint8_t uVexLength; /* 0x33, 0x19 */
505	/** Additional EVEX stuff. */
506	uint8_t fEvexStuff; /* 0x34, 0x1a */
507
508	/** Explicit alignment padding. */
509	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
510	/** The FPU opcode (FOP). */
511	uint16_t uFpuOpcode; /* 0x36, 0x1c */
512	#ifndef IEM_WITH_CODE_TLB
513	/** Explicit alignment padding. */
514	uint8_t abAlignment2b[2]; /* 0x1e */
515	#endif
516
517	/** The opcode bytes. */
518	uint8_t abOpcode[15]; /* 0x48, 0x20 */
519	/** Explicit alignment padding. */
520	#ifdef IEM_WITH_CODE_TLB
521	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
522	#else
523	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
524	#endif
525	/** @} */
526
527
528	/** The flags of the current exception / interrupt. */
529	uint32_t fCurXcpt; /* 0x48, 0x48 */
530	/** The current exception / interrupt. */
531	uint8_t uCurXcpt;
532	/** Exception / interrupt recursion depth. */
533	int8_t cXcptRecursions;
534
535	/** The number of active guest memory mappings. */
536	uint8_t cActiveMappings;
537	/** The next unused mapping index. */
538	uint8_t iNextMapping;
539	/** Records for tracking guest memory mappings. */
540	struct
541	{
542	/** The address of the mapped bytes. */
543	void *pv;
544	/** The access flags (IEM_ACCESS_XXX).
545	* IEM_ACCESS_INVALID if the entry is unused. */
546	uint32_t fAccess;
547	#if HC_ARCH_BITS == 64
548	uint32_t u32Alignment4; /*< Alignment padding. /
549	#endif
550	} aMemMappings[3];
551
552	/** Locking records for the mapped memory. */
553	union
554	{
555	PGMPAGEMAPLOCK Lock;
556	uint64_t au64Padding[2];
557	} aMemMappingLocks[3];
558
559	/** Bounce buffer info.
560	* This runs in parallel to aMemMappings. */
561	struct
562	{
563	/** The physical address of the first byte. */
564	RTGCPHYS GCPhysFirst;
565	/** The physical address of the second page. */
566	RTGCPHYS GCPhysSecond;
567	/** The number of bytes in the first page. */
568	uint16_t cbFirst;
569	/** The number of bytes in the second page. */
570	uint16_t cbSecond;
571	/** Whether it's unassigned memory. */
572	bool fUnassigned;
573	/** Explicit alignment padding. */
574	bool afAlignment5[3];
575	} aMemBbMappings[3];
576
577	/** Bounce buffer storage.
578	* This runs in parallel to aMemMappings and aMemBbMappings. */
579	struct
580	{
581	uint8_t ab[512];
582	} aBounceBuffers[3];
583
584
585	/** Pointer set jump buffer - ring-3 context. */
586	R3PTRTYPE(jmp_buf *) pJmpBufR3;
587	/** Pointer set jump buffer - ring-0 context. */
588	R0PTRTYPE(jmp_buf *) pJmpBufR0;
589
590	/** @todo Should move this near @a fCurXcpt later. */
591	/** The CR2 for the current exception / interrupt. */
592	uint64_t uCurXcptCr2;
593	/** The error code for the current exception / interrupt. */
594	uint32_t uCurXcptErr;
595
596	/** @name Statistics
597	* @{ */
598	/** The number of instructions we've executed. */
599	uint32_t cInstructions;
600	/** The number of potential exits. */
601	uint32_t cPotentialExits;
602	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
603	* This may contain uncommitted writes. */
604	uint32_t cbWritten;
605	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
606	uint32_t cRetInstrNotImplemented;
607	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
608	uint32_t cRetAspectNotImplemented;
609	/** Counts informational statuses returned (other than VINF_SUCCESS). */
610	uint32_t cRetInfStatuses;
611	/** Counts other error statuses returned. */
612	uint32_t cRetErrStatuses;
613	/** Number of times rcPassUp has been used. */
614	uint32_t cRetPassUpStatus;
615	/** Number of times RZ left with instruction commit pending for ring-3. */
616	uint32_t cPendingCommit;
617	/** Number of long jumps. */
618	uint32_t cLongJumps;
619	/** @} */
620
621	/** @name Target CPU information.
622	* @{ */
623	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
624	/** The target CPU. */
625	uint8_t uTargetCpu;
626	#else
627	uint8_t bTargetCpuPadding;
628	#endif
629	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
630	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values. This is for instance used for the
631	* BSF & BSR instructions where AMD and Intel CPUs produce different EFLAGS. */
632	uint8_t idxTargetCpuEflFlavour;
633
634	/** The CPU vendor. */
635	CPUMCPUVENDOR enmCpuVendor;
636	/** @} */
637
638	/** @name Host CPU information.
639	* @{ */
640	/** The CPU vendor. */
641	CPUMCPUVENDOR enmHostCpuVendor;
642	/** @} */
643
644	/** Counts RDMSR \#GP(0) LogRel(). */
645	uint8_t cLogRelRdMsr;
646	/** Counts WRMSR \#GP(0) LogRel(). */
647	uint8_t cLogRelWrMsr;
648	/** Alignment padding. */
649	uint8_t abAlignment8[50];
650
651	/** Data TLB.
652	* @remarks Must be 64-byte aligned. */
653	IEMTLB DataTlb;
654	/** Instruction TLB.
655	* @remarks Must be 64-byte aligned. */
656	IEMTLB CodeTlb;
657
658	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
659	/** Instruction statistics for ring-0/raw-mode. */
660	IEMINSTRSTATS StatsRZ;
661	/** Instruction statistics for ring-3. */
662	IEMINSTRSTATS StatsR3;
663	#endif
664	} IEMCPU;
665	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
666	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
667	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
668	/** Pointer to the per-CPU IEM state. */
669	typedef IEMCPU *PIEMCPU;
670	/** Pointer to the const per-CPU IEM state. */
671	typedef IEMCPU const *PCIEMCPU;
672
673
674	/** @def IEM_GET_CTX
675	* Gets the guest CPU context for the calling EMT.
676	* @returns PCPUMCTX
677	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
678	*/
679	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
680
681	/** @def IEM_CTX_ASSERT
682	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
683	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
684	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
685	*/
686	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
687	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
688	(a_fExtrnMbz)))
689
690	/** @def IEM_CTX_IMPORT_RET
691	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
692	*
693	* Will call the keep to import the bits as needed.
694	*
695	* Returns on import failure.
696	*
697	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
698	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
699	*/
700	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
701	do { \
702	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
703	{ /* likely */ } \
704	else \
705	{ \
706	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
707	AssertRCReturn(rcCtxImport, rcCtxImport); \
708	} \
709	} while (0)
710
711	/** @def IEM_CTX_IMPORT_NORET
712	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
713	*
714	* Will call the keep to import the bits as needed.
715	*
716	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
717	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
718	*/
719	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
720	do { \
721	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
722	{ /* likely */ } \
723	else \
724	{ \
725	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
726	AssertLogRelRC(rcCtxImport); \
727	} \
728	} while (0)
729
730	/** @def IEM_CTX_IMPORT_JMP
731	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
732	*
733	* Will call the keep to import the bits as needed.
734	*
735	* Jumps on import failure.
736	*
737	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
738	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
739	*/
740	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
741	do { \
742	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
743	{ /* likely */ } \
744	else \
745	{ \
746	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
747	AssertRCStmt(rcCtxImport, longjmp(*pVCpu->iem.s.CTX_SUFF(pJmpBuf), rcCtxImport)); \
748	} \
749	} while (0)
750
751
752
753	/** @def IEM_GET_TARGET_CPU
754	* Gets the current IEMTARGETCPU value.
755	* @returns IEMTARGETCPU value.
756	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
757	*/
758	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
759	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
760	#else
761	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
762	#endif
763
764	/** @def IEM_GET_INSTR_LEN
765	* Gets the instruction length. */
766	#ifdef IEM_WITH_CODE_TLB
767	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
768	#else
769	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
770	#endif
771
772
773	/**
774	* Shared per-VM IEM data.
775	*/
776	typedef struct IEM
777	{
778	/** The VMX APIC-access page handler type. */
779	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
780	} IEM;
781
782
783
784	/** @name IEM_ACCESS_XXX - Access details.
785	* @{ */
786	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
787	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
788	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
789	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
790	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
791	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
792	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
793	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
794	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
795	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
796	/** The writes are partial, so if initialize the bounce buffer with the
797	* orignal RAM content. */
798	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
799	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
800	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
801	/** Bounce buffer with ring-3 write pending, first page. */
802	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
803	/** Bounce buffer with ring-3 write pending, second page. */
804	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
805	/** Not locked, accessed via the TLB. */
806	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
807	/** Valid bit mask. */
808	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
809	/** Read+write data alias. */
810	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
811	/** Write data alias. */
812	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
813	/** Read data alias. */
814	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
815	/** Instruction fetch alias. */
816	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
817	/** Stack write alias. */
818	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
819	/** Stack read alias. */
820	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
821	/** Stack read+write alias. */
822	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
823	/** Read system table alias. */
824	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
825	/** Read+write system table alias. */
826	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
827	/** @} */
828
829	/** @name Prefix constants (IEMCPU::fPrefixes)
830	* @{ */
831	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
832	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
833	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
834	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
835	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
836	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
837	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
838
839	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
840	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
841	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
842
843	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
844	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
845	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
846
847	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
848	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
849	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
850	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
851	/** Mask with all the REX prefix flags.
852	* This is generally for use when needing to undo the REX prefixes when they
853	* are followed legacy prefixes and therefore does not immediately preceed
854	* the first opcode byte.
855	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
856	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
857
858	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
859	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
860	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
861	/** @} */
862
863	/** @name IEMOPFORM_XXX - Opcode forms
864	* @note These are ORed together with IEMOPHINT_XXX.
865	* @{ */
866	/** ModR/M: reg, r/m */
867	#define IEMOPFORM_RM 0
868	/** ModR/M: reg, r/m (register) */
869	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
870	/** ModR/M: reg, r/m (memory) */
871	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
872	/** ModR/M: r/m, reg */
873	#define IEMOPFORM_MR 1
874	/** ModR/M: r/m (register), reg */
875	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
876	/** ModR/M: r/m (memory), reg */
877	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
878	/** ModR/M: r/m only */
879	#define IEMOPFORM_M 2
880	/** ModR/M: r/m only (register). */
881	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
882	/** ModR/M: r/m only (memory). */
883	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
884	/** ModR/M: reg only */
885	#define IEMOPFORM_R 3
886
887	/** VEX+ModR/M: reg, r/m */
888	#define IEMOPFORM_VEX_RM 4
889	/** VEX+ModR/M: reg, r/m (register) */
890	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
891	/** VEX+ModR/M: reg, r/m (memory) */
892	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
893	/** VEX+ModR/M: r/m, reg */
894	#define IEMOPFORM_VEX_MR 5
895	/** VEX+ModR/M: r/m (register), reg */
896	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
897	/** VEX+ModR/M: r/m (memory), reg */
898	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
899	/** VEX+ModR/M: r/m only */
900	#define IEMOPFORM_VEX_M 6
901	/** VEX+ModR/M: r/m only (register). */
902	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
903	/** VEX+ModR/M: r/m only (memory). */
904	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
905	/** VEX+ModR/M: reg only */
906	#define IEMOPFORM_VEX_R 7
907	/** VEX+ModR/M: reg, vvvv, r/m */
908	#define IEMOPFORM_VEX_RVM 8
909	/** VEX+ModR/M: reg, vvvv, r/m (register). */
910	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
911	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
912	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
913	/** VEX+ModR/M: r/m, vvvv, reg */
914	#define IEMOPFORM_VEX_MVR 9
915	/** VEX+ModR/M: r/m, vvvv, reg (register) */
916	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
917	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
918	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
919
920	/** Fixed register instruction, no R/M. */
921	#define IEMOPFORM_FIXED 16
922
923	/** The r/m is a register. */
924	#define IEMOPFORM_MOD3 RT_BIT_32(8)
925	/** The r/m is a memory access. */
926	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
927	/** @} */
928
929	/** @name IEMOPHINT_XXX - Additional Opcode Hints
930	* @note These are ORed together with IEMOPFORM_XXX.
931	* @{ */
932	/** Ignores the operand size prefix (66h). */
933	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
934	/** Ignores REX.W (aka WIG). */
935	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
936	/** Both the operand size prefixes (66h + REX.W) are ignored. */
937	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
938	/** Allowed with the lock prefix. */
939	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
940	/** The VEX.L value is ignored (aka LIG). */
941	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
942	/** The VEX.L value must be zero (i.e. 128-bit width only). */
943	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
944
945	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
946	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
947	/** @} */
948
949	/**
950	* Possible hardware task switch sources.
951	*/
952	typedef enum IEMTASKSWITCH
953	{
954	/** Task switch caused by an interrupt/exception. */
955	IEMTASKSWITCH_INT_XCPT = 1,
956	/** Task switch caused by a far CALL. */
957	IEMTASKSWITCH_CALL,
958	/** Task switch caused by a far JMP. */
959	IEMTASKSWITCH_JUMP,
960	/** Task switch caused by an IRET. */
961	IEMTASKSWITCH_IRET
962	} IEMTASKSWITCH;
963	AssertCompileSize(IEMTASKSWITCH, 4);
964
965	/**
966	* Possible CrX load (write) sources.
967	*/
968	typedef enum IEMACCESSCRX
969	{
970	/** CrX access caused by 'mov crX' instruction. */
971	IEMACCESSCRX_MOV_CRX,
972	/** CrX (CR0) write caused by 'lmsw' instruction. */
973	IEMACCESSCRX_LMSW,
974	/** CrX (CR0) write caused by 'clts' instruction. */
975	IEMACCESSCRX_CLTS,
976	/** CrX (CR0) read caused by 'smsw' instruction. */
977	IEMACCESSCRX_SMSW
978	} IEMACCESSCRX;
979
980	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
981	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
982	*
983	* These flags provide further context to SLAT page-walk failures that could not be
984	* determined by PGM (e.g, PGM is not privy to memory access permissions).
985	*
986	* @{
987	*/
988	/** Translating a nested-guest linear address failed accessing a nested-guest
989	* physical address. */
990	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
991	/** Translating a nested-guest linear address failed accessing a
992	* paging-structure entry or updating accessed/dirty bits. */
993	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
994	/** @} */
995
996	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
997	# ifndef IN_RING3
998	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
999	# endif
1000	#endif
1001
1002	/**
1003	* Indicates to the verifier that the given flag set is undefined.
1004	*
1005	* Can be invoked again to add more flags.
1006	*
1007	* This is a NOOP if the verifier isn't compiled in.
1008	*
1009	* @note We're temporarily keeping this until code is converted to new
1010	* disassembler style opcode handling.
1011	*/
1012	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1013
1014
1015	/** @def IEM_DECL_IMPL_TYPE
1016	* For typedef'ing an instruction implementation function.
1017	*
1018	* @param a_RetType The return type.
1019	* @param a_Name The name of the type.
1020	* @param a_ArgList The argument list enclosed in parentheses.
1021	*/
1022
1023	/** @def IEM_DECL_IMPL_DEF
1024	* For defining an instruction implementation function.
1025	*
1026	* @param a_RetType The return type.
1027	* @param a_Name The name of the type.
1028	* @param a_ArgList The argument list enclosed in parentheses.
1029	*/
1030
1031	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1032	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1033	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1034	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1035	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1036	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1037	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1038
1039	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1040	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1041	a_RetType (__fastcall a_Name) a_ArgList
1042	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1043	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1044	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1045	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1046
1047	#elif __cplusplus >= 201700 /* P0012R1 support */
1048	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1049	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1050	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1051	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1052	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1053	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1054
1055	#else
1056	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1057	a_RetType (VBOXCALL a_Name) a_ArgList
1058	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1059	a_RetType VBOXCALL a_Name a_ArgList
1060	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1061	a_RetType VBOXCALL a_Name a_ArgList
1062
1063	#endif
1064
1065	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1066	RT_C_DECLS_BEGIN
1067	extern uint8_t const g_afParity[256];
1068	RT_C_DECLS_END
1069
1070
1071	/** @name Arithmetic assignment operations on bytes (binary).
1072	* @{ */
1073	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1074	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1075	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1076	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1077	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1078	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1079	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1080	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1081	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1082	/** @} */
1083
1084	/** @name Arithmetic assignment operations on words (binary).
1085	* @{ */
1086	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1087	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1088	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1089	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1090	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1091	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1092	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1093	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1094	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1095	/** @} */
1096
1097	/** @name Arithmetic assignment operations on double words (binary).
1098	* @{ */
1099	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1100	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1101	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1102	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1103	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1104	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1105	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1106	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1107	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1108	/** @} */
1109
1110	/** @name Arithmetic assignment operations on quad words (binary).
1111	* @{ */
1112	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1113	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1114	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1115	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1116	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1117	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1118	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1119	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1120	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1121	/** @} */
1122
1123	/** @name Compare operations (thrown in with the binary ops).
1124	* @{ */
1125	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1126	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1127	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1128	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1129	/** @} */
1130
1131	/** @name Test operations (thrown in with the binary ops).
1132	* @{ */
1133	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1134	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1135	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1136	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1137	/** @} */
1138
1139	/** @name Bit operations operations (thrown in with the binary ops).
1140	* @{ */
1141	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1142	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1143	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1144	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1145	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1146	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1147	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1148	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1149	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1150	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1151	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1152	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1153	/** @} */
1154
1155	/** @name Exchange memory with register operations.
1156	* @{ */
1157	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1158	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1159	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1160	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1161	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1162	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1163	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1164	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1165	/** @} */
1166
1167	/** @name Exchange and add operations.
1168	* @{ */
1169	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1170	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1171	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1172	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1173	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1174	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1175	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1176	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1177	/** @} */
1178
1179	/** @name Compare and exchange.
1180	* @{ */
1181	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1182	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1183	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1184	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1185	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1186	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1187	#if ARCH_BITS == 32
1188	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1189	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1190	#else
1191	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1192	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1193	#endif
1194	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1195	uint32_t *pEFlags));
1196	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1197	uint32_t *pEFlags));
1198	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1199	uint32_t *pEFlags));
1200	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1201	uint32_t *pEFlags));
1202	#ifndef RT_ARCH_ARM64
1203	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1204	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1205	#endif
1206	/** @} */
1207
1208	/** @name Memory ordering
1209	* @{ */
1210	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1211	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1212	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1213	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1214	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1215	#ifndef RT_ARCH_ARM64
1216	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1217	#endif
1218	/** @} */
1219
1220	/** @name Double precision shifts
1221	* @{ */
1222	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1223	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1224	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1225	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1226	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1227	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1228	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1229	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1230	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1231	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1232	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1233	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1234	/** @} */
1235
1236
1237	/** @name Bit search operations (thrown in with the binary ops).
1238	* @{ */
1239	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1240	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1241	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1242	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1243	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1244	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1245	/** @} */
1246
1247	/** @name Signed multiplication operations (thrown in with the binary ops).
1248	* @{ */
1249	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1250	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1251	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1252	/** @} */
1253
1254	/** @name Arithmetic assignment operations on bytes (unary).
1255	* @{ */
1256	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1257	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1258	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1259	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1260	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1261	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1262	/** @} */
1263
1264	/** @name Arithmetic assignment operations on words (unary).
1265	* @{ */
1266	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1267	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1268	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1269	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1270	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1271	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1272	/** @} */
1273
1274	/** @name Arithmetic assignment operations on double words (unary).
1275	* @{ */
1276	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1277	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1278	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1279	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1280	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1281	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1282	/** @} */
1283
1284	/** @name Arithmetic assignment operations on quad words (unary).
1285	* @{ */
1286	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1287	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1288	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1289	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1290	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1291	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1292	/** @} */
1293
1294
1295	/** @name Shift operations on bytes (Group 2).
1296	* @{ */
1297	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1298	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1299	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1300	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1301	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1302	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1303	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1304	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1305	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1306	/** @} */
1307
1308	/** @name Shift operations on words (Group 2).
1309	* @{ */
1310	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1311	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1312	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1313	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1314	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1315	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1316	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1317	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1318	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1319	/** @} */
1320
1321	/** @name Shift operations on double words (Group 2).
1322	* @{ */
1323	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1324	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1325	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1326	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1327	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1328	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1329	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1330	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1331	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1332	/** @} */
1333
1334	/** @name Shift operations on words (Group 2).
1335	* @{ */
1336	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1337	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1338	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1339	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1340	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1341	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1342	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1343	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1344	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1345	/** @} */
1346
1347	/** @name Multiplication and division operations.
1348	* @{ */
1349	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1350	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1351	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1352	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1353	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1354	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1355
1356	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1357	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1358	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1359	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1360	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1361	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1362
1363	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1364	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1365	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1366	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1367	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1368	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1369
1370	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1371	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1372	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1373	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1374	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1375	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1376	/** @} */
1377
1378	/** @name Byte Swap.
1379	* @{ */
1380	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1381	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1382	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1383	/** @} */
1384
1385	/** @name Misc.
1386	* @{ */
1387	FNIEMAIMPLBINU16 iemAImpl_arpl;
1388	/** @} */
1389
1390
1391	/** @name FPU operations taking a 32-bit float argument
1392	* @{ */
1393	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1394	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1395	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1396
1397	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1398	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1399	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1400
1401	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1402	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1403	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1404	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1405	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1406	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1407	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1408
1409	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1410	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1411	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1412	/** @} */
1413
1414	/** @name FPU operations taking a 64-bit float argument
1415	* @{ */
1416	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1417	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1418	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
1419
1420	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1421	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1422	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1423
1424	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
1425	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1426	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1427	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1428	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1429	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1430	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1431
1432	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1433	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1434	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1435	/** @} */
1436
1437	/** @name FPU operations taking a 80-bit float argument
1438	* @{ */
1439	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1440	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1441	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1442	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1443	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1444	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1445	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1446	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1447	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1448	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1449	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1450	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1451
1452	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
1453	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
1454	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
1455
1456	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1457	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1458	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1459	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1460	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1461
1462	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1463	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1464	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1465	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1466	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1467
1468	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1469	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1470	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1471	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1472	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
1473	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1474	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1475	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
1476	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
1477
1478	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1479	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1480	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1481	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1482
1483	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1484	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1485	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1486	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1487	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1488	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1489	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1490	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1491	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1492
1493	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1494	PCRTFLOAT80U pr80Val));
1495	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1496	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
1497	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1498	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
1499
1500	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1501	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1502	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1503
1504	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
1505	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1506	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
1507
1508	/** @} */
1509
1510	/** @name FPU operations taking a 16-bit signed integer argument
1511	* @{ */
1512	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1513	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1514	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1515	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1516	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
1517	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
1518
1519	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1520	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1521	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1522	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1523	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1524	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1525
1526	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1527	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1528	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
1529	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
1530
1531	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1532	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
1533	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
1534	/** @} */
1535
1536	/** @name FPU operations taking a 32-bit signed integer argument
1537	* @{ */
1538	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1539	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1540	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1541	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1542	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
1543	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
1544
1545	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1546	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1547	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1548	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1549	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1550	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1551
1552	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1553	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1554	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
1555	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
1556
1557	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1558	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
1559	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
1560	/** @} */
1561
1562	/** @name FPU operations taking a 64-bit signed integer argument
1563	* @{ */
1564	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1565	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
1566	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
1567
1568	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1569	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
1570	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
1571	/** @} */
1572
1573
1574	/** Temporary type representing a 256-bit vector register. */
1575	typedef struct { uint64_t au64[4]; } IEMVMM256;
1576	/** Temporary type pointing to a 256-bit vector register. */
1577	typedef IEMVMM256 *PIEMVMM256;
1578	/** Temporary type pointing to a const 256-bit vector register. */
1579	typedef IEMVMM256 *PCIEMVMM256;
1580
1581
1582	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1583	* @{ */
1584	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1585	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1586	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1587	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1588	FNIEMAIMPLMEDIAF2U64 iemAImpl_pxor_u64, iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1589	FNIEMAIMPLMEDIAF2U128 iemAImpl_pxor_u128, iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1590	/** @} */
1591
1592	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1593	* @{ */
1594	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src));
1595	typedef FNIEMAIMPLMEDIAF1L1U64 *PFNIEMAIMPLMEDIAF1L1U64;
1596	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src));
1597	typedef FNIEMAIMPLMEDIAF1L1U128 *PFNIEMAIMPLMEDIAF1L1U128;
1598	FNIEMAIMPLMEDIAF1L1U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1599	FNIEMAIMPLMEDIAF1L1U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1600	/** @} */
1601
1602	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
1603	* @{ */
1604	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1605	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF1H1U64;
1606	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1607	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF1H1U128;
1608	FNIEMAIMPLMEDIAF1H1U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
1609	FNIEMAIMPLMEDIAF1H1U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
1610	/** @} */
1611
1612	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
1613	* @{ */
1614	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUF,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst,
1615	PCRTUINT128U pu128Src, uint8_t bEvil));
1616	typedef FNIEMAIMPLMEDIAPSHUF *PFNIEMAIMPLMEDIAPSHUF;
1617	FNIEMAIMPLMEDIAPSHUF iemAImpl_pshufhw, iemAImpl_pshuflw, iemAImpl_pshufd;
1618	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil));
1619	/** @} */
1620
1621	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
1622	* @{ */
1623	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1624	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src));
1625	/** @} */
1626
1627	/** @name Media (SSE/MMX/AVX) operation: Sort this later
1628	* @{ */
1629	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1630	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1631	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc));
1632
1633	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1634	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1635	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1636	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1637
1638	/** @} */
1639
1640
1641	/** @name Function tables.
1642	* @{
1643	*/
1644
1645	/**
1646	* Function table for a binary operator providing implementation based on
1647	* operand size.
1648	*/
1649	typedef struct IEMOPBINSIZES
1650	{
1651	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
1652	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
1653	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
1654	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
1655	} IEMOPBINSIZES;
1656	/** Pointer to a binary operator function table. */
1657	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
1658
1659
1660	/**
1661	* Function table for a unary operator providing implementation based on
1662	* operand size.
1663	*/
1664	typedef struct IEMOPUNARYSIZES
1665	{
1666	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
1667	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
1668	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
1669	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
1670	} IEMOPUNARYSIZES;
1671	/** Pointer to a unary operator function table. */
1672	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
1673
1674
1675	/**
1676	* Function table for a shift operator providing implementation based on
1677	* operand size.
1678	*/
1679	typedef struct IEMOPSHIFTSIZES
1680	{
1681	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
1682	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
1683	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
1684	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
1685	} IEMOPSHIFTSIZES;
1686	/** Pointer to a shift operator function table. */
1687	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
1688
1689
1690	/**
1691	* Function table for a multiplication or division operation.
1692	*/
1693	typedef struct IEMOPMULDIVSIZES
1694	{
1695	PFNIEMAIMPLMULDIVU8 pfnU8;
1696	PFNIEMAIMPLMULDIVU16 pfnU16;
1697	PFNIEMAIMPLMULDIVU32 pfnU32;
1698	PFNIEMAIMPLMULDIVU64 pfnU64;
1699	} IEMOPMULDIVSIZES;
1700	/** Pointer to a multiplication or division operation function table. */
1701	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
1702
1703
1704	/**
1705	* Function table for a double precision shift operator providing implementation
1706	* based on operand size.
1707	*/
1708	typedef struct IEMOPSHIFTDBLSIZES
1709	{
1710	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
1711	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
1712	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
1713	} IEMOPSHIFTDBLSIZES;
1714	/** Pointer to a double precision shift function table. */
1715	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
1716
1717
1718	/**
1719	* Function table for media instruction taking two full sized media registers,
1720	* optionally the 2nd being a memory reference (only modifying the first op.)
1721	*/
1722	typedef struct IEMOPMEDIAF2
1723	{
1724	PFNIEMAIMPLMEDIAF2U64 pfnU64;
1725	PFNIEMAIMPLMEDIAF2U128 pfnU128;
1726	} IEMOPMEDIAF2;
1727	/** Pointer to a media operation function table for full sized ops. */
1728	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
1729
1730	/**
1731	* Function table for media instruction taking taking one full and one lower
1732	* half media register.
1733	*/
1734	typedef struct IEMOPMEDIAF1L1
1735	{
1736	PFNIEMAIMPLMEDIAF1L1U64 pfnU64;
1737	PFNIEMAIMPLMEDIAF1L1U128 pfnU128;
1738	} IEMOPMEDIAF1L1;
1739	/** Pointer to a media operation function table for lowhalf+lowhalf -> full. */
1740	typedef IEMOPMEDIAF1L1 const *PCIEMOPMEDIAF1L1;
1741
1742	/**
1743	* Function table for media instruction taking taking one full and one high half
1744	* media register.
1745	*/
1746	typedef struct IEMOPMEDIAF1H1
1747	{
1748	PFNIEMAIMPLMEDIAF1H1U64 pfnU64;
1749	PFNIEMAIMPLMEDIAF1H1U128 pfnU128;
1750	} IEMOPMEDIAF1H1;
1751	/** Pointer to a media operation function table for hihalf+hihalf -> full. */
1752	typedef IEMOPMEDIAF1H1 const *PCIEMOPMEDIAF1H1;
1753
1754
1755	/** @} */
1756
1757
1758	/** @name C instruction implementations for anything slightly complicated.
1759	* @{ */
1760
1761	/**
1762	* For typedef'ing or declaring a C instruction implementation function taking
1763	* no extra arguments.
1764	*
1765	* @param a_Name The name of the type.
1766	*/
1767	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
1768	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
1769	/**
1770	* For defining a C instruction implementation function taking no extra
1771	* arguments.
1772	*
1773	* @param a_Name The name of the function
1774	*/
1775	# define IEM_CIMPL_DEF_0(a_Name) \
1776	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
1777	/**
1778	* Prototype version of IEM_CIMPL_DEF_0.
1779	*/
1780	# define IEM_CIMPL_PROTO_0(a_Name) \
1781	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
1782	/**
1783	* For calling a C instruction implementation function taking no extra
1784	* arguments.
1785	*
1786	* This special call macro adds default arguments to the call and allow us to
1787	* change these later.
1788	*
1789	* @param a_fn The name of the function.
1790	*/
1791	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
1792
1793	/**
1794	* For typedef'ing or declaring a C instruction implementation function taking
1795	* one extra argument.
1796	*
1797	* @param a_Name The name of the type.
1798	* @param a_Type0 The argument type.
1799	* @param a_Arg0 The argument name.
1800	*/
1801	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
1802	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1803	/**
1804	* For defining a C instruction implementation function taking one extra
1805	* argument.
1806	*
1807	* @param a_Name The name of the function
1808	* @param a_Type0 The argument type.
1809	* @param a_Arg0 The argument name.
1810	*/
1811	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
1812	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1813	/**
1814	* Prototype version of IEM_CIMPL_DEF_1.
1815	*/
1816	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
1817	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1818	/**
1819	* For calling a C instruction implementation function taking one extra
1820	* argument.
1821	*
1822	* This special call macro adds default arguments to the call and allow us to
1823	* change these later.
1824	*
1825	* @param a_fn The name of the function.
1826	* @param a0 The name of the 1st argument.
1827	*/
1828	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
1829
1830	/**
1831	* For typedef'ing or declaring a C instruction implementation function taking
1832	* two extra arguments.
1833	*
1834	* @param a_Name The name of the type.
1835	* @param a_Type0 The type of the 1st argument
1836	* @param a_Arg0 The name of the 1st argument.
1837	* @param a_Type1 The type of the 2nd argument.
1838	* @param a_Arg1 The name of the 2nd argument.
1839	*/
1840	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1841	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1842	/**
1843	* For defining a C instruction implementation function taking two extra
1844	* arguments.
1845	*
1846	* @param a_Name The name of the function.
1847	* @param a_Type0 The type of the 1st argument
1848	* @param a_Arg0 The name of the 1st argument.
1849	* @param a_Type1 The type of the 2nd argument.
1850	* @param a_Arg1 The name of the 2nd argument.
1851	*/
1852	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1853	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1854	/**
1855	* Prototype version of IEM_CIMPL_DEF_2.
1856	*/
1857	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1858	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1859	/**
1860	* For calling a C instruction implementation function taking two extra
1861	* arguments.
1862	*
1863	* This special call macro adds default arguments to the call and allow us to
1864	* change these later.
1865	*
1866	* @param a_fn The name of the function.
1867	* @param a0 The name of the 1st argument.
1868	* @param a1 The name of the 2nd argument.
1869	*/
1870	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
1871
1872	/**
1873	* For typedef'ing or declaring a C instruction implementation function taking
1874	* three extra arguments.
1875	*
1876	* @param a_Name The name of the type.
1877	* @param a_Type0 The type of the 1st argument
1878	* @param a_Arg0 The name of the 1st argument.
1879	* @param a_Type1 The type of the 2nd argument.
1880	* @param a_Arg1 The name of the 2nd argument.
1881	* @param a_Type2 The type of the 3rd argument.
1882	* @param a_Arg2 The name of the 3rd argument.
1883	*/
1884	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1885	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1886	/**
1887	* For defining a C instruction implementation function taking three extra
1888	* arguments.
1889	*
1890	* @param a_Name The name of the function.
1891	* @param a_Type0 The type of the 1st argument
1892	* @param a_Arg0 The name of the 1st argument.
1893	* @param a_Type1 The type of the 2nd argument.
1894	* @param a_Arg1 The name of the 2nd argument.
1895	* @param a_Type2 The type of the 3rd argument.
1896	* @param a_Arg2 The name of the 3rd argument.
1897	*/
1898	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1899	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1900	/**
1901	* Prototype version of IEM_CIMPL_DEF_3.
1902	*/
1903	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1904	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1905	/**
1906	* For calling a C instruction implementation function taking three extra
1907	* arguments.
1908	*
1909	* This special call macro adds default arguments to the call and allow us to
1910	* change these later.
1911	*
1912	* @param a_fn The name of the function.
1913	* @param a0 The name of the 1st argument.
1914	* @param a1 The name of the 2nd argument.
1915	* @param a2 The name of the 3rd argument.
1916	*/
1917	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
1918
1919
1920	/**
1921	* For typedef'ing or declaring a C instruction implementation function taking
1922	* four extra arguments.
1923	*
1924	* @param a_Name The name of the type.
1925	* @param a_Type0 The type of the 1st argument
1926	* @param a_Arg0 The name of the 1st argument.
1927	* @param a_Type1 The type of the 2nd argument.
1928	* @param a_Arg1 The name of the 2nd argument.
1929	* @param a_Type2 The type of the 3rd argument.
1930	* @param a_Arg2 The name of the 3rd argument.
1931	* @param a_Type3 The type of the 4th argument.
1932	* @param a_Arg3 The name of the 4th argument.
1933	*/
1934	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1935	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
1936	/**
1937	* For defining a C instruction implementation function taking four extra
1938	* arguments.
1939	*
1940	* @param a_Name The name of the function.
1941	* @param a_Type0 The type of the 1st argument
1942	* @param a_Arg0 The name of the 1st argument.
1943	* @param a_Type1 The type of the 2nd argument.
1944	* @param a_Arg1 The name of the 2nd argument.
1945	* @param a_Type2 The type of the 3rd argument.
1946	* @param a_Arg2 The name of the 3rd argument.
1947	* @param a_Type3 The type of the 4th argument.
1948	* @param a_Arg3 The name of the 4th argument.
1949	*/
1950	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1951	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1952	a_Type2 a_Arg2, a_Type3 a_Arg3))
1953	/**
1954	* Prototype version of IEM_CIMPL_DEF_4.
1955	*/
1956	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1957	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1958	a_Type2 a_Arg2, a_Type3 a_Arg3))
1959	/**
1960	* For calling a C instruction implementation function taking four extra
1961	* arguments.
1962	*
1963	* This special call macro adds default arguments to the call and allow us to
1964	* change these later.
1965	*
1966	* @param a_fn The name of the function.
1967	* @param a0 The name of the 1st argument.
1968	* @param a1 The name of the 2nd argument.
1969	* @param a2 The name of the 3rd argument.
1970	* @param a3 The name of the 4th argument.
1971	*/
1972	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
1973
1974
1975	/**
1976	* For typedef'ing or declaring a C instruction implementation function taking
1977	* five extra arguments.
1978	*
1979	* @param a_Name The name of the type.
1980	* @param a_Type0 The type of the 1st argument
1981	* @param a_Arg0 The name of the 1st argument.
1982	* @param a_Type1 The type of the 2nd argument.
1983	* @param a_Arg1 The name of the 2nd argument.
1984	* @param a_Type2 The type of the 3rd argument.
1985	* @param a_Arg2 The name of the 3rd argument.
1986	* @param a_Type3 The type of the 4th argument.
1987	* @param a_Arg3 The name of the 4th argument.
1988	* @param a_Type4 The type of the 5th argument.
1989	* @param a_Arg4 The name of the 5th argument.
1990	*/
1991	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
1992	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
1993	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
1994	a_Type3 a_Arg3, a_Type4 a_Arg4))
1995	/**
1996	* For defining a C instruction implementation function taking five extra
1997	* arguments.
1998	*
1999	* @param a_Name The name of the function.
2000	* @param a_Type0 The type of the 1st argument
2001	* @param a_Arg0 The name of the 1st argument.
2002	* @param a_Type1 The type of the 2nd argument.
2003	* @param a_Arg1 The name of the 2nd argument.
2004	* @param a_Type2 The type of the 3rd argument.
2005	* @param a_Arg2 The name of the 3rd argument.
2006	* @param a_Type3 The type of the 4th argument.
2007	* @param a_Arg3 The name of the 4th argument.
2008	* @param a_Type4 The type of the 5th argument.
2009	* @param a_Arg4 The name of the 5th argument.
2010	*/
2011	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2012	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2013	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
2014	/**
2015	* Prototype version of IEM_CIMPL_DEF_5.
2016	*/
2017	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2018	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2019	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
2020	/**
2021	* For calling a C instruction implementation function taking five extra
2022	* arguments.
2023	*
2024	* This special call macro adds default arguments to the call and allow us to
2025	* change these later.
2026	*
2027	* @param a_fn The name of the function.
2028	* @param a0 The name of the 1st argument.
2029	* @param a1 The name of the 2nd argument.
2030	* @param a2 The name of the 3rd argument.
2031	* @param a3 The name of the 4th argument.
2032	* @param a4 The name of the 5th argument.
2033	*/
2034	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
2035
2036	/** @} */
2037
2038
2039	/** @name Opcode Decoder Function Types.
2040	* @{ */
2041
2042	/** @typedef PFNIEMOP
2043	* Pointer to an opcode decoder function.
2044	*/
2045
2046	/** @def FNIEMOP_DEF
2047	* Define an opcode decoder function.
2048	*
2049	* We're using macors for this so that adding and removing parameters as well as
2050	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
2051	*
2052	* @param a_Name The function name.
2053	*/
2054
2055	/** @typedef PFNIEMOPRM
2056	* Pointer to an opcode decoder function with RM byte.
2057	*/
2058
2059	/** @def FNIEMOPRM_DEF
2060	* Define an opcode decoder function with RM byte.
2061	*
2062	* We're using macors for this so that adding and removing parameters as well as
2063	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
2064	*
2065	* @param a_Name The function name.
2066	*/
2067
2068	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2069	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
2070	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2071	# define FNIEMOP_DEF(a_Name) \
2072	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
2073	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2074	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
2075	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2076	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
2077
2078	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2079	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
2080	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2081	# define FNIEMOP_DEF(a_Name) \
2082	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
2083	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2084	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
2085	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2086	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
2087
2088	#elif defined(__GNUC__)
2089	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
2090	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2091	# define FNIEMOP_DEF(a_Name) \
2092	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
2093	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2094	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
2095	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2096	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
2097
2098	#else
2099	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
2100	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2101	# define FNIEMOP_DEF(a_Name) \
2102	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
2103	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2104	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
2105	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2106	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
2107
2108	#endif
2109	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
2110
2111	/**
2112	* Call an opcode decoder function.
2113	*
2114	* We're using macors for this so that adding and removing parameters can be
2115	* done as we please. See FNIEMOP_DEF.
2116	*/
2117	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
2118
2119	/**
2120	* Call a common opcode decoder function taking one extra argument.
2121	*
2122	* We're using macors for this so that adding and removing parameters can be
2123	* done as we please. See FNIEMOP_DEF_1.
2124	*/
2125	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
2126
2127	/**
2128	* Call a common opcode decoder function taking one extra argument.
2129	*
2130	* We're using macors for this so that adding and removing parameters can be
2131	* done as we please. See FNIEMOP_DEF_1.
2132	*/
2133	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
2134	/** @} */
2135
2136
2137	/** @name Misc Helpers
2138	* @{ */
2139
2140	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
2141	* due to GCC lacking knowledge about the value range of a switch. */
2142	#define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
2143
2144	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
2145	#define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
2146
2147	/**
2148	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
2149	* occation.
2150	*/
2151	#ifdef LOG_ENABLED
2152	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
2153	do { \
2154	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
2155	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
2156	} while (0)
2157	#else
2158	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
2159	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
2160	#endif
2161
2162	/**
2163	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
2164	* occation using the supplied logger statement.
2165	*
2166	* @param a_LoggerArgs What to log on failure.
2167	*/
2168	#ifdef LOG_ENABLED
2169	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
2170	do { \
2171	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
2172	/LogFunc(a_LoggerArgs);/ \
2173	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
2174	} while (0)
2175	#else
2176	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
2177	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
2178	#endif
2179
2180	/**
2181	* Check if we're currently executing in real or virtual 8086 mode.
2182	*
2183	* @returns @c true if it is, @c false if not.
2184	* @param a_pVCpu The IEM state of the current CPU.
2185	*/
2186	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (CPUMIsGuestInRealOrV86ModeEx(IEM_GET_CTX(a_pVCpu)))
2187
2188	/**
2189	* Check if we're currently executing in virtual 8086 mode.
2190	*
2191	* @returns @c true if it is, @c false if not.
2192	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2193	*/
2194	#define IEM_IS_V86_MODE(a_pVCpu) (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(a_pVCpu)))
2195
2196	/**
2197	* Check if we're currently executing in long mode.
2198	*
2199	* @returns @c true if it is, @c false if not.
2200	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2201	*/
2202	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
2203
2204	/**
2205	* Check if we're currently executing in a 64-bit code segment.
2206	*
2207	* @returns @c true if it is, @c false if not.
2208	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2209	*/
2210	#define IEM_IS_64BIT_CODE(a_pVCpu) (CPUMIsGuestIn64BitCodeEx(IEM_GET_CTX(a_pVCpu)))
2211
2212	/**
2213	* Check if we're currently executing in real mode.
2214	*
2215	* @returns @c true if it is, @c false if not.
2216	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2217	*/
2218	#define IEM_IS_REAL_MODE(a_pVCpu) (CPUMIsGuestInRealModeEx(IEM_GET_CTX(a_pVCpu)))
2219
2220	/**
2221	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
2222	* @returns PCCPUMFEATURES
2223	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2224	*/
2225	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
2226
2227	/**
2228	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
2229	* @returns PCCPUMFEATURES
2230	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2231	*/
2232	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.HostFeatures))
2233
2234	/**
2235	* Evaluates to true if we're presenting an Intel CPU to the guest.
2236	*/
2237	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
2238
2239	/**
2240	* Evaluates to true if we're presenting an AMD CPU to the guest.
2241	*/
2242	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
2243
2244	/**
2245	* Check if the address is canonical.
2246	*/
2247	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
2248
2249	/**
2250	* Gets the effective VEX.VVVV value.
2251	*
2252	* The 4th bit is ignored if not 64-bit code.
2253	* @returns effective V-register value.
2254	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2255	*/
2256	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
2257	((a_pVCpu)->iem.s.enmCpuMode == IEMMODE_64BIT ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
2258
2259
2260	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2261
2262	/**
2263	* Check if the guest has entered VMX root operation.
2264	*/
2265	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
2266
2267	/**
2268	* Check if the guest has entered VMX non-root operation.
2269	*/
2270	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(a_pVCpu)))
2271
2272	/**
2273	* Check if the nested-guest has the given Pin-based VM-execution control set.
2274	*/
2275	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) \
2276	(CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
2277
2278	/**
2279	* Check if the nested-guest has the given Processor-based VM-execution control set.
2280	*/
2281	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) \
2282	(CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
2283
2284	/**
2285	* Check if the nested-guest has the given Secondary Processor-based VM-execution
2286	* control set.
2287	*/
2288	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) \
2289	(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
2290
2291	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
2292	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
2293
2294	/** Whether a shadow VMCS is present for the given VCPU. */
2295	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
2296
2297	/** Gets the VMXON region pointer. */
2298	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
2299
2300	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
2301	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
2302
2303	/** Whether a current VMCS is present for the given VCPU. */
2304	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
2305
2306	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
2307	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
2308	do \
2309	{ \
2310	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
2311	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
2312	} while (0)
2313
2314	/** Clears any current VMCS for the given VCPU. */
2315	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
2316	do \
2317	{ \
2318	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
2319	} while (0)
2320
2321	/**
2322	* Invokes the VMX VM-exit handler for an instruction intercept.
2323	*/
2324	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
2325	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
2326
2327	/**
2328	* Invokes the VMX VM-exit handler for an instruction intercept where the
2329	* instruction provides additional VM-exit information.
2330	*/
2331	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
2332	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
2333
2334	/**
2335	* Invokes the VMX VM-exit handler for a task switch.
2336	*/
2337	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
2338	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
2339
2340	/**
2341	* Invokes the VMX VM-exit handler for MWAIT.
2342	*/
2343	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
2344	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
2345
2346	/**
2347	* Invokes the VMX VM-exit handler for EPT faults.
2348	*/
2349	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
2350	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
2351
2352	/**
2353	* Invokes the VMX VM-exit handler.
2354	*/
2355	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
2356	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
2357
2358	#else
2359	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
2360	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
2361	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
2362	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
2363	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
2364	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2365	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2366	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2367	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2368	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2369	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
2370
2371	#endif
2372
2373	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2374	/**
2375	* Check if an SVM control/instruction intercept is set.
2376	*/
2377	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
2378	(CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
2379
2380	/**
2381	* Check if an SVM read CRx intercept is set.
2382	*/
2383	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
2384	(CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
2385
2386	/**
2387	* Check if an SVM write CRx intercept is set.
2388	*/
2389	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
2390	(CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
2391
2392	/**
2393	* Check if an SVM read DRx intercept is set.
2394	*/
2395	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
2396	(CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
2397
2398	/**
2399	* Check if an SVM write DRx intercept is set.
2400	*/
2401	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
2402	(CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
2403
2404	/**
2405	* Check if an SVM exception intercept is set.
2406	*/
2407	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
2408	(CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
2409
2410	/**
2411	* Invokes the SVM \#VMEXIT handler for the nested-guest.
2412	*/
2413	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
2414	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
2415
2416	/**
2417	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
2418	* corresponding decode assist information.
2419	*/
2420	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
2421	do \
2422	{ \
2423	uint64_t uExitInfo1; \
2424	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
2425	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
2426	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
2427	else \
2428	uExitInfo1 = 0; \
2429	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
2430	} while (0)
2431
2432	/** Check and handles SVM nested-guest instruction intercept and updates
2433	* NRIP if needed.
2434	*/
2435	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
2436	do \
2437	{ \
2438	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
2439	{ \
2440	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
2441	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
2442	} \
2443	} while (0)
2444
2445	/** Checks and handles SVM nested-guest CR0 read intercept. */
2446	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) \
2447	do \
2448	{ \
2449	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
2450	{ /* probably likely */ } \
2451	else \
2452	{ \
2453	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
2454	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
2455	} \
2456	} while (0)
2457
2458	/**
2459	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
2460	*/
2461	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) \
2462	do { \
2463	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
2464	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), IEM_GET_INSTR_LEN(a_pVCpu)); \
2465	} while (0)
2466
2467	#else
2468	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
2469	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
2470	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
2471	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
2472	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
2473	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
2474	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
2475	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
2476	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0)
2477	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) do { } while (0)
2478	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) do { } while (0)
2479
2480	#endif
2481
2482	/** @} */
2483
2484
2485
2486	/**
2487	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
2488	*/
2489	typedef union IEMSELDESC
2490	{
2491	/** The legacy view. */
2492	X86DESC Legacy;
2493	/** The long mode view. */
2494	X86DESC64 Long;
2495	} IEMSELDESC;
2496	/** Pointer to a selector descriptor table entry. */
2497	typedef IEMSELDESC *PIEMSELDESC;
2498
2499	/** @name Raising Exceptions.
2500	* @{ */
2501	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
2502	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
2503
2504	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
2505	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
2506	#ifdef IEM_WITH_SETJMP
2507	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
2508	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
2509	#endif
2510	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
2511	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
2512	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
2513	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
2514	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
2515	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
2516	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
2517	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
2518	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
2519	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
2520	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
2521	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
2522	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
2523	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
2524	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
2525	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
2526	#ifdef IEM_WITH_SETJMP
2527	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2528	#endif
2529	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
2530	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
2531	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
2532	#ifdef IEM_WITH_SETJMP
2533	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
2534	#endif
2535	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
2536	#ifdef IEM_WITH_SETJMP
2537	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
2538	#endif
2539	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
2540	#ifdef IEM_WITH_SETJMP
2541	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
2542	#endif
2543	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
2544	#ifdef IEM_WITH_SETJMP
2545	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
2546	#endif
2547	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu);
2548	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu);
2549	#ifdef IEM_WITH_SETJMP
2550	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2551	#endif
2552
2553	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
2554	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
2555	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
2556
2557	/**
2558	* Macro for calling iemCImplRaiseDivideError().
2559	*
2560	* This enables us to add/remove arguments and force different levels of
2561	* inlining as we wish.
2562	*
2563	* @return Strict VBox status code.
2564	*/
2565	#define IEMOP_RAISE_DIVIDE_ERROR() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseDivideError)
2566
2567	/**
2568	* Macro for calling iemCImplRaiseInvalidLockPrefix().
2569	*
2570	* This enables us to add/remove arguments and force different levels of
2571	* inlining as we wish.
2572	*
2573	* @return Strict VBox status code.
2574	*/
2575	#define IEMOP_RAISE_INVALID_LOCK_PREFIX() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidLockPrefix)
2576
2577	/**
2578	* Macro for calling iemCImplRaiseInvalidOpcode().
2579	*
2580	* This enables us to add/remove arguments and force different levels of
2581	* inlining as we wish.
2582	*
2583	* @return Strict VBox status code.
2584	*/
2585	#define IEMOP_RAISE_INVALID_OPCODE() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidOpcode)
2586	/** @} */
2587
2588	/** @name Register Access.
2589	* @{ */
2590	VBOXSTRICTRC iemRegRipRelativeJumpS8(PVMCPUCC pVCpu, int8_t offNextInstr) RT_NOEXCEPT;
2591	VBOXSTRICTRC iemRegRipRelativeJumpS16(PVMCPUCC pVCpu, int16_t offNextInstr) RT_NOEXCEPT;
2592	VBOXSTRICTRC iemRegRipRelativeJumpS32(PVMCPUCC pVCpu, int32_t offNextInstr) RT_NOEXCEPT;
2593	VBOXSTRICTRC iemRegRipJump(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
2594	/** @} */
2595
2596	/** @name FPU access and helpers.
2597	* @{ */
2598	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult) RT_NOEXCEPT;
2599	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2600	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult) RT_NOEXCEPT;
2601	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
2602	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
2603	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
2604	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2605	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
2606	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2607	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2608	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
2609	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
2610	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2611	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
2612	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2613	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
2614	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2615	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
2616	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2617	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu) RT_NOEXCEPT;
2618	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
2619	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu) RT_NOEXCEPT;
2620	void iemFpuStackPushOverflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
2621	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2622	/** @} */
2623
2624	/** @name Memory access.
2625	* @{ */
2626	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t fAccess) RT_NOEXCEPT;
2627	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
2628	#ifndef IN_RING3
2629	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
2630	#endif
2631	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
2632	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
2633	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
2634	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
2635
2636	#ifdef IEM_WITH_CODE_TLB
2637	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) RT_NOEXCEPT;
2638	#else
2639	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
2640	#endif
2641	#ifdef IEM_WITH_SETJMP
2642	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2643	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2644	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2645	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2646	#else
2647	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
2648	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
2649	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
2650	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2651	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
2652	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
2653	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2654	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
2655	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2656	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2657	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2658	#endif
2659
2660	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2661	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2662	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2663	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2664	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2665	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2666	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2667	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2668	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2669	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2670	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2671	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2672	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
2673	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
2674	#ifdef IEM_WITH_SETJMP
2675	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2676	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2677	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2678	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2679	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2680	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2681	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2682	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2683	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2684	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2685	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2686	#endif
2687
2688	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2689	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2690	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2691	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2692	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
2693
2694	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
2695	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
2696	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
2697	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
2698	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
2699	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
2700	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
2701	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
2702	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2703	#ifdef IEM_WITH_SETJMP
2704	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
2705	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
2706	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
2707	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
2708	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
2709	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
2710	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
2711	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
2712	#endif
2713
2714	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
2715	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
2716	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
2717	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
2718	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
2719	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2720	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2721	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2722	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
2723	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
2724	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t cbMem, void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
2725	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
2726	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
2727	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
2728	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
2729	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2730	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2731	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2732	/** @} */
2733
2734	/** @name IEMAllCImpl.cpp
2735	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
2736	* @{ */
2737	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
2738	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
2739	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
2740	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
2741	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
2742	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
2743	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
2744	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
2745	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
2746	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
2747	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
2748	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
2749	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
2750	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
2751	IEM_CIMPL_PROTO_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
2752	IEM_CIMPL_PROTO_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
2753	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
2754	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
2755	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
2756	IEM_CIMPL_PROTO_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop);
2757	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
2758	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
2759	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
2760	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
2761	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
2762	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
2763	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
2764	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
2765	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
2766	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
2767	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
2768	IEM_CIMPL_PROTO_0(iemCImpl_sysret);
2769	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
2770	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
2771	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
2772	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
2773	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
2774	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
2775	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
2776	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
2777	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
2778	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
2779	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2780	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
2781	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2782	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
2783	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
2784	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2785	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
2786	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
2787	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2788	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
2789	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
2790	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2791	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
2792	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
2793	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
2794	IEM_CIMPL_PROTO_0(iemCImpl_clts);
2795	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
2796	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
2797	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
2798	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
2799	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
2800	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
2801	IEM_CIMPL_PROTO_0(iemCImpl_invd);
2802	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
2803	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
2804	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
2805	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
2806	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
2807	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
2808	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
2809	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
2810	IEM_CIMPL_PROTO_1(iemCImpl_in_eAX_DX, uint8_t, cbReg);
2811	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
2812	IEM_CIMPL_PROTO_1(iemCImpl_out_DX_eAX, uint8_t, cbReg);
2813	IEM_CIMPL_PROTO_0(iemCImpl_cli);
2814	IEM_CIMPL_PROTO_0(iemCImpl_sti);
2815	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
2816	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
2817	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
2818	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
2819	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
2820	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
2821	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
2822	IEM_CIMPL_PROTO_0(iemCImpl_daa);
2823	IEM_CIMPL_PROTO_0(iemCImpl_das);
2824	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
2825	IEM_CIMPL_PROTO_0(iemCImpl_aas);
2826	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
2827	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
2828	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
2829	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
2830	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
2831	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
2832	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
2833	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
2834	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
2835	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
2836	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
2837	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
2838	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
2839	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
2840	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
2841	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2842	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2843	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
2844	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
2845	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
2846	IEM_CIMPL_PROTO_1(iemCImpl_fxch_underflow, uint8_t, iStReg);
2847	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop);
2848	/** @} */
2849
2850	/** @name IEMAllCImplStrInstr.cpp.h
2851	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
2852	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
2853	* @{ */
2854	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
2855	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
2856	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
2857	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
2858	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
2859	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
2860	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
2861	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
2862	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
2863	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
2864	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
2865
2866	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
2867	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
2868	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
2869	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
2870	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
2871	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
2872	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
2873	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
2874	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
2875	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
2876	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
2877
2878	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
2879	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
2880	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
2881	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
2882	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
2883	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
2884	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
2885	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
2886	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
2887	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
2888	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
2889
2890
2891	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
2892	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
2893	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
2894	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
2895	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
2896	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
2897	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
2898	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
2899	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
2900	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
2901	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
2902
2903	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
2904	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
2905	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
2906	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
2907	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
2908	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
2909	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
2910	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
2911	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
2912	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
2913	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
2914
2915	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
2916	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
2917	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
2918	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
2919	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
2920	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
2921	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
2922	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
2923	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
2924	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
2925	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
2926
2927	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
2928	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
2929	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
2930	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
2931	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
2932	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
2933	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
2934	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
2935	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
2936	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
2937	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
2938
2939
2940	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
2941	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
2942	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
2943	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
2944	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
2945	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
2946	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
2947	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
2948	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
2949	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
2950	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
2951
2952	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
2953	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
2954	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
2955	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
2956	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
2957	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
2958	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
2959	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
2960	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
2961	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
2962	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
2963
2964	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
2965	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
2966	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
2967	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
2968	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
2969	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
2970	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
2971	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
2972	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
2973	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
2974	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
2975
2976	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
2977	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
2978	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
2979	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
2980	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
2981	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
2982	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
2983	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
2984	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
2985	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
2986	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
2987	/** @} */
2988
2989	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2990	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
2991	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
2992	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
2993	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
2994	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
2995	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
2996	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
2997	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
2998	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
2999	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3000	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
3001	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3002	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
3003	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3004	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3005	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3006	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3007	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3008	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3009	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
3010	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
3011	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
3012	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
3013	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
3014	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
3015	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
3016	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
3017	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
3018	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
3019	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
3020	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
3021	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
3022	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
3023	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
3024	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3025	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3026	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3027	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
3028	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
3029	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
3030	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField);
3031	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
3032	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
3033	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
3034	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
3035	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
3036	IEM_CIMPL_PROTO_0(iemCImpl_vmcall);
3037	#endif
3038
3039	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3040	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
3041	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3042	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
3043	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
3044	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite) RT_NOEXCEPT;
3045	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
3046	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
3047	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
3048	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
3049	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
3050	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
3051	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
3052	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
3053	#endif
3054
3055	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall);
3056	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode);
3057
3058
3059	extern const PFNIEMOP g_apfnOneByteMap[256];
3060
3061	/** @} */
3062
3063	RT_C_DECLS_END
3064
3065	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
3066

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 94842

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