IEMInternal.h@ 95185

Last change on this file since 95185 was 95185, checked in by vboxsync, 3 years ago
VMM/IEM: Use setjmp-without-sigmask.h as well.
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1	/* $Id: IEMInternal.h 95185 2022-06-03 13:36:56Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
19	#define VMM_INCLUDED_SRC_include_IEMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/vmm/cpum.h>
25	#include <VBox/vmm/iem.h>
26	#include <VBox/vmm/pgm.h>
27	#include <VBox/vmm/stam.h>
28	#include <VBox/param.h>
29
30	#include <iprt/setjmp-without-sigmask.h>
31
32
33	RT_C_DECLS_BEGIN
34
35
36	/** @defgroup grp_iem_int Internals
37	* @ingroup grp_iem
38	* @internal
39	* @{
40	*/
41
42	/** For expanding symbol in slickedit and other products tagging and
43	* crossreferencing IEM symbols. */
44	#ifndef IEM_STATIC
45	# define IEM_STATIC static
46	#endif
47
48	/** @def IEM_WITH_SETJMP
49	* Enables alternative status code handling using setjmps.
50	*
51	* This adds a bit of expense via the setjmp() call since it saves all the
52	* non-volatile registers. However, it eliminates return code checks and allows
53	* for more optimal return value passing (return regs instead of stack buffer).
54	*/
55	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
56	# define IEM_WITH_SETJMP
57	#endif
58
59	#define IEM_IMPLEMENTS_TASKSWITCH
60
61	/** @def IEM_WITH_3DNOW
62	* Includes the 3DNow decoding. */
63	#define IEM_WITH_3DNOW
64
65	/** @def IEM_WITH_THREE_0F_38
66	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
67	#define IEM_WITH_THREE_0F_38
68
69	/** @def IEM_WITH_THREE_0F_3A
70	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
71	#define IEM_WITH_THREE_0F_3A
72
73	/** @def IEM_WITH_VEX
74	* Includes the VEX decoding. */
75	#define IEM_WITH_VEX
76
77	/** @def IEM_CFG_TARGET_CPU
78	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
79	*
80	* By default we allow this to be configured by the user via the
81	* CPUM/GuestCpuName config string, but this comes at a slight cost during
82	* decoding. So, for applications of this code where there is no need to
83	* be dynamic wrt target CPU, just modify this define.
84	*/
85	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
86	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
87	#endif
88
89	//#define IEM_WITH_CODE_TLB // - work in progress
90	//#define IEM_WITH_DATA_TLB // - work in progress
91
92
93	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
94	* Use unaligned accesses instead of elaborate byte assembly. */
95	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
96	# define IEM_USE_UNALIGNED_DATA_ACCESS
97	#endif
98
99	//#define IEM_LOG_MEMORY_WRITES
100
101	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
102	/** Instruction statistics. */
103	typedef struct IEMINSTRSTATS
104	{
105	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
106	# include "IEMInstructionStatisticsTmpl.h"
107	# undef IEM_DO_INSTR_STAT
108	} IEMINSTRSTATS;
109	#else
110	struct IEMINSTRSTATS;
111	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
112	#endif
113	/** Pointer to IEM instruction statistics. */
114	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
115
116
117	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::idxTargetCpuEflFlavour
118	* @{ */
119	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
120	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
121	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
122	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
123	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
124	/** Selects the right variant from a_aArray.
125	* pVCpu is implicit in the caller context. */
126	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
127	(a_aArray[pVCpu->iem.s.idxTargetCpuEflFlavour & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
128	/** @} */
129
130
131	/**
132	* Extended operand mode that includes a representation of 8-bit.
133	*
134	* This is used for packing down modes when invoking some C instruction
135	* implementations.
136	*/
137	typedef enum IEMMODEX
138	{
139	IEMMODEX_16BIT = IEMMODE_16BIT,
140	IEMMODEX_32BIT = IEMMODE_32BIT,
141	IEMMODEX_64BIT = IEMMODE_64BIT,
142	IEMMODEX_8BIT
143	} IEMMODEX;
144	AssertCompileSize(IEMMODEX, 4);
145
146
147	/**
148	* Branch types.
149	*/
150	typedef enum IEMBRANCH
151	{
152	IEMBRANCH_JUMP = 1,
153	IEMBRANCH_CALL,
154	IEMBRANCH_TRAP,
155	IEMBRANCH_SOFTWARE_INT,
156	IEMBRANCH_HARDWARE_INT
157	} IEMBRANCH;
158	AssertCompileSize(IEMBRANCH, 4);
159
160
161	/**
162	* INT instruction types.
163	*/
164	typedef enum IEMINT
165	{
166	/** INT n instruction (opcode 0xcd imm). */
167	IEMINT_INTN = 0,
168	/** Single byte INT3 instruction (opcode 0xcc). */
169	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
170	/** Single byte INTO instruction (opcode 0xce). */
171	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
172	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
173	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
174	} IEMINT;
175	AssertCompileSize(IEMINT, 4);
176
177
178	/**
179	* A FPU result.
180	*/
181	typedef struct IEMFPURESULT
182	{
183	/** The output value. */
184	RTFLOAT80U r80Result;
185	/** The output status. */
186	uint16_t FSW;
187	} IEMFPURESULT;
188	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
189	/** Pointer to a FPU result. */
190	typedef IEMFPURESULT *PIEMFPURESULT;
191	/** Pointer to a const FPU result. */
192	typedef IEMFPURESULT const *PCIEMFPURESULT;
193
194
195	/**
196	* A FPU result consisting of two output values and FSW.
197	*/
198	typedef struct IEMFPURESULTTWO
199	{
200	/** The first output value. */
201	RTFLOAT80U r80Result1;
202	/** The output status. */
203	uint16_t FSW;
204	/** The second output value. */
205	RTFLOAT80U r80Result2;
206	} IEMFPURESULTTWO;
207	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
208	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
209	/** Pointer to a FPU result consisting of two output values and FSW. */
210	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
211	/** Pointer to a const FPU result consisting of two output values and FSW. */
212	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
213
214
215	/**
216	* IEM TLB entry.
217	*
218	* Lookup assembly:
219	* @code{.asm}
220	; Calculate tag.
221	mov rax, [VA]
222	shl rax, 16
223	shr rax, 16 + X86_PAGE_SHIFT
224	or rax, [uTlbRevision]
225
226	; Do indexing.
227	movzx ecx, al
228	lea rcx, [pTlbEntries + rcx]
229
230	; Check tag.
231	cmp [rcx + IEMTLBENTRY.uTag], rax
232	jne .TlbMiss
233
234	; Check access.
235	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
236	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
237	cmp rax, [uTlbPhysRev]
238	jne .TlbMiss
239
240	; Calc address and we're done.
241	mov eax, X86_PAGE_OFFSET_MASK
242	and eax, [VA]
243	or rax, [rcx + IEMTLBENTRY.pMappingR3]
244	%ifdef VBOX_WITH_STATISTICS
245	inc qword [cTlbHits]
246	%endif
247	jmp .Done
248
249	.TlbMiss:
250	mov r8d, ACCESS_FLAGS
251	mov rdx, [VA]
252	mov rcx, [pVCpu]
253	call iemTlbTypeMiss
254	.Done:
255
256	@endcode
257	*
258	*/
259	typedef struct IEMTLBENTRY
260	{
261	/** The TLB entry tag.
262	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
263	* is ASSUMING a virtual address width of 48 bits.
264	*
265	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
266	*
267	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
268	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
269	* revision wraps around though, the tags needs to be zeroed.
270	*
271	* @note Try use SHRD instruction? After seeing
272	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
273	*
274	* @todo This will need to be reorganized for 57-bit wide virtual address and
275	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
276	* have to move the TLB entry versioning entirely to the
277	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
278	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
279	* consumed by PCID and ASID (12 + 6 = 18).
280	*/
281	uint64_t uTag;
282	/** Access flags and physical TLB revision.
283	*
284	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
285	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
286	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
287	* - Bit 3 - pgm phys/virt - not directly writable.
288	* - Bit 4 - pgm phys page - not directly readable.
289	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
290	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
291	* - Bit 7 - tlb entry - pMappingR3 member not valid.
292	* - Bits 63 thru 8 are used for the physical TLB revision number.
293	*
294	* We're using complemented bit meanings here because it makes it easy to check
295	* whether special action is required. For instance a user mode write access
296	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
297	* non-zero result would mean special handling needed because either it wasn't
298	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
299	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
300	* need to check any PTE flag.
301	*/
302	uint64_t fFlagsAndPhysRev;
303	/** The guest physical page address. */
304	uint64_t GCPhys;
305	/** Pointer to the ring-3 mapping. */
306	R3PTRTYPE(uint8_t *) pbMappingR3;
307	#if HC_ARCH_BITS == 32
308	uint32_t u32Padding1;
309	#endif
310	} IEMTLBENTRY;
311	AssertCompileSize(IEMTLBENTRY, 32);
312	/** Pointer to an IEM TLB entry. */
313	typedef IEMTLBENTRY *PIEMTLBENTRY;
314
315	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
316	* @{ */
317	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
318	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
319	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
320	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
321	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
322	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
323	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
324	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
325	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
326	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
327	/** @} */
328
329
330	/**
331	* An IEM TLB.
332	*
333	* We've got two of these, one for data and one for instructions.
334	*/
335	typedef struct IEMTLB
336	{
337	/** The TLB entries.
338	* We've choosen 256 because that way we can obtain the result directly from a
339	* 8-bit register without an additional AND instruction. */
340	IEMTLBENTRY aEntries[256];
341	/** The TLB revision.
342	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
343	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
344	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
345	* (The revision zero indicates an invalid TLB entry.)
346	*
347	* The initial value is choosen to cause an early wraparound. */
348	uint64_t uTlbRevision;
349	/** The TLB physical address revision - shadow of PGM variable.
350	*
351	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
352	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
353	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
354	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
355	*
356	* The initial value is choosen to cause an early wraparound. */
357	uint64_t volatile uTlbPhysRev;
358
359	/* Statistics: */
360
361	/** TLB hits (VBOX_WITH_STATISTICS only). */
362	uint64_t cTlbHits;
363	/** TLB misses. */
364	uint32_t cTlbMisses;
365	/** Slow read path. */
366	uint32_t cTlbSlowReadPath;
367	#if 0
368	/** TLB misses because of tag mismatch. */
369	uint32_t cTlbMissesTag;
370	/** TLB misses because of virtual access violation. */
371	uint32_t cTlbMissesVirtAccess;
372	/** TLB misses because of dirty bit. */
373	uint32_t cTlbMissesDirty;
374	/** TLB misses because of MMIO */
375	uint32_t cTlbMissesMmio;
376	/** TLB misses because of write access handlers. */
377	uint32_t cTlbMissesWriteHandler;
378	/** TLB misses because no r3(/r0) mapping. */
379	uint32_t cTlbMissesMapping;
380	#endif
381	/** Alignment padding. */
382	uint32_t au32Padding[3+5];
383	} IEMTLB;
384	AssertCompileSizeAlignment(IEMTLB, 64);
385	/** IEMTLB::uTlbRevision increment. */
386	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
387	/** IEMTLB::uTlbRevision mask. */
388	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
389	/** IEMTLB::uTlbPhysRev increment.
390	* @sa IEMTLBE_F_PHYS_REV */
391	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
392	/**
393	* Calculates the TLB tag for a virtual address.
394	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
395	* @param a_pTlb The TLB.
396	* @param a_GCPtr The virtual address.
397	*/
398	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
399	/**
400	* Calculates the TLB tag for a virtual address but without TLB revision.
401	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
402	* @param a_GCPtr The virtual address.
403	*/
404	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
405	/**
406	* Converts a TLB tag value into a TLB index.
407	* @returns Index into IEMTLB::aEntries.
408	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
409	*/
410	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
411	/**
412	* Converts a TLB tag value into a TLB index.
413	* @returns Index into IEMTLB::aEntries.
414	* @param a_pTlb The TLB.
415	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
416	*/
417	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
418
419
420	/**
421	* The per-CPU IEM state.
422	*/
423	typedef struct IEMCPU
424	{
425	/** Info status code that needs to be propagated to the IEM caller.
426	* This cannot be passed internally, as it would complicate all success
427	* checks within the interpreter making the code larger and almost impossible
428	* to get right. Instead, we'll store status codes to pass on here. Each
429	* source of these codes will perform appropriate sanity checks. */
430	int32_t rcPassUp; /* 0x00 */
431
432	/** The current CPU execution mode (CS). */
433	IEMMODE enmCpuMode; /* 0x04 */
434	/** The CPL. */
435	uint8_t uCpl; /* 0x05 */
436
437	/** Whether to bypass access handlers or not. */
438	bool fBypassHandlers; /* 0x06 */
439	/** Whether to disregard the lock prefix (implied or not). */
440	bool fDisregardLock; /* 0x07 */
441
442	/** @name Decoder state.
443	* @{ */
444	#ifdef IEM_WITH_CODE_TLB
445	/** The offset of the next instruction byte. */
446	uint32_t offInstrNextByte; /* 0x08 */
447	/** The number of bytes available at pbInstrBuf for the current instruction.
448	* This takes the max opcode length into account so that doesn't need to be
449	* checked separately. */
450	uint32_t cbInstrBuf; /* 0x0c */
451	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
452	* This can be NULL if the page isn't mappable for some reason, in which
453	* case we'll do fallback stuff.
454	*
455	* If we're executing an instruction from a user specified buffer,
456	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
457	* aligned pointer but pointer to the user data.
458	*
459	* For instructions crossing pages, this will start on the first page and be
460	* advanced to the next page by the time we've decoded the instruction. This
461	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
462	*/
463	uint8_t const pbInstrBuf; / 0x10 */
464	# if ARCH_BITS == 32
465	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
466	# endif
467	/** The program counter corresponding to pbInstrBuf.
468	* This is set to a non-canonical address when we need to invalidate it. */
469	uint64_t uInstrBufPc; /* 0x18 */
470	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
471	* This takes the CS segment limit into account. */
472	uint16_t cbInstrBufTotal; /* 0x20 */
473	/** Offset into pbInstrBuf of the first byte of the current instruction.
474	* Can be negative to efficiently handle cross page instructions. */
475	int16_t offCurInstrStart; /* 0x22 */
476
477	/** The prefix mask (IEM_OP_PRF_XXX). */
478	uint32_t fPrefixes; /* 0x24 */
479	/** The extra REX ModR/M register field bit (REX.R << 3). */
480	uint8_t uRexReg; /* 0x28 */
481	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
482	* (REX.B << 3). */
483	uint8_t uRexB; /* 0x29 */
484	/** The extra REX SIB index field bit (REX.X << 3). */
485	uint8_t uRexIndex; /* 0x2a */
486
487	/** The effective segment register (X86_SREG_XXX). */
488	uint8_t iEffSeg; /* 0x2b */
489
490	/** The offset of the ModR/M byte relative to the start of the instruction. */
491	uint8_t offModRm; /* 0x2c */
492	#else
493	/** The size of what has currently been fetched into abOpcode. */
494	uint8_t cbOpcode; /* 0x08 */
495	/** The current offset into abOpcode. */
496	uint8_t offOpcode; /* 0x09 */
497	/** The offset of the ModR/M byte relative to the start of the instruction. */
498	uint8_t offModRm; /* 0x0a */
499
500	/** The effective segment register (X86_SREG_XXX). */
501	uint8_t iEffSeg; /* 0x0b */
502
503	/** The prefix mask (IEM_OP_PRF_XXX). */
504	uint32_t fPrefixes; /* 0x0c */
505	/** The extra REX ModR/M register field bit (REX.R << 3). */
506	uint8_t uRexReg; /* 0x10 */
507	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
508	* (REX.B << 3). */
509	uint8_t uRexB; /* 0x11 */
510	/** The extra REX SIB index field bit (REX.X << 3). */
511	uint8_t uRexIndex; /* 0x12 */
512
513	#endif
514
515	/** The effective operand mode. */
516	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
517	/** The default addressing mode. */
518	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
519	/** The effective addressing mode. */
520	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
521	/** The default operand mode. */
522	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
523
524	/** Prefix index (VEX.pp) for two byte and three byte tables. */
525	uint8_t idxPrefix; /* 0x31, 0x17 */
526	/** 3rd VEX/EVEX/XOP register.
527	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
528	uint8_t uVex3rdReg; /* 0x32, 0x18 */
529	/** The VEX/EVEX/XOP length field. */
530	uint8_t uVexLength; /* 0x33, 0x19 */
531	/** Additional EVEX stuff. */
532	uint8_t fEvexStuff; /* 0x34, 0x1a */
533
534	/** Explicit alignment padding. */
535	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
536	/** The FPU opcode (FOP). */
537	uint16_t uFpuOpcode; /* 0x36, 0x1c */
538	#ifndef IEM_WITH_CODE_TLB
539	/** Explicit alignment padding. */
540	uint8_t abAlignment2b[2]; /* 0x1e */
541	#endif
542
543	/** The opcode bytes. */
544	uint8_t abOpcode[15]; /* 0x48, 0x20 */
545	/** Explicit alignment padding. */
546	#ifdef IEM_WITH_CODE_TLB
547	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
548	#else
549	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
550	#endif
551	/** @} */
552
553
554	/** The flags of the current exception / interrupt. */
555	uint32_t fCurXcpt; /* 0x48, 0x48 */
556	/** The current exception / interrupt. */
557	uint8_t uCurXcpt;
558	/** Exception / interrupt recursion depth. */
559	int8_t cXcptRecursions;
560
561	/** The number of active guest memory mappings. */
562	uint8_t cActiveMappings;
563	/** The next unused mapping index. */
564	uint8_t iNextMapping;
565	/** Records for tracking guest memory mappings. */
566	struct
567	{
568	/** The address of the mapped bytes. */
569	void *pv;
570	/** The access flags (IEM_ACCESS_XXX).
571	* IEM_ACCESS_INVALID if the entry is unused. */
572	uint32_t fAccess;
573	#if HC_ARCH_BITS == 64
574	uint32_t u32Alignment4; /*< Alignment padding. /
575	#endif
576	} aMemMappings[3];
577
578	/** Locking records for the mapped memory. */
579	union
580	{
581	PGMPAGEMAPLOCK Lock;
582	uint64_t au64Padding[2];
583	} aMemMappingLocks[3];
584
585	/** Bounce buffer info.
586	* This runs in parallel to aMemMappings. */
587	struct
588	{
589	/** The physical address of the first byte. */
590	RTGCPHYS GCPhysFirst;
591	/** The physical address of the second page. */
592	RTGCPHYS GCPhysSecond;
593	/** The number of bytes in the first page. */
594	uint16_t cbFirst;
595	/** The number of bytes in the second page. */
596	uint16_t cbSecond;
597	/** Whether it's unassigned memory. */
598	bool fUnassigned;
599	/** Explicit alignment padding. */
600	bool afAlignment5[3];
601	} aMemBbMappings[3];
602
603	/** Bounce buffer storage.
604	* This runs in parallel to aMemMappings and aMemBbMappings. */
605	struct
606	{
607	uint8_t ab[512];
608	} aBounceBuffers[3];
609
610
611	/** Pointer set jump buffer - ring-3 context. */
612	R3PTRTYPE(jmp_buf *) pJmpBufR3;
613	/** Pointer set jump buffer - ring-0 context. */
614	R0PTRTYPE(jmp_buf *) pJmpBufR0;
615
616	/** @todo Should move this near @a fCurXcpt later. */
617	/** The CR2 for the current exception / interrupt. */
618	uint64_t uCurXcptCr2;
619	/** The error code for the current exception / interrupt. */
620	uint32_t uCurXcptErr;
621
622	/** @name Statistics
623	* @{ */
624	/** The number of instructions we've executed. */
625	uint32_t cInstructions;
626	/** The number of potential exits. */
627	uint32_t cPotentialExits;
628	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
629	* This may contain uncommitted writes. */
630	uint32_t cbWritten;
631	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
632	uint32_t cRetInstrNotImplemented;
633	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
634	uint32_t cRetAspectNotImplemented;
635	/** Counts informational statuses returned (other than VINF_SUCCESS). */
636	uint32_t cRetInfStatuses;
637	/** Counts other error statuses returned. */
638	uint32_t cRetErrStatuses;
639	/** Number of times rcPassUp has been used. */
640	uint32_t cRetPassUpStatus;
641	/** Number of times RZ left with instruction commit pending for ring-3. */
642	uint32_t cPendingCommit;
643	/** Number of long jumps. */
644	uint32_t cLongJumps;
645	/** @} */
646
647	/** @name Target CPU information.
648	* @{ */
649	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
650	/** The target CPU. */
651	uint8_t uTargetCpu;
652	#else
653	uint8_t bTargetCpuPadding;
654	#endif
655	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
656	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values. This is for instance used for the
657	* BSF & BSR instructions where AMD and Intel CPUs produce different EFLAGS. */
658	uint8_t idxTargetCpuEflFlavour;
659
660	/** The CPU vendor. */
661	CPUMCPUVENDOR enmCpuVendor;
662	/** @} */
663
664	/** @name Host CPU information.
665	* @{ */
666	/** The CPU vendor. */
667	CPUMCPUVENDOR enmHostCpuVendor;
668	/** @} */
669
670	/** Counts RDMSR \#GP(0) LogRel(). */
671	uint8_t cLogRelRdMsr;
672	/** Counts WRMSR \#GP(0) LogRel(). */
673	uint8_t cLogRelWrMsr;
674	/** Alignment padding. */
675	uint8_t abAlignment8[50];
676
677	/** Data TLB.
678	* @remarks Must be 64-byte aligned. */
679	IEMTLB DataTlb;
680	/** Instruction TLB.
681	* @remarks Must be 64-byte aligned. */
682	IEMTLB CodeTlb;
683
684	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
685	/** Instruction statistics for ring-0/raw-mode. */
686	IEMINSTRSTATS StatsRZ;
687	/** Instruction statistics for ring-3. */
688	IEMINSTRSTATS StatsR3;
689	#endif
690	} IEMCPU;
691	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
692	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
693	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
694	/** Pointer to the per-CPU IEM state. */
695	typedef IEMCPU *PIEMCPU;
696	/** Pointer to the const per-CPU IEM state. */
697	typedef IEMCPU const *PCIEMCPU;
698
699
700	/** @def IEM_GET_CTX
701	* Gets the guest CPU context for the calling EMT.
702	* @returns PCPUMCTX
703	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
704	*/
705	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
706
707	/** @def IEM_CTX_ASSERT
708	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
709	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
710	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
711	*/
712	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
713	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
714	(a_fExtrnMbz)))
715
716	/** @def IEM_CTX_IMPORT_RET
717	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
718	*
719	* Will call the keep to import the bits as needed.
720	*
721	* Returns on import failure.
722	*
723	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
724	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
725	*/
726	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
727	do { \
728	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
729	{ /* likely */ } \
730	else \
731	{ \
732	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
733	AssertRCReturn(rcCtxImport, rcCtxImport); \
734	} \
735	} while (0)
736
737	/** @def IEM_CTX_IMPORT_NORET
738	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
739	*
740	* Will call the keep to import the bits as needed.
741	*
742	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
743	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
744	*/
745	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
746	do { \
747	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
748	{ /* likely */ } \
749	else \
750	{ \
751	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
752	AssertLogRelRC(rcCtxImport); \
753	} \
754	} while (0)
755
756	/** @def IEM_CTX_IMPORT_JMP
757	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
758	*
759	* Will call the keep to import the bits as needed.
760	*
761	* Jumps on import failure.
762	*
763	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
764	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
765	*/
766	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
767	do { \
768	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
769	{ /* likely */ } \
770	else \
771	{ \
772	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
773	AssertRCStmt(rcCtxImport, longjmp(*pVCpu->iem.s.CTX_SUFF(pJmpBuf), rcCtxImport)); \
774	} \
775	} while (0)
776
777
778
779	/** @def IEM_GET_TARGET_CPU
780	* Gets the current IEMTARGETCPU value.
781	* @returns IEMTARGETCPU value.
782	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
783	*/
784	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
785	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
786	#else
787	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
788	#endif
789
790	/** @def IEM_GET_INSTR_LEN
791	* Gets the instruction length. */
792	#ifdef IEM_WITH_CODE_TLB
793	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
794	#else
795	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
796	#endif
797
798
799	/**
800	* Shared per-VM IEM data.
801	*/
802	typedef struct IEM
803	{
804	/** The VMX APIC-access page handler type. */
805	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
806	} IEM;
807
808
809
810	/** @name IEM_ACCESS_XXX - Access details.
811	* @{ */
812	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
813	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
814	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
815	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
816	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
817	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
818	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
819	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
820	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
821	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
822	/** The writes are partial, so if initialize the bounce buffer with the
823	* orignal RAM content. */
824	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
825	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
826	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
827	/** Bounce buffer with ring-3 write pending, first page. */
828	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
829	/** Bounce buffer with ring-3 write pending, second page. */
830	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
831	/** Not locked, accessed via the TLB. */
832	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
833	/** Valid bit mask. */
834	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
835	/** Shift count for the TLB flags (upper word). */
836	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
837
838	/** Read+write data alias. */
839	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
840	/** Write data alias. */
841	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
842	/** Read data alias. */
843	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
844	/** Instruction fetch alias. */
845	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
846	/** Stack write alias. */
847	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
848	/** Stack read alias. */
849	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
850	/** Stack read+write alias. */
851	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
852	/** Read system table alias. */
853	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
854	/** Read+write system table alias. */
855	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
856	/** @} */
857
858	/** @name Prefix constants (IEMCPU::fPrefixes)
859	* @{ */
860	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
861	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
862	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
863	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
864	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
865	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
866	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
867
868	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
869	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
870	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
871
872	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
873	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
874	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
875
876	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
877	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
878	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
879	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
880	/** Mask with all the REX prefix flags.
881	* This is generally for use when needing to undo the REX prefixes when they
882	* are followed legacy prefixes and therefore does not immediately preceed
883	* the first opcode byte.
884	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
885	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
886
887	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
888	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
889	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
890	/** @} */
891
892	/** @name IEMOPFORM_XXX - Opcode forms
893	* @note These are ORed together with IEMOPHINT_XXX.
894	* @{ */
895	/** ModR/M: reg, r/m */
896	#define IEMOPFORM_RM 0
897	/** ModR/M: reg, r/m (register) */
898	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
899	/** ModR/M: reg, r/m (memory) */
900	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
901	/** ModR/M: r/m, reg */
902	#define IEMOPFORM_MR 1
903	/** ModR/M: r/m (register), reg */
904	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
905	/** ModR/M: r/m (memory), reg */
906	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
907	/** ModR/M: r/m only */
908	#define IEMOPFORM_M 2
909	/** ModR/M: r/m only (register). */
910	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
911	/** ModR/M: r/m only (memory). */
912	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
913	/** ModR/M: reg only */
914	#define IEMOPFORM_R 3
915
916	/** VEX+ModR/M: reg, r/m */
917	#define IEMOPFORM_VEX_RM 4
918	/** VEX+ModR/M: reg, r/m (register) */
919	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
920	/** VEX+ModR/M: reg, r/m (memory) */
921	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
922	/** VEX+ModR/M: r/m, reg */
923	#define IEMOPFORM_VEX_MR 5
924	/** VEX+ModR/M: r/m (register), reg */
925	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
926	/** VEX+ModR/M: r/m (memory), reg */
927	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
928	/** VEX+ModR/M: r/m only */
929	#define IEMOPFORM_VEX_M 6
930	/** VEX+ModR/M: r/m only (register). */
931	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
932	/** VEX+ModR/M: r/m only (memory). */
933	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
934	/** VEX+ModR/M: reg only */
935	#define IEMOPFORM_VEX_R 7
936	/** VEX+ModR/M: reg, vvvv, r/m */
937	#define IEMOPFORM_VEX_RVM 8
938	/** VEX+ModR/M: reg, vvvv, r/m (register). */
939	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
940	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
941	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
942	/** VEX+ModR/M: r/m, vvvv, reg */
943	#define IEMOPFORM_VEX_MVR 9
944	/** VEX+ModR/M: r/m, vvvv, reg (register) */
945	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
946	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
947	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
948
949	/** Fixed register instruction, no R/M. */
950	#define IEMOPFORM_FIXED 16
951
952	/** The r/m is a register. */
953	#define IEMOPFORM_MOD3 RT_BIT_32(8)
954	/** The r/m is a memory access. */
955	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
956	/** @} */
957
958	/** @name IEMOPHINT_XXX - Additional Opcode Hints
959	* @note These are ORed together with IEMOPFORM_XXX.
960	* @{ */
961	/** Ignores the operand size prefix (66h). */
962	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
963	/** Ignores REX.W (aka WIG). */
964	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
965	/** Both the operand size prefixes (66h + REX.W) are ignored. */
966	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
967	/** Allowed with the lock prefix. */
968	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
969	/** The VEX.L value is ignored (aka LIG). */
970	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
971	/** The VEX.L value must be zero (i.e. 128-bit width only). */
972	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
973
974	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
975	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
976	/** @} */
977
978	/**
979	* Possible hardware task switch sources.
980	*/
981	typedef enum IEMTASKSWITCH
982	{
983	/** Task switch caused by an interrupt/exception. */
984	IEMTASKSWITCH_INT_XCPT = 1,
985	/** Task switch caused by a far CALL. */
986	IEMTASKSWITCH_CALL,
987	/** Task switch caused by a far JMP. */
988	IEMTASKSWITCH_JUMP,
989	/** Task switch caused by an IRET. */
990	IEMTASKSWITCH_IRET
991	} IEMTASKSWITCH;
992	AssertCompileSize(IEMTASKSWITCH, 4);
993
994	/**
995	* Possible CrX load (write) sources.
996	*/
997	typedef enum IEMACCESSCRX
998	{
999	/** CrX access caused by 'mov crX' instruction. */
1000	IEMACCESSCRX_MOV_CRX,
1001	/** CrX (CR0) write caused by 'lmsw' instruction. */
1002	IEMACCESSCRX_LMSW,
1003	/** CrX (CR0) write caused by 'clts' instruction. */
1004	IEMACCESSCRX_CLTS,
1005	/** CrX (CR0) read caused by 'smsw' instruction. */
1006	IEMACCESSCRX_SMSW
1007	} IEMACCESSCRX;
1008
1009	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1010	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1011	*
1012	* These flags provide further context to SLAT page-walk failures that could not be
1013	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1014	*
1015	* @{
1016	*/
1017	/** Translating a nested-guest linear address failed accessing a nested-guest
1018	* physical address. */
1019	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1020	/** Translating a nested-guest linear address failed accessing a
1021	* paging-structure entry or updating accessed/dirty bits. */
1022	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1023	/** @} */
1024
1025	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1026	# ifndef IN_RING3
1027	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1028	# endif
1029	#endif
1030
1031	/**
1032	* Indicates to the verifier that the given flag set is undefined.
1033	*
1034	* Can be invoked again to add more flags.
1035	*
1036	* This is a NOOP if the verifier isn't compiled in.
1037	*
1038	* @note We're temporarily keeping this until code is converted to new
1039	* disassembler style opcode handling.
1040	*/
1041	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1042
1043
1044	/** @def IEM_DECL_IMPL_TYPE
1045	* For typedef'ing an instruction implementation function.
1046	*
1047	* @param a_RetType The return type.
1048	* @param a_Name The name of the type.
1049	* @param a_ArgList The argument list enclosed in parentheses.
1050	*/
1051
1052	/** @def IEM_DECL_IMPL_DEF
1053	* For defining an instruction implementation function.
1054	*
1055	* @param a_RetType The return type.
1056	* @param a_Name The name of the type.
1057	* @param a_ArgList The argument list enclosed in parentheses.
1058	*/
1059
1060	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1061	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1062	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1063	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1064	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1065	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1066	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1067
1068	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1069	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1070	a_RetType (__fastcall a_Name) a_ArgList
1071	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1072	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1073	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1074	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1075
1076	#elif __cplusplus >= 201700 /* P0012R1 support */
1077	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1078	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1079	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1080	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1081	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1082	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1083
1084	#else
1085	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1086	a_RetType (VBOXCALL a_Name) a_ArgList
1087	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1088	a_RetType VBOXCALL a_Name a_ArgList
1089	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1090	a_RetType VBOXCALL a_Name a_ArgList
1091
1092	#endif
1093
1094	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1095	RT_C_DECLS_BEGIN
1096	extern uint8_t const g_afParity[256];
1097	RT_C_DECLS_END
1098
1099
1100	/** @name Arithmetic assignment operations on bytes (binary).
1101	* @{ */
1102	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1103	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1104	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1105	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1106	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1107	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1108	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1109	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1110	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1111	/** @} */
1112
1113	/** @name Arithmetic assignment operations on words (binary).
1114	* @{ */
1115	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1116	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1117	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1118	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1119	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1120	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1121	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1122	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1123	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1124	/** @} */
1125
1126	/** @name Arithmetic assignment operations on double words (binary).
1127	* @{ */
1128	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1129	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1130	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1131	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1132	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1133	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1134	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1135	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1136	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1137	/** @} */
1138
1139	/** @name Arithmetic assignment operations on quad words (binary).
1140	* @{ */
1141	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1142	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1143	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1144	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1145	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1146	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1147	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1148	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1149	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1150	/** @} */
1151
1152	/** @name Compare operations (thrown in with the binary ops).
1153	* @{ */
1154	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1155	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1156	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1157	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1158	/** @} */
1159
1160	/** @name Test operations (thrown in with the binary ops).
1161	* @{ */
1162	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1163	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1164	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1165	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1166	/** @} */
1167
1168	/** @name Bit operations operations (thrown in with the binary ops).
1169	* @{ */
1170	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1171	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1172	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1173	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1174	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1175	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1176	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1177	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1178	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1179	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1180	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1181	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1182	/** @} */
1183
1184	/** @name Exchange memory with register operations.
1185	* @{ */
1186	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1187	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1188	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1189	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1190	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1191	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1192	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1193	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1194	/** @} */
1195
1196	/** @name Exchange and add operations.
1197	* @{ */
1198	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1199	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1200	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1201	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1202	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1203	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1204	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1205	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1206	/** @} */
1207
1208	/** @name Compare and exchange.
1209	* @{ */
1210	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1211	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1212	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1213	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1214	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1215	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1216	#if ARCH_BITS == 32
1217	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1218	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1219	#else
1220	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1221	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1222	#endif
1223	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1224	uint32_t *pEFlags));
1225	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1226	uint32_t *pEFlags));
1227	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1228	uint32_t *pEFlags));
1229	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1230	uint32_t *pEFlags));
1231	#ifndef RT_ARCH_ARM64
1232	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1233	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1234	#endif
1235	/** @} */
1236
1237	/** @name Memory ordering
1238	* @{ */
1239	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1240	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1241	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1242	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1243	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1244	#ifndef RT_ARCH_ARM64
1245	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1246	#endif
1247	/** @} */
1248
1249	/** @name Double precision shifts
1250	* @{ */
1251	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1252	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1253	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1254	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1255	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1256	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1257	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1258	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1259	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1260	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1261	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1262	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1263	/** @} */
1264
1265
1266	/** @name Bit search operations (thrown in with the binary ops).
1267	* @{ */
1268	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1269	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1270	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1271	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1272	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1273	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1274	/** @} */
1275
1276	/** @name Signed multiplication operations (thrown in with the binary ops).
1277	* @{ */
1278	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1279	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1280	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1281	/** @} */
1282
1283	/** @name Arithmetic assignment operations on bytes (unary).
1284	* @{ */
1285	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1286	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1287	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1288	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1289	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1290	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1291	/** @} */
1292
1293	/** @name Arithmetic assignment operations on words (unary).
1294	* @{ */
1295	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1296	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1297	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1298	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1299	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1300	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1301	/** @} */
1302
1303	/** @name Arithmetic assignment operations on double words (unary).
1304	* @{ */
1305	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1306	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1307	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1308	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1309	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1310	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1311	/** @} */
1312
1313	/** @name Arithmetic assignment operations on quad words (unary).
1314	* @{ */
1315	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1316	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1317	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1318	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1319	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1320	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1321	/** @} */
1322
1323
1324	/** @name Shift operations on bytes (Group 2).
1325	* @{ */
1326	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1327	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1328	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1329	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1330	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1331	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1332	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1333	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1334	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1335	/** @} */
1336
1337	/** @name Shift operations on words (Group 2).
1338	* @{ */
1339	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1340	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1341	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1342	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1343	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1344	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1345	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1346	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1347	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1348	/** @} */
1349
1350	/** @name Shift operations on double words (Group 2).
1351	* @{ */
1352	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1353	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1354	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1355	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1356	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1357	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1358	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1359	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1360	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1361	/** @} */
1362
1363	/** @name Shift operations on words (Group 2).
1364	* @{ */
1365	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1366	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1367	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1368	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1369	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1370	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1371	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1372	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1373	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1374	/** @} */
1375
1376	/** @name Multiplication and division operations.
1377	* @{ */
1378	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1379	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1380	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1381	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1382	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1383	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1384
1385	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1386	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1387	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1388	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1389	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1390	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1391
1392	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1393	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1394	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1395	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1396	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1397	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1398
1399	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1400	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1401	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1402	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1403	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1404	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1405	/** @} */
1406
1407	/** @name Byte Swap.
1408	* @{ */
1409	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1410	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1411	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1412	/** @} */
1413
1414	/** @name Misc.
1415	* @{ */
1416	FNIEMAIMPLBINU16 iemAImpl_arpl;
1417	/** @} */
1418
1419
1420	/** @name FPU operations taking a 32-bit float argument
1421	* @{ */
1422	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1423	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1424	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1425
1426	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1427	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1428	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1429
1430	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1431	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1432	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1433	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1434	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1435	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1436	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1437
1438	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1439	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1440	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1441	/** @} */
1442
1443	/** @name FPU operations taking a 64-bit float argument
1444	* @{ */
1445	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1446	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1447	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
1448
1449	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1450	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1451	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1452
1453	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
1454	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1455	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1456	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1457	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1458	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1459	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1460
1461	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1462	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1463	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1464	/** @} */
1465
1466	/** @name FPU operations taking a 80-bit float argument
1467	* @{ */
1468	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1469	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1470	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1471	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1472	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1473	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1474	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1475	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1476	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1477	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1478	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1479	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1480
1481	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
1482	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
1483	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
1484
1485	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1486	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1487	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1488	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1489	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1490
1491	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1492	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1493	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1494	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1495	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1496
1497	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1498	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1499	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1500	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1501	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
1502	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1503	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1504	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
1505	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
1506
1507	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1508	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1509	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1510	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1511
1512	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1513	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1514	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1515	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1516	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1517	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1518	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1519	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1520	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1521
1522	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1523	PCRTFLOAT80U pr80Val));
1524	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1525	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
1526	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1527	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
1528
1529	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1530	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1531	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1532
1533	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
1534	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1535	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
1536
1537	/** @} */
1538
1539	/** @name FPU operations taking a 16-bit signed integer argument
1540	* @{ */
1541	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1542	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1543	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1544	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1545	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
1546	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
1547
1548	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1549	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1550	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1551	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1552	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1553	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1554
1555	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1556	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1557	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
1558	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
1559
1560	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1561	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
1562	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
1563	/** @} */
1564
1565	/** @name FPU operations taking a 32-bit signed integer argument
1566	* @{ */
1567	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1568	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1569	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1570	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1571	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
1572	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
1573
1574	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1575	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1576	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1577	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1578	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1579	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1580
1581	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1582	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1583	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
1584	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
1585
1586	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1587	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
1588	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
1589	/** @} */
1590
1591	/** @name FPU operations taking a 64-bit signed integer argument
1592	* @{ */
1593	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1594	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
1595	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
1596
1597	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1598	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
1599	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
1600	/** @} */
1601
1602
1603	/** Temporary type representing a 256-bit vector register. */
1604	typedef struct { uint64_t au64[4]; } IEMVMM256;
1605	/** Temporary type pointing to a 256-bit vector register. */
1606	typedef IEMVMM256 *PIEMVMM256;
1607	/** Temporary type pointing to a const 256-bit vector register. */
1608	typedef IEMVMM256 *PCIEMVMM256;
1609
1610
1611	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1612	* @{ */
1613	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1614	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1615	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1616	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1617	FNIEMAIMPLMEDIAF2U64 iemAImpl_pxor_u64, iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1618	FNIEMAIMPLMEDIAF2U128 iemAImpl_pxor_u128, iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1619	/** @} */
1620
1621	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1622	* @{ */
1623	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src));
1624	typedef FNIEMAIMPLMEDIAF1L1U64 *PFNIEMAIMPLMEDIAF1L1U64;
1625	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src));
1626	typedef FNIEMAIMPLMEDIAF1L1U128 *PFNIEMAIMPLMEDIAF1L1U128;
1627	FNIEMAIMPLMEDIAF1L1U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1628	FNIEMAIMPLMEDIAF1L1U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1629	/** @} */
1630
1631	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
1632	* @{ */
1633	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1634	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF1H1U64;
1635	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1636	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF1H1U128;
1637	FNIEMAIMPLMEDIAF1H1U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
1638	FNIEMAIMPLMEDIAF1H1U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
1639	/** @} */
1640
1641	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
1642	* @{ */
1643	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUF,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst,
1644	PCRTUINT128U pu128Src, uint8_t bEvil));
1645	typedef FNIEMAIMPLMEDIAPSHUF *PFNIEMAIMPLMEDIAPSHUF;
1646	FNIEMAIMPLMEDIAPSHUF iemAImpl_pshufhw, iemAImpl_pshuflw, iemAImpl_pshufd;
1647	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil));
1648	/** @} */
1649
1650	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
1651	* @{ */
1652	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1653	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src));
1654	/** @} */
1655
1656	/** @name Media (SSE/MMX/AVX) operation: Sort this later
1657	* @{ */
1658	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1659	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1660	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc));
1661
1662	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1663	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1664	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1665	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1666
1667	/** @} */
1668
1669
1670	/** @name Function tables.
1671	* @{
1672	*/
1673
1674	/**
1675	* Function table for a binary operator providing implementation based on
1676	* operand size.
1677	*/
1678	typedef struct IEMOPBINSIZES
1679	{
1680	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
1681	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
1682	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
1683	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
1684	} IEMOPBINSIZES;
1685	/** Pointer to a binary operator function table. */
1686	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
1687
1688
1689	/**
1690	* Function table for a unary operator providing implementation based on
1691	* operand size.
1692	*/
1693	typedef struct IEMOPUNARYSIZES
1694	{
1695	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
1696	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
1697	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
1698	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
1699	} IEMOPUNARYSIZES;
1700	/** Pointer to a unary operator function table. */
1701	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
1702
1703
1704	/**
1705	* Function table for a shift operator providing implementation based on
1706	* operand size.
1707	*/
1708	typedef struct IEMOPSHIFTSIZES
1709	{
1710	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
1711	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
1712	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
1713	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
1714	} IEMOPSHIFTSIZES;
1715	/** Pointer to a shift operator function table. */
1716	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
1717
1718
1719	/**
1720	* Function table for a multiplication or division operation.
1721	*/
1722	typedef struct IEMOPMULDIVSIZES
1723	{
1724	PFNIEMAIMPLMULDIVU8 pfnU8;
1725	PFNIEMAIMPLMULDIVU16 pfnU16;
1726	PFNIEMAIMPLMULDIVU32 pfnU32;
1727	PFNIEMAIMPLMULDIVU64 pfnU64;
1728	} IEMOPMULDIVSIZES;
1729	/** Pointer to a multiplication or division operation function table. */
1730	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
1731
1732
1733	/**
1734	* Function table for a double precision shift operator providing implementation
1735	* based on operand size.
1736	*/
1737	typedef struct IEMOPSHIFTDBLSIZES
1738	{
1739	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
1740	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
1741	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
1742	} IEMOPSHIFTDBLSIZES;
1743	/** Pointer to a double precision shift function table. */
1744	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
1745
1746
1747	/**
1748	* Function table for media instruction taking two full sized media registers,
1749	* optionally the 2nd being a memory reference (only modifying the first op.)
1750	*/
1751	typedef struct IEMOPMEDIAF2
1752	{
1753	PFNIEMAIMPLMEDIAF2U64 pfnU64;
1754	PFNIEMAIMPLMEDIAF2U128 pfnU128;
1755	} IEMOPMEDIAF2;
1756	/** Pointer to a media operation function table for full sized ops. */
1757	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
1758
1759	/**
1760	* Function table for media instruction taking taking one full and one lower
1761	* half media register.
1762	*/
1763	typedef struct IEMOPMEDIAF1L1
1764	{
1765	PFNIEMAIMPLMEDIAF1L1U64 pfnU64;
1766	PFNIEMAIMPLMEDIAF1L1U128 pfnU128;
1767	} IEMOPMEDIAF1L1;
1768	/** Pointer to a media operation function table for lowhalf+lowhalf -> full. */
1769	typedef IEMOPMEDIAF1L1 const *PCIEMOPMEDIAF1L1;
1770
1771	/**
1772	* Function table for media instruction taking taking one full and one high half
1773	* media register.
1774	*/
1775	typedef struct IEMOPMEDIAF1H1
1776	{
1777	PFNIEMAIMPLMEDIAF1H1U64 pfnU64;
1778	PFNIEMAIMPLMEDIAF1H1U128 pfnU128;
1779	} IEMOPMEDIAF1H1;
1780	/** Pointer to a media operation function table for hihalf+hihalf -> full. */
1781	typedef IEMOPMEDIAF1H1 const *PCIEMOPMEDIAF1H1;
1782
1783
1784	/** @} */
1785
1786
1787	/** @name C instruction implementations for anything slightly complicated.
1788	* @{ */
1789
1790	/**
1791	* For typedef'ing or declaring a C instruction implementation function taking
1792	* no extra arguments.
1793	*
1794	* @param a_Name The name of the type.
1795	*/
1796	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
1797	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
1798	/**
1799	* For defining a C instruction implementation function taking no extra
1800	* arguments.
1801	*
1802	* @param a_Name The name of the function
1803	*/
1804	# define IEM_CIMPL_DEF_0(a_Name) \
1805	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
1806	/**
1807	* Prototype version of IEM_CIMPL_DEF_0.
1808	*/
1809	# define IEM_CIMPL_PROTO_0(a_Name) \
1810	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
1811	/**
1812	* For calling a C instruction implementation function taking no extra
1813	* arguments.
1814	*
1815	* This special call macro adds default arguments to the call and allow us to
1816	* change these later.
1817	*
1818	* @param a_fn The name of the function.
1819	*/
1820	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
1821
1822	/**
1823	* For typedef'ing or declaring a C instruction implementation function taking
1824	* one extra argument.
1825	*
1826	* @param a_Name The name of the type.
1827	* @param a_Type0 The argument type.
1828	* @param a_Arg0 The argument name.
1829	*/
1830	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
1831	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1832	/**
1833	* For defining a C instruction implementation function taking one extra
1834	* argument.
1835	*
1836	* @param a_Name The name of the function
1837	* @param a_Type0 The argument type.
1838	* @param a_Arg0 The argument name.
1839	*/
1840	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
1841	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1842	/**
1843	* Prototype version of IEM_CIMPL_DEF_1.
1844	*/
1845	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
1846	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1847	/**
1848	* For calling a C instruction implementation function taking one extra
1849	* argument.
1850	*
1851	* This special call macro adds default arguments to the call and allow us to
1852	* change these later.
1853	*
1854	* @param a_fn The name of the function.
1855	* @param a0 The name of the 1st argument.
1856	*/
1857	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
1858
1859	/**
1860	* For typedef'ing or declaring a C instruction implementation function taking
1861	* two extra arguments.
1862	*
1863	* @param a_Name The name of the type.
1864	* @param a_Type0 The type of the 1st argument
1865	* @param a_Arg0 The name of the 1st argument.
1866	* @param a_Type1 The type of the 2nd argument.
1867	* @param a_Arg1 The name of the 2nd argument.
1868	*/
1869	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1870	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1871	/**
1872	* For defining a C instruction implementation function taking two extra
1873	* arguments.
1874	*
1875	* @param a_Name The name of the function.
1876	* @param a_Type0 The type of the 1st argument
1877	* @param a_Arg0 The name of the 1st argument.
1878	* @param a_Type1 The type of the 2nd argument.
1879	* @param a_Arg1 The name of the 2nd argument.
1880	*/
1881	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1882	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1883	/**
1884	* Prototype version of IEM_CIMPL_DEF_2.
1885	*/
1886	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1887	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1888	/**
1889	* For calling a C instruction implementation function taking two extra
1890	* arguments.
1891	*
1892	* This special call macro adds default arguments to the call and allow us to
1893	* change these later.
1894	*
1895	* @param a_fn The name of the function.
1896	* @param a0 The name of the 1st argument.
1897	* @param a1 The name of the 2nd argument.
1898	*/
1899	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
1900
1901	/**
1902	* For typedef'ing or declaring a C instruction implementation function taking
1903	* three extra arguments.
1904	*
1905	* @param a_Name The name of the type.
1906	* @param a_Type0 The type of the 1st argument
1907	* @param a_Arg0 The name of the 1st argument.
1908	* @param a_Type1 The type of the 2nd argument.
1909	* @param a_Arg1 The name of the 2nd argument.
1910	* @param a_Type2 The type of the 3rd argument.
1911	* @param a_Arg2 The name of the 3rd argument.
1912	*/
1913	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1914	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1915	/**
1916	* For defining a C instruction implementation function taking three extra
1917	* arguments.
1918	*
1919	* @param a_Name The name of the function.
1920	* @param a_Type0 The type of the 1st argument
1921	* @param a_Arg0 The name of the 1st argument.
1922	* @param a_Type1 The type of the 2nd argument.
1923	* @param a_Arg1 The name of the 2nd argument.
1924	* @param a_Type2 The type of the 3rd argument.
1925	* @param a_Arg2 The name of the 3rd argument.
1926	*/
1927	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1928	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1929	/**
1930	* Prototype version of IEM_CIMPL_DEF_3.
1931	*/
1932	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
1933	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
1934	/**
1935	* For calling a C instruction implementation function taking three extra
1936	* arguments.
1937	*
1938	* This special call macro adds default arguments to the call and allow us to
1939	* change these later.
1940	*
1941	* @param a_fn The name of the function.
1942	* @param a0 The name of the 1st argument.
1943	* @param a1 The name of the 2nd argument.
1944	* @param a2 The name of the 3rd argument.
1945	*/
1946	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
1947
1948
1949	/**
1950	* For typedef'ing or declaring a C instruction implementation function taking
1951	* four extra arguments.
1952	*
1953	* @param a_Name The name of the type.
1954	* @param a_Type0 The type of the 1st argument
1955	* @param a_Arg0 The name of the 1st argument.
1956	* @param a_Type1 The type of the 2nd argument.
1957	* @param a_Arg1 The name of the 2nd argument.
1958	* @param a_Type2 The type of the 3rd argument.
1959	* @param a_Arg2 The name of the 3rd argument.
1960	* @param a_Type3 The type of the 4th argument.
1961	* @param a_Arg3 The name of the 4th argument.
1962	*/
1963	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1964	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
1965	/**
1966	* For defining a C instruction implementation function taking four extra
1967	* arguments.
1968	*
1969	* @param a_Name The name of the function.
1970	* @param a_Type0 The type of the 1st argument
1971	* @param a_Arg0 The name of the 1st argument.
1972	* @param a_Type1 The type of the 2nd argument.
1973	* @param a_Arg1 The name of the 2nd argument.
1974	* @param a_Type2 The type of the 3rd argument.
1975	* @param a_Arg2 The name of the 3rd argument.
1976	* @param a_Type3 The type of the 4th argument.
1977	* @param a_Arg3 The name of the 4th argument.
1978	*/
1979	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1980	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1981	a_Type2 a_Arg2, a_Type3 a_Arg3))
1982	/**
1983	* Prototype version of IEM_CIMPL_DEF_4.
1984	*/
1985	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
1986	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
1987	a_Type2 a_Arg2, a_Type3 a_Arg3))
1988	/**
1989	* For calling a C instruction implementation function taking four extra
1990	* arguments.
1991	*
1992	* This special call macro adds default arguments to the call and allow us to
1993	* change these later.
1994	*
1995	* @param a_fn The name of the function.
1996	* @param a0 The name of the 1st argument.
1997	* @param a1 The name of the 2nd argument.
1998	* @param a2 The name of the 3rd argument.
1999	* @param a3 The name of the 4th argument.
2000	*/
2001	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
2002
2003
2004	/**
2005	* For typedef'ing or declaring a C instruction implementation function taking
2006	* five extra arguments.
2007	*
2008	* @param a_Name The name of the type.
2009	* @param a_Type0 The type of the 1st argument
2010	* @param a_Arg0 The name of the 1st argument.
2011	* @param a_Type1 The type of the 2nd argument.
2012	* @param a_Arg1 The name of the 2nd argument.
2013	* @param a_Type2 The type of the 3rd argument.
2014	* @param a_Arg2 The name of the 3rd argument.
2015	* @param a_Type3 The type of the 4th argument.
2016	* @param a_Arg3 The name of the 4th argument.
2017	* @param a_Type4 The type of the 5th argument.
2018	* @param a_Arg4 The name of the 5th argument.
2019	*/
2020	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2021	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
2022	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
2023	a_Type3 a_Arg3, a_Type4 a_Arg4))
2024	/**
2025	* For defining a C instruction implementation function taking five extra
2026	* arguments.
2027	*
2028	* @param a_Name The name of the function.
2029	* @param a_Type0 The type of the 1st argument
2030	* @param a_Arg0 The name of the 1st argument.
2031	* @param a_Type1 The type of the 2nd argument.
2032	* @param a_Arg1 The name of the 2nd argument.
2033	* @param a_Type2 The type of the 3rd argument.
2034	* @param a_Arg2 The name of the 3rd argument.
2035	* @param a_Type3 The type of the 4th argument.
2036	* @param a_Arg3 The name of the 4th argument.
2037	* @param a_Type4 The type of the 5th argument.
2038	* @param a_Arg4 The name of the 5th argument.
2039	*/
2040	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2041	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2042	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
2043	/**
2044	* Prototype version of IEM_CIMPL_DEF_5.
2045	*/
2046	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2047	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2048	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
2049	/**
2050	* For calling a C instruction implementation function taking five extra
2051	* arguments.
2052	*
2053	* This special call macro adds default arguments to the call and allow us to
2054	* change these later.
2055	*
2056	* @param a_fn The name of the function.
2057	* @param a0 The name of the 1st argument.
2058	* @param a1 The name of the 2nd argument.
2059	* @param a2 The name of the 3rd argument.
2060	* @param a3 The name of the 4th argument.
2061	* @param a4 The name of the 5th argument.
2062	*/
2063	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
2064
2065	/** @} */
2066
2067
2068	/** @name Opcode Decoder Function Types.
2069	* @{ */
2070
2071	/** @typedef PFNIEMOP
2072	* Pointer to an opcode decoder function.
2073	*/
2074
2075	/** @def FNIEMOP_DEF
2076	* Define an opcode decoder function.
2077	*
2078	* We're using macors for this so that adding and removing parameters as well as
2079	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
2080	*
2081	* @param a_Name The function name.
2082	*/
2083
2084	/** @typedef PFNIEMOPRM
2085	* Pointer to an opcode decoder function with RM byte.
2086	*/
2087
2088	/** @def FNIEMOPRM_DEF
2089	* Define an opcode decoder function with RM byte.
2090	*
2091	* We're using macors for this so that adding and removing parameters as well as
2092	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
2093	*
2094	* @param a_Name The function name.
2095	*/
2096
2097	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2098	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
2099	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2100	# define FNIEMOP_DEF(a_Name) \
2101	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
2102	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2103	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
2104	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2105	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
2106
2107	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2108	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
2109	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2110	# define FNIEMOP_DEF(a_Name) \
2111	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
2112	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2113	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
2114	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2115	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
2116
2117	#elif defined(__GNUC__)
2118	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
2119	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2120	# define FNIEMOP_DEF(a_Name) \
2121	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
2122	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2123	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
2124	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2125	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
2126
2127	#else
2128	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
2129	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2130	# define FNIEMOP_DEF(a_Name) \
2131	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
2132	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2133	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
2134	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2135	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
2136
2137	#endif
2138	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
2139
2140	/**
2141	* Call an opcode decoder function.
2142	*
2143	* We're using macors for this so that adding and removing parameters can be
2144	* done as we please. See FNIEMOP_DEF.
2145	*/
2146	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
2147
2148	/**
2149	* Call a common opcode decoder function taking one extra argument.
2150	*
2151	* We're using macors for this so that adding and removing parameters can be
2152	* done as we please. See FNIEMOP_DEF_1.
2153	*/
2154	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
2155
2156	/**
2157	* Call a common opcode decoder function taking one extra argument.
2158	*
2159	* We're using macors for this so that adding and removing parameters can be
2160	* done as we please. See FNIEMOP_DEF_1.
2161	*/
2162	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
2163	/** @} */
2164
2165
2166	/** @name Misc Helpers
2167	* @{ */
2168
2169	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
2170	* due to GCC lacking knowledge about the value range of a switch. */
2171	#define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
2172
2173	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
2174	#define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
2175
2176	/**
2177	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
2178	* occation.
2179	*/
2180	#ifdef LOG_ENABLED
2181	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
2182	do { \
2183	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
2184	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
2185	} while (0)
2186	#else
2187	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
2188	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
2189	#endif
2190
2191	/**
2192	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
2193	* occation using the supplied logger statement.
2194	*
2195	* @param a_LoggerArgs What to log on failure.
2196	*/
2197	#ifdef LOG_ENABLED
2198	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
2199	do { \
2200	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
2201	/LogFunc(a_LoggerArgs);/ \
2202	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
2203	} while (0)
2204	#else
2205	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
2206	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
2207	#endif
2208
2209	/**
2210	* Check if we're currently executing in real or virtual 8086 mode.
2211	*
2212	* @returns @c true if it is, @c false if not.
2213	* @param a_pVCpu The IEM state of the current CPU.
2214	*/
2215	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (CPUMIsGuestInRealOrV86ModeEx(IEM_GET_CTX(a_pVCpu)))
2216
2217	/**
2218	* Check if we're currently executing in virtual 8086 mode.
2219	*
2220	* @returns @c true if it is, @c false if not.
2221	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2222	*/
2223	#define IEM_IS_V86_MODE(a_pVCpu) (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(a_pVCpu)))
2224
2225	/**
2226	* Check if we're currently executing in long mode.
2227	*
2228	* @returns @c true if it is, @c false if not.
2229	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2230	*/
2231	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
2232
2233	/**
2234	* Check if we're currently executing in a 64-bit code segment.
2235	*
2236	* @returns @c true if it is, @c false if not.
2237	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2238	*/
2239	#define IEM_IS_64BIT_CODE(a_pVCpu) (CPUMIsGuestIn64BitCodeEx(IEM_GET_CTX(a_pVCpu)))
2240
2241	/**
2242	* Check if we're currently executing in real mode.
2243	*
2244	* @returns @c true if it is, @c false if not.
2245	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2246	*/
2247	#define IEM_IS_REAL_MODE(a_pVCpu) (CPUMIsGuestInRealModeEx(IEM_GET_CTX(a_pVCpu)))
2248
2249	/**
2250	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
2251	* @returns PCCPUMFEATURES
2252	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2253	*/
2254	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
2255
2256	/**
2257	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
2258	* @returns PCCPUMFEATURES
2259	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2260	*/
2261	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
2262
2263	/**
2264	* Evaluates to true if we're presenting an Intel CPU to the guest.
2265	*/
2266	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
2267
2268	/**
2269	* Evaluates to true if we're presenting an AMD CPU to the guest.
2270	*/
2271	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
2272
2273	/**
2274	* Check if the address is canonical.
2275	*/
2276	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
2277
2278	/**
2279	* Gets the effective VEX.VVVV value.
2280	*
2281	* The 4th bit is ignored if not 64-bit code.
2282	* @returns effective V-register value.
2283	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2284	*/
2285	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
2286	((a_pVCpu)->iem.s.enmCpuMode == IEMMODE_64BIT ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
2287
2288
2289	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2290
2291	/**
2292	* Check if the guest has entered VMX root operation.
2293	*/
2294	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
2295
2296	/**
2297	* Check if the guest has entered VMX non-root operation.
2298	*/
2299	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(a_pVCpu)))
2300
2301	/**
2302	* Check if the nested-guest has the given Pin-based VM-execution control set.
2303	*/
2304	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) \
2305	(CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
2306
2307	/**
2308	* Check if the nested-guest has the given Processor-based VM-execution control set.
2309	*/
2310	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) \
2311	(CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
2312
2313	/**
2314	* Check if the nested-guest has the given Secondary Processor-based VM-execution
2315	* control set.
2316	*/
2317	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) \
2318	(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
2319
2320	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
2321	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
2322
2323	/** Whether a shadow VMCS is present for the given VCPU. */
2324	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
2325
2326	/** Gets the VMXON region pointer. */
2327	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
2328
2329	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
2330	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
2331
2332	/** Whether a current VMCS is present for the given VCPU. */
2333	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
2334
2335	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
2336	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
2337	do \
2338	{ \
2339	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
2340	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
2341	} while (0)
2342
2343	/** Clears any current VMCS for the given VCPU. */
2344	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
2345	do \
2346	{ \
2347	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
2348	} while (0)
2349
2350	/**
2351	* Invokes the VMX VM-exit handler for an instruction intercept.
2352	*/
2353	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
2354	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
2355
2356	/**
2357	* Invokes the VMX VM-exit handler for an instruction intercept where the
2358	* instruction provides additional VM-exit information.
2359	*/
2360	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
2361	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
2362
2363	/**
2364	* Invokes the VMX VM-exit handler for a task switch.
2365	*/
2366	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
2367	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
2368
2369	/**
2370	* Invokes the VMX VM-exit handler for MWAIT.
2371	*/
2372	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
2373	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
2374
2375	/**
2376	* Invokes the VMX VM-exit handler for EPT faults.
2377	*/
2378	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
2379	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
2380
2381	/**
2382	* Invokes the VMX VM-exit handler.
2383	*/
2384	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
2385	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
2386
2387	#else
2388	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
2389	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
2390	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
2391	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
2392	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
2393	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2394	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2395	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2396	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2397	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2398	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
2399
2400	#endif
2401
2402	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2403	/**
2404	* Check if an SVM control/instruction intercept is set.
2405	*/
2406	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
2407	(CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
2408
2409	/**
2410	* Check if an SVM read CRx intercept is set.
2411	*/
2412	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
2413	(CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
2414
2415	/**
2416	* Check if an SVM write CRx intercept is set.
2417	*/
2418	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
2419	(CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
2420
2421	/**
2422	* Check if an SVM read DRx intercept is set.
2423	*/
2424	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
2425	(CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
2426
2427	/**
2428	* Check if an SVM write DRx intercept is set.
2429	*/
2430	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
2431	(CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
2432
2433	/**
2434	* Check if an SVM exception intercept is set.
2435	*/
2436	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
2437	(CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
2438
2439	/**
2440	* Invokes the SVM \#VMEXIT handler for the nested-guest.
2441	*/
2442	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
2443	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
2444
2445	/**
2446	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
2447	* corresponding decode assist information.
2448	*/
2449	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
2450	do \
2451	{ \
2452	uint64_t uExitInfo1; \
2453	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
2454	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
2455	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
2456	else \
2457	uExitInfo1 = 0; \
2458	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
2459	} while (0)
2460
2461	/** Check and handles SVM nested-guest instruction intercept and updates
2462	* NRIP if needed.
2463	*/
2464	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
2465	do \
2466	{ \
2467	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
2468	{ \
2469	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
2470	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
2471	} \
2472	} while (0)
2473
2474	/** Checks and handles SVM nested-guest CR0 read intercept. */
2475	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) \
2476	do \
2477	{ \
2478	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
2479	{ /* probably likely */ } \
2480	else \
2481	{ \
2482	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
2483	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
2484	} \
2485	} while (0)
2486
2487	/**
2488	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
2489	*/
2490	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) \
2491	do { \
2492	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
2493	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), IEM_GET_INSTR_LEN(a_pVCpu)); \
2494	} while (0)
2495
2496	#else
2497	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
2498	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
2499	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
2500	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
2501	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
2502	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
2503	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
2504	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
2505	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0)
2506	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) do { } while (0)
2507	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) do { } while (0)
2508
2509	#endif
2510
2511	/** @} */
2512
2513
2514
2515	/**
2516	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
2517	*/
2518	typedef union IEMSELDESC
2519	{
2520	/** The legacy view. */
2521	X86DESC Legacy;
2522	/** The long mode view. */
2523	X86DESC64 Long;
2524	} IEMSELDESC;
2525	/** Pointer to a selector descriptor table entry. */
2526	typedef IEMSELDESC *PIEMSELDESC;
2527
2528	/** @name Raising Exceptions.
2529	* @{ */
2530	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
2531	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
2532
2533	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
2534	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
2535	#ifdef IEM_WITH_SETJMP
2536	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
2537	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
2538	#endif
2539	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
2540	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
2541	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
2542	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
2543	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
2544	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
2545	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
2546	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
2547	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
2548	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
2549	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
2550	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
2551	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
2552	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
2553	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
2554	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
2555	#ifdef IEM_WITH_SETJMP
2556	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2557	#endif
2558	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
2559	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
2560	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
2561	#ifdef IEM_WITH_SETJMP
2562	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
2563	#endif
2564	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
2565	#ifdef IEM_WITH_SETJMP
2566	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
2567	#endif
2568	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
2569	#ifdef IEM_WITH_SETJMP
2570	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
2571	#endif
2572	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
2573	#ifdef IEM_WITH_SETJMP
2574	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
2575	#endif
2576	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu);
2577	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu);
2578	#ifdef IEM_WITH_SETJMP
2579	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2580	#endif
2581
2582	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
2583	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
2584	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
2585
2586	/**
2587	* Macro for calling iemCImplRaiseDivideError().
2588	*
2589	* This enables us to add/remove arguments and force different levels of
2590	* inlining as we wish.
2591	*
2592	* @return Strict VBox status code.
2593	*/
2594	#define IEMOP_RAISE_DIVIDE_ERROR() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseDivideError)
2595
2596	/**
2597	* Macro for calling iemCImplRaiseInvalidLockPrefix().
2598	*
2599	* This enables us to add/remove arguments and force different levels of
2600	* inlining as we wish.
2601	*
2602	* @return Strict VBox status code.
2603	*/
2604	#define IEMOP_RAISE_INVALID_LOCK_PREFIX() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidLockPrefix)
2605
2606	/**
2607	* Macro for calling iemCImplRaiseInvalidOpcode().
2608	*
2609	* This enables us to add/remove arguments and force different levels of
2610	* inlining as we wish.
2611	*
2612	* @return Strict VBox status code.
2613	*/
2614	#define IEMOP_RAISE_INVALID_OPCODE() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidOpcode)
2615	/** @} */
2616
2617	/** @name Register Access.
2618	* @{ */
2619	VBOXSTRICTRC iemRegRipRelativeJumpS8(PVMCPUCC pVCpu, int8_t offNextInstr) RT_NOEXCEPT;
2620	VBOXSTRICTRC iemRegRipRelativeJumpS16(PVMCPUCC pVCpu, int16_t offNextInstr) RT_NOEXCEPT;
2621	VBOXSTRICTRC iemRegRipRelativeJumpS32(PVMCPUCC pVCpu, int32_t offNextInstr) RT_NOEXCEPT;
2622	VBOXSTRICTRC iemRegRipJump(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
2623	/** @} */
2624
2625	/** @name FPU access and helpers.
2626	* @{ */
2627	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult) RT_NOEXCEPT;
2628	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2629	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult) RT_NOEXCEPT;
2630	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
2631	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
2632	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
2633	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2634	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
2635	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2636	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2637	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
2638	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
2639	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2640	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
2641	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2642	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
2643	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2644	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
2645	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2646	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu) RT_NOEXCEPT;
2647	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
2648	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu) RT_NOEXCEPT;
2649	void iemFpuStackPushOverflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
2650	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2651	/** @} */
2652
2653	/** @name Memory access.
2654	* @{ */
2655	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t fAccess) RT_NOEXCEPT;
2656	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
2657	#ifndef IN_RING3
2658	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
2659	#endif
2660	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
2661	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
2662	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
2663	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
2664
2665	#ifdef IEM_WITH_CODE_TLB
2666	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) RT_NOEXCEPT;
2667	#else
2668	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
2669	#endif
2670	#ifdef IEM_WITH_SETJMP
2671	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2672	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2673	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2674	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2675	#else
2676	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
2677	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
2678	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
2679	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2680	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
2681	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
2682	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2683	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
2684	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2685	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2686	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2687	#endif
2688
2689	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2690	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2691	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2692	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2693	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2694	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2695	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2696	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2697	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2698	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2699	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2700	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2701	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
2702	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
2703	#ifdef IEM_WITH_SETJMP
2704	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2705	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2706	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2707	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2708	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2709	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2710	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2711	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2712	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2713	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2714	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2715	#endif
2716
2717	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2718	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2719	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2720	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2721	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
2722
2723	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
2724	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
2725	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
2726	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
2727	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
2728	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
2729	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
2730	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
2731	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2732	#ifdef IEM_WITH_SETJMP
2733	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
2734	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
2735	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
2736	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
2737	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
2738	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
2739	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
2740	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
2741	#endif
2742
2743	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
2744	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
2745	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
2746	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
2747	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
2748	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2749	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2750	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2751	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
2752	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
2753	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t cbMem, void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
2754	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
2755	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
2756	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
2757	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
2758	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2759	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2760	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2761	/** @} */
2762
2763	/** @name IEMAllCImpl.cpp
2764	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
2765	* @{ */
2766	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
2767	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
2768	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
2769	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
2770	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
2771	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
2772	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
2773	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
2774	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
2775	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
2776	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
2777	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
2778	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
2779	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
2780	IEM_CIMPL_PROTO_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
2781	IEM_CIMPL_PROTO_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
2782	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
2783	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
2784	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
2785	IEM_CIMPL_PROTO_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop);
2786	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
2787	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
2788	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
2789	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
2790	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
2791	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
2792	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
2793	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
2794	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
2795	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
2796	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
2797	IEM_CIMPL_PROTO_0(iemCImpl_sysret);
2798	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
2799	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
2800	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
2801	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
2802	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
2803	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
2804	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
2805	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
2806	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
2807	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
2808	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2809	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
2810	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2811	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
2812	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
2813	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2814	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
2815	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
2816	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2817	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
2818	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
2819	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2820	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
2821	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
2822	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
2823	IEM_CIMPL_PROTO_0(iemCImpl_clts);
2824	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
2825	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
2826	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
2827	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
2828	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
2829	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
2830	IEM_CIMPL_PROTO_0(iemCImpl_invd);
2831	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
2832	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
2833	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
2834	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
2835	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
2836	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
2837	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
2838	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
2839	IEM_CIMPL_PROTO_1(iemCImpl_in_eAX_DX, uint8_t, cbReg);
2840	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
2841	IEM_CIMPL_PROTO_1(iemCImpl_out_DX_eAX, uint8_t, cbReg);
2842	IEM_CIMPL_PROTO_0(iemCImpl_cli);
2843	IEM_CIMPL_PROTO_0(iemCImpl_sti);
2844	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
2845	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
2846	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
2847	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
2848	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
2849	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
2850	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
2851	IEM_CIMPL_PROTO_0(iemCImpl_daa);
2852	IEM_CIMPL_PROTO_0(iemCImpl_das);
2853	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
2854	IEM_CIMPL_PROTO_0(iemCImpl_aas);
2855	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
2856	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
2857	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
2858	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
2859	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
2860	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
2861	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
2862	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
2863	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
2864	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
2865	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
2866	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
2867	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
2868	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
2869	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
2870	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2871	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2872	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
2873	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
2874	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
2875	IEM_CIMPL_PROTO_1(iemCImpl_fxch_underflow, uint8_t, iStReg);
2876	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop);
2877	/** @} */
2878
2879	/** @name IEMAllCImplStrInstr.cpp.h
2880	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
2881	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
2882	* @{ */
2883	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
2884	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
2885	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
2886	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
2887	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
2888	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
2889	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
2890	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
2891	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
2892	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
2893	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
2894
2895	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
2896	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
2897	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
2898	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
2899	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
2900	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
2901	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
2902	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
2903	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
2904	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
2905	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
2906
2907	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
2908	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
2909	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
2910	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
2911	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
2912	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
2913	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
2914	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
2915	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
2916	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
2917	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
2918
2919
2920	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
2921	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
2922	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
2923	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
2924	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
2925	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
2926	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
2927	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
2928	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
2929	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
2930	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
2931
2932	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
2933	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
2934	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
2935	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
2936	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
2937	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
2938	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
2939	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
2940	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
2941	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
2942	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
2943
2944	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
2945	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
2946	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
2947	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
2948	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
2949	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
2950	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
2951	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
2952	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
2953	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
2954	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
2955
2956	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
2957	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
2958	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
2959	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
2960	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
2961	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
2962	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
2963	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
2964	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
2965	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
2966	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
2967
2968
2969	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
2970	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
2971	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
2972	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
2973	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
2974	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
2975	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
2976	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
2977	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
2978	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
2979	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
2980
2981	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
2982	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
2983	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
2984	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
2985	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
2986	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
2987	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
2988	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
2989	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
2990	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
2991	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
2992
2993	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
2994	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
2995	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
2996	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
2997	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
2998	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
2999	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
3000	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
3001	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
3002	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3003	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3004
3005	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
3006	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
3007	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
3008	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
3009	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
3010	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
3011	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
3012	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
3013	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
3014	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3015	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3016	/** @} */
3017
3018	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3019	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
3020	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
3021	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
3022	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
3023	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
3024	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
3025	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
3026	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
3027	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
3028	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3029	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
3030	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3031	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
3032	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3033	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3034	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3035	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3036	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3037	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3038	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
3039	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
3040	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
3041	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
3042	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
3043	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
3044	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
3045	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
3046	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
3047	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
3048	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
3049	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
3050	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
3051	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
3052	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
3053	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3054	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3055	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3056	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
3057	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
3058	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
3059	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField);
3060	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
3061	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
3062	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
3063	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
3064	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
3065	#endif
3066
3067	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3068	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
3069	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3070	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
3071	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
3072	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite) RT_NOEXCEPT;
3073	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
3074	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
3075	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
3076	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
3077	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
3078	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
3079	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
3080	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
3081	#endif
3082
3083	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
3084	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
3085	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
3086
3087
3088	extern const PFNIEMOP g_apfnOneByteMap[256];
3089
3090	/** @} */
3091
3092	RT_C_DECLS_END
3093
3094	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
3095

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 95185

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