IEMInternal.h@ 95308

Last change on this file since 95308 was 95308, checked in by vboxsync, 3 years ago
VMM/IEM: Implemented ANDN, BEXTR, SHLX, SARX, SHRX, RORX, TZCNT, and LZCNT. Fixed long-mod bug in 32-bit version of BSR and BSF (would clear the upper 32 bits of the destination register when ZF=1). bugref:9898
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 152.7 KB

Line
1	/* $Id: IEMInternal.h 95308 2022-06-19 20:40:26Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
19	#define VMM_INCLUDED_SRC_include_IEMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/vmm/cpum.h>
25	#include <VBox/vmm/iem.h>
26	#include <VBox/vmm/pgm.h>
27	#include <VBox/vmm/stam.h>
28	#include <VBox/param.h>
29
30	#include <iprt/setjmp-without-sigmask.h>
31
32
33	RT_C_DECLS_BEGIN
34
35
36	/** @defgroup grp_iem_int Internals
37	* @ingroup grp_iem
38	* @internal
39	* @{
40	*/
41
42	/** For expanding symbol in slickedit and other products tagging and
43	* crossreferencing IEM symbols. */
44	#ifndef IEM_STATIC
45	# define IEM_STATIC static
46	#endif
47
48	/** @def IEM_WITH_SETJMP
49	* Enables alternative status code handling using setjmps.
50	*
51	* This adds a bit of expense via the setjmp() call since it saves all the
52	* non-volatile registers. However, it eliminates return code checks and allows
53	* for more optimal return value passing (return regs instead of stack buffer).
54	*/
55	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
56	# define IEM_WITH_SETJMP
57	#endif
58
59	#define IEM_IMPLEMENTS_TASKSWITCH
60
61	/** @def IEM_WITH_3DNOW
62	* Includes the 3DNow decoding. */
63	#define IEM_WITH_3DNOW
64
65	/** @def IEM_WITH_THREE_0F_38
66	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
67	#define IEM_WITH_THREE_0F_38
68
69	/** @def IEM_WITH_THREE_0F_3A
70	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
71	#define IEM_WITH_THREE_0F_3A
72
73	/** @def IEM_WITH_VEX
74	* Includes the VEX decoding. */
75	#define IEM_WITH_VEX
76
77	/** @def IEM_CFG_TARGET_CPU
78	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
79	*
80	* By default we allow this to be configured by the user via the
81	* CPUM/GuestCpuName config string, but this comes at a slight cost during
82	* decoding. So, for applications of this code where there is no need to
83	* be dynamic wrt target CPU, just modify this define.
84	*/
85	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
86	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
87	#endif
88
89	//#define IEM_WITH_CODE_TLB // - work in progress
90	//#define IEM_WITH_DATA_TLB // - work in progress
91
92
93	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
94	* Use unaligned accesses instead of elaborate byte assembly. */
95	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
96	# define IEM_USE_UNALIGNED_DATA_ACCESS
97	#endif
98
99	//#define IEM_LOG_MEMORY_WRITES
100
101	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
102	/** Instruction statistics. */
103	typedef struct IEMINSTRSTATS
104	{
105	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
106	# include "IEMInstructionStatisticsTmpl.h"
107	# undef IEM_DO_INSTR_STAT
108	} IEMINSTRSTATS;
109	#else
110	struct IEMINSTRSTATS;
111	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
112	#endif
113	/** Pointer to IEM instruction statistics. */
114	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
115
116
117	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
118	* @{ */
119	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
120	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
121	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
122	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
123	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
124	/** Selects the right variant from a_aArray.
125	* pVCpu is implicit in the caller context. */
126	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
127	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
128	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
129	* be used because the host CPU does not support the operation. */
130	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
131	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
132	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
133	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
134	* into the two.
135	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
136	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
137	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
138	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
139	#else
140	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
141	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
142	#endif
143	/** @} */
144
145	/**
146	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
147	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
148	*
149	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
150	* indicator.
151	*
152	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
153	*/
154	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
155	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
156	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
157	#else
158	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
159	#endif
160
161
162	/**
163	* Extended operand mode that includes a representation of 8-bit.
164	*
165	* This is used for packing down modes when invoking some C instruction
166	* implementations.
167	*/
168	typedef enum IEMMODEX
169	{
170	IEMMODEX_16BIT = IEMMODE_16BIT,
171	IEMMODEX_32BIT = IEMMODE_32BIT,
172	IEMMODEX_64BIT = IEMMODE_64BIT,
173	IEMMODEX_8BIT
174	} IEMMODEX;
175	AssertCompileSize(IEMMODEX, 4);
176
177
178	/**
179	* Branch types.
180	*/
181	typedef enum IEMBRANCH
182	{
183	IEMBRANCH_JUMP = 1,
184	IEMBRANCH_CALL,
185	IEMBRANCH_TRAP,
186	IEMBRANCH_SOFTWARE_INT,
187	IEMBRANCH_HARDWARE_INT
188	} IEMBRANCH;
189	AssertCompileSize(IEMBRANCH, 4);
190
191
192	/**
193	* INT instruction types.
194	*/
195	typedef enum IEMINT
196	{
197	/** INT n instruction (opcode 0xcd imm). */
198	IEMINT_INTN = 0,
199	/** Single byte INT3 instruction (opcode 0xcc). */
200	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
201	/** Single byte INTO instruction (opcode 0xce). */
202	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
203	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
204	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
205	} IEMINT;
206	AssertCompileSize(IEMINT, 4);
207
208
209	/**
210	* A FPU result.
211	*/
212	typedef struct IEMFPURESULT
213	{
214	/** The output value. */
215	RTFLOAT80U r80Result;
216	/** The output status. */
217	uint16_t FSW;
218	} IEMFPURESULT;
219	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
220	/** Pointer to a FPU result. */
221	typedef IEMFPURESULT *PIEMFPURESULT;
222	/** Pointer to a const FPU result. */
223	typedef IEMFPURESULT const *PCIEMFPURESULT;
224
225
226	/**
227	* A FPU result consisting of two output values and FSW.
228	*/
229	typedef struct IEMFPURESULTTWO
230	{
231	/** The first output value. */
232	RTFLOAT80U r80Result1;
233	/** The output status. */
234	uint16_t FSW;
235	/** The second output value. */
236	RTFLOAT80U r80Result2;
237	} IEMFPURESULTTWO;
238	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
239	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
240	/** Pointer to a FPU result consisting of two output values and FSW. */
241	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
242	/** Pointer to a const FPU result consisting of two output values and FSW. */
243	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
244
245
246	/**
247	* IEM TLB entry.
248	*
249	* Lookup assembly:
250	* @code{.asm}
251	; Calculate tag.
252	mov rax, [VA]
253	shl rax, 16
254	shr rax, 16 + X86_PAGE_SHIFT
255	or rax, [uTlbRevision]
256
257	; Do indexing.
258	movzx ecx, al
259	lea rcx, [pTlbEntries + rcx]
260
261	; Check tag.
262	cmp [rcx + IEMTLBENTRY.uTag], rax
263	jne .TlbMiss
264
265	; Check access.
266	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
267	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
268	cmp rax, [uTlbPhysRev]
269	jne .TlbMiss
270
271	; Calc address and we're done.
272	mov eax, X86_PAGE_OFFSET_MASK
273	and eax, [VA]
274	or rax, [rcx + IEMTLBENTRY.pMappingR3]
275	%ifdef VBOX_WITH_STATISTICS
276	inc qword [cTlbHits]
277	%endif
278	jmp .Done
279
280	.TlbMiss:
281	mov r8d, ACCESS_FLAGS
282	mov rdx, [VA]
283	mov rcx, [pVCpu]
284	call iemTlbTypeMiss
285	.Done:
286
287	@endcode
288	*
289	*/
290	typedef struct IEMTLBENTRY
291	{
292	/** The TLB entry tag.
293	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
294	* is ASSUMING a virtual address width of 48 bits.
295	*
296	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
297	*
298	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
299	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
300	* revision wraps around though, the tags needs to be zeroed.
301	*
302	* @note Try use SHRD instruction? After seeing
303	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
304	*
305	* @todo This will need to be reorganized for 57-bit wide virtual address and
306	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
307	* have to move the TLB entry versioning entirely to the
308	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
309	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
310	* consumed by PCID and ASID (12 + 6 = 18).
311	*/
312	uint64_t uTag;
313	/** Access flags and physical TLB revision.
314	*
315	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
316	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
317	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
318	* - Bit 3 - pgm phys/virt - not directly writable.
319	* - Bit 4 - pgm phys page - not directly readable.
320	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
321	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
322	* - Bit 7 - tlb entry - pMappingR3 member not valid.
323	* - Bits 63 thru 8 are used for the physical TLB revision number.
324	*
325	* We're using complemented bit meanings here because it makes it easy to check
326	* whether special action is required. For instance a user mode write access
327	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
328	* non-zero result would mean special handling needed because either it wasn't
329	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
330	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
331	* need to check any PTE flag.
332	*/
333	uint64_t fFlagsAndPhysRev;
334	/** The guest physical page address. */
335	uint64_t GCPhys;
336	/** Pointer to the ring-3 mapping. */
337	R3PTRTYPE(uint8_t *) pbMappingR3;
338	#if HC_ARCH_BITS == 32
339	uint32_t u32Padding1;
340	#endif
341	} IEMTLBENTRY;
342	AssertCompileSize(IEMTLBENTRY, 32);
343	/** Pointer to an IEM TLB entry. */
344	typedef IEMTLBENTRY *PIEMTLBENTRY;
345
346	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
347	* @{ */
348	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
349	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
350	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
351	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
352	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
353	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
354	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
355	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
356	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
357	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
358	/** @} */
359
360
361	/**
362	* An IEM TLB.
363	*
364	* We've got two of these, one for data and one for instructions.
365	*/
366	typedef struct IEMTLB
367	{
368	/** The TLB entries.
369	* We've choosen 256 because that way we can obtain the result directly from a
370	* 8-bit register without an additional AND instruction. */
371	IEMTLBENTRY aEntries[256];
372	/** The TLB revision.
373	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
374	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
375	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
376	* (The revision zero indicates an invalid TLB entry.)
377	*
378	* The initial value is choosen to cause an early wraparound. */
379	uint64_t uTlbRevision;
380	/** The TLB physical address revision - shadow of PGM variable.
381	*
382	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
383	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
384	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
385	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
386	*
387	* The initial value is choosen to cause an early wraparound. */
388	uint64_t volatile uTlbPhysRev;
389
390	/* Statistics: */
391
392	/** TLB hits (VBOX_WITH_STATISTICS only). */
393	uint64_t cTlbHits;
394	/** TLB misses. */
395	uint32_t cTlbMisses;
396	/** Slow read path. */
397	uint32_t cTlbSlowReadPath;
398	#if 0
399	/** TLB misses because of tag mismatch. */
400	uint32_t cTlbMissesTag;
401	/** TLB misses because of virtual access violation. */
402	uint32_t cTlbMissesVirtAccess;
403	/** TLB misses because of dirty bit. */
404	uint32_t cTlbMissesDirty;
405	/** TLB misses because of MMIO */
406	uint32_t cTlbMissesMmio;
407	/** TLB misses because of write access handlers. */
408	uint32_t cTlbMissesWriteHandler;
409	/** TLB misses because no r3(/r0) mapping. */
410	uint32_t cTlbMissesMapping;
411	#endif
412	/** Alignment padding. */
413	uint32_t au32Padding[3+5];
414	} IEMTLB;
415	AssertCompileSizeAlignment(IEMTLB, 64);
416	/** IEMTLB::uTlbRevision increment. */
417	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
418	/** IEMTLB::uTlbRevision mask. */
419	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
420	/** IEMTLB::uTlbPhysRev increment.
421	* @sa IEMTLBE_F_PHYS_REV */
422	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
423	/**
424	* Calculates the TLB tag for a virtual address.
425	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
426	* @param a_pTlb The TLB.
427	* @param a_GCPtr The virtual address.
428	*/
429	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
430	/**
431	* Calculates the TLB tag for a virtual address but without TLB revision.
432	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
433	* @param a_GCPtr The virtual address.
434	*/
435	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
436	/**
437	* Converts a TLB tag value into a TLB index.
438	* @returns Index into IEMTLB::aEntries.
439	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
440	*/
441	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
442	/**
443	* Converts a TLB tag value into a TLB index.
444	* @returns Index into IEMTLB::aEntries.
445	* @param a_pTlb The TLB.
446	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
447	*/
448	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
449
450
451	/**
452	* The per-CPU IEM state.
453	*/
454	typedef struct IEMCPU
455	{
456	/** Info status code that needs to be propagated to the IEM caller.
457	* This cannot be passed internally, as it would complicate all success
458	* checks within the interpreter making the code larger and almost impossible
459	* to get right. Instead, we'll store status codes to pass on here. Each
460	* source of these codes will perform appropriate sanity checks. */
461	int32_t rcPassUp; /* 0x00 */
462
463	/** The current CPU execution mode (CS). */
464	IEMMODE enmCpuMode; /* 0x04 */
465	/** The CPL. */
466	uint8_t uCpl; /* 0x05 */
467
468	/** Whether to bypass access handlers or not. */
469	bool fBypassHandlers; /* 0x06 */
470	/** Whether to disregard the lock prefix (implied or not). */
471	bool fDisregardLock; /* 0x07 */
472
473	/** @name Decoder state.
474	* @{ */
475	#ifdef IEM_WITH_CODE_TLB
476	/** The offset of the next instruction byte. */
477	uint32_t offInstrNextByte; /* 0x08 */
478	/** The number of bytes available at pbInstrBuf for the current instruction.
479	* This takes the max opcode length into account so that doesn't need to be
480	* checked separately. */
481	uint32_t cbInstrBuf; /* 0x0c */
482	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
483	* This can be NULL if the page isn't mappable for some reason, in which
484	* case we'll do fallback stuff.
485	*
486	* If we're executing an instruction from a user specified buffer,
487	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
488	* aligned pointer but pointer to the user data.
489	*
490	* For instructions crossing pages, this will start on the first page and be
491	* advanced to the next page by the time we've decoded the instruction. This
492	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
493	*/
494	uint8_t const pbInstrBuf; / 0x10 */
495	# if ARCH_BITS == 32
496	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
497	# endif
498	/** The program counter corresponding to pbInstrBuf.
499	* This is set to a non-canonical address when we need to invalidate it. */
500	uint64_t uInstrBufPc; /* 0x18 */
501	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
502	* This takes the CS segment limit into account. */
503	uint16_t cbInstrBufTotal; /* 0x20 */
504	/** Offset into pbInstrBuf of the first byte of the current instruction.
505	* Can be negative to efficiently handle cross page instructions. */
506	int16_t offCurInstrStart; /* 0x22 */
507
508	/** The prefix mask (IEM_OP_PRF_XXX). */
509	uint32_t fPrefixes; /* 0x24 */
510	/** The extra REX ModR/M register field bit (REX.R << 3). */
511	uint8_t uRexReg; /* 0x28 */
512	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
513	* (REX.B << 3). */
514	uint8_t uRexB; /* 0x29 */
515	/** The extra REX SIB index field bit (REX.X << 3). */
516	uint8_t uRexIndex; /* 0x2a */
517
518	/** The effective segment register (X86_SREG_XXX). */
519	uint8_t iEffSeg; /* 0x2b */
520
521	/** The offset of the ModR/M byte relative to the start of the instruction. */
522	uint8_t offModRm; /* 0x2c */
523	#else
524	/** The size of what has currently been fetched into abOpcode. */
525	uint8_t cbOpcode; /* 0x08 */
526	/** The current offset into abOpcode. */
527	uint8_t offOpcode; /* 0x09 */
528	/** The offset of the ModR/M byte relative to the start of the instruction. */
529	uint8_t offModRm; /* 0x0a */
530
531	/** The effective segment register (X86_SREG_XXX). */
532	uint8_t iEffSeg; /* 0x0b */
533
534	/** The prefix mask (IEM_OP_PRF_XXX). */
535	uint32_t fPrefixes; /* 0x0c */
536	/** The extra REX ModR/M register field bit (REX.R << 3). */
537	uint8_t uRexReg; /* 0x10 */
538	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
539	* (REX.B << 3). */
540	uint8_t uRexB; /* 0x11 */
541	/** The extra REX SIB index field bit (REX.X << 3). */
542	uint8_t uRexIndex; /* 0x12 */
543
544	#endif
545
546	/** The effective operand mode. */
547	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
548	/** The default addressing mode. */
549	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
550	/** The effective addressing mode. */
551	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
552	/** The default operand mode. */
553	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
554
555	/** Prefix index (VEX.pp) for two byte and three byte tables. */
556	uint8_t idxPrefix; /* 0x31, 0x17 */
557	/** 3rd VEX/EVEX/XOP register.
558	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
559	uint8_t uVex3rdReg; /* 0x32, 0x18 */
560	/** The VEX/EVEX/XOP length field. */
561	uint8_t uVexLength; /* 0x33, 0x19 */
562	/** Additional EVEX stuff. */
563	uint8_t fEvexStuff; /* 0x34, 0x1a */
564
565	/** Explicit alignment padding. */
566	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
567	/** The FPU opcode (FOP). */
568	uint16_t uFpuOpcode; /* 0x36, 0x1c */
569	#ifndef IEM_WITH_CODE_TLB
570	/** Explicit alignment padding. */
571	uint8_t abAlignment2b[2]; /* 0x1e */
572	#endif
573
574	/** The opcode bytes. */
575	uint8_t abOpcode[15]; /* 0x48, 0x20 */
576	/** Explicit alignment padding. */
577	#ifdef IEM_WITH_CODE_TLB
578	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
579	#else
580	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
581	#endif
582	/** @} */
583
584
585	/** The flags of the current exception / interrupt. */
586	uint32_t fCurXcpt; /* 0x48, 0x48 */
587	/** The current exception / interrupt. */
588	uint8_t uCurXcpt;
589	/** Exception / interrupt recursion depth. */
590	int8_t cXcptRecursions;
591
592	/** The number of active guest memory mappings. */
593	uint8_t cActiveMappings;
594	/** The next unused mapping index. */
595	uint8_t iNextMapping;
596	/** Records for tracking guest memory mappings. */
597	struct
598	{
599	/** The address of the mapped bytes. */
600	void *pv;
601	/** The access flags (IEM_ACCESS_XXX).
602	* IEM_ACCESS_INVALID if the entry is unused. */
603	uint32_t fAccess;
604	#if HC_ARCH_BITS == 64
605	uint32_t u32Alignment4; /*< Alignment padding. /
606	#endif
607	} aMemMappings[3];
608
609	/** Locking records for the mapped memory. */
610	union
611	{
612	PGMPAGEMAPLOCK Lock;
613	uint64_t au64Padding[2];
614	} aMemMappingLocks[3];
615
616	/** Bounce buffer info.
617	* This runs in parallel to aMemMappings. */
618	struct
619	{
620	/** The physical address of the first byte. */
621	RTGCPHYS GCPhysFirst;
622	/** The physical address of the second page. */
623	RTGCPHYS GCPhysSecond;
624	/** The number of bytes in the first page. */
625	uint16_t cbFirst;
626	/** The number of bytes in the second page. */
627	uint16_t cbSecond;
628	/** Whether it's unassigned memory. */
629	bool fUnassigned;
630	/** Explicit alignment padding. */
631	bool afAlignment5[3];
632	} aMemBbMappings[3];
633
634	/** Bounce buffer storage.
635	* This runs in parallel to aMemMappings and aMemBbMappings. */
636	struct
637	{
638	uint8_t ab[512];
639	} aBounceBuffers[3];
640
641
642	/** Pointer set jump buffer - ring-3 context. */
643	R3PTRTYPE(jmp_buf *) pJmpBufR3;
644	/** Pointer set jump buffer - ring-0 context. */
645	R0PTRTYPE(jmp_buf *) pJmpBufR0;
646
647	/** @todo Should move this near @a fCurXcpt later. */
648	/** The CR2 for the current exception / interrupt. */
649	uint64_t uCurXcptCr2;
650	/** The error code for the current exception / interrupt. */
651	uint32_t uCurXcptErr;
652
653	/** @name Statistics
654	* @{ */
655	/** The number of instructions we've executed. */
656	uint32_t cInstructions;
657	/** The number of potential exits. */
658	uint32_t cPotentialExits;
659	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
660	* This may contain uncommitted writes. */
661	uint32_t cbWritten;
662	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
663	uint32_t cRetInstrNotImplemented;
664	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
665	uint32_t cRetAspectNotImplemented;
666	/** Counts informational statuses returned (other than VINF_SUCCESS). */
667	uint32_t cRetInfStatuses;
668	/** Counts other error statuses returned. */
669	uint32_t cRetErrStatuses;
670	/** Number of times rcPassUp has been used. */
671	uint32_t cRetPassUpStatus;
672	/** Number of times RZ left with instruction commit pending for ring-3. */
673	uint32_t cPendingCommit;
674	/** Number of long jumps. */
675	uint32_t cLongJumps;
676	/** @} */
677
678	/** @name Target CPU information.
679	* @{ */
680	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
681	/** The target CPU. */
682	uint8_t uTargetCpu;
683	#else
684	uint8_t bTargetCpuPadding;
685	#endif
686	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
687	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
688	* native host support and the 2nd for when there is.
689	*
690	* The two values are typically indexed by a g_CpumHostFeatures bit.
691	*
692	* This is for instance used for the BSF & BSR instructions where AMD and
693	* Intel CPUs produce different EFLAGS. */
694	uint8_t aidxTargetCpuEflFlavour[2];
695
696	/** The CPU vendor. */
697	CPUMCPUVENDOR enmCpuVendor;
698	/** @} */
699
700	/** @name Host CPU information.
701	* @{ */
702	/** The CPU vendor. */
703	CPUMCPUVENDOR enmHostCpuVendor;
704	/** @} */
705
706	/** Counts RDMSR \#GP(0) LogRel(). */
707	uint8_t cLogRelRdMsr;
708	/** Counts WRMSR \#GP(0) LogRel(). */
709	uint8_t cLogRelWrMsr;
710	/** Alignment padding. */
711	uint8_t abAlignment8[50];
712
713	/** Data TLB.
714	* @remarks Must be 64-byte aligned. */
715	IEMTLB DataTlb;
716	/** Instruction TLB.
717	* @remarks Must be 64-byte aligned. */
718	IEMTLB CodeTlb;
719
720	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
721	/** Instruction statistics for ring-0/raw-mode. */
722	IEMINSTRSTATS StatsRZ;
723	/** Instruction statistics for ring-3. */
724	IEMINSTRSTATS StatsR3;
725	#endif
726	} IEMCPU;
727	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
728	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
729	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
730	/** Pointer to the per-CPU IEM state. */
731	typedef IEMCPU *PIEMCPU;
732	/** Pointer to the const per-CPU IEM state. */
733	typedef IEMCPU const *PCIEMCPU;
734
735
736	/** @def IEM_GET_CTX
737	* Gets the guest CPU context for the calling EMT.
738	* @returns PCPUMCTX
739	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
740	*/
741	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
742
743	/** @def IEM_CTX_ASSERT
744	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
745	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
746	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
747	*/
748	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
749	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
750	(a_fExtrnMbz)))
751
752	/** @def IEM_CTX_IMPORT_RET
753	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
754	*
755	* Will call the keep to import the bits as needed.
756	*
757	* Returns on import failure.
758	*
759	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
760	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
761	*/
762	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
763	do { \
764	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
765	{ /* likely */ } \
766	else \
767	{ \
768	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
769	AssertRCReturn(rcCtxImport, rcCtxImport); \
770	} \
771	} while (0)
772
773	/** @def IEM_CTX_IMPORT_NORET
774	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
775	*
776	* Will call the keep to import the bits as needed.
777	*
778	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
779	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
780	*/
781	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
782	do { \
783	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
784	{ /* likely */ } \
785	else \
786	{ \
787	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
788	AssertLogRelRC(rcCtxImport); \
789	} \
790	} while (0)
791
792	/** @def IEM_CTX_IMPORT_JMP
793	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
794	*
795	* Will call the keep to import the bits as needed.
796	*
797	* Jumps on import failure.
798	*
799	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
800	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
801	*/
802	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
803	do { \
804	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
805	{ /* likely */ } \
806	else \
807	{ \
808	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
809	AssertRCStmt(rcCtxImport, longjmp(*pVCpu->iem.s.CTX_SUFF(pJmpBuf), rcCtxImport)); \
810	} \
811	} while (0)
812
813
814
815	/** @def IEM_GET_TARGET_CPU
816	* Gets the current IEMTARGETCPU value.
817	* @returns IEMTARGETCPU value.
818	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
819	*/
820	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
821	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
822	#else
823	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
824	#endif
825
826	/** @def IEM_GET_INSTR_LEN
827	* Gets the instruction length. */
828	#ifdef IEM_WITH_CODE_TLB
829	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
830	#else
831	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
832	#endif
833
834
835	/**
836	* Shared per-VM IEM data.
837	*/
838	typedef struct IEM
839	{
840	/** The VMX APIC-access page handler type. */
841	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
842	} IEM;
843
844
845
846	/** @name IEM_ACCESS_XXX - Access details.
847	* @{ */
848	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
849	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
850	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
851	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
852	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
853	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
854	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
855	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
856	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
857	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
858	/** The writes are partial, so if initialize the bounce buffer with the
859	* orignal RAM content. */
860	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
861	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
862	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
863	/** Bounce buffer with ring-3 write pending, first page. */
864	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
865	/** Bounce buffer with ring-3 write pending, second page. */
866	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
867	/** Not locked, accessed via the TLB. */
868	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
869	/** Valid bit mask. */
870	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
871	/** Shift count for the TLB flags (upper word). */
872	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
873
874	/** Read+write data alias. */
875	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
876	/** Write data alias. */
877	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
878	/** Read data alias. */
879	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
880	/** Instruction fetch alias. */
881	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
882	/** Stack write alias. */
883	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
884	/** Stack read alias. */
885	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
886	/** Stack read+write alias. */
887	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
888	/** Read system table alias. */
889	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
890	/** Read+write system table alias. */
891	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
892	/** @} */
893
894	/** @name Prefix constants (IEMCPU::fPrefixes)
895	* @{ */
896	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
897	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
898	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
899	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
900	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
901	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
902	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
903
904	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
905	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
906	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
907
908	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
909	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
910	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
911
912	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
913	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
914	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
915	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
916	/** Mask with all the REX prefix flags.
917	* This is generally for use when needing to undo the REX prefixes when they
918	* are followed legacy prefixes and therefore does not immediately preceed
919	* the first opcode byte.
920	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
921	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
922
923	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
924	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
925	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
926	/** @} */
927
928	/** @name IEMOPFORM_XXX - Opcode forms
929	* @note These are ORed together with IEMOPHINT_XXX.
930	* @{ */
931	/** ModR/M: reg, r/m */
932	#define IEMOPFORM_RM 0
933	/** ModR/M: reg, r/m (register) */
934	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
935	/** ModR/M: reg, r/m (memory) */
936	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
937	/** ModR/M: r/m, reg */
938	#define IEMOPFORM_MR 1
939	/** ModR/M: r/m (register), reg */
940	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
941	/** ModR/M: r/m (memory), reg */
942	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
943	/** ModR/M: r/m only */
944	#define IEMOPFORM_M 2
945	/** ModR/M: r/m only (register). */
946	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
947	/** ModR/M: r/m only (memory). */
948	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
949	/** ModR/M: reg only */
950	#define IEMOPFORM_R 3
951
952	/** VEX+ModR/M: reg, r/m */
953	#define IEMOPFORM_VEX_RM 4
954	/** VEX+ModR/M: reg, r/m (register) */
955	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
956	/** VEX+ModR/M: reg, r/m (memory) */
957	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
958	/** VEX+ModR/M: r/m, reg */
959	#define IEMOPFORM_VEX_MR 5
960	/** VEX+ModR/M: r/m (register), reg */
961	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
962	/** VEX+ModR/M: r/m (memory), reg */
963	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
964	/** VEX+ModR/M: r/m only */
965	#define IEMOPFORM_VEX_M 6
966	/** VEX+ModR/M: r/m only (register). */
967	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
968	/** VEX+ModR/M: r/m only (memory). */
969	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
970	/** VEX+ModR/M: reg only */
971	#define IEMOPFORM_VEX_R 7
972	/** VEX+ModR/M: reg, vvvv, r/m */
973	#define IEMOPFORM_VEX_RVM 8
974	/** VEX+ModR/M: reg, vvvv, r/m (register). */
975	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
976	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
977	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
978	/** VEX+ModR/M: reg, r/m, vvvv */
979	#define IEMOPFORM_VEX_RMV 9
980	/** VEX+ModR/M: reg, r/m, vvvv (register). */
981	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
982	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
983	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
984	/** VEX+ModR/M: reg, r/m, imm8 */
985	#define IEMOPFORM_VEX_RMI 10
986	/** VEX+ModR/M: reg, r/m, imm8 (register). */
987	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
988	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
989	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
990	/** VEX+ModR/M: r/m, vvvv, reg */
991	#define IEMOPFORM_VEX_MVR 11
992	/** VEX+ModR/M: r/m, vvvv, reg (register) */
993	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
994	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
995	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
996
997	/** Fixed register instruction, no R/M. */
998	#define IEMOPFORM_FIXED 16
999
1000	/** The r/m is a register. */
1001	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1002	/** The r/m is a memory access. */
1003	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1004	/** @} */
1005
1006	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1007	* @note These are ORed together with IEMOPFORM_XXX.
1008	* @{ */
1009	/** Ignores the operand size prefix (66h). */
1010	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1011	/** Ignores REX.W (aka WIG). */
1012	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1013	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1014	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1015	/** Allowed with the lock prefix. */
1016	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1017	/** The VEX.L value is ignored (aka LIG). */
1018	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1019	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1020	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1021	/** The VEX.V value must be zero. */
1022	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1023
1024	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1025	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1026	/** @} */
1027
1028	/**
1029	* Possible hardware task switch sources.
1030	*/
1031	typedef enum IEMTASKSWITCH
1032	{
1033	/** Task switch caused by an interrupt/exception. */
1034	IEMTASKSWITCH_INT_XCPT = 1,
1035	/** Task switch caused by a far CALL. */
1036	IEMTASKSWITCH_CALL,
1037	/** Task switch caused by a far JMP. */
1038	IEMTASKSWITCH_JUMP,
1039	/** Task switch caused by an IRET. */
1040	IEMTASKSWITCH_IRET
1041	} IEMTASKSWITCH;
1042	AssertCompileSize(IEMTASKSWITCH, 4);
1043
1044	/**
1045	* Possible CrX load (write) sources.
1046	*/
1047	typedef enum IEMACCESSCRX
1048	{
1049	/** CrX access caused by 'mov crX' instruction. */
1050	IEMACCESSCRX_MOV_CRX,
1051	/** CrX (CR0) write caused by 'lmsw' instruction. */
1052	IEMACCESSCRX_LMSW,
1053	/** CrX (CR0) write caused by 'clts' instruction. */
1054	IEMACCESSCRX_CLTS,
1055	/** CrX (CR0) read caused by 'smsw' instruction. */
1056	IEMACCESSCRX_SMSW
1057	} IEMACCESSCRX;
1058
1059	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1060	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1061	*
1062	* These flags provide further context to SLAT page-walk failures that could not be
1063	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1064	*
1065	* @{
1066	*/
1067	/** Translating a nested-guest linear address failed accessing a nested-guest
1068	* physical address. */
1069	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1070	/** Translating a nested-guest linear address failed accessing a
1071	* paging-structure entry or updating accessed/dirty bits. */
1072	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1073	/** @} */
1074
1075	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1076	# ifndef IN_RING3
1077	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1078	# endif
1079	#endif
1080
1081	/**
1082	* Indicates to the verifier that the given flag set is undefined.
1083	*
1084	* Can be invoked again to add more flags.
1085	*
1086	* This is a NOOP if the verifier isn't compiled in.
1087	*
1088	* @note We're temporarily keeping this until code is converted to new
1089	* disassembler style opcode handling.
1090	*/
1091	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1092
1093
1094	/** @def IEM_DECL_IMPL_TYPE
1095	* For typedef'ing an instruction implementation function.
1096	*
1097	* @param a_RetType The return type.
1098	* @param a_Name The name of the type.
1099	* @param a_ArgList The argument list enclosed in parentheses.
1100	*/
1101
1102	/** @def IEM_DECL_IMPL_DEF
1103	* For defining an instruction implementation function.
1104	*
1105	* @param a_RetType The return type.
1106	* @param a_Name The name of the type.
1107	* @param a_ArgList The argument list enclosed in parentheses.
1108	*/
1109
1110	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1111	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1112	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1113	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1114	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1115	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1116	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1117
1118	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1119	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1120	a_RetType (__fastcall a_Name) a_ArgList
1121	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1122	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1123	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1124	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1125
1126	#elif __cplusplus >= 201700 /* P0012R1 support */
1127	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1128	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1129	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1130	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1131	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1132	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1133
1134	#else
1135	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1136	a_RetType (VBOXCALL a_Name) a_ArgList
1137	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1138	a_RetType VBOXCALL a_Name a_ArgList
1139	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1140	a_RetType VBOXCALL a_Name a_ArgList
1141
1142	#endif
1143
1144	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1145	RT_C_DECLS_BEGIN
1146	extern uint8_t const g_afParity[256];
1147	RT_C_DECLS_END
1148
1149
1150	/** @name Arithmetic assignment operations on bytes (binary).
1151	* @{ */
1152	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1153	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1154	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1155	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1156	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1157	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1158	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1159	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1160	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1161	/** @} */
1162
1163	/** @name Arithmetic assignment operations on words (binary).
1164	* @{ */
1165	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1166	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1167	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1168	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1169	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1170	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1171	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1172	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1173	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1174	/** @} */
1175
1176	/** @name Arithmetic assignment operations on double words (binary).
1177	* @{ */
1178	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1179	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1180	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1181	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1182	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1183	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1184	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1185	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1186	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1187	/** @} */
1188
1189	/** @name Arithmetic assignment operations on quad words (binary).
1190	* @{ */
1191	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1192	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1193	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1194	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1195	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1196	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1197	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1198	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1199	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1200	/** @} */
1201
1202	/** @name Compare operations (thrown in with the binary ops).
1203	* @{ */
1204	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1205	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1206	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1207	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1208	/** @} */
1209
1210	/** @name Test operations (thrown in with the binary ops).
1211	* @{ */
1212	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1213	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1214	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1215	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1216	/** @} */
1217
1218	/** @name Bit operations operations (thrown in with the binary ops).
1219	* @{ */
1220	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1221	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1222	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1223	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1224	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1225	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1226	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1227	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1228	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1229	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1230	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1231	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1232	/** @} */
1233
1234	/** @name Arithmetic three operand operations on double words (binary).
1235	* @{ */
1236	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
1237	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1238	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1239	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1240	/** @} */
1241
1242	/** @name Arithmetic three operand operations on quad words (binary).
1243	* @{ */
1244	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
1245	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1246	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1247	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1248	/** @} */
1249
1250	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1251	* @{ */
1252	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1253	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1254	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1255	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1256	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1257	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1258	/** @} */
1259
1260	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1261	* @{ */
1262	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1263	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1264	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1265	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1266	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1267	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1268	/** @} */
1269
1270	/** @name Exchange memory with register operations.
1271	* @{ */
1272	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1273	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1274	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1275	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1276	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1277	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1278	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1279	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1280	/** @} */
1281
1282	/** @name Exchange and add operations.
1283	* @{ */
1284	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1285	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1286	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1287	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1288	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1289	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1290	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1291	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1292	/** @} */
1293
1294	/** @name Compare and exchange.
1295	* @{ */
1296	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1297	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1298	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1299	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1300	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1301	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1302	#if ARCH_BITS == 32
1303	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1304	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1305	#else
1306	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1307	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1308	#endif
1309	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1310	uint32_t *pEFlags));
1311	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1312	uint32_t *pEFlags));
1313	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1314	uint32_t *pEFlags));
1315	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1316	uint32_t *pEFlags));
1317	#ifndef RT_ARCH_ARM64
1318	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1319	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1320	#endif
1321	/** @} */
1322
1323	/** @name Memory ordering
1324	* @{ */
1325	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1326	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1327	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1328	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1329	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1330	#ifndef RT_ARCH_ARM64
1331	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1332	#endif
1333	/** @} */
1334
1335	/** @name Double precision shifts
1336	* @{ */
1337	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1338	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1339	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1340	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1341	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1342	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1343	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1344	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1345	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1346	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1347	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1348	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1349	/** @} */
1350
1351
1352	/** @name Bit search operations (thrown in with the binary ops).
1353	* @{ */
1354	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1355	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1356	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1357	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1358	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1359	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1360	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1361	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1362	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1363	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
1364	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
1365	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
1366	/** @} */
1367
1368	/** @name Signed multiplication operations (thrown in with the binary ops).
1369	* @{ */
1370	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1371	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1372	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1373	/** @} */
1374
1375	/** @name Arithmetic assignment operations on bytes (unary).
1376	* @{ */
1377	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1378	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1379	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1380	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1381	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1382	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1383	/** @} */
1384
1385	/** @name Arithmetic assignment operations on words (unary).
1386	* @{ */
1387	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1388	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1389	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1390	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1391	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1392	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1393	/** @} */
1394
1395	/** @name Arithmetic assignment operations on double words (unary).
1396	* @{ */
1397	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1398	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1399	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1400	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1401	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1402	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1403	/** @} */
1404
1405	/** @name Arithmetic assignment operations on quad words (unary).
1406	* @{ */
1407	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1408	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1409	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1410	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1411	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1412	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1413	/** @} */
1414
1415
1416	/** @name Shift operations on bytes (Group 2).
1417	* @{ */
1418	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1419	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1420	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1421	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1422	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1423	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1424	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1425	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1426	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1427	/** @} */
1428
1429	/** @name Shift operations on words (Group 2).
1430	* @{ */
1431	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1432	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1433	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1434	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1435	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1436	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1437	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1438	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1439	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1440	/** @} */
1441
1442	/** @name Shift operations on double words (Group 2).
1443	* @{ */
1444	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1445	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1446	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1447	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1448	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1449	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1450	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1451	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1452	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1453	/** @} */
1454
1455	/** @name Shift operations on words (Group 2).
1456	* @{ */
1457	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1458	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1459	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1460	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1461	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1462	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1463	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1464	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1465	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1466	/** @} */
1467
1468	/** @name Multiplication and division operations.
1469	* @{ */
1470	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1471	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1472	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1473	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1474	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1475	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1476
1477	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1478	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1479	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1480	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1481	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1482	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1483
1484	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1485	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1486	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1487	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1488	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1489	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1490
1491	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1492	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1493	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1494	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1495	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1496	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1497	/** @} */
1498
1499	/** @name Byte Swap.
1500	* @{ */
1501	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1502	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1503	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1504	/** @} */
1505
1506	/** @name Misc.
1507	* @{ */
1508	FNIEMAIMPLBINU16 iemAImpl_arpl;
1509	/** @} */
1510
1511
1512	/** @name FPU operations taking a 32-bit float argument
1513	* @{ */
1514	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1515	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1516	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1517
1518	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1519	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1520	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1521
1522	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1523	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1524	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1525	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1526	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1527	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1528	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1529
1530	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1531	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1532	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1533	/** @} */
1534
1535	/** @name FPU operations taking a 64-bit float argument
1536	* @{ */
1537	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1538	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1539	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
1540
1541	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1542	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1543	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1544
1545	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
1546	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1547	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1548	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1549	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1550	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1551	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1552
1553	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1554	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1555	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1556	/** @} */
1557
1558	/** @name FPU operations taking a 80-bit float argument
1559	* @{ */
1560	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1561	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1562	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1563	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1564	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1565	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1566	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1567	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1568	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1569	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1570	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1571	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1572
1573	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
1574	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
1575	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
1576
1577	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1578	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1579	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1580	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1581	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1582
1583	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1584	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1585	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1586	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1587	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1588
1589	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1590	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1591	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1592	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1593	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
1594	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1595	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1596	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
1597	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
1598
1599	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1600	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1601	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1602	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1603
1604	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1605	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1606	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1607	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1608	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1609	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1610	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1611	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1612	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1613
1614	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1615	PCRTFLOAT80U pr80Val));
1616	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1617	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
1618	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1619	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
1620
1621	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1622	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1623	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1624
1625	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
1626	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1627	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
1628
1629	/** @} */
1630
1631	/** @name FPU operations taking a 16-bit signed integer argument
1632	* @{ */
1633	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1634	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1635	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1636	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1637	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
1638	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
1639
1640	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1641	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1642	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1643	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1644	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1645	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1646
1647	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1648	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1649	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
1650	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
1651
1652	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1653	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
1654	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
1655	/** @} */
1656
1657	/** @name FPU operations taking a 32-bit signed integer argument
1658	* @{ */
1659	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1660	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1661	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1662	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1663	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
1664	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
1665
1666	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1667	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1668	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1669	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1670	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1671	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1672
1673	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1674	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1675	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
1676	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
1677
1678	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1679	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
1680	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
1681	/** @} */
1682
1683	/** @name FPU operations taking a 64-bit signed integer argument
1684	* @{ */
1685	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1686	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
1687	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
1688
1689	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1690	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
1691	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
1692	/** @} */
1693
1694
1695	/** Temporary type representing a 256-bit vector register. */
1696	typedef struct { uint64_t au64[4]; } IEMVMM256;
1697	/** Temporary type pointing to a 256-bit vector register. */
1698	typedef IEMVMM256 *PIEMVMM256;
1699	/** Temporary type pointing to a const 256-bit vector register. */
1700	typedef IEMVMM256 *PCIEMVMM256;
1701
1702
1703	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1704	* @{ */
1705	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1706	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1707	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1708	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1709	FNIEMAIMPLMEDIAF2U64 iemAImpl_pxor_u64, iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1710	FNIEMAIMPLMEDIAF2U128 iemAImpl_pxor_u128, iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1711	/** @} */
1712
1713	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1714	* @{ */
1715	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint32_t const pu32Src));
1716	typedef FNIEMAIMPLMEDIAF1L1U64 *PFNIEMAIMPLMEDIAF1L1U64;
1717	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1L1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, uint64_t const *pu64Src));
1718	typedef FNIEMAIMPLMEDIAF1L1U128 *PFNIEMAIMPLMEDIAF1L1U128;
1719	FNIEMAIMPLMEDIAF1L1U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1720	FNIEMAIMPLMEDIAF1L1U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1721	/** @} */
1722
1723	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
1724	* @{ */
1725	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1726	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF1H1U64;
1727	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF1H1U128,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst, PCRTUINT128U pu128Src));
1728	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF1H1U128;
1729	FNIEMAIMPLMEDIAF1H1U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
1730	FNIEMAIMPLMEDIAF1H1U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
1731	/** @} */
1732
1733	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
1734	* @{ */
1735	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUF,(PCX86FXSTATE pFpuState, PRTUINT128U pu128Dst,
1736	PCRTUINT128U pu128Src, uint8_t bEvil));
1737	typedef FNIEMAIMPLMEDIAPSHUF *PFNIEMAIMPLMEDIAPSHUF;
1738	FNIEMAIMPLMEDIAPSHUF iemAImpl_pshufhw, iemAImpl_pshuflw, iemAImpl_pshufd;
1739	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src, uint8_t bEvil));
1740	/** @} */
1741
1742	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
1743	* @{ */
1744	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(PCX86FXSTATE pFpuState, uint64_t pu64Dst, uint64_t const pu64Src));
1745	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(PCX86FXSTATE pFpuState, uint64_t *pu64Dst, PCRTUINT128U pu128Src));
1746	/** @} */
1747
1748	/** @name Media (SSE/MMX/AVX) operation: Sort this later
1749	* @{ */
1750	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1751	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1752	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, uint64_t uSrc));
1753
1754	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1755	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1756	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
1757	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
1758
1759	/** @} */
1760
1761
1762	/** @name Function tables.
1763	* @{
1764	*/
1765
1766	/**
1767	* Function table for a binary operator providing implementation based on
1768	* operand size.
1769	*/
1770	typedef struct IEMOPBINSIZES
1771	{
1772	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
1773	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
1774	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
1775	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
1776	} IEMOPBINSIZES;
1777	/** Pointer to a binary operator function table. */
1778	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
1779
1780
1781	/**
1782	* Function table for a unary operator providing implementation based on
1783	* operand size.
1784	*/
1785	typedef struct IEMOPUNARYSIZES
1786	{
1787	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
1788	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
1789	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
1790	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
1791	} IEMOPUNARYSIZES;
1792	/** Pointer to a unary operator function table. */
1793	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
1794
1795
1796	/**
1797	* Function table for a shift operator providing implementation based on
1798	* operand size.
1799	*/
1800	typedef struct IEMOPSHIFTSIZES
1801	{
1802	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
1803	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
1804	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
1805	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
1806	} IEMOPSHIFTSIZES;
1807	/** Pointer to a shift operator function table. */
1808	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
1809
1810
1811	/**
1812	* Function table for a multiplication or division operation.
1813	*/
1814	typedef struct IEMOPMULDIVSIZES
1815	{
1816	PFNIEMAIMPLMULDIVU8 pfnU8;
1817	PFNIEMAIMPLMULDIVU16 pfnU16;
1818	PFNIEMAIMPLMULDIVU32 pfnU32;
1819	PFNIEMAIMPLMULDIVU64 pfnU64;
1820	} IEMOPMULDIVSIZES;
1821	/** Pointer to a multiplication or division operation function table. */
1822	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
1823
1824
1825	/**
1826	* Function table for a double precision shift operator providing implementation
1827	* based on operand size.
1828	*/
1829	typedef struct IEMOPSHIFTDBLSIZES
1830	{
1831	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
1832	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
1833	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
1834	} IEMOPSHIFTDBLSIZES;
1835	/** Pointer to a double precision shift function table. */
1836	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
1837
1838
1839	/**
1840	* Function table for media instruction taking two full sized media registers,
1841	* optionally the 2nd being a memory reference (only modifying the first op.)
1842	*/
1843	typedef struct IEMOPMEDIAF2
1844	{
1845	PFNIEMAIMPLMEDIAF2U64 pfnU64;
1846	PFNIEMAIMPLMEDIAF2U128 pfnU128;
1847	} IEMOPMEDIAF2;
1848	/** Pointer to a media operation function table for full sized ops. */
1849	typedef IEMOPMEDIAF2 const *PCIEMOPMEDIAF2;
1850
1851	/**
1852	* Function table for media instruction taking taking one full and one lower
1853	* half media register.
1854	*/
1855	typedef struct IEMOPMEDIAF1L1
1856	{
1857	PFNIEMAIMPLMEDIAF1L1U64 pfnU64;
1858	PFNIEMAIMPLMEDIAF1L1U128 pfnU128;
1859	} IEMOPMEDIAF1L1;
1860	/** Pointer to a media operation function table for lowhalf+lowhalf -> full. */
1861	typedef IEMOPMEDIAF1L1 const *PCIEMOPMEDIAF1L1;
1862
1863	/**
1864	* Function table for media instruction taking taking one full and one high half
1865	* media register.
1866	*/
1867	typedef struct IEMOPMEDIAF1H1
1868	{
1869	PFNIEMAIMPLMEDIAF1H1U64 pfnU64;
1870	PFNIEMAIMPLMEDIAF1H1U128 pfnU128;
1871	} IEMOPMEDIAF1H1;
1872	/** Pointer to a media operation function table for hihalf+hihalf -> full. */
1873	typedef IEMOPMEDIAF1H1 const *PCIEMOPMEDIAF1H1;
1874
1875
1876	/** @} */
1877
1878
1879	/** @name C instruction implementations for anything slightly complicated.
1880	* @{ */
1881
1882	/**
1883	* For typedef'ing or declaring a C instruction implementation function taking
1884	* no extra arguments.
1885	*
1886	* @param a_Name The name of the type.
1887	*/
1888	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
1889	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
1890	/**
1891	* For defining a C instruction implementation function taking no extra
1892	* arguments.
1893	*
1894	* @param a_Name The name of the function
1895	*/
1896	# define IEM_CIMPL_DEF_0(a_Name) \
1897	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
1898	/**
1899	* Prototype version of IEM_CIMPL_DEF_0.
1900	*/
1901	# define IEM_CIMPL_PROTO_0(a_Name) \
1902	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
1903	/**
1904	* For calling a C instruction implementation function taking no extra
1905	* arguments.
1906	*
1907	* This special call macro adds default arguments to the call and allow us to
1908	* change these later.
1909	*
1910	* @param a_fn The name of the function.
1911	*/
1912	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
1913
1914	/**
1915	* For typedef'ing or declaring a C instruction implementation function taking
1916	* one extra argument.
1917	*
1918	* @param a_Name The name of the type.
1919	* @param a_Type0 The argument type.
1920	* @param a_Arg0 The argument name.
1921	*/
1922	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
1923	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1924	/**
1925	* For defining a C instruction implementation function taking one extra
1926	* argument.
1927	*
1928	* @param a_Name The name of the function
1929	* @param a_Type0 The argument type.
1930	* @param a_Arg0 The argument name.
1931	*/
1932	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
1933	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1934	/**
1935	* Prototype version of IEM_CIMPL_DEF_1.
1936	*/
1937	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
1938	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
1939	/**
1940	* For calling a C instruction implementation function taking one extra
1941	* argument.
1942	*
1943	* This special call macro adds default arguments to the call and allow us to
1944	* change these later.
1945	*
1946	* @param a_fn The name of the function.
1947	* @param a0 The name of the 1st argument.
1948	*/
1949	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
1950
1951	/**
1952	* For typedef'ing or declaring a C instruction implementation function taking
1953	* two extra arguments.
1954	*
1955	* @param a_Name The name of the type.
1956	* @param a_Type0 The type of the 1st argument
1957	* @param a_Arg0 The name of the 1st argument.
1958	* @param a_Type1 The type of the 2nd argument.
1959	* @param a_Arg1 The name of the 2nd argument.
1960	*/
1961	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1962	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1963	/**
1964	* For defining a C instruction implementation function taking two extra
1965	* arguments.
1966	*
1967	* @param a_Name The name of the function.
1968	* @param a_Type0 The type of the 1st argument
1969	* @param a_Arg0 The name of the 1st argument.
1970	* @param a_Type1 The type of the 2nd argument.
1971	* @param a_Arg1 The name of the 2nd argument.
1972	*/
1973	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1974	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1975	/**
1976	* Prototype version of IEM_CIMPL_DEF_2.
1977	*/
1978	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
1979	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
1980	/**
1981	* For calling a C instruction implementation function taking two extra
1982	* arguments.
1983	*
1984	* This special call macro adds default arguments to the call and allow us to
1985	* change these later.
1986	*
1987	* @param a_fn The name of the function.
1988	* @param a0 The name of the 1st argument.
1989	* @param a1 The name of the 2nd argument.
1990	*/
1991	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
1992
1993	/**
1994	* For typedef'ing or declaring a C instruction implementation function taking
1995	* three extra arguments.
1996	*
1997	* @param a_Name The name of the type.
1998	* @param a_Type0 The type of the 1st argument
1999	* @param a_Arg0 The name of the 1st argument.
2000	* @param a_Type1 The type of the 2nd argument.
2001	* @param a_Arg1 The name of the 2nd argument.
2002	* @param a_Type2 The type of the 3rd argument.
2003	* @param a_Arg2 The name of the 3rd argument.
2004	*/
2005	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2006	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2007	/**
2008	* For defining a C instruction implementation function taking three extra
2009	* arguments.
2010	*
2011	* @param a_Name The name of the function.
2012	* @param a_Type0 The type of the 1st argument
2013	* @param a_Arg0 The name of the 1st argument.
2014	* @param a_Type1 The type of the 2nd argument.
2015	* @param a_Arg1 The name of the 2nd argument.
2016	* @param a_Type2 The type of the 3rd argument.
2017	* @param a_Arg2 The name of the 3rd argument.
2018	*/
2019	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2020	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2021	/**
2022	* Prototype version of IEM_CIMPL_DEF_3.
2023	*/
2024	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2025	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2026	/**
2027	* For calling a C instruction implementation function taking three extra
2028	* arguments.
2029	*
2030	* This special call macro adds default arguments to the call and allow us to
2031	* change these later.
2032	*
2033	* @param a_fn The name of the function.
2034	* @param a0 The name of the 1st argument.
2035	* @param a1 The name of the 2nd argument.
2036	* @param a2 The name of the 3rd argument.
2037	*/
2038	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
2039
2040
2041	/**
2042	* For typedef'ing or declaring a C instruction implementation function taking
2043	* four extra arguments.
2044	*
2045	* @param a_Name The name of the type.
2046	* @param a_Type0 The type of the 1st argument
2047	* @param a_Arg0 The name of the 1st argument.
2048	* @param a_Type1 The type of the 2nd argument.
2049	* @param a_Arg1 The name of the 2nd argument.
2050	* @param a_Type2 The type of the 3rd argument.
2051	* @param a_Arg2 The name of the 3rd argument.
2052	* @param a_Type3 The type of the 4th argument.
2053	* @param a_Arg3 The name of the 4th argument.
2054	*/
2055	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
2056	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
2057	/**
2058	* For defining a C instruction implementation function taking four extra
2059	* arguments.
2060	*
2061	* @param a_Name The name of the function.
2062	* @param a_Type0 The type of the 1st argument
2063	* @param a_Arg0 The name of the 1st argument.
2064	* @param a_Type1 The type of the 2nd argument.
2065	* @param a_Arg1 The name of the 2nd argument.
2066	* @param a_Type2 The type of the 3rd argument.
2067	* @param a_Arg2 The name of the 3rd argument.
2068	* @param a_Type3 The type of the 4th argument.
2069	* @param a_Arg3 The name of the 4th argument.
2070	*/
2071	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
2072	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2073	a_Type2 a_Arg2, a_Type3 a_Arg3))
2074	/**
2075	* Prototype version of IEM_CIMPL_DEF_4.
2076	*/
2077	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
2078	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2079	a_Type2 a_Arg2, a_Type3 a_Arg3))
2080	/**
2081	* For calling a C instruction implementation function taking four extra
2082	* arguments.
2083	*
2084	* This special call macro adds default arguments to the call and allow us to
2085	* change these later.
2086	*
2087	* @param a_fn The name of the function.
2088	* @param a0 The name of the 1st argument.
2089	* @param a1 The name of the 2nd argument.
2090	* @param a2 The name of the 3rd argument.
2091	* @param a3 The name of the 4th argument.
2092	*/
2093	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
2094
2095
2096	/**
2097	* For typedef'ing or declaring a C instruction implementation function taking
2098	* five extra arguments.
2099	*
2100	* @param a_Name The name of the type.
2101	* @param a_Type0 The type of the 1st argument
2102	* @param a_Arg0 The name of the 1st argument.
2103	* @param a_Type1 The type of the 2nd argument.
2104	* @param a_Arg1 The name of the 2nd argument.
2105	* @param a_Type2 The type of the 3rd argument.
2106	* @param a_Arg2 The name of the 3rd argument.
2107	* @param a_Type3 The type of the 4th argument.
2108	* @param a_Arg3 The name of the 4th argument.
2109	* @param a_Type4 The type of the 5th argument.
2110	* @param a_Arg4 The name of the 5th argument.
2111	*/
2112	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2113	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
2114	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
2115	a_Type3 a_Arg3, a_Type4 a_Arg4))
2116	/**
2117	* For defining a C instruction implementation function taking five extra
2118	* arguments.
2119	*
2120	* @param a_Name The name of the function.
2121	* @param a_Type0 The type of the 1st argument
2122	* @param a_Arg0 The name of the 1st argument.
2123	* @param a_Type1 The type of the 2nd argument.
2124	* @param a_Arg1 The name of the 2nd argument.
2125	* @param a_Type2 The type of the 3rd argument.
2126	* @param a_Arg2 The name of the 3rd argument.
2127	* @param a_Type3 The type of the 4th argument.
2128	* @param a_Arg3 The name of the 4th argument.
2129	* @param a_Type4 The type of the 5th argument.
2130	* @param a_Arg4 The name of the 5th argument.
2131	*/
2132	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2133	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2134	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
2135	/**
2136	* Prototype version of IEM_CIMPL_DEF_5.
2137	*/
2138	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2139	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2140	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
2141	/**
2142	* For calling a C instruction implementation function taking five extra
2143	* arguments.
2144	*
2145	* This special call macro adds default arguments to the call and allow us to
2146	* change these later.
2147	*
2148	* @param a_fn The name of the function.
2149	* @param a0 The name of the 1st argument.
2150	* @param a1 The name of the 2nd argument.
2151	* @param a2 The name of the 3rd argument.
2152	* @param a3 The name of the 4th argument.
2153	* @param a4 The name of the 5th argument.
2154	*/
2155	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
2156
2157	/** @} */
2158
2159
2160	/** @name Opcode Decoder Function Types.
2161	* @{ */
2162
2163	/** @typedef PFNIEMOP
2164	* Pointer to an opcode decoder function.
2165	*/
2166
2167	/** @def FNIEMOP_DEF
2168	* Define an opcode decoder function.
2169	*
2170	* We're using macors for this so that adding and removing parameters as well as
2171	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
2172	*
2173	* @param a_Name The function name.
2174	*/
2175
2176	/** @typedef PFNIEMOPRM
2177	* Pointer to an opcode decoder function with RM byte.
2178	*/
2179
2180	/** @def FNIEMOPRM_DEF
2181	* Define an opcode decoder function with RM byte.
2182	*
2183	* We're using macors for this so that adding and removing parameters as well as
2184	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
2185	*
2186	* @param a_Name The function name.
2187	*/
2188
2189	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2190	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
2191	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2192	# define FNIEMOP_DEF(a_Name) \
2193	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
2194	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2195	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
2196	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2197	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
2198
2199	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2200	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
2201	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2202	# define FNIEMOP_DEF(a_Name) \
2203	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
2204	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2205	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
2206	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2207	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
2208
2209	#elif defined(__GNUC__)
2210	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
2211	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2212	# define FNIEMOP_DEF(a_Name) \
2213	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
2214	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2215	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
2216	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2217	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
2218
2219	#else
2220	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
2221	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2222	# define FNIEMOP_DEF(a_Name) \
2223	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
2224	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2225	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
2226	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2227	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
2228
2229	#endif
2230	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
2231
2232	/**
2233	* Call an opcode decoder function.
2234	*
2235	* We're using macors for this so that adding and removing parameters can be
2236	* done as we please. See FNIEMOP_DEF.
2237	*/
2238	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
2239
2240	/**
2241	* Call a common opcode decoder function taking one extra argument.
2242	*
2243	* We're using macors for this so that adding and removing parameters can be
2244	* done as we please. See FNIEMOP_DEF_1.
2245	*/
2246	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
2247
2248	/**
2249	* Call a common opcode decoder function taking one extra argument.
2250	*
2251	* We're using macors for this so that adding and removing parameters can be
2252	* done as we please. See FNIEMOP_DEF_1.
2253	*/
2254	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
2255	/** @} */
2256
2257
2258	/** @name Misc Helpers
2259	* @{ */
2260
2261	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
2262	* due to GCC lacking knowledge about the value range of a switch. */
2263	#define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
2264
2265	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
2266	#define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
2267
2268	/**
2269	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
2270	* occation.
2271	*/
2272	#ifdef LOG_ENABLED
2273	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
2274	do { \
2275	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
2276	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
2277	} while (0)
2278	#else
2279	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
2280	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
2281	#endif
2282
2283	/**
2284	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
2285	* occation using the supplied logger statement.
2286	*
2287	* @param a_LoggerArgs What to log on failure.
2288	*/
2289	#ifdef LOG_ENABLED
2290	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
2291	do { \
2292	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
2293	/LogFunc(a_LoggerArgs);/ \
2294	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
2295	} while (0)
2296	#else
2297	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
2298	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
2299	#endif
2300
2301	/**
2302	* Check if we're currently executing in real or virtual 8086 mode.
2303	*
2304	* @returns @c true if it is, @c false if not.
2305	* @param a_pVCpu The IEM state of the current CPU.
2306	*/
2307	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (CPUMIsGuestInRealOrV86ModeEx(IEM_GET_CTX(a_pVCpu)))
2308
2309	/**
2310	* Check if we're currently executing in virtual 8086 mode.
2311	*
2312	* @returns @c true if it is, @c false if not.
2313	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2314	*/
2315	#define IEM_IS_V86_MODE(a_pVCpu) (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(a_pVCpu)))
2316
2317	/**
2318	* Check if we're currently executing in long mode.
2319	*
2320	* @returns @c true if it is, @c false if not.
2321	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2322	*/
2323	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
2324
2325	/**
2326	* Check if we're currently executing in a 64-bit code segment.
2327	*
2328	* @returns @c true if it is, @c false if not.
2329	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2330	*/
2331	#define IEM_IS_64BIT_CODE(a_pVCpu) (CPUMIsGuestIn64BitCodeEx(IEM_GET_CTX(a_pVCpu)))
2332
2333	/**
2334	* Check if we're currently executing in real mode.
2335	*
2336	* @returns @c true if it is, @c false if not.
2337	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2338	*/
2339	#define IEM_IS_REAL_MODE(a_pVCpu) (CPUMIsGuestInRealModeEx(IEM_GET_CTX(a_pVCpu)))
2340
2341	/**
2342	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
2343	* @returns PCCPUMFEATURES
2344	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2345	*/
2346	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
2347
2348	/**
2349	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
2350	* @returns PCCPUMFEATURES
2351	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2352	*/
2353	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
2354
2355	/**
2356	* Evaluates to true if we're presenting an Intel CPU to the guest.
2357	*/
2358	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
2359
2360	/**
2361	* Evaluates to true if we're presenting an AMD CPU to the guest.
2362	*/
2363	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
2364
2365	/**
2366	* Check if the address is canonical.
2367	*/
2368	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
2369
2370
2371	/**
2372	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
2373	*
2374	* For use during decoding.
2375	*/
2376	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
2377	/**
2378	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
2379	*
2380	* For use during decoding.
2381	*/
2382	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
2383
2384	/**
2385	* Gets the effective VEX.VVVV value.
2386	*
2387	* The 4th bit is ignored if not 64-bit code.
2388	* @returns effective V-register value.
2389	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2390	*/
2391	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
2392	((a_pVCpu)->iem.s.enmCpuMode == IEMMODE_64BIT ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
2393
2394
2395	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2396
2397	/**
2398	* Check if the guest has entered VMX root operation.
2399	*/
2400	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
2401
2402	/**
2403	* Check if the guest has entered VMX non-root operation.
2404	*/
2405	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(a_pVCpu)))
2406
2407	/**
2408	* Check if the nested-guest has the given Pin-based VM-execution control set.
2409	*/
2410	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) \
2411	(CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
2412
2413	/**
2414	* Check if the nested-guest has the given Processor-based VM-execution control set.
2415	*/
2416	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) \
2417	(CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
2418
2419	/**
2420	* Check if the nested-guest has the given Secondary Processor-based VM-execution
2421	* control set.
2422	*/
2423	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) \
2424	(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
2425
2426	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
2427	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
2428
2429	/** Whether a shadow VMCS is present for the given VCPU. */
2430	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
2431
2432	/** Gets the VMXON region pointer. */
2433	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
2434
2435	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
2436	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
2437
2438	/** Whether a current VMCS is present for the given VCPU. */
2439	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
2440
2441	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
2442	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
2443	do \
2444	{ \
2445	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
2446	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
2447	} while (0)
2448
2449	/** Clears any current VMCS for the given VCPU. */
2450	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
2451	do \
2452	{ \
2453	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
2454	} while (0)
2455
2456	/**
2457	* Invokes the VMX VM-exit handler for an instruction intercept.
2458	*/
2459	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
2460	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
2461
2462	/**
2463	* Invokes the VMX VM-exit handler for an instruction intercept where the
2464	* instruction provides additional VM-exit information.
2465	*/
2466	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
2467	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
2468
2469	/**
2470	* Invokes the VMX VM-exit handler for a task switch.
2471	*/
2472	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
2473	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
2474
2475	/**
2476	* Invokes the VMX VM-exit handler for MWAIT.
2477	*/
2478	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
2479	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
2480
2481	/**
2482	* Invokes the VMX VM-exit handler for EPT faults.
2483	*/
2484	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
2485	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
2486
2487	/**
2488	* Invokes the VMX VM-exit handler.
2489	*/
2490	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
2491	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
2492
2493	#else
2494	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
2495	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
2496	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
2497	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
2498	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
2499	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2500	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2501	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2502	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2503	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
2504	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
2505
2506	#endif
2507
2508	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
2509	/**
2510	* Check if an SVM control/instruction intercept is set.
2511	*/
2512	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
2513	(CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
2514
2515	/**
2516	* Check if an SVM read CRx intercept is set.
2517	*/
2518	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
2519	(CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
2520
2521	/**
2522	* Check if an SVM write CRx intercept is set.
2523	*/
2524	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
2525	(CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
2526
2527	/**
2528	* Check if an SVM read DRx intercept is set.
2529	*/
2530	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
2531	(CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
2532
2533	/**
2534	* Check if an SVM write DRx intercept is set.
2535	*/
2536	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
2537	(CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
2538
2539	/**
2540	* Check if an SVM exception intercept is set.
2541	*/
2542	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
2543	(CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
2544
2545	/**
2546	* Invokes the SVM \#VMEXIT handler for the nested-guest.
2547	*/
2548	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
2549	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
2550
2551	/**
2552	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
2553	* corresponding decode assist information.
2554	*/
2555	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
2556	do \
2557	{ \
2558	uint64_t uExitInfo1; \
2559	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
2560	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
2561	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
2562	else \
2563	uExitInfo1 = 0; \
2564	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
2565	} while (0)
2566
2567	/** Check and handles SVM nested-guest instruction intercept and updates
2568	* NRIP if needed.
2569	*/
2570	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
2571	do \
2572	{ \
2573	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
2574	{ \
2575	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
2576	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
2577	} \
2578	} while (0)
2579
2580	/** Checks and handles SVM nested-guest CR0 read intercept. */
2581	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) \
2582	do \
2583	{ \
2584	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
2585	{ /* probably likely */ } \
2586	else \
2587	{ \
2588	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
2589	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
2590	} \
2591	} while (0)
2592
2593	/**
2594	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
2595	*/
2596	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) \
2597	do { \
2598	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
2599	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), IEM_GET_INSTR_LEN(a_pVCpu)); \
2600	} while (0)
2601
2602	#else
2603	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
2604	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
2605	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
2606	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
2607	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
2608	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
2609	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
2610	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
2611	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0)
2612	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) do { } while (0)
2613	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) do { } while (0)
2614
2615	#endif
2616
2617	/** @} */
2618
2619
2620
2621	/**
2622	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
2623	*/
2624	typedef union IEMSELDESC
2625	{
2626	/** The legacy view. */
2627	X86DESC Legacy;
2628	/** The long mode view. */
2629	X86DESC64 Long;
2630	} IEMSELDESC;
2631	/** Pointer to a selector descriptor table entry. */
2632	typedef IEMSELDESC *PIEMSELDESC;
2633
2634	/** @name Raising Exceptions.
2635	* @{ */
2636	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
2637	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
2638
2639	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
2640	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
2641	#ifdef IEM_WITH_SETJMP
2642	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
2643	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
2644	#endif
2645	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
2646	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
2647	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
2648	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
2649	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
2650	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
2651	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
2652	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
2653	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
2654	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
2655	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
2656	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
2657	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
2658	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
2659	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
2660	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
2661	#ifdef IEM_WITH_SETJMP
2662	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2663	#endif
2664	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
2665	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
2666	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
2667	#ifdef IEM_WITH_SETJMP
2668	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
2669	#endif
2670	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
2671	#ifdef IEM_WITH_SETJMP
2672	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
2673	#endif
2674	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
2675	#ifdef IEM_WITH_SETJMP
2676	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
2677	#endif
2678	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
2679	#ifdef IEM_WITH_SETJMP
2680	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
2681	#endif
2682	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu);
2683	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu);
2684	#ifdef IEM_WITH_SETJMP
2685	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2686	#endif
2687
2688	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
2689	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
2690	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
2691
2692	/**
2693	* Macro for calling iemCImplRaiseDivideError().
2694	*
2695	* This enables us to add/remove arguments and force different levels of
2696	* inlining as we wish.
2697	*
2698	* @return Strict VBox status code.
2699	*/
2700	#define IEMOP_RAISE_DIVIDE_ERROR() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseDivideError)
2701
2702	/**
2703	* Macro for calling iemCImplRaiseInvalidLockPrefix().
2704	*
2705	* This enables us to add/remove arguments and force different levels of
2706	* inlining as we wish.
2707	*
2708	* @return Strict VBox status code.
2709	*/
2710	#define IEMOP_RAISE_INVALID_LOCK_PREFIX() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidLockPrefix)
2711
2712	/**
2713	* Macro for calling iemCImplRaiseInvalidOpcode().
2714	*
2715	* This enables us to add/remove arguments and force different levels of
2716	* inlining as we wish.
2717	*
2718	* @return Strict VBox status code.
2719	*/
2720	#define IEMOP_RAISE_INVALID_OPCODE() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidOpcode)
2721	/** @} */
2722
2723	/** @name Register Access.
2724	* @{ */
2725	VBOXSTRICTRC iemRegRipRelativeJumpS8(PVMCPUCC pVCpu, int8_t offNextInstr) RT_NOEXCEPT;
2726	VBOXSTRICTRC iemRegRipRelativeJumpS16(PVMCPUCC pVCpu, int16_t offNextInstr) RT_NOEXCEPT;
2727	VBOXSTRICTRC iemRegRipRelativeJumpS32(PVMCPUCC pVCpu, int32_t offNextInstr) RT_NOEXCEPT;
2728	VBOXSTRICTRC iemRegRipJump(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
2729	/** @} */
2730
2731	/** @name FPU access and helpers.
2732	* @{ */
2733	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult) RT_NOEXCEPT;
2734	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2735	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult) RT_NOEXCEPT;
2736	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
2737	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
2738	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
2739	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2740	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
2741	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2742	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2743	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
2744	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
2745	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2746	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
2747	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2748	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
2749	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2750	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
2751	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2752	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu) RT_NOEXCEPT;
2753	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
2754	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu) RT_NOEXCEPT;
2755	void iemFpuStackPushOverflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
2756	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
2757	/** @} */
2758
2759	/** @name Memory access.
2760	* @{ */
2761	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t fAccess) RT_NOEXCEPT;
2762	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
2763	#ifndef IN_RING3
2764	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
2765	#endif
2766	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
2767	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
2768	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
2769	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
2770
2771	#ifdef IEM_WITH_CODE_TLB
2772	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) RT_NOEXCEPT;
2773	#else
2774	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
2775	#endif
2776	#ifdef IEM_WITH_SETJMP
2777	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2778	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2779	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2780	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
2781	#else
2782	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
2783	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
2784	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
2785	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2786	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
2787	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
2788	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2789	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
2790	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2791	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2792	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
2793	#endif
2794
2795	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2796	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2797	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2798	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2799	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2800	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2801	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2802	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2803	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2804	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2805	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2806	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2807	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
2808	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
2809	#ifdef IEM_WITH_SETJMP
2810	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2811	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2812	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2813	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2814	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2815	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2816	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2817	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2818	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2819	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2820	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2821	#endif
2822
2823	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2824	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2825	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2826	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2827	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
2828
2829	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
2830	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
2831	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
2832	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
2833	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
2834	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
2835	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
2836	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
2837	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
2838	#ifdef IEM_WITH_SETJMP
2839	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
2840	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
2841	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
2842	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
2843	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
2844	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
2845	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
2846	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
2847	#endif
2848
2849	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
2850	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
2851	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
2852	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
2853	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
2854	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2855	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2856	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2857	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
2858	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
2859	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t cbMem, void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
2860	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
2861	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
2862	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
2863	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
2864	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2865	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2866	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
2867	/** @} */
2868
2869	/** @name IEMAllCImpl.cpp
2870	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
2871	* @{ */
2872	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
2873	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
2874	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
2875	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
2876	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
2877	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
2878	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
2879	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
2880	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
2881	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
2882	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
2883	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
2884	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
2885	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
2886	IEM_CIMPL_PROTO_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
2887	IEM_CIMPL_PROTO_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
2888	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
2889	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
2890	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
2891	IEM_CIMPL_PROTO_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop);
2892	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
2893	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
2894	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
2895	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
2896	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
2897	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
2898	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
2899	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
2900	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
2901	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
2902	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
2903	IEM_CIMPL_PROTO_0(iemCImpl_sysret);
2904	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
2905	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
2906	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
2907	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
2908	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
2909	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
2910	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
2911	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
2912	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
2913	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
2914	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2915	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
2916	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2917	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
2918	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
2919	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2920	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
2921	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
2922	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2923	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
2924	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
2925	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2926	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
2927	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
2928	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
2929	IEM_CIMPL_PROTO_0(iemCImpl_clts);
2930	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
2931	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
2932	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
2933	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
2934	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
2935	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
2936	IEM_CIMPL_PROTO_0(iemCImpl_invd);
2937	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
2938	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
2939	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
2940	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
2941	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
2942	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
2943	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
2944	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
2945	IEM_CIMPL_PROTO_1(iemCImpl_in_eAX_DX, uint8_t, cbReg);
2946	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
2947	IEM_CIMPL_PROTO_1(iemCImpl_out_DX_eAX, uint8_t, cbReg);
2948	IEM_CIMPL_PROTO_0(iemCImpl_cli);
2949	IEM_CIMPL_PROTO_0(iemCImpl_sti);
2950	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
2951	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
2952	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
2953	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
2954	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
2955	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
2956	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
2957	IEM_CIMPL_PROTO_0(iemCImpl_daa);
2958	IEM_CIMPL_PROTO_0(iemCImpl_das);
2959	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
2960	IEM_CIMPL_PROTO_0(iemCImpl_aas);
2961	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
2962	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
2963	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
2964	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
2965	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
2966	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
2967	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
2968	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
2969	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
2970	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
2971	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
2972	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
2973	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
2974	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
2975	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
2976	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2977	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
2978	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
2979	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
2980	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
2981	IEM_CIMPL_PROTO_1(iemCImpl_fxch_underflow, uint8_t, iStReg);
2982	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop);
2983	/** @} */
2984
2985	/** @name IEMAllCImplStrInstr.cpp.h
2986	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
2987	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
2988	* @{ */
2989	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
2990	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
2991	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
2992	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
2993	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
2994	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
2995	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
2996	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
2997	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
2998	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
2999	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3000
3001	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
3002	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
3003	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
3004	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
3005	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
3006	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
3007	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
3008	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
3009	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
3010	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3011	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3012
3013	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
3014	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
3015	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
3016	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
3017	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
3018	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
3019	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
3020	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
3021	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
3022	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3023	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3024
3025
3026	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
3027	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
3028	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
3029	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
3030	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
3031	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
3032	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
3033	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
3034	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
3035	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3036	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3037
3038	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
3039	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
3040	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
3041	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
3042	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
3043	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
3044	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
3045	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
3046	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
3047	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3048	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3049
3050	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
3051	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
3052	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
3053	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
3054	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
3055	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
3056	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
3057	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
3058	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
3059	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3060	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3061
3062	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
3063	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
3064	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
3065	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
3066	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
3067	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
3068	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
3069	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
3070	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
3071	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3072	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3073
3074
3075	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
3076	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
3077	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
3078	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
3079	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
3080	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
3081	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
3082	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
3083	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
3084	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3085	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3086
3087	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
3088	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
3089	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
3090	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
3091	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
3092	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
3093	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
3094	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
3095	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
3096	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3097	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3098
3099	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
3100	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
3101	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
3102	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
3103	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
3104	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
3105	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
3106	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
3107	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
3108	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3109	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3110
3111	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
3112	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
3113	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
3114	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
3115	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
3116	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
3117	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
3118	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
3119	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
3120	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3121	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3122	/** @} */
3123
3124	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3125	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
3126	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
3127	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
3128	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
3129	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
3130	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
3131	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
3132	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
3133	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
3134	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3135	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
3136	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3137	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
3138	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3139	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3140	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3141	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3142	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3143	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3144	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
3145	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
3146	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
3147	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
3148	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
3149	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
3150	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
3151	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
3152	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
3153	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
3154	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
3155	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
3156	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
3157	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
3158	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
3159	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3160	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3161	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3162	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
3163	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
3164	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
3165	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField);
3166	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
3167	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
3168	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
3169	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
3170	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
3171	#endif
3172
3173	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3174	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
3175	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3176	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
3177	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
3178	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite) RT_NOEXCEPT;
3179	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
3180	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
3181	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
3182	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
3183	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
3184	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
3185	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
3186	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
3187	#endif
3188
3189	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
3190	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
3191	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
3192
3193
3194	extern const PFNIEMOP g_apfnOneByteMap[256];
3195
3196	/** @} */
3197
3198	RT_C_DECLS_END
3199
3200	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
3201

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 95308

Download in other formats: