IEMInternal.h@ 96379

Last change on this file since 96379 was 96379, checked in by vboxsync, 2 years ago
VMM/IEM: Implement cvtss2sd/cvtsd2ss instructions + some streamlinging of the instruction helpers and fixes, bugref:9898
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File size: 194.4 KB

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1	/* $Id: IEMInternal.h 96379 2022-08-20 19:23:07Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
19	#define VMM_INCLUDED_SRC_include_IEMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/vmm/cpum.h>
25	#include <VBox/vmm/iem.h>
26	#include <VBox/vmm/pgm.h>
27	#include <VBox/vmm/stam.h>
28	#include <VBox/param.h>
29
30	#include <iprt/setjmp-without-sigmask.h>
31
32
33	RT_C_DECLS_BEGIN
34
35
36	/** @defgroup grp_iem_int Internals
37	* @ingroup grp_iem
38	* @internal
39	* @{
40	*/
41
42	/** For expanding symbol in slickedit and other products tagging and
43	* crossreferencing IEM symbols. */
44	#ifndef IEM_STATIC
45	# define IEM_STATIC static
46	#endif
47
48	/** @def IEM_WITH_SETJMP
49	* Enables alternative status code handling using setjmps.
50	*
51	* This adds a bit of expense via the setjmp() call since it saves all the
52	* non-volatile registers. However, it eliminates return code checks and allows
53	* for more optimal return value passing (return regs instead of stack buffer).
54	*/
55	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
56	# define IEM_WITH_SETJMP
57	#endif
58
59	#define IEM_IMPLEMENTS_TASKSWITCH
60
61	/** @def IEM_WITH_3DNOW
62	* Includes the 3DNow decoding. */
63	#define IEM_WITH_3DNOW
64
65	/** @def IEM_WITH_THREE_0F_38
66	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
67	#define IEM_WITH_THREE_0F_38
68
69	/** @def IEM_WITH_THREE_0F_3A
70	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
71	#define IEM_WITH_THREE_0F_3A
72
73	/** @def IEM_WITH_VEX
74	* Includes the VEX decoding. */
75	#define IEM_WITH_VEX
76
77	/** @def IEM_CFG_TARGET_CPU
78	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
79	*
80	* By default we allow this to be configured by the user via the
81	* CPUM/GuestCpuName config string, but this comes at a slight cost during
82	* decoding. So, for applications of this code where there is no need to
83	* be dynamic wrt target CPU, just modify this define.
84	*/
85	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
86	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
87	#endif
88
89	//#define IEM_WITH_CODE_TLB // - work in progress
90	//#define IEM_WITH_DATA_TLB // - work in progress
91
92
93	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
94	* Use unaligned accesses instead of elaborate byte assembly. */
95	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
96	# define IEM_USE_UNALIGNED_DATA_ACCESS
97	#endif
98
99	//#define IEM_LOG_MEMORY_WRITES
100
101	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
102	/** Instruction statistics. */
103	typedef struct IEMINSTRSTATS
104	{
105	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
106	# include "IEMInstructionStatisticsTmpl.h"
107	# undef IEM_DO_INSTR_STAT
108	} IEMINSTRSTATS;
109	#else
110	struct IEMINSTRSTATS;
111	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
112	#endif
113	/** Pointer to IEM instruction statistics. */
114	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
115
116
117	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
118	* @{ */
119	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
120	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
121	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
122	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
123	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
124	/** Selects the right variant from a_aArray.
125	* pVCpu is implicit in the caller context. */
126	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
127	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
128	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
129	* be used because the host CPU does not support the operation. */
130	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
131	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
132	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
133	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
134	* into the two.
135	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
136	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
137	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
138	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
139	#else
140	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
141	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
142	#endif
143	/** @} */
144
145	/**
146	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
147	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
148	*
149	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
150	* indicator.
151	*
152	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
153	*/
154	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
155	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
156	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
157	#else
158	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
159	#endif
160
161
162	/**
163	* Extended operand mode that includes a representation of 8-bit.
164	*
165	* This is used for packing down modes when invoking some C instruction
166	* implementations.
167	*/
168	typedef enum IEMMODEX
169	{
170	IEMMODEX_16BIT = IEMMODE_16BIT,
171	IEMMODEX_32BIT = IEMMODE_32BIT,
172	IEMMODEX_64BIT = IEMMODE_64BIT,
173	IEMMODEX_8BIT
174	} IEMMODEX;
175	AssertCompileSize(IEMMODEX, 4);
176
177
178	/**
179	* Branch types.
180	*/
181	typedef enum IEMBRANCH
182	{
183	IEMBRANCH_JUMP = 1,
184	IEMBRANCH_CALL,
185	IEMBRANCH_TRAP,
186	IEMBRANCH_SOFTWARE_INT,
187	IEMBRANCH_HARDWARE_INT
188	} IEMBRANCH;
189	AssertCompileSize(IEMBRANCH, 4);
190
191
192	/**
193	* INT instruction types.
194	*/
195	typedef enum IEMINT
196	{
197	/** INT n instruction (opcode 0xcd imm). */
198	IEMINT_INTN = 0,
199	/** Single byte INT3 instruction (opcode 0xcc). */
200	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
201	/** Single byte INTO instruction (opcode 0xce). */
202	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
203	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
204	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
205	} IEMINT;
206	AssertCompileSize(IEMINT, 4);
207
208
209	/**
210	* A FPU result.
211	*/
212	typedef struct IEMFPURESULT
213	{
214	/** The output value. */
215	RTFLOAT80U r80Result;
216	/** The output status. */
217	uint16_t FSW;
218	} IEMFPURESULT;
219	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
220	/** Pointer to a FPU result. */
221	typedef IEMFPURESULT *PIEMFPURESULT;
222	/** Pointer to a const FPU result. */
223	typedef IEMFPURESULT const *PCIEMFPURESULT;
224
225
226	/**
227	* A FPU result consisting of two output values and FSW.
228	*/
229	typedef struct IEMFPURESULTTWO
230	{
231	/** The first output value. */
232	RTFLOAT80U r80Result1;
233	/** The output status. */
234	uint16_t FSW;
235	/** The second output value. */
236	RTFLOAT80U r80Result2;
237	} IEMFPURESULTTWO;
238	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
239	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
240	/** Pointer to a FPU result consisting of two output values and FSW. */
241	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
242	/** Pointer to a const FPU result consisting of two output values and FSW. */
243	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
244
245
246	/**
247	* IEM TLB entry.
248	*
249	* Lookup assembly:
250	* @code{.asm}
251	; Calculate tag.
252	mov rax, [VA]
253	shl rax, 16
254	shr rax, 16 + X86_PAGE_SHIFT
255	or rax, [uTlbRevision]
256
257	; Do indexing.
258	movzx ecx, al
259	lea rcx, [pTlbEntries + rcx]
260
261	; Check tag.
262	cmp [rcx + IEMTLBENTRY.uTag], rax
263	jne .TlbMiss
264
265	; Check access.
266	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
267	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
268	cmp rax, [uTlbPhysRev]
269	jne .TlbMiss
270
271	; Calc address and we're done.
272	mov eax, X86_PAGE_OFFSET_MASK
273	and eax, [VA]
274	or rax, [rcx + IEMTLBENTRY.pMappingR3]
275	%ifdef VBOX_WITH_STATISTICS
276	inc qword [cTlbHits]
277	%endif
278	jmp .Done
279
280	.TlbMiss:
281	mov r8d, ACCESS_FLAGS
282	mov rdx, [VA]
283	mov rcx, [pVCpu]
284	call iemTlbTypeMiss
285	.Done:
286
287	@endcode
288	*
289	*/
290	typedef struct IEMTLBENTRY
291	{
292	/** The TLB entry tag.
293	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
294	* is ASSUMING a virtual address width of 48 bits.
295	*
296	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
297	*
298	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
299	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
300	* revision wraps around though, the tags needs to be zeroed.
301	*
302	* @note Try use SHRD instruction? After seeing
303	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
304	*
305	* @todo This will need to be reorganized for 57-bit wide virtual address and
306	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
307	* have to move the TLB entry versioning entirely to the
308	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
309	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
310	* consumed by PCID and ASID (12 + 6 = 18).
311	*/
312	uint64_t uTag;
313	/** Access flags and physical TLB revision.
314	*
315	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
316	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
317	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
318	* - Bit 3 - pgm phys/virt - not directly writable.
319	* - Bit 4 - pgm phys page - not directly readable.
320	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
321	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
322	* - Bit 7 - tlb entry - pMappingR3 member not valid.
323	* - Bits 63 thru 8 are used for the physical TLB revision number.
324	*
325	* We're using complemented bit meanings here because it makes it easy to check
326	* whether special action is required. For instance a user mode write access
327	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
328	* non-zero result would mean special handling needed because either it wasn't
329	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
330	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
331	* need to check any PTE flag.
332	*/
333	uint64_t fFlagsAndPhysRev;
334	/** The guest physical page address. */
335	uint64_t GCPhys;
336	/** Pointer to the ring-3 mapping. */
337	R3PTRTYPE(uint8_t *) pbMappingR3;
338	#if HC_ARCH_BITS == 32
339	uint32_t u32Padding1;
340	#endif
341	} IEMTLBENTRY;
342	AssertCompileSize(IEMTLBENTRY, 32);
343	/** Pointer to an IEM TLB entry. */
344	typedef IEMTLBENTRY *PIEMTLBENTRY;
345
346	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
347	* @{ */
348	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
349	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
350	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
351	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
352	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
353	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
354	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
355	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
356	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
357	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
358	/** @} */
359
360
361	/**
362	* An IEM TLB.
363	*
364	* We've got two of these, one for data and one for instructions.
365	*/
366	typedef struct IEMTLB
367	{
368	/** The TLB entries.
369	* We've choosen 256 because that way we can obtain the result directly from a
370	* 8-bit register without an additional AND instruction. */
371	IEMTLBENTRY aEntries[256];
372	/** The TLB revision.
373	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
374	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
375	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
376	* (The revision zero indicates an invalid TLB entry.)
377	*
378	* The initial value is choosen to cause an early wraparound. */
379	uint64_t uTlbRevision;
380	/** The TLB physical address revision - shadow of PGM variable.
381	*
382	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
383	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
384	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
385	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
386	*
387	* The initial value is choosen to cause an early wraparound. */
388	uint64_t volatile uTlbPhysRev;
389
390	/* Statistics: */
391
392	/** TLB hits (VBOX_WITH_STATISTICS only). */
393	uint64_t cTlbHits;
394	/** TLB misses. */
395	uint32_t cTlbMisses;
396	/** Slow read path. */
397	uint32_t cTlbSlowReadPath;
398	#if 0
399	/** TLB misses because of tag mismatch. */
400	uint32_t cTlbMissesTag;
401	/** TLB misses because of virtual access violation. */
402	uint32_t cTlbMissesVirtAccess;
403	/** TLB misses because of dirty bit. */
404	uint32_t cTlbMissesDirty;
405	/** TLB misses because of MMIO */
406	uint32_t cTlbMissesMmio;
407	/** TLB misses because of write access handlers. */
408	uint32_t cTlbMissesWriteHandler;
409	/** TLB misses because no r3(/r0) mapping. */
410	uint32_t cTlbMissesMapping;
411	#endif
412	/** Alignment padding. */
413	uint32_t au32Padding[3+5];
414	} IEMTLB;
415	AssertCompileSizeAlignment(IEMTLB, 64);
416	/** IEMTLB::uTlbRevision increment. */
417	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
418	/** IEMTLB::uTlbRevision mask. */
419	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
420	/** IEMTLB::uTlbPhysRev increment.
421	* @sa IEMTLBE_F_PHYS_REV */
422	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
423	/**
424	* Calculates the TLB tag for a virtual address.
425	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
426	* @param a_pTlb The TLB.
427	* @param a_GCPtr The virtual address.
428	*/
429	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
430	/**
431	* Calculates the TLB tag for a virtual address but without TLB revision.
432	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
433	* @param a_GCPtr The virtual address.
434	*/
435	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
436	/**
437	* Converts a TLB tag value into a TLB index.
438	* @returns Index into IEMTLB::aEntries.
439	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
440	*/
441	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
442	/**
443	* Converts a TLB tag value into a TLB index.
444	* @returns Index into IEMTLB::aEntries.
445	* @param a_pTlb The TLB.
446	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
447	*/
448	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
449
450
451	/**
452	* The per-CPU IEM state.
453	*/
454	typedef struct IEMCPU
455	{
456	/** Info status code that needs to be propagated to the IEM caller.
457	* This cannot be passed internally, as it would complicate all success
458	* checks within the interpreter making the code larger and almost impossible
459	* to get right. Instead, we'll store status codes to pass on here. Each
460	* source of these codes will perform appropriate sanity checks. */
461	int32_t rcPassUp; /* 0x00 */
462
463	/** The current CPU execution mode (CS). */
464	IEMMODE enmCpuMode; /* 0x04 */
465	/** The CPL. */
466	uint8_t uCpl; /* 0x05 */
467
468	/** Whether to bypass access handlers or not. */
469	bool fBypassHandlers; /* 0x06 */
470	/** Whether to disregard the lock prefix (implied or not). */
471	bool fDisregardLock; /* 0x07 */
472
473	/** @name Decoder state.
474	* @{ */
475	#ifdef IEM_WITH_CODE_TLB
476	/** The offset of the next instruction byte. */
477	uint32_t offInstrNextByte; /* 0x08 */
478	/** The number of bytes available at pbInstrBuf for the current instruction.
479	* This takes the max opcode length into account so that doesn't need to be
480	* checked separately. */
481	uint32_t cbInstrBuf; /* 0x0c */
482	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
483	* This can be NULL if the page isn't mappable for some reason, in which
484	* case we'll do fallback stuff.
485	*
486	* If we're executing an instruction from a user specified buffer,
487	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
488	* aligned pointer but pointer to the user data.
489	*
490	* For instructions crossing pages, this will start on the first page and be
491	* advanced to the next page by the time we've decoded the instruction. This
492	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
493	*/
494	uint8_t const pbInstrBuf; / 0x10 */
495	# if ARCH_BITS == 32
496	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
497	# endif
498	/** The program counter corresponding to pbInstrBuf.
499	* This is set to a non-canonical address when we need to invalidate it. */
500	uint64_t uInstrBufPc; /* 0x18 */
501	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
502	* This takes the CS segment limit into account. */
503	uint16_t cbInstrBufTotal; /* 0x20 */
504	/** Offset into pbInstrBuf of the first byte of the current instruction.
505	* Can be negative to efficiently handle cross page instructions. */
506	int16_t offCurInstrStart; /* 0x22 */
507
508	/** The prefix mask (IEM_OP_PRF_XXX). */
509	uint32_t fPrefixes; /* 0x24 */
510	/** The extra REX ModR/M register field bit (REX.R << 3). */
511	uint8_t uRexReg; /* 0x28 */
512	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
513	* (REX.B << 3). */
514	uint8_t uRexB; /* 0x29 */
515	/** The extra REX SIB index field bit (REX.X << 3). */
516	uint8_t uRexIndex; /* 0x2a */
517
518	/** The effective segment register (X86_SREG_XXX). */
519	uint8_t iEffSeg; /* 0x2b */
520
521	/** The offset of the ModR/M byte relative to the start of the instruction. */
522	uint8_t offModRm; /* 0x2c */
523	#else
524	/** The size of what has currently been fetched into abOpcode. */
525	uint8_t cbOpcode; /* 0x08 */
526	/** The current offset into abOpcode. */
527	uint8_t offOpcode; /* 0x09 */
528	/** The offset of the ModR/M byte relative to the start of the instruction. */
529	uint8_t offModRm; /* 0x0a */
530
531	/** The effective segment register (X86_SREG_XXX). */
532	uint8_t iEffSeg; /* 0x0b */
533
534	/** The prefix mask (IEM_OP_PRF_XXX). */
535	uint32_t fPrefixes; /* 0x0c */
536	/** The extra REX ModR/M register field bit (REX.R << 3). */
537	uint8_t uRexReg; /* 0x10 */
538	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
539	* (REX.B << 3). */
540	uint8_t uRexB; /* 0x11 */
541	/** The extra REX SIB index field bit (REX.X << 3). */
542	uint8_t uRexIndex; /* 0x12 */
543
544	#endif
545
546	/** The effective operand mode. */
547	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
548	/** The default addressing mode. */
549	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
550	/** The effective addressing mode. */
551	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
552	/** The default operand mode. */
553	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
554
555	/** Prefix index (VEX.pp) for two byte and three byte tables. */
556	uint8_t idxPrefix; /* 0x31, 0x17 */
557	/** 3rd VEX/EVEX/XOP register.
558	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
559	uint8_t uVex3rdReg; /* 0x32, 0x18 */
560	/** The VEX/EVEX/XOP length field. */
561	uint8_t uVexLength; /* 0x33, 0x19 */
562	/** Additional EVEX stuff. */
563	uint8_t fEvexStuff; /* 0x34, 0x1a */
564
565	/** Explicit alignment padding. */
566	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
567	/** The FPU opcode (FOP). */
568	uint16_t uFpuOpcode; /* 0x36, 0x1c */
569	#ifndef IEM_WITH_CODE_TLB
570	/** Explicit alignment padding. */
571	uint8_t abAlignment2b[2]; /* 0x1e */
572	#endif
573
574	/** The opcode bytes. */
575	uint8_t abOpcode[15]; /* 0x48, 0x20 */
576	/** Explicit alignment padding. */
577	#ifdef IEM_WITH_CODE_TLB
578	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
579	#else
580	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
581	#endif
582	/** @} */
583
584
585	/** The flags of the current exception / interrupt. */
586	uint32_t fCurXcpt; /* 0x48, 0x48 */
587	/** The current exception / interrupt. */
588	uint8_t uCurXcpt;
589	/** Exception / interrupt recursion depth. */
590	int8_t cXcptRecursions;
591
592	/** The number of active guest memory mappings. */
593	uint8_t cActiveMappings;
594	/** The next unused mapping index. */
595	uint8_t iNextMapping;
596	/** Records for tracking guest memory mappings. */
597	struct
598	{
599	/** The address of the mapped bytes. */
600	void *pv;
601	/** The access flags (IEM_ACCESS_XXX).
602	* IEM_ACCESS_INVALID if the entry is unused. */
603	uint32_t fAccess;
604	#if HC_ARCH_BITS == 64
605	uint32_t u32Alignment4; /*< Alignment padding. /
606	#endif
607	} aMemMappings[3];
608
609	/** Locking records for the mapped memory. */
610	union
611	{
612	PGMPAGEMAPLOCK Lock;
613	uint64_t au64Padding[2];
614	} aMemMappingLocks[3];
615
616	/** Bounce buffer info.
617	* This runs in parallel to aMemMappings. */
618	struct
619	{
620	/** The physical address of the first byte. */
621	RTGCPHYS GCPhysFirst;
622	/** The physical address of the second page. */
623	RTGCPHYS GCPhysSecond;
624	/** The number of bytes in the first page. */
625	uint16_t cbFirst;
626	/** The number of bytes in the second page. */
627	uint16_t cbSecond;
628	/** Whether it's unassigned memory. */
629	bool fUnassigned;
630	/** Explicit alignment padding. */
631	bool afAlignment5[3];
632	} aMemBbMappings[3];
633
634	/** Bounce buffer storage.
635	* This runs in parallel to aMemMappings and aMemBbMappings. */
636	struct
637	{
638	uint8_t ab[512];
639	} aBounceBuffers[3];
640
641
642	/** Pointer set jump buffer - ring-3 context. */
643	R3PTRTYPE(jmp_buf *) pJmpBufR3;
644	/** Pointer set jump buffer - ring-0 context. */
645	R0PTRTYPE(jmp_buf *) pJmpBufR0;
646
647	/** @todo Should move this near @a fCurXcpt later. */
648	/** The CR2 for the current exception / interrupt. */
649	uint64_t uCurXcptCr2;
650	/** The error code for the current exception / interrupt. */
651	uint32_t uCurXcptErr;
652
653	/** @name Statistics
654	* @{ */
655	/** The number of instructions we've executed. */
656	uint32_t cInstructions;
657	/** The number of potential exits. */
658	uint32_t cPotentialExits;
659	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
660	* This may contain uncommitted writes. */
661	uint32_t cbWritten;
662	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
663	uint32_t cRetInstrNotImplemented;
664	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
665	uint32_t cRetAspectNotImplemented;
666	/** Counts informational statuses returned (other than VINF_SUCCESS). */
667	uint32_t cRetInfStatuses;
668	/** Counts other error statuses returned. */
669	uint32_t cRetErrStatuses;
670	/** Number of times rcPassUp has been used. */
671	uint32_t cRetPassUpStatus;
672	/** Number of times RZ left with instruction commit pending for ring-3. */
673	uint32_t cPendingCommit;
674	/** Number of long jumps. */
675	uint32_t cLongJumps;
676	/** @} */
677
678	/** @name Target CPU information.
679	* @{ */
680	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
681	/** The target CPU. */
682	uint8_t uTargetCpu;
683	#else
684	uint8_t bTargetCpuPadding;
685	#endif
686	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
687	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
688	* native host support and the 2nd for when there is.
689	*
690	* The two values are typically indexed by a g_CpumHostFeatures bit.
691	*
692	* This is for instance used for the BSF & BSR instructions where AMD and
693	* Intel CPUs produce different EFLAGS. */
694	uint8_t aidxTargetCpuEflFlavour[2];
695
696	/** The CPU vendor. */
697	CPUMCPUVENDOR enmCpuVendor;
698	/** @} */
699
700	/** @name Host CPU information.
701	* @{ */
702	/** The CPU vendor. */
703	CPUMCPUVENDOR enmHostCpuVendor;
704	/** @} */
705
706	/** Counts RDMSR \#GP(0) LogRel(). */
707	uint8_t cLogRelRdMsr;
708	/** Counts WRMSR \#GP(0) LogRel(). */
709	uint8_t cLogRelWrMsr;
710	/** Alignment padding. */
711	uint8_t abAlignment8[50];
712
713	/** Data TLB.
714	* @remarks Must be 64-byte aligned. */
715	IEMTLB DataTlb;
716	/** Instruction TLB.
717	* @remarks Must be 64-byte aligned. */
718	IEMTLB CodeTlb;
719
720	/** Exception statistics. */
721	STAMCOUNTER aStatXcpts[32];
722	/** Interrupt statistics. */
723	uint32_t aStatInts[256];
724
725	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
726	/** Instruction statistics for ring-0/raw-mode. */
727	IEMINSTRSTATS StatsRZ;
728	/** Instruction statistics for ring-3. */
729	IEMINSTRSTATS StatsR3;
730	#endif
731	} IEMCPU;
732	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
733	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
734	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
735	/** Pointer to the per-CPU IEM state. */
736	typedef IEMCPU *PIEMCPU;
737	/** Pointer to the const per-CPU IEM state. */
738	typedef IEMCPU const *PCIEMCPU;
739
740
741	/** @def IEM_GET_CTX
742	* Gets the guest CPU context for the calling EMT.
743	* @returns PCPUMCTX
744	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
745	*/
746	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
747
748	/** @def IEM_CTX_ASSERT
749	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
750	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
751	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
752	*/
753	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
754	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
755	(a_fExtrnMbz)))
756
757	/** @def IEM_CTX_IMPORT_RET
758	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
759	*
760	* Will call the keep to import the bits as needed.
761	*
762	* Returns on import failure.
763	*
764	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
765	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
766	*/
767	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
768	do { \
769	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
770	{ /* likely */ } \
771	else \
772	{ \
773	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
774	AssertRCReturn(rcCtxImport, rcCtxImport); \
775	} \
776	} while (0)
777
778	/** @def IEM_CTX_IMPORT_NORET
779	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
780	*
781	* Will call the keep to import the bits as needed.
782	*
783	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
784	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
785	*/
786	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
787	do { \
788	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
789	{ /* likely */ } \
790	else \
791	{ \
792	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
793	AssertLogRelRC(rcCtxImport); \
794	} \
795	} while (0)
796
797	/** @def IEM_CTX_IMPORT_JMP
798	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
799	*
800	* Will call the keep to import the bits as needed.
801	*
802	* Jumps on import failure.
803	*
804	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
805	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
806	*/
807	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
808	do { \
809	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
810	{ /* likely */ } \
811	else \
812	{ \
813	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
814	AssertRCStmt(rcCtxImport, longjmp(*pVCpu->iem.s.CTX_SUFF(pJmpBuf), rcCtxImport)); \
815	} \
816	} while (0)
817
818
819
820	/** @def IEM_GET_TARGET_CPU
821	* Gets the current IEMTARGETCPU value.
822	* @returns IEMTARGETCPU value.
823	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
824	*/
825	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
826	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
827	#else
828	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
829	#endif
830
831	/** @def IEM_GET_INSTR_LEN
832	* Gets the instruction length. */
833	#ifdef IEM_WITH_CODE_TLB
834	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
835	#else
836	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
837	#endif
838
839
840	/**
841	* Shared per-VM IEM data.
842	*/
843	typedef struct IEM
844	{
845	/** The VMX APIC-access page handler type. */
846	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
847	} IEM;
848
849
850
851	/** @name IEM_ACCESS_XXX - Access details.
852	* @{ */
853	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
854	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
855	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
856	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
857	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
858	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
859	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
860	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
861	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
862	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
863	/** The writes are partial, so if initialize the bounce buffer with the
864	* orignal RAM content. */
865	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
866	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
867	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
868	/** Bounce buffer with ring-3 write pending, first page. */
869	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
870	/** Bounce buffer with ring-3 write pending, second page. */
871	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
872	/** Not locked, accessed via the TLB. */
873	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
874	/** Valid bit mask. */
875	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
876	/** Shift count for the TLB flags (upper word). */
877	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
878
879	/** Read+write data alias. */
880	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
881	/** Write data alias. */
882	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
883	/** Read data alias. */
884	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
885	/** Instruction fetch alias. */
886	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
887	/** Stack write alias. */
888	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
889	/** Stack read alias. */
890	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
891	/** Stack read+write alias. */
892	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
893	/** Read system table alias. */
894	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
895	/** Read+write system table alias. */
896	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
897	/** @} */
898
899	/** @name Prefix constants (IEMCPU::fPrefixes)
900	* @{ */
901	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
902	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
903	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
904	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
905	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
906	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
907	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
908
909	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
910	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
911	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
912
913	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
914	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
915	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
916
917	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
918	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
919	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
920	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
921	/** Mask with all the REX prefix flags.
922	* This is generally for use when needing to undo the REX prefixes when they
923	* are followed legacy prefixes and therefore does not immediately preceed
924	* the first opcode byte.
925	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
926	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
927
928	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
929	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
930	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
931	/** @} */
932
933	/** @name IEMOPFORM_XXX - Opcode forms
934	* @note These are ORed together with IEMOPHINT_XXX.
935	* @{ */
936	/** ModR/M: reg, r/m */
937	#define IEMOPFORM_RM 0
938	/** ModR/M: reg, r/m (register) */
939	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
940	/** ModR/M: reg, r/m (memory) */
941	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
942	/** ModR/M: reg, r/m */
943	#define IEMOPFORM_RMI 1
944	/** ModR/M: reg, r/m (register) */
945	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
946	/** ModR/M: reg, r/m (memory) */
947	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
948	/** ModR/M: r/m, reg */
949	#define IEMOPFORM_MR 2
950	/** ModR/M: r/m (register), reg */
951	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
952	/** ModR/M: r/m (memory), reg */
953	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
954	/** ModR/M: r/m only */
955	#define IEMOPFORM_M 3
956	/** ModR/M: r/m only (register). */
957	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
958	/** ModR/M: r/m only (memory). */
959	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
960	/** ModR/M: reg only */
961	#define IEMOPFORM_R 4
962
963	/** VEX+ModR/M: reg, r/m */
964	#define IEMOPFORM_VEX_RM 8
965	/** VEX+ModR/M: reg, r/m (register) */
966	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
967	/** VEX+ModR/M: reg, r/m (memory) */
968	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
969	/** VEX+ModR/M: r/m, reg */
970	#define IEMOPFORM_VEX_MR 9
971	/** VEX+ModR/M: r/m (register), reg */
972	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
973	/** VEX+ModR/M: r/m (memory), reg */
974	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
975	/** VEX+ModR/M: r/m only */
976	#define IEMOPFORM_VEX_M 10
977	/** VEX+ModR/M: r/m only (register). */
978	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
979	/** VEX+ModR/M: r/m only (memory). */
980	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
981	/** VEX+ModR/M: reg only */
982	#define IEMOPFORM_VEX_R 11
983	/** VEX+ModR/M: reg, vvvv, r/m */
984	#define IEMOPFORM_VEX_RVM 12
985	/** VEX+ModR/M: reg, vvvv, r/m (register). */
986	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
987	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
988	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
989	/** VEX+ModR/M: reg, r/m, vvvv */
990	#define IEMOPFORM_VEX_RMV 13
991	/** VEX+ModR/M: reg, r/m, vvvv (register). */
992	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
993	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
994	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
995	/** VEX+ModR/M: reg, r/m, imm8 */
996	#define IEMOPFORM_VEX_RMI 14
997	/** VEX+ModR/M: reg, r/m, imm8 (register). */
998	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
999	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1000	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1001	/** VEX+ModR/M: r/m, vvvv, reg */
1002	#define IEMOPFORM_VEX_MVR 15
1003	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1004	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1005	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1006	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1007	/** VEX+ModR/M+/n: vvvv, r/m */
1008	#define IEMOPFORM_VEX_VM 16
1009	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1010	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1011	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1012	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1013
1014	/** Fixed register instruction, no R/M. */
1015	#define IEMOPFORM_FIXED 32
1016
1017	/** The r/m is a register. */
1018	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1019	/** The r/m is a memory access. */
1020	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1021	/** @} */
1022
1023	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1024	* @note These are ORed together with IEMOPFORM_XXX.
1025	* @{ */
1026	/** Ignores the operand size prefix (66h). */
1027	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1028	/** Ignores REX.W (aka WIG). */
1029	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1030	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1031	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1032	/** Allowed with the lock prefix. */
1033	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1034	/** The VEX.L value is ignored (aka LIG). */
1035	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1036	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1037	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1038	/** The VEX.V value must be zero. */
1039	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1040
1041	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1042	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1043	/** @} */
1044
1045	/**
1046	* Possible hardware task switch sources.
1047	*/
1048	typedef enum IEMTASKSWITCH
1049	{
1050	/** Task switch caused by an interrupt/exception. */
1051	IEMTASKSWITCH_INT_XCPT = 1,
1052	/** Task switch caused by a far CALL. */
1053	IEMTASKSWITCH_CALL,
1054	/** Task switch caused by a far JMP. */
1055	IEMTASKSWITCH_JUMP,
1056	/** Task switch caused by an IRET. */
1057	IEMTASKSWITCH_IRET
1058	} IEMTASKSWITCH;
1059	AssertCompileSize(IEMTASKSWITCH, 4);
1060
1061	/**
1062	* Possible CrX load (write) sources.
1063	*/
1064	typedef enum IEMACCESSCRX
1065	{
1066	/** CrX access caused by 'mov crX' instruction. */
1067	IEMACCESSCRX_MOV_CRX,
1068	/** CrX (CR0) write caused by 'lmsw' instruction. */
1069	IEMACCESSCRX_LMSW,
1070	/** CrX (CR0) write caused by 'clts' instruction. */
1071	IEMACCESSCRX_CLTS,
1072	/** CrX (CR0) read caused by 'smsw' instruction. */
1073	IEMACCESSCRX_SMSW
1074	} IEMACCESSCRX;
1075
1076	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1077	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1078	*
1079	* These flags provide further context to SLAT page-walk failures that could not be
1080	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1081	*
1082	* @{
1083	*/
1084	/** Translating a nested-guest linear address failed accessing a nested-guest
1085	* physical address. */
1086	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1087	/** Translating a nested-guest linear address failed accessing a
1088	* paging-structure entry or updating accessed/dirty bits. */
1089	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1090	/** @} */
1091
1092	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1093	# ifndef IN_RING3
1094	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1095	# endif
1096	#endif
1097
1098	/**
1099	* Indicates to the verifier that the given flag set is undefined.
1100	*
1101	* Can be invoked again to add more flags.
1102	*
1103	* This is a NOOP if the verifier isn't compiled in.
1104	*
1105	* @note We're temporarily keeping this until code is converted to new
1106	* disassembler style opcode handling.
1107	*/
1108	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1109
1110
1111	/** @def IEM_DECL_IMPL_TYPE
1112	* For typedef'ing an instruction implementation function.
1113	*
1114	* @param a_RetType The return type.
1115	* @param a_Name The name of the type.
1116	* @param a_ArgList The argument list enclosed in parentheses.
1117	*/
1118
1119	/** @def IEM_DECL_IMPL_DEF
1120	* For defining an instruction implementation function.
1121	*
1122	* @param a_RetType The return type.
1123	* @param a_Name The name of the type.
1124	* @param a_ArgList The argument list enclosed in parentheses.
1125	*/
1126
1127	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1128	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1129	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1130	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1131	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1132	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1133	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1134
1135	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1136	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1137	a_RetType (__fastcall a_Name) a_ArgList
1138	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1139	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1140	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1141	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1142
1143	#elif __cplusplus >= 201700 /* P0012R1 support */
1144	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1145	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1146	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1147	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1148	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1149	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1150
1151	#else
1152	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1153	a_RetType (VBOXCALL a_Name) a_ArgList
1154	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1155	a_RetType VBOXCALL a_Name a_ArgList
1156	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1157	a_RetType VBOXCALL a_Name a_ArgList
1158
1159	#endif
1160
1161	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1162	RT_C_DECLS_BEGIN
1163	extern uint8_t const g_afParity[256];
1164	RT_C_DECLS_END
1165
1166
1167	/** @name Arithmetic assignment operations on bytes (binary).
1168	* @{ */
1169	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1170	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1171	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1172	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1173	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1174	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1175	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1176	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1177	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1178	/** @} */
1179
1180	/** @name Arithmetic assignment operations on words (binary).
1181	* @{ */
1182	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1183	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1184	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1185	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1186	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1187	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1188	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1189	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1190	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1191	/** @} */
1192
1193	/** @name Arithmetic assignment operations on double words (binary).
1194	* @{ */
1195	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1196	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1197	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1198	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1199	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1200	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1201	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1202	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1203	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1204	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1205	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1206	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1207	/** @} */
1208
1209	/** @name Arithmetic assignment operations on quad words (binary).
1210	* @{ */
1211	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1212	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1213	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1214	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1215	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1216	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1217	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1218	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1219	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1220	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1221	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1222	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1223	/** @} */
1224
1225	/** @name Compare operations (thrown in with the binary ops).
1226	* @{ */
1227	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1228	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1229	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1230	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1231	/** @} */
1232
1233	/** @name Test operations (thrown in with the binary ops).
1234	* @{ */
1235	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1236	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1237	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1238	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1239	/** @} */
1240
1241	/** @name Bit operations operations (thrown in with the binary ops).
1242	* @{ */
1243	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1244	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1245	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1246	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1247	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1248	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1249	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1250	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1251	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1252	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1253	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1254	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1255	/** @} */
1256
1257	/** @name Arithmetic three operand operations on double words (binary).
1258	* @{ */
1259	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
1260	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1261	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1262	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1263	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1264	/** @} */
1265
1266	/** @name Arithmetic three operand operations on quad words (binary).
1267	* @{ */
1268	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
1269	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1270	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1271	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1272	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1273	/** @} */
1274
1275	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1276	* @{ */
1277	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1278	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1279	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1280	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1281	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1282	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1283	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1284	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1285	/** @} */
1286
1287	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1288	* @{ */
1289	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1290	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1291	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1292	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1293	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1294	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1295	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1296	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1297	/** @} */
1298
1299	/** @name MULX 32-bit and 64-bit.
1300	* @{ */
1301	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
1302	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1303	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1304
1305	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
1306	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1307	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1308	/** @} */
1309
1310
1311	/** @name Exchange memory with register operations.
1312	* @{ */
1313	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1314	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1315	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1316	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1317	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1318	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1319	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1320	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1321	/** @} */
1322
1323	/** @name Exchange and add operations.
1324	* @{ */
1325	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1326	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1327	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1328	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1329	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1330	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1331	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1332	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1333	/** @} */
1334
1335	/** @name Compare and exchange.
1336	* @{ */
1337	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1338	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1339	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1340	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1341	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1342	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1343	#if ARCH_BITS == 32
1344	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1345	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1346	#else
1347	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1348	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1349	#endif
1350	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1351	uint32_t *pEFlags));
1352	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1353	uint32_t *pEFlags));
1354	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1355	uint32_t *pEFlags));
1356	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1357	uint32_t *pEFlags));
1358	#ifndef RT_ARCH_ARM64
1359	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1360	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1361	#endif
1362	/** @} */
1363
1364	/** @name Memory ordering
1365	* @{ */
1366	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1367	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1368	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1369	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1370	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1371	#ifndef RT_ARCH_ARM64
1372	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1373	#endif
1374	/** @} */
1375
1376	/** @name Double precision shifts
1377	* @{ */
1378	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1379	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1380	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1381	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1382	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1383	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1384	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1385	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1386	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1387	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1388	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1389	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1390	/** @} */
1391
1392
1393	/** @name Bit search operations (thrown in with the binary ops).
1394	* @{ */
1395	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1396	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1397	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1398	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1399	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1400	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1401	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1402	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1403	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1404	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
1405	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
1406	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
1407	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
1408	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
1409	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
1410	/** @} */
1411
1412	/** @name Signed multiplication operations (thrown in with the binary ops).
1413	* @{ */
1414	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1415	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1416	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1417	/** @} */
1418
1419	/** @name Arithmetic assignment operations on bytes (unary).
1420	* @{ */
1421	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1422	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1423	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1424	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1425	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1426	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1427	/** @} */
1428
1429	/** @name Arithmetic assignment operations on words (unary).
1430	* @{ */
1431	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1432	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1433	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1434	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1435	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1436	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1437	/** @} */
1438
1439	/** @name Arithmetic assignment operations on double words (unary).
1440	* @{ */
1441	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1442	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1443	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1444	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1445	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1446	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1447	/** @} */
1448
1449	/** @name Arithmetic assignment operations on quad words (unary).
1450	* @{ */
1451	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1452	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1453	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1454	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1455	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1456	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1457	/** @} */
1458
1459
1460	/** @name Shift operations on bytes (Group 2).
1461	* @{ */
1462	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1463	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1464	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1465	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1466	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1467	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1468	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1469	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1470	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1471	/** @} */
1472
1473	/** @name Shift operations on words (Group 2).
1474	* @{ */
1475	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1476	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1477	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1478	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1479	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1480	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1481	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1482	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1483	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1484	/** @} */
1485
1486	/** @name Shift operations on double words (Group 2).
1487	* @{ */
1488	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1489	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1490	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1491	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1492	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1493	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1494	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1495	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1496	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1497	/** @} */
1498
1499	/** @name Shift operations on words (Group 2).
1500	* @{ */
1501	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1502	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1503	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1504	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1505	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1506	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1507	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1508	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1509	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1510	/** @} */
1511
1512	/** @name Multiplication and division operations.
1513	* @{ */
1514	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1515	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1516	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1517	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1518	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1519	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1520
1521	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1522	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1523	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1524	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1525	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1526	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1527
1528	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1529	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1530	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1531	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1532	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1533	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1534
1535	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1536	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1537	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1538	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1539	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1540	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1541	/** @} */
1542
1543	/** @name Byte Swap.
1544	* @{ */
1545	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1546	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1547	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1548	/** @} */
1549
1550	/** @name Misc.
1551	* @{ */
1552	FNIEMAIMPLBINU16 iemAImpl_arpl;
1553	/** @} */
1554
1555
1556	/** @name FPU operations taking a 32-bit float argument
1557	* @{ */
1558	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1559	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1560	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1561
1562	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1563	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1564	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1565
1566	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1567	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1568	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1569	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1570	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1571	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1572	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1573
1574	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1575	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1576	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1577	/** @} */
1578
1579	/** @name FPU operations taking a 64-bit float argument
1580	* @{ */
1581	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1582	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1583	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
1584
1585	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1586	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1587	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1588
1589	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
1590	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1591	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1592	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1593	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1594	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1595	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1596
1597	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1598	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1599	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1600	/** @} */
1601
1602	/** @name FPU operations taking a 80-bit float argument
1603	* @{ */
1604	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1605	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1606	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1607	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1608	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1609	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1610	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1611	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1612	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1613	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1614	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1615	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1616
1617	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
1618	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
1619	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
1620
1621	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1622	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1623	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1624	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1625	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1626
1627	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1628	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1629	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1630	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1631	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1632
1633	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1634	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1635	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1636	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1637	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
1638	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1639	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1640	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
1641	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
1642
1643	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1644	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1645	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1646	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1647
1648	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1649	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1650	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1651	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1652	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1653	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1654	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1655	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1656	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1657
1658	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1659	PCRTFLOAT80U pr80Val));
1660	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1661	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
1662	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1663	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
1664
1665	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1666	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1667	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1668
1669	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
1670	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1671	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
1672
1673	/** @} */
1674
1675	/** @name FPU operations taking a 16-bit signed integer argument
1676	* @{ */
1677	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1678	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1679	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1680	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1681	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
1682	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
1683
1684	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1685	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1686	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1687	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1688	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1689	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1690
1691	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1692	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1693	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
1694	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
1695
1696	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1697	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
1698	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
1699	/** @} */
1700
1701	/** @name FPU operations taking a 32-bit signed integer argument
1702	* @{ */
1703	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1704	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1705	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1706	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1707	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
1708	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
1709
1710	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1711	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1712	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1713	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1714	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1715	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1716
1717	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1718	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1719	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
1720	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
1721
1722	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1723	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
1724	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
1725	/** @} */
1726
1727	/** @name FPU operations taking a 64-bit signed integer argument
1728	* @{ */
1729	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1730	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
1731	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
1732
1733	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1734	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
1735	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
1736	/** @} */
1737
1738
1739	/** Temporary type representing a 256-bit vector register. */
1740	typedef struct { uint64_t au64[4]; } IEMVMM256;
1741	/** Temporary type pointing to a 256-bit vector register. */
1742	typedef IEMVMM256 *PIEMVMM256;
1743	/** Temporary type pointing to a const 256-bit vector register. */
1744	typedef IEMVMM256 *PCIEMVMM256;
1745
1746
1747	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1748	* @{ */
1749	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
1750	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1751	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1752	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1753	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1754	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
1755	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1756	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
1757	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
1758	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
1759	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
1760	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
1761	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1762	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
1763	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1764	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
1765	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
1766	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
1767	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
1768	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
1769	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1770	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
1771	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
1772	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
1773	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
1774	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
1775	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
1776	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
1777	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
1778	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
1779	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
1780	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
1781	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
1782	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
1783	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
1784	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
1785	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
1786	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
1787	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
1788	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
1789	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
1790	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
1791	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
1792	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
1793	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
1794	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
1795	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
1796	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
1797	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
1798	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
1799	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
1800	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
1801	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
1802	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
1803	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
1804	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
1805	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
1806
1807	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
1808	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
1809	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1810	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
1811	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
1812	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
1813	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
1814	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
1815	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
1816	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
1817	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
1818	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
1819	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
1820	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
1821	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
1822	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
1823	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
1824	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
1825	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
1826	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
1827	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
1828	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
1829	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
1830	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
1831	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
1832	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
1833	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
1834	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
1835	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
1836	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
1837	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
1838	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
1839	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
1840	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
1841	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
1842	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
1843	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
1844	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
1845	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
1846	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
1847	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
1848	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
1849	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
1850	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
1851	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
1852	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
1853	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
1854	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
1855	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
1856	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
1857	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
1858	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
1859	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
1860	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
1861	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
1862	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
1863
1864	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
1865	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
1866	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
1867	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
1868	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
1869	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
1870	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
1871	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
1872	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
1873	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
1874	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
1875	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
1876	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
1877	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
1878	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
1879	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
1880	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
1881	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
1882	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
1883	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
1884	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
1885	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
1886	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
1887	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
1888	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
1889	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
1890	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
1891	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
1892	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
1893	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
1894	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
1895	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
1896	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
1897	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
1898	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
1899	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
1900	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
1901	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
1902	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
1903	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
1904	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
1905	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
1906	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
1907	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
1908	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
1909	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
1910	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
1911	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
1912	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
1913	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
1914	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
1915	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
1916	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
1917	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
1918	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
1919	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
1920	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
1921
1922	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
1923	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
1924	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
1925
1926	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
1927	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
1928	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
1929	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
1930	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
1931	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
1932	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
1933	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
1934	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
1935	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
1936	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
1937	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
1938	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
1939	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
1940	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
1941	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
1942	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
1943	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
1944	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
1945	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
1946	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
1947	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
1948	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
1949	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
1950	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
1951	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
1952	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
1953	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
1954	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
1955	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
1956	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
1957	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
1958	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
1959	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
1960	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
1961	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
1962	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
1963	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
1964	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
1965	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
1966	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
1967	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
1968	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
1969	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
1970	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
1971	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
1972	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
1973	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
1974	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
1975	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
1976	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
1977	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
1978	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
1979	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
1980	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
1981	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
1982	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
1983
1984	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
1985	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
1986	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
1987	/** @} */
1988
1989	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
1990	* @{ */
1991	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
1992	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
1993	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
1994	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
1995	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
1996	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
1997	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
1998	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
1999	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2000	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2001
2002	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2003	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2004	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2005	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2006	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2007	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2008	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2009	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2010	/** @} */
2011
2012	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2013	* @{ */
2014	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2015	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2016	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2017	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2018	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2019	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2020	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2021	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2022	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2023	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2024	/** @} */
2025
2026	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2027	* @{ */
2028	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2029	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2030	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2031	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2032	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
2033	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2034	#ifndef IEM_WITHOUT_ASSEMBLY
2035	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2036	#endif
2037	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2038	/** @} */
2039
2040	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2041	* @{ */
2042	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2043	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2044	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2045	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2046	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2047	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2048	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2049	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2050	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2051	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2052	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2053	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2054	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2055	/** @} */
2056
2057	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2058	* @{ */
2059	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
2060	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2061	#ifndef IEM_WITHOUT_ASSEMBLY
2062	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2063	#endif
2064	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2065	/** @} */
2066
2067	/** @name Media (SSE/MMX/AVX) operation: Sort this later
2068	* @{ */
2069	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2070	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2071	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PRTUINT128U puDst, uint64_t uSrc));
2072
2073	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2074	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2075	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2076	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2077	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2078	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2079
2080	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2081	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2082	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2083	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2084	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2085
2086	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2087	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2088	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2089	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2090	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2091
2092	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2093	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2094	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2095	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2096	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2097
2098	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2099	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2100	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2101	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2102	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2103
2104	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2105	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2106	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2107	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2108	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2109
2110	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2111	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2112	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2113	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2114	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2115
2116	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2117	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2118	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2119	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2120	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2121
2122	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2123	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2124	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2125	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2126	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2127
2128	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2129	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2130	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2131	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2132	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2133
2134	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2135	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2136	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2137	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2138	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2139
2140	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2141	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2142	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2143	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2144	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2145
2146	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2147	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2148	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2149	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2150	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2151
2152	/** @} */
2153
2154	/** @name Media Odds and Ends
2155	* @{ */
2156	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
2157	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
2158	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
2159	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
2160	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
2161	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
2162	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
2163	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
2164
2165	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
2166	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
2167	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
2168	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
2169	/** @} */
2170
2171
2172	/** @name Function tables.
2173	* @{
2174	*/
2175
2176	/**
2177	* Function table for a binary operator providing implementation based on
2178	* operand size.
2179	*/
2180	typedef struct IEMOPBINSIZES
2181	{
2182	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
2183	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
2184	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
2185	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
2186	} IEMOPBINSIZES;
2187	/** Pointer to a binary operator function table. */
2188	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
2189
2190
2191	/**
2192	* Function table for a unary operator providing implementation based on
2193	* operand size.
2194	*/
2195	typedef struct IEMOPUNARYSIZES
2196	{
2197	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
2198	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
2199	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
2200	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
2201	} IEMOPUNARYSIZES;
2202	/** Pointer to a unary operator function table. */
2203	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
2204
2205
2206	/**
2207	* Function table for a shift operator providing implementation based on
2208	* operand size.
2209	*/
2210	typedef struct IEMOPSHIFTSIZES
2211	{
2212	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
2213	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
2214	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
2215	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
2216	} IEMOPSHIFTSIZES;
2217	/** Pointer to a shift operator function table. */
2218	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
2219
2220
2221	/**
2222	* Function table for a multiplication or division operation.
2223	*/
2224	typedef struct IEMOPMULDIVSIZES
2225	{
2226	PFNIEMAIMPLMULDIVU8 pfnU8;
2227	PFNIEMAIMPLMULDIVU16 pfnU16;
2228	PFNIEMAIMPLMULDIVU32 pfnU32;
2229	PFNIEMAIMPLMULDIVU64 pfnU64;
2230	} IEMOPMULDIVSIZES;
2231	/** Pointer to a multiplication or division operation function table. */
2232	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
2233
2234
2235	/**
2236	* Function table for a double precision shift operator providing implementation
2237	* based on operand size.
2238	*/
2239	typedef struct IEMOPSHIFTDBLSIZES
2240	{
2241	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
2242	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
2243	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
2244	} IEMOPSHIFTDBLSIZES;
2245	/** Pointer to a double precision shift function table. */
2246	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
2247
2248
2249	/**
2250	* Function table for media instruction taking two full sized media source
2251	* registers and one full sized destination register (AVX).
2252	*/
2253	typedef struct IEMOPMEDIAF3
2254	{
2255	PFNIEMAIMPLMEDIAF3U128 pfnU128;
2256	PFNIEMAIMPLMEDIAF3U256 pfnU256;
2257	} IEMOPMEDIAF3;
2258	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2259	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
2260
2261	/** @def IEMOPMEDIAF3_INIT_VARS_EX
2262	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2263	* given functions as initializers. For use in AVX functions where a pair of
2264	* functions are only used once and the function table need not be public. */
2265	#ifndef TST_IEM_CHECK_MC
2266	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2267	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2268	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2269	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2270	# else
2271	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2272	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2273	# endif
2274	#else
2275	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2276	#endif
2277	/** @def IEMOPMEDIAF3_INIT_VARS
2278	* Generate AVX function tables for the @a a_InstrNm instruction.
2279	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
2280	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
2281	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2282	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2283
2284	/**
2285	* Function table for media instruction taking two full sized media source
2286	* registers and one full sized destination register, but no additional state
2287	* (AVX).
2288	*/
2289	typedef struct IEMOPMEDIAOPTF3
2290	{
2291	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
2292	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
2293	} IEMOPMEDIAOPTF3;
2294	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2295	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
2296
2297	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
2298	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2299	* given functions as initializers. For use in AVX functions where a pair of
2300	* functions are only used once and the function table need not be public. */
2301	#ifndef TST_IEM_CHECK_MC
2302	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2303	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2304	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2305	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2306	# else
2307	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2308	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2309	# endif
2310	#else
2311	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2312	#endif
2313	/** @def IEMOPMEDIAOPTF3_INIT_VARS
2314	* Generate AVX function tables for the @a a_InstrNm instruction.
2315	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
2316	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
2317	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2318	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2319
2320	/**
2321	* Function table for media instruction taking one full sized media source
2322	* registers and one full sized destination register, but no additional state
2323	* (AVX).
2324	*/
2325	typedef struct IEMOPMEDIAOPTF2
2326	{
2327	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
2328	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
2329	} IEMOPMEDIAOPTF2;
2330	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
2331	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
2332
2333	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
2334	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2335	* given functions as initializers. For use in AVX functions where a pair of
2336	* functions are only used once and the function table need not be public. */
2337	#ifndef TST_IEM_CHECK_MC
2338	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2339	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2340	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2341	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2342	# else
2343	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2344	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2345	# endif
2346	#else
2347	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2348	#endif
2349	/** @def IEMOPMEDIAOPTF2_INIT_VARS
2350	* Generate AVX function tables for the @a a_InstrNm instruction.
2351	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
2352	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
2353	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2354	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2355	/** @} */
2356
2357
2358	/** @name SSE/AVX single/double precision floating point operations.
2359	* @{ */
2360	/**
2361	* A SSE result.
2362	*/
2363	typedef struct IEMSSERESULT
2364	{
2365	/** The output value. */
2366	X86XMMREG uResult;
2367	/** The output status. */
2368	uint32_t MXCSR;
2369	} IEMSSERESULT;
2370	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
2371	/** Pointer to a SSE result. */
2372	typedef IEMSSERESULT *PIEMSSERESULT;
2373	/** Pointer to a const SSE result. */
2374	typedef IEMSSERESULT const *PCIEMSSERESULT;
2375
2376
2377	/**
2378	* A AVX128 result.
2379	*/
2380	typedef struct IEMAVX128RESULT
2381	{
2382	/** The output value. */
2383	X86XMMREG uResult;
2384	/** The output status. */
2385	uint32_t MXCSR;
2386	} IEMAVX128RESULT;
2387	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
2388	/** Pointer to a AVX128 result. */
2389	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
2390	/** Pointer to a const AVX128 result. */
2391	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
2392
2393
2394	/**
2395	* A AVX256 result.
2396	*/
2397	typedef struct IEMAVX256RESULT
2398	{
2399	/** The output value. */
2400	X86YMMREG uResult;
2401	/** The output status. */
2402	uint32_t MXCSR;
2403	} IEMAVX256RESULT;
2404	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
2405	/** Pointer to a AVX256 result. */
2406	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
2407	/** Pointer to a const AVX256 result. */
2408	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
2409
2410
2411	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2412	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
2413	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2414	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
2415	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2416	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
2417
2418	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2419	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
2420	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2421	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
2422	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2423	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
2424
2425	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
2426	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
2427
2428	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
2429	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
2430	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
2431	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
2432	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
2433	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
2434	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
2435	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
2436	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
2437	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
2438	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
2439	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
2440
2441	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
2442	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
2443	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
2444	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
2445	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
2446	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
2447	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
2448	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
2449	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
2450	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
2451	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
2452	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
2453	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
2454	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
2455
2456	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
2457	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
2458	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
2459	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
2460	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
2461	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
2462	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
2463	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
2464	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
2465	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
2466	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
2467	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
2468
2469	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
2470	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
2471	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
2472	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
2473	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
2474	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
2475	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
2476	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
2477	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
2478	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
2479	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
2480	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
2481
2482	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
2483	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
2484	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
2485	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
2486	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
2487	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
2488	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
2489	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
2490	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
2491	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
2492	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
2493	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
2494	/** @} */
2495
2496	/** @name C instruction implementations for anything slightly complicated.
2497	* @{ */
2498
2499	/**
2500	* For typedef'ing or declaring a C instruction implementation function taking
2501	* no extra arguments.
2502	*
2503	* @param a_Name The name of the type.
2504	*/
2505	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
2506	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2507	/**
2508	* For defining a C instruction implementation function taking no extra
2509	* arguments.
2510	*
2511	* @param a_Name The name of the function
2512	*/
2513	# define IEM_CIMPL_DEF_0(a_Name) \
2514	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2515	/**
2516	* Prototype version of IEM_CIMPL_DEF_0.
2517	*/
2518	# define IEM_CIMPL_PROTO_0(a_Name) \
2519	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2520	/**
2521	* For calling a C instruction implementation function taking no extra
2522	* arguments.
2523	*
2524	* This special call macro adds default arguments to the call and allow us to
2525	* change these later.
2526	*
2527	* @param a_fn The name of the function.
2528	*/
2529	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
2530
2531	/**
2532	* For typedef'ing or declaring a C instruction implementation function taking
2533	* one extra argument.
2534	*
2535	* @param a_Name The name of the type.
2536	* @param a_Type0 The argument type.
2537	* @param a_Arg0 The argument name.
2538	*/
2539	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
2540	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2541	/**
2542	* For defining a C instruction implementation function taking one extra
2543	* argument.
2544	*
2545	* @param a_Name The name of the function
2546	* @param a_Type0 The argument type.
2547	* @param a_Arg0 The argument name.
2548	*/
2549	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
2550	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2551	/**
2552	* Prototype version of IEM_CIMPL_DEF_1.
2553	*/
2554	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
2555	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2556	/**
2557	* For calling a C instruction implementation function taking one extra
2558	* argument.
2559	*
2560	* This special call macro adds default arguments to the call and allow us to
2561	* change these later.
2562	*
2563	* @param a_fn The name of the function.
2564	* @param a0 The name of the 1st argument.
2565	*/
2566	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
2567
2568	/**
2569	* For typedef'ing or declaring a C instruction implementation function taking
2570	* two extra arguments.
2571	*
2572	* @param a_Name The name of the type.
2573	* @param a_Type0 The type of the 1st argument
2574	* @param a_Arg0 The name of the 1st argument.
2575	* @param a_Type1 The type of the 2nd argument.
2576	* @param a_Arg1 The name of the 2nd argument.
2577	*/
2578	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2579	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2580	/**
2581	* For defining a C instruction implementation function taking two extra
2582	* arguments.
2583	*
2584	* @param a_Name The name of the function.
2585	* @param a_Type0 The type of the 1st argument
2586	* @param a_Arg0 The name of the 1st argument.
2587	* @param a_Type1 The type of the 2nd argument.
2588	* @param a_Arg1 The name of the 2nd argument.
2589	*/
2590	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2591	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2592	/**
2593	* Prototype version of IEM_CIMPL_DEF_2.
2594	*/
2595	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2596	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2597	/**
2598	* For calling a C instruction implementation function taking two extra
2599	* arguments.
2600	*
2601	* This special call macro adds default arguments to the call and allow us to
2602	* change these later.
2603	*
2604	* @param a_fn The name of the function.
2605	* @param a0 The name of the 1st argument.
2606	* @param a1 The name of the 2nd argument.
2607	*/
2608	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
2609
2610	/**
2611	* For typedef'ing or declaring a C instruction implementation function taking
2612	* three extra arguments.
2613	*
2614	* @param a_Name The name of the type.
2615	* @param a_Type0 The type of the 1st argument
2616	* @param a_Arg0 The name of the 1st argument.
2617	* @param a_Type1 The type of the 2nd argument.
2618	* @param a_Arg1 The name of the 2nd argument.
2619	* @param a_Type2 The type of the 3rd argument.
2620	* @param a_Arg2 The name of the 3rd argument.
2621	*/
2622	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2623	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2624	/**
2625	* For defining a C instruction implementation function taking three extra
2626	* arguments.
2627	*
2628	* @param a_Name The name of the function.
2629	* @param a_Type0 The type of the 1st argument
2630	* @param a_Arg0 The name of the 1st argument.
2631	* @param a_Type1 The type of the 2nd argument.
2632	* @param a_Arg1 The name of the 2nd argument.
2633	* @param a_Type2 The type of the 3rd argument.
2634	* @param a_Arg2 The name of the 3rd argument.
2635	*/
2636	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2637	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2638	/**
2639	* Prototype version of IEM_CIMPL_DEF_3.
2640	*/
2641	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2642	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2643	/**
2644	* For calling a C instruction implementation function taking three extra
2645	* arguments.
2646	*
2647	* This special call macro adds default arguments to the call and allow us to
2648	* change these later.
2649	*
2650	* @param a_fn The name of the function.
2651	* @param a0 The name of the 1st argument.
2652	* @param a1 The name of the 2nd argument.
2653	* @param a2 The name of the 3rd argument.
2654	*/
2655	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
2656
2657
2658	/**
2659	* For typedef'ing or declaring a C instruction implementation function taking
2660	* four extra arguments.
2661	*
2662	* @param a_Name The name of the type.
2663	* @param a_Type0 The type of the 1st argument
2664	* @param a_Arg0 The name of the 1st argument.
2665	* @param a_Type1 The type of the 2nd argument.
2666	* @param a_Arg1 The name of the 2nd argument.
2667	* @param a_Type2 The type of the 3rd argument.
2668	* @param a_Arg2 The name of the 3rd argument.
2669	* @param a_Type3 The type of the 4th argument.
2670	* @param a_Arg3 The name of the 4th argument.
2671	*/
2672	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
2673	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
2674	/**
2675	* For defining a C instruction implementation function taking four extra
2676	* arguments.
2677	*
2678	* @param a_Name The name of the function.
2679	* @param a_Type0 The type of the 1st argument
2680	* @param a_Arg0 The name of the 1st argument.
2681	* @param a_Type1 The type of the 2nd argument.
2682	* @param a_Arg1 The name of the 2nd argument.
2683	* @param a_Type2 The type of the 3rd argument.
2684	* @param a_Arg2 The name of the 3rd argument.
2685	* @param a_Type3 The type of the 4th argument.
2686	* @param a_Arg3 The name of the 4th argument.
2687	*/
2688	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
2689	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2690	a_Type2 a_Arg2, a_Type3 a_Arg3))
2691	/**
2692	* Prototype version of IEM_CIMPL_DEF_4.
2693	*/
2694	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
2695	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2696	a_Type2 a_Arg2, a_Type3 a_Arg3))
2697	/**
2698	* For calling a C instruction implementation function taking four extra
2699	* arguments.
2700	*
2701	* This special call macro adds default arguments to the call and allow us to
2702	* change these later.
2703	*
2704	* @param a_fn The name of the function.
2705	* @param a0 The name of the 1st argument.
2706	* @param a1 The name of the 2nd argument.
2707	* @param a2 The name of the 3rd argument.
2708	* @param a3 The name of the 4th argument.
2709	*/
2710	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
2711
2712
2713	/**
2714	* For typedef'ing or declaring a C instruction implementation function taking
2715	* five extra arguments.
2716	*
2717	* @param a_Name The name of the type.
2718	* @param a_Type0 The type of the 1st argument
2719	* @param a_Arg0 The name of the 1st argument.
2720	* @param a_Type1 The type of the 2nd argument.
2721	* @param a_Arg1 The name of the 2nd argument.
2722	* @param a_Type2 The type of the 3rd argument.
2723	* @param a_Arg2 The name of the 3rd argument.
2724	* @param a_Type3 The type of the 4th argument.
2725	* @param a_Arg3 The name of the 4th argument.
2726	* @param a_Type4 The type of the 5th argument.
2727	* @param a_Arg4 The name of the 5th argument.
2728	*/
2729	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2730	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
2731	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
2732	a_Type3 a_Arg3, a_Type4 a_Arg4))
2733	/**
2734	* For defining a C instruction implementation function taking five extra
2735	* arguments.
2736	*
2737	* @param a_Name The name of the function.
2738	* @param a_Type0 The type of the 1st argument
2739	* @param a_Arg0 The name of the 1st argument.
2740	* @param a_Type1 The type of the 2nd argument.
2741	* @param a_Arg1 The name of the 2nd argument.
2742	* @param a_Type2 The type of the 3rd argument.
2743	* @param a_Arg2 The name of the 3rd argument.
2744	* @param a_Type3 The type of the 4th argument.
2745	* @param a_Arg3 The name of the 4th argument.
2746	* @param a_Type4 The type of the 5th argument.
2747	* @param a_Arg4 The name of the 5th argument.
2748	*/
2749	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2750	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2751	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
2752	/**
2753	* Prototype version of IEM_CIMPL_DEF_5.
2754	*/
2755	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2756	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2757	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
2758	/**
2759	* For calling a C instruction implementation function taking five extra
2760	* arguments.
2761	*
2762	* This special call macro adds default arguments to the call and allow us to
2763	* change these later.
2764	*
2765	* @param a_fn The name of the function.
2766	* @param a0 The name of the 1st argument.
2767	* @param a1 The name of the 2nd argument.
2768	* @param a2 The name of the 3rd argument.
2769	* @param a3 The name of the 4th argument.
2770	* @param a4 The name of the 5th argument.
2771	*/
2772	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
2773
2774	/** @} */
2775
2776
2777	/** @name Opcode Decoder Function Types.
2778	* @{ */
2779
2780	/** @typedef PFNIEMOP
2781	* Pointer to an opcode decoder function.
2782	*/
2783
2784	/** @def FNIEMOP_DEF
2785	* Define an opcode decoder function.
2786	*
2787	* We're using macors for this so that adding and removing parameters as well as
2788	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
2789	*
2790	* @param a_Name The function name.
2791	*/
2792
2793	/** @typedef PFNIEMOPRM
2794	* Pointer to an opcode decoder function with RM byte.
2795	*/
2796
2797	/** @def FNIEMOPRM_DEF
2798	* Define an opcode decoder function with RM byte.
2799	*
2800	* We're using macors for this so that adding and removing parameters as well as
2801	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
2802	*
2803	* @param a_Name The function name.
2804	*/
2805
2806	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2807	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
2808	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2809	# define FNIEMOP_DEF(a_Name) \
2810	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
2811	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2812	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
2813	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2814	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
2815
2816	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2817	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
2818	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2819	# define FNIEMOP_DEF(a_Name) \
2820	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
2821	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2822	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
2823	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2824	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
2825
2826	#elif defined(__GNUC__)
2827	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
2828	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2829	# define FNIEMOP_DEF(a_Name) \
2830	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
2831	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2832	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
2833	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2834	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
2835
2836	#else
2837	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
2838	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2839	# define FNIEMOP_DEF(a_Name) \
2840	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
2841	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2842	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
2843	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2844	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
2845
2846	#endif
2847	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
2848
2849	/**
2850	* Call an opcode decoder function.
2851	*
2852	* We're using macors for this so that adding and removing parameters can be
2853	* done as we please. See FNIEMOP_DEF.
2854	*/
2855	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
2856
2857	/**
2858	* Call a common opcode decoder function taking one extra argument.
2859	*
2860	* We're using macors for this so that adding and removing parameters can be
2861	* done as we please. See FNIEMOP_DEF_1.
2862	*/
2863	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
2864
2865	/**
2866	* Call a common opcode decoder function taking one extra argument.
2867	*
2868	* We're using macors for this so that adding and removing parameters can be
2869	* done as we please. See FNIEMOP_DEF_1.
2870	*/
2871	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
2872	/** @} */
2873
2874
2875	/** @name Misc Helpers
2876	* @{ */
2877
2878	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
2879	* due to GCC lacking knowledge about the value range of a switch. */
2880	#define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
2881
2882	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
2883	#define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
2884
2885	/**
2886	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
2887	* occation.
2888	*/
2889	#ifdef LOG_ENABLED
2890	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
2891	do { \
2892	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
2893	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
2894	} while (0)
2895	#else
2896	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
2897	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
2898	#endif
2899
2900	/**
2901	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
2902	* occation using the supplied logger statement.
2903	*
2904	* @param a_LoggerArgs What to log on failure.
2905	*/
2906	#ifdef LOG_ENABLED
2907	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
2908	do { \
2909	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
2910	/LogFunc(a_LoggerArgs);/ \
2911	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
2912	} while (0)
2913	#else
2914	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
2915	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
2916	#endif
2917
2918	/**
2919	* Check if we're currently executing in real or virtual 8086 mode.
2920	*
2921	* @returns @c true if it is, @c false if not.
2922	* @param a_pVCpu The IEM state of the current CPU.
2923	*/
2924	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (CPUMIsGuestInRealOrV86ModeEx(IEM_GET_CTX(a_pVCpu)))
2925
2926	/**
2927	* Check if we're currently executing in virtual 8086 mode.
2928	*
2929	* @returns @c true if it is, @c false if not.
2930	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2931	*/
2932	#define IEM_IS_V86_MODE(a_pVCpu) (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(a_pVCpu)))
2933
2934	/**
2935	* Check if we're currently executing in long mode.
2936	*
2937	* @returns @c true if it is, @c false if not.
2938	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2939	*/
2940	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
2941
2942	/**
2943	* Check if we're currently executing in a 64-bit code segment.
2944	*
2945	* @returns @c true if it is, @c false if not.
2946	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2947	*/
2948	#define IEM_IS_64BIT_CODE(a_pVCpu) (CPUMIsGuestIn64BitCodeEx(IEM_GET_CTX(a_pVCpu)))
2949
2950	/**
2951	* Check if we're currently executing in real mode.
2952	*
2953	* @returns @c true if it is, @c false if not.
2954	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2955	*/
2956	#define IEM_IS_REAL_MODE(a_pVCpu) (CPUMIsGuestInRealModeEx(IEM_GET_CTX(a_pVCpu)))
2957
2958	/**
2959	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
2960	* @returns PCCPUMFEATURES
2961	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2962	*/
2963	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
2964
2965	/**
2966	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
2967	* @returns PCCPUMFEATURES
2968	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2969	*/
2970	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
2971
2972	/**
2973	* Evaluates to true if we're presenting an Intel CPU to the guest.
2974	*/
2975	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
2976
2977	/**
2978	* Evaluates to true if we're presenting an AMD CPU to the guest.
2979	*/
2980	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
2981
2982	/**
2983	* Check if the address is canonical.
2984	*/
2985	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
2986
2987	/** Checks if the ModR/M byte is in register mode or not. */
2988	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
2989	/** Checks if the ModR/M byte is in memory mode or not. */
2990	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
2991
2992	/**
2993	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
2994	*
2995	* For use during decoding.
2996	*/
2997	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
2998	/**
2999	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
3000	*
3001	* For use during decoding.
3002	*/
3003	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
3004
3005	/**
3006	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
3007	*
3008	* For use during decoding.
3009	*/
3010	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
3011	/**
3012	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
3013	*
3014	* For use during decoding.
3015	*/
3016	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
3017
3018	/**
3019	* Gets the effective VEX.VVVV value.
3020	*
3021	* The 4th bit is ignored if not 64-bit code.
3022	* @returns effective V-register value.
3023	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3024	*/
3025	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
3026	((a_pVCpu)->iem.s.enmCpuMode == IEMMODE_64BIT ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
3027
3028
3029	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3030
3031	/**
3032	* Check if the guest has entered VMX root operation.
3033	*/
3034	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
3035
3036	/**
3037	* Check if the guest has entered VMX non-root operation.
3038	*/
3039	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(a_pVCpu)))
3040
3041	/**
3042	* Check if the nested-guest has the given Pin-based VM-execution control set.
3043	*/
3044	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) \
3045	(CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
3046
3047	/**
3048	* Check if the nested-guest has the given Processor-based VM-execution control set.
3049	*/
3050	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) \
3051	(CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
3052
3053	/**
3054	* Check if the nested-guest has the given Secondary Processor-based VM-execution
3055	* control set.
3056	*/
3057	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) \
3058	(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
3059
3060	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
3061	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
3062
3063	/** Whether a shadow VMCS is present for the given VCPU. */
3064	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3065
3066	/** Gets the VMXON region pointer. */
3067	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
3068
3069	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
3070	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
3071
3072	/** Whether a current VMCS is present for the given VCPU. */
3073	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3074
3075	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
3076	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
3077	do \
3078	{ \
3079	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
3080	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
3081	} while (0)
3082
3083	/** Clears any current VMCS for the given VCPU. */
3084	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
3085	do \
3086	{ \
3087	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
3088	} while (0)
3089
3090	/**
3091	* Invokes the VMX VM-exit handler for an instruction intercept.
3092	*/
3093	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
3094	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
3095
3096	/**
3097	* Invokes the VMX VM-exit handler for an instruction intercept where the
3098	* instruction provides additional VM-exit information.
3099	*/
3100	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
3101	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
3102
3103	/**
3104	* Invokes the VMX VM-exit handler for a task switch.
3105	*/
3106	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
3107	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
3108
3109	/**
3110	* Invokes the VMX VM-exit handler for MWAIT.
3111	*/
3112	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
3113	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
3114
3115	/**
3116	* Invokes the VMX VM-exit handler for EPT faults.
3117	*/
3118	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
3119	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
3120
3121	/**
3122	* Invokes the VMX VM-exit handler.
3123	*/
3124	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
3125	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
3126
3127	#else
3128	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
3129	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
3130	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
3131	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
3132	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
3133	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3134	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3135	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3136	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3137	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3138	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
3139
3140	#endif
3141
3142	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3143	/**
3144	* Check if an SVM control/instruction intercept is set.
3145	*/
3146	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
3147	(CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
3148
3149	/**
3150	* Check if an SVM read CRx intercept is set.
3151	*/
3152	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3153	(CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3154
3155	/**
3156	* Check if an SVM write CRx intercept is set.
3157	*/
3158	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3159	(CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3160
3161	/**
3162	* Check if an SVM read DRx intercept is set.
3163	*/
3164	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3165	(CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3166
3167	/**
3168	* Check if an SVM write DRx intercept is set.
3169	*/
3170	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3171	(CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3172
3173	/**
3174	* Check if an SVM exception intercept is set.
3175	*/
3176	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
3177	(CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
3178
3179	/**
3180	* Invokes the SVM \#VMEXIT handler for the nested-guest.
3181	*/
3182	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3183	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
3184
3185	/**
3186	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
3187	* corresponding decode assist information.
3188	*/
3189	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
3190	do \
3191	{ \
3192	uint64_t uExitInfo1; \
3193	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
3194	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
3195	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
3196	else \
3197	uExitInfo1 = 0; \
3198	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
3199	} while (0)
3200
3201	/** Check and handles SVM nested-guest instruction intercept and updates
3202	* NRIP if needed.
3203	*/
3204	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3205	do \
3206	{ \
3207	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
3208	{ \
3209	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3210	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
3211	} \
3212	} while (0)
3213
3214	/** Checks and handles SVM nested-guest CR0 read intercept. */
3215	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) \
3216	do \
3217	{ \
3218	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
3219	{ /* probably likely */ } \
3220	else \
3221	{ \
3222	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3223	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
3224	} \
3225	} while (0)
3226
3227	/**
3228	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
3229	*/
3230	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) \
3231	do { \
3232	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
3233	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), IEM_GET_INSTR_LEN(a_pVCpu)); \
3234	} while (0)
3235
3236	#else
3237	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
3238	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3239	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3240	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3241	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3242	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
3243	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
3244	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
3245	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3246	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3247	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) do { } while (0)
3248
3249	#endif
3250
3251	/** @} */
3252
3253
3254
3255	/**
3256	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
3257	*/
3258	typedef union IEMSELDESC
3259	{
3260	/** The legacy view. */
3261	X86DESC Legacy;
3262	/** The long mode view. */
3263	X86DESC64 Long;
3264	} IEMSELDESC;
3265	/** Pointer to a selector descriptor table entry. */
3266	typedef IEMSELDESC *PIEMSELDESC;
3267
3268	/** @name Raising Exceptions.
3269	* @{ */
3270	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
3271	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
3272
3273	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
3274	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3275	#ifdef IEM_WITH_SETJMP
3276	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
3277	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3278	#endif
3279	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
3280	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3281	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
3282	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
3283	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
3284	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3285	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
3286	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3287	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3288	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
3289	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3290	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3291	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3292	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3293	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3294	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3295	#ifdef IEM_WITH_SETJMP
3296	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3297	#endif
3298	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3299	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
3300	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3301	#ifdef IEM_WITH_SETJMP
3302	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3303	#endif
3304	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3305	#ifdef IEM_WITH_SETJMP
3306	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3307	#endif
3308	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3309	#ifdef IEM_WITH_SETJMP
3310	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3311	#endif
3312	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
3313	#ifdef IEM_WITH_SETJMP
3314	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
3315	#endif
3316	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu);
3317	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu);
3318	#ifdef IEM_WITH_SETJMP
3319	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3320	#endif
3321	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3322
3323	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
3324	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
3325	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
3326
3327	/**
3328	* Macro for calling iemCImplRaiseDivideError().
3329	*
3330	* This enables us to add/remove arguments and force different levels of
3331	* inlining as we wish.
3332	*
3333	* @return Strict VBox status code.
3334	*/
3335	#define IEMOP_RAISE_DIVIDE_ERROR() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseDivideError)
3336
3337	/**
3338	* Macro for calling iemCImplRaiseInvalidLockPrefix().
3339	*
3340	* This enables us to add/remove arguments and force different levels of
3341	* inlining as we wish.
3342	*
3343	* @return Strict VBox status code.
3344	*/
3345	#define IEMOP_RAISE_INVALID_LOCK_PREFIX() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidLockPrefix)
3346
3347	/**
3348	* Macro for calling iemCImplRaiseInvalidOpcode().
3349	*
3350	* This enables us to add/remove arguments and force different levels of
3351	* inlining as we wish.
3352	*
3353	* @return Strict VBox status code.
3354	*/
3355	#define IEMOP_RAISE_INVALID_OPCODE() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidOpcode)
3356	/** @} */
3357
3358	/** @name Register Access.
3359	* @{ */
3360	VBOXSTRICTRC iemRegRipRelativeJumpS8(PVMCPUCC pVCpu, int8_t offNextInstr) RT_NOEXCEPT;
3361	VBOXSTRICTRC iemRegRipRelativeJumpS16(PVMCPUCC pVCpu, int16_t offNextInstr) RT_NOEXCEPT;
3362	VBOXSTRICTRC iemRegRipRelativeJumpS32(PVMCPUCC pVCpu, int32_t offNextInstr) RT_NOEXCEPT;
3363	VBOXSTRICTRC iemRegRipJump(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
3364	/** @} */
3365
3366	/** @name FPU access and helpers.
3367	* @{ */
3368	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult) RT_NOEXCEPT;
3369	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3370	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult) RT_NOEXCEPT;
3371	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3372	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3373	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3374	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3375	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3376	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3377	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3378	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3379	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3380	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3381	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3382	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3383	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3384	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3385	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3386	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3387	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu) RT_NOEXCEPT;
3388	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3389	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu) RT_NOEXCEPT;
3390	void iemFpuStackPushOverflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3391	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3392	/** @} */
3393
3394	/** @name SSE+AVX SIMD access and helpers.
3395	* @{ */
3396	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
3397	/** @} */
3398
3399	/** @name Memory access.
3400	* @{ */
3401
3402	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
3403	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
3404	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
3405	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
3406	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
3407	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
3408	* Users include FXSAVE & FXRSTOR. */
3409	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
3410
3411	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
3412	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
3413	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3414	#ifndef IN_RING3
3415	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3416	#endif
3417	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
3418	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
3419	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3420	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
3421
3422	#ifdef IEM_WITH_CODE_TLB
3423	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) RT_NOEXCEPT;
3424	#else
3425	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
3426	#endif
3427	#ifdef IEM_WITH_SETJMP
3428	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3429	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3430	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3431	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3432	#else
3433	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
3434	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3435	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3436	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3437	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3438	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3439	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3440	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3441	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3442	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3443	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3444	#endif
3445
3446	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3447	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3448	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3449	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3450	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3451	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3452	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3453	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3454	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3455	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3456	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3457	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3458	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
3459	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
3460	#ifdef IEM_WITH_SETJMP
3461	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3462	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3463	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3464	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3465	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3466	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3467	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3468	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3469	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3470	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3471	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3472	#endif
3473
3474	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3475	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3476	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3477	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3478	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
3479
3480	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
3481	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
3482	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
3483	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
3484	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3485	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3486	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3487	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3488	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3489	#ifdef IEM_WITH_SETJMP
3490	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
3491	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
3492	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
3493	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
3494	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3495	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3496	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3497	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3498	#endif
3499
3500	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
3501	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
3502	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
3503	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
3504	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3505	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
3506	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3507	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3508	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3509	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3510	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
3511	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
3512	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t cbMem, void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
3513	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
3514	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
3515	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
3516	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
3517	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3518	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3519	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3520	/** @} */
3521
3522	/** @name IEMAllCImpl.cpp
3523	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
3524	* @{ */
3525	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
3526	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
3527	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
3528	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
3529	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
3530	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
3531	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
3532	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
3533	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
3534	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
3535	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
3536	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
3537	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3538	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3539	IEM_CIMPL_PROTO_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3540	IEM_CIMPL_PROTO_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3541	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
3542	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
3543	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
3544	IEM_CIMPL_PROTO_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop);
3545	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
3546	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
3547	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
3548	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
3549	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
3550	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
3551	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
3552	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
3553	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
3554	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
3555	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
3556	IEM_CIMPL_PROTO_0(iemCImpl_sysret);
3557	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
3558	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
3559	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
3560	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
3561	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
3562	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
3563	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
3564	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
3565	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
3566	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
3567	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3568	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
3569	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3570	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
3571	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3572	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3573	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
3574	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3575	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3576	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
3577	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3578	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3579	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
3580	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
3581	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
3582	IEM_CIMPL_PROTO_0(iemCImpl_clts);
3583	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
3584	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
3585	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
3586	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
3587	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
3588	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
3589	IEM_CIMPL_PROTO_0(iemCImpl_invd);
3590	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
3591	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
3592	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
3593	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
3594	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
3595	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
3596	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
3597	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
3598	IEM_CIMPL_PROTO_1(iemCImpl_in_eAX_DX, uint8_t, cbReg);
3599	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
3600	IEM_CIMPL_PROTO_1(iemCImpl_out_DX_eAX, uint8_t, cbReg);
3601	IEM_CIMPL_PROTO_0(iemCImpl_cli);
3602	IEM_CIMPL_PROTO_0(iemCImpl_sti);
3603	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
3604	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
3605	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
3606	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
3607	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
3608	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
3609	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
3610	IEM_CIMPL_PROTO_0(iemCImpl_daa);
3611	IEM_CIMPL_PROTO_0(iemCImpl_das);
3612	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
3613	IEM_CIMPL_PROTO_0(iemCImpl_aas);
3614	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
3615	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
3616	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
3617	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
3618	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
3619	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
3620	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3621	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
3622	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3623	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3624	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3625	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3626	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3627	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3628	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3629	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3630	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3631	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
3632	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
3633	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
3634	IEM_CIMPL_PROTO_1(iemCImpl_fxch_underflow, uint8_t, iStReg);
3635	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop);
3636	/** @} */
3637
3638	/** @name IEMAllCImplStrInstr.cpp.h
3639	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
3640	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
3641	* @{ */
3642	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
3643	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
3644	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
3645	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
3646	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
3647	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
3648	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
3649	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
3650	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
3651	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3652	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3653
3654	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
3655	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
3656	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
3657	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
3658	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
3659	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
3660	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
3661	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
3662	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
3663	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3664	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3665
3666	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
3667	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
3668	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
3669	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
3670	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
3671	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
3672	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
3673	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
3674	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
3675	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3676	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3677
3678
3679	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
3680	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
3681	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
3682	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
3683	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
3684	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
3685	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
3686	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
3687	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
3688	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3689	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3690
3691	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
3692	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
3693	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
3694	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
3695	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
3696	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
3697	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
3698	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
3699	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
3700	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3701	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3702
3703	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
3704	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
3705	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
3706	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
3707	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
3708	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
3709	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
3710	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
3711	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
3712	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3713	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3714
3715	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
3716	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
3717	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
3718	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
3719	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
3720	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
3721	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
3722	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
3723	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
3724	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3725	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3726
3727
3728	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
3729	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
3730	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
3731	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
3732	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
3733	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
3734	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
3735	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
3736	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
3737	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3738	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3739
3740	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
3741	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
3742	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
3743	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
3744	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
3745	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
3746	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
3747	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
3748	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
3749	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3750	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3751
3752	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
3753	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
3754	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
3755	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
3756	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
3757	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
3758	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
3759	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
3760	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
3761	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3762	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3763
3764	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
3765	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
3766	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
3767	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
3768	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
3769	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
3770	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
3771	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
3772	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
3773	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3774	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3775	/** @} */
3776
3777	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3778	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
3779	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
3780	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
3781	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
3782	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
3783	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
3784	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
3785	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
3786	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
3787	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3788	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
3789	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3790	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
3791	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3792	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3793	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3794	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3795	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3796	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3797	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
3798	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
3799	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
3800	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
3801	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
3802	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
3803	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
3804	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
3805	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
3806	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
3807	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
3808	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
3809	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
3810	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
3811	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
3812	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3813	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3814	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3815	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
3816	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
3817	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
3818	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField);
3819	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
3820	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
3821	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
3822	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
3823	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
3824	#endif
3825
3826	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3827	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
3828	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3829	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
3830	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
3831	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite) RT_NOEXCEPT;
3832	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
3833	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
3834	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
3835	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
3836	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
3837	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
3838	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
3839	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
3840	#endif
3841
3842	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
3843	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
3844	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
3845
3846
3847	extern const PFNIEMOP g_apfnOneByteMap[256];
3848
3849	/** @} */
3850
3851	RT_C_DECLS_END
3852
3853	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
3854

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 96379

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