IEMInternal.h@ 96438

Last change on this file since 96438 was 96438, checked in by vboxsync, 3 years ago
VMM/IEM: Implement [v]phminposuw instructions, bugref:9898
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1	/* $Id: IEMInternal.h 96438 2022-08-23 13:16:15Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41
42
43	RT_C_DECLS_BEGIN
44
45
46	/** @defgroup grp_iem_int Internals
47	* @ingroup grp_iem
48	* @internal
49	* @{
50	*/
51
52	/** For expanding symbol in slickedit and other products tagging and
53	* crossreferencing IEM symbols. */
54	#ifndef IEM_STATIC
55	# define IEM_STATIC static
56	#endif
57
58	/** @def IEM_WITH_SETJMP
59	* Enables alternative status code handling using setjmps.
60	*
61	* This adds a bit of expense via the setjmp() call since it saves all the
62	* non-volatile registers. However, it eliminates return code checks and allows
63	* for more optimal return value passing (return regs instead of stack buffer).
64	*/
65	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
66	# define IEM_WITH_SETJMP
67	#endif
68
69	#define IEM_IMPLEMENTS_TASKSWITCH
70
71	/** @def IEM_WITH_3DNOW
72	* Includes the 3DNow decoding. */
73	#define IEM_WITH_3DNOW
74
75	/** @def IEM_WITH_THREE_0F_38
76	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
77	#define IEM_WITH_THREE_0F_38
78
79	/** @def IEM_WITH_THREE_0F_3A
80	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
81	#define IEM_WITH_THREE_0F_3A
82
83	/** @def IEM_WITH_VEX
84	* Includes the VEX decoding. */
85	#define IEM_WITH_VEX
86
87	/** @def IEM_CFG_TARGET_CPU
88	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
89	*
90	* By default we allow this to be configured by the user via the
91	* CPUM/GuestCpuName config string, but this comes at a slight cost during
92	* decoding. So, for applications of this code where there is no need to
93	* be dynamic wrt target CPU, just modify this define.
94	*/
95	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
96	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
97	#endif
98
99	//#define IEM_WITH_CODE_TLB // - work in progress
100	//#define IEM_WITH_DATA_TLB // - work in progress
101
102
103	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
104	* Use unaligned accesses instead of elaborate byte assembly. */
105	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
106	# define IEM_USE_UNALIGNED_DATA_ACCESS
107	#endif
108
109	//#define IEM_LOG_MEMORY_WRITES
110
111	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
112	/** Instruction statistics. */
113	typedef struct IEMINSTRSTATS
114	{
115	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
116	# include "IEMInstructionStatisticsTmpl.h"
117	# undef IEM_DO_INSTR_STAT
118	} IEMINSTRSTATS;
119	#else
120	struct IEMINSTRSTATS;
121	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
122	#endif
123	/** Pointer to IEM instruction statistics. */
124	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
125
126
127	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
128	* @{ */
129	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
130	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
131	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
132	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
133	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
134	/** Selects the right variant from a_aArray.
135	* pVCpu is implicit in the caller context. */
136	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
137	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
138	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
139	* be used because the host CPU does not support the operation. */
140	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
141	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
142	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
143	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
144	* into the two.
145	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
146	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
147	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
148	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
149	#else
150	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
151	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
152	#endif
153	/** @} */
154
155	/**
156	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
157	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
158	*
159	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
160	* indicator.
161	*
162	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
163	*/
164	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
165	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
166	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
167	#else
168	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
169	#endif
170
171
172	/**
173	* Extended operand mode that includes a representation of 8-bit.
174	*
175	* This is used for packing down modes when invoking some C instruction
176	* implementations.
177	*/
178	typedef enum IEMMODEX
179	{
180	IEMMODEX_16BIT = IEMMODE_16BIT,
181	IEMMODEX_32BIT = IEMMODE_32BIT,
182	IEMMODEX_64BIT = IEMMODE_64BIT,
183	IEMMODEX_8BIT
184	} IEMMODEX;
185	AssertCompileSize(IEMMODEX, 4);
186
187
188	/**
189	* Branch types.
190	*/
191	typedef enum IEMBRANCH
192	{
193	IEMBRANCH_JUMP = 1,
194	IEMBRANCH_CALL,
195	IEMBRANCH_TRAP,
196	IEMBRANCH_SOFTWARE_INT,
197	IEMBRANCH_HARDWARE_INT
198	} IEMBRANCH;
199	AssertCompileSize(IEMBRANCH, 4);
200
201
202	/**
203	* INT instruction types.
204	*/
205	typedef enum IEMINT
206	{
207	/** INT n instruction (opcode 0xcd imm). */
208	IEMINT_INTN = 0,
209	/** Single byte INT3 instruction (opcode 0xcc). */
210	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
211	/** Single byte INTO instruction (opcode 0xce). */
212	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
213	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
214	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
215	} IEMINT;
216	AssertCompileSize(IEMINT, 4);
217
218
219	/**
220	* A FPU result.
221	*/
222	typedef struct IEMFPURESULT
223	{
224	/** The output value. */
225	RTFLOAT80U r80Result;
226	/** The output status. */
227	uint16_t FSW;
228	} IEMFPURESULT;
229	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
230	/** Pointer to a FPU result. */
231	typedef IEMFPURESULT *PIEMFPURESULT;
232	/** Pointer to a const FPU result. */
233	typedef IEMFPURESULT const *PCIEMFPURESULT;
234
235
236	/**
237	* A FPU result consisting of two output values and FSW.
238	*/
239	typedef struct IEMFPURESULTTWO
240	{
241	/** The first output value. */
242	RTFLOAT80U r80Result1;
243	/** The output status. */
244	uint16_t FSW;
245	/** The second output value. */
246	RTFLOAT80U r80Result2;
247	} IEMFPURESULTTWO;
248	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
249	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
250	/** Pointer to a FPU result consisting of two output values and FSW. */
251	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
252	/** Pointer to a const FPU result consisting of two output values and FSW. */
253	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
254
255
256	/**
257	* IEM TLB entry.
258	*
259	* Lookup assembly:
260	* @code{.asm}
261	; Calculate tag.
262	mov rax, [VA]
263	shl rax, 16
264	shr rax, 16 + X86_PAGE_SHIFT
265	or rax, [uTlbRevision]
266
267	; Do indexing.
268	movzx ecx, al
269	lea rcx, [pTlbEntries + rcx]
270
271	; Check tag.
272	cmp [rcx + IEMTLBENTRY.uTag], rax
273	jne .TlbMiss
274
275	; Check access.
276	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
277	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
278	cmp rax, [uTlbPhysRev]
279	jne .TlbMiss
280
281	; Calc address and we're done.
282	mov eax, X86_PAGE_OFFSET_MASK
283	and eax, [VA]
284	or rax, [rcx + IEMTLBENTRY.pMappingR3]
285	%ifdef VBOX_WITH_STATISTICS
286	inc qword [cTlbHits]
287	%endif
288	jmp .Done
289
290	.TlbMiss:
291	mov r8d, ACCESS_FLAGS
292	mov rdx, [VA]
293	mov rcx, [pVCpu]
294	call iemTlbTypeMiss
295	.Done:
296
297	@endcode
298	*
299	*/
300	typedef struct IEMTLBENTRY
301	{
302	/** The TLB entry tag.
303	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
304	* is ASSUMING a virtual address width of 48 bits.
305	*
306	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
307	*
308	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
309	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
310	* revision wraps around though, the tags needs to be zeroed.
311	*
312	* @note Try use SHRD instruction? After seeing
313	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
314	*
315	* @todo This will need to be reorganized for 57-bit wide virtual address and
316	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
317	* have to move the TLB entry versioning entirely to the
318	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
319	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
320	* consumed by PCID and ASID (12 + 6 = 18).
321	*/
322	uint64_t uTag;
323	/** Access flags and physical TLB revision.
324	*
325	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
326	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
327	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
328	* - Bit 3 - pgm phys/virt - not directly writable.
329	* - Bit 4 - pgm phys page - not directly readable.
330	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
331	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
332	* - Bit 7 - tlb entry - pMappingR3 member not valid.
333	* - Bits 63 thru 8 are used for the physical TLB revision number.
334	*
335	* We're using complemented bit meanings here because it makes it easy to check
336	* whether special action is required. For instance a user mode write access
337	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
338	* non-zero result would mean special handling needed because either it wasn't
339	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
340	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
341	* need to check any PTE flag.
342	*/
343	uint64_t fFlagsAndPhysRev;
344	/** The guest physical page address. */
345	uint64_t GCPhys;
346	/** Pointer to the ring-3 mapping. */
347	R3PTRTYPE(uint8_t *) pbMappingR3;
348	#if HC_ARCH_BITS == 32
349	uint32_t u32Padding1;
350	#endif
351	} IEMTLBENTRY;
352	AssertCompileSize(IEMTLBENTRY, 32);
353	/** Pointer to an IEM TLB entry. */
354	typedef IEMTLBENTRY *PIEMTLBENTRY;
355
356	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
357	* @{ */
358	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
359	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
360	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
361	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
362	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
363	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
364	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
365	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
366	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
367	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
368	/** @} */
369
370
371	/**
372	* An IEM TLB.
373	*
374	* We've got two of these, one for data and one for instructions.
375	*/
376	typedef struct IEMTLB
377	{
378	/** The TLB entries.
379	* We've choosen 256 because that way we can obtain the result directly from a
380	* 8-bit register without an additional AND instruction. */
381	IEMTLBENTRY aEntries[256];
382	/** The TLB revision.
383	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
384	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
385	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
386	* (The revision zero indicates an invalid TLB entry.)
387	*
388	* The initial value is choosen to cause an early wraparound. */
389	uint64_t uTlbRevision;
390	/** The TLB physical address revision - shadow of PGM variable.
391	*
392	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
393	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
394	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
395	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
396	*
397	* The initial value is choosen to cause an early wraparound. */
398	uint64_t volatile uTlbPhysRev;
399
400	/* Statistics: */
401
402	/** TLB hits (VBOX_WITH_STATISTICS only). */
403	uint64_t cTlbHits;
404	/** TLB misses. */
405	uint32_t cTlbMisses;
406	/** Slow read path. */
407	uint32_t cTlbSlowReadPath;
408	#if 0
409	/** TLB misses because of tag mismatch. */
410	uint32_t cTlbMissesTag;
411	/** TLB misses because of virtual access violation. */
412	uint32_t cTlbMissesVirtAccess;
413	/** TLB misses because of dirty bit. */
414	uint32_t cTlbMissesDirty;
415	/** TLB misses because of MMIO */
416	uint32_t cTlbMissesMmio;
417	/** TLB misses because of write access handlers. */
418	uint32_t cTlbMissesWriteHandler;
419	/** TLB misses because no r3(/r0) mapping. */
420	uint32_t cTlbMissesMapping;
421	#endif
422	/** Alignment padding. */
423	uint32_t au32Padding[3+5];
424	} IEMTLB;
425	AssertCompileSizeAlignment(IEMTLB, 64);
426	/** IEMTLB::uTlbRevision increment. */
427	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
428	/** IEMTLB::uTlbRevision mask. */
429	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
430	/** IEMTLB::uTlbPhysRev increment.
431	* @sa IEMTLBE_F_PHYS_REV */
432	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
433	/**
434	* Calculates the TLB tag for a virtual address.
435	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
436	* @param a_pTlb The TLB.
437	* @param a_GCPtr The virtual address.
438	*/
439	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
440	/**
441	* Calculates the TLB tag for a virtual address but without TLB revision.
442	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
443	* @param a_GCPtr The virtual address.
444	*/
445	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
446	/**
447	* Converts a TLB tag value into a TLB index.
448	* @returns Index into IEMTLB::aEntries.
449	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
450	*/
451	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
452	/**
453	* Converts a TLB tag value into a TLB index.
454	* @returns Index into IEMTLB::aEntries.
455	* @param a_pTlb The TLB.
456	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
457	*/
458	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
459
460
461	/**
462	* The per-CPU IEM state.
463	*/
464	typedef struct IEMCPU
465	{
466	/** Info status code that needs to be propagated to the IEM caller.
467	* This cannot be passed internally, as it would complicate all success
468	* checks within the interpreter making the code larger and almost impossible
469	* to get right. Instead, we'll store status codes to pass on here. Each
470	* source of these codes will perform appropriate sanity checks. */
471	int32_t rcPassUp; /* 0x00 */
472
473	/** The current CPU execution mode (CS). */
474	IEMMODE enmCpuMode; /* 0x04 */
475	/** The CPL. */
476	uint8_t uCpl; /* 0x05 */
477
478	/** Whether to bypass access handlers or not. */
479	bool fBypassHandlers; /* 0x06 */
480	/** Whether to disregard the lock prefix (implied or not). */
481	bool fDisregardLock; /* 0x07 */
482
483	/** @name Decoder state.
484	* @{ */
485	#ifdef IEM_WITH_CODE_TLB
486	/** The offset of the next instruction byte. */
487	uint32_t offInstrNextByte; /* 0x08 */
488	/** The number of bytes available at pbInstrBuf for the current instruction.
489	* This takes the max opcode length into account so that doesn't need to be
490	* checked separately. */
491	uint32_t cbInstrBuf; /* 0x0c */
492	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
493	* This can be NULL if the page isn't mappable for some reason, in which
494	* case we'll do fallback stuff.
495	*
496	* If we're executing an instruction from a user specified buffer,
497	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
498	* aligned pointer but pointer to the user data.
499	*
500	* For instructions crossing pages, this will start on the first page and be
501	* advanced to the next page by the time we've decoded the instruction. This
502	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
503	*/
504	uint8_t const pbInstrBuf; / 0x10 */
505	# if ARCH_BITS == 32
506	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
507	# endif
508	/** The program counter corresponding to pbInstrBuf.
509	* This is set to a non-canonical address when we need to invalidate it. */
510	uint64_t uInstrBufPc; /* 0x18 */
511	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
512	* This takes the CS segment limit into account. */
513	uint16_t cbInstrBufTotal; /* 0x20 */
514	/** Offset into pbInstrBuf of the first byte of the current instruction.
515	* Can be negative to efficiently handle cross page instructions. */
516	int16_t offCurInstrStart; /* 0x22 */
517
518	/** The prefix mask (IEM_OP_PRF_XXX). */
519	uint32_t fPrefixes; /* 0x24 */
520	/** The extra REX ModR/M register field bit (REX.R << 3). */
521	uint8_t uRexReg; /* 0x28 */
522	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
523	* (REX.B << 3). */
524	uint8_t uRexB; /* 0x29 */
525	/** The extra REX SIB index field bit (REX.X << 3). */
526	uint8_t uRexIndex; /* 0x2a */
527
528	/** The effective segment register (X86_SREG_XXX). */
529	uint8_t iEffSeg; /* 0x2b */
530
531	/** The offset of the ModR/M byte relative to the start of the instruction. */
532	uint8_t offModRm; /* 0x2c */
533	#else
534	/** The size of what has currently been fetched into abOpcode. */
535	uint8_t cbOpcode; /* 0x08 */
536	/** The current offset into abOpcode. */
537	uint8_t offOpcode; /* 0x09 */
538	/** The offset of the ModR/M byte relative to the start of the instruction. */
539	uint8_t offModRm; /* 0x0a */
540
541	/** The effective segment register (X86_SREG_XXX). */
542	uint8_t iEffSeg; /* 0x0b */
543
544	/** The prefix mask (IEM_OP_PRF_XXX). */
545	uint32_t fPrefixes; /* 0x0c */
546	/** The extra REX ModR/M register field bit (REX.R << 3). */
547	uint8_t uRexReg; /* 0x10 */
548	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
549	* (REX.B << 3). */
550	uint8_t uRexB; /* 0x11 */
551	/** The extra REX SIB index field bit (REX.X << 3). */
552	uint8_t uRexIndex; /* 0x12 */
553
554	#endif
555
556	/** The effective operand mode. */
557	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
558	/** The default addressing mode. */
559	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
560	/** The effective addressing mode. */
561	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
562	/** The default operand mode. */
563	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
564
565	/** Prefix index (VEX.pp) for two byte and three byte tables. */
566	uint8_t idxPrefix; /* 0x31, 0x17 */
567	/** 3rd VEX/EVEX/XOP register.
568	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
569	uint8_t uVex3rdReg; /* 0x32, 0x18 */
570	/** The VEX/EVEX/XOP length field. */
571	uint8_t uVexLength; /* 0x33, 0x19 */
572	/** Additional EVEX stuff. */
573	uint8_t fEvexStuff; /* 0x34, 0x1a */
574
575	/** Explicit alignment padding. */
576	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
577	/** The FPU opcode (FOP). */
578	uint16_t uFpuOpcode; /* 0x36, 0x1c */
579	#ifndef IEM_WITH_CODE_TLB
580	/** Explicit alignment padding. */
581	uint8_t abAlignment2b[2]; /* 0x1e */
582	#endif
583
584	/** The opcode bytes. */
585	uint8_t abOpcode[15]; /* 0x48, 0x20 */
586	/** Explicit alignment padding. */
587	#ifdef IEM_WITH_CODE_TLB
588	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
589	#else
590	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
591	#endif
592	/** @} */
593
594
595	/** The flags of the current exception / interrupt. */
596	uint32_t fCurXcpt; /* 0x48, 0x48 */
597	/** The current exception / interrupt. */
598	uint8_t uCurXcpt;
599	/** Exception / interrupt recursion depth. */
600	int8_t cXcptRecursions;
601
602	/** The number of active guest memory mappings. */
603	uint8_t cActiveMappings;
604	/** The next unused mapping index. */
605	uint8_t iNextMapping;
606	/** Records for tracking guest memory mappings. */
607	struct
608	{
609	/** The address of the mapped bytes. */
610	void *pv;
611	/** The access flags (IEM_ACCESS_XXX).
612	* IEM_ACCESS_INVALID if the entry is unused. */
613	uint32_t fAccess;
614	#if HC_ARCH_BITS == 64
615	uint32_t u32Alignment4; /*< Alignment padding. /
616	#endif
617	} aMemMappings[3];
618
619	/** Locking records for the mapped memory. */
620	union
621	{
622	PGMPAGEMAPLOCK Lock;
623	uint64_t au64Padding[2];
624	} aMemMappingLocks[3];
625
626	/** Bounce buffer info.
627	* This runs in parallel to aMemMappings. */
628	struct
629	{
630	/** The physical address of the first byte. */
631	RTGCPHYS GCPhysFirst;
632	/** The physical address of the second page. */
633	RTGCPHYS GCPhysSecond;
634	/** The number of bytes in the first page. */
635	uint16_t cbFirst;
636	/** The number of bytes in the second page. */
637	uint16_t cbSecond;
638	/** Whether it's unassigned memory. */
639	bool fUnassigned;
640	/** Explicit alignment padding. */
641	bool afAlignment5[3];
642	} aMemBbMappings[3];
643
644	/** Bounce buffer storage.
645	* This runs in parallel to aMemMappings and aMemBbMappings. */
646	struct
647	{
648	uint8_t ab[512];
649	} aBounceBuffers[3];
650
651
652	/** Pointer set jump buffer - ring-3 context. */
653	R3PTRTYPE(jmp_buf *) pJmpBufR3;
654	/** Pointer set jump buffer - ring-0 context. */
655	R0PTRTYPE(jmp_buf *) pJmpBufR0;
656
657	/** @todo Should move this near @a fCurXcpt later. */
658	/** The CR2 for the current exception / interrupt. */
659	uint64_t uCurXcptCr2;
660	/** The error code for the current exception / interrupt. */
661	uint32_t uCurXcptErr;
662
663	/** @name Statistics
664	* @{ */
665	/** The number of instructions we've executed. */
666	uint32_t cInstructions;
667	/** The number of potential exits. */
668	uint32_t cPotentialExits;
669	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
670	* This may contain uncommitted writes. */
671	uint32_t cbWritten;
672	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
673	uint32_t cRetInstrNotImplemented;
674	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
675	uint32_t cRetAspectNotImplemented;
676	/** Counts informational statuses returned (other than VINF_SUCCESS). */
677	uint32_t cRetInfStatuses;
678	/** Counts other error statuses returned. */
679	uint32_t cRetErrStatuses;
680	/** Number of times rcPassUp has been used. */
681	uint32_t cRetPassUpStatus;
682	/** Number of times RZ left with instruction commit pending for ring-3. */
683	uint32_t cPendingCommit;
684	/** Number of long jumps. */
685	uint32_t cLongJumps;
686	/** @} */
687
688	/** @name Target CPU information.
689	* @{ */
690	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
691	/** The target CPU. */
692	uint8_t uTargetCpu;
693	#else
694	uint8_t bTargetCpuPadding;
695	#endif
696	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
697	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
698	* native host support and the 2nd for when there is.
699	*
700	* The two values are typically indexed by a g_CpumHostFeatures bit.
701	*
702	* This is for instance used for the BSF & BSR instructions where AMD and
703	* Intel CPUs produce different EFLAGS. */
704	uint8_t aidxTargetCpuEflFlavour[2];
705
706	/** The CPU vendor. */
707	CPUMCPUVENDOR enmCpuVendor;
708	/** @} */
709
710	/** @name Host CPU information.
711	* @{ */
712	/** The CPU vendor. */
713	CPUMCPUVENDOR enmHostCpuVendor;
714	/** @} */
715
716	/** Counts RDMSR \#GP(0) LogRel(). */
717	uint8_t cLogRelRdMsr;
718	/** Counts WRMSR \#GP(0) LogRel(). */
719	uint8_t cLogRelWrMsr;
720	/** Alignment padding. */
721	uint8_t abAlignment8[50];
722
723	/** Data TLB.
724	* @remarks Must be 64-byte aligned. */
725	IEMTLB DataTlb;
726	/** Instruction TLB.
727	* @remarks Must be 64-byte aligned. */
728	IEMTLB CodeTlb;
729
730	/** Exception statistics. */
731	STAMCOUNTER aStatXcpts[32];
732	/** Interrupt statistics. */
733	uint32_t aStatInts[256];
734
735	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
736	/** Instruction statistics for ring-0/raw-mode. */
737	IEMINSTRSTATS StatsRZ;
738	/** Instruction statistics for ring-3. */
739	IEMINSTRSTATS StatsR3;
740	#endif
741	} IEMCPU;
742	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
743	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
744	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
745	/** Pointer to the per-CPU IEM state. */
746	typedef IEMCPU *PIEMCPU;
747	/** Pointer to the const per-CPU IEM state. */
748	typedef IEMCPU const *PCIEMCPU;
749
750
751	/** @def IEM_GET_CTX
752	* Gets the guest CPU context for the calling EMT.
753	* @returns PCPUMCTX
754	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
755	*/
756	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
757
758	/** @def IEM_CTX_ASSERT
759	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
760	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
761	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
762	*/
763	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
764	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
765	(a_fExtrnMbz)))
766
767	/** @def IEM_CTX_IMPORT_RET
768	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
769	*
770	* Will call the keep to import the bits as needed.
771	*
772	* Returns on import failure.
773	*
774	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
775	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
776	*/
777	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
778	do { \
779	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
780	{ /* likely */ } \
781	else \
782	{ \
783	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
784	AssertRCReturn(rcCtxImport, rcCtxImport); \
785	} \
786	} while (0)
787
788	/** @def IEM_CTX_IMPORT_NORET
789	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
790	*
791	* Will call the keep to import the bits as needed.
792	*
793	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
794	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
795	*/
796	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
797	do { \
798	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
799	{ /* likely */ } \
800	else \
801	{ \
802	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
803	AssertLogRelRC(rcCtxImport); \
804	} \
805	} while (0)
806
807	/** @def IEM_CTX_IMPORT_JMP
808	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
809	*
810	* Will call the keep to import the bits as needed.
811	*
812	* Jumps on import failure.
813	*
814	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
815	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
816	*/
817	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
818	do { \
819	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
820	{ /* likely */ } \
821	else \
822	{ \
823	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
824	AssertRCStmt(rcCtxImport, longjmp(*pVCpu->iem.s.CTX_SUFF(pJmpBuf), rcCtxImport)); \
825	} \
826	} while (0)
827
828
829
830	/** @def IEM_GET_TARGET_CPU
831	* Gets the current IEMTARGETCPU value.
832	* @returns IEMTARGETCPU value.
833	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
834	*/
835	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
836	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
837	#else
838	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
839	#endif
840
841	/** @def IEM_GET_INSTR_LEN
842	* Gets the instruction length. */
843	#ifdef IEM_WITH_CODE_TLB
844	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
845	#else
846	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
847	#endif
848
849
850	/**
851	* Shared per-VM IEM data.
852	*/
853	typedef struct IEM
854	{
855	/** The VMX APIC-access page handler type. */
856	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
857	} IEM;
858
859
860
861	/** @name IEM_ACCESS_XXX - Access details.
862	* @{ */
863	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
864	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
865	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
866	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
867	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
868	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
869	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
870	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
871	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
872	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
873	/** The writes are partial, so if initialize the bounce buffer with the
874	* orignal RAM content. */
875	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
876	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
877	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
878	/** Bounce buffer with ring-3 write pending, first page. */
879	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
880	/** Bounce buffer with ring-3 write pending, second page. */
881	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
882	/** Not locked, accessed via the TLB. */
883	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
884	/** Valid bit mask. */
885	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
886	/** Shift count for the TLB flags (upper word). */
887	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
888
889	/** Read+write data alias. */
890	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
891	/** Write data alias. */
892	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
893	/** Read data alias. */
894	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
895	/** Instruction fetch alias. */
896	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
897	/** Stack write alias. */
898	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
899	/** Stack read alias. */
900	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
901	/** Stack read+write alias. */
902	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
903	/** Read system table alias. */
904	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
905	/** Read+write system table alias. */
906	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
907	/** @} */
908
909	/** @name Prefix constants (IEMCPU::fPrefixes)
910	* @{ */
911	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
912	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
913	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
914	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
915	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
916	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
917	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
918
919	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
920	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
921	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
922
923	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
924	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
925	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
926
927	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
928	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
929	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
930	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
931	/** Mask with all the REX prefix flags.
932	* This is generally for use when needing to undo the REX prefixes when they
933	* are followed legacy prefixes and therefore does not immediately preceed
934	* the first opcode byte.
935	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
936	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
937
938	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
939	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
940	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
941	/** @} */
942
943	/** @name IEMOPFORM_XXX - Opcode forms
944	* @note These are ORed together with IEMOPHINT_XXX.
945	* @{ */
946	/** ModR/M: reg, r/m */
947	#define IEMOPFORM_RM 0
948	/** ModR/M: reg, r/m (register) */
949	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
950	/** ModR/M: reg, r/m (memory) */
951	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
952	/** ModR/M: reg, r/m */
953	#define IEMOPFORM_RMI 1
954	/** ModR/M: reg, r/m (register) */
955	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
956	/** ModR/M: reg, r/m (memory) */
957	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
958	/** ModR/M: r/m, reg */
959	#define IEMOPFORM_MR 2
960	/** ModR/M: r/m (register), reg */
961	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
962	/** ModR/M: r/m (memory), reg */
963	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
964	/** ModR/M: r/m only */
965	#define IEMOPFORM_M 3
966	/** ModR/M: r/m only (register). */
967	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
968	/** ModR/M: r/m only (memory). */
969	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
970	/** ModR/M: reg only */
971	#define IEMOPFORM_R 4
972
973	/** VEX+ModR/M: reg, r/m */
974	#define IEMOPFORM_VEX_RM 8
975	/** VEX+ModR/M: reg, r/m (register) */
976	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
977	/** VEX+ModR/M: reg, r/m (memory) */
978	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
979	/** VEX+ModR/M: r/m, reg */
980	#define IEMOPFORM_VEX_MR 9
981	/** VEX+ModR/M: r/m (register), reg */
982	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
983	/** VEX+ModR/M: r/m (memory), reg */
984	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
985	/** VEX+ModR/M: r/m only */
986	#define IEMOPFORM_VEX_M 10
987	/** VEX+ModR/M: r/m only (register). */
988	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
989	/** VEX+ModR/M: r/m only (memory). */
990	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
991	/** VEX+ModR/M: reg only */
992	#define IEMOPFORM_VEX_R 11
993	/** VEX+ModR/M: reg, vvvv, r/m */
994	#define IEMOPFORM_VEX_RVM 12
995	/** VEX+ModR/M: reg, vvvv, r/m (register). */
996	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
997	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
998	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
999	/** VEX+ModR/M: reg, r/m, vvvv */
1000	#define IEMOPFORM_VEX_RMV 13
1001	/** VEX+ModR/M: reg, r/m, vvvv (register). */
1002	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
1003	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1004	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
1005	/** VEX+ModR/M: reg, r/m, imm8 */
1006	#define IEMOPFORM_VEX_RMI 14
1007	/** VEX+ModR/M: reg, r/m, imm8 (register). */
1008	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
1009	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1010	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1011	/** VEX+ModR/M: r/m, vvvv, reg */
1012	#define IEMOPFORM_VEX_MVR 15
1013	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1014	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1015	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1016	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1017	/** VEX+ModR/M+/n: vvvv, r/m */
1018	#define IEMOPFORM_VEX_VM 16
1019	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1020	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1021	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1022	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1023
1024	/** Fixed register instruction, no R/M. */
1025	#define IEMOPFORM_FIXED 32
1026
1027	/** The r/m is a register. */
1028	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1029	/** The r/m is a memory access. */
1030	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1031	/** @} */
1032
1033	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1034	* @note These are ORed together with IEMOPFORM_XXX.
1035	* @{ */
1036	/** Ignores the operand size prefix (66h). */
1037	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1038	/** Ignores REX.W (aka WIG). */
1039	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1040	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1041	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1042	/** Allowed with the lock prefix. */
1043	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1044	/** The VEX.L value is ignored (aka LIG). */
1045	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1046	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1047	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1048	/** The VEX.V value must be zero. */
1049	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1050
1051	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1052	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1053	/** @} */
1054
1055	/**
1056	* Possible hardware task switch sources.
1057	*/
1058	typedef enum IEMTASKSWITCH
1059	{
1060	/** Task switch caused by an interrupt/exception. */
1061	IEMTASKSWITCH_INT_XCPT = 1,
1062	/** Task switch caused by a far CALL. */
1063	IEMTASKSWITCH_CALL,
1064	/** Task switch caused by a far JMP. */
1065	IEMTASKSWITCH_JUMP,
1066	/** Task switch caused by an IRET. */
1067	IEMTASKSWITCH_IRET
1068	} IEMTASKSWITCH;
1069	AssertCompileSize(IEMTASKSWITCH, 4);
1070
1071	/**
1072	* Possible CrX load (write) sources.
1073	*/
1074	typedef enum IEMACCESSCRX
1075	{
1076	/** CrX access caused by 'mov crX' instruction. */
1077	IEMACCESSCRX_MOV_CRX,
1078	/** CrX (CR0) write caused by 'lmsw' instruction. */
1079	IEMACCESSCRX_LMSW,
1080	/** CrX (CR0) write caused by 'clts' instruction. */
1081	IEMACCESSCRX_CLTS,
1082	/** CrX (CR0) read caused by 'smsw' instruction. */
1083	IEMACCESSCRX_SMSW
1084	} IEMACCESSCRX;
1085
1086	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1087	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1088	*
1089	* These flags provide further context to SLAT page-walk failures that could not be
1090	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1091	*
1092	* @{
1093	*/
1094	/** Translating a nested-guest linear address failed accessing a nested-guest
1095	* physical address. */
1096	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1097	/** Translating a nested-guest linear address failed accessing a
1098	* paging-structure entry or updating accessed/dirty bits. */
1099	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1100	/** @} */
1101
1102	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1103	# ifndef IN_RING3
1104	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1105	# endif
1106	#endif
1107
1108	/**
1109	* Indicates to the verifier that the given flag set is undefined.
1110	*
1111	* Can be invoked again to add more flags.
1112	*
1113	* This is a NOOP if the verifier isn't compiled in.
1114	*
1115	* @note We're temporarily keeping this until code is converted to new
1116	* disassembler style opcode handling.
1117	*/
1118	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1119
1120
1121	/** @def IEM_DECL_IMPL_TYPE
1122	* For typedef'ing an instruction implementation function.
1123	*
1124	* @param a_RetType The return type.
1125	* @param a_Name The name of the type.
1126	* @param a_ArgList The argument list enclosed in parentheses.
1127	*/
1128
1129	/** @def IEM_DECL_IMPL_DEF
1130	* For defining an instruction implementation function.
1131	*
1132	* @param a_RetType The return type.
1133	* @param a_Name The name of the type.
1134	* @param a_ArgList The argument list enclosed in parentheses.
1135	*/
1136
1137	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1138	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1139	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1140	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1141	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1142	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1143	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1144
1145	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1146	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1147	a_RetType (__fastcall a_Name) a_ArgList
1148	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1149	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1150	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1151	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1152
1153	#elif __cplusplus >= 201700 /* P0012R1 support */
1154	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1155	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1156	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1157	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1158	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1159	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1160
1161	#else
1162	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1163	a_RetType (VBOXCALL a_Name) a_ArgList
1164	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1165	a_RetType VBOXCALL a_Name a_ArgList
1166	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1167	a_RetType VBOXCALL a_Name a_ArgList
1168
1169	#endif
1170
1171	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1172	RT_C_DECLS_BEGIN
1173	extern uint8_t const g_afParity[256];
1174	RT_C_DECLS_END
1175
1176
1177	/** @name Arithmetic assignment operations on bytes (binary).
1178	* @{ */
1179	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1180	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1181	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1182	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1183	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1184	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1185	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1186	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1187	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1188	/** @} */
1189
1190	/** @name Arithmetic assignment operations on words (binary).
1191	* @{ */
1192	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1193	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1194	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1195	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1196	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1197	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1198	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1199	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1200	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1201	/** @} */
1202
1203	/** @name Arithmetic assignment operations on double words (binary).
1204	* @{ */
1205	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1206	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1207	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1208	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1209	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1210	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1211	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1212	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1213	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1214	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1215	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1216	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1217	/** @} */
1218
1219	/** @name Arithmetic assignment operations on quad words (binary).
1220	* @{ */
1221	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1222	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1223	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1224	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1225	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1226	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1227	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1228	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1229	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1230	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1231	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1232	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1233	/** @} */
1234
1235	/** @name Compare operations (thrown in with the binary ops).
1236	* @{ */
1237	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1238	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1239	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1240	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1241	/** @} */
1242
1243	/** @name Test operations (thrown in with the binary ops).
1244	* @{ */
1245	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1246	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1247	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1248	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1249	/** @} */
1250
1251	/** @name Bit operations operations (thrown in with the binary ops).
1252	* @{ */
1253	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1254	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1255	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1256	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1257	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1258	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1259	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1260	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1261	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1262	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1263	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1264	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1265	/** @} */
1266
1267	/** @name Arithmetic three operand operations on double words (binary).
1268	* @{ */
1269	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
1270	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1271	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1272	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1273	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1274	/** @} */
1275
1276	/** @name Arithmetic three operand operations on quad words (binary).
1277	* @{ */
1278	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
1279	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1280	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1281	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1282	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1283	/** @} */
1284
1285	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1286	* @{ */
1287	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1288	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1289	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1290	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1291	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1292	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1293	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1294	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1295	/** @} */
1296
1297	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1298	* @{ */
1299	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1300	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1301	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1302	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1303	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1304	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1305	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1306	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1307	/** @} */
1308
1309	/** @name MULX 32-bit and 64-bit.
1310	* @{ */
1311	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
1312	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1313	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1314
1315	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
1316	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1317	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1318	/** @} */
1319
1320
1321	/** @name Exchange memory with register operations.
1322	* @{ */
1323	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1324	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1325	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1326	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1327	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1328	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1329	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1330	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1331	/** @} */
1332
1333	/** @name Exchange and add operations.
1334	* @{ */
1335	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1336	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1337	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1338	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1339	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1340	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1341	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1342	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1343	/** @} */
1344
1345	/** @name Compare and exchange.
1346	* @{ */
1347	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1348	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1349	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1350	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1351	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1352	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1353	#if ARCH_BITS == 32
1354	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1355	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1356	#else
1357	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1358	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1359	#endif
1360	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1361	uint32_t *pEFlags));
1362	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1363	uint32_t *pEFlags));
1364	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1365	uint32_t *pEFlags));
1366	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1367	uint32_t *pEFlags));
1368	#ifndef RT_ARCH_ARM64
1369	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1370	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1371	#endif
1372	/** @} */
1373
1374	/** @name Memory ordering
1375	* @{ */
1376	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1377	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1378	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1379	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1380	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1381	#ifndef RT_ARCH_ARM64
1382	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1383	#endif
1384	/** @} */
1385
1386	/** @name Double precision shifts
1387	* @{ */
1388	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1389	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1390	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1391	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1392	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1393	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1394	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1395	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1396	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1397	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1398	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1399	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1400	/** @} */
1401
1402
1403	/** @name Bit search operations (thrown in with the binary ops).
1404	* @{ */
1405	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1406	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1407	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1408	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1409	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1410	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1411	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1412	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1413	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1414	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
1415	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
1416	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
1417	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
1418	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
1419	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
1420	/** @} */
1421
1422	/** @name Signed multiplication operations (thrown in with the binary ops).
1423	* @{ */
1424	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1425	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1426	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1427	/** @} */
1428
1429	/** @name Arithmetic assignment operations on bytes (unary).
1430	* @{ */
1431	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1432	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1433	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1434	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1435	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1436	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1437	/** @} */
1438
1439	/** @name Arithmetic assignment operations on words (unary).
1440	* @{ */
1441	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1442	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1443	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1444	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1445	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1446	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1447	/** @} */
1448
1449	/** @name Arithmetic assignment operations on double words (unary).
1450	* @{ */
1451	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1452	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1453	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1454	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1455	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1456	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1457	/** @} */
1458
1459	/** @name Arithmetic assignment operations on quad words (unary).
1460	* @{ */
1461	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1462	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1463	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1464	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1465	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1466	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1467	/** @} */
1468
1469
1470	/** @name Shift operations on bytes (Group 2).
1471	* @{ */
1472	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1473	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1474	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1475	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1476	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1477	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1478	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1479	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1480	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1481	/** @} */
1482
1483	/** @name Shift operations on words (Group 2).
1484	* @{ */
1485	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1486	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1487	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1488	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1489	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1490	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1491	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1492	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1493	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1494	/** @} */
1495
1496	/** @name Shift operations on double words (Group 2).
1497	* @{ */
1498	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1499	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1500	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1501	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1502	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1503	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1504	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1505	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1506	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1507	/** @} */
1508
1509	/** @name Shift operations on words (Group 2).
1510	* @{ */
1511	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1512	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1513	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1514	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1515	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1516	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1517	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1518	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1519	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1520	/** @} */
1521
1522	/** @name Multiplication and division operations.
1523	* @{ */
1524	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1525	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1526	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1527	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1528	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1529	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1530
1531	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1532	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1533	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1534	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1535	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1536	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1537
1538	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1539	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1540	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1541	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1542	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1543	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1544
1545	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1546	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1547	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1548	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1549	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1550	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1551	/** @} */
1552
1553	/** @name Byte Swap.
1554	* @{ */
1555	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1556	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1557	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1558	/** @} */
1559
1560	/** @name Misc.
1561	* @{ */
1562	FNIEMAIMPLBINU16 iemAImpl_arpl;
1563	/** @} */
1564
1565
1566	/** @name FPU operations taking a 32-bit float argument
1567	* @{ */
1568	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1569	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1570	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1571
1572	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1573	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1574	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1575
1576	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1577	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1578	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1579	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1580	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1581	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1582	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1583
1584	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1585	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1586	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1587	/** @} */
1588
1589	/** @name FPU operations taking a 64-bit float argument
1590	* @{ */
1591	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1592	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1593	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
1594
1595	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1596	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1597	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1598
1599	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
1600	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1601	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1602	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1603	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1604	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1605	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1606
1607	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1608	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1609	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1610	/** @} */
1611
1612	/** @name FPU operations taking a 80-bit float argument
1613	* @{ */
1614	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1615	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1616	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1617	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1618	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1619	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1620	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1621	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1622	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1623	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1624	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1625	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1626
1627	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
1628	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
1629	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
1630
1631	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1632	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1633	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1634	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1635	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1636
1637	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1638	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1639	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1640	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1641	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1642
1643	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1644	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1645	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1646	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1647	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
1648	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1649	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1650	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
1651	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
1652
1653	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1654	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1655	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1656	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1657
1658	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1659	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1660	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1661	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1662	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1663	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1664	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1665	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1666	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1667
1668	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1669	PCRTFLOAT80U pr80Val));
1670	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1671	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
1672	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1673	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
1674
1675	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1676	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1677	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1678
1679	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
1680	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1681	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
1682
1683	/** @} */
1684
1685	/** @name FPU operations taking a 16-bit signed integer argument
1686	* @{ */
1687	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1688	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1689	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1690	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1691	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
1692	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
1693
1694	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1695	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1696	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1697	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1698	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1699	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1700
1701	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1702	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1703	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
1704	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
1705
1706	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1707	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
1708	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
1709	/** @} */
1710
1711	/** @name FPU operations taking a 32-bit signed integer argument
1712	* @{ */
1713	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1714	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1715	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1716	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1717	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
1718	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
1719
1720	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1721	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1722	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1723	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1724	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1725	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1726
1727	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1728	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1729	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
1730	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
1731
1732	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1733	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
1734	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
1735	/** @} */
1736
1737	/** @name FPU operations taking a 64-bit signed integer argument
1738	* @{ */
1739	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1740	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
1741	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
1742
1743	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1744	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
1745	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
1746	/** @} */
1747
1748
1749	/** Temporary type representing a 256-bit vector register. */
1750	typedef struct { uint64_t au64[4]; } IEMVMM256;
1751	/** Temporary type pointing to a 256-bit vector register. */
1752	typedef IEMVMM256 *PIEMVMM256;
1753	/** Temporary type pointing to a const 256-bit vector register. */
1754	typedef IEMVMM256 *PCIEMVMM256;
1755
1756
1757	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1758	* @{ */
1759	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
1760	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1761	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1762	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1763	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1764	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
1765	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1766	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
1767	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
1768	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
1769	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
1770	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
1771	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1772	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
1773	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1774	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
1775	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
1776	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
1777	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
1778	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
1779	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1780	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
1781	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
1782	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
1783	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
1784	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
1785	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
1786	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
1787	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
1788	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
1789	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
1790	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
1791	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
1792	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
1793	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
1794	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
1795	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
1796	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
1797	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
1798	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
1799	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
1800	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
1801	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
1802	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
1803	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
1804	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
1805	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
1806	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
1807	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
1808	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
1809	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
1810	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
1811	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
1812	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
1813	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
1814	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
1815	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
1816
1817	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
1818	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
1819	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1820	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
1821	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
1822	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
1823	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
1824	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
1825	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
1826	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
1827	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
1828	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
1829	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
1830	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
1831	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
1832	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
1833	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
1834	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
1835	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
1836	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
1837	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
1838	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
1839	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
1840	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
1841	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
1842	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
1843	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
1844	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
1845	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
1846	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
1847	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
1848	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
1849	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
1850	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
1851	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
1852	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
1853	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
1854	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
1855	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
1856	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
1857	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
1858	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
1859	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
1860	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
1861	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
1862	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
1863	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
1864	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
1865	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
1866	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
1867	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
1868	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
1869	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
1870	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
1871	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
1872	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
1873	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
1874
1875	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
1876	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
1877	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
1878	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
1879	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
1880	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
1881	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
1882	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
1883	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
1884	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
1885	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
1886	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
1887	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
1888	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
1889	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
1890	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
1891	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
1892	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
1893	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
1894	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
1895	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
1896	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
1897	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
1898	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
1899	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
1900	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
1901	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
1902	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
1903	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
1904	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
1905	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
1906	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
1907	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
1908	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
1909	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
1910	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
1911	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
1912	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
1913	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
1914	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
1915	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
1916	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
1917	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
1918	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
1919	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
1920	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
1921	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
1922	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
1923	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
1924	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
1925	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
1926	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
1927	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
1928	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
1929	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
1930	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
1931	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
1932
1933	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
1934	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
1935	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
1936	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
1937
1938	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
1939	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
1940	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
1941	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
1942	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
1943	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
1944	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
1945	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
1946	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
1947	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
1948	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
1949	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
1950	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
1951	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
1952	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
1953	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
1954	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
1955	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
1956	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
1957	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
1958	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
1959	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
1960	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
1961	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
1962	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
1963	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
1964	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
1965	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
1966	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
1967	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
1968	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
1969	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
1970	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
1971	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
1972	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
1973	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
1974	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
1975	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
1976	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
1977	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
1978	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
1979	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
1980	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
1981	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
1982	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
1983	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
1984	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
1985	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
1986	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
1987	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
1988	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
1989	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
1990	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
1991	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
1992	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
1993	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
1994	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
1995
1996	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
1997	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
1998	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
1999	/** @} */
2000
2001	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2002	* @{ */
2003	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2004	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2005	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2006	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2007	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2008	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2009	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2010	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2011	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2012	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2013
2014	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2015	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2016	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2017	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2018	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2019	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2020	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2021	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2022	/** @} */
2023
2024	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2025	* @{ */
2026	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2027	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2028	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2029	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2030	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2031	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2032	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2033	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2034	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2035	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2036	/** @} */
2037
2038	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2039	* @{ */
2040	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2041	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2042	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2043	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2044	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
2045	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2046	#ifndef IEM_WITHOUT_ASSEMBLY
2047	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2048	#endif
2049	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2050	/** @} */
2051
2052	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2053	* @{ */
2054	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2055	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2056	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2057	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2058	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2059	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2060	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2061	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2062	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2063	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2064	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2065	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2066	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2067	/** @} */
2068
2069	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2070	* @{ */
2071	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
2072	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2073	#ifndef IEM_WITHOUT_ASSEMBLY
2074	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2075	#endif
2076	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2077	/** @} */
2078
2079	/** @name Media (SSE/MMX/AVX) operation: Sort this later
2080	* @{ */
2081	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2082	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2083	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PRTUINT128U puDst, uint64_t uSrc));
2084
2085	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2086	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2087	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2088	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2089	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2090	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2091
2092	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2093	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2094	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2095	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2096	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2097
2098	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2099	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2100	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2101	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2102	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2103
2104	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2105	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2106	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2107	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2108	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2109
2110	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2111	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2112	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2113	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2114	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2115
2116	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2117	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2118	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2119	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2120	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2121
2122	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2123	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2124	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2125	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2126	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2127
2128	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2129	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2130	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2131	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2132	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2133
2134	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2135	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2136	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2137	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2138	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2139
2140	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2141	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2142	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2143	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2144	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2145
2146	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2147	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2148	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2149	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2150	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2151
2152	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2153	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2154	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2155	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2156	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2157
2158	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2159	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2160	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2161	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2162	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2163
2164	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2165	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2166	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2167	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2168	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2169
2170	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2171	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2172	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2173	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2174	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2175	/** @} */
2176
2177	/** @name Media Odds and Ends
2178	* @{ */
2179	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
2180	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
2181	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
2182	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
2183	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
2184	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
2185	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
2186	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
2187
2188	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
2189	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
2190	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
2191	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
2192	/** @} */
2193
2194
2195	/** @name Function tables.
2196	* @{
2197	*/
2198
2199	/**
2200	* Function table for a binary operator providing implementation based on
2201	* operand size.
2202	*/
2203	typedef struct IEMOPBINSIZES
2204	{
2205	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
2206	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
2207	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
2208	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
2209	} IEMOPBINSIZES;
2210	/** Pointer to a binary operator function table. */
2211	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
2212
2213
2214	/**
2215	* Function table for a unary operator providing implementation based on
2216	* operand size.
2217	*/
2218	typedef struct IEMOPUNARYSIZES
2219	{
2220	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
2221	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
2222	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
2223	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
2224	} IEMOPUNARYSIZES;
2225	/** Pointer to a unary operator function table. */
2226	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
2227
2228
2229	/**
2230	* Function table for a shift operator providing implementation based on
2231	* operand size.
2232	*/
2233	typedef struct IEMOPSHIFTSIZES
2234	{
2235	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
2236	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
2237	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
2238	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
2239	} IEMOPSHIFTSIZES;
2240	/** Pointer to a shift operator function table. */
2241	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
2242
2243
2244	/**
2245	* Function table for a multiplication or division operation.
2246	*/
2247	typedef struct IEMOPMULDIVSIZES
2248	{
2249	PFNIEMAIMPLMULDIVU8 pfnU8;
2250	PFNIEMAIMPLMULDIVU16 pfnU16;
2251	PFNIEMAIMPLMULDIVU32 pfnU32;
2252	PFNIEMAIMPLMULDIVU64 pfnU64;
2253	} IEMOPMULDIVSIZES;
2254	/** Pointer to a multiplication or division operation function table. */
2255	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
2256
2257
2258	/**
2259	* Function table for a double precision shift operator providing implementation
2260	* based on operand size.
2261	*/
2262	typedef struct IEMOPSHIFTDBLSIZES
2263	{
2264	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
2265	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
2266	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
2267	} IEMOPSHIFTDBLSIZES;
2268	/** Pointer to a double precision shift function table. */
2269	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
2270
2271
2272	/**
2273	* Function table for media instruction taking two full sized media source
2274	* registers and one full sized destination register (AVX).
2275	*/
2276	typedef struct IEMOPMEDIAF3
2277	{
2278	PFNIEMAIMPLMEDIAF3U128 pfnU128;
2279	PFNIEMAIMPLMEDIAF3U256 pfnU256;
2280	} IEMOPMEDIAF3;
2281	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2282	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
2283
2284	/** @def IEMOPMEDIAF3_INIT_VARS_EX
2285	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2286	* given functions as initializers. For use in AVX functions where a pair of
2287	* functions are only used once and the function table need not be public. */
2288	#ifndef TST_IEM_CHECK_MC
2289	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2290	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2291	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2292	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2293	# else
2294	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2295	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2296	# endif
2297	#else
2298	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2299	#endif
2300	/** @def IEMOPMEDIAF3_INIT_VARS
2301	* Generate AVX function tables for the @a a_InstrNm instruction.
2302	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
2303	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
2304	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2305	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2306
2307	/**
2308	* Function table for media instruction taking two full sized media source
2309	* registers and one full sized destination register, but no additional state
2310	* (AVX).
2311	*/
2312	typedef struct IEMOPMEDIAOPTF3
2313	{
2314	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
2315	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
2316	} IEMOPMEDIAOPTF3;
2317	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2318	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
2319
2320	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
2321	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2322	* given functions as initializers. For use in AVX functions where a pair of
2323	* functions are only used once and the function table need not be public. */
2324	#ifndef TST_IEM_CHECK_MC
2325	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2326	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2327	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2328	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2329	# else
2330	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2331	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2332	# endif
2333	#else
2334	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2335	#endif
2336	/** @def IEMOPMEDIAOPTF3_INIT_VARS
2337	* Generate AVX function tables for the @a a_InstrNm instruction.
2338	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
2339	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
2340	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2341	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2342
2343	/**
2344	* Function table for media instruction taking one full sized media source
2345	* registers and one full sized destination register, but no additional state
2346	* (AVX).
2347	*/
2348	typedef struct IEMOPMEDIAOPTF2
2349	{
2350	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
2351	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
2352	} IEMOPMEDIAOPTF2;
2353	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
2354	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
2355
2356	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
2357	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2358	* given functions as initializers. For use in AVX functions where a pair of
2359	* functions are only used once and the function table need not be public. */
2360	#ifndef TST_IEM_CHECK_MC
2361	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2362	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2363	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2364	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2365	# else
2366	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2367	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2368	# endif
2369	#else
2370	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2371	#endif
2372	/** @def IEMOPMEDIAOPTF2_INIT_VARS
2373	* Generate AVX function tables for the @a a_InstrNm instruction.
2374	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
2375	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
2376	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2377	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2378	/** @} */
2379
2380
2381	/** @name SSE/AVX single/double precision floating point operations.
2382	* @{ */
2383	/**
2384	* A SSE result.
2385	*/
2386	typedef struct IEMSSERESULT
2387	{
2388	/** The output value. */
2389	X86XMMREG uResult;
2390	/** The output status. */
2391	uint32_t MXCSR;
2392	} IEMSSERESULT;
2393	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
2394	/** Pointer to a SSE result. */
2395	typedef IEMSSERESULT *PIEMSSERESULT;
2396	/** Pointer to a const SSE result. */
2397	typedef IEMSSERESULT const *PCIEMSSERESULT;
2398
2399
2400	/**
2401	* A AVX128 result.
2402	*/
2403	typedef struct IEMAVX128RESULT
2404	{
2405	/** The output value. */
2406	X86XMMREG uResult;
2407	/** The output status. */
2408	uint32_t MXCSR;
2409	} IEMAVX128RESULT;
2410	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
2411	/** Pointer to a AVX128 result. */
2412	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
2413	/** Pointer to a const AVX128 result. */
2414	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
2415
2416
2417	/**
2418	* A AVX256 result.
2419	*/
2420	typedef struct IEMAVX256RESULT
2421	{
2422	/** The output value. */
2423	X86YMMREG uResult;
2424	/** The output status. */
2425	uint32_t MXCSR;
2426	} IEMAVX256RESULT;
2427	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
2428	/** Pointer to a AVX256 result. */
2429	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
2430	/** Pointer to a const AVX256 result. */
2431	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
2432
2433
2434	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2435	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
2436	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2437	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
2438	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2439	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
2440
2441	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2442	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
2443	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2444	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
2445	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2446	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
2447
2448	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
2449	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
2450
2451	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
2452	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
2453	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
2454	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
2455	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
2456	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
2457	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
2458	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
2459	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
2460	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
2461	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
2462	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
2463	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
2464	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
2465	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
2466	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
2467	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
2468	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
2469	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
2470	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
2471	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
2472
2473	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
2474	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
2475	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
2476	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
2477	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
2478	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
2479	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
2480	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
2481	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
2482	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
2483	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
2484	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
2485	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
2486	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
2487	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
2488	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
2489
2490	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
2491	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
2492	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
2493	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
2494	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
2495	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
2496	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
2497	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
2498	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
2499	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
2500	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
2501	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
2502	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
2503	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
2504	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
2505	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
2506	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
2507	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
2508	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
2509	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
2510	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
2511
2512	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
2513	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
2514	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
2515	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
2516	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
2517	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
2518	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
2519	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
2520	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
2521	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
2522	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
2523	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
2524	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
2525	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
2526
2527	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
2528	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
2529	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
2530	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
2531	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
2532	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
2533	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
2534	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
2535	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
2536	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
2537	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
2538	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
2539	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
2540	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
2541	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
2542	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
2543	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
2544	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
2545	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
2546	/** @} */
2547
2548	/** @name C instruction implementations for anything slightly complicated.
2549	* @{ */
2550
2551	/**
2552	* For typedef'ing or declaring a C instruction implementation function taking
2553	* no extra arguments.
2554	*
2555	* @param a_Name The name of the type.
2556	*/
2557	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
2558	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2559	/**
2560	* For defining a C instruction implementation function taking no extra
2561	* arguments.
2562	*
2563	* @param a_Name The name of the function
2564	*/
2565	# define IEM_CIMPL_DEF_0(a_Name) \
2566	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2567	/**
2568	* Prototype version of IEM_CIMPL_DEF_0.
2569	*/
2570	# define IEM_CIMPL_PROTO_0(a_Name) \
2571	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2572	/**
2573	* For calling a C instruction implementation function taking no extra
2574	* arguments.
2575	*
2576	* This special call macro adds default arguments to the call and allow us to
2577	* change these later.
2578	*
2579	* @param a_fn The name of the function.
2580	*/
2581	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
2582
2583	/**
2584	* For typedef'ing or declaring a C instruction implementation function taking
2585	* one extra argument.
2586	*
2587	* @param a_Name The name of the type.
2588	* @param a_Type0 The argument type.
2589	* @param a_Arg0 The argument name.
2590	*/
2591	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
2592	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2593	/**
2594	* For defining a C instruction implementation function taking one extra
2595	* argument.
2596	*
2597	* @param a_Name The name of the function
2598	* @param a_Type0 The argument type.
2599	* @param a_Arg0 The argument name.
2600	*/
2601	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
2602	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2603	/**
2604	* Prototype version of IEM_CIMPL_DEF_1.
2605	*/
2606	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
2607	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2608	/**
2609	* For calling a C instruction implementation function taking one extra
2610	* argument.
2611	*
2612	* This special call macro adds default arguments to the call and allow us to
2613	* change these later.
2614	*
2615	* @param a_fn The name of the function.
2616	* @param a0 The name of the 1st argument.
2617	*/
2618	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
2619
2620	/**
2621	* For typedef'ing or declaring a C instruction implementation function taking
2622	* two extra arguments.
2623	*
2624	* @param a_Name The name of the type.
2625	* @param a_Type0 The type of the 1st argument
2626	* @param a_Arg0 The name of the 1st argument.
2627	* @param a_Type1 The type of the 2nd argument.
2628	* @param a_Arg1 The name of the 2nd argument.
2629	*/
2630	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2631	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2632	/**
2633	* For defining a C instruction implementation function taking two extra
2634	* arguments.
2635	*
2636	* @param a_Name The name of the function.
2637	* @param a_Type0 The type of the 1st argument
2638	* @param a_Arg0 The name of the 1st argument.
2639	* @param a_Type1 The type of the 2nd argument.
2640	* @param a_Arg1 The name of the 2nd argument.
2641	*/
2642	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2643	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2644	/**
2645	* Prototype version of IEM_CIMPL_DEF_2.
2646	*/
2647	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2648	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2649	/**
2650	* For calling a C instruction implementation function taking two extra
2651	* arguments.
2652	*
2653	* This special call macro adds default arguments to the call and allow us to
2654	* change these later.
2655	*
2656	* @param a_fn The name of the function.
2657	* @param a0 The name of the 1st argument.
2658	* @param a1 The name of the 2nd argument.
2659	*/
2660	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
2661
2662	/**
2663	* For typedef'ing or declaring a C instruction implementation function taking
2664	* three extra arguments.
2665	*
2666	* @param a_Name The name of the type.
2667	* @param a_Type0 The type of the 1st argument
2668	* @param a_Arg0 The name of the 1st argument.
2669	* @param a_Type1 The type of the 2nd argument.
2670	* @param a_Arg1 The name of the 2nd argument.
2671	* @param a_Type2 The type of the 3rd argument.
2672	* @param a_Arg2 The name of the 3rd argument.
2673	*/
2674	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2675	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2676	/**
2677	* For defining a C instruction implementation function taking three extra
2678	* arguments.
2679	*
2680	* @param a_Name The name of the function.
2681	* @param a_Type0 The type of the 1st argument
2682	* @param a_Arg0 The name of the 1st argument.
2683	* @param a_Type1 The type of the 2nd argument.
2684	* @param a_Arg1 The name of the 2nd argument.
2685	* @param a_Type2 The type of the 3rd argument.
2686	* @param a_Arg2 The name of the 3rd argument.
2687	*/
2688	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2689	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2690	/**
2691	* Prototype version of IEM_CIMPL_DEF_3.
2692	*/
2693	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2694	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2695	/**
2696	* For calling a C instruction implementation function taking three extra
2697	* arguments.
2698	*
2699	* This special call macro adds default arguments to the call and allow us to
2700	* change these later.
2701	*
2702	* @param a_fn The name of the function.
2703	* @param a0 The name of the 1st argument.
2704	* @param a1 The name of the 2nd argument.
2705	* @param a2 The name of the 3rd argument.
2706	*/
2707	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
2708
2709
2710	/**
2711	* For typedef'ing or declaring a C instruction implementation function taking
2712	* four extra arguments.
2713	*
2714	* @param a_Name The name of the type.
2715	* @param a_Type0 The type of the 1st argument
2716	* @param a_Arg0 The name of the 1st argument.
2717	* @param a_Type1 The type of the 2nd argument.
2718	* @param a_Arg1 The name of the 2nd argument.
2719	* @param a_Type2 The type of the 3rd argument.
2720	* @param a_Arg2 The name of the 3rd argument.
2721	* @param a_Type3 The type of the 4th argument.
2722	* @param a_Arg3 The name of the 4th argument.
2723	*/
2724	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
2725	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
2726	/**
2727	* For defining a C instruction implementation function taking four extra
2728	* arguments.
2729	*
2730	* @param a_Name The name of the function.
2731	* @param a_Type0 The type of the 1st argument
2732	* @param a_Arg0 The name of the 1st argument.
2733	* @param a_Type1 The type of the 2nd argument.
2734	* @param a_Arg1 The name of the 2nd argument.
2735	* @param a_Type2 The type of the 3rd argument.
2736	* @param a_Arg2 The name of the 3rd argument.
2737	* @param a_Type3 The type of the 4th argument.
2738	* @param a_Arg3 The name of the 4th argument.
2739	*/
2740	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
2741	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2742	a_Type2 a_Arg2, a_Type3 a_Arg3))
2743	/**
2744	* Prototype version of IEM_CIMPL_DEF_4.
2745	*/
2746	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
2747	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2748	a_Type2 a_Arg2, a_Type3 a_Arg3))
2749	/**
2750	* For calling a C instruction implementation function taking four extra
2751	* arguments.
2752	*
2753	* This special call macro adds default arguments to the call and allow us to
2754	* change these later.
2755	*
2756	* @param a_fn The name of the function.
2757	* @param a0 The name of the 1st argument.
2758	* @param a1 The name of the 2nd argument.
2759	* @param a2 The name of the 3rd argument.
2760	* @param a3 The name of the 4th argument.
2761	*/
2762	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
2763
2764
2765	/**
2766	* For typedef'ing or declaring a C instruction implementation function taking
2767	* five extra arguments.
2768	*
2769	* @param a_Name The name of the type.
2770	* @param a_Type0 The type of the 1st argument
2771	* @param a_Arg0 The name of the 1st argument.
2772	* @param a_Type1 The type of the 2nd argument.
2773	* @param a_Arg1 The name of the 2nd argument.
2774	* @param a_Type2 The type of the 3rd argument.
2775	* @param a_Arg2 The name of the 3rd argument.
2776	* @param a_Type3 The type of the 4th argument.
2777	* @param a_Arg3 The name of the 4th argument.
2778	* @param a_Type4 The type of the 5th argument.
2779	* @param a_Arg4 The name of the 5th argument.
2780	*/
2781	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2782	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
2783	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
2784	a_Type3 a_Arg3, a_Type4 a_Arg4))
2785	/**
2786	* For defining a C instruction implementation function taking five extra
2787	* arguments.
2788	*
2789	* @param a_Name The name of the function.
2790	* @param a_Type0 The type of the 1st argument
2791	* @param a_Arg0 The name of the 1st argument.
2792	* @param a_Type1 The type of the 2nd argument.
2793	* @param a_Arg1 The name of the 2nd argument.
2794	* @param a_Type2 The type of the 3rd argument.
2795	* @param a_Arg2 The name of the 3rd argument.
2796	* @param a_Type3 The type of the 4th argument.
2797	* @param a_Arg3 The name of the 4th argument.
2798	* @param a_Type4 The type of the 5th argument.
2799	* @param a_Arg4 The name of the 5th argument.
2800	*/
2801	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2802	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2803	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
2804	/**
2805	* Prototype version of IEM_CIMPL_DEF_5.
2806	*/
2807	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2808	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2809	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
2810	/**
2811	* For calling a C instruction implementation function taking five extra
2812	* arguments.
2813	*
2814	* This special call macro adds default arguments to the call and allow us to
2815	* change these later.
2816	*
2817	* @param a_fn The name of the function.
2818	* @param a0 The name of the 1st argument.
2819	* @param a1 The name of the 2nd argument.
2820	* @param a2 The name of the 3rd argument.
2821	* @param a3 The name of the 4th argument.
2822	* @param a4 The name of the 5th argument.
2823	*/
2824	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
2825
2826	/** @} */
2827
2828
2829	/** @name Opcode Decoder Function Types.
2830	* @{ */
2831
2832	/** @typedef PFNIEMOP
2833	* Pointer to an opcode decoder function.
2834	*/
2835
2836	/** @def FNIEMOP_DEF
2837	* Define an opcode decoder function.
2838	*
2839	* We're using macors for this so that adding and removing parameters as well as
2840	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
2841	*
2842	* @param a_Name The function name.
2843	*/
2844
2845	/** @typedef PFNIEMOPRM
2846	* Pointer to an opcode decoder function with RM byte.
2847	*/
2848
2849	/** @def FNIEMOPRM_DEF
2850	* Define an opcode decoder function with RM byte.
2851	*
2852	* We're using macors for this so that adding and removing parameters as well as
2853	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
2854	*
2855	* @param a_Name The function name.
2856	*/
2857
2858	#if defined(__GNUC__) && defined(RT_ARCH_X86)
2859	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
2860	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2861	# define FNIEMOP_DEF(a_Name) \
2862	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
2863	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2864	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
2865	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2866	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
2867
2868	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
2869	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
2870	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2871	# define FNIEMOP_DEF(a_Name) \
2872	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
2873	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2874	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
2875	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2876	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
2877
2878	#elif defined(__GNUC__)
2879	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
2880	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2881	# define FNIEMOP_DEF(a_Name) \
2882	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
2883	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2884	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
2885	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2886	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
2887
2888	#else
2889	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
2890	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
2891	# define FNIEMOP_DEF(a_Name) \
2892	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
2893	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
2894	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
2895	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
2896	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
2897
2898	#endif
2899	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
2900
2901	/**
2902	* Call an opcode decoder function.
2903	*
2904	* We're using macors for this so that adding and removing parameters can be
2905	* done as we please. See FNIEMOP_DEF.
2906	*/
2907	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
2908
2909	/**
2910	* Call a common opcode decoder function taking one extra argument.
2911	*
2912	* We're using macors for this so that adding and removing parameters can be
2913	* done as we please. See FNIEMOP_DEF_1.
2914	*/
2915	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
2916
2917	/**
2918	* Call a common opcode decoder function taking one extra argument.
2919	*
2920	* We're using macors for this so that adding and removing parameters can be
2921	* done as we please. See FNIEMOP_DEF_1.
2922	*/
2923	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
2924	/** @} */
2925
2926
2927	/** @name Misc Helpers
2928	* @{ */
2929
2930	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
2931	* due to GCC lacking knowledge about the value range of a switch. */
2932	#define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
2933
2934	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
2935	#define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
2936
2937	/**
2938	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
2939	* occation.
2940	*/
2941	#ifdef LOG_ENABLED
2942	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
2943	do { \
2944	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
2945	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
2946	} while (0)
2947	#else
2948	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
2949	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
2950	#endif
2951
2952	/**
2953	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
2954	* occation using the supplied logger statement.
2955	*
2956	* @param a_LoggerArgs What to log on failure.
2957	*/
2958	#ifdef LOG_ENABLED
2959	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
2960	do { \
2961	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
2962	/LogFunc(a_LoggerArgs);/ \
2963	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
2964	} while (0)
2965	#else
2966	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
2967	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
2968	#endif
2969
2970	/**
2971	* Check if we're currently executing in real or virtual 8086 mode.
2972	*
2973	* @returns @c true if it is, @c false if not.
2974	* @param a_pVCpu The IEM state of the current CPU.
2975	*/
2976	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (CPUMIsGuestInRealOrV86ModeEx(IEM_GET_CTX(a_pVCpu)))
2977
2978	/**
2979	* Check if we're currently executing in virtual 8086 mode.
2980	*
2981	* @returns @c true if it is, @c false if not.
2982	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2983	*/
2984	#define IEM_IS_V86_MODE(a_pVCpu) (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(a_pVCpu)))
2985
2986	/**
2987	* Check if we're currently executing in long mode.
2988	*
2989	* @returns @c true if it is, @c false if not.
2990	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2991	*/
2992	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
2993
2994	/**
2995	* Check if we're currently executing in a 64-bit code segment.
2996	*
2997	* @returns @c true if it is, @c false if not.
2998	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
2999	*/
3000	#define IEM_IS_64BIT_CODE(a_pVCpu) (CPUMIsGuestIn64BitCodeEx(IEM_GET_CTX(a_pVCpu)))
3001
3002	/**
3003	* Check if we're currently executing in real mode.
3004	*
3005	* @returns @c true if it is, @c false if not.
3006	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3007	*/
3008	#define IEM_IS_REAL_MODE(a_pVCpu) (CPUMIsGuestInRealModeEx(IEM_GET_CTX(a_pVCpu)))
3009
3010	/**
3011	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
3012	* @returns PCCPUMFEATURES
3013	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3014	*/
3015	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
3016
3017	/**
3018	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
3019	* @returns PCCPUMFEATURES
3020	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3021	*/
3022	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
3023
3024	/**
3025	* Evaluates to true if we're presenting an Intel CPU to the guest.
3026	*/
3027	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
3028
3029	/**
3030	* Evaluates to true if we're presenting an AMD CPU to the guest.
3031	*/
3032	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
3033
3034	/**
3035	* Check if the address is canonical.
3036	*/
3037	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
3038
3039	/** Checks if the ModR/M byte is in register mode or not. */
3040	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
3041	/** Checks if the ModR/M byte is in memory mode or not. */
3042	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
3043
3044	/**
3045	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
3046	*
3047	* For use during decoding.
3048	*/
3049	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
3050	/**
3051	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
3052	*
3053	* For use during decoding.
3054	*/
3055	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
3056
3057	/**
3058	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
3059	*
3060	* For use during decoding.
3061	*/
3062	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
3063	/**
3064	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
3065	*
3066	* For use during decoding.
3067	*/
3068	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
3069
3070	/**
3071	* Gets the effective VEX.VVVV value.
3072	*
3073	* The 4th bit is ignored if not 64-bit code.
3074	* @returns effective V-register value.
3075	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3076	*/
3077	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
3078	((a_pVCpu)->iem.s.enmCpuMode == IEMMODE_64BIT ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
3079
3080
3081	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3082
3083	/**
3084	* Check if the guest has entered VMX root operation.
3085	*/
3086	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
3087
3088	/**
3089	* Check if the guest has entered VMX non-root operation.
3090	*/
3091	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(a_pVCpu)))
3092
3093	/**
3094	* Check if the nested-guest has the given Pin-based VM-execution control set.
3095	*/
3096	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) \
3097	(CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
3098
3099	/**
3100	* Check if the nested-guest has the given Processor-based VM-execution control set.
3101	*/
3102	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) \
3103	(CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
3104
3105	/**
3106	* Check if the nested-guest has the given Secondary Processor-based VM-execution
3107	* control set.
3108	*/
3109	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) \
3110	(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
3111
3112	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
3113	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
3114
3115	/** Whether a shadow VMCS is present for the given VCPU. */
3116	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3117
3118	/** Gets the VMXON region pointer. */
3119	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
3120
3121	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
3122	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
3123
3124	/** Whether a current VMCS is present for the given VCPU. */
3125	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3126
3127	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
3128	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
3129	do \
3130	{ \
3131	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
3132	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
3133	} while (0)
3134
3135	/** Clears any current VMCS for the given VCPU. */
3136	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
3137	do \
3138	{ \
3139	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
3140	} while (0)
3141
3142	/**
3143	* Invokes the VMX VM-exit handler for an instruction intercept.
3144	*/
3145	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
3146	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
3147
3148	/**
3149	* Invokes the VMX VM-exit handler for an instruction intercept where the
3150	* instruction provides additional VM-exit information.
3151	*/
3152	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
3153	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
3154
3155	/**
3156	* Invokes the VMX VM-exit handler for a task switch.
3157	*/
3158	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
3159	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
3160
3161	/**
3162	* Invokes the VMX VM-exit handler for MWAIT.
3163	*/
3164	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
3165	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
3166
3167	/**
3168	* Invokes the VMX VM-exit handler for EPT faults.
3169	*/
3170	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
3171	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
3172
3173	/**
3174	* Invokes the VMX VM-exit handler.
3175	*/
3176	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
3177	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
3178
3179	#else
3180	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
3181	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
3182	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
3183	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
3184	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
3185	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3186	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3187	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3188	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3189	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3190	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
3191
3192	#endif
3193
3194	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3195	/**
3196	* Check if an SVM control/instruction intercept is set.
3197	*/
3198	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
3199	(CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
3200
3201	/**
3202	* Check if an SVM read CRx intercept is set.
3203	*/
3204	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3205	(CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3206
3207	/**
3208	* Check if an SVM write CRx intercept is set.
3209	*/
3210	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3211	(CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3212
3213	/**
3214	* Check if an SVM read DRx intercept is set.
3215	*/
3216	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3217	(CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3218
3219	/**
3220	* Check if an SVM write DRx intercept is set.
3221	*/
3222	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3223	(CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3224
3225	/**
3226	* Check if an SVM exception intercept is set.
3227	*/
3228	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
3229	(CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
3230
3231	/**
3232	* Invokes the SVM \#VMEXIT handler for the nested-guest.
3233	*/
3234	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3235	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
3236
3237	/**
3238	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
3239	* corresponding decode assist information.
3240	*/
3241	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
3242	do \
3243	{ \
3244	uint64_t uExitInfo1; \
3245	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
3246	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
3247	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
3248	else \
3249	uExitInfo1 = 0; \
3250	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
3251	} while (0)
3252
3253	/** Check and handles SVM nested-guest instruction intercept and updates
3254	* NRIP if needed.
3255	*/
3256	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3257	do \
3258	{ \
3259	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
3260	{ \
3261	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3262	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
3263	} \
3264	} while (0)
3265
3266	/** Checks and handles SVM nested-guest CR0 read intercept. */
3267	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) \
3268	do \
3269	{ \
3270	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
3271	{ /* probably likely */ } \
3272	else \
3273	{ \
3274	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3275	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
3276	} \
3277	} while (0)
3278
3279	/**
3280	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
3281	*/
3282	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) \
3283	do { \
3284	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
3285	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), IEM_GET_INSTR_LEN(a_pVCpu)); \
3286	} while (0)
3287
3288	#else
3289	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
3290	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3291	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3292	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3293	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3294	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
3295	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
3296	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
3297	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3298	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3299	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) do { } while (0)
3300
3301	#endif
3302
3303	/** @} */
3304
3305
3306
3307	/**
3308	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
3309	*/
3310	typedef union IEMSELDESC
3311	{
3312	/** The legacy view. */
3313	X86DESC Legacy;
3314	/** The long mode view. */
3315	X86DESC64 Long;
3316	} IEMSELDESC;
3317	/** Pointer to a selector descriptor table entry. */
3318	typedef IEMSELDESC *PIEMSELDESC;
3319
3320	/** @name Raising Exceptions.
3321	* @{ */
3322	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
3323	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
3324
3325	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
3326	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3327	#ifdef IEM_WITH_SETJMP
3328	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
3329	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3330	#endif
3331	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
3332	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3333	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
3334	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
3335	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
3336	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3337	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
3338	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3339	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3340	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
3341	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3342	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3343	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3344	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3345	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3346	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3347	#ifdef IEM_WITH_SETJMP
3348	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3349	#endif
3350	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3351	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
3352	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3353	#ifdef IEM_WITH_SETJMP
3354	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3355	#endif
3356	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3357	#ifdef IEM_WITH_SETJMP
3358	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3359	#endif
3360	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3361	#ifdef IEM_WITH_SETJMP
3362	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3363	#endif
3364	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
3365	#ifdef IEM_WITH_SETJMP
3366	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
3367	#endif
3368	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu);
3369	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu);
3370	#ifdef IEM_WITH_SETJMP
3371	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3372	#endif
3373	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3374
3375	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
3376	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
3377	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
3378
3379	/**
3380	* Macro for calling iemCImplRaiseDivideError().
3381	*
3382	* This enables us to add/remove arguments and force different levels of
3383	* inlining as we wish.
3384	*
3385	* @return Strict VBox status code.
3386	*/
3387	#define IEMOP_RAISE_DIVIDE_ERROR() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseDivideError)
3388
3389	/**
3390	* Macro for calling iemCImplRaiseInvalidLockPrefix().
3391	*
3392	* This enables us to add/remove arguments and force different levels of
3393	* inlining as we wish.
3394	*
3395	* @return Strict VBox status code.
3396	*/
3397	#define IEMOP_RAISE_INVALID_LOCK_PREFIX() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidLockPrefix)
3398
3399	/**
3400	* Macro for calling iemCImplRaiseInvalidOpcode().
3401	*
3402	* This enables us to add/remove arguments and force different levels of
3403	* inlining as we wish.
3404	*
3405	* @return Strict VBox status code.
3406	*/
3407	#define IEMOP_RAISE_INVALID_OPCODE() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidOpcode)
3408	/** @} */
3409
3410	/** @name Register Access.
3411	* @{ */
3412	VBOXSTRICTRC iemRegRipRelativeJumpS8(PVMCPUCC pVCpu, int8_t offNextInstr) RT_NOEXCEPT;
3413	VBOXSTRICTRC iemRegRipRelativeJumpS16(PVMCPUCC pVCpu, int16_t offNextInstr) RT_NOEXCEPT;
3414	VBOXSTRICTRC iemRegRipRelativeJumpS32(PVMCPUCC pVCpu, int32_t offNextInstr) RT_NOEXCEPT;
3415	VBOXSTRICTRC iemRegRipJump(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
3416	/** @} */
3417
3418	/** @name FPU access and helpers.
3419	* @{ */
3420	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult) RT_NOEXCEPT;
3421	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3422	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult) RT_NOEXCEPT;
3423	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3424	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3425	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3426	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3427	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3428	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3429	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3430	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3431	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3432	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3433	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3434	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3435	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3436	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3437	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3438	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3439	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu) RT_NOEXCEPT;
3440	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3441	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu) RT_NOEXCEPT;
3442	void iemFpuStackPushOverflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3443	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3444	/** @} */
3445
3446	/** @name SSE+AVX SIMD access and helpers.
3447	* @{ */
3448	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
3449	/** @} */
3450
3451	/** @name Memory access.
3452	* @{ */
3453
3454	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
3455	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
3456	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
3457	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
3458	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
3459	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
3460	* Users include FXSAVE & FXRSTOR. */
3461	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
3462
3463	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
3464	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
3465	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3466	#ifndef IN_RING3
3467	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3468	#endif
3469	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
3470	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
3471	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3472	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
3473
3474	#ifdef IEM_WITH_CODE_TLB
3475	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) RT_NOEXCEPT;
3476	#else
3477	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
3478	#endif
3479	#ifdef IEM_WITH_SETJMP
3480	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3481	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3482	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3483	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3484	#else
3485	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
3486	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3487	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3488	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3489	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3490	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3491	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3492	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3493	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3494	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3495	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3496	#endif
3497
3498	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3499	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3500	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3501	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3502	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3503	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3504	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3505	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3506	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3507	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3508	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3509	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3510	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
3511	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
3512	#ifdef IEM_WITH_SETJMP
3513	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3514	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3515	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3516	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3517	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3518	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3519	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3520	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3521	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3522	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3523	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3524	#endif
3525
3526	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3527	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3528	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3529	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3530	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
3531
3532	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
3533	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
3534	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
3535	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
3536	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3537	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3538	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3539	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3540	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3541	#ifdef IEM_WITH_SETJMP
3542	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
3543	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
3544	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
3545	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
3546	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3547	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3548	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3549	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3550	#endif
3551
3552	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
3553	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
3554	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
3555	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
3556	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3557	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
3558	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3559	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3560	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3561	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3562	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
3563	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
3564	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t cbMem, void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
3565	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
3566	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
3567	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
3568	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
3569	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3570	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3571	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3572	/** @} */
3573
3574	/** @name IEMAllCImpl.cpp
3575	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
3576	* @{ */
3577	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
3578	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
3579	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
3580	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
3581	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
3582	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
3583	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
3584	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
3585	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
3586	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
3587	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
3588	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
3589	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3590	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3591	IEM_CIMPL_PROTO_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3592	IEM_CIMPL_PROTO_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3593	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
3594	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
3595	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
3596	IEM_CIMPL_PROTO_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop);
3597	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
3598	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
3599	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
3600	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
3601	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
3602	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
3603	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
3604	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
3605	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
3606	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
3607	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
3608	IEM_CIMPL_PROTO_0(iemCImpl_sysret);
3609	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
3610	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
3611	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
3612	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
3613	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
3614	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
3615	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
3616	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
3617	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
3618	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
3619	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3620	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
3621	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3622	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
3623	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3624	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3625	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
3626	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3627	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3628	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
3629	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3630	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3631	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
3632	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
3633	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
3634	IEM_CIMPL_PROTO_0(iemCImpl_clts);
3635	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
3636	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
3637	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
3638	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
3639	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
3640	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
3641	IEM_CIMPL_PROTO_0(iemCImpl_invd);
3642	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
3643	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
3644	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
3645	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
3646	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
3647	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
3648	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
3649	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
3650	IEM_CIMPL_PROTO_1(iemCImpl_in_eAX_DX, uint8_t, cbReg);
3651	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
3652	IEM_CIMPL_PROTO_1(iemCImpl_out_DX_eAX, uint8_t, cbReg);
3653	IEM_CIMPL_PROTO_0(iemCImpl_cli);
3654	IEM_CIMPL_PROTO_0(iemCImpl_sti);
3655	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
3656	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
3657	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
3658	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
3659	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
3660	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
3661	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
3662	IEM_CIMPL_PROTO_0(iemCImpl_daa);
3663	IEM_CIMPL_PROTO_0(iemCImpl_das);
3664	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
3665	IEM_CIMPL_PROTO_0(iemCImpl_aas);
3666	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
3667	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
3668	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
3669	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
3670	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
3671	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
3672	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3673	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
3674	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3675	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3676	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3677	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3678	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3679	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3680	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3681	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3682	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3683	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
3684	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
3685	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
3686	IEM_CIMPL_PROTO_1(iemCImpl_fxch_underflow, uint8_t, iStReg);
3687	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop);
3688	/** @} */
3689
3690	/** @name IEMAllCImplStrInstr.cpp.h
3691	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
3692	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
3693	* @{ */
3694	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
3695	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
3696	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
3697	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
3698	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
3699	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
3700	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
3701	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
3702	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
3703	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3704	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3705
3706	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
3707	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
3708	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
3709	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
3710	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
3711	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
3712	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
3713	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
3714	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
3715	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3716	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3717
3718	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
3719	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
3720	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
3721	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
3722	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
3723	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
3724	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
3725	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
3726	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
3727	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3728	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3729
3730
3731	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
3732	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
3733	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
3734	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
3735	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
3736	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
3737	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
3738	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
3739	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
3740	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3741	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3742
3743	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
3744	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
3745	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
3746	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
3747	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
3748	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
3749	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
3750	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
3751	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
3752	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3753	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3754
3755	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
3756	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
3757	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
3758	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
3759	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
3760	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
3761	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
3762	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
3763	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
3764	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3765	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3766
3767	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
3768	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
3769	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
3770	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
3771	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
3772	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
3773	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
3774	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
3775	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
3776	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3777	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3778
3779
3780	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
3781	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
3782	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
3783	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
3784	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
3785	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
3786	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
3787	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
3788	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
3789	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3790	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3791
3792	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
3793	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
3794	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
3795	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
3796	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
3797	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
3798	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
3799	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
3800	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
3801	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3802	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3803
3804	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
3805	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
3806	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
3807	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
3808	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
3809	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
3810	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
3811	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
3812	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
3813	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3814	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3815
3816	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
3817	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
3818	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
3819	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
3820	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
3821	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
3822	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
3823	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
3824	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
3825	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3826	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3827	/** @} */
3828
3829	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3830	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
3831	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
3832	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
3833	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
3834	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
3835	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
3836	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
3837	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
3838	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
3839	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3840	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
3841	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3842	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
3843	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3844	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3845	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3846	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3847	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3848	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3849	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
3850	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
3851	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
3852	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
3853	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
3854	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
3855	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
3856	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
3857	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
3858	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
3859	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
3860	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
3861	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
3862	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
3863	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
3864	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3865	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3866	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
3867	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
3868	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
3869	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
3870	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField);
3871	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
3872	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
3873	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
3874	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
3875	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
3876	#endif
3877
3878	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3879	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
3880	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3881	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
3882	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
3883	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite) RT_NOEXCEPT;
3884	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
3885	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
3886	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
3887	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
3888	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
3889	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
3890	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
3891	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
3892	#endif
3893
3894	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
3895	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
3896	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
3897
3898
3899	extern const PFNIEMOP g_apfnOneByteMap[256];
3900
3901	/** @} */
3902
3903	RT_C_DECLS_END
3904
3905	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
3906

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 96438

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