IEMInternal.h@ 96673

Last change on this file since 96673 was 96652, checked in by vboxsync, 3 years ago
VMM/IEM: Implement [v]pclmulqdq instruction, bugref:9898
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1	/* $Id: IEMInternal.h 96652 2022-09-08 08:49:40Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41
42
43	RT_C_DECLS_BEGIN
44
45
46	/** @defgroup grp_iem_int Internals
47	* @ingroup grp_iem
48	* @internal
49	* @{
50	*/
51
52	/** For expanding symbol in slickedit and other products tagging and
53	* crossreferencing IEM symbols. */
54	#ifndef IEM_STATIC
55	# define IEM_STATIC static
56	#endif
57
58	/** @def IEM_WITH_SETJMP
59	* Enables alternative status code handling using setjmps.
60	*
61	* This adds a bit of expense via the setjmp() call since it saves all the
62	* non-volatile registers. However, it eliminates return code checks and allows
63	* for more optimal return value passing (return regs instead of stack buffer).
64	*/
65	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
66	# define IEM_WITH_SETJMP
67	#endif
68
69	#define IEM_IMPLEMENTS_TASKSWITCH
70
71	/** @def IEM_WITH_3DNOW
72	* Includes the 3DNow decoding. */
73	#define IEM_WITH_3DNOW
74
75	/** @def IEM_WITH_THREE_0F_38
76	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
77	#define IEM_WITH_THREE_0F_38
78
79	/** @def IEM_WITH_THREE_0F_3A
80	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
81	#define IEM_WITH_THREE_0F_3A
82
83	/** @def IEM_WITH_VEX
84	* Includes the VEX decoding. */
85	#define IEM_WITH_VEX
86
87	/** @def IEM_CFG_TARGET_CPU
88	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
89	*
90	* By default we allow this to be configured by the user via the
91	* CPUM/GuestCpuName config string, but this comes at a slight cost during
92	* decoding. So, for applications of this code where there is no need to
93	* be dynamic wrt target CPU, just modify this define.
94	*/
95	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
96	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
97	#endif
98
99	//#define IEM_WITH_CODE_TLB // - work in progress
100	//#define IEM_WITH_DATA_TLB // - work in progress
101
102
103	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
104	* Use unaligned accesses instead of elaborate byte assembly. */
105	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
106	# define IEM_USE_UNALIGNED_DATA_ACCESS
107	#endif
108
109	//#define IEM_LOG_MEMORY_WRITES
110
111	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
112	/** Instruction statistics. */
113	typedef struct IEMINSTRSTATS
114	{
115	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
116	# include "IEMInstructionStatisticsTmpl.h"
117	# undef IEM_DO_INSTR_STAT
118	} IEMINSTRSTATS;
119	#else
120	struct IEMINSTRSTATS;
121	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
122	#endif
123	/** Pointer to IEM instruction statistics. */
124	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
125
126
127	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
128	* @{ */
129	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
130	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
131	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
132	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
133	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
134	/** Selects the right variant from a_aArray.
135	* pVCpu is implicit in the caller context. */
136	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
137	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
138	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
139	* be used because the host CPU does not support the operation. */
140	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
141	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
142	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
143	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
144	* into the two.
145	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
146	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
147	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
148	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
149	#else
150	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
151	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
152	#endif
153	/** @} */
154
155	/**
156	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
157	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
158	*
159	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
160	* indicator.
161	*
162	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
163	*/
164	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
165	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
166	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
167	#else
168	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
169	#endif
170
171
172	/**
173	* Extended operand mode that includes a representation of 8-bit.
174	*
175	* This is used for packing down modes when invoking some C instruction
176	* implementations.
177	*/
178	typedef enum IEMMODEX
179	{
180	IEMMODEX_16BIT = IEMMODE_16BIT,
181	IEMMODEX_32BIT = IEMMODE_32BIT,
182	IEMMODEX_64BIT = IEMMODE_64BIT,
183	IEMMODEX_8BIT
184	} IEMMODEX;
185	AssertCompileSize(IEMMODEX, 4);
186
187
188	/**
189	* Branch types.
190	*/
191	typedef enum IEMBRANCH
192	{
193	IEMBRANCH_JUMP = 1,
194	IEMBRANCH_CALL,
195	IEMBRANCH_TRAP,
196	IEMBRANCH_SOFTWARE_INT,
197	IEMBRANCH_HARDWARE_INT
198	} IEMBRANCH;
199	AssertCompileSize(IEMBRANCH, 4);
200
201
202	/**
203	* INT instruction types.
204	*/
205	typedef enum IEMINT
206	{
207	/** INT n instruction (opcode 0xcd imm). */
208	IEMINT_INTN = 0,
209	/** Single byte INT3 instruction (opcode 0xcc). */
210	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
211	/** Single byte INTO instruction (opcode 0xce). */
212	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
213	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
214	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
215	} IEMINT;
216	AssertCompileSize(IEMINT, 4);
217
218
219	/**
220	* A FPU result.
221	*/
222	typedef struct IEMFPURESULT
223	{
224	/** The output value. */
225	RTFLOAT80U r80Result;
226	/** The output status. */
227	uint16_t FSW;
228	} IEMFPURESULT;
229	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
230	/** Pointer to a FPU result. */
231	typedef IEMFPURESULT *PIEMFPURESULT;
232	/** Pointer to a const FPU result. */
233	typedef IEMFPURESULT const *PCIEMFPURESULT;
234
235
236	/**
237	* A FPU result consisting of two output values and FSW.
238	*/
239	typedef struct IEMFPURESULTTWO
240	{
241	/** The first output value. */
242	RTFLOAT80U r80Result1;
243	/** The output status. */
244	uint16_t FSW;
245	/** The second output value. */
246	RTFLOAT80U r80Result2;
247	} IEMFPURESULTTWO;
248	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
249	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
250	/** Pointer to a FPU result consisting of two output values and FSW. */
251	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
252	/** Pointer to a const FPU result consisting of two output values and FSW. */
253	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
254
255
256	/**
257	* IEM TLB entry.
258	*
259	* Lookup assembly:
260	* @code{.asm}
261	; Calculate tag.
262	mov rax, [VA]
263	shl rax, 16
264	shr rax, 16 + X86_PAGE_SHIFT
265	or rax, [uTlbRevision]
266
267	; Do indexing.
268	movzx ecx, al
269	lea rcx, [pTlbEntries + rcx]
270
271	; Check tag.
272	cmp [rcx + IEMTLBENTRY.uTag], rax
273	jne .TlbMiss
274
275	; Check access.
276	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
277	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
278	cmp rax, [uTlbPhysRev]
279	jne .TlbMiss
280
281	; Calc address and we're done.
282	mov eax, X86_PAGE_OFFSET_MASK
283	and eax, [VA]
284	or rax, [rcx + IEMTLBENTRY.pMappingR3]
285	%ifdef VBOX_WITH_STATISTICS
286	inc qword [cTlbHits]
287	%endif
288	jmp .Done
289
290	.TlbMiss:
291	mov r8d, ACCESS_FLAGS
292	mov rdx, [VA]
293	mov rcx, [pVCpu]
294	call iemTlbTypeMiss
295	.Done:
296
297	@endcode
298	*
299	*/
300	typedef struct IEMTLBENTRY
301	{
302	/** The TLB entry tag.
303	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
304	* is ASSUMING a virtual address width of 48 bits.
305	*
306	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
307	*
308	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
309	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
310	* revision wraps around though, the tags needs to be zeroed.
311	*
312	* @note Try use SHRD instruction? After seeing
313	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
314	*
315	* @todo This will need to be reorganized for 57-bit wide virtual address and
316	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
317	* have to move the TLB entry versioning entirely to the
318	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
319	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
320	* consumed by PCID and ASID (12 + 6 = 18).
321	*/
322	uint64_t uTag;
323	/** Access flags and physical TLB revision.
324	*
325	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
326	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
327	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
328	* - Bit 3 - pgm phys/virt - not directly writable.
329	* - Bit 4 - pgm phys page - not directly readable.
330	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
331	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
332	* - Bit 7 - tlb entry - pMappingR3 member not valid.
333	* - Bits 63 thru 8 are used for the physical TLB revision number.
334	*
335	* We're using complemented bit meanings here because it makes it easy to check
336	* whether special action is required. For instance a user mode write access
337	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
338	* non-zero result would mean special handling needed because either it wasn't
339	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
340	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
341	* need to check any PTE flag.
342	*/
343	uint64_t fFlagsAndPhysRev;
344	/** The guest physical page address. */
345	uint64_t GCPhys;
346	/** Pointer to the ring-3 mapping. */
347	R3PTRTYPE(uint8_t *) pbMappingR3;
348	#if HC_ARCH_BITS == 32
349	uint32_t u32Padding1;
350	#endif
351	} IEMTLBENTRY;
352	AssertCompileSize(IEMTLBENTRY, 32);
353	/** Pointer to an IEM TLB entry. */
354	typedef IEMTLBENTRY *PIEMTLBENTRY;
355
356	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
357	* @{ */
358	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
359	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
360	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
361	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
362	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
363	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
364	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
365	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
366	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
367	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
368	/** @} */
369
370
371	/**
372	* An IEM TLB.
373	*
374	* We've got two of these, one for data and one for instructions.
375	*/
376	typedef struct IEMTLB
377	{
378	/** The TLB entries.
379	* We've choosen 256 because that way we can obtain the result directly from a
380	* 8-bit register without an additional AND instruction. */
381	IEMTLBENTRY aEntries[256];
382	/** The TLB revision.
383	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
384	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
385	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
386	* (The revision zero indicates an invalid TLB entry.)
387	*
388	* The initial value is choosen to cause an early wraparound. */
389	uint64_t uTlbRevision;
390	/** The TLB physical address revision - shadow of PGM variable.
391	*
392	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
393	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
394	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
395	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
396	*
397	* The initial value is choosen to cause an early wraparound. */
398	uint64_t volatile uTlbPhysRev;
399
400	/* Statistics: */
401
402	/** TLB hits (VBOX_WITH_STATISTICS only). */
403	uint64_t cTlbHits;
404	/** TLB misses. */
405	uint32_t cTlbMisses;
406	/** Slow read path. */
407	uint32_t cTlbSlowReadPath;
408	#if 0
409	/** TLB misses because of tag mismatch. */
410	uint32_t cTlbMissesTag;
411	/** TLB misses because of virtual access violation. */
412	uint32_t cTlbMissesVirtAccess;
413	/** TLB misses because of dirty bit. */
414	uint32_t cTlbMissesDirty;
415	/** TLB misses because of MMIO */
416	uint32_t cTlbMissesMmio;
417	/** TLB misses because of write access handlers. */
418	uint32_t cTlbMissesWriteHandler;
419	/** TLB misses because no r3(/r0) mapping. */
420	uint32_t cTlbMissesMapping;
421	#endif
422	/** Alignment padding. */
423	uint32_t au32Padding[3+5];
424	} IEMTLB;
425	AssertCompileSizeAlignment(IEMTLB, 64);
426	/** IEMTLB::uTlbRevision increment. */
427	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
428	/** IEMTLB::uTlbRevision mask. */
429	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
430	/** IEMTLB::uTlbPhysRev increment.
431	* @sa IEMTLBE_F_PHYS_REV */
432	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
433	/**
434	* Calculates the TLB tag for a virtual address.
435	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
436	* @param a_pTlb The TLB.
437	* @param a_GCPtr The virtual address.
438	*/
439	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
440	/**
441	* Calculates the TLB tag for a virtual address but without TLB revision.
442	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
443	* @param a_GCPtr The virtual address.
444	*/
445	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
446	/**
447	* Converts a TLB tag value into a TLB index.
448	* @returns Index into IEMTLB::aEntries.
449	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
450	*/
451	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
452	/**
453	* Converts a TLB tag value into a TLB index.
454	* @returns Index into IEMTLB::aEntries.
455	* @param a_pTlb The TLB.
456	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
457	*/
458	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
459
460
461	/**
462	* The per-CPU IEM state.
463	*/
464	typedef struct IEMCPU
465	{
466	/** Info status code that needs to be propagated to the IEM caller.
467	* This cannot be passed internally, as it would complicate all success
468	* checks within the interpreter making the code larger and almost impossible
469	* to get right. Instead, we'll store status codes to pass on here. Each
470	* source of these codes will perform appropriate sanity checks. */
471	int32_t rcPassUp; /* 0x00 */
472
473	/** The current CPU execution mode (CS). */
474	IEMMODE enmCpuMode; /* 0x04 */
475	/** The CPL. */
476	uint8_t uCpl; /* 0x05 */
477
478	/** Whether to bypass access handlers or not. */
479	bool fBypassHandlers; /* 0x06 */
480	/** Whether to disregard the lock prefix (implied or not). */
481	bool fDisregardLock; /* 0x07 */
482
483	/** @name Decoder state.
484	* @{ */
485	#ifdef IEM_WITH_CODE_TLB
486	/** The offset of the next instruction byte. */
487	uint32_t offInstrNextByte; /* 0x08 */
488	/** The number of bytes available at pbInstrBuf for the current instruction.
489	* This takes the max opcode length into account so that doesn't need to be
490	* checked separately. */
491	uint32_t cbInstrBuf; /* 0x0c */
492	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
493	* This can be NULL if the page isn't mappable for some reason, in which
494	* case we'll do fallback stuff.
495	*
496	* If we're executing an instruction from a user specified buffer,
497	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
498	* aligned pointer but pointer to the user data.
499	*
500	* For instructions crossing pages, this will start on the first page and be
501	* advanced to the next page by the time we've decoded the instruction. This
502	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
503	*/
504	uint8_t const pbInstrBuf; / 0x10 */
505	# if ARCH_BITS == 32
506	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
507	# endif
508	/** The program counter corresponding to pbInstrBuf.
509	* This is set to a non-canonical address when we need to invalidate it. */
510	uint64_t uInstrBufPc; /* 0x18 */
511	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
512	* This takes the CS segment limit into account. */
513	uint16_t cbInstrBufTotal; /* 0x20 */
514	/** Offset into pbInstrBuf of the first byte of the current instruction.
515	* Can be negative to efficiently handle cross page instructions. */
516	int16_t offCurInstrStart; /* 0x22 */
517
518	/** The prefix mask (IEM_OP_PRF_XXX). */
519	uint32_t fPrefixes; /* 0x24 */
520	/** The extra REX ModR/M register field bit (REX.R << 3). */
521	uint8_t uRexReg; /* 0x28 */
522	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
523	* (REX.B << 3). */
524	uint8_t uRexB; /* 0x29 */
525	/** The extra REX SIB index field bit (REX.X << 3). */
526	uint8_t uRexIndex; /* 0x2a */
527
528	/** The effective segment register (X86_SREG_XXX). */
529	uint8_t iEffSeg; /* 0x2b */
530
531	/** The offset of the ModR/M byte relative to the start of the instruction. */
532	uint8_t offModRm; /* 0x2c */
533	#else
534	/** The size of what has currently been fetched into abOpcode. */
535	uint8_t cbOpcode; /* 0x08 */
536	/** The current offset into abOpcode. */
537	uint8_t offOpcode; /* 0x09 */
538	/** The offset of the ModR/M byte relative to the start of the instruction. */
539	uint8_t offModRm; /* 0x0a */
540
541	/** The effective segment register (X86_SREG_XXX). */
542	uint8_t iEffSeg; /* 0x0b */
543
544	/** The prefix mask (IEM_OP_PRF_XXX). */
545	uint32_t fPrefixes; /* 0x0c */
546	/** The extra REX ModR/M register field bit (REX.R << 3). */
547	uint8_t uRexReg; /* 0x10 */
548	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
549	* (REX.B << 3). */
550	uint8_t uRexB; /* 0x11 */
551	/** The extra REX SIB index field bit (REX.X << 3). */
552	uint8_t uRexIndex; /* 0x12 */
553
554	#endif
555
556	/** The effective operand mode. */
557	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
558	/** The default addressing mode. */
559	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
560	/** The effective addressing mode. */
561	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
562	/** The default operand mode. */
563	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
564
565	/** Prefix index (VEX.pp) for two byte and three byte tables. */
566	uint8_t idxPrefix; /* 0x31, 0x17 */
567	/** 3rd VEX/EVEX/XOP register.
568	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
569	uint8_t uVex3rdReg; /* 0x32, 0x18 */
570	/** The VEX/EVEX/XOP length field. */
571	uint8_t uVexLength; /* 0x33, 0x19 */
572	/** Additional EVEX stuff. */
573	uint8_t fEvexStuff; /* 0x34, 0x1a */
574
575	/** Explicit alignment padding. */
576	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
577	/** The FPU opcode (FOP). */
578	uint16_t uFpuOpcode; /* 0x36, 0x1c */
579	#ifndef IEM_WITH_CODE_TLB
580	/** Explicit alignment padding. */
581	uint8_t abAlignment2b[2]; /* 0x1e */
582	#endif
583
584	/** The opcode bytes. */
585	uint8_t abOpcode[15]; /* 0x48, 0x20 */
586	/** Explicit alignment padding. */
587	#ifdef IEM_WITH_CODE_TLB
588	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
589	#else
590	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
591	#endif
592	/** @} */
593
594
595	/** The flags of the current exception / interrupt. */
596	uint32_t fCurXcpt; /* 0x48, 0x48 */
597	/** The current exception / interrupt. */
598	uint8_t uCurXcpt;
599	/** Exception / interrupt recursion depth. */
600	int8_t cXcptRecursions;
601
602	/** The number of active guest memory mappings. */
603	uint8_t cActiveMappings;
604	/** The next unused mapping index. */
605	uint8_t iNextMapping;
606	/** Records for tracking guest memory mappings. */
607	struct
608	{
609	/** The address of the mapped bytes. */
610	void *pv;
611	/** The access flags (IEM_ACCESS_XXX).
612	* IEM_ACCESS_INVALID if the entry is unused. */
613	uint32_t fAccess;
614	#if HC_ARCH_BITS == 64
615	uint32_t u32Alignment4; /*< Alignment padding. /
616	#endif
617	} aMemMappings[3];
618
619	/** Locking records for the mapped memory. */
620	union
621	{
622	PGMPAGEMAPLOCK Lock;
623	uint64_t au64Padding[2];
624	} aMemMappingLocks[3];
625
626	/** Bounce buffer info.
627	* This runs in parallel to aMemMappings. */
628	struct
629	{
630	/** The physical address of the first byte. */
631	RTGCPHYS GCPhysFirst;
632	/** The physical address of the second page. */
633	RTGCPHYS GCPhysSecond;
634	/** The number of bytes in the first page. */
635	uint16_t cbFirst;
636	/** The number of bytes in the second page. */
637	uint16_t cbSecond;
638	/** Whether it's unassigned memory. */
639	bool fUnassigned;
640	/** Explicit alignment padding. */
641	bool afAlignment5[3];
642	} aMemBbMappings[3];
643
644	/* Ensure that aBounceBuffers are aligned at a 32 byte boundrary. */
645	uint64_t abAlignment7[1];
646
647	/** Bounce buffer storage.
648	* This runs in parallel to aMemMappings and aMemBbMappings. */
649	struct
650	{
651	uint8_t ab[512];
652	} aBounceBuffers[3];
653
654
655	/** Pointer set jump buffer - ring-3 context. */
656	R3PTRTYPE(jmp_buf *) pJmpBufR3;
657	/** Pointer set jump buffer - ring-0 context. */
658	R0PTRTYPE(jmp_buf *) pJmpBufR0;
659
660	/** @todo Should move this near @a fCurXcpt later. */
661	/** The CR2 for the current exception / interrupt. */
662	uint64_t uCurXcptCr2;
663	/** The error code for the current exception / interrupt. */
664	uint32_t uCurXcptErr;
665
666	/** @name Statistics
667	* @{ */
668	/** The number of instructions we've executed. */
669	uint32_t cInstructions;
670	/** The number of potential exits. */
671	uint32_t cPotentialExits;
672	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
673	* This may contain uncommitted writes. */
674	uint32_t cbWritten;
675	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
676	uint32_t cRetInstrNotImplemented;
677	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
678	uint32_t cRetAspectNotImplemented;
679	/** Counts informational statuses returned (other than VINF_SUCCESS). */
680	uint32_t cRetInfStatuses;
681	/** Counts other error statuses returned. */
682	uint32_t cRetErrStatuses;
683	/** Number of times rcPassUp has been used. */
684	uint32_t cRetPassUpStatus;
685	/** Number of times RZ left with instruction commit pending for ring-3. */
686	uint32_t cPendingCommit;
687	/** Number of long jumps. */
688	uint32_t cLongJumps;
689	/** @} */
690
691	/** @name Target CPU information.
692	* @{ */
693	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
694	/** The target CPU. */
695	uint8_t uTargetCpu;
696	#else
697	uint8_t bTargetCpuPadding;
698	#endif
699	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
700	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
701	* native host support and the 2nd for when there is.
702	*
703	* The two values are typically indexed by a g_CpumHostFeatures bit.
704	*
705	* This is for instance used for the BSF & BSR instructions where AMD and
706	* Intel CPUs produce different EFLAGS. */
707	uint8_t aidxTargetCpuEflFlavour[2];
708
709	/** The CPU vendor. */
710	CPUMCPUVENDOR enmCpuVendor;
711	/** @} */
712
713	/** @name Host CPU information.
714	* @{ */
715	/** The CPU vendor. */
716	CPUMCPUVENDOR enmHostCpuVendor;
717	/** @} */
718
719	/** Counts RDMSR \#GP(0) LogRel(). */
720	uint8_t cLogRelRdMsr;
721	/** Counts WRMSR \#GP(0) LogRel(). */
722	uint8_t cLogRelWrMsr;
723	/** Alignment padding. */
724	uint8_t abAlignment8[42];
725
726	/** Data TLB.
727	* @remarks Must be 64-byte aligned. */
728	IEMTLB DataTlb;
729	/** Instruction TLB.
730	* @remarks Must be 64-byte aligned. */
731	IEMTLB CodeTlb;
732
733	/** Exception statistics. */
734	STAMCOUNTER aStatXcpts[32];
735	/** Interrupt statistics. */
736	uint32_t aStatInts[256];
737
738	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
739	/** Instruction statistics for ring-0/raw-mode. */
740	IEMINSTRSTATS StatsRZ;
741	/** Instruction statistics for ring-3. */
742	IEMINSTRSTATS StatsR3;
743	#endif
744	} IEMCPU;
745	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
746	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 8);
747	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 16);
748	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 32);
749	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
750	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
751	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
752
753	/** Pointer to the per-CPU IEM state. */
754	typedef IEMCPU *PIEMCPU;
755	/** Pointer to the const per-CPU IEM state. */
756	typedef IEMCPU const *PCIEMCPU;
757
758
759	/** @def IEM_GET_CTX
760	* Gets the guest CPU context for the calling EMT.
761	* @returns PCPUMCTX
762	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
763	*/
764	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
765
766	/** @def IEM_CTX_ASSERT
767	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
768	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
769	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
770	*/
771	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
772	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
773	(a_fExtrnMbz)))
774
775	/** @def IEM_CTX_IMPORT_RET
776	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
777	*
778	* Will call the keep to import the bits as needed.
779	*
780	* Returns on import failure.
781	*
782	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
783	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
784	*/
785	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
786	do { \
787	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
788	{ /* likely */ } \
789	else \
790	{ \
791	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
792	AssertRCReturn(rcCtxImport, rcCtxImport); \
793	} \
794	} while (0)
795
796	/** @def IEM_CTX_IMPORT_NORET
797	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
798	*
799	* Will call the keep to import the bits as needed.
800	*
801	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
802	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
803	*/
804	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
805	do { \
806	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
807	{ /* likely */ } \
808	else \
809	{ \
810	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
811	AssertLogRelRC(rcCtxImport); \
812	} \
813	} while (0)
814
815	/** @def IEM_CTX_IMPORT_JMP
816	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
817	*
818	* Will call the keep to import the bits as needed.
819	*
820	* Jumps on import failure.
821	*
822	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
823	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
824	*/
825	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
826	do { \
827	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
828	{ /* likely */ } \
829	else \
830	{ \
831	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
832	AssertRCStmt(rcCtxImport, longjmp(*pVCpu->iem.s.CTX_SUFF(pJmpBuf), rcCtxImport)); \
833	} \
834	} while (0)
835
836
837
838	/** @def IEM_GET_TARGET_CPU
839	* Gets the current IEMTARGETCPU value.
840	* @returns IEMTARGETCPU value.
841	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
842	*/
843	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
844	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
845	#else
846	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
847	#endif
848
849	/** @def IEM_GET_INSTR_LEN
850	* Gets the instruction length. */
851	#ifdef IEM_WITH_CODE_TLB
852	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
853	#else
854	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
855	#endif
856
857
858	/**
859	* Shared per-VM IEM data.
860	*/
861	typedef struct IEM
862	{
863	/** The VMX APIC-access page handler type. */
864	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
865	} IEM;
866
867
868
869	/** @name IEM_ACCESS_XXX - Access details.
870	* @{ */
871	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
872	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
873	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
874	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
875	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
876	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
877	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
878	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
879	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
880	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
881	/** The writes are partial, so if initialize the bounce buffer with the
882	* orignal RAM content. */
883	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
884	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
885	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
886	/** Bounce buffer with ring-3 write pending, first page. */
887	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
888	/** Bounce buffer with ring-3 write pending, second page. */
889	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
890	/** Not locked, accessed via the TLB. */
891	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
892	/** Valid bit mask. */
893	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
894	/** Shift count for the TLB flags (upper word). */
895	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
896
897	/** Read+write data alias. */
898	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
899	/** Write data alias. */
900	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
901	/** Read data alias. */
902	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
903	/** Instruction fetch alias. */
904	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
905	/** Stack write alias. */
906	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
907	/** Stack read alias. */
908	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
909	/** Stack read+write alias. */
910	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
911	/** Read system table alias. */
912	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
913	/** Read+write system table alias. */
914	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
915	/** @} */
916
917	/** @name Prefix constants (IEMCPU::fPrefixes)
918	* @{ */
919	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
920	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
921	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
922	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
923	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
924	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
925	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
926
927	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
928	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
929	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
930
931	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
932	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
933	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
934
935	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
936	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
937	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
938	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
939	/** Mask with all the REX prefix flags.
940	* This is generally for use when needing to undo the REX prefixes when they
941	* are followed legacy prefixes and therefore does not immediately preceed
942	* the first opcode byte.
943	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
944	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
945
946	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
947	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
948	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
949	/** @} */
950
951	/** @name IEMOPFORM_XXX - Opcode forms
952	* @note These are ORed together with IEMOPHINT_XXX.
953	* @{ */
954	/** ModR/M: reg, r/m */
955	#define IEMOPFORM_RM 0
956	/** ModR/M: reg, r/m (register) */
957	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
958	/** ModR/M: reg, r/m (memory) */
959	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
960	/** ModR/M: reg, r/m */
961	#define IEMOPFORM_RMI 1
962	/** ModR/M: reg, r/m (register) */
963	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
964	/** ModR/M: reg, r/m (memory) */
965	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
966	/** ModR/M: r/m, reg */
967	#define IEMOPFORM_MR 2
968	/** ModR/M: r/m (register), reg */
969	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
970	/** ModR/M: r/m (memory), reg */
971	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
972	/** ModR/M: r/m only */
973	#define IEMOPFORM_M 3
974	/** ModR/M: r/m only (register). */
975	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
976	/** ModR/M: r/m only (memory). */
977	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
978	/** ModR/M: reg only */
979	#define IEMOPFORM_R 4
980
981	/** VEX+ModR/M: reg, r/m */
982	#define IEMOPFORM_VEX_RM 8
983	/** VEX+ModR/M: reg, r/m (register) */
984	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
985	/** VEX+ModR/M: reg, r/m (memory) */
986	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
987	/** VEX+ModR/M: r/m, reg */
988	#define IEMOPFORM_VEX_MR 9
989	/** VEX+ModR/M: r/m (register), reg */
990	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
991	/** VEX+ModR/M: r/m (memory), reg */
992	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
993	/** VEX+ModR/M: r/m only */
994	#define IEMOPFORM_VEX_M 10
995	/** VEX+ModR/M: r/m only (register). */
996	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
997	/** VEX+ModR/M: r/m only (memory). */
998	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
999	/** VEX+ModR/M: reg only */
1000	#define IEMOPFORM_VEX_R 11
1001	/** VEX+ModR/M: reg, vvvv, r/m */
1002	#define IEMOPFORM_VEX_RVM 12
1003	/** VEX+ModR/M: reg, vvvv, r/m (register). */
1004	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
1005	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
1006	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
1007	/** VEX+ModR/M: reg, r/m, vvvv */
1008	#define IEMOPFORM_VEX_RMV 13
1009	/** VEX+ModR/M: reg, r/m, vvvv (register). */
1010	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
1011	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1012	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
1013	/** VEX+ModR/M: reg, r/m, imm8 */
1014	#define IEMOPFORM_VEX_RMI 14
1015	/** VEX+ModR/M: reg, r/m, imm8 (register). */
1016	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
1017	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1018	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1019	/** VEX+ModR/M: r/m, vvvv, reg */
1020	#define IEMOPFORM_VEX_MVR 15
1021	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1022	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1023	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1024	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1025	/** VEX+ModR/M+/n: vvvv, r/m */
1026	#define IEMOPFORM_VEX_VM 16
1027	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1028	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1029	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1030	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1031
1032	/** Fixed register instruction, no R/M. */
1033	#define IEMOPFORM_FIXED 32
1034
1035	/** The r/m is a register. */
1036	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1037	/** The r/m is a memory access. */
1038	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1039	/** @} */
1040
1041	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1042	* @note These are ORed together with IEMOPFORM_XXX.
1043	* @{ */
1044	/** Ignores the operand size prefix (66h). */
1045	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1046	/** Ignores REX.W (aka WIG). */
1047	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1048	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1049	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1050	/** Allowed with the lock prefix. */
1051	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1052	/** The VEX.L value is ignored (aka LIG). */
1053	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1054	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1055	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1056	/** The VEX.V value must be zero. */
1057	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1058
1059	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1060	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1061	/** @} */
1062
1063	/**
1064	* Possible hardware task switch sources.
1065	*/
1066	typedef enum IEMTASKSWITCH
1067	{
1068	/** Task switch caused by an interrupt/exception. */
1069	IEMTASKSWITCH_INT_XCPT = 1,
1070	/** Task switch caused by a far CALL. */
1071	IEMTASKSWITCH_CALL,
1072	/** Task switch caused by a far JMP. */
1073	IEMTASKSWITCH_JUMP,
1074	/** Task switch caused by an IRET. */
1075	IEMTASKSWITCH_IRET
1076	} IEMTASKSWITCH;
1077	AssertCompileSize(IEMTASKSWITCH, 4);
1078
1079	/**
1080	* Possible CrX load (write) sources.
1081	*/
1082	typedef enum IEMACCESSCRX
1083	{
1084	/** CrX access caused by 'mov crX' instruction. */
1085	IEMACCESSCRX_MOV_CRX,
1086	/** CrX (CR0) write caused by 'lmsw' instruction. */
1087	IEMACCESSCRX_LMSW,
1088	/** CrX (CR0) write caused by 'clts' instruction. */
1089	IEMACCESSCRX_CLTS,
1090	/** CrX (CR0) read caused by 'smsw' instruction. */
1091	IEMACCESSCRX_SMSW
1092	} IEMACCESSCRX;
1093
1094	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1095	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1096	*
1097	* These flags provide further context to SLAT page-walk failures that could not be
1098	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1099	*
1100	* @{
1101	*/
1102	/** Translating a nested-guest linear address failed accessing a nested-guest
1103	* physical address. */
1104	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1105	/** Translating a nested-guest linear address failed accessing a
1106	* paging-structure entry or updating accessed/dirty bits. */
1107	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1108	/** @} */
1109
1110	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1111	# ifndef IN_RING3
1112	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1113	# endif
1114	#endif
1115
1116	/**
1117	* Indicates to the verifier that the given flag set is undefined.
1118	*
1119	* Can be invoked again to add more flags.
1120	*
1121	* This is a NOOP if the verifier isn't compiled in.
1122	*
1123	* @note We're temporarily keeping this until code is converted to new
1124	* disassembler style opcode handling.
1125	*/
1126	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1127
1128
1129	/** @def IEM_DECL_IMPL_TYPE
1130	* For typedef'ing an instruction implementation function.
1131	*
1132	* @param a_RetType The return type.
1133	* @param a_Name The name of the type.
1134	* @param a_ArgList The argument list enclosed in parentheses.
1135	*/
1136
1137	/** @def IEM_DECL_IMPL_DEF
1138	* For defining an instruction implementation function.
1139	*
1140	* @param a_RetType The return type.
1141	* @param a_Name The name of the type.
1142	* @param a_ArgList The argument list enclosed in parentheses.
1143	*/
1144
1145	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1146	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1147	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1148	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1149	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1150	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1151	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1152
1153	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1154	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1155	a_RetType (__fastcall a_Name) a_ArgList
1156	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1157	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1158	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1159	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1160
1161	#elif __cplusplus >= 201700 /* P0012R1 support */
1162	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1163	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1164	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1165	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1166	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1167	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1168
1169	#else
1170	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1171	a_RetType (VBOXCALL a_Name) a_ArgList
1172	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1173	a_RetType VBOXCALL a_Name a_ArgList
1174	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1175	a_RetType VBOXCALL a_Name a_ArgList
1176
1177	#endif
1178
1179	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1180	RT_C_DECLS_BEGIN
1181	extern uint8_t const g_afParity[256];
1182	RT_C_DECLS_END
1183
1184
1185	/** @name Arithmetic assignment operations on bytes (binary).
1186	* @{ */
1187	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1188	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1189	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1190	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1191	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1192	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1193	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1194	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1195	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1196	/** @} */
1197
1198	/** @name Arithmetic assignment operations on words (binary).
1199	* @{ */
1200	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1201	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1202	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1203	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1204	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1205	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1206	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1207	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1208	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1209	/** @} */
1210
1211	/** @name Arithmetic assignment operations on double words (binary).
1212	* @{ */
1213	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1214	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1215	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1216	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1217	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1218	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1219	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1220	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1221	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1222	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1223	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1224	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1225	/** @} */
1226
1227	/** @name Arithmetic assignment operations on quad words (binary).
1228	* @{ */
1229	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1230	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1231	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1232	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1233	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1234	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1235	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1236	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1237	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1238	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1239	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1240	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1241	/** @} */
1242
1243	/** @name Compare operations (thrown in with the binary ops).
1244	* @{ */
1245	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1246	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1247	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1248	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1249	/** @} */
1250
1251	/** @name Test operations (thrown in with the binary ops).
1252	* @{ */
1253	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1254	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1255	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1256	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1257	/** @} */
1258
1259	/** @name Bit operations operations (thrown in with the binary ops).
1260	* @{ */
1261	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1262	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1263	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1264	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1265	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1266	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1267	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1268	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1269	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1270	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1271	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1272	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1273	/** @} */
1274
1275	/** @name Arithmetic three operand operations on double words (binary).
1276	* @{ */
1277	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
1278	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1279	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1280	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1281	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1282	/** @} */
1283
1284	/** @name Arithmetic three operand operations on quad words (binary).
1285	* @{ */
1286	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
1287	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1288	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1289	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1290	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1291	/** @} */
1292
1293	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1294	* @{ */
1295	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1296	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1297	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1298	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1299	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1300	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1301	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1302	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1303	/** @} */
1304
1305	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1306	* @{ */
1307	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1308	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1309	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1310	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1311	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1312	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1313	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1314	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1315	/** @} */
1316
1317	/** @name MULX 32-bit and 64-bit.
1318	* @{ */
1319	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
1320	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1321	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1322
1323	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
1324	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1325	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1326	/** @} */
1327
1328
1329	/** @name Exchange memory with register operations.
1330	* @{ */
1331	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1332	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1333	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1334	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1335	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1336	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1337	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1338	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1339	/** @} */
1340
1341	/** @name Exchange and add operations.
1342	* @{ */
1343	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1344	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1345	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1346	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1347	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1348	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1349	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1350	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1351	/** @} */
1352
1353	/** @name Compare and exchange.
1354	* @{ */
1355	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1356	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1357	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1358	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1359	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1360	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1361	#if ARCH_BITS == 32
1362	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1363	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1364	#else
1365	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1366	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1367	#endif
1368	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1369	uint32_t *pEFlags));
1370	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1371	uint32_t *pEFlags));
1372	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1373	uint32_t *pEFlags));
1374	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1375	uint32_t *pEFlags));
1376	#ifndef RT_ARCH_ARM64
1377	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1378	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1379	#endif
1380	/** @} */
1381
1382	/** @name Memory ordering
1383	* @{ */
1384	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1385	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1386	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1387	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1388	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1389	#ifndef RT_ARCH_ARM64
1390	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1391	#endif
1392	/** @} */
1393
1394	/** @name Double precision shifts
1395	* @{ */
1396	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1397	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1398	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1399	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1400	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1401	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1402	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1403	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1404	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1405	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1406	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1407	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1408	/** @} */
1409
1410
1411	/** @name Bit search operations (thrown in with the binary ops).
1412	* @{ */
1413	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1414	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1415	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1416	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1417	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1418	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1419	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1420	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1421	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1422	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
1423	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
1424	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
1425	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
1426	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
1427	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
1428	/** @} */
1429
1430	/** @name Signed multiplication operations (thrown in with the binary ops).
1431	* @{ */
1432	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1433	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1434	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1435	/** @} */
1436
1437	/** @name Arithmetic assignment operations on bytes (unary).
1438	* @{ */
1439	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1440	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1441	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1442	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1443	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1444	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1445	/** @} */
1446
1447	/** @name Arithmetic assignment operations on words (unary).
1448	* @{ */
1449	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1450	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1451	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1452	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1453	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1454	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1455	/** @} */
1456
1457	/** @name Arithmetic assignment operations on double words (unary).
1458	* @{ */
1459	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1460	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1461	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1462	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1463	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1464	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1465	/** @} */
1466
1467	/** @name Arithmetic assignment operations on quad words (unary).
1468	* @{ */
1469	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1470	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1471	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1472	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1473	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1474	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1475	/** @} */
1476
1477
1478	/** @name Shift operations on bytes (Group 2).
1479	* @{ */
1480	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1481	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1482	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1483	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1484	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1485	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1486	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1487	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1488	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1489	/** @} */
1490
1491	/** @name Shift operations on words (Group 2).
1492	* @{ */
1493	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1494	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1495	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1496	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1497	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1498	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1499	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1500	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1501	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1502	/** @} */
1503
1504	/** @name Shift operations on double words (Group 2).
1505	* @{ */
1506	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1507	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1508	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1509	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1510	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1511	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1512	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1513	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1514	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1515	/** @} */
1516
1517	/** @name Shift operations on words (Group 2).
1518	* @{ */
1519	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1520	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1521	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1522	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1523	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1524	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1525	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1526	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1527	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1528	/** @} */
1529
1530	/** @name Multiplication and division operations.
1531	* @{ */
1532	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1533	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1534	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1535	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1536	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1537	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1538
1539	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1540	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1541	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1542	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1543	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1544	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1545
1546	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1547	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1548	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1549	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1550	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1551	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1552
1553	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1554	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1555	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1556	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1557	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1558	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1559	/** @} */
1560
1561	/** @name Byte Swap.
1562	* @{ */
1563	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1564	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1565	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1566	/** @} */
1567
1568	/** @name Misc.
1569	* @{ */
1570	FNIEMAIMPLBINU16 iemAImpl_arpl;
1571	/** @} */
1572
1573
1574	/** @name FPU operations taking a 32-bit float argument
1575	* @{ */
1576	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1577	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1578	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1579
1580	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1581	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1582	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1583
1584	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1585	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1586	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1587	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1588	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1589	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1590	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1591
1592	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1593	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1594	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1595	/** @} */
1596
1597	/** @name FPU operations taking a 64-bit float argument
1598	* @{ */
1599	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1600	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1601	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
1602
1603	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1604	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1605	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1606
1607	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
1608	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1609	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1610	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1611	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1612	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1613	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1614
1615	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1616	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1617	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1618	/** @} */
1619
1620	/** @name FPU operations taking a 80-bit float argument
1621	* @{ */
1622	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1623	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1624	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1625	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1626	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1627	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1628	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1629	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1630	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1631	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1632	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1633	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1634
1635	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
1636	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
1637	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
1638
1639	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1640	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1641	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1642	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1643	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1644
1645	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1646	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1647	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1648	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1649	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1650
1651	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1652	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1653	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1654	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1655	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
1656	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1657	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1658	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
1659	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
1660
1661	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1662	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1663	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1664	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1665
1666	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1667	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1668	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1669	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1670	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1671	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1672	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1673	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1674	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1675
1676	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1677	PCRTFLOAT80U pr80Val));
1678	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1679	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
1680	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1681	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
1682
1683	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1684	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1685	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1686
1687	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
1688	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1689	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
1690
1691	/** @} */
1692
1693	/** @name FPU operations taking a 16-bit signed integer argument
1694	* @{ */
1695	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1696	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1697	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1698	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1699	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
1700	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
1701
1702	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1703	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1704	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1705	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1706	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1707	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1708
1709	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1710	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1711	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
1712	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
1713
1714	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1715	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
1716	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
1717	/** @} */
1718
1719	/** @name FPU operations taking a 32-bit signed integer argument
1720	* @{ */
1721	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1722	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1723	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1724	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1725	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
1726	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
1727
1728	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1729	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1730	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1731	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1732	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1733	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1734
1735	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1736	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1737	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
1738	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
1739
1740	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1741	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
1742	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
1743	/** @} */
1744
1745	/** @name FPU operations taking a 64-bit signed integer argument
1746	* @{ */
1747	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1748	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
1749	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
1750
1751	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1752	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
1753	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
1754	/** @} */
1755
1756
1757	/** Temporary type representing a 256-bit vector register. */
1758	typedef struct { uint64_t au64[4]; } IEMVMM256;
1759	/** Temporary type pointing to a 256-bit vector register. */
1760	typedef IEMVMM256 *PIEMVMM256;
1761	/** Temporary type pointing to a const 256-bit vector register. */
1762	typedef IEMVMM256 *PCIEMVMM256;
1763
1764
1765	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1766	* @{ */
1767	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
1768	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1769	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1770	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1771	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1772	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
1773	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1774	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
1775	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
1776	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
1777	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
1778	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
1779	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1780	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
1781	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1782	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
1783	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
1784	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
1785	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
1786	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
1787	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1788	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
1789	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
1790	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
1791	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
1792	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
1793	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
1794	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
1795	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
1796	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
1797	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
1798	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
1799	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
1800	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
1801	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
1802	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
1803	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
1804	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
1805	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
1806	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
1807	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
1808	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
1809	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
1810	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
1811	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
1812	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
1813	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
1814	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
1815	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
1816	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
1817	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
1818	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
1819	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
1820	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
1821	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
1822	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
1823	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
1824
1825	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
1826	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
1827	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1828	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
1829	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
1830	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
1831	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
1832	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
1833	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
1834	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
1835	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
1836	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
1837	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
1838	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
1839	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
1840	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
1841	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
1842	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
1843	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
1844	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
1845	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
1846	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
1847	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
1848	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
1849	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
1850	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
1851	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
1852	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
1853	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
1854	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
1855	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
1856	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
1857	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
1858	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
1859	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
1860	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
1861	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
1862	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
1863	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
1864	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
1865	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
1866	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
1867	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
1868	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
1869	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
1870	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
1871	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
1872	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
1873	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
1874	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
1875	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
1876	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
1877	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
1878	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
1879	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
1880	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
1881	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
1882
1883	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
1884	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
1885	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
1886	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
1887	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
1888	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
1889	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
1890	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
1891	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
1892	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
1893	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
1894	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
1895	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
1896	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
1897	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
1898	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
1899	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
1900	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
1901	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
1902	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
1903	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
1904	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
1905	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
1906	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
1907	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
1908	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
1909	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
1910	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
1911	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
1912	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
1913	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
1914	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
1915	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
1916	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
1917	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
1918	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
1919	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
1920	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
1921	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
1922	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
1923	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
1924	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
1925	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
1926	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
1927	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
1928	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
1929	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
1930	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
1931	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
1932	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
1933	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
1934	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
1935	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
1936	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
1937	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
1938	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
1939	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
1940
1941	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
1942	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
1943	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
1944	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
1945
1946	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
1947	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
1948	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
1949	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
1950	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
1951	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
1952	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
1953	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
1954	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
1955	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
1956	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
1957	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
1958	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
1959	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
1960	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
1961	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
1962	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
1963	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
1964	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
1965	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
1966	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
1967	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
1968	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
1969	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
1970	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
1971	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
1972	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
1973	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
1974	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
1975	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
1976	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
1977	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
1978	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
1979	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
1980	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
1981	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
1982	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
1983	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
1984	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
1985	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
1986	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
1987	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
1988	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
1989	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
1990	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
1991	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
1992	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
1993	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
1994	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
1995	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
1996	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
1997	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
1998	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
1999	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
2000	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
2001	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
2002	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
2003
2004	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
2005	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
2006	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
2007	/** @} */
2008
2009	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2010	* @{ */
2011	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2012	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2013	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2014	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2015	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2016	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2017	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2018	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2019	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2020	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2021
2022	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2023	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2024	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2025	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2026	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2027	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2028	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2029	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2030	/** @} */
2031
2032	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2033	* @{ */
2034	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2035	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2036	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2037	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2038	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2039	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2040	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2041	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2042	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2043	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2044	/** @} */
2045
2046	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2047	* @{ */
2048	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2049	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2050	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2051	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2052	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
2053	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2054	#ifndef IEM_WITHOUT_ASSEMBLY
2055	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2056	#endif
2057	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2058	/** @} */
2059
2060	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2061	* @{ */
2062	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2063	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2064	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2065	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2066	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2067	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2068	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2069	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2070	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2071	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2072	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2073	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2074	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2075	/** @} */
2076
2077	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2078	* @{ */
2079	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
2080	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2081	#ifndef IEM_WITHOUT_ASSEMBLY
2082	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2083	#endif
2084	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2085	/** @} */
2086
2087	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
2088	* @{ */
2089	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
2090	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
2091	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
2092	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
2093	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
2094	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
2095
2096	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
2097	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
2098	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
2099	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
2100	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
2101	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
2102
2103	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
2104	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
2105	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
2106	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
2107	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
2108	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
2109
2110	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
2111	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
2112	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
2113	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
2114	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
2115	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
2116	/** @} */
2117
2118
2119	/** @name Media (SSE/MMX/AVX) operation: Sort this later
2120	* @{ */
2121	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2122	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2123	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PRTUINT128U puDst, uint64_t uSrc));
2124
2125	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2126	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2127	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2128	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2129	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2130	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2131
2132	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2133	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2134	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2135	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2136	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2137
2138	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2139	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2140	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2141	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2142	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2143
2144	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2145	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2146	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2147	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2148	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2149
2150	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2151	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2152	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2153	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2154	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2155
2156	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2157	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2158	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2159	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2160	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2161
2162	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2163	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2164	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2165	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2166	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2167
2168	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2169	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2170	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2171	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2172	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2173
2174	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2175	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2176	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2177	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2178	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2179
2180	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2181	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2182	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2183	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2184	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2185
2186	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2187	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2188	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2189	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2190	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2191
2192	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2193	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2194	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2195	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2196	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2197
2198	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2199	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2200	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2201	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2202	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2203
2204	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2205	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2206	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2207	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2208	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2209
2210	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2211	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2212	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2213	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2214	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2215
2216	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2217	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2218
2219	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2220	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
2221	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2222	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
2223	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2224	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
2225
2226	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
2227	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
2228	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
2229	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
2230
2231	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
2232	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
2233	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
2234	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
2235
2236	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
2237	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
2238	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
2239	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
2240
2241
2242	typedef struct IEMPCMPISTRISRC
2243	{
2244	RTUINT128U uSrc1;
2245	RTUINT128U uSrc2;
2246	} IEMPCMPISTRISRC;
2247	typedef IEMPCMPISTRISRC *PIEMPCMPISTRISRC;
2248	typedef const IEMPCMPISTRISRC *PCIEMPCMPISTRISRC;
2249
2250	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpistri_u128,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRISRC pSrc, uint8_t bEvil));
2251	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpistri_u128_fallback,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRISRC pSrc, uint8_t bEvil));
2252
2253	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
2254	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
2255	/** @} */
2256
2257	/** @name Media Odds and Ends
2258	* @{ */
2259	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
2260	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
2261	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
2262	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
2263	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
2264	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
2265	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
2266	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
2267
2268	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
2269	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
2270	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
2271	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
2272	/** @} */
2273
2274
2275	/** @name Function tables.
2276	* @{
2277	*/
2278
2279	/**
2280	* Function table for a binary operator providing implementation based on
2281	* operand size.
2282	*/
2283	typedef struct IEMOPBINSIZES
2284	{
2285	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
2286	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
2287	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
2288	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
2289	} IEMOPBINSIZES;
2290	/** Pointer to a binary operator function table. */
2291	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
2292
2293
2294	/**
2295	* Function table for a unary operator providing implementation based on
2296	* operand size.
2297	*/
2298	typedef struct IEMOPUNARYSIZES
2299	{
2300	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
2301	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
2302	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
2303	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
2304	} IEMOPUNARYSIZES;
2305	/** Pointer to a unary operator function table. */
2306	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
2307
2308
2309	/**
2310	* Function table for a shift operator providing implementation based on
2311	* operand size.
2312	*/
2313	typedef struct IEMOPSHIFTSIZES
2314	{
2315	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
2316	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
2317	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
2318	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
2319	} IEMOPSHIFTSIZES;
2320	/** Pointer to a shift operator function table. */
2321	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
2322
2323
2324	/**
2325	* Function table for a multiplication or division operation.
2326	*/
2327	typedef struct IEMOPMULDIVSIZES
2328	{
2329	PFNIEMAIMPLMULDIVU8 pfnU8;
2330	PFNIEMAIMPLMULDIVU16 pfnU16;
2331	PFNIEMAIMPLMULDIVU32 pfnU32;
2332	PFNIEMAIMPLMULDIVU64 pfnU64;
2333	} IEMOPMULDIVSIZES;
2334	/** Pointer to a multiplication or division operation function table. */
2335	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
2336
2337
2338	/**
2339	* Function table for a double precision shift operator providing implementation
2340	* based on operand size.
2341	*/
2342	typedef struct IEMOPSHIFTDBLSIZES
2343	{
2344	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
2345	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
2346	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
2347	} IEMOPSHIFTDBLSIZES;
2348	/** Pointer to a double precision shift function table. */
2349	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
2350
2351
2352	/**
2353	* Function table for media instruction taking two full sized media source
2354	* registers and one full sized destination register (AVX).
2355	*/
2356	typedef struct IEMOPMEDIAF3
2357	{
2358	PFNIEMAIMPLMEDIAF3U128 pfnU128;
2359	PFNIEMAIMPLMEDIAF3U256 pfnU256;
2360	} IEMOPMEDIAF3;
2361	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2362	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
2363
2364	/** @def IEMOPMEDIAF3_INIT_VARS_EX
2365	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2366	* given functions as initializers. For use in AVX functions where a pair of
2367	* functions are only used once and the function table need not be public. */
2368	#ifndef TST_IEM_CHECK_MC
2369	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2370	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2371	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2372	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2373	# else
2374	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2375	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2376	# endif
2377	#else
2378	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2379	#endif
2380	/** @def IEMOPMEDIAF3_INIT_VARS
2381	* Generate AVX function tables for the @a a_InstrNm instruction.
2382	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
2383	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
2384	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2385	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2386
2387	/**
2388	* Function table for media instruction taking two full sized media source
2389	* registers and one full sized destination register, but no additional state
2390	* (AVX).
2391	*/
2392	typedef struct IEMOPMEDIAOPTF3
2393	{
2394	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
2395	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
2396	} IEMOPMEDIAOPTF3;
2397	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2398	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
2399
2400	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
2401	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2402	* given functions as initializers. For use in AVX functions where a pair of
2403	* functions are only used once and the function table need not be public. */
2404	#ifndef TST_IEM_CHECK_MC
2405	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2406	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2407	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2408	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2409	# else
2410	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2411	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2412	# endif
2413	#else
2414	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2415	#endif
2416	/** @def IEMOPMEDIAOPTF3_INIT_VARS
2417	* Generate AVX function tables for the @a a_InstrNm instruction.
2418	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
2419	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
2420	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2421	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2422
2423	/**
2424	* Function table for media instruction taking one full sized media source
2425	* registers and one full sized destination register, but no additional state
2426	* (AVX).
2427	*/
2428	typedef struct IEMOPMEDIAOPTF2
2429	{
2430	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
2431	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
2432	} IEMOPMEDIAOPTF2;
2433	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
2434	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
2435
2436	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
2437	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2438	* given functions as initializers. For use in AVX functions where a pair of
2439	* functions are only used once and the function table need not be public. */
2440	#ifndef TST_IEM_CHECK_MC
2441	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2442	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2443	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2444	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2445	# else
2446	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2447	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2448	# endif
2449	#else
2450	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2451	#endif
2452	/** @def IEMOPMEDIAOPTF2_INIT_VARS
2453	* Generate AVX function tables for the @a a_InstrNm instruction.
2454	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
2455	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
2456	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2457	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2458
2459	/**
2460	* Function table for media instruction taking two full sized media source
2461	* registers and one full sized destination register and an 8-bit immediate, but no additional state
2462	* (AVX).
2463	*/
2464	typedef struct IEMOPMEDIAOPTF3IMM8
2465	{
2466	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
2467	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
2468	} IEMOPMEDIAOPTF3IMM8;
2469	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2470	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
2471
2472	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
2473	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2474	* given functions as initializers. For use in AVX functions where a pair of
2475	* functions are only used once and the function table need not be public. */
2476	#ifndef TST_IEM_CHECK_MC
2477	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2478	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2479	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2480	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2481	# else
2482	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2483	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2484	# endif
2485	#else
2486	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2487	#endif
2488	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
2489	* Generate AVX function tables for the @a a_InstrNm instruction.
2490	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
2491	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
2492	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2493	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2494	/** @} */
2495
2496
2497	/**
2498	* Function table for blend type instruction taking three full sized media source
2499	* registers and one full sized destination register, but no additional state
2500	* (AVX).
2501	*/
2502	typedef struct IEMOPBLENDOP
2503	{
2504	PFNIEMAIMPLAVXBLENDU128 pfnU128;
2505	PFNIEMAIMPLAVXBLENDU256 pfnU256;
2506	} IEMOPBLENDOP;
2507	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
2508	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
2509
2510	/** @def IEMOPBLENDOP_INIT_VARS_EX
2511	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2512	* given functions as initializers. For use in AVX functions where a pair of
2513	* functions are only used once and the function table need not be public. */
2514	#ifndef TST_IEM_CHECK_MC
2515	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2516	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2517	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2518	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2519	# else
2520	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2521	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2522	# endif
2523	#else
2524	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2525	#endif
2526	/** @def IEMOPBLENDOP_INIT_VARS
2527	* Generate AVX function tables for the @a a_InstrNm instruction.
2528	* @sa IEMOPBLENDOP_INIT_VARS_EX */
2529	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
2530	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2531	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2532
2533
2534	/** @name SSE/AVX single/double precision floating point operations.
2535	* @{ */
2536	/**
2537	* A SSE result.
2538	*/
2539	typedef struct IEMSSERESULT
2540	{
2541	/** The output value. */
2542	X86XMMREG uResult;
2543	/** The output status. */
2544	uint32_t MXCSR;
2545	} IEMSSERESULT;
2546	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
2547	/** Pointer to a SSE result. */
2548	typedef IEMSSERESULT *PIEMSSERESULT;
2549	/** Pointer to a const SSE result. */
2550	typedef IEMSSERESULT const *PCIEMSSERESULT;
2551
2552
2553	/**
2554	* A AVX128 result.
2555	*/
2556	typedef struct IEMAVX128RESULT
2557	{
2558	/** The output value. */
2559	X86XMMREG uResult;
2560	/** The output status. */
2561	uint32_t MXCSR;
2562	} IEMAVX128RESULT;
2563	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
2564	/** Pointer to a AVX128 result. */
2565	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
2566	/** Pointer to a const AVX128 result. */
2567	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
2568
2569
2570	/**
2571	* A AVX256 result.
2572	*/
2573	typedef struct IEMAVX256RESULT
2574	{
2575	/** The output value. */
2576	X86YMMREG uResult;
2577	/** The output status. */
2578	uint32_t MXCSR;
2579	} IEMAVX256RESULT;
2580	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
2581	/** Pointer to a AVX256 result. */
2582	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
2583	/** Pointer to a const AVX256 result. */
2584	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
2585
2586
2587	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2588	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
2589	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2590	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
2591	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2592	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
2593
2594	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2595	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
2596	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2597	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
2598	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2599	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
2600
2601	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
2602	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
2603
2604	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
2605	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
2606	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
2607	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
2608	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
2609	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
2610	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
2611	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
2612	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
2613	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
2614	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
2615	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
2616	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
2617	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
2618	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
2619	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
2620	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
2621	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
2622	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
2623	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
2624	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
2625
2626	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
2627	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
2628	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
2629	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
2630	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
2631	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
2632	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
2633	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
2634	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
2635	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
2636	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
2637	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
2638	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
2639	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
2640	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
2641	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
2642
2643	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
2644	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
2645	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
2646	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
2647	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
2648	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
2649	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
2650	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
2651	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
2652	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
2653	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
2654	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
2655	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
2656	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
2657	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
2658	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
2659	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
2660	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
2661	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
2662	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
2663	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
2664
2665	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
2666	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
2667	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
2668	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
2669	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
2670	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
2671	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
2672	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
2673	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
2674	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
2675	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
2676	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
2677	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
2678	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
2679
2680	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
2681	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
2682	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
2683	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
2684	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
2685	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
2686	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
2687	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
2688	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
2689	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
2690	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
2691	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
2692	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
2693	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
2694	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
2695	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
2696	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
2697	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
2698	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
2699	/** @} */
2700
2701	/** @name C instruction implementations for anything slightly complicated.
2702	* @{ */
2703
2704	/**
2705	* For typedef'ing or declaring a C instruction implementation function taking
2706	* no extra arguments.
2707	*
2708	* @param a_Name The name of the type.
2709	*/
2710	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
2711	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2712	/**
2713	* For defining a C instruction implementation function taking no extra
2714	* arguments.
2715	*
2716	* @param a_Name The name of the function
2717	*/
2718	# define IEM_CIMPL_DEF_0(a_Name) \
2719	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2720	/**
2721	* Prototype version of IEM_CIMPL_DEF_0.
2722	*/
2723	# define IEM_CIMPL_PROTO_0(a_Name) \
2724	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2725	/**
2726	* For calling a C instruction implementation function taking no extra
2727	* arguments.
2728	*
2729	* This special call macro adds default arguments to the call and allow us to
2730	* change these later.
2731	*
2732	* @param a_fn The name of the function.
2733	*/
2734	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
2735
2736	/**
2737	* For typedef'ing or declaring a C instruction implementation function taking
2738	* one extra argument.
2739	*
2740	* @param a_Name The name of the type.
2741	* @param a_Type0 The argument type.
2742	* @param a_Arg0 The argument name.
2743	*/
2744	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
2745	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2746	/**
2747	* For defining a C instruction implementation function taking one extra
2748	* argument.
2749	*
2750	* @param a_Name The name of the function
2751	* @param a_Type0 The argument type.
2752	* @param a_Arg0 The argument name.
2753	*/
2754	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
2755	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2756	/**
2757	* Prototype version of IEM_CIMPL_DEF_1.
2758	*/
2759	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
2760	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2761	/**
2762	* For calling a C instruction implementation function taking one extra
2763	* argument.
2764	*
2765	* This special call macro adds default arguments to the call and allow us to
2766	* change these later.
2767	*
2768	* @param a_fn The name of the function.
2769	* @param a0 The name of the 1st argument.
2770	*/
2771	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
2772
2773	/**
2774	* For typedef'ing or declaring a C instruction implementation function taking
2775	* two extra arguments.
2776	*
2777	* @param a_Name The name of the type.
2778	* @param a_Type0 The type of the 1st argument
2779	* @param a_Arg0 The name of the 1st argument.
2780	* @param a_Type1 The type of the 2nd argument.
2781	* @param a_Arg1 The name of the 2nd argument.
2782	*/
2783	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2784	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2785	/**
2786	* For defining a C instruction implementation function taking two extra
2787	* arguments.
2788	*
2789	* @param a_Name The name of the function.
2790	* @param a_Type0 The type of the 1st argument
2791	* @param a_Arg0 The name of the 1st argument.
2792	* @param a_Type1 The type of the 2nd argument.
2793	* @param a_Arg1 The name of the 2nd argument.
2794	*/
2795	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2796	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2797	/**
2798	* Prototype version of IEM_CIMPL_DEF_2.
2799	*/
2800	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2801	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2802	/**
2803	* For calling a C instruction implementation function taking two extra
2804	* arguments.
2805	*
2806	* This special call macro adds default arguments to the call and allow us to
2807	* change these later.
2808	*
2809	* @param a_fn The name of the function.
2810	* @param a0 The name of the 1st argument.
2811	* @param a1 The name of the 2nd argument.
2812	*/
2813	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
2814
2815	/**
2816	* For typedef'ing or declaring a C instruction implementation function taking
2817	* three extra arguments.
2818	*
2819	* @param a_Name The name of the type.
2820	* @param a_Type0 The type of the 1st argument
2821	* @param a_Arg0 The name of the 1st argument.
2822	* @param a_Type1 The type of the 2nd argument.
2823	* @param a_Arg1 The name of the 2nd argument.
2824	* @param a_Type2 The type of the 3rd argument.
2825	* @param a_Arg2 The name of the 3rd argument.
2826	*/
2827	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2828	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2829	/**
2830	* For defining a C instruction implementation function taking three extra
2831	* arguments.
2832	*
2833	* @param a_Name The name of the function.
2834	* @param a_Type0 The type of the 1st argument
2835	* @param a_Arg0 The name of the 1st argument.
2836	* @param a_Type1 The type of the 2nd argument.
2837	* @param a_Arg1 The name of the 2nd argument.
2838	* @param a_Type2 The type of the 3rd argument.
2839	* @param a_Arg2 The name of the 3rd argument.
2840	*/
2841	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2842	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2843	/**
2844	* Prototype version of IEM_CIMPL_DEF_3.
2845	*/
2846	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
2847	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
2848	/**
2849	* For calling a C instruction implementation function taking three extra
2850	* arguments.
2851	*
2852	* This special call macro adds default arguments to the call and allow us to
2853	* change these later.
2854	*
2855	* @param a_fn The name of the function.
2856	* @param a0 The name of the 1st argument.
2857	* @param a1 The name of the 2nd argument.
2858	* @param a2 The name of the 3rd argument.
2859	*/
2860	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
2861
2862
2863	/**
2864	* For typedef'ing or declaring a C instruction implementation function taking
2865	* four extra arguments.
2866	*
2867	* @param a_Name The name of the type.
2868	* @param a_Type0 The type of the 1st argument
2869	* @param a_Arg0 The name of the 1st argument.
2870	* @param a_Type1 The type of the 2nd argument.
2871	* @param a_Arg1 The name of the 2nd argument.
2872	* @param a_Type2 The type of the 3rd argument.
2873	* @param a_Arg2 The name of the 3rd argument.
2874	* @param a_Type3 The type of the 4th argument.
2875	* @param a_Arg3 The name of the 4th argument.
2876	*/
2877	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
2878	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
2879	/**
2880	* For defining a C instruction implementation function taking four extra
2881	* arguments.
2882	*
2883	* @param a_Name The name of the function.
2884	* @param a_Type0 The type of the 1st argument
2885	* @param a_Arg0 The name of the 1st argument.
2886	* @param a_Type1 The type of the 2nd argument.
2887	* @param a_Arg1 The name of the 2nd argument.
2888	* @param a_Type2 The type of the 3rd argument.
2889	* @param a_Arg2 The name of the 3rd argument.
2890	* @param a_Type3 The type of the 4th argument.
2891	* @param a_Arg3 The name of the 4th argument.
2892	*/
2893	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
2894	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2895	a_Type2 a_Arg2, a_Type3 a_Arg3))
2896	/**
2897	* Prototype version of IEM_CIMPL_DEF_4.
2898	*/
2899	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
2900	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2901	a_Type2 a_Arg2, a_Type3 a_Arg3))
2902	/**
2903	* For calling a C instruction implementation function taking four extra
2904	* arguments.
2905	*
2906	* This special call macro adds default arguments to the call and allow us to
2907	* change these later.
2908	*
2909	* @param a_fn The name of the function.
2910	* @param a0 The name of the 1st argument.
2911	* @param a1 The name of the 2nd argument.
2912	* @param a2 The name of the 3rd argument.
2913	* @param a3 The name of the 4th argument.
2914	*/
2915	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
2916
2917
2918	/**
2919	* For typedef'ing or declaring a C instruction implementation function taking
2920	* five extra arguments.
2921	*
2922	* @param a_Name The name of the type.
2923	* @param a_Type0 The type of the 1st argument
2924	* @param a_Arg0 The name of the 1st argument.
2925	* @param a_Type1 The type of the 2nd argument.
2926	* @param a_Arg1 The name of the 2nd argument.
2927	* @param a_Type2 The type of the 3rd argument.
2928	* @param a_Arg2 The name of the 3rd argument.
2929	* @param a_Type3 The type of the 4th argument.
2930	* @param a_Arg3 The name of the 4th argument.
2931	* @param a_Type4 The type of the 5th argument.
2932	* @param a_Arg4 The name of the 5th argument.
2933	*/
2934	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2935	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
2936	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
2937	a_Type3 a_Arg3, a_Type4 a_Arg4))
2938	/**
2939	* For defining a C instruction implementation function taking five extra
2940	* arguments.
2941	*
2942	* @param a_Name The name of the function.
2943	* @param a_Type0 The type of the 1st argument
2944	* @param a_Arg0 The name of the 1st argument.
2945	* @param a_Type1 The type of the 2nd argument.
2946	* @param a_Arg1 The name of the 2nd argument.
2947	* @param a_Type2 The type of the 3rd argument.
2948	* @param a_Arg2 The name of the 3rd argument.
2949	* @param a_Type3 The type of the 4th argument.
2950	* @param a_Arg3 The name of the 4th argument.
2951	* @param a_Type4 The type of the 5th argument.
2952	* @param a_Arg4 The name of the 5th argument.
2953	*/
2954	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2955	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2956	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
2957	/**
2958	* Prototype version of IEM_CIMPL_DEF_5.
2959	*/
2960	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
2961	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
2962	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
2963	/**
2964	* For calling a C instruction implementation function taking five extra
2965	* arguments.
2966	*
2967	* This special call macro adds default arguments to the call and allow us to
2968	* change these later.
2969	*
2970	* @param a_fn The name of the function.
2971	* @param a0 The name of the 1st argument.
2972	* @param a1 The name of the 2nd argument.
2973	* @param a2 The name of the 3rd argument.
2974	* @param a3 The name of the 4th argument.
2975	* @param a4 The name of the 5th argument.
2976	*/
2977	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
2978
2979	/** @} */
2980
2981
2982	/** @name Opcode Decoder Function Types.
2983	* @{ */
2984
2985	/** @typedef PFNIEMOP
2986	* Pointer to an opcode decoder function.
2987	*/
2988
2989	/** @def FNIEMOP_DEF
2990	* Define an opcode decoder function.
2991	*
2992	* We're using macors for this so that adding and removing parameters as well as
2993	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
2994	*
2995	* @param a_Name The function name.
2996	*/
2997
2998	/** @typedef PFNIEMOPRM
2999	* Pointer to an opcode decoder function with RM byte.
3000	*/
3001
3002	/** @def FNIEMOPRM_DEF
3003	* Define an opcode decoder function with RM byte.
3004	*
3005	* We're using macors for this so that adding and removing parameters as well as
3006	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
3007	*
3008	* @param a_Name The function name.
3009	*/
3010
3011	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3012	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
3013	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3014	# define FNIEMOP_DEF(a_Name) \
3015	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
3016	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3017	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3018	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3019	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3020
3021	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3022	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
3023	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3024	# define FNIEMOP_DEF(a_Name) \
3025	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
3026	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3027	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
3028	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3029	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
3030
3031	#elif defined(__GNUC__)
3032	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3033	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3034	# define FNIEMOP_DEF(a_Name) \
3035	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
3036	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3037	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3038	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3039	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3040
3041	#else
3042	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3043	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3044	# define FNIEMOP_DEF(a_Name) \
3045	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
3046	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3047	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
3048	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3049	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
3050
3051	#endif
3052	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
3053
3054	/**
3055	* Call an opcode decoder function.
3056	*
3057	* We're using macors for this so that adding and removing parameters can be
3058	* done as we please. See FNIEMOP_DEF.
3059	*/
3060	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
3061
3062	/**
3063	* Call a common opcode decoder function taking one extra argument.
3064	*
3065	* We're using macors for this so that adding and removing parameters can be
3066	* done as we please. See FNIEMOP_DEF_1.
3067	*/
3068	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
3069
3070	/**
3071	* Call a common opcode decoder function taking one extra argument.
3072	*
3073	* We're using macors for this so that adding and removing parameters can be
3074	* done as we please. See FNIEMOP_DEF_1.
3075	*/
3076	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
3077	/** @} */
3078
3079
3080	/** @name Misc Helpers
3081	* @{ */
3082
3083	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
3084	* due to GCC lacking knowledge about the value range of a switch. */
3085	#define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3086
3087	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
3088	#define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
3089
3090	/**
3091	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3092	* occation.
3093	*/
3094	#ifdef LOG_ENABLED
3095	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3096	do { \
3097	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
3098	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3099	} while (0)
3100	#else
3101	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3102	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3103	#endif
3104
3105	/**
3106	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3107	* occation using the supplied logger statement.
3108	*
3109	* @param a_LoggerArgs What to log on failure.
3110	*/
3111	#ifdef LOG_ENABLED
3112	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3113	do { \
3114	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
3115	/LogFunc(a_LoggerArgs);/ \
3116	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3117	} while (0)
3118	#else
3119	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3120	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3121	#endif
3122
3123	/**
3124	* Check if we're currently executing in real or virtual 8086 mode.
3125	*
3126	* @returns @c true if it is, @c false if not.
3127	* @param a_pVCpu The IEM state of the current CPU.
3128	*/
3129	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (CPUMIsGuestInRealOrV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3130
3131	/**
3132	* Check if we're currently executing in virtual 8086 mode.
3133	*
3134	* @returns @c true if it is, @c false if not.
3135	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3136	*/
3137	#define IEM_IS_V86_MODE(a_pVCpu) (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3138
3139	/**
3140	* Check if we're currently executing in long mode.
3141	*
3142	* @returns @c true if it is, @c false if not.
3143	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3144	*/
3145	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
3146
3147	/**
3148	* Check if we're currently executing in a 64-bit code segment.
3149	*
3150	* @returns @c true if it is, @c false if not.
3151	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3152	*/
3153	#define IEM_IS_64BIT_CODE(a_pVCpu) (CPUMIsGuestIn64BitCodeEx(IEM_GET_CTX(a_pVCpu)))
3154
3155	/**
3156	* Check if we're currently executing in real mode.
3157	*
3158	* @returns @c true if it is, @c false if not.
3159	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3160	*/
3161	#define IEM_IS_REAL_MODE(a_pVCpu) (CPUMIsGuestInRealModeEx(IEM_GET_CTX(a_pVCpu)))
3162
3163	/**
3164	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
3165	* @returns PCCPUMFEATURES
3166	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3167	*/
3168	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
3169
3170	/**
3171	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
3172	* @returns PCCPUMFEATURES
3173	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3174	*/
3175	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
3176
3177	/**
3178	* Evaluates to true if we're presenting an Intel CPU to the guest.
3179	*/
3180	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
3181
3182	/**
3183	* Evaluates to true if we're presenting an AMD CPU to the guest.
3184	*/
3185	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
3186
3187	/**
3188	* Check if the address is canonical.
3189	*/
3190	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
3191
3192	/** Checks if the ModR/M byte is in register mode or not. */
3193	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
3194	/** Checks if the ModR/M byte is in memory mode or not. */
3195	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
3196
3197	/**
3198	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
3199	*
3200	* For use during decoding.
3201	*/
3202	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
3203	/**
3204	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
3205	*
3206	* For use during decoding.
3207	*/
3208	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
3209
3210	/**
3211	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
3212	*
3213	* For use during decoding.
3214	*/
3215	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
3216	/**
3217	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
3218	*
3219	* For use during decoding.
3220	*/
3221	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
3222
3223	/**
3224	* Gets the effective VEX.VVVV value.
3225	*
3226	* The 4th bit is ignored if not 64-bit code.
3227	* @returns effective V-register value.
3228	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3229	*/
3230	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
3231	((a_pVCpu)->iem.s.enmCpuMode == IEMMODE_64BIT ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
3232
3233
3234	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3235
3236	/**
3237	* Check if the guest has entered VMX root operation.
3238	*/
3239	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
3240
3241	/**
3242	* Check if the guest has entered VMX non-root operation.
3243	*/
3244	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(a_pVCpu)))
3245
3246	/**
3247	* Check if the nested-guest has the given Pin-based VM-execution control set.
3248	*/
3249	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) \
3250	(CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
3251
3252	/**
3253	* Check if the nested-guest has the given Processor-based VM-execution control set.
3254	*/
3255	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) \
3256	(CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
3257
3258	/**
3259	* Check if the nested-guest has the given Secondary Processor-based VM-execution
3260	* control set.
3261	*/
3262	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) \
3263	(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
3264
3265	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
3266	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
3267
3268	/** Whether a shadow VMCS is present for the given VCPU. */
3269	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3270
3271	/** Gets the VMXON region pointer. */
3272	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
3273
3274	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
3275	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
3276
3277	/** Whether a current VMCS is present for the given VCPU. */
3278	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3279
3280	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
3281	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
3282	do \
3283	{ \
3284	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
3285	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
3286	} while (0)
3287
3288	/** Clears any current VMCS for the given VCPU. */
3289	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
3290	do \
3291	{ \
3292	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
3293	} while (0)
3294
3295	/**
3296	* Invokes the VMX VM-exit handler for an instruction intercept.
3297	*/
3298	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
3299	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
3300
3301	/**
3302	* Invokes the VMX VM-exit handler for an instruction intercept where the
3303	* instruction provides additional VM-exit information.
3304	*/
3305	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
3306	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
3307
3308	/**
3309	* Invokes the VMX VM-exit handler for a task switch.
3310	*/
3311	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
3312	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
3313
3314	/**
3315	* Invokes the VMX VM-exit handler for MWAIT.
3316	*/
3317	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
3318	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
3319
3320	/**
3321	* Invokes the VMX VM-exit handler for EPT faults.
3322	*/
3323	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
3324	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
3325
3326	/**
3327	* Invokes the VMX VM-exit handler.
3328	*/
3329	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
3330	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
3331
3332	#else
3333	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
3334	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
3335	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
3336	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
3337	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
3338	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3339	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3340	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3341	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3342	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3343	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
3344
3345	#endif
3346
3347	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3348	/**
3349	* Check if an SVM control/instruction intercept is set.
3350	*/
3351	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
3352	(CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
3353
3354	/**
3355	* Check if an SVM read CRx intercept is set.
3356	*/
3357	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3358	(CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3359
3360	/**
3361	* Check if an SVM write CRx intercept is set.
3362	*/
3363	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3364	(CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3365
3366	/**
3367	* Check if an SVM read DRx intercept is set.
3368	*/
3369	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3370	(CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3371
3372	/**
3373	* Check if an SVM write DRx intercept is set.
3374	*/
3375	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3376	(CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3377
3378	/**
3379	* Check if an SVM exception intercept is set.
3380	*/
3381	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
3382	(CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
3383
3384	/**
3385	* Invokes the SVM \#VMEXIT handler for the nested-guest.
3386	*/
3387	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3388	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
3389
3390	/**
3391	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
3392	* corresponding decode assist information.
3393	*/
3394	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
3395	do \
3396	{ \
3397	uint64_t uExitInfo1; \
3398	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
3399	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
3400	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
3401	else \
3402	uExitInfo1 = 0; \
3403	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
3404	} while (0)
3405
3406	/** Check and handles SVM nested-guest instruction intercept and updates
3407	* NRIP if needed.
3408	*/
3409	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3410	do \
3411	{ \
3412	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
3413	{ \
3414	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3415	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
3416	} \
3417	} while (0)
3418
3419	/** Checks and handles SVM nested-guest CR0 read intercept. */
3420	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) \
3421	do \
3422	{ \
3423	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
3424	{ /* probably likely */ } \
3425	else \
3426	{ \
3427	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3428	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
3429	} \
3430	} while (0)
3431
3432	/**
3433	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
3434	*/
3435	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) \
3436	do { \
3437	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
3438	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), IEM_GET_INSTR_LEN(a_pVCpu)); \
3439	} while (0)
3440
3441	#else
3442	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
3443	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3444	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3445	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3446	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3447	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
3448	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
3449	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
3450	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3451	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3452	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) do { } while (0)
3453
3454	#endif
3455
3456	/** @} */
3457
3458
3459
3460	/**
3461	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
3462	*/
3463	typedef union IEMSELDESC
3464	{
3465	/** The legacy view. */
3466	X86DESC Legacy;
3467	/** The long mode view. */
3468	X86DESC64 Long;
3469	} IEMSELDESC;
3470	/** Pointer to a selector descriptor table entry. */
3471	typedef IEMSELDESC *PIEMSELDESC;
3472
3473	/** @name Raising Exceptions.
3474	* @{ */
3475	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
3476	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
3477
3478	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
3479	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3480	#ifdef IEM_WITH_SETJMP
3481	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
3482	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3483	#endif
3484	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
3485	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3486	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
3487	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
3488	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
3489	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3490	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
3491	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3492	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3493	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
3494	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3495	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3496	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3497	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3498	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3499	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3500	#ifdef IEM_WITH_SETJMP
3501	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3502	#endif
3503	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3504	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
3505	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3506	#ifdef IEM_WITH_SETJMP
3507	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3508	#endif
3509	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3510	#ifdef IEM_WITH_SETJMP
3511	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3512	#endif
3513	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3514	#ifdef IEM_WITH_SETJMP
3515	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3516	#endif
3517	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
3518	#ifdef IEM_WITH_SETJMP
3519	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
3520	#endif
3521	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu);
3522	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu);
3523	#ifdef IEM_WITH_SETJMP
3524	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3525	#endif
3526	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3527
3528	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
3529	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
3530	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
3531
3532	/**
3533	* Macro for calling iemCImplRaiseDivideError().
3534	*
3535	* This enables us to add/remove arguments and force different levels of
3536	* inlining as we wish.
3537	*
3538	* @return Strict VBox status code.
3539	*/
3540	#define IEMOP_RAISE_DIVIDE_ERROR() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseDivideError)
3541
3542	/**
3543	* Macro for calling iemCImplRaiseInvalidLockPrefix().
3544	*
3545	* This enables us to add/remove arguments and force different levels of
3546	* inlining as we wish.
3547	*
3548	* @return Strict VBox status code.
3549	*/
3550	#define IEMOP_RAISE_INVALID_LOCK_PREFIX() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidLockPrefix)
3551
3552	/**
3553	* Macro for calling iemCImplRaiseInvalidOpcode().
3554	*
3555	* This enables us to add/remove arguments and force different levels of
3556	* inlining as we wish.
3557	*
3558	* @return Strict VBox status code.
3559	*/
3560	#define IEMOP_RAISE_INVALID_OPCODE() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidOpcode)
3561	/** @} */
3562
3563	/** @name Register Access.
3564	* @{ */
3565	VBOXSTRICTRC iemRegRipRelativeJumpS8(PVMCPUCC pVCpu, int8_t offNextInstr) RT_NOEXCEPT;
3566	VBOXSTRICTRC iemRegRipRelativeJumpS16(PVMCPUCC pVCpu, int16_t offNextInstr) RT_NOEXCEPT;
3567	VBOXSTRICTRC iemRegRipRelativeJumpS32(PVMCPUCC pVCpu, int32_t offNextInstr) RT_NOEXCEPT;
3568	VBOXSTRICTRC iemRegRipJump(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
3569	/** @} */
3570
3571	/** @name FPU access and helpers.
3572	* @{ */
3573	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult) RT_NOEXCEPT;
3574	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3575	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult) RT_NOEXCEPT;
3576	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3577	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3578	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3579	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3580	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3581	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3582	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3583	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3584	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3585	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3586	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3587	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3588	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3589	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3590	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3591	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3592	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu) RT_NOEXCEPT;
3593	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3594	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu) RT_NOEXCEPT;
3595	void iemFpuStackPushOverflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3596	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3597	/** @} */
3598
3599	/** @name SSE+AVX SIMD access and helpers.
3600	* @{ */
3601	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
3602	/** @} */
3603
3604	/** @name Memory access.
3605	* @{ */
3606
3607	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
3608	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
3609	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
3610	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
3611	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
3612	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
3613	* Users include FXSAVE & FXRSTOR. */
3614	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
3615
3616	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
3617	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
3618	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3619	#ifndef IN_RING3
3620	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3621	#endif
3622	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
3623	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
3624	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3625	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
3626
3627	#ifdef IEM_WITH_CODE_TLB
3628	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) RT_NOEXCEPT;
3629	#else
3630	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
3631	#endif
3632	#ifdef IEM_WITH_SETJMP
3633	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3634	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3635	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3636	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3637	#else
3638	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
3639	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3640	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3641	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3642	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3643	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3644	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3645	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3646	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3647	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3648	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3649	#endif
3650
3651	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3652	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3653	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3654	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3655	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3656	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3657	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3658	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3659	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3660	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3661	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3662	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3663	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
3664	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
3665	#ifdef IEM_WITH_SETJMP
3666	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3667	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3668	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3669	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3670	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3671	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3672	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3673	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3674	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3675	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3676	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3677	#endif
3678
3679	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3680	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3681	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3682	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3683	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
3684
3685	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
3686	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
3687	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
3688	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
3689	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3690	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3691	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3692	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3693	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3694	#ifdef IEM_WITH_SETJMP
3695	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
3696	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
3697	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
3698	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
3699	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3700	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3701	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3702	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3703	#endif
3704
3705	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
3706	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
3707	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
3708	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
3709	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3710	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
3711	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3712	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3713	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3714	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3715	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
3716	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
3717	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
3718	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
3719	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
3720	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
3721	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
3722	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
3723	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3724	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3725	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3726	/** @} */
3727
3728	/** @name IEMAllCImpl.cpp
3729	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
3730	* @{ */
3731	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
3732	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
3733	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
3734	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
3735	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
3736	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
3737	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
3738	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
3739	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
3740	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
3741	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
3742	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
3743	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3744	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3745	IEM_CIMPL_PROTO_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3746	IEM_CIMPL_PROTO_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3747	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
3748	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
3749	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
3750	IEM_CIMPL_PROTO_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop);
3751	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
3752	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
3753	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
3754	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
3755	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
3756	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
3757	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
3758	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
3759	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
3760	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
3761	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
3762	IEM_CIMPL_PROTO_0(iemCImpl_sysret);
3763	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
3764	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
3765	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
3766	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
3767	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
3768	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
3769	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
3770	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
3771	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
3772	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
3773	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3774	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
3775	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3776	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
3777	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3778	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3779	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
3780	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3781	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3782	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
3783	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3784	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3785	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
3786	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
3787	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
3788	IEM_CIMPL_PROTO_0(iemCImpl_clts);
3789	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
3790	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
3791	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
3792	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
3793	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
3794	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
3795	IEM_CIMPL_PROTO_0(iemCImpl_invd);
3796	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
3797	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
3798	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
3799	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
3800	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
3801	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
3802	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
3803	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
3804	IEM_CIMPL_PROTO_1(iemCImpl_in_eAX_DX, uint8_t, cbReg);
3805	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
3806	IEM_CIMPL_PROTO_1(iemCImpl_out_DX_eAX, uint8_t, cbReg);
3807	IEM_CIMPL_PROTO_0(iemCImpl_cli);
3808	IEM_CIMPL_PROTO_0(iemCImpl_sti);
3809	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
3810	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
3811	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
3812	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
3813	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
3814	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
3815	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
3816	IEM_CIMPL_PROTO_0(iemCImpl_daa);
3817	IEM_CIMPL_PROTO_0(iemCImpl_das);
3818	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
3819	IEM_CIMPL_PROTO_0(iemCImpl_aas);
3820	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
3821	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
3822	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
3823	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
3824	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
3825	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
3826	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3827	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
3828	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3829	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3830	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3831	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
3832	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3833	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3834	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
3835	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3836	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3837	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
3838	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
3839	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
3840	IEM_CIMPL_PROTO_1(iemCImpl_fxch_underflow, uint8_t, iStReg);
3841	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop);
3842	/** @} */
3843
3844	/** @name IEMAllCImplStrInstr.cpp.h
3845	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
3846	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
3847	* @{ */
3848	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
3849	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
3850	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
3851	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
3852	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
3853	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
3854	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
3855	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
3856	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
3857	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3858	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3859
3860	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
3861	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
3862	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
3863	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
3864	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
3865	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
3866	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
3867	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
3868	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
3869	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3870	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3871
3872	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
3873	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
3874	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
3875	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
3876	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
3877	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
3878	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
3879	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
3880	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
3881	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3882	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
3883
3884
3885	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
3886	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
3887	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
3888	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
3889	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
3890	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
3891	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
3892	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
3893	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
3894	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3895	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3896
3897	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
3898	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
3899	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
3900	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
3901	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
3902	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
3903	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
3904	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
3905	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
3906	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3907	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3908
3909	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
3910	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
3911	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
3912	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
3913	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
3914	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
3915	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
3916	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
3917	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
3918	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3919	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3920
3921	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
3922	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
3923	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
3924	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
3925	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
3926	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
3927	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
3928	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
3929	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
3930	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3931	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
3932
3933
3934	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
3935	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
3936	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
3937	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
3938	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
3939	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
3940	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
3941	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
3942	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
3943	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3944	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3945
3946	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
3947	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
3948	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
3949	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
3950	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
3951	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
3952	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
3953	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
3954	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
3955	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3956	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3957
3958	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
3959	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
3960	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
3961	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
3962	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
3963	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
3964	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
3965	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
3966	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
3967	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3968	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3969
3970	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
3971	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
3972	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
3973	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
3974	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
3975	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
3976	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
3977	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
3978	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
3979	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3980	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
3981	/** @} */
3982
3983	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3984	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
3985	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
3986	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
3987	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
3988	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
3989	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
3990	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
3991	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
3992	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
3993	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
3994	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
3995	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
3996	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
3997	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3998	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
3999	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4000	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4001	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4002	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4003	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
4004	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
4005	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
4006	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
4007	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
4008	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
4009	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
4010	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
4011	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
4012	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
4013	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
4014	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
4015	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
4016	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
4017	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
4018	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4019	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4020	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4021	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
4022	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
4023	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
4024	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField);
4025	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
4026	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
4027	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
4028	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
4029	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
4030	#endif
4031
4032	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4033	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
4034	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4035	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
4036	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
4037	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite) RT_NOEXCEPT;
4038	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
4039	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
4040	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
4041	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
4042	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
4043	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
4044	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
4045	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
4046	#endif
4047
4048	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
4049	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
4050	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
4051
4052
4053	extern const PFNIEMOP g_apfnOneByteMap[256];
4054
4055	/** @} */
4056
4057	RT_C_DECLS_END
4058
4059	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
4060

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 96673

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