IEMInternal.h@ 97458

Last change on this file since 97458 was 97458, checked in by vboxsync, 2 years ago
VMM/IEM: Need to mark functions that may be involved in longjmps differently for Visual C++, otherwise they may end up in std::terminate during unwinding.
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1	/* $Id: IEMInternal.h 97458 2022-11-08 16:04:48Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41
42
43	RT_C_DECLS_BEGIN
44
45
46	/** @defgroup grp_iem_int Internals
47	* @ingroup grp_iem
48	* @internal
49	* @{
50	*/
51
52	/** For expanding symbol in slickedit and other products tagging and
53	* crossreferencing IEM symbols. */
54	#ifndef IEM_STATIC
55	# define IEM_STATIC static
56	#endif
57
58	/** @def IEM_WITH_SETJMP
59	* Enables alternative status code handling using setjmps.
60	*
61	* This adds a bit of expense via the setjmp() call since it saves all the
62	* non-volatile registers. However, it eliminates return code checks and allows
63	* for more optimal return value passing (return regs instead of stack buffer).
64	*/
65	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
66	# define IEM_WITH_SETJMP
67	#endif
68
69	/** For use with IEM function that may do a longjmp (when enabled).
70	*
71	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
72	* attribute. So, we indicate that function that may be part of a longjmp may
73	* throw "exceptions" and that the compiler should definitely not generate and
74	* std::terminate calling unwind code.
75	*
76	* Here is one example of this ending in std::terminate:
77	* @code{.txt}
78	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
79	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
80	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
81	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
82	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
83	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
84	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
85	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
86	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
87	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
88	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
89	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
90	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
91	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
92	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
93	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
94	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
95	@endcode
96	*/
97	#if defined(_MSC_VER) && defined(IEM_WITH_SETJMP)
98	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
99	#else
100	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
101	#endif
102
103	#define IEM_IMPLEMENTS_TASKSWITCH
104
105	/** @def IEM_WITH_3DNOW
106	* Includes the 3DNow decoding. */
107	#define IEM_WITH_3DNOW
108
109	/** @def IEM_WITH_THREE_0F_38
110	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
111	#define IEM_WITH_THREE_0F_38
112
113	/** @def IEM_WITH_THREE_0F_3A
114	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
115	#define IEM_WITH_THREE_0F_3A
116
117	/** @def IEM_WITH_VEX
118	* Includes the VEX decoding. */
119	#define IEM_WITH_VEX
120
121	/** @def IEM_CFG_TARGET_CPU
122	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
123	*
124	* By default we allow this to be configured by the user via the
125	* CPUM/GuestCpuName config string, but this comes at a slight cost during
126	* decoding. So, for applications of this code where there is no need to
127	* be dynamic wrt target CPU, just modify this define.
128	*/
129	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
130	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
131	#endif
132
133	//#define IEM_WITH_CODE_TLB // - work in progress
134	//#define IEM_WITH_DATA_TLB // - work in progress
135
136
137	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
138	* Use unaligned accesses instead of elaborate byte assembly. */
139	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
140	# define IEM_USE_UNALIGNED_DATA_ACCESS
141	#endif
142
143	//#define IEM_LOG_MEMORY_WRITES
144
145	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
146	/** Instruction statistics. */
147	typedef struct IEMINSTRSTATS
148	{
149	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
150	# include "IEMInstructionStatisticsTmpl.h"
151	# undef IEM_DO_INSTR_STAT
152	} IEMINSTRSTATS;
153	#else
154	struct IEMINSTRSTATS;
155	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
156	#endif
157	/** Pointer to IEM instruction statistics. */
158	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
159
160
161	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
162	* @{ */
163	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
164	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
165	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
166	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
167	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
168	/** Selects the right variant from a_aArray.
169	* pVCpu is implicit in the caller context. */
170	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
171	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
172	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
173	* be used because the host CPU does not support the operation. */
174	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
175	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
176	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
177	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
178	* into the two.
179	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
180	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
181	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
182	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
183	#else
184	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
185	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
186	#endif
187	/** @} */
188
189	/**
190	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
191	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
192	*
193	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
194	* indicator.
195	*
196	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
197	*/
198	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
199	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
200	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
201	#else
202	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
203	#endif
204
205
206	/**
207	* Extended operand mode that includes a representation of 8-bit.
208	*
209	* This is used for packing down modes when invoking some C instruction
210	* implementations.
211	*/
212	typedef enum IEMMODEX
213	{
214	IEMMODEX_16BIT = IEMMODE_16BIT,
215	IEMMODEX_32BIT = IEMMODE_32BIT,
216	IEMMODEX_64BIT = IEMMODE_64BIT,
217	IEMMODEX_8BIT
218	} IEMMODEX;
219	AssertCompileSize(IEMMODEX, 4);
220
221
222	/**
223	* Branch types.
224	*/
225	typedef enum IEMBRANCH
226	{
227	IEMBRANCH_JUMP = 1,
228	IEMBRANCH_CALL,
229	IEMBRANCH_TRAP,
230	IEMBRANCH_SOFTWARE_INT,
231	IEMBRANCH_HARDWARE_INT
232	} IEMBRANCH;
233	AssertCompileSize(IEMBRANCH, 4);
234
235
236	/**
237	* INT instruction types.
238	*/
239	typedef enum IEMINT
240	{
241	/** INT n instruction (opcode 0xcd imm). */
242	IEMINT_INTN = 0,
243	/** Single byte INT3 instruction (opcode 0xcc). */
244	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
245	/** Single byte INTO instruction (opcode 0xce). */
246	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
247	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
248	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
249	} IEMINT;
250	AssertCompileSize(IEMINT, 4);
251
252
253	/**
254	* A FPU result.
255	*/
256	typedef struct IEMFPURESULT
257	{
258	/** The output value. */
259	RTFLOAT80U r80Result;
260	/** The output status. */
261	uint16_t FSW;
262	} IEMFPURESULT;
263	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
264	/** Pointer to a FPU result. */
265	typedef IEMFPURESULT *PIEMFPURESULT;
266	/** Pointer to a const FPU result. */
267	typedef IEMFPURESULT const *PCIEMFPURESULT;
268
269
270	/**
271	* A FPU result consisting of two output values and FSW.
272	*/
273	typedef struct IEMFPURESULTTWO
274	{
275	/** The first output value. */
276	RTFLOAT80U r80Result1;
277	/** The output status. */
278	uint16_t FSW;
279	/** The second output value. */
280	RTFLOAT80U r80Result2;
281	} IEMFPURESULTTWO;
282	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
283	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
284	/** Pointer to a FPU result consisting of two output values and FSW. */
285	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
286	/** Pointer to a const FPU result consisting of two output values and FSW. */
287	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
288
289
290	/**
291	* IEM TLB entry.
292	*
293	* Lookup assembly:
294	* @code{.asm}
295	; Calculate tag.
296	mov rax, [VA]
297	shl rax, 16
298	shr rax, 16 + X86_PAGE_SHIFT
299	or rax, [uTlbRevision]
300
301	; Do indexing.
302	movzx ecx, al
303	lea rcx, [pTlbEntries + rcx]
304
305	; Check tag.
306	cmp [rcx + IEMTLBENTRY.uTag], rax
307	jne .TlbMiss
308
309	; Check access.
310	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
311	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
312	cmp rax, [uTlbPhysRev]
313	jne .TlbMiss
314
315	; Calc address and we're done.
316	mov eax, X86_PAGE_OFFSET_MASK
317	and eax, [VA]
318	or rax, [rcx + IEMTLBENTRY.pMappingR3]
319	%ifdef VBOX_WITH_STATISTICS
320	inc qword [cTlbHits]
321	%endif
322	jmp .Done
323
324	.TlbMiss:
325	mov r8d, ACCESS_FLAGS
326	mov rdx, [VA]
327	mov rcx, [pVCpu]
328	call iemTlbTypeMiss
329	.Done:
330
331	@endcode
332	*
333	*/
334	typedef struct IEMTLBENTRY
335	{
336	/** The TLB entry tag.
337	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
338	* is ASSUMING a virtual address width of 48 bits.
339	*
340	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
341	*
342	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
343	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
344	* revision wraps around though, the tags needs to be zeroed.
345	*
346	* @note Try use SHRD instruction? After seeing
347	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
348	*
349	* @todo This will need to be reorganized for 57-bit wide virtual address and
350	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
351	* have to move the TLB entry versioning entirely to the
352	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
353	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
354	* consumed by PCID and ASID (12 + 6 = 18).
355	*/
356	uint64_t uTag;
357	/** Access flags and physical TLB revision.
358	*
359	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
360	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
361	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
362	* - Bit 3 - pgm phys/virt - not directly writable.
363	* - Bit 4 - pgm phys page - not directly readable.
364	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
365	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
366	* - Bit 7 - tlb entry - pMappingR3 member not valid.
367	* - Bits 63 thru 8 are used for the physical TLB revision number.
368	*
369	* We're using complemented bit meanings here because it makes it easy to check
370	* whether special action is required. For instance a user mode write access
371	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
372	* non-zero result would mean special handling needed because either it wasn't
373	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
374	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
375	* need to check any PTE flag.
376	*/
377	uint64_t fFlagsAndPhysRev;
378	/** The guest physical page address. */
379	uint64_t GCPhys;
380	/** Pointer to the ring-3 mapping. */
381	R3PTRTYPE(uint8_t *) pbMappingR3;
382	#if HC_ARCH_BITS == 32
383	uint32_t u32Padding1;
384	#endif
385	} IEMTLBENTRY;
386	AssertCompileSize(IEMTLBENTRY, 32);
387	/** Pointer to an IEM TLB entry. */
388	typedef IEMTLBENTRY *PIEMTLBENTRY;
389
390	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
391	* @{ */
392	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
393	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
394	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
395	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
396	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
397	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
398	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
399	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
400	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
401	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
402	/** @} */
403
404
405	/**
406	* An IEM TLB.
407	*
408	* We've got two of these, one for data and one for instructions.
409	*/
410	typedef struct IEMTLB
411	{
412	/** The TLB entries.
413	* We've choosen 256 because that way we can obtain the result directly from a
414	* 8-bit register without an additional AND instruction. */
415	IEMTLBENTRY aEntries[256];
416	/** The TLB revision.
417	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
418	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
419	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
420	* (The revision zero indicates an invalid TLB entry.)
421	*
422	* The initial value is choosen to cause an early wraparound. */
423	uint64_t uTlbRevision;
424	/** The TLB physical address revision - shadow of PGM variable.
425	*
426	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
427	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
428	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
429	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
430	*
431	* The initial value is choosen to cause an early wraparound. */
432	uint64_t volatile uTlbPhysRev;
433
434	/* Statistics: */
435
436	/** TLB hits (VBOX_WITH_STATISTICS only). */
437	uint64_t cTlbHits;
438	/** TLB misses. */
439	uint32_t cTlbMisses;
440	/** Slow read path. */
441	uint32_t cTlbSlowReadPath;
442	#if 0
443	/** TLB misses because of tag mismatch. */
444	uint32_t cTlbMissesTag;
445	/** TLB misses because of virtual access violation. */
446	uint32_t cTlbMissesVirtAccess;
447	/** TLB misses because of dirty bit. */
448	uint32_t cTlbMissesDirty;
449	/** TLB misses because of MMIO */
450	uint32_t cTlbMissesMmio;
451	/** TLB misses because of write access handlers. */
452	uint32_t cTlbMissesWriteHandler;
453	/** TLB misses because no r3(/r0) mapping. */
454	uint32_t cTlbMissesMapping;
455	#endif
456	/** Alignment padding. */
457	uint32_t au32Padding[3+5];
458	} IEMTLB;
459	AssertCompileSizeAlignment(IEMTLB, 64);
460	/** IEMTLB::uTlbRevision increment. */
461	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
462	/** IEMTLB::uTlbRevision mask. */
463	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
464	/** IEMTLB::uTlbPhysRev increment.
465	* @sa IEMTLBE_F_PHYS_REV */
466	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
467	/**
468	* Calculates the TLB tag for a virtual address.
469	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
470	* @param a_pTlb The TLB.
471	* @param a_GCPtr The virtual address.
472	*/
473	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
474	/**
475	* Calculates the TLB tag for a virtual address but without TLB revision.
476	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
477	* @param a_GCPtr The virtual address.
478	*/
479	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
480	/**
481	* Converts a TLB tag value into a TLB index.
482	* @returns Index into IEMTLB::aEntries.
483	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
484	*/
485	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
486	/**
487	* Converts a TLB tag value into a TLB index.
488	* @returns Index into IEMTLB::aEntries.
489	* @param a_pTlb The TLB.
490	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
491	*/
492	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
493
494
495	/**
496	* The per-CPU IEM state.
497	*/
498	typedef struct IEMCPU
499	{
500	/** Info status code that needs to be propagated to the IEM caller.
501	* This cannot be passed internally, as it would complicate all success
502	* checks within the interpreter making the code larger and almost impossible
503	* to get right. Instead, we'll store status codes to pass on here. Each
504	* source of these codes will perform appropriate sanity checks. */
505	int32_t rcPassUp; /* 0x00 */
506
507	/** The current CPU execution mode (CS). */
508	IEMMODE enmCpuMode; /* 0x04 */
509	/** The CPL. */
510	uint8_t uCpl; /* 0x05 */
511
512	/** Whether to bypass access handlers or not. */
513	bool fBypassHandlers; /* 0x06 */
514	/** Whether to disregard the lock prefix (implied or not). */
515	bool fDisregardLock; /* 0x07 */
516
517	/** @name Decoder state.
518	* @{ */
519	#ifdef IEM_WITH_CODE_TLB
520	/** The offset of the next instruction byte. */
521	uint32_t offInstrNextByte; /* 0x08 */
522	/** The number of bytes available at pbInstrBuf for the current instruction.
523	* This takes the max opcode length into account so that doesn't need to be
524	* checked separately. */
525	uint32_t cbInstrBuf; /* 0x0c */
526	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
527	* This can be NULL if the page isn't mappable for some reason, in which
528	* case we'll do fallback stuff.
529	*
530	* If we're executing an instruction from a user specified buffer,
531	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
532	* aligned pointer but pointer to the user data.
533	*
534	* For instructions crossing pages, this will start on the first page and be
535	* advanced to the next page by the time we've decoded the instruction. This
536	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
537	*/
538	uint8_t const pbInstrBuf; / 0x10 */
539	# if ARCH_BITS == 32
540	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
541	# endif
542	/** The program counter corresponding to pbInstrBuf.
543	* This is set to a non-canonical address when we need to invalidate it. */
544	uint64_t uInstrBufPc; /* 0x18 */
545	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
546	* This takes the CS segment limit into account. */
547	uint16_t cbInstrBufTotal; /* 0x20 */
548	/** Offset into pbInstrBuf of the first byte of the current instruction.
549	* Can be negative to efficiently handle cross page instructions. */
550	int16_t offCurInstrStart; /* 0x22 */
551
552	/** The prefix mask (IEM_OP_PRF_XXX). */
553	uint32_t fPrefixes; /* 0x24 */
554	/** The extra REX ModR/M register field bit (REX.R << 3). */
555	uint8_t uRexReg; /* 0x28 */
556	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
557	* (REX.B << 3). */
558	uint8_t uRexB; /* 0x29 */
559	/** The extra REX SIB index field bit (REX.X << 3). */
560	uint8_t uRexIndex; /* 0x2a */
561
562	/** The effective segment register (X86_SREG_XXX). */
563	uint8_t iEffSeg; /* 0x2b */
564
565	/** The offset of the ModR/M byte relative to the start of the instruction. */
566	uint8_t offModRm; /* 0x2c */
567	#else
568	/** The size of what has currently been fetched into abOpcode. */
569	uint8_t cbOpcode; /* 0x08 */
570	/** The current offset into abOpcode. */
571	uint8_t offOpcode; /* 0x09 */
572	/** The offset of the ModR/M byte relative to the start of the instruction. */
573	uint8_t offModRm; /* 0x0a */
574
575	/** The effective segment register (X86_SREG_XXX). */
576	uint8_t iEffSeg; /* 0x0b */
577
578	/** The prefix mask (IEM_OP_PRF_XXX). */
579	uint32_t fPrefixes; /* 0x0c */
580	/** The extra REX ModR/M register field bit (REX.R << 3). */
581	uint8_t uRexReg; /* 0x10 */
582	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
583	* (REX.B << 3). */
584	uint8_t uRexB; /* 0x11 */
585	/** The extra REX SIB index field bit (REX.X << 3). */
586	uint8_t uRexIndex; /* 0x12 */
587
588	#endif
589
590	/** The effective operand mode. */
591	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
592	/** The default addressing mode. */
593	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
594	/** The effective addressing mode. */
595	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
596	/** The default operand mode. */
597	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
598
599	/** Prefix index (VEX.pp) for two byte and three byte tables. */
600	uint8_t idxPrefix; /* 0x31, 0x17 */
601	/** 3rd VEX/EVEX/XOP register.
602	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
603	uint8_t uVex3rdReg; /* 0x32, 0x18 */
604	/** The VEX/EVEX/XOP length field. */
605	uint8_t uVexLength; /* 0x33, 0x19 */
606	/** Additional EVEX stuff. */
607	uint8_t fEvexStuff; /* 0x34, 0x1a */
608
609	/** Explicit alignment padding. */
610	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
611	/** The FPU opcode (FOP). */
612	uint16_t uFpuOpcode; /* 0x36, 0x1c */
613	#ifndef IEM_WITH_CODE_TLB
614	/** Explicit alignment padding. */
615	uint8_t abAlignment2b[2]; /* 0x1e */
616	#endif
617
618	/** The opcode bytes. */
619	uint8_t abOpcode[15]; /* 0x48, 0x20 */
620	/** Explicit alignment padding. */
621	#ifdef IEM_WITH_CODE_TLB
622	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
623	#else
624	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
625	#endif
626	/** @} */
627
628
629	/** The flags of the current exception / interrupt. */
630	uint32_t fCurXcpt; /* 0x48, 0x48 */
631	/** The current exception / interrupt. */
632	uint8_t uCurXcpt;
633	/** Exception / interrupt recursion depth. */
634	int8_t cXcptRecursions;
635
636	/** The number of active guest memory mappings. */
637	uint8_t cActiveMappings;
638	/** The next unused mapping index. */
639	uint8_t iNextMapping;
640	/** Records for tracking guest memory mappings. */
641	struct
642	{
643	/** The address of the mapped bytes. */
644	void *pv;
645	/** The access flags (IEM_ACCESS_XXX).
646	* IEM_ACCESS_INVALID if the entry is unused. */
647	uint32_t fAccess;
648	#if HC_ARCH_BITS == 64
649	uint32_t u32Alignment4; /*< Alignment padding. /
650	#endif
651	} aMemMappings[3];
652
653	/** Locking records for the mapped memory. */
654	union
655	{
656	PGMPAGEMAPLOCK Lock;
657	uint64_t au64Padding[2];
658	} aMemMappingLocks[3];
659
660	/** Bounce buffer info.
661	* This runs in parallel to aMemMappings. */
662	struct
663	{
664	/** The physical address of the first byte. */
665	RTGCPHYS GCPhysFirst;
666	/** The physical address of the second page. */
667	RTGCPHYS GCPhysSecond;
668	/** The number of bytes in the first page. */
669	uint16_t cbFirst;
670	/** The number of bytes in the second page. */
671	uint16_t cbSecond;
672	/** Whether it's unassigned memory. */
673	bool fUnassigned;
674	/** Explicit alignment padding. */
675	bool afAlignment5[3];
676	} aMemBbMappings[3];
677
678	/* Ensure that aBounceBuffers are aligned at a 32 byte boundrary. */
679	uint64_t abAlignment7[1];
680
681	/** Bounce buffer storage.
682	* This runs in parallel to aMemMappings and aMemBbMappings. */
683	struct
684	{
685	uint8_t ab[512];
686	} aBounceBuffers[3];
687
688
689	/** Pointer set jump buffer - ring-3 context. */
690	R3PTRTYPE(jmp_buf *) pJmpBufR3;
691	/** Pointer set jump buffer - ring-0 context. */
692	R0PTRTYPE(jmp_buf *) pJmpBufR0;
693
694	/** @todo Should move this near @a fCurXcpt later. */
695	/** The CR2 for the current exception / interrupt. */
696	uint64_t uCurXcptCr2;
697	/** The error code for the current exception / interrupt. */
698	uint32_t uCurXcptErr;
699
700	/** @name Statistics
701	* @{ */
702	/** The number of instructions we've executed. */
703	uint32_t cInstructions;
704	/** The number of potential exits. */
705	uint32_t cPotentialExits;
706	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
707	* This may contain uncommitted writes. */
708	uint32_t cbWritten;
709	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
710	uint32_t cRetInstrNotImplemented;
711	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
712	uint32_t cRetAspectNotImplemented;
713	/** Counts informational statuses returned (other than VINF_SUCCESS). */
714	uint32_t cRetInfStatuses;
715	/** Counts other error statuses returned. */
716	uint32_t cRetErrStatuses;
717	/** Number of times rcPassUp has been used. */
718	uint32_t cRetPassUpStatus;
719	/** Number of times RZ left with instruction commit pending for ring-3. */
720	uint32_t cPendingCommit;
721	/** Number of long jumps. */
722	uint32_t cLongJumps;
723	/** @} */
724
725	/** @name Target CPU information.
726	* @{ */
727	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
728	/** The target CPU. */
729	uint8_t uTargetCpu;
730	#else
731	uint8_t bTargetCpuPadding;
732	#endif
733	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
734	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
735	* native host support and the 2nd for when there is.
736	*
737	* The two values are typically indexed by a g_CpumHostFeatures bit.
738	*
739	* This is for instance used for the BSF & BSR instructions where AMD and
740	* Intel CPUs produce different EFLAGS. */
741	uint8_t aidxTargetCpuEflFlavour[2];
742
743	/** The CPU vendor. */
744	CPUMCPUVENDOR enmCpuVendor;
745	/** @} */
746
747	/** @name Host CPU information.
748	* @{ */
749	/** The CPU vendor. */
750	CPUMCPUVENDOR enmHostCpuVendor;
751	/** @} */
752
753	/** Counts RDMSR \#GP(0) LogRel(). */
754	uint8_t cLogRelRdMsr;
755	/** Counts WRMSR \#GP(0) LogRel(). */
756	uint8_t cLogRelWrMsr;
757	/** Alignment padding. */
758	uint8_t abAlignment8[42];
759
760	/** Data TLB.
761	* @remarks Must be 64-byte aligned. */
762	IEMTLB DataTlb;
763	/** Instruction TLB.
764	* @remarks Must be 64-byte aligned. */
765	IEMTLB CodeTlb;
766
767	/** Exception statistics. */
768	STAMCOUNTER aStatXcpts[32];
769	/** Interrupt statistics. */
770	uint32_t aStatInts[256];
771
772	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
773	/** Instruction statistics for ring-0/raw-mode. */
774	IEMINSTRSTATS StatsRZ;
775	/** Instruction statistics for ring-3. */
776	IEMINSTRSTATS StatsR3;
777	#endif
778	} IEMCPU;
779	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
780	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 8);
781	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 16);
782	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 32);
783	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
784	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
785	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
786
787	/** Pointer to the per-CPU IEM state. */
788	typedef IEMCPU *PIEMCPU;
789	/** Pointer to the const per-CPU IEM state. */
790	typedef IEMCPU const *PCIEMCPU;
791
792
793	/** @def IEM_GET_CTX
794	* Gets the guest CPU context for the calling EMT.
795	* @returns PCPUMCTX
796	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
797	*/
798	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
799
800	/** @def IEM_CTX_ASSERT
801	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
802	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
803	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
804	*/
805	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
806	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
807	(a_fExtrnMbz)))
808
809	/** @def IEM_CTX_IMPORT_RET
810	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
811	*
812	* Will call the keep to import the bits as needed.
813	*
814	* Returns on import failure.
815	*
816	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
817	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
818	*/
819	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
820	do { \
821	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
822	{ /* likely */ } \
823	else \
824	{ \
825	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
826	AssertRCReturn(rcCtxImport, rcCtxImport); \
827	} \
828	} while (0)
829
830	/** @def IEM_CTX_IMPORT_NORET
831	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
832	*
833	* Will call the keep to import the bits as needed.
834	*
835	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
836	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
837	*/
838	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
839	do { \
840	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
841	{ /* likely */ } \
842	else \
843	{ \
844	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
845	AssertLogRelRC(rcCtxImport); \
846	} \
847	} while (0)
848
849	/** @def IEM_CTX_IMPORT_JMP
850	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
851	*
852	* Will call the keep to import the bits as needed.
853	*
854	* Jumps on import failure.
855	*
856	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
857	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
858	*/
859	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
860	do { \
861	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
862	{ /* likely */ } \
863	else \
864	{ \
865	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
866	AssertRCStmt(rcCtxImport, longjmp(*pVCpu->iem.s.CTX_SUFF(pJmpBuf), rcCtxImport)); \
867	} \
868	} while (0)
869
870
871
872	/** @def IEM_GET_TARGET_CPU
873	* Gets the current IEMTARGETCPU value.
874	* @returns IEMTARGETCPU value.
875	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
876	*/
877	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
878	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
879	#else
880	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
881	#endif
882
883	/** @def IEM_GET_INSTR_LEN
884	* Gets the instruction length. */
885	#ifdef IEM_WITH_CODE_TLB
886	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
887	#else
888	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
889	#endif
890
891
892	/**
893	* Shared per-VM IEM data.
894	*/
895	typedef struct IEM
896	{
897	/** The VMX APIC-access page handler type. */
898	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
899	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
900	/** Set if the CPUID host call functionality is enabled. */
901	bool fCpuIdHostCall;
902	#endif
903	} IEM;
904
905
906
907	/** @name IEM_ACCESS_XXX - Access details.
908	* @{ */
909	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
910	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
911	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
912	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
913	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
914	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
915	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
916	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
917	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
918	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
919	/** The writes are partial, so if initialize the bounce buffer with the
920	* orignal RAM content. */
921	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
922	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
923	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
924	/** Bounce buffer with ring-3 write pending, first page. */
925	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
926	/** Bounce buffer with ring-3 write pending, second page. */
927	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
928	/** Not locked, accessed via the TLB. */
929	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
930	/** Valid bit mask. */
931	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
932	/** Shift count for the TLB flags (upper word). */
933	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
934
935	/** Read+write data alias. */
936	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
937	/** Write data alias. */
938	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
939	/** Read data alias. */
940	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
941	/** Instruction fetch alias. */
942	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
943	/** Stack write alias. */
944	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
945	/** Stack read alias. */
946	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
947	/** Stack read+write alias. */
948	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
949	/** Read system table alias. */
950	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
951	/** Read+write system table alias. */
952	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
953	/** @} */
954
955	/** @name Prefix constants (IEMCPU::fPrefixes)
956	* @{ */
957	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
958	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
959	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
960	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
961	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
962	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
963	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
964
965	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
966	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
967	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
968
969	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
970	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
971	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
972
973	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
974	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
975	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
976	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
977	/** Mask with all the REX prefix flags.
978	* This is generally for use when needing to undo the REX prefixes when they
979	* are followed legacy prefixes and therefore does not immediately preceed
980	* the first opcode byte.
981	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
982	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
983
984	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
985	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
986	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
987	/** @} */
988
989	/** @name IEMOPFORM_XXX - Opcode forms
990	* @note These are ORed together with IEMOPHINT_XXX.
991	* @{ */
992	/** ModR/M: reg, r/m */
993	#define IEMOPFORM_RM 0
994	/** ModR/M: reg, r/m (register) */
995	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
996	/** ModR/M: reg, r/m (memory) */
997	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
998	/** ModR/M: reg, r/m */
999	#define IEMOPFORM_RMI 1
1000	/** ModR/M: reg, r/m (register) */
1001	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1002	/** ModR/M: reg, r/m (memory) */
1003	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1004	/** ModR/M: r/m, reg */
1005	#define IEMOPFORM_MR 2
1006	/** ModR/M: r/m (register), reg */
1007	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1008	/** ModR/M: r/m (memory), reg */
1009	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1010	/** ModR/M: r/m only */
1011	#define IEMOPFORM_M 3
1012	/** ModR/M: r/m only (register). */
1013	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
1014	/** ModR/M: r/m only (memory). */
1015	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
1016	/** ModR/M: reg only */
1017	#define IEMOPFORM_R 4
1018
1019	/** VEX+ModR/M: reg, r/m */
1020	#define IEMOPFORM_VEX_RM 8
1021	/** VEX+ModR/M: reg, r/m (register) */
1022	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
1023	/** VEX+ModR/M: reg, r/m (memory) */
1024	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
1025	/** VEX+ModR/M: r/m, reg */
1026	#define IEMOPFORM_VEX_MR 9
1027	/** VEX+ModR/M: r/m (register), reg */
1028	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
1029	/** VEX+ModR/M: r/m (memory), reg */
1030	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
1031	/** VEX+ModR/M: r/m only */
1032	#define IEMOPFORM_VEX_M 10
1033	/** VEX+ModR/M: r/m only (register). */
1034	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
1035	/** VEX+ModR/M: r/m only (memory). */
1036	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
1037	/** VEX+ModR/M: reg only */
1038	#define IEMOPFORM_VEX_R 11
1039	/** VEX+ModR/M: reg, vvvv, r/m */
1040	#define IEMOPFORM_VEX_RVM 12
1041	/** VEX+ModR/M: reg, vvvv, r/m (register). */
1042	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
1043	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
1044	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
1045	/** VEX+ModR/M: reg, r/m, vvvv */
1046	#define IEMOPFORM_VEX_RMV 13
1047	/** VEX+ModR/M: reg, r/m, vvvv (register). */
1048	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
1049	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1050	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
1051	/** VEX+ModR/M: reg, r/m, imm8 */
1052	#define IEMOPFORM_VEX_RMI 14
1053	/** VEX+ModR/M: reg, r/m, imm8 (register). */
1054	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
1055	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1056	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1057	/** VEX+ModR/M: r/m, vvvv, reg */
1058	#define IEMOPFORM_VEX_MVR 15
1059	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1060	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1061	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1062	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1063	/** VEX+ModR/M+/n: vvvv, r/m */
1064	#define IEMOPFORM_VEX_VM 16
1065	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1066	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1067	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1068	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1069
1070	/** Fixed register instruction, no R/M. */
1071	#define IEMOPFORM_FIXED 32
1072
1073	/** The r/m is a register. */
1074	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1075	/** The r/m is a memory access. */
1076	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1077	/** @} */
1078
1079	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1080	* @note These are ORed together with IEMOPFORM_XXX.
1081	* @{ */
1082	/** Ignores the operand size prefix (66h). */
1083	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1084	/** Ignores REX.W (aka WIG). */
1085	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1086	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1087	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1088	/** Allowed with the lock prefix. */
1089	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1090	/** The VEX.L value is ignored (aka LIG). */
1091	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1092	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1093	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1094	/** The VEX.V value must be zero. */
1095	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1096
1097	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1098	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1099	/** @} */
1100
1101	/**
1102	* Possible hardware task switch sources.
1103	*/
1104	typedef enum IEMTASKSWITCH
1105	{
1106	/** Task switch caused by an interrupt/exception. */
1107	IEMTASKSWITCH_INT_XCPT = 1,
1108	/** Task switch caused by a far CALL. */
1109	IEMTASKSWITCH_CALL,
1110	/** Task switch caused by a far JMP. */
1111	IEMTASKSWITCH_JUMP,
1112	/** Task switch caused by an IRET. */
1113	IEMTASKSWITCH_IRET
1114	} IEMTASKSWITCH;
1115	AssertCompileSize(IEMTASKSWITCH, 4);
1116
1117	/**
1118	* Possible CrX load (write) sources.
1119	*/
1120	typedef enum IEMACCESSCRX
1121	{
1122	/** CrX access caused by 'mov crX' instruction. */
1123	IEMACCESSCRX_MOV_CRX,
1124	/** CrX (CR0) write caused by 'lmsw' instruction. */
1125	IEMACCESSCRX_LMSW,
1126	/** CrX (CR0) write caused by 'clts' instruction. */
1127	IEMACCESSCRX_CLTS,
1128	/** CrX (CR0) read caused by 'smsw' instruction. */
1129	IEMACCESSCRX_SMSW
1130	} IEMACCESSCRX;
1131
1132	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1133	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1134	*
1135	* These flags provide further context to SLAT page-walk failures that could not be
1136	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1137	*
1138	* @{
1139	*/
1140	/** Translating a nested-guest linear address failed accessing a nested-guest
1141	* physical address. */
1142	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1143	/** Translating a nested-guest linear address failed accessing a
1144	* paging-structure entry or updating accessed/dirty bits. */
1145	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1146	/** @} */
1147
1148	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1149	# ifndef IN_RING3
1150	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1151	# endif
1152	#endif
1153
1154	/**
1155	* Indicates to the verifier that the given flag set is undefined.
1156	*
1157	* Can be invoked again to add more flags.
1158	*
1159	* This is a NOOP if the verifier isn't compiled in.
1160	*
1161	* @note We're temporarily keeping this until code is converted to new
1162	* disassembler style opcode handling.
1163	*/
1164	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1165
1166
1167	/** @def IEM_DECL_IMPL_TYPE
1168	* For typedef'ing an instruction implementation function.
1169	*
1170	* @param a_RetType The return type.
1171	* @param a_Name The name of the type.
1172	* @param a_ArgList The argument list enclosed in parentheses.
1173	*/
1174
1175	/** @def IEM_DECL_IMPL_DEF
1176	* For defining an instruction implementation function.
1177	*
1178	* @param a_RetType The return type.
1179	* @param a_Name The name of the type.
1180	* @param a_ArgList The argument list enclosed in parentheses.
1181	*/
1182
1183	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1184	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1185	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1186	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1187	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1188	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1189	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1190
1191	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1192	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1193	a_RetType (__fastcall a_Name) a_ArgList
1194	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1195	a_RetType __fastcall a_Name a_ArgList IEM_NOEXCEPT_MAY_LONGJMP
1196	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1197	a_RetType __fastcall a_Name a_ArgList IEM_NOEXCEPT_MAY_LONGJMP
1198
1199	#elif __cplusplus >= 201700 /* P0012R1 support */
1200	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1201	a_RetType (VBOXCALL a_Name) a_ArgList IEM_NOEXCEPT_MAY_LONGJMP
1202	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1203	a_RetType VBOXCALL a_Name a_ArgList IEM_NOEXCEPT_MAY_LONGJMP
1204	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1205	a_RetType VBOXCALL a_Name a_ArgList IEM_NOEXCEPT_MAY_LONGJMP
1206
1207	#else
1208	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1209	a_RetType (VBOXCALL a_Name) a_ArgList
1210	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1211	a_RetType VBOXCALL a_Name a_ArgList
1212	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1213	a_RetType VBOXCALL a_Name a_ArgList
1214
1215	#endif
1216
1217	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1218	RT_C_DECLS_BEGIN
1219	extern uint8_t const g_afParity[256];
1220	RT_C_DECLS_END
1221
1222
1223	/** @name Arithmetic assignment operations on bytes (binary).
1224	* @{ */
1225	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1226	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1227	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1228	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1229	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1230	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1231	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1232	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1233	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1234	/** @} */
1235
1236	/** @name Arithmetic assignment operations on words (binary).
1237	* @{ */
1238	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1239	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1240	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1241	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1242	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1243	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1244	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1245	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1246	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1247	/** @} */
1248
1249	/** @name Arithmetic assignment operations on double words (binary).
1250	* @{ */
1251	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1252	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1253	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1254	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1255	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1256	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1257	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1258	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1259	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1260	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1261	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1262	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1263	/** @} */
1264
1265	/** @name Arithmetic assignment operations on quad words (binary).
1266	* @{ */
1267	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1268	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1269	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1270	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1271	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1272	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1273	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1274	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1275	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1276	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1277	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1278	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1279	/** @} */
1280
1281	/** @name Compare operations (thrown in with the binary ops).
1282	* @{ */
1283	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1284	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1285	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1286	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1287	/** @} */
1288
1289	/** @name Test operations (thrown in with the binary ops).
1290	* @{ */
1291	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1292	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1293	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1294	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1295	/** @} */
1296
1297	/** @name Bit operations operations (thrown in with the binary ops).
1298	* @{ */
1299	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1300	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1301	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1302	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1303	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1304	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1305	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1306	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1307	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1308	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1309	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1310	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1311	/** @} */
1312
1313	/** @name Arithmetic three operand operations on double words (binary).
1314	* @{ */
1315	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
1316	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1317	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1318	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1319	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1320	/** @} */
1321
1322	/** @name Arithmetic three operand operations on quad words (binary).
1323	* @{ */
1324	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
1325	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1326	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1327	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1328	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1329	/** @} */
1330
1331	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1332	* @{ */
1333	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1334	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1335	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1336	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1337	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1338	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1339	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1340	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1341	/** @} */
1342
1343	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1344	* @{ */
1345	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1346	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1347	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1348	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1349	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1350	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1351	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1352	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1353	/** @} */
1354
1355	/** @name MULX 32-bit and 64-bit.
1356	* @{ */
1357	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
1358	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1359	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1360
1361	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
1362	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1363	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1364	/** @} */
1365
1366
1367	/** @name Exchange memory with register operations.
1368	* @{ */
1369	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1370	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1371	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1372	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1373	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1374	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1375	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1376	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1377	/** @} */
1378
1379	/** @name Exchange and add operations.
1380	* @{ */
1381	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1382	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1383	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1384	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1385	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1386	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1387	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1388	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1389	/** @} */
1390
1391	/** @name Compare and exchange.
1392	* @{ */
1393	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1394	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1395	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1396	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1397	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1398	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1399	#if ARCH_BITS == 32
1400	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1401	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1402	#else
1403	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1404	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1405	#endif
1406	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1407	uint32_t *pEFlags));
1408	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1409	uint32_t *pEFlags));
1410	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1411	uint32_t *pEFlags));
1412	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1413	uint32_t *pEFlags));
1414	#ifndef RT_ARCH_ARM64
1415	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1416	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1417	#endif
1418	/** @} */
1419
1420	/** @name Memory ordering
1421	* @{ */
1422	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1423	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1424	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1425	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1426	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1427	#ifndef RT_ARCH_ARM64
1428	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1429	#endif
1430	/** @} */
1431
1432	/** @name Double precision shifts
1433	* @{ */
1434	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1435	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1436	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1437	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1438	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1439	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1440	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1441	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1442	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1443	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1444	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1445	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1446	/** @} */
1447
1448
1449	/** @name Bit search operations (thrown in with the binary ops).
1450	* @{ */
1451	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1452	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1453	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1454	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1455	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1456	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1457	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1458	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1459	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1460	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
1461	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
1462	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
1463	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
1464	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
1465	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
1466	/** @} */
1467
1468	/** @name Signed multiplication operations (thrown in with the binary ops).
1469	* @{ */
1470	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1471	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1472	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1473	/** @} */
1474
1475	/** @name Arithmetic assignment operations on bytes (unary).
1476	* @{ */
1477	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1478	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1479	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1480	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1481	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1482	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1483	/** @} */
1484
1485	/** @name Arithmetic assignment operations on words (unary).
1486	* @{ */
1487	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1488	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1489	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1490	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1491	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1492	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1493	/** @} */
1494
1495	/** @name Arithmetic assignment operations on double words (unary).
1496	* @{ */
1497	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1498	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1499	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1500	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1501	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1502	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1503	/** @} */
1504
1505	/** @name Arithmetic assignment operations on quad words (unary).
1506	* @{ */
1507	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1508	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1509	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1510	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1511	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1512	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1513	/** @} */
1514
1515
1516	/** @name Shift operations on bytes (Group 2).
1517	* @{ */
1518	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1519	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1520	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1521	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1522	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1523	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1524	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1525	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1526	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1527	/** @} */
1528
1529	/** @name Shift operations on words (Group 2).
1530	* @{ */
1531	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1532	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1533	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1534	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1535	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1536	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1537	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1538	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1539	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1540	/** @} */
1541
1542	/** @name Shift operations on double words (Group 2).
1543	* @{ */
1544	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1545	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1546	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1547	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1548	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1549	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1550	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1551	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1552	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1553	/** @} */
1554
1555	/** @name Shift operations on words (Group 2).
1556	* @{ */
1557	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1558	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1559	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1560	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1561	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1562	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1563	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1564	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1565	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1566	/** @} */
1567
1568	/** @name Multiplication and division operations.
1569	* @{ */
1570	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1571	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1572	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1573	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1574	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1575	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1576
1577	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1578	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1579	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1580	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1581	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1582	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1583
1584	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1585	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1586	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1587	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1588	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1589	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1590
1591	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1592	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1593	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1594	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1595	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1596	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1597	/** @} */
1598
1599	/** @name Byte Swap.
1600	* @{ */
1601	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1602	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1603	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1604	/** @} */
1605
1606	/** @name Misc.
1607	* @{ */
1608	FNIEMAIMPLBINU16 iemAImpl_arpl;
1609	/** @} */
1610
1611	/** @name RDRAND and RDSEED
1612	* @{ */
1613	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
1614	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
1615	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
1616	typedef FNIEMAIMPLRDRANDSEEDU16 *FNIEMAIMPLPRDRANDSEEDU16;
1617	typedef FNIEMAIMPLRDRANDSEEDU32 *FNIEMAIMPLPRDRANDSEEDU32;
1618	typedef FNIEMAIMPLRDRANDSEEDU64 *FNIEMAIMPLPRDRANDSEEDU64;
1619
1620	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
1621	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
1622	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
1623	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
1624	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
1625	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
1626	/** @} */
1627
1628	/** @name FPU operations taking a 32-bit float argument
1629	* @{ */
1630	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1631	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1632	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1633
1634	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1635	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1636	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1637
1638	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1639	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1640	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1641	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1642	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1643	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1644	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1645
1646	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1647	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1648	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1649	/** @} */
1650
1651	/** @name FPU operations taking a 64-bit float argument
1652	* @{ */
1653	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1654	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1655	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
1656
1657	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1658	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1659	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1660
1661	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
1662	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1663	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1664	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1665	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1666	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1667	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1668
1669	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1670	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1671	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1672	/** @} */
1673
1674	/** @name FPU operations taking a 80-bit float argument
1675	* @{ */
1676	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1677	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1678	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1679	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1680	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1681	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1682	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1683	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1684	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1685	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1686	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1687	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1688
1689	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
1690	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
1691	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
1692
1693	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1694	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1695	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1696	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1697	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1698
1699	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1700	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1701	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1702	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1703	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1704
1705	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1706	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1707	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1708	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1709	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
1710	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1711	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1712	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
1713	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
1714
1715	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1716	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1717	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1718	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1719
1720	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1721	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1722	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1723	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1724	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1725	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1726	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1727	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1728	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1729
1730	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1731	PCRTFLOAT80U pr80Val));
1732	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1733	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
1734	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1735	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
1736
1737	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1738	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1739	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1740
1741	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
1742	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1743	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
1744
1745	/** @} */
1746
1747	/** @name FPU operations taking a 16-bit signed integer argument
1748	* @{ */
1749	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1750	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1751	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1752	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1753	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
1754	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
1755
1756	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1757	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1758	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1759	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1760	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1761	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1762
1763	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1764	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1765	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
1766	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
1767
1768	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1769	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
1770	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
1771	/** @} */
1772
1773	/** @name FPU operations taking a 32-bit signed integer argument
1774	* @{ */
1775	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1776	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1777	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1778	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1779	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
1780	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
1781
1782	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1783	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1784	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1785	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1786	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1787	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1788
1789	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1790	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1791	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
1792	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
1793
1794	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1795	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
1796	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
1797	/** @} */
1798
1799	/** @name FPU operations taking a 64-bit signed integer argument
1800	* @{ */
1801	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1802	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
1803	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
1804
1805	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1806	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
1807	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
1808	/** @} */
1809
1810
1811	/** Temporary type representing a 256-bit vector register. */
1812	typedef struct { uint64_t au64[4]; } IEMVMM256;
1813	/** Temporary type pointing to a 256-bit vector register. */
1814	typedef IEMVMM256 *PIEMVMM256;
1815	/** Temporary type pointing to a const 256-bit vector register. */
1816	typedef IEMVMM256 *PCIEMVMM256;
1817
1818
1819	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1820	* @{ */
1821	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
1822	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1823	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1824	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1825	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1826	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
1827	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1828	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
1829	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
1830	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
1831	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
1832	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
1833	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1834	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
1835	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1836	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
1837	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
1838	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
1839	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
1840	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
1841	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1842	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
1843	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
1844	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
1845	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
1846	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
1847	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
1848	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
1849	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
1850	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
1851	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
1852	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
1853	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
1854	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
1855	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
1856	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
1857	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
1858	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
1859	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
1860	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
1861	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
1862	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
1863	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
1864	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
1865	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
1866	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
1867	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
1868	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
1869	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
1870	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
1871	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
1872	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
1873	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
1874	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
1875	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
1876	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
1877	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
1878
1879	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
1880	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
1881	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1882	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
1883	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
1884	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
1885	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
1886	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
1887	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
1888	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
1889	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
1890	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
1891	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
1892	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
1893	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
1894	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
1895	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
1896	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
1897	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
1898	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
1899	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
1900	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
1901	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
1902	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
1903	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
1904	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
1905	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
1906	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
1907	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
1908	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
1909	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
1910	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
1911	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
1912	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
1913	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
1914	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
1915	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
1916	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
1917	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
1918	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
1919	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
1920	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
1921	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
1922	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
1923	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
1924	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
1925	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
1926	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
1927	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
1928	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
1929	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
1930	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
1931	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
1932	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
1933	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
1934	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
1935	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
1936
1937	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
1938	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
1939	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
1940	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
1941	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
1942	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
1943	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
1944	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
1945	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
1946	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
1947	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
1948	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
1949	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
1950	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
1951	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
1952	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
1953	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
1954	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
1955	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
1956	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
1957	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
1958	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
1959	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
1960	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
1961	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
1962	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
1963	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
1964	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
1965	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
1966	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
1967	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
1968	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
1969	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
1970	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
1971	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
1972	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
1973	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
1974	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
1975	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
1976	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
1977	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
1978	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
1979	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
1980	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
1981	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
1982	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
1983	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
1984	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
1985	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
1986	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
1987	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
1988	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
1989	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
1990	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
1991	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
1992	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
1993	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
1994
1995	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
1996	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
1997	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
1998	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
1999
2000	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
2001	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
2002	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
2003	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
2004	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
2005	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
2006	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
2007	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
2008	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
2009	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
2010	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
2011	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
2012	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
2013	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
2014	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
2015	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
2016	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
2017	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
2018	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
2019	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
2020	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
2021	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
2022	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
2023	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
2024	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
2025	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
2026	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
2027	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
2028	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
2029	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
2030	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
2031	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
2032	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
2033	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
2034	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
2035	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
2036	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
2037	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
2038	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
2039	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
2040	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
2041	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
2042	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
2043	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
2044	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
2045	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
2046	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
2047	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
2048	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
2049	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
2050	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
2051	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
2052	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
2053	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
2054	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
2055	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
2056	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
2057
2058	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
2059	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
2060	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
2061	/** @} */
2062
2063	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2064	* @{ */
2065	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2066	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2067	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2068	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2069	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2070	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2071	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2072	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2073	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2074	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2075
2076	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2077	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2078	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2079	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2080	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2081	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2082	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2083	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2084	/** @} */
2085
2086	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2087	* @{ */
2088	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2089	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2090	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2091	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2092	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2093	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2094	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2095	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2096	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2097	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2098	/** @} */
2099
2100	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2101	* @{ */
2102	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2103	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2104	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2105	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2106	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
2107	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2108	#ifndef IEM_WITHOUT_ASSEMBLY
2109	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2110	#endif
2111	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2112	/** @} */
2113
2114	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2115	* @{ */
2116	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2117	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2118	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2119	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2120	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2121	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2122	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2123	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2124	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2125	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2126	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2127	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2128	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2129	/** @} */
2130
2131	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2132	* @{ */
2133	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
2134	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2135	#ifndef IEM_WITHOUT_ASSEMBLY
2136	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2137	#endif
2138	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2139	/** @} */
2140
2141	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
2142	* @{ */
2143	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
2144	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
2145	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
2146	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
2147	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
2148	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
2149
2150	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
2151	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
2152	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
2153	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
2154	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
2155	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
2156
2157	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
2158	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
2159	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
2160	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
2161	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
2162	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
2163
2164	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
2165	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
2166	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
2167	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
2168	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
2169	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
2170	/** @} */
2171
2172
2173	/** @name Media (SSE/MMX/AVX) operation: Sort this later
2174	* @{ */
2175	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2176	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2177	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PRTUINT128U puDst, uint64_t uSrc));
2178
2179	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2180	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2181	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2182	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2183	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2184	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2185
2186	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2187	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2188	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2189	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2190	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2191
2192	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2193	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2194	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2195	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2196	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2197
2198	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2199	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2200	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2201	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2202	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2203
2204	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2205	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2206	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2207	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2208	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2209
2210	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2211	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2212	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2213	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2214	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2215
2216	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2217	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2218	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2219	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2220	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2221
2222	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2223	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2224	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2225	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2226	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2227
2228	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2229	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2230	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2231	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2232	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2233
2234	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2235	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2236	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2237	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2238	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2239
2240	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2241	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2242	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2243	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2244	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2245
2246	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2247	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2248	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2249	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2250	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2251
2252	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2253	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2254	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2255	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2256	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2257
2258	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2259	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2260	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2261	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2262	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2263
2264	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2265	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2266	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2267	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2268	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2269
2270	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2271	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2272
2273	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
2274	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
2275	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2276	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2277
2278	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
2279	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2280	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2281	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2282
2283	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2284	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2285	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2286	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2287	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2288
2289	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2290	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2291	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2292	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2293	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2294
2295
2296	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2297	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
2298	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2299	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
2300	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2301	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
2302
2303	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
2304	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
2305	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
2306	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
2307
2308	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
2309	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
2310	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
2311	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
2312
2313	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
2314	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
2315	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
2316	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
2317
2318	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
2319	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
2320	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
2321	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
2322	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
2323
2324	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
2325	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
2326	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
2327	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
2328	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
2329
2330	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
2331
2332	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
2333
2334
2335	typedef struct IEMPCMPISTRISRC
2336	{
2337	RTUINT128U uSrc1;
2338	RTUINT128U uSrc2;
2339	} IEMPCMPISTRISRC;
2340	typedef IEMPCMPISTRISRC *PIEMPCMPISTRISRC;
2341	typedef const IEMPCMPISTRISRC *PCIEMPCMPISTRISRC;
2342
2343	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpistri_u128,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRISRC pSrc, uint8_t bEvil));
2344	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpistri_u128_fallback,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRISRC pSrc, uint8_t bEvil));
2345
2346	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
2347	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
2348	/** @} */
2349
2350	/** @name Media Odds and Ends
2351	* @{ */
2352	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
2353	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
2354	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
2355	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
2356	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
2357	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
2358	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
2359	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
2360
2361	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
2362	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
2363	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
2364	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
2365
2366	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2367	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
2368	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2369	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
2370	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2371	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
2372	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2373	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
2374
2375	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
2376	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
2377
2378	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
2379	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
2380
2381	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
2382	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
2383
2384	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
2385	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
2386
2387	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
2388	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
2389	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
2390	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
2391
2392	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
2393	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
2394
2395	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
2396	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
2397	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
2398	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
2399
2400	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
2401	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
2402
2403
2404	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2405	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
2406
2407	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
2408	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
2409
2410	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
2411	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
2412
2413	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
2414	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
2415
2416	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
2417	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
2418
2419
2420	typedef struct IEMMEDIAF2XMMSRC
2421	{
2422	X86XMMREG uSrc1;
2423	X86XMMREG uSrc2;
2424	} IEMMEDIAF2XMMSRC;
2425	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
2426	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
2427
2428	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
2429	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
2430
2431	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
2432	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
2433	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
2434	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
2435
2436	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
2437	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
2438
2439	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
2440	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
2441
2442	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
2443	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
2444
2445	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
2446	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
2447
2448	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
2449	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
2450
2451	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
2452	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
2453
2454	/** @} */
2455
2456
2457	/** @name Function tables.
2458	* @{
2459	*/
2460
2461	/**
2462	* Function table for a binary operator providing implementation based on
2463	* operand size.
2464	*/
2465	typedef struct IEMOPBINSIZES
2466	{
2467	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
2468	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
2469	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
2470	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
2471	} IEMOPBINSIZES;
2472	/** Pointer to a binary operator function table. */
2473	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
2474
2475
2476	/**
2477	* Function table for a unary operator providing implementation based on
2478	* operand size.
2479	*/
2480	typedef struct IEMOPUNARYSIZES
2481	{
2482	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
2483	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
2484	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
2485	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
2486	} IEMOPUNARYSIZES;
2487	/** Pointer to a unary operator function table. */
2488	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
2489
2490
2491	/**
2492	* Function table for a shift operator providing implementation based on
2493	* operand size.
2494	*/
2495	typedef struct IEMOPSHIFTSIZES
2496	{
2497	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
2498	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
2499	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
2500	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
2501	} IEMOPSHIFTSIZES;
2502	/** Pointer to a shift operator function table. */
2503	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
2504
2505
2506	/**
2507	* Function table for a multiplication or division operation.
2508	*/
2509	typedef struct IEMOPMULDIVSIZES
2510	{
2511	PFNIEMAIMPLMULDIVU8 pfnU8;
2512	PFNIEMAIMPLMULDIVU16 pfnU16;
2513	PFNIEMAIMPLMULDIVU32 pfnU32;
2514	PFNIEMAIMPLMULDIVU64 pfnU64;
2515	} IEMOPMULDIVSIZES;
2516	/** Pointer to a multiplication or division operation function table. */
2517	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
2518
2519
2520	/**
2521	* Function table for a double precision shift operator providing implementation
2522	* based on operand size.
2523	*/
2524	typedef struct IEMOPSHIFTDBLSIZES
2525	{
2526	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
2527	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
2528	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
2529	} IEMOPSHIFTDBLSIZES;
2530	/** Pointer to a double precision shift function table. */
2531	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
2532
2533
2534	/**
2535	* Function table for media instruction taking two full sized media source
2536	* registers and one full sized destination register (AVX).
2537	*/
2538	typedef struct IEMOPMEDIAF3
2539	{
2540	PFNIEMAIMPLMEDIAF3U128 pfnU128;
2541	PFNIEMAIMPLMEDIAF3U256 pfnU256;
2542	} IEMOPMEDIAF3;
2543	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2544	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
2545
2546	/** @def IEMOPMEDIAF3_INIT_VARS_EX
2547	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2548	* given functions as initializers. For use in AVX functions where a pair of
2549	* functions are only used once and the function table need not be public. */
2550	#ifndef TST_IEM_CHECK_MC
2551	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2552	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2553	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2554	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2555	# else
2556	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2557	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2558	# endif
2559	#else
2560	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2561	#endif
2562	/** @def IEMOPMEDIAF3_INIT_VARS
2563	* Generate AVX function tables for the @a a_InstrNm instruction.
2564	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
2565	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
2566	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2567	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2568
2569	/**
2570	* Function table for media instruction taking two full sized media source
2571	* registers and one full sized destination register, but no additional state
2572	* (AVX).
2573	*/
2574	typedef struct IEMOPMEDIAOPTF3
2575	{
2576	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
2577	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
2578	} IEMOPMEDIAOPTF3;
2579	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2580	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
2581
2582	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
2583	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2584	* given functions as initializers. For use in AVX functions where a pair of
2585	* functions are only used once and the function table need not be public. */
2586	#ifndef TST_IEM_CHECK_MC
2587	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2588	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2589	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2590	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2591	# else
2592	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2593	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2594	# endif
2595	#else
2596	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2597	#endif
2598	/** @def IEMOPMEDIAOPTF3_INIT_VARS
2599	* Generate AVX function tables for the @a a_InstrNm instruction.
2600	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
2601	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
2602	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2603	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2604
2605	/**
2606	* Function table for media instruction taking one full sized media source
2607	* registers and one full sized destination register, but no additional state
2608	* (AVX).
2609	*/
2610	typedef struct IEMOPMEDIAOPTF2
2611	{
2612	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
2613	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
2614	} IEMOPMEDIAOPTF2;
2615	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
2616	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
2617
2618	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
2619	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2620	* given functions as initializers. For use in AVX functions where a pair of
2621	* functions are only used once and the function table need not be public. */
2622	#ifndef TST_IEM_CHECK_MC
2623	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2624	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2625	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2626	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2627	# else
2628	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2629	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2630	# endif
2631	#else
2632	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2633	#endif
2634	/** @def IEMOPMEDIAOPTF2_INIT_VARS
2635	* Generate AVX function tables for the @a a_InstrNm instruction.
2636	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
2637	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
2638	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2639	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2640
2641	/**
2642	* Function table for media instruction taking two full sized media source
2643	* registers and one full sized destination register and an 8-bit immediate, but no additional state
2644	* (AVX).
2645	*/
2646	typedef struct IEMOPMEDIAOPTF3IMM8
2647	{
2648	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
2649	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
2650	} IEMOPMEDIAOPTF3IMM8;
2651	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2652	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
2653
2654	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
2655	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2656	* given functions as initializers. For use in AVX functions where a pair of
2657	* functions are only used once and the function table need not be public. */
2658	#ifndef TST_IEM_CHECK_MC
2659	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2660	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2661	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2662	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2663	# else
2664	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2665	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2666	# endif
2667	#else
2668	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2669	#endif
2670	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
2671	* Generate AVX function tables for the @a a_InstrNm instruction.
2672	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
2673	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
2674	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2675	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2676	/** @} */
2677
2678
2679	/**
2680	* Function table for blend type instruction taking three full sized media source
2681	* registers and one full sized destination register, but no additional state
2682	* (AVX).
2683	*/
2684	typedef struct IEMOPBLENDOP
2685	{
2686	PFNIEMAIMPLAVXBLENDU128 pfnU128;
2687	PFNIEMAIMPLAVXBLENDU256 pfnU256;
2688	} IEMOPBLENDOP;
2689	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
2690	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
2691
2692	/** @def IEMOPBLENDOP_INIT_VARS_EX
2693	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2694	* given functions as initializers. For use in AVX functions where a pair of
2695	* functions are only used once and the function table need not be public. */
2696	#ifndef TST_IEM_CHECK_MC
2697	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2698	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2699	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2700	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2701	# else
2702	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2703	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2704	# endif
2705	#else
2706	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2707	#endif
2708	/** @def IEMOPBLENDOP_INIT_VARS
2709	* Generate AVX function tables for the @a a_InstrNm instruction.
2710	* @sa IEMOPBLENDOP_INIT_VARS_EX */
2711	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
2712	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2713	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2714
2715
2716	/** @name SSE/AVX single/double precision floating point operations.
2717	* @{ */
2718	/**
2719	* A SSE result.
2720	*/
2721	typedef struct IEMSSERESULT
2722	{
2723	/** The output value. */
2724	X86XMMREG uResult;
2725	/** The output status. */
2726	uint32_t MXCSR;
2727	} IEMSSERESULT;
2728	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
2729	/** Pointer to a SSE result. */
2730	typedef IEMSSERESULT *PIEMSSERESULT;
2731	/** Pointer to a const SSE result. */
2732	typedef IEMSSERESULT const *PCIEMSSERESULT;
2733
2734
2735	/**
2736	* A AVX128 result.
2737	*/
2738	typedef struct IEMAVX128RESULT
2739	{
2740	/** The output value. */
2741	X86XMMREG uResult;
2742	/** The output status. */
2743	uint32_t MXCSR;
2744	} IEMAVX128RESULT;
2745	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
2746	/** Pointer to a AVX128 result. */
2747	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
2748	/** Pointer to a const AVX128 result. */
2749	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
2750
2751
2752	/**
2753	* A AVX256 result.
2754	*/
2755	typedef struct IEMAVX256RESULT
2756	{
2757	/** The output value. */
2758	X86YMMREG uResult;
2759	/** The output status. */
2760	uint32_t MXCSR;
2761	} IEMAVX256RESULT;
2762	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
2763	/** Pointer to a AVX256 result. */
2764	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
2765	/** Pointer to a const AVX256 result. */
2766	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
2767
2768
2769	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2770	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
2771	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2772	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
2773	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2774	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
2775
2776	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2777	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
2778	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2779	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
2780	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2781	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
2782
2783	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
2784	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
2785
2786	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
2787	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
2788	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
2789	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
2790	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
2791	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
2792	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
2793	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
2794	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
2795	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
2796	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
2797	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
2798	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
2799	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
2800	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
2801	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
2802	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
2803	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
2804	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
2805	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
2806	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
2807	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
2808
2809	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
2810	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
2811	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
2812	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
2813	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
2814	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
2815
2816	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
2817	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
2818	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
2819	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
2820	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
2821	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
2822	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
2823	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
2824	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
2825	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
2826	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
2827	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
2828	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
2829	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
2830	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
2831	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
2832
2833	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
2834	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
2835	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
2836	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
2837	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
2838	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
2839	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
2840	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
2841	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
2842	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
2843	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
2844	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
2845	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
2846	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
2847	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
2848	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
2849	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
2850	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
2851	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
2852	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
2853	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
2854	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
2855
2856	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
2857	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
2858	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
2859	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
2860	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
2861	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
2862	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
2863	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
2864	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
2865	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
2866	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
2867	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
2868	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
2869	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
2870
2871	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
2872	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
2873	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
2874	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
2875	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
2876	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
2877	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
2878	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
2879	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
2880	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
2881	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
2882	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
2883	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
2884	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
2885	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
2886	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
2887	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
2888	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
2889	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
2890	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
2891	/** @} */
2892
2893	/** @name C instruction implementations for anything slightly complicated.
2894	* @{ */
2895
2896	/**
2897	* For typedef'ing or declaring a C instruction implementation function taking
2898	* no extra arguments.
2899	*
2900	* @param a_Name The name of the type.
2901	*/
2902	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
2903	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2904	/**
2905	* For defining a C instruction implementation function taking no extra
2906	* arguments.
2907	*
2908	* @param a_Name The name of the function
2909	*/
2910	# define IEM_CIMPL_DEF_0(a_Name) \
2911	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2912	/**
2913	* Prototype version of IEM_CIMPL_DEF_0.
2914	*/
2915	# define IEM_CIMPL_PROTO_0(a_Name) \
2916	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2917	/**
2918	* For calling a C instruction implementation function taking no extra
2919	* arguments.
2920	*
2921	* This special call macro adds default arguments to the call and allow us to
2922	* change these later.
2923	*
2924	* @param a_fn The name of the function.
2925	*/
2926	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
2927
2928	/**
2929	* For typedef'ing or declaring a C instruction implementation function taking
2930	* one extra argument.
2931	*
2932	* @param a_Name The name of the type.
2933	* @param a_Type0 The argument type.
2934	* @param a_Arg0 The argument name.
2935	*/
2936	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
2937	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2938	/**
2939	* For defining a C instruction implementation function taking one extra
2940	* argument.
2941	*
2942	* @param a_Name The name of the function
2943	* @param a_Type0 The argument type.
2944	* @param a_Arg0 The argument name.
2945	*/
2946	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
2947	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2948	/**
2949	* Prototype version of IEM_CIMPL_DEF_1.
2950	*/
2951	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
2952	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2953	/**
2954	* For calling a C instruction implementation function taking one extra
2955	* argument.
2956	*
2957	* This special call macro adds default arguments to the call and allow us to
2958	* change these later.
2959	*
2960	* @param a_fn The name of the function.
2961	* @param a0 The name of the 1st argument.
2962	*/
2963	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
2964
2965	/**
2966	* For typedef'ing or declaring a C instruction implementation function taking
2967	* two extra arguments.
2968	*
2969	* @param a_Name The name of the type.
2970	* @param a_Type0 The type of the 1st argument
2971	* @param a_Arg0 The name of the 1st argument.
2972	* @param a_Type1 The type of the 2nd argument.
2973	* @param a_Arg1 The name of the 2nd argument.
2974	*/
2975	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2976	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2977	/**
2978	* For defining a C instruction implementation function taking two extra
2979	* arguments.
2980	*
2981	* @param a_Name The name of the function.
2982	* @param a_Type0 The type of the 1st argument
2983	* @param a_Arg0 The name of the 1st argument.
2984	* @param a_Type1 The type of the 2nd argument.
2985	* @param a_Arg1 The name of the 2nd argument.
2986	*/
2987	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2988	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2989	/**
2990	* Prototype version of IEM_CIMPL_DEF_2.
2991	*/
2992	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
2993	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
2994	/**
2995	* For calling a C instruction implementation function taking two extra
2996	* arguments.
2997	*
2998	* This special call macro adds default arguments to the call and allow us to
2999	* change these later.
3000	*
3001	* @param a_fn The name of the function.
3002	* @param a0 The name of the 1st argument.
3003	* @param a1 The name of the 2nd argument.
3004	*/
3005	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
3006
3007	/**
3008	* For typedef'ing or declaring a C instruction implementation function taking
3009	* three extra arguments.
3010	*
3011	* @param a_Name The name of the type.
3012	* @param a_Type0 The type of the 1st argument
3013	* @param a_Arg0 The name of the 1st argument.
3014	* @param a_Type1 The type of the 2nd argument.
3015	* @param a_Arg1 The name of the 2nd argument.
3016	* @param a_Type2 The type of the 3rd argument.
3017	* @param a_Arg2 The name of the 3rd argument.
3018	*/
3019	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3020	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3021	/**
3022	* For defining a C instruction implementation function taking three extra
3023	* arguments.
3024	*
3025	* @param a_Name The name of the function.
3026	* @param a_Type0 The type of the 1st argument
3027	* @param a_Arg0 The name of the 1st argument.
3028	* @param a_Type1 The type of the 2nd argument.
3029	* @param a_Arg1 The name of the 2nd argument.
3030	* @param a_Type2 The type of the 3rd argument.
3031	* @param a_Arg2 The name of the 3rd argument.
3032	*/
3033	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3034	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3035	/**
3036	* Prototype version of IEM_CIMPL_DEF_3.
3037	*/
3038	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3039	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3040	/**
3041	* For calling a C instruction implementation function taking three extra
3042	* arguments.
3043	*
3044	* This special call macro adds default arguments to the call and allow us to
3045	* change these later.
3046	*
3047	* @param a_fn The name of the function.
3048	* @param a0 The name of the 1st argument.
3049	* @param a1 The name of the 2nd argument.
3050	* @param a2 The name of the 3rd argument.
3051	*/
3052	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
3053
3054
3055	/**
3056	* For typedef'ing or declaring a C instruction implementation function taking
3057	* four extra arguments.
3058	*
3059	* @param a_Name The name of the type.
3060	* @param a_Type0 The type of the 1st argument
3061	* @param a_Arg0 The name of the 1st argument.
3062	* @param a_Type1 The type of the 2nd argument.
3063	* @param a_Arg1 The name of the 2nd argument.
3064	* @param a_Type2 The type of the 3rd argument.
3065	* @param a_Arg2 The name of the 3rd argument.
3066	* @param a_Type3 The type of the 4th argument.
3067	* @param a_Arg3 The name of the 4th argument.
3068	*/
3069	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3070	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
3071	/**
3072	* For defining a C instruction implementation function taking four extra
3073	* arguments.
3074	*
3075	* @param a_Name The name of the function.
3076	* @param a_Type0 The type of the 1st argument
3077	* @param a_Arg0 The name of the 1st argument.
3078	* @param a_Type1 The type of the 2nd argument.
3079	* @param a_Arg1 The name of the 2nd argument.
3080	* @param a_Type2 The type of the 3rd argument.
3081	* @param a_Arg2 The name of the 3rd argument.
3082	* @param a_Type3 The type of the 4th argument.
3083	* @param a_Arg3 The name of the 4th argument.
3084	*/
3085	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3086	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3087	a_Type2 a_Arg2, a_Type3 a_Arg3))
3088	/**
3089	* Prototype version of IEM_CIMPL_DEF_4.
3090	*/
3091	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3092	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3093	a_Type2 a_Arg2, a_Type3 a_Arg3))
3094	/**
3095	* For calling a C instruction implementation function taking four extra
3096	* arguments.
3097	*
3098	* This special call macro adds default arguments to the call and allow us to
3099	* change these later.
3100	*
3101	* @param a_fn The name of the function.
3102	* @param a0 The name of the 1st argument.
3103	* @param a1 The name of the 2nd argument.
3104	* @param a2 The name of the 3rd argument.
3105	* @param a3 The name of the 4th argument.
3106	*/
3107	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
3108
3109
3110	/**
3111	* For typedef'ing or declaring a C instruction implementation function taking
3112	* five extra arguments.
3113	*
3114	* @param a_Name The name of the type.
3115	* @param a_Type0 The type of the 1st argument
3116	* @param a_Arg0 The name of the 1st argument.
3117	* @param a_Type1 The type of the 2nd argument.
3118	* @param a_Arg1 The name of the 2nd argument.
3119	* @param a_Type2 The type of the 3rd argument.
3120	* @param a_Arg2 The name of the 3rd argument.
3121	* @param a_Type3 The type of the 4th argument.
3122	* @param a_Arg3 The name of the 4th argument.
3123	* @param a_Type4 The type of the 5th argument.
3124	* @param a_Arg4 The name of the 5th argument.
3125	*/
3126	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3127	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
3128	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
3129	a_Type3 a_Arg3, a_Type4 a_Arg4))
3130	/**
3131	* For defining a C instruction implementation function taking five extra
3132	* arguments.
3133	*
3134	* @param a_Name The name of the function.
3135	* @param a_Type0 The type of the 1st argument
3136	* @param a_Arg0 The name of the 1st argument.
3137	* @param a_Type1 The type of the 2nd argument.
3138	* @param a_Arg1 The name of the 2nd argument.
3139	* @param a_Type2 The type of the 3rd argument.
3140	* @param a_Arg2 The name of the 3rd argument.
3141	* @param a_Type3 The type of the 4th argument.
3142	* @param a_Arg3 The name of the 4th argument.
3143	* @param a_Type4 The type of the 5th argument.
3144	* @param a_Arg4 The name of the 5th argument.
3145	*/
3146	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3147	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3148	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3149	/**
3150	* Prototype version of IEM_CIMPL_DEF_5.
3151	*/
3152	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3153	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3154	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3155	/**
3156	* For calling a C instruction implementation function taking five extra
3157	* arguments.
3158	*
3159	* This special call macro adds default arguments to the call and allow us to
3160	* change these later.
3161	*
3162	* @param a_fn The name of the function.
3163	* @param a0 The name of the 1st argument.
3164	* @param a1 The name of the 2nd argument.
3165	* @param a2 The name of the 3rd argument.
3166	* @param a3 The name of the 4th argument.
3167	* @param a4 The name of the 5th argument.
3168	*/
3169	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
3170
3171	/** @} */
3172
3173
3174	/** @name Opcode Decoder Function Types.
3175	* @{ */
3176
3177	/** @typedef PFNIEMOP
3178	* Pointer to an opcode decoder function.
3179	*/
3180
3181	/** @def FNIEMOP_DEF
3182	* Define an opcode decoder function.
3183	*
3184	* We're using macors for this so that adding and removing parameters as well as
3185	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
3186	*
3187	* @param a_Name The function name.
3188	*/
3189
3190	/** @typedef PFNIEMOPRM
3191	* Pointer to an opcode decoder function with RM byte.
3192	*/
3193
3194	/** @def FNIEMOPRM_DEF
3195	* Define an opcode decoder function with RM byte.
3196	*
3197	* We're using macors for this so that adding and removing parameters as well as
3198	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
3199	*
3200	* @param a_Name The function name.
3201	*/
3202
3203	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3204	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
3205	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3206	# define FNIEMOP_DEF(a_Name) \
3207	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
3208	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3209	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3210	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3211	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3212
3213	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3214	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
3215	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3216	# define FNIEMOP_DEF(a_Name) \
3217	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
3218	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3219	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
3220	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3221	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
3222
3223	#elif defined(__GNUC__)
3224	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3225	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3226	# define FNIEMOP_DEF(a_Name) \
3227	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
3228	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3229	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3230	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3231	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3232
3233	#else
3234	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3235	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3236	# define FNIEMOP_DEF(a_Name) \
3237	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) RT_NO_THROW_DEF
3238	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3239	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) RT_NO_THROW_DEF
3240	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3241	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) RT_NO_THROW_DEF
3242
3243	#endif
3244	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
3245
3246	/**
3247	* Call an opcode decoder function.
3248	*
3249	* We're using macors for this so that adding and removing parameters can be
3250	* done as we please. See FNIEMOP_DEF.
3251	*/
3252	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
3253
3254	/**
3255	* Call a common opcode decoder function taking one extra argument.
3256	*
3257	* We're using macors for this so that adding and removing parameters can be
3258	* done as we please. See FNIEMOP_DEF_1.
3259	*/
3260	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
3261
3262	/**
3263	* Call a common opcode decoder function taking one extra argument.
3264	*
3265	* We're using macors for this so that adding and removing parameters can be
3266	* done as we please. See FNIEMOP_DEF_1.
3267	*/
3268	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
3269	/** @} */
3270
3271
3272	/** @name Misc Helpers
3273	* @{ */
3274
3275	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
3276	* due to GCC lacking knowledge about the value range of a switch. */
3277	#if RT_CPLUSPLUS_PREREQ(202000)
3278	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3279	#else
3280	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3281	#endif
3282
3283	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
3284	#if RT_CPLUSPLUS_PREREQ(202000)
3285	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
3286	#else
3287	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
3288	#endif
3289
3290	/**
3291	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3292	* occation.
3293	*/
3294	#ifdef LOG_ENABLED
3295	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3296	do { \
3297	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
3298	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3299	} while (0)
3300	#else
3301	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3302	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3303	#endif
3304
3305	/**
3306	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3307	* occation using the supplied logger statement.
3308	*
3309	* @param a_LoggerArgs What to log on failure.
3310	*/
3311	#ifdef LOG_ENABLED
3312	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3313	do { \
3314	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
3315	/LogFunc(a_LoggerArgs);/ \
3316	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3317	} while (0)
3318	#else
3319	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3320	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3321	#endif
3322
3323	/**
3324	* Check if we're currently executing in real or virtual 8086 mode.
3325	*
3326	* @returns @c true if it is, @c false if not.
3327	* @param a_pVCpu The IEM state of the current CPU.
3328	*/
3329	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (CPUMIsGuestInRealOrV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3330
3331	/**
3332	* Check if we're currently executing in virtual 8086 mode.
3333	*
3334	* @returns @c true if it is, @c false if not.
3335	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3336	*/
3337	#define IEM_IS_V86_MODE(a_pVCpu) (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3338
3339	/**
3340	* Check if we're currently executing in long mode.
3341	*
3342	* @returns @c true if it is, @c false if not.
3343	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3344	*/
3345	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
3346
3347	/**
3348	* Check if we're currently executing in a 64-bit code segment.
3349	*
3350	* @returns @c true if it is, @c false if not.
3351	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3352	*/
3353	#define IEM_IS_64BIT_CODE(a_pVCpu) (CPUMIsGuestIn64BitCodeEx(IEM_GET_CTX(a_pVCpu)))
3354
3355	/**
3356	* Check if we're currently executing in real mode.
3357	*
3358	* @returns @c true if it is, @c false if not.
3359	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3360	*/
3361	#define IEM_IS_REAL_MODE(a_pVCpu) (CPUMIsGuestInRealModeEx(IEM_GET_CTX(a_pVCpu)))
3362
3363	/**
3364	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
3365	* @returns PCCPUMFEATURES
3366	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3367	*/
3368	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
3369
3370	/**
3371	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
3372	* @returns PCCPUMFEATURES
3373	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3374	*/
3375	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
3376
3377	/**
3378	* Evaluates to true if we're presenting an Intel CPU to the guest.
3379	*/
3380	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
3381
3382	/**
3383	* Evaluates to true if we're presenting an AMD CPU to the guest.
3384	*/
3385	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
3386
3387	/**
3388	* Check if the address is canonical.
3389	*/
3390	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
3391
3392	/** Checks if the ModR/M byte is in register mode or not. */
3393	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
3394	/** Checks if the ModR/M byte is in memory mode or not. */
3395	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
3396
3397	/**
3398	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
3399	*
3400	* For use during decoding.
3401	*/
3402	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
3403	/**
3404	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
3405	*
3406	* For use during decoding.
3407	*/
3408	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
3409
3410	/**
3411	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
3412	*
3413	* For use during decoding.
3414	*/
3415	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
3416	/**
3417	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
3418	*
3419	* For use during decoding.
3420	*/
3421	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
3422
3423	/**
3424	* Gets the effective VEX.VVVV value.
3425	*
3426	* The 4th bit is ignored if not 64-bit code.
3427	* @returns effective V-register value.
3428	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3429	*/
3430	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
3431	((a_pVCpu)->iem.s.enmCpuMode == IEMMODE_64BIT ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
3432
3433
3434	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3435
3436	/**
3437	* Check if the guest has entered VMX root operation.
3438	*/
3439	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
3440
3441	/**
3442	* Check if the guest has entered VMX non-root operation.
3443	*/
3444	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(a_pVCpu)))
3445
3446	/**
3447	* Check if the nested-guest has the given Pin-based VM-execution control set.
3448	*/
3449	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) \
3450	(CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
3451
3452	/**
3453	* Check if the nested-guest has the given Processor-based VM-execution control set.
3454	*/
3455	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) \
3456	(CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
3457
3458	/**
3459	* Check if the nested-guest has the given Secondary Processor-based VM-execution
3460	* control set.
3461	*/
3462	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) \
3463	(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
3464
3465	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
3466	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
3467
3468	/** Whether a shadow VMCS is present for the given VCPU. */
3469	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3470
3471	/** Gets the VMXON region pointer. */
3472	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
3473
3474	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
3475	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
3476
3477	/** Whether a current VMCS is present for the given VCPU. */
3478	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3479
3480	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
3481	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
3482	do \
3483	{ \
3484	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
3485	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
3486	} while (0)
3487
3488	/** Clears any current VMCS for the given VCPU. */
3489	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
3490	do \
3491	{ \
3492	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
3493	} while (0)
3494
3495	/**
3496	* Invokes the VMX VM-exit handler for an instruction intercept.
3497	*/
3498	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
3499	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
3500
3501	/**
3502	* Invokes the VMX VM-exit handler for an instruction intercept where the
3503	* instruction provides additional VM-exit information.
3504	*/
3505	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
3506	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
3507
3508	/**
3509	* Invokes the VMX VM-exit handler for a task switch.
3510	*/
3511	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
3512	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
3513
3514	/**
3515	* Invokes the VMX VM-exit handler for MWAIT.
3516	*/
3517	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
3518	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
3519
3520	/**
3521	* Invokes the VMX VM-exit handler for EPT faults.
3522	*/
3523	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
3524	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
3525
3526	/**
3527	* Invokes the VMX VM-exit handler.
3528	*/
3529	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
3530	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
3531
3532	#else
3533	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
3534	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
3535	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
3536	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
3537	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
3538	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3539	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3540	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3541	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3542	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3543	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
3544
3545	#endif
3546
3547	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3548	/**
3549	* Check if an SVM control/instruction intercept is set.
3550	*/
3551	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
3552	(CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
3553
3554	/**
3555	* Check if an SVM read CRx intercept is set.
3556	*/
3557	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3558	(CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3559
3560	/**
3561	* Check if an SVM write CRx intercept is set.
3562	*/
3563	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3564	(CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3565
3566	/**
3567	* Check if an SVM read DRx intercept is set.
3568	*/
3569	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3570	(CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3571
3572	/**
3573	* Check if an SVM write DRx intercept is set.
3574	*/
3575	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3576	(CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3577
3578	/**
3579	* Check if an SVM exception intercept is set.
3580	*/
3581	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
3582	(CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
3583
3584	/**
3585	* Invokes the SVM \#VMEXIT handler for the nested-guest.
3586	*/
3587	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3588	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
3589
3590	/**
3591	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
3592	* corresponding decode assist information.
3593	*/
3594	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
3595	do \
3596	{ \
3597	uint64_t uExitInfo1; \
3598	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
3599	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
3600	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
3601	else \
3602	uExitInfo1 = 0; \
3603	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
3604	} while (0)
3605
3606	/** Check and handles SVM nested-guest instruction intercept and updates
3607	* NRIP if needed.
3608	*/
3609	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3610	do \
3611	{ \
3612	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
3613	{ \
3614	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3615	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
3616	} \
3617	} while (0)
3618
3619	/** Checks and handles SVM nested-guest CR0 read intercept. */
3620	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) \
3621	do \
3622	{ \
3623	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
3624	{ /* probably likely */ } \
3625	else \
3626	{ \
3627	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3628	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
3629	} \
3630	} while (0)
3631
3632	/**
3633	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
3634	*/
3635	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) \
3636	do { \
3637	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
3638	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), IEM_GET_INSTR_LEN(a_pVCpu)); \
3639	} while (0)
3640
3641	#else
3642	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
3643	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3644	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3645	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3646	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3647	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
3648	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
3649	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
3650	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3651	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3652	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) do { } while (0)
3653
3654	#endif
3655
3656	/** @} */
3657
3658
3659
3660	/**
3661	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
3662	*/
3663	typedef union IEMSELDESC
3664	{
3665	/** The legacy view. */
3666	X86DESC Legacy;
3667	/** The long mode view. */
3668	X86DESC64 Long;
3669	} IEMSELDESC;
3670	/** Pointer to a selector descriptor table entry. */
3671	typedef IEMSELDESC *PIEMSELDESC;
3672
3673	/** @name Raising Exceptions.
3674	* @{ */
3675	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
3676	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
3677
3678	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
3679	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3680	#ifdef IEM_WITH_SETJMP
3681	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
3682	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
3683	#endif
3684	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
3685	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3686	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
3687	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
3688	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
3689	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3690	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
3691	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3692	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3693	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
3694	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3695	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3696	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3697	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3698	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3699	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3700	#ifdef IEM_WITH_SETJMP
3701	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3702	#endif
3703	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3704	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
3705	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3706	#ifdef IEM_WITH_SETJMP
3707	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
3708	#endif
3709	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3710	#ifdef IEM_WITH_SETJMP
3711	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
3712	#endif
3713	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3714	#ifdef IEM_WITH_SETJMP
3715	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
3716	#endif
3717	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
3718	#ifdef IEM_WITH_SETJMP
3719	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
3720	#endif
3721	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
3722	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3723	#ifdef IEM_WITH_SETJMP
3724	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3725	#endif
3726	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3727
3728	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
3729	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
3730	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
3731
3732	/**
3733	* Macro for calling iemCImplRaiseDivideError().
3734	*
3735	* This enables us to add/remove arguments and force different levels of
3736	* inlining as we wish.
3737	*
3738	* @return Strict VBox status code.
3739	*/
3740	#define IEMOP_RAISE_DIVIDE_ERROR() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseDivideError)
3741
3742	/**
3743	* Macro for calling iemCImplRaiseInvalidLockPrefix().
3744	*
3745	* This enables us to add/remove arguments and force different levels of
3746	* inlining as we wish.
3747	*
3748	* @return Strict VBox status code.
3749	*/
3750	#define IEMOP_RAISE_INVALID_LOCK_PREFIX() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidLockPrefix)
3751
3752	/**
3753	* Macro for calling iemCImplRaiseInvalidOpcode().
3754	*
3755	* This enables us to add/remove arguments and force different levels of
3756	* inlining as we wish.
3757	*
3758	* @return Strict VBox status code.
3759	*/
3760	#define IEMOP_RAISE_INVALID_OPCODE() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidOpcode)
3761	/** @} */
3762
3763	/** @name Register Access.
3764	* @{ */
3765	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
3766	IEMMODE enmEffOpSize) RT_NOEXCEPT;
3767	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
3768	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
3769	IEMMODE enmEffOpSize) RT_NOEXCEPT;
3770	VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
3771	VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
3772	VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
3773	/** @} */
3774
3775	/** @name FPU access and helpers.
3776	* @{ */
3777	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult) RT_NOEXCEPT;
3778	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3779	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult) RT_NOEXCEPT;
3780	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3781	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3782	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3783	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3784	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3785	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3786	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3787	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3788	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3789	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3790	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3791	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3792	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3793	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3794	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3795	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3796	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu) RT_NOEXCEPT;
3797	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3798	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu) RT_NOEXCEPT;
3799	void iemFpuStackPushOverflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3800	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3801	/** @} */
3802
3803	/** @name SSE+AVX SIMD access and helpers.
3804	* @{ */
3805	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
3806	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
3807	/** @} */
3808
3809	/** @name Memory access.
3810	* @{ */
3811
3812	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
3813	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
3814	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
3815	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
3816	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
3817	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
3818	* Users include FXSAVE & FXRSTOR. */
3819	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
3820
3821	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
3822	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
3823	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3824	#ifndef IN_RING3
3825	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3826	#endif
3827	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
3828	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
3829	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3830	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
3831
3832	#ifdef IEM_WITH_CODE_TLB
3833	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) RT_NOEXCEPT;
3834	#else
3835	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
3836	#endif
3837	#ifdef IEM_WITH_SETJMP
3838	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3839	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3840	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3841	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3842	#else
3843	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
3844	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3845	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3846	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3847	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3848	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3849	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3850	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3851	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3852	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3853	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3854	#endif
3855
3856	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3857	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3858	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3859	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3860	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3861	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3862	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3863	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3864	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3865	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3866	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3867	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3868	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
3869	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
3870	#ifdef IEM_WITH_SETJMP
3871	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3872	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3873	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3874	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3875	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3876	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3877	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3878	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3879	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3880	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3881	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3882	#endif
3883
3884	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3885	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3886	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3887	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3888	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
3889
3890	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
3891	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
3892	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
3893	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
3894	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3895	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3896	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3897	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3898	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3899	#ifdef IEM_WITH_SETJMP
3900	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
3901	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
3902	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
3903	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
3904	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
3905	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
3906	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
3907	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
3908	#endif
3909
3910	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
3911	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
3912	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
3913	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
3914	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3915	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
3916	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3917	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3918	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3919	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3920	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
3921	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
3922	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
3923	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
3924	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
3925	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
3926	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
3927	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
3928	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3929	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3930	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3931	/** @} */
3932
3933	/** @name IEMAllCImpl.cpp
3934	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
3935	* @{ */
3936	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
3937	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
3938	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
3939	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
3940	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
3941	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
3942	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
3943	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
3944	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
3945	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
3946	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
3947	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
3948	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3949	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3950	IEM_CIMPL_PROTO_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3951	IEM_CIMPL_PROTO_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3952	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
3953	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
3954	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
3955	IEM_CIMPL_PROTO_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop);
3956	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
3957	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
3958	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
3959	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
3960	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
3961	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
3962	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
3963	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
3964	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
3965	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
3966	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
3967	IEM_CIMPL_PROTO_0(iemCImpl_sysret);
3968	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
3969	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
3970	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
3971	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
3972	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
3973	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
3974	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
3975	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
3976	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
3977	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
3978	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3979	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
3980	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3981	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
3982	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3983	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3984	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
3985	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3986	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3987	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
3988	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
3989	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
3990	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
3991	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
3992	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
3993	IEM_CIMPL_PROTO_0(iemCImpl_clts);
3994	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
3995	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
3996	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
3997	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
3998	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
3999	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
4000	IEM_CIMPL_PROTO_0(iemCImpl_invd);
4001	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
4002	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
4003	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
4004	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
4005	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
4006	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
4007	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
4008	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
4009	IEM_CIMPL_PROTO_1(iemCImpl_in_eAX_DX, uint8_t, cbReg);
4010	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
4011	IEM_CIMPL_PROTO_1(iemCImpl_out_DX_eAX, uint8_t, cbReg);
4012	IEM_CIMPL_PROTO_0(iemCImpl_cli);
4013	IEM_CIMPL_PROTO_0(iemCImpl_sti);
4014	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
4015	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
4016	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
4017	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
4018	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
4019	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
4020	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
4021	IEM_CIMPL_PROTO_0(iemCImpl_daa);
4022	IEM_CIMPL_PROTO_0(iemCImpl_das);
4023	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
4024	IEM_CIMPL_PROTO_0(iemCImpl_aas);
4025	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
4026	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
4027	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
4028	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
4029	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
4030	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
4031	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4032	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
4033	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4034	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4035	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4036	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4037	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4038	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4039	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4040	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4041	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4042	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4043	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4044	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
4045	IEM_CIMPL_PROTO_1(iemCImpl_fxch_underflow, uint8_t, iStReg);
4046	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop);
4047	/** @} */
4048
4049	/** @name IEMAllCImplStrInstr.cpp.h
4050	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
4051	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
4052	* @{ */
4053	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
4054	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
4055	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
4056	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
4057	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
4058	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
4059	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
4060	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
4061	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
4062	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4063	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4064
4065	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
4066	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
4067	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
4068	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
4069	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
4070	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
4071	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
4072	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
4073	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
4074	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4075	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4076
4077	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
4078	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
4079	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
4080	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
4081	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
4082	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
4083	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
4084	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
4085	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
4086	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4087	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4088
4089
4090	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
4091	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
4092	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
4093	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
4094	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
4095	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
4096	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
4097	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
4098	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
4099	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4100	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4101
4102	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
4103	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
4104	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
4105	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
4106	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
4107	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
4108	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
4109	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
4110	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
4111	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4112	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4113
4114	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
4115	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
4116	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
4117	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
4118	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
4119	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
4120	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
4121	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
4122	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
4123	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4124	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4125
4126	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
4127	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
4128	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
4129	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
4130	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
4131	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
4132	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
4133	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
4134	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
4135	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4136	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4137
4138
4139	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
4140	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
4141	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
4142	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
4143	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
4144	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
4145	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
4146	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
4147	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
4148	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4149	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4150
4151	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
4152	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
4153	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
4154	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
4155	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
4156	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
4157	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
4158	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
4159	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
4160	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4161	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4162
4163	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
4164	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
4165	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
4166	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
4167	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
4168	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
4169	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
4170	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
4171	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
4172	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4173	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4174
4175	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
4176	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
4177	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
4178	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
4179	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
4180	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
4181	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
4182	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
4183	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
4184	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4185	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4186	/** @} */
4187
4188	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4189	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
4190	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
4191	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
4192	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
4193	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
4194	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4195	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
4196	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
4197	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
4198	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
4199	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
4200	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
4201	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
4202	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4203	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4204	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4205	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4206	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4207	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4208	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
4209	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
4210	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
4211	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
4212	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
4213	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
4214	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
4215	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
4216	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
4217	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
4218	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
4219	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
4220	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
4221	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
4222	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
4223	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4224	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4225	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4226	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
4227	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
4228	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
4229	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField);
4230	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
4231	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
4232	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
4233	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
4234	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
4235	#endif
4236
4237	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4238	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
4239	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4240	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
4241	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
4242	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite) RT_NOEXCEPT;
4243	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
4244	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
4245	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
4246	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
4247	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
4248	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
4249	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
4250	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
4251	#endif
4252
4253	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
4254	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
4255	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
4256
4257
4258	extern const PFNIEMOP g_apfnOneByteMap[256];
4259
4260	/** @} */
4261
4262	RT_C_DECLS_END
4263
4264	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
4265

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 97458

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