IEMInternal.h@ 97469

Last change on this file since 97469 was 97469, checked in by vboxsync, 2 years ago
VMM/IEM: Use try/throw/catch instead of setjmp/longjmp when compiling ring-3 with GCC or clang, it looks like it must be faster. bugref:9898
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1	/* $Id: IEMInternal.h 97469 2022-11-08 23:56:41Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41
42
43	RT_C_DECLS_BEGIN
44
45
46	/** @defgroup grp_iem_int Internals
47	* @ingroup grp_iem
48	* @internal
49	* @{
50	*/
51
52	/** For expanding symbol in slickedit and other products tagging and
53	* crossreferencing IEM symbols. */
54	#ifndef IEM_STATIC
55	# define IEM_STATIC static
56	#endif
57
58	/** @def IEM_WITH_SETJMP
59	* Enables alternative status code handling using setjmps.
60	*
61	* This adds a bit of expense via the setjmp() call since it saves all the
62	* non-volatile registers. However, it eliminates return code checks and allows
63	* for more optimal return value passing (return regs instead of stack buffer).
64	*/
65	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
66	# define IEM_WITH_SETJMP
67	#endif
68
69	/** @def IEM_WITH_THROW_CATCH
70	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
71	* mode code when IEM_WITH_SETJMP is in effect.
72	*
73	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
74	* setjmp/long resulted in bs2-test-1 running %3 faster all but on test result
75	* value improving by more than 1%. (Best out of three.)
76	*/
77	#if (defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| 0)) \
78	\|\| defined(DOXYGEN_RUNNING)
79	# define IEM_WITH_THROW_CATCH
80	#endif
81
82	/** @def IEM_DO_LONGJMP
83	*
84	* Wrapper around longjmp / throw.
85	*
86	* @param a_pVCpu The CPU handle.
87	* @param a_rc The status code jump back with / throw.
88	*/
89	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
90	# ifdef IEM_WITH_THROW_CATCH
91	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
92	# else
93	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
94	# endif
95	#endif
96
97	/** For use with IEM function that may do a longjmp (when enabled).
98	*
99	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
100	* attribute. So, we indicate that function that may be part of a longjmp may
101	* throw "exceptions" and that the compiler should definitely not generate and
102	* std::terminate calling unwind code.
103	*
104	* Here is one example of this ending in std::terminate:
105	* @code{.txt}
106	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
107	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
108	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
109	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
110	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
111	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
112	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
113	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
114	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
115	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
116	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
117	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
118	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
119	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
120	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
121	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
122	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
123	@endcode
124	*
125	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
126	*/
127	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
128	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
129	#else
130	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
131	#endif
132
133	#define IEM_IMPLEMENTS_TASKSWITCH
134
135	/** @def IEM_WITH_3DNOW
136	* Includes the 3DNow decoding. */
137	#define IEM_WITH_3DNOW
138
139	/** @def IEM_WITH_THREE_0F_38
140	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
141	#define IEM_WITH_THREE_0F_38
142
143	/** @def IEM_WITH_THREE_0F_3A
144	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
145	#define IEM_WITH_THREE_0F_3A
146
147	/** @def IEM_WITH_VEX
148	* Includes the VEX decoding. */
149	#define IEM_WITH_VEX
150
151	/** @def IEM_CFG_TARGET_CPU
152	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
153	*
154	* By default we allow this to be configured by the user via the
155	* CPUM/GuestCpuName config string, but this comes at a slight cost during
156	* decoding. So, for applications of this code where there is no need to
157	* be dynamic wrt target CPU, just modify this define.
158	*/
159	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
160	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
161	#endif
162
163	//#define IEM_WITH_CODE_TLB // - work in progress
164	//#define IEM_WITH_DATA_TLB // - work in progress
165
166
167	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
168	* Use unaligned accesses instead of elaborate byte assembly. */
169	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
170	# define IEM_USE_UNALIGNED_DATA_ACCESS
171	#endif
172
173	//#define IEM_LOG_MEMORY_WRITES
174
175	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
176	/** Instruction statistics. */
177	typedef struct IEMINSTRSTATS
178	{
179	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
180	# include "IEMInstructionStatisticsTmpl.h"
181	# undef IEM_DO_INSTR_STAT
182	} IEMINSTRSTATS;
183	#else
184	struct IEMINSTRSTATS;
185	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
186	#endif
187	/** Pointer to IEM instruction statistics. */
188	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
189
190
191	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
192	* @{ */
193	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
194	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
195	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
196	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
197	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
198	/** Selects the right variant from a_aArray.
199	* pVCpu is implicit in the caller context. */
200	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
201	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
202	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
203	* be used because the host CPU does not support the operation. */
204	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
205	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
206	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
207	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
208	* into the two.
209	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
210	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
211	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
212	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
213	#else
214	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
215	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
216	#endif
217	/** @} */
218
219	/**
220	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
221	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
222	*
223	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
224	* indicator.
225	*
226	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
227	*/
228	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
229	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
230	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
231	#else
232	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
233	#endif
234
235
236	/**
237	* Extended operand mode that includes a representation of 8-bit.
238	*
239	* This is used for packing down modes when invoking some C instruction
240	* implementations.
241	*/
242	typedef enum IEMMODEX
243	{
244	IEMMODEX_16BIT = IEMMODE_16BIT,
245	IEMMODEX_32BIT = IEMMODE_32BIT,
246	IEMMODEX_64BIT = IEMMODE_64BIT,
247	IEMMODEX_8BIT
248	} IEMMODEX;
249	AssertCompileSize(IEMMODEX, 4);
250
251
252	/**
253	* Branch types.
254	*/
255	typedef enum IEMBRANCH
256	{
257	IEMBRANCH_JUMP = 1,
258	IEMBRANCH_CALL,
259	IEMBRANCH_TRAP,
260	IEMBRANCH_SOFTWARE_INT,
261	IEMBRANCH_HARDWARE_INT
262	} IEMBRANCH;
263	AssertCompileSize(IEMBRANCH, 4);
264
265
266	/**
267	* INT instruction types.
268	*/
269	typedef enum IEMINT
270	{
271	/** INT n instruction (opcode 0xcd imm). */
272	IEMINT_INTN = 0,
273	/** Single byte INT3 instruction (opcode 0xcc). */
274	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
275	/** Single byte INTO instruction (opcode 0xce). */
276	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
277	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
278	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
279	} IEMINT;
280	AssertCompileSize(IEMINT, 4);
281
282
283	/**
284	* A FPU result.
285	*/
286	typedef struct IEMFPURESULT
287	{
288	/** The output value. */
289	RTFLOAT80U r80Result;
290	/** The output status. */
291	uint16_t FSW;
292	} IEMFPURESULT;
293	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
294	/** Pointer to a FPU result. */
295	typedef IEMFPURESULT *PIEMFPURESULT;
296	/** Pointer to a const FPU result. */
297	typedef IEMFPURESULT const *PCIEMFPURESULT;
298
299
300	/**
301	* A FPU result consisting of two output values and FSW.
302	*/
303	typedef struct IEMFPURESULTTWO
304	{
305	/** The first output value. */
306	RTFLOAT80U r80Result1;
307	/** The output status. */
308	uint16_t FSW;
309	/** The second output value. */
310	RTFLOAT80U r80Result2;
311	} IEMFPURESULTTWO;
312	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
313	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
314	/** Pointer to a FPU result consisting of two output values and FSW. */
315	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
316	/** Pointer to a const FPU result consisting of two output values and FSW. */
317	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
318
319
320	/**
321	* IEM TLB entry.
322	*
323	* Lookup assembly:
324	* @code{.asm}
325	; Calculate tag.
326	mov rax, [VA]
327	shl rax, 16
328	shr rax, 16 + X86_PAGE_SHIFT
329	or rax, [uTlbRevision]
330
331	; Do indexing.
332	movzx ecx, al
333	lea rcx, [pTlbEntries + rcx]
334
335	; Check tag.
336	cmp [rcx + IEMTLBENTRY.uTag], rax
337	jne .TlbMiss
338
339	; Check access.
340	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
341	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
342	cmp rax, [uTlbPhysRev]
343	jne .TlbMiss
344
345	; Calc address and we're done.
346	mov eax, X86_PAGE_OFFSET_MASK
347	and eax, [VA]
348	or rax, [rcx + IEMTLBENTRY.pMappingR3]
349	%ifdef VBOX_WITH_STATISTICS
350	inc qword [cTlbHits]
351	%endif
352	jmp .Done
353
354	.TlbMiss:
355	mov r8d, ACCESS_FLAGS
356	mov rdx, [VA]
357	mov rcx, [pVCpu]
358	call iemTlbTypeMiss
359	.Done:
360
361	@endcode
362	*
363	*/
364	typedef struct IEMTLBENTRY
365	{
366	/** The TLB entry tag.
367	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
368	* is ASSUMING a virtual address width of 48 bits.
369	*
370	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
371	*
372	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
373	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
374	* revision wraps around though, the tags needs to be zeroed.
375	*
376	* @note Try use SHRD instruction? After seeing
377	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
378	*
379	* @todo This will need to be reorganized for 57-bit wide virtual address and
380	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
381	* have to move the TLB entry versioning entirely to the
382	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
383	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
384	* consumed by PCID and ASID (12 + 6 = 18).
385	*/
386	uint64_t uTag;
387	/** Access flags and physical TLB revision.
388	*
389	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
390	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
391	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
392	* - Bit 3 - pgm phys/virt - not directly writable.
393	* - Bit 4 - pgm phys page - not directly readable.
394	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
395	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
396	* - Bit 7 - tlb entry - pMappingR3 member not valid.
397	* - Bits 63 thru 8 are used for the physical TLB revision number.
398	*
399	* We're using complemented bit meanings here because it makes it easy to check
400	* whether special action is required. For instance a user mode write access
401	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
402	* non-zero result would mean special handling needed because either it wasn't
403	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
404	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
405	* need to check any PTE flag.
406	*/
407	uint64_t fFlagsAndPhysRev;
408	/** The guest physical page address. */
409	uint64_t GCPhys;
410	/** Pointer to the ring-3 mapping. */
411	R3PTRTYPE(uint8_t *) pbMappingR3;
412	#if HC_ARCH_BITS == 32
413	uint32_t u32Padding1;
414	#endif
415	} IEMTLBENTRY;
416	AssertCompileSize(IEMTLBENTRY, 32);
417	/** Pointer to an IEM TLB entry. */
418	typedef IEMTLBENTRY *PIEMTLBENTRY;
419
420	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
421	* @{ */
422	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
423	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
424	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
425	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
426	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
427	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
428	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
429	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
430	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
431	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
432	/** @} */
433
434
435	/**
436	* An IEM TLB.
437	*
438	* We've got two of these, one for data and one for instructions.
439	*/
440	typedef struct IEMTLB
441	{
442	/** The TLB entries.
443	* We've choosen 256 because that way we can obtain the result directly from a
444	* 8-bit register without an additional AND instruction. */
445	IEMTLBENTRY aEntries[256];
446	/** The TLB revision.
447	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
448	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
449	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
450	* (The revision zero indicates an invalid TLB entry.)
451	*
452	* The initial value is choosen to cause an early wraparound. */
453	uint64_t uTlbRevision;
454	/** The TLB physical address revision - shadow of PGM variable.
455	*
456	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
457	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
458	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
459	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
460	*
461	* The initial value is choosen to cause an early wraparound. */
462	uint64_t volatile uTlbPhysRev;
463
464	/* Statistics: */
465
466	/** TLB hits (VBOX_WITH_STATISTICS only). */
467	uint64_t cTlbHits;
468	/** TLB misses. */
469	uint32_t cTlbMisses;
470	/** Slow read path. */
471	uint32_t cTlbSlowReadPath;
472	#if 0
473	/** TLB misses because of tag mismatch. */
474	uint32_t cTlbMissesTag;
475	/** TLB misses because of virtual access violation. */
476	uint32_t cTlbMissesVirtAccess;
477	/** TLB misses because of dirty bit. */
478	uint32_t cTlbMissesDirty;
479	/** TLB misses because of MMIO */
480	uint32_t cTlbMissesMmio;
481	/** TLB misses because of write access handlers. */
482	uint32_t cTlbMissesWriteHandler;
483	/** TLB misses because no r3(/r0) mapping. */
484	uint32_t cTlbMissesMapping;
485	#endif
486	/** Alignment padding. */
487	uint32_t au32Padding[3+5];
488	} IEMTLB;
489	AssertCompileSizeAlignment(IEMTLB, 64);
490	/** IEMTLB::uTlbRevision increment. */
491	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
492	/** IEMTLB::uTlbRevision mask. */
493	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
494	/** IEMTLB::uTlbPhysRev increment.
495	* @sa IEMTLBE_F_PHYS_REV */
496	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
497	/**
498	* Calculates the TLB tag for a virtual address.
499	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
500	* @param a_pTlb The TLB.
501	* @param a_GCPtr The virtual address.
502	*/
503	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
504	/**
505	* Calculates the TLB tag for a virtual address but without TLB revision.
506	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
507	* @param a_GCPtr The virtual address.
508	*/
509	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
510	/**
511	* Converts a TLB tag value into a TLB index.
512	* @returns Index into IEMTLB::aEntries.
513	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
514	*/
515	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
516	/**
517	* Converts a TLB tag value into a TLB index.
518	* @returns Index into IEMTLB::aEntries.
519	* @param a_pTlb The TLB.
520	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
521	*/
522	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
523
524
525	/**
526	* The per-CPU IEM state.
527	*/
528	typedef struct IEMCPU
529	{
530	/** Info status code that needs to be propagated to the IEM caller.
531	* This cannot be passed internally, as it would complicate all success
532	* checks within the interpreter making the code larger and almost impossible
533	* to get right. Instead, we'll store status codes to pass on here. Each
534	* source of these codes will perform appropriate sanity checks. */
535	int32_t rcPassUp; /* 0x00 */
536
537	/** The current CPU execution mode (CS). */
538	IEMMODE enmCpuMode; /* 0x04 */
539	/** The CPL. */
540	uint8_t uCpl; /* 0x05 */
541
542	/** Whether to bypass access handlers or not. */
543	bool fBypassHandlers; /* 0x06 */
544	/** Whether to disregard the lock prefix (implied or not). */
545	bool fDisregardLock; /* 0x07 */
546
547	/** @name Decoder state.
548	* @{ */
549	#ifdef IEM_WITH_CODE_TLB
550	/** The offset of the next instruction byte. */
551	uint32_t offInstrNextByte; /* 0x08 */
552	/** The number of bytes available at pbInstrBuf for the current instruction.
553	* This takes the max opcode length into account so that doesn't need to be
554	* checked separately. */
555	uint32_t cbInstrBuf; /* 0x0c */
556	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
557	* This can be NULL if the page isn't mappable for some reason, in which
558	* case we'll do fallback stuff.
559	*
560	* If we're executing an instruction from a user specified buffer,
561	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
562	* aligned pointer but pointer to the user data.
563	*
564	* For instructions crossing pages, this will start on the first page and be
565	* advanced to the next page by the time we've decoded the instruction. This
566	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
567	*/
568	uint8_t const pbInstrBuf; / 0x10 */
569	# if ARCH_BITS == 32
570	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
571	# endif
572	/** The program counter corresponding to pbInstrBuf.
573	* This is set to a non-canonical address when we need to invalidate it. */
574	uint64_t uInstrBufPc; /* 0x18 */
575	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
576	* This takes the CS segment limit into account. */
577	uint16_t cbInstrBufTotal; /* 0x20 */
578	/** Offset into pbInstrBuf of the first byte of the current instruction.
579	* Can be negative to efficiently handle cross page instructions. */
580	int16_t offCurInstrStart; /* 0x22 */
581
582	/** The prefix mask (IEM_OP_PRF_XXX). */
583	uint32_t fPrefixes; /* 0x24 */
584	/** The extra REX ModR/M register field bit (REX.R << 3). */
585	uint8_t uRexReg; /* 0x28 */
586	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
587	* (REX.B << 3). */
588	uint8_t uRexB; /* 0x29 */
589	/** The extra REX SIB index field bit (REX.X << 3). */
590	uint8_t uRexIndex; /* 0x2a */
591
592	/** The effective segment register (X86_SREG_XXX). */
593	uint8_t iEffSeg; /* 0x2b */
594
595	/** The offset of the ModR/M byte relative to the start of the instruction. */
596	uint8_t offModRm; /* 0x2c */
597	#else
598	/** The size of what has currently been fetched into abOpcode. */
599	uint8_t cbOpcode; /* 0x08 */
600	/** The current offset into abOpcode. */
601	uint8_t offOpcode; /* 0x09 */
602	/** The offset of the ModR/M byte relative to the start of the instruction. */
603	uint8_t offModRm; /* 0x0a */
604
605	/** The effective segment register (X86_SREG_XXX). */
606	uint8_t iEffSeg; /* 0x0b */
607
608	/** The prefix mask (IEM_OP_PRF_XXX). */
609	uint32_t fPrefixes; /* 0x0c */
610	/** The extra REX ModR/M register field bit (REX.R << 3). */
611	uint8_t uRexReg; /* 0x10 */
612	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
613	* (REX.B << 3). */
614	uint8_t uRexB; /* 0x11 */
615	/** The extra REX SIB index field bit (REX.X << 3). */
616	uint8_t uRexIndex; /* 0x12 */
617
618	#endif
619
620	/** The effective operand mode. */
621	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
622	/** The default addressing mode. */
623	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
624	/** The effective addressing mode. */
625	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
626	/** The default operand mode. */
627	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
628
629	/** Prefix index (VEX.pp) for two byte and three byte tables. */
630	uint8_t idxPrefix; /* 0x31, 0x17 */
631	/** 3rd VEX/EVEX/XOP register.
632	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
633	uint8_t uVex3rdReg; /* 0x32, 0x18 */
634	/** The VEX/EVEX/XOP length field. */
635	uint8_t uVexLength; /* 0x33, 0x19 */
636	/** Additional EVEX stuff. */
637	uint8_t fEvexStuff; /* 0x34, 0x1a */
638
639	/** Explicit alignment padding. */
640	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
641	/** The FPU opcode (FOP). */
642	uint16_t uFpuOpcode; /* 0x36, 0x1c */
643	#ifndef IEM_WITH_CODE_TLB
644	/** Explicit alignment padding. */
645	uint8_t abAlignment2b[2]; /* 0x1e */
646	#endif
647
648	/** The opcode bytes. */
649	uint8_t abOpcode[15]; /* 0x48, 0x20 */
650	/** Explicit alignment padding. */
651	#ifdef IEM_WITH_CODE_TLB
652	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
653	#else
654	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
655	#endif
656	/** @} */
657
658
659	/** The flags of the current exception / interrupt. */
660	uint32_t fCurXcpt; /* 0x48, 0x48 */
661	/** The current exception / interrupt. */
662	uint8_t uCurXcpt;
663	/** Exception / interrupt recursion depth. */
664	int8_t cXcptRecursions;
665
666	/** The number of active guest memory mappings. */
667	uint8_t cActiveMappings;
668	/** The next unused mapping index. */
669	uint8_t iNextMapping;
670	/** Records for tracking guest memory mappings. */
671	struct
672	{
673	/** The address of the mapped bytes. */
674	void *pv;
675	/** The access flags (IEM_ACCESS_XXX).
676	* IEM_ACCESS_INVALID if the entry is unused. */
677	uint32_t fAccess;
678	#if HC_ARCH_BITS == 64
679	uint32_t u32Alignment4; /*< Alignment padding. /
680	#endif
681	} aMemMappings[3];
682
683	/** Locking records for the mapped memory. */
684	union
685	{
686	PGMPAGEMAPLOCK Lock;
687	uint64_t au64Padding[2];
688	} aMemMappingLocks[3];
689
690	/** Bounce buffer info.
691	* This runs in parallel to aMemMappings. */
692	struct
693	{
694	/** The physical address of the first byte. */
695	RTGCPHYS GCPhysFirst;
696	/** The physical address of the second page. */
697	RTGCPHYS GCPhysSecond;
698	/** The number of bytes in the first page. */
699	uint16_t cbFirst;
700	/** The number of bytes in the second page. */
701	uint16_t cbSecond;
702	/** Whether it's unassigned memory. */
703	bool fUnassigned;
704	/** Explicit alignment padding. */
705	bool afAlignment5[3];
706	} aMemBbMappings[3];
707
708	/* Ensure that aBounceBuffers are aligned at a 32 byte boundrary. */
709	uint64_t abAlignment7[1];
710
711	/** Bounce buffer storage.
712	* This runs in parallel to aMemMappings and aMemBbMappings. */
713	struct
714	{
715	uint8_t ab[512];
716	} aBounceBuffers[3];
717
718
719	/** Pointer set jump buffer - ring-3 context. */
720	R3PTRTYPE(jmp_buf *) pJmpBufR3;
721	/** Pointer set jump buffer - ring-0 context. */
722	R0PTRTYPE(jmp_buf *) pJmpBufR0;
723
724	/** @todo Should move this near @a fCurXcpt later. */
725	/** The CR2 for the current exception / interrupt. */
726	uint64_t uCurXcptCr2;
727	/** The error code for the current exception / interrupt. */
728	uint32_t uCurXcptErr;
729
730	/** @name Statistics
731	* @{ */
732	/** The number of instructions we've executed. */
733	uint32_t cInstructions;
734	/** The number of potential exits. */
735	uint32_t cPotentialExits;
736	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
737	* This may contain uncommitted writes. */
738	uint32_t cbWritten;
739	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
740	uint32_t cRetInstrNotImplemented;
741	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
742	uint32_t cRetAspectNotImplemented;
743	/** Counts informational statuses returned (other than VINF_SUCCESS). */
744	uint32_t cRetInfStatuses;
745	/** Counts other error statuses returned. */
746	uint32_t cRetErrStatuses;
747	/** Number of times rcPassUp has been used. */
748	uint32_t cRetPassUpStatus;
749	/** Number of times RZ left with instruction commit pending for ring-3. */
750	uint32_t cPendingCommit;
751	/** Number of long jumps. */
752	uint32_t cLongJumps;
753	/** @} */
754
755	/** @name Target CPU information.
756	* @{ */
757	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
758	/** The target CPU. */
759	uint8_t uTargetCpu;
760	#else
761	uint8_t bTargetCpuPadding;
762	#endif
763	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
764	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
765	* native host support and the 2nd for when there is.
766	*
767	* The two values are typically indexed by a g_CpumHostFeatures bit.
768	*
769	* This is for instance used for the BSF & BSR instructions where AMD and
770	* Intel CPUs produce different EFLAGS. */
771	uint8_t aidxTargetCpuEflFlavour[2];
772
773	/** The CPU vendor. */
774	CPUMCPUVENDOR enmCpuVendor;
775	/** @} */
776
777	/** @name Host CPU information.
778	* @{ */
779	/** The CPU vendor. */
780	CPUMCPUVENDOR enmHostCpuVendor;
781	/** @} */
782
783	/** Counts RDMSR \#GP(0) LogRel(). */
784	uint8_t cLogRelRdMsr;
785	/** Counts WRMSR \#GP(0) LogRel(). */
786	uint8_t cLogRelWrMsr;
787	/** Alignment padding. */
788	uint8_t abAlignment8[42];
789
790	/** Data TLB.
791	* @remarks Must be 64-byte aligned. */
792	IEMTLB DataTlb;
793	/** Instruction TLB.
794	* @remarks Must be 64-byte aligned. */
795	IEMTLB CodeTlb;
796
797	/** Exception statistics. */
798	STAMCOUNTER aStatXcpts[32];
799	/** Interrupt statistics. */
800	uint32_t aStatInts[256];
801
802	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
803	/** Instruction statistics for ring-0/raw-mode. */
804	IEMINSTRSTATS StatsRZ;
805	/** Instruction statistics for ring-3. */
806	IEMINSTRSTATS StatsR3;
807	#endif
808	} IEMCPU;
809	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
810	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 8);
811	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 16);
812	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 32);
813	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
814	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
815	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
816
817	/** Pointer to the per-CPU IEM state. */
818	typedef IEMCPU *PIEMCPU;
819	/** Pointer to the const per-CPU IEM state. */
820	typedef IEMCPU const *PCIEMCPU;
821
822
823	/** @def IEM_GET_CTX
824	* Gets the guest CPU context for the calling EMT.
825	* @returns PCPUMCTX
826	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
827	*/
828	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
829
830	/** @def IEM_CTX_ASSERT
831	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
832	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
833	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
834	*/
835	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
836	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
837	(a_fExtrnMbz)))
838
839	/** @def IEM_CTX_IMPORT_RET
840	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
841	*
842	* Will call the keep to import the bits as needed.
843	*
844	* Returns on import failure.
845	*
846	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
847	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
848	*/
849	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
850	do { \
851	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
852	{ /* likely */ } \
853	else \
854	{ \
855	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
856	AssertRCReturn(rcCtxImport, rcCtxImport); \
857	} \
858	} while (0)
859
860	/** @def IEM_CTX_IMPORT_NORET
861	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
862	*
863	* Will call the keep to import the bits as needed.
864	*
865	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
866	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
867	*/
868	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
869	do { \
870	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
871	{ /* likely */ } \
872	else \
873	{ \
874	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
875	AssertLogRelRC(rcCtxImport); \
876	} \
877	} while (0)
878
879	/** @def IEM_CTX_IMPORT_JMP
880	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
881	*
882	* Will call the keep to import the bits as needed.
883	*
884	* Jumps on import failure.
885	*
886	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
887	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
888	*/
889	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
890	do { \
891	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
892	{ /* likely */ } \
893	else \
894	{ \
895	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
896	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
897	} \
898	} while (0)
899
900
901
902	/** @def IEM_GET_TARGET_CPU
903	* Gets the current IEMTARGETCPU value.
904	* @returns IEMTARGETCPU value.
905	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
906	*/
907	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
908	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
909	#else
910	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
911	#endif
912
913	/** @def IEM_GET_INSTR_LEN
914	* Gets the instruction length. */
915	#ifdef IEM_WITH_CODE_TLB
916	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
917	#else
918	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
919	#endif
920
921
922	/**
923	* Shared per-VM IEM data.
924	*/
925	typedef struct IEM
926	{
927	/** The VMX APIC-access page handler type. */
928	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
929	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
930	/** Set if the CPUID host call functionality is enabled. */
931	bool fCpuIdHostCall;
932	#endif
933	} IEM;
934
935
936
937	/** @name IEM_ACCESS_XXX - Access details.
938	* @{ */
939	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
940	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
941	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
942	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
943	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
944	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
945	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
946	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
947	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
948	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
949	/** The writes are partial, so if initialize the bounce buffer with the
950	* orignal RAM content. */
951	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
952	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
953	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
954	/** Bounce buffer with ring-3 write pending, first page. */
955	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
956	/** Bounce buffer with ring-3 write pending, second page. */
957	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
958	/** Not locked, accessed via the TLB. */
959	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
960	/** Valid bit mask. */
961	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
962	/** Shift count for the TLB flags (upper word). */
963	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
964
965	/** Read+write data alias. */
966	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
967	/** Write data alias. */
968	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
969	/** Read data alias. */
970	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
971	/** Instruction fetch alias. */
972	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
973	/** Stack write alias. */
974	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
975	/** Stack read alias. */
976	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
977	/** Stack read+write alias. */
978	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
979	/** Read system table alias. */
980	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
981	/** Read+write system table alias. */
982	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
983	/** @} */
984
985	/** @name Prefix constants (IEMCPU::fPrefixes)
986	* @{ */
987	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
988	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
989	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
990	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
991	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
992	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
993	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
994
995	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
996	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
997	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
998
999	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
1000	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
1001	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
1002
1003	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
1004	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
1005	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
1006	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
1007	/** Mask with all the REX prefix flags.
1008	* This is generally for use when needing to undo the REX prefixes when they
1009	* are followed legacy prefixes and therefore does not immediately preceed
1010	* the first opcode byte.
1011	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
1012	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
1013
1014	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
1015	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
1016	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
1017	/** @} */
1018
1019	/** @name IEMOPFORM_XXX - Opcode forms
1020	* @note These are ORed together with IEMOPHINT_XXX.
1021	* @{ */
1022	/** ModR/M: reg, r/m */
1023	#define IEMOPFORM_RM 0
1024	/** ModR/M: reg, r/m (register) */
1025	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1026	/** ModR/M: reg, r/m (memory) */
1027	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1028	/** ModR/M: reg, r/m */
1029	#define IEMOPFORM_RMI 1
1030	/** ModR/M: reg, r/m (register) */
1031	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1032	/** ModR/M: reg, r/m (memory) */
1033	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1034	/** ModR/M: r/m, reg */
1035	#define IEMOPFORM_MR 2
1036	/** ModR/M: r/m (register), reg */
1037	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1038	/** ModR/M: r/m (memory), reg */
1039	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1040	/** ModR/M: r/m only */
1041	#define IEMOPFORM_M 3
1042	/** ModR/M: r/m only (register). */
1043	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
1044	/** ModR/M: r/m only (memory). */
1045	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
1046	/** ModR/M: reg only */
1047	#define IEMOPFORM_R 4
1048
1049	/** VEX+ModR/M: reg, r/m */
1050	#define IEMOPFORM_VEX_RM 8
1051	/** VEX+ModR/M: reg, r/m (register) */
1052	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
1053	/** VEX+ModR/M: reg, r/m (memory) */
1054	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
1055	/** VEX+ModR/M: r/m, reg */
1056	#define IEMOPFORM_VEX_MR 9
1057	/** VEX+ModR/M: r/m (register), reg */
1058	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
1059	/** VEX+ModR/M: r/m (memory), reg */
1060	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
1061	/** VEX+ModR/M: r/m only */
1062	#define IEMOPFORM_VEX_M 10
1063	/** VEX+ModR/M: r/m only (register). */
1064	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
1065	/** VEX+ModR/M: r/m only (memory). */
1066	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
1067	/** VEX+ModR/M: reg only */
1068	#define IEMOPFORM_VEX_R 11
1069	/** VEX+ModR/M: reg, vvvv, r/m */
1070	#define IEMOPFORM_VEX_RVM 12
1071	/** VEX+ModR/M: reg, vvvv, r/m (register). */
1072	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
1073	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
1074	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
1075	/** VEX+ModR/M: reg, r/m, vvvv */
1076	#define IEMOPFORM_VEX_RMV 13
1077	/** VEX+ModR/M: reg, r/m, vvvv (register). */
1078	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
1079	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1080	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
1081	/** VEX+ModR/M: reg, r/m, imm8 */
1082	#define IEMOPFORM_VEX_RMI 14
1083	/** VEX+ModR/M: reg, r/m, imm8 (register). */
1084	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
1085	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1086	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1087	/** VEX+ModR/M: r/m, vvvv, reg */
1088	#define IEMOPFORM_VEX_MVR 15
1089	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1090	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1091	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1092	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1093	/** VEX+ModR/M+/n: vvvv, r/m */
1094	#define IEMOPFORM_VEX_VM 16
1095	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1096	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1097	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1098	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1099
1100	/** Fixed register instruction, no R/M. */
1101	#define IEMOPFORM_FIXED 32
1102
1103	/** The r/m is a register. */
1104	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1105	/** The r/m is a memory access. */
1106	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1107	/** @} */
1108
1109	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1110	* @note These are ORed together with IEMOPFORM_XXX.
1111	* @{ */
1112	/** Ignores the operand size prefix (66h). */
1113	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1114	/** Ignores REX.W (aka WIG). */
1115	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1116	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1117	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1118	/** Allowed with the lock prefix. */
1119	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1120	/** The VEX.L value is ignored (aka LIG). */
1121	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1122	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1123	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1124	/** The VEX.V value must be zero. */
1125	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1126
1127	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1128	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1129	/** @} */
1130
1131	/**
1132	* Possible hardware task switch sources.
1133	*/
1134	typedef enum IEMTASKSWITCH
1135	{
1136	/** Task switch caused by an interrupt/exception. */
1137	IEMTASKSWITCH_INT_XCPT = 1,
1138	/** Task switch caused by a far CALL. */
1139	IEMTASKSWITCH_CALL,
1140	/** Task switch caused by a far JMP. */
1141	IEMTASKSWITCH_JUMP,
1142	/** Task switch caused by an IRET. */
1143	IEMTASKSWITCH_IRET
1144	} IEMTASKSWITCH;
1145	AssertCompileSize(IEMTASKSWITCH, 4);
1146
1147	/**
1148	* Possible CrX load (write) sources.
1149	*/
1150	typedef enum IEMACCESSCRX
1151	{
1152	/** CrX access caused by 'mov crX' instruction. */
1153	IEMACCESSCRX_MOV_CRX,
1154	/** CrX (CR0) write caused by 'lmsw' instruction. */
1155	IEMACCESSCRX_LMSW,
1156	/** CrX (CR0) write caused by 'clts' instruction. */
1157	IEMACCESSCRX_CLTS,
1158	/** CrX (CR0) read caused by 'smsw' instruction. */
1159	IEMACCESSCRX_SMSW
1160	} IEMACCESSCRX;
1161
1162	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1163	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1164	*
1165	* These flags provide further context to SLAT page-walk failures that could not be
1166	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1167	*
1168	* @{
1169	*/
1170	/** Translating a nested-guest linear address failed accessing a nested-guest
1171	* physical address. */
1172	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1173	/** Translating a nested-guest linear address failed accessing a
1174	* paging-structure entry or updating accessed/dirty bits. */
1175	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1176	/** @} */
1177
1178	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1179	# ifndef IN_RING3
1180	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1181	# endif
1182	#endif
1183
1184	/**
1185	* Indicates to the verifier that the given flag set is undefined.
1186	*
1187	* Can be invoked again to add more flags.
1188	*
1189	* This is a NOOP if the verifier isn't compiled in.
1190	*
1191	* @note We're temporarily keeping this until code is converted to new
1192	* disassembler style opcode handling.
1193	*/
1194	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1195
1196
1197	/** @def IEM_DECL_IMPL_TYPE
1198	* For typedef'ing an instruction implementation function.
1199	*
1200	* @param a_RetType The return type.
1201	* @param a_Name The name of the type.
1202	* @param a_ArgList The argument list enclosed in parentheses.
1203	*/
1204
1205	/** @def IEM_DECL_IMPL_DEF
1206	* For defining an instruction implementation function.
1207	*
1208	* @param a_RetType The return type.
1209	* @param a_Name The name of the type.
1210	* @param a_ArgList The argument list enclosed in parentheses.
1211	*/
1212
1213	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1214	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1215	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1216	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1217	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1218	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1219	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1220
1221	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1222	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1223	a_RetType (__fastcall a_Name) a_ArgList
1224	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1225	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1226	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1227	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1228
1229	#elif __cplusplus >= 201700 /* P0012R1 support */
1230	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1231	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1232	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1233	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1234	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1235	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1236
1237	#else
1238	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1239	a_RetType (VBOXCALL a_Name) a_ArgList
1240	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1241	a_RetType VBOXCALL a_Name a_ArgList
1242	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1243	a_RetType VBOXCALL a_Name a_ArgList
1244
1245	#endif
1246
1247	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1248	RT_C_DECLS_BEGIN
1249	extern uint8_t const g_afParity[256];
1250	RT_C_DECLS_END
1251
1252
1253	/** @name Arithmetic assignment operations on bytes (binary).
1254	* @{ */
1255	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1256	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1257	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1258	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1259	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1260	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1261	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1262	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1263	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1264	/** @} */
1265
1266	/** @name Arithmetic assignment operations on words (binary).
1267	* @{ */
1268	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1269	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1270	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1271	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1272	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1273	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1274	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1275	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1276	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1277	/** @} */
1278
1279	/** @name Arithmetic assignment operations on double words (binary).
1280	* @{ */
1281	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1282	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1283	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1284	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1285	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1286	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1287	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1288	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1289	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1290	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1291	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1292	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1293	/** @} */
1294
1295	/** @name Arithmetic assignment operations on quad words (binary).
1296	* @{ */
1297	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1298	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1299	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1300	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1301	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1302	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1303	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1304	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1305	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1306	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1307	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1308	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1309	/** @} */
1310
1311	/** @name Compare operations (thrown in with the binary ops).
1312	* @{ */
1313	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1314	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1315	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1316	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1317	/** @} */
1318
1319	/** @name Test operations (thrown in with the binary ops).
1320	* @{ */
1321	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1322	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1323	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1324	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1325	/** @} */
1326
1327	/** @name Bit operations operations (thrown in with the binary ops).
1328	* @{ */
1329	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1330	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1331	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1332	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1333	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1334	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1335	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1336	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1337	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1338	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1339	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1340	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1341	/** @} */
1342
1343	/** @name Arithmetic three operand operations on double words (binary).
1344	* @{ */
1345	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
1346	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1347	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1348	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1349	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1350	/** @} */
1351
1352	/** @name Arithmetic three operand operations on quad words (binary).
1353	* @{ */
1354	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
1355	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1356	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1357	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1358	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1359	/** @} */
1360
1361	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1362	* @{ */
1363	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1364	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1365	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1366	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1367	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1368	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1369	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1370	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1371	/** @} */
1372
1373	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1374	* @{ */
1375	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1376	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1377	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1378	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1379	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1380	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1381	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1382	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1383	/** @} */
1384
1385	/** @name MULX 32-bit and 64-bit.
1386	* @{ */
1387	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
1388	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1389	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1390
1391	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
1392	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1393	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1394	/** @} */
1395
1396
1397	/** @name Exchange memory with register operations.
1398	* @{ */
1399	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1400	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1401	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1402	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1403	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1404	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1405	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1406	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1407	/** @} */
1408
1409	/** @name Exchange and add operations.
1410	* @{ */
1411	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1412	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1413	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1414	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1415	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1416	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1417	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1418	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1419	/** @} */
1420
1421	/** @name Compare and exchange.
1422	* @{ */
1423	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1424	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1425	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1426	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1427	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1428	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1429	#if ARCH_BITS == 32
1430	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1431	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1432	#else
1433	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1434	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1435	#endif
1436	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1437	uint32_t *pEFlags));
1438	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1439	uint32_t *pEFlags));
1440	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1441	uint32_t *pEFlags));
1442	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1443	uint32_t *pEFlags));
1444	#ifndef RT_ARCH_ARM64
1445	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1446	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1447	#endif
1448	/** @} */
1449
1450	/** @name Memory ordering
1451	* @{ */
1452	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1453	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1454	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1455	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1456	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1457	#ifndef RT_ARCH_ARM64
1458	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1459	#endif
1460	/** @} */
1461
1462	/** @name Double precision shifts
1463	* @{ */
1464	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1465	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1466	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1467	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1468	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1469	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1470	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1471	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1472	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1473	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1474	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1475	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1476	/** @} */
1477
1478
1479	/** @name Bit search operations (thrown in with the binary ops).
1480	* @{ */
1481	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1482	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1483	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1484	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1485	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1486	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1487	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1488	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1489	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1490	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
1491	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
1492	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
1493	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
1494	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
1495	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
1496	/** @} */
1497
1498	/** @name Signed multiplication operations (thrown in with the binary ops).
1499	* @{ */
1500	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1501	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1502	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1503	/** @} */
1504
1505	/** @name Arithmetic assignment operations on bytes (unary).
1506	* @{ */
1507	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1508	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1509	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1510	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1511	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1512	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1513	/** @} */
1514
1515	/** @name Arithmetic assignment operations on words (unary).
1516	* @{ */
1517	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1518	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1519	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1520	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1521	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1522	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1523	/** @} */
1524
1525	/** @name Arithmetic assignment operations on double words (unary).
1526	* @{ */
1527	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1528	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1529	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1530	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1531	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1532	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1533	/** @} */
1534
1535	/** @name Arithmetic assignment operations on quad words (unary).
1536	* @{ */
1537	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1538	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1539	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1540	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1541	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1542	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1543	/** @} */
1544
1545
1546	/** @name Shift operations on bytes (Group 2).
1547	* @{ */
1548	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1549	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1550	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1551	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1552	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1553	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1554	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1555	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1556	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1557	/** @} */
1558
1559	/** @name Shift operations on words (Group 2).
1560	* @{ */
1561	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1562	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1563	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1564	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1565	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1566	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1567	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1568	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1569	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1570	/** @} */
1571
1572	/** @name Shift operations on double words (Group 2).
1573	* @{ */
1574	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1575	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1576	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1577	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1578	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1579	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1580	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1581	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1582	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1583	/** @} */
1584
1585	/** @name Shift operations on words (Group 2).
1586	* @{ */
1587	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1588	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1589	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1590	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1591	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1592	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1593	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1594	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1595	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1596	/** @} */
1597
1598	/** @name Multiplication and division operations.
1599	* @{ */
1600	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1601	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1602	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1603	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1604	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1605	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1606
1607	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1608	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1609	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1610	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1611	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1612	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1613
1614	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1615	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1616	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1617	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1618	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1619	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1620
1621	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1622	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1623	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1624	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1625	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1626	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1627	/** @} */
1628
1629	/** @name Byte Swap.
1630	* @{ */
1631	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1632	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1633	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1634	/** @} */
1635
1636	/** @name Misc.
1637	* @{ */
1638	FNIEMAIMPLBINU16 iemAImpl_arpl;
1639	/** @} */
1640
1641	/** @name RDRAND and RDSEED
1642	* @{ */
1643	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
1644	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
1645	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
1646	typedef FNIEMAIMPLRDRANDSEEDU16 *FNIEMAIMPLPRDRANDSEEDU16;
1647	typedef FNIEMAIMPLRDRANDSEEDU32 *FNIEMAIMPLPRDRANDSEEDU32;
1648	typedef FNIEMAIMPLRDRANDSEEDU64 *FNIEMAIMPLPRDRANDSEEDU64;
1649
1650	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
1651	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
1652	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
1653	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
1654	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
1655	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
1656	/** @} */
1657
1658	/** @name FPU operations taking a 32-bit float argument
1659	* @{ */
1660	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1661	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1662	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1663
1664	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1665	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1666	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1667
1668	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1669	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1670	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1671	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1672	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1673	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1674	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1675
1676	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1677	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1678	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1679	/** @} */
1680
1681	/** @name FPU operations taking a 64-bit float argument
1682	* @{ */
1683	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1684	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1685	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
1686
1687	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1688	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1689	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1690
1691	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
1692	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1693	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1694	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1695	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1696	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1697	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1698
1699	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1700	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1701	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1702	/** @} */
1703
1704	/** @name FPU operations taking a 80-bit float argument
1705	* @{ */
1706	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1707	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1708	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1709	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1710	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1711	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1712	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1713	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1714	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1715	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1716	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1717	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1718
1719	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
1720	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
1721	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
1722
1723	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1724	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1725	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1726	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1727	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1728
1729	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1730	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1731	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1732	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1733	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1734
1735	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1736	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1737	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1738	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1739	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
1740	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1741	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1742	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
1743	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
1744
1745	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1746	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1747	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1748	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1749
1750	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1751	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1752	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1753	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1754	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1755	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1756	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1757	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1758	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1759
1760	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1761	PCRTFLOAT80U pr80Val));
1762	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1763	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
1764	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1765	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
1766
1767	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1768	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1769	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1770
1771	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
1772	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1773	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
1774
1775	/** @} */
1776
1777	/** @name FPU operations taking a 16-bit signed integer argument
1778	* @{ */
1779	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1780	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1781	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1782	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1783	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
1784	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
1785
1786	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1787	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1788	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1789	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1790	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1791	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1792
1793	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1794	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1795	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
1796	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
1797
1798	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1799	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
1800	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
1801	/** @} */
1802
1803	/** @name FPU operations taking a 32-bit signed integer argument
1804	* @{ */
1805	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1806	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1807	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1808	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1809	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
1810	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
1811
1812	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1813	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1814	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1815	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1816	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1817	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1818
1819	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1820	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1821	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
1822	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
1823
1824	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1825	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
1826	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
1827	/** @} */
1828
1829	/** @name FPU operations taking a 64-bit signed integer argument
1830	* @{ */
1831	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1832	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
1833	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
1834
1835	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1836	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
1837	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
1838	/** @} */
1839
1840
1841	/** Temporary type representing a 256-bit vector register. */
1842	typedef struct { uint64_t au64[4]; } IEMVMM256;
1843	/** Temporary type pointing to a 256-bit vector register. */
1844	typedef IEMVMM256 *PIEMVMM256;
1845	/** Temporary type pointing to a const 256-bit vector register. */
1846	typedef IEMVMM256 *PCIEMVMM256;
1847
1848
1849	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1850	* @{ */
1851	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
1852	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1853	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1854	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1855	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1856	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
1857	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1858	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
1859	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
1860	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
1861	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
1862	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
1863	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1864	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
1865	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1866	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
1867	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
1868	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
1869	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
1870	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
1871	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1872	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
1873	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
1874	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
1875	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
1876	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
1877	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
1878	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
1879	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
1880	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
1881	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
1882	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
1883	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
1884	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
1885	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
1886	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
1887	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
1888	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
1889	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
1890	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
1891	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
1892	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
1893	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
1894	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
1895	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
1896	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
1897	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
1898	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
1899	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
1900	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
1901	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
1902	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
1903	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
1904	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
1905	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
1906	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
1907	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
1908
1909	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
1910	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
1911	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1912	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
1913	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
1914	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
1915	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
1916	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
1917	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
1918	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
1919	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
1920	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
1921	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
1922	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
1923	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
1924	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
1925	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
1926	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
1927	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
1928	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
1929	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
1930	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
1931	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
1932	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
1933	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
1934	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
1935	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
1936	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
1937	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
1938	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
1939	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
1940	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
1941	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
1942	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
1943	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
1944	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
1945	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
1946	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
1947	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
1948	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
1949	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
1950	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
1951	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
1952	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
1953	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
1954	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
1955	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
1956	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
1957	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
1958	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
1959	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
1960	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
1961	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
1962	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
1963	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
1964	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
1965	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
1966
1967	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
1968	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
1969	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
1970	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
1971	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
1972	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
1973	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
1974	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
1975	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
1976	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
1977	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
1978	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
1979	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
1980	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
1981	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
1982	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
1983	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
1984	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
1985	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
1986	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
1987	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
1988	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
1989	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
1990	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
1991	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
1992	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
1993	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
1994	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
1995	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
1996	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
1997	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
1998	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
1999	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
2000	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
2001	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
2002	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
2003	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
2004	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
2005	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
2006	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
2007	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
2008	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
2009	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
2010	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
2011	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
2012	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
2013	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
2014	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
2015	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
2016	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
2017	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
2018	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
2019	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
2020	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
2021	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
2022	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
2023	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
2024
2025	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
2026	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
2027	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
2028	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
2029
2030	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
2031	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
2032	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
2033	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
2034	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
2035	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
2036	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
2037	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
2038	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
2039	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
2040	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
2041	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
2042	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
2043	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
2044	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
2045	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
2046	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
2047	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
2048	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
2049	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
2050	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
2051	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
2052	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
2053	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
2054	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
2055	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
2056	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
2057	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
2058	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
2059	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
2060	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
2061	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
2062	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
2063	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
2064	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
2065	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
2066	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
2067	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
2068	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
2069	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
2070	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
2071	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
2072	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
2073	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
2074	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
2075	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
2076	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
2077	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
2078	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
2079	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
2080	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
2081	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
2082	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
2083	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
2084	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
2085	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
2086	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
2087
2088	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
2089	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
2090	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
2091	/** @} */
2092
2093	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2094	* @{ */
2095	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2096	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2097	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2098	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2099	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2100	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2101	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2102	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2103	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2104	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2105
2106	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2107	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2108	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2109	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2110	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2111	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2112	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2113	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2114	/** @} */
2115
2116	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2117	* @{ */
2118	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2119	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2120	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2121	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2122	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2123	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2124	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2125	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2126	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2127	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2128	/** @} */
2129
2130	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2131	* @{ */
2132	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2133	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2134	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2135	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2136	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
2137	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2138	#ifndef IEM_WITHOUT_ASSEMBLY
2139	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2140	#endif
2141	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2142	/** @} */
2143
2144	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2145	* @{ */
2146	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2147	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2148	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2149	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2150	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2151	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2152	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2153	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2154	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2155	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2156	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2157	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2158	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2159	/** @} */
2160
2161	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2162	* @{ */
2163	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
2164	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2165	#ifndef IEM_WITHOUT_ASSEMBLY
2166	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2167	#endif
2168	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2169	/** @} */
2170
2171	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
2172	* @{ */
2173	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
2174	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
2175	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
2176	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
2177	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
2178	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
2179
2180	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
2181	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
2182	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
2183	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
2184	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
2185	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
2186
2187	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
2188	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
2189	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
2190	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
2191	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
2192	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
2193
2194	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
2195	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
2196	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
2197	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
2198	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
2199	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
2200	/** @} */
2201
2202
2203	/** @name Media (SSE/MMX/AVX) operation: Sort this later
2204	* @{ */
2205	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2206	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2207	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PRTUINT128U puDst, uint64_t uSrc));
2208
2209	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2210	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2211	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2212	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2213	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2214	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2215
2216	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2217	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2218	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2219	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2220	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2221
2222	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2223	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2224	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2225	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2226	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2227
2228	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2229	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2230	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2231	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2232	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2233
2234	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2235	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2236	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2237	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2238	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2239
2240	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2241	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2242	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2243	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2244	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2245
2246	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2247	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2248	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2249	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2250	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2251
2252	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2253	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2254	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2255	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2256	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2257
2258	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2259	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2260	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2261	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2262	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2263
2264	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2265	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2266	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2267	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2268	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2269
2270	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2271	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2272	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2273	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2274	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2275
2276	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2277	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2278	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2279	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2280	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2281
2282	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2283	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2284	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2285	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2286	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2287
2288	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2289	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2290	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2291	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2292	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2293
2294	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2295	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2296	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2297	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2298	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2299
2300	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2301	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2302
2303	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
2304	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
2305	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2306	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2307
2308	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
2309	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2310	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2311	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2312
2313	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2314	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2315	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2316	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2317	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2318
2319	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2320	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2321	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2322	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2323	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2324
2325
2326	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2327	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
2328	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2329	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
2330	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2331	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
2332
2333	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
2334	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
2335	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
2336	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
2337
2338	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
2339	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
2340	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
2341	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
2342
2343	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
2344	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
2345	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
2346	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
2347
2348	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
2349	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
2350	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
2351	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
2352	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
2353
2354	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
2355	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
2356	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
2357	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
2358	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
2359
2360	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
2361
2362	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
2363
2364
2365	typedef struct IEMPCMPISTRISRC
2366	{
2367	RTUINT128U uSrc1;
2368	RTUINT128U uSrc2;
2369	} IEMPCMPISTRISRC;
2370	typedef IEMPCMPISTRISRC *PIEMPCMPISTRISRC;
2371	typedef const IEMPCMPISTRISRC *PCIEMPCMPISTRISRC;
2372
2373	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpistri_u128,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRISRC pSrc, uint8_t bEvil));
2374	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpistri_u128_fallback,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRISRC pSrc, uint8_t bEvil));
2375
2376	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
2377	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
2378	/** @} */
2379
2380	/** @name Media Odds and Ends
2381	* @{ */
2382	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
2383	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
2384	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
2385	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
2386	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
2387	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
2388	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
2389	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
2390
2391	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
2392	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
2393	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
2394	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
2395
2396	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2397	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
2398	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2399	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
2400	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2401	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
2402	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2403	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
2404
2405	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
2406	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
2407
2408	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
2409	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
2410
2411	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
2412	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
2413
2414	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
2415	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
2416
2417	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
2418	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
2419	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
2420	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
2421
2422	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
2423	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
2424
2425	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
2426	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
2427	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
2428	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
2429
2430	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
2431	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
2432
2433
2434	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2435	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
2436
2437	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
2438	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
2439
2440	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
2441	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
2442
2443	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
2444	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
2445
2446	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
2447	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
2448
2449
2450	typedef struct IEMMEDIAF2XMMSRC
2451	{
2452	X86XMMREG uSrc1;
2453	X86XMMREG uSrc2;
2454	} IEMMEDIAF2XMMSRC;
2455	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
2456	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
2457
2458	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
2459	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
2460
2461	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
2462	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
2463	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
2464	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
2465
2466	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
2467	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
2468
2469	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
2470	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
2471
2472	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
2473	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
2474
2475	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
2476	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
2477
2478	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
2479	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
2480
2481	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
2482	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
2483
2484	/** @} */
2485
2486
2487	/** @name Function tables.
2488	* @{
2489	*/
2490
2491	/**
2492	* Function table for a binary operator providing implementation based on
2493	* operand size.
2494	*/
2495	typedef struct IEMOPBINSIZES
2496	{
2497	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
2498	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
2499	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
2500	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
2501	} IEMOPBINSIZES;
2502	/** Pointer to a binary operator function table. */
2503	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
2504
2505
2506	/**
2507	* Function table for a unary operator providing implementation based on
2508	* operand size.
2509	*/
2510	typedef struct IEMOPUNARYSIZES
2511	{
2512	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
2513	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
2514	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
2515	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
2516	} IEMOPUNARYSIZES;
2517	/** Pointer to a unary operator function table. */
2518	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
2519
2520
2521	/**
2522	* Function table for a shift operator providing implementation based on
2523	* operand size.
2524	*/
2525	typedef struct IEMOPSHIFTSIZES
2526	{
2527	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
2528	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
2529	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
2530	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
2531	} IEMOPSHIFTSIZES;
2532	/** Pointer to a shift operator function table. */
2533	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
2534
2535
2536	/**
2537	* Function table for a multiplication or division operation.
2538	*/
2539	typedef struct IEMOPMULDIVSIZES
2540	{
2541	PFNIEMAIMPLMULDIVU8 pfnU8;
2542	PFNIEMAIMPLMULDIVU16 pfnU16;
2543	PFNIEMAIMPLMULDIVU32 pfnU32;
2544	PFNIEMAIMPLMULDIVU64 pfnU64;
2545	} IEMOPMULDIVSIZES;
2546	/** Pointer to a multiplication or division operation function table. */
2547	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
2548
2549
2550	/**
2551	* Function table for a double precision shift operator providing implementation
2552	* based on operand size.
2553	*/
2554	typedef struct IEMOPSHIFTDBLSIZES
2555	{
2556	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
2557	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
2558	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
2559	} IEMOPSHIFTDBLSIZES;
2560	/** Pointer to a double precision shift function table. */
2561	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
2562
2563
2564	/**
2565	* Function table for media instruction taking two full sized media source
2566	* registers and one full sized destination register (AVX).
2567	*/
2568	typedef struct IEMOPMEDIAF3
2569	{
2570	PFNIEMAIMPLMEDIAF3U128 pfnU128;
2571	PFNIEMAIMPLMEDIAF3U256 pfnU256;
2572	} IEMOPMEDIAF3;
2573	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2574	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
2575
2576	/** @def IEMOPMEDIAF3_INIT_VARS_EX
2577	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2578	* given functions as initializers. For use in AVX functions where a pair of
2579	* functions are only used once and the function table need not be public. */
2580	#ifndef TST_IEM_CHECK_MC
2581	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2582	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2583	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2584	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2585	# else
2586	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2587	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2588	# endif
2589	#else
2590	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2591	#endif
2592	/** @def IEMOPMEDIAF3_INIT_VARS
2593	* Generate AVX function tables for the @a a_InstrNm instruction.
2594	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
2595	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
2596	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2597	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2598
2599	/**
2600	* Function table for media instruction taking two full sized media source
2601	* registers and one full sized destination register, but no additional state
2602	* (AVX).
2603	*/
2604	typedef struct IEMOPMEDIAOPTF3
2605	{
2606	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
2607	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
2608	} IEMOPMEDIAOPTF3;
2609	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2610	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
2611
2612	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
2613	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2614	* given functions as initializers. For use in AVX functions where a pair of
2615	* functions are only used once and the function table need not be public. */
2616	#ifndef TST_IEM_CHECK_MC
2617	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2618	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2619	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2620	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2621	# else
2622	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2623	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2624	# endif
2625	#else
2626	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2627	#endif
2628	/** @def IEMOPMEDIAOPTF3_INIT_VARS
2629	* Generate AVX function tables for the @a a_InstrNm instruction.
2630	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
2631	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
2632	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2633	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2634
2635	/**
2636	* Function table for media instruction taking one full sized media source
2637	* registers and one full sized destination register, but no additional state
2638	* (AVX).
2639	*/
2640	typedef struct IEMOPMEDIAOPTF2
2641	{
2642	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
2643	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
2644	} IEMOPMEDIAOPTF2;
2645	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
2646	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
2647
2648	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
2649	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2650	* given functions as initializers. For use in AVX functions where a pair of
2651	* functions are only used once and the function table need not be public. */
2652	#ifndef TST_IEM_CHECK_MC
2653	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2654	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2655	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2656	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2657	# else
2658	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2659	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2660	# endif
2661	#else
2662	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2663	#endif
2664	/** @def IEMOPMEDIAOPTF2_INIT_VARS
2665	* Generate AVX function tables for the @a a_InstrNm instruction.
2666	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
2667	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
2668	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2669	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2670
2671	/**
2672	* Function table for media instruction taking two full sized media source
2673	* registers and one full sized destination register and an 8-bit immediate, but no additional state
2674	* (AVX).
2675	*/
2676	typedef struct IEMOPMEDIAOPTF3IMM8
2677	{
2678	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
2679	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
2680	} IEMOPMEDIAOPTF3IMM8;
2681	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2682	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
2683
2684	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
2685	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2686	* given functions as initializers. For use in AVX functions where a pair of
2687	* functions are only used once and the function table need not be public. */
2688	#ifndef TST_IEM_CHECK_MC
2689	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2690	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2691	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2692	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2693	# else
2694	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2695	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2696	# endif
2697	#else
2698	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2699	#endif
2700	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
2701	* Generate AVX function tables for the @a a_InstrNm instruction.
2702	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
2703	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
2704	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2705	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2706	/** @} */
2707
2708
2709	/**
2710	* Function table for blend type instruction taking three full sized media source
2711	* registers and one full sized destination register, but no additional state
2712	* (AVX).
2713	*/
2714	typedef struct IEMOPBLENDOP
2715	{
2716	PFNIEMAIMPLAVXBLENDU128 pfnU128;
2717	PFNIEMAIMPLAVXBLENDU256 pfnU256;
2718	} IEMOPBLENDOP;
2719	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
2720	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
2721
2722	/** @def IEMOPBLENDOP_INIT_VARS_EX
2723	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2724	* given functions as initializers. For use in AVX functions where a pair of
2725	* functions are only used once and the function table need not be public. */
2726	#ifndef TST_IEM_CHECK_MC
2727	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2728	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2729	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2730	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2731	# else
2732	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2733	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2734	# endif
2735	#else
2736	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2737	#endif
2738	/** @def IEMOPBLENDOP_INIT_VARS
2739	* Generate AVX function tables for the @a a_InstrNm instruction.
2740	* @sa IEMOPBLENDOP_INIT_VARS_EX */
2741	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
2742	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2743	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2744
2745
2746	/** @name SSE/AVX single/double precision floating point operations.
2747	* @{ */
2748	/**
2749	* A SSE result.
2750	*/
2751	typedef struct IEMSSERESULT
2752	{
2753	/** The output value. */
2754	X86XMMREG uResult;
2755	/** The output status. */
2756	uint32_t MXCSR;
2757	} IEMSSERESULT;
2758	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
2759	/** Pointer to a SSE result. */
2760	typedef IEMSSERESULT *PIEMSSERESULT;
2761	/** Pointer to a const SSE result. */
2762	typedef IEMSSERESULT const *PCIEMSSERESULT;
2763
2764
2765	/**
2766	* A AVX128 result.
2767	*/
2768	typedef struct IEMAVX128RESULT
2769	{
2770	/** The output value. */
2771	X86XMMREG uResult;
2772	/** The output status. */
2773	uint32_t MXCSR;
2774	} IEMAVX128RESULT;
2775	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
2776	/** Pointer to a AVX128 result. */
2777	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
2778	/** Pointer to a const AVX128 result. */
2779	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
2780
2781
2782	/**
2783	* A AVX256 result.
2784	*/
2785	typedef struct IEMAVX256RESULT
2786	{
2787	/** The output value. */
2788	X86YMMREG uResult;
2789	/** The output status. */
2790	uint32_t MXCSR;
2791	} IEMAVX256RESULT;
2792	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
2793	/** Pointer to a AVX256 result. */
2794	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
2795	/** Pointer to a const AVX256 result. */
2796	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
2797
2798
2799	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2800	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
2801	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2802	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
2803	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2804	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
2805
2806	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2807	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
2808	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2809	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
2810	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2811	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
2812
2813	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
2814	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
2815
2816	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
2817	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
2818	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
2819	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
2820	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
2821	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
2822	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
2823	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
2824	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
2825	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
2826	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
2827	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
2828	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
2829	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
2830	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
2831	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
2832	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
2833	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
2834	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
2835	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
2836	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
2837	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
2838
2839	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
2840	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
2841	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
2842	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
2843	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
2844	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
2845
2846	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
2847	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
2848	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
2849	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
2850	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
2851	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
2852	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
2853	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
2854	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
2855	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
2856	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
2857	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
2858	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
2859	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
2860	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
2861	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
2862
2863	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
2864	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
2865	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
2866	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
2867	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
2868	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
2869	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
2870	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
2871	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
2872	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
2873	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
2874	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
2875	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
2876	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
2877	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
2878	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
2879	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
2880	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
2881	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
2882	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
2883	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
2884	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
2885
2886	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
2887	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
2888	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
2889	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
2890	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
2891	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
2892	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
2893	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
2894	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
2895	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
2896	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
2897	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
2898	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
2899	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
2900
2901	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
2902	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
2903	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
2904	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
2905	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
2906	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
2907	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
2908	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
2909	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
2910	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
2911	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
2912	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
2913	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
2914	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
2915	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
2916	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
2917	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
2918	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
2919	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
2920	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
2921	/** @} */
2922
2923	/** @name C instruction implementations for anything slightly complicated.
2924	* @{ */
2925
2926	/**
2927	* For typedef'ing or declaring a C instruction implementation function taking
2928	* no extra arguments.
2929	*
2930	* @param a_Name The name of the type.
2931	*/
2932	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
2933	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2934	/**
2935	* For defining a C instruction implementation function taking no extra
2936	* arguments.
2937	*
2938	* @param a_Name The name of the function
2939	*/
2940	# define IEM_CIMPL_DEF_0(a_Name) \
2941	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2942	/**
2943	* Prototype version of IEM_CIMPL_DEF_0.
2944	*/
2945	# define IEM_CIMPL_PROTO_0(a_Name) \
2946	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2947	/**
2948	* For calling a C instruction implementation function taking no extra
2949	* arguments.
2950	*
2951	* This special call macro adds default arguments to the call and allow us to
2952	* change these later.
2953	*
2954	* @param a_fn The name of the function.
2955	*/
2956	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
2957
2958	/**
2959	* For typedef'ing or declaring a C instruction implementation function taking
2960	* one extra argument.
2961	*
2962	* @param a_Name The name of the type.
2963	* @param a_Type0 The argument type.
2964	* @param a_Arg0 The argument name.
2965	*/
2966	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
2967	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2968	/**
2969	* For defining a C instruction implementation function taking one extra
2970	* argument.
2971	*
2972	* @param a_Name The name of the function
2973	* @param a_Type0 The argument type.
2974	* @param a_Arg0 The argument name.
2975	*/
2976	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
2977	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2978	/**
2979	* Prototype version of IEM_CIMPL_DEF_1.
2980	*/
2981	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
2982	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2983	/**
2984	* For calling a C instruction implementation function taking one extra
2985	* argument.
2986	*
2987	* This special call macro adds default arguments to the call and allow us to
2988	* change these later.
2989	*
2990	* @param a_fn The name of the function.
2991	* @param a0 The name of the 1st argument.
2992	*/
2993	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
2994
2995	/**
2996	* For typedef'ing or declaring a C instruction implementation function taking
2997	* two extra arguments.
2998	*
2999	* @param a_Name The name of the type.
3000	* @param a_Type0 The type of the 1st argument
3001	* @param a_Arg0 The name of the 1st argument.
3002	* @param a_Type1 The type of the 2nd argument.
3003	* @param a_Arg1 The name of the 2nd argument.
3004	*/
3005	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3006	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3007	/**
3008	* For defining a C instruction implementation function taking two extra
3009	* arguments.
3010	*
3011	* @param a_Name The name of the function.
3012	* @param a_Type0 The type of the 1st argument
3013	* @param a_Arg0 The name of the 1st argument.
3014	* @param a_Type1 The type of the 2nd argument.
3015	* @param a_Arg1 The name of the 2nd argument.
3016	*/
3017	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3018	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3019	/**
3020	* Prototype version of IEM_CIMPL_DEF_2.
3021	*/
3022	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3023	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3024	/**
3025	* For calling a C instruction implementation function taking two extra
3026	* arguments.
3027	*
3028	* This special call macro adds default arguments to the call and allow us to
3029	* change these later.
3030	*
3031	* @param a_fn The name of the function.
3032	* @param a0 The name of the 1st argument.
3033	* @param a1 The name of the 2nd argument.
3034	*/
3035	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
3036
3037	/**
3038	* For typedef'ing or declaring a C instruction implementation function taking
3039	* three extra arguments.
3040	*
3041	* @param a_Name The name of the type.
3042	* @param a_Type0 The type of the 1st argument
3043	* @param a_Arg0 The name of the 1st argument.
3044	* @param a_Type1 The type of the 2nd argument.
3045	* @param a_Arg1 The name of the 2nd argument.
3046	* @param a_Type2 The type of the 3rd argument.
3047	* @param a_Arg2 The name of the 3rd argument.
3048	*/
3049	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3050	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3051	/**
3052	* For defining a C instruction implementation function taking three extra
3053	* arguments.
3054	*
3055	* @param a_Name The name of the function.
3056	* @param a_Type0 The type of the 1st argument
3057	* @param a_Arg0 The name of the 1st argument.
3058	* @param a_Type1 The type of the 2nd argument.
3059	* @param a_Arg1 The name of the 2nd argument.
3060	* @param a_Type2 The type of the 3rd argument.
3061	* @param a_Arg2 The name of the 3rd argument.
3062	*/
3063	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3064	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3065	/**
3066	* Prototype version of IEM_CIMPL_DEF_3.
3067	*/
3068	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3069	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3070	/**
3071	* For calling a C instruction implementation function taking three extra
3072	* arguments.
3073	*
3074	* This special call macro adds default arguments to the call and allow us to
3075	* change these later.
3076	*
3077	* @param a_fn The name of the function.
3078	* @param a0 The name of the 1st argument.
3079	* @param a1 The name of the 2nd argument.
3080	* @param a2 The name of the 3rd argument.
3081	*/
3082	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
3083
3084
3085	/**
3086	* For typedef'ing or declaring a C instruction implementation function taking
3087	* four extra arguments.
3088	*
3089	* @param a_Name The name of the type.
3090	* @param a_Type0 The type of the 1st argument
3091	* @param a_Arg0 The name of the 1st argument.
3092	* @param a_Type1 The type of the 2nd argument.
3093	* @param a_Arg1 The name of the 2nd argument.
3094	* @param a_Type2 The type of the 3rd argument.
3095	* @param a_Arg2 The name of the 3rd argument.
3096	* @param a_Type3 The type of the 4th argument.
3097	* @param a_Arg3 The name of the 4th argument.
3098	*/
3099	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3100	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
3101	/**
3102	* For defining a C instruction implementation function taking four extra
3103	* arguments.
3104	*
3105	* @param a_Name The name of the function.
3106	* @param a_Type0 The type of the 1st argument
3107	* @param a_Arg0 The name of the 1st argument.
3108	* @param a_Type1 The type of the 2nd argument.
3109	* @param a_Arg1 The name of the 2nd argument.
3110	* @param a_Type2 The type of the 3rd argument.
3111	* @param a_Arg2 The name of the 3rd argument.
3112	* @param a_Type3 The type of the 4th argument.
3113	* @param a_Arg3 The name of the 4th argument.
3114	*/
3115	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3116	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3117	a_Type2 a_Arg2, a_Type3 a_Arg3))
3118	/**
3119	* Prototype version of IEM_CIMPL_DEF_4.
3120	*/
3121	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3122	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3123	a_Type2 a_Arg2, a_Type3 a_Arg3))
3124	/**
3125	* For calling a C instruction implementation function taking four extra
3126	* arguments.
3127	*
3128	* This special call macro adds default arguments to the call and allow us to
3129	* change these later.
3130	*
3131	* @param a_fn The name of the function.
3132	* @param a0 The name of the 1st argument.
3133	* @param a1 The name of the 2nd argument.
3134	* @param a2 The name of the 3rd argument.
3135	* @param a3 The name of the 4th argument.
3136	*/
3137	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
3138
3139
3140	/**
3141	* For typedef'ing or declaring a C instruction implementation function taking
3142	* five extra arguments.
3143	*
3144	* @param a_Name The name of the type.
3145	* @param a_Type0 The type of the 1st argument
3146	* @param a_Arg0 The name of the 1st argument.
3147	* @param a_Type1 The type of the 2nd argument.
3148	* @param a_Arg1 The name of the 2nd argument.
3149	* @param a_Type2 The type of the 3rd argument.
3150	* @param a_Arg2 The name of the 3rd argument.
3151	* @param a_Type3 The type of the 4th argument.
3152	* @param a_Arg3 The name of the 4th argument.
3153	* @param a_Type4 The type of the 5th argument.
3154	* @param a_Arg4 The name of the 5th argument.
3155	*/
3156	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3157	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
3158	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
3159	a_Type3 a_Arg3, a_Type4 a_Arg4))
3160	/**
3161	* For defining a C instruction implementation function taking five extra
3162	* arguments.
3163	*
3164	* @param a_Name The name of the function.
3165	* @param a_Type0 The type of the 1st argument
3166	* @param a_Arg0 The name of the 1st argument.
3167	* @param a_Type1 The type of the 2nd argument.
3168	* @param a_Arg1 The name of the 2nd argument.
3169	* @param a_Type2 The type of the 3rd argument.
3170	* @param a_Arg2 The name of the 3rd argument.
3171	* @param a_Type3 The type of the 4th argument.
3172	* @param a_Arg3 The name of the 4th argument.
3173	* @param a_Type4 The type of the 5th argument.
3174	* @param a_Arg4 The name of the 5th argument.
3175	*/
3176	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3177	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3178	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3179	/**
3180	* Prototype version of IEM_CIMPL_DEF_5.
3181	*/
3182	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3183	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3184	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3185	/**
3186	* For calling a C instruction implementation function taking five extra
3187	* arguments.
3188	*
3189	* This special call macro adds default arguments to the call and allow us to
3190	* change these later.
3191	*
3192	* @param a_fn The name of the function.
3193	* @param a0 The name of the 1st argument.
3194	* @param a1 The name of the 2nd argument.
3195	* @param a2 The name of the 3rd argument.
3196	* @param a3 The name of the 4th argument.
3197	* @param a4 The name of the 5th argument.
3198	*/
3199	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
3200
3201	/** @} */
3202
3203
3204	/** @name Opcode Decoder Function Types.
3205	* @{ */
3206
3207	/** @typedef PFNIEMOP
3208	* Pointer to an opcode decoder function.
3209	*/
3210
3211	/** @def FNIEMOP_DEF
3212	* Define an opcode decoder function.
3213	*
3214	* We're using macors for this so that adding and removing parameters as well as
3215	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
3216	*
3217	* @param a_Name The function name.
3218	*/
3219
3220	/** @typedef PFNIEMOPRM
3221	* Pointer to an opcode decoder function with RM byte.
3222	*/
3223
3224	/** @def FNIEMOPRM_DEF
3225	* Define an opcode decoder function with RM byte.
3226	*
3227	* We're using macors for this so that adding and removing parameters as well as
3228	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
3229	*
3230	* @param a_Name The function name.
3231	*/
3232
3233	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3234	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
3235	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3236	# define FNIEMOP_DEF(a_Name) \
3237	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
3238	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3239	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3240	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3241	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3242
3243	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3244	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
3245	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3246	# define FNIEMOP_DEF(a_Name) \
3247	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3248	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3249	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3250	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3251	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3252
3253	#elif defined(__GNUC__)
3254	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3255	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3256	# define FNIEMOP_DEF(a_Name) \
3257	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
3258	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3259	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3260	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3261	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3262
3263	#else
3264	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3265	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3266	# define FNIEMOP_DEF(a_Name) \
3267	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3268	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3269	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3270	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3271	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3272
3273	#endif
3274	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
3275
3276	/**
3277	* Call an opcode decoder function.
3278	*
3279	* We're using macors for this so that adding and removing parameters can be
3280	* done as we please. See FNIEMOP_DEF.
3281	*/
3282	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
3283
3284	/**
3285	* Call a common opcode decoder function taking one extra argument.
3286	*
3287	* We're using macors for this so that adding and removing parameters can be
3288	* done as we please. See FNIEMOP_DEF_1.
3289	*/
3290	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
3291
3292	/**
3293	* Call a common opcode decoder function taking one extra argument.
3294	*
3295	* We're using macors for this so that adding and removing parameters can be
3296	* done as we please. See FNIEMOP_DEF_1.
3297	*/
3298	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
3299	/** @} */
3300
3301
3302	/** @name Misc Helpers
3303	* @{ */
3304
3305	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
3306	* due to GCC lacking knowledge about the value range of a switch. */
3307	#if RT_CPLUSPLUS_PREREQ(202000)
3308	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3309	#else
3310	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3311	#endif
3312
3313	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
3314	#if RT_CPLUSPLUS_PREREQ(202000)
3315	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
3316	#else
3317	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
3318	#endif
3319
3320	/**
3321	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3322	* occation.
3323	*/
3324	#ifdef LOG_ENABLED
3325	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3326	do { \
3327	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
3328	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3329	} while (0)
3330	#else
3331	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3332	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3333	#endif
3334
3335	/**
3336	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3337	* occation using the supplied logger statement.
3338	*
3339	* @param a_LoggerArgs What to log on failure.
3340	*/
3341	#ifdef LOG_ENABLED
3342	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3343	do { \
3344	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
3345	/LogFunc(a_LoggerArgs);/ \
3346	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3347	} while (0)
3348	#else
3349	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3350	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3351	#endif
3352
3353	/**
3354	* Check if we're currently executing in real or virtual 8086 mode.
3355	*
3356	* @returns @c true if it is, @c false if not.
3357	* @param a_pVCpu The IEM state of the current CPU.
3358	*/
3359	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (CPUMIsGuestInRealOrV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3360
3361	/**
3362	* Check if we're currently executing in virtual 8086 mode.
3363	*
3364	* @returns @c true if it is, @c false if not.
3365	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3366	*/
3367	#define IEM_IS_V86_MODE(a_pVCpu) (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3368
3369	/**
3370	* Check if we're currently executing in long mode.
3371	*
3372	* @returns @c true if it is, @c false if not.
3373	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3374	*/
3375	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
3376
3377	/**
3378	* Check if we're currently executing in a 64-bit code segment.
3379	*
3380	* @returns @c true if it is, @c false if not.
3381	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3382	*/
3383	#define IEM_IS_64BIT_CODE(a_pVCpu) (CPUMIsGuestIn64BitCodeEx(IEM_GET_CTX(a_pVCpu)))
3384
3385	/**
3386	* Check if we're currently executing in real mode.
3387	*
3388	* @returns @c true if it is, @c false if not.
3389	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3390	*/
3391	#define IEM_IS_REAL_MODE(a_pVCpu) (CPUMIsGuestInRealModeEx(IEM_GET_CTX(a_pVCpu)))
3392
3393	/**
3394	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
3395	* @returns PCCPUMFEATURES
3396	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3397	*/
3398	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
3399
3400	/**
3401	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
3402	* @returns PCCPUMFEATURES
3403	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3404	*/
3405	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
3406
3407	/**
3408	* Evaluates to true if we're presenting an Intel CPU to the guest.
3409	*/
3410	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
3411
3412	/**
3413	* Evaluates to true if we're presenting an AMD CPU to the guest.
3414	*/
3415	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
3416
3417	/**
3418	* Check if the address is canonical.
3419	*/
3420	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
3421
3422	/** Checks if the ModR/M byte is in register mode or not. */
3423	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
3424	/** Checks if the ModR/M byte is in memory mode or not. */
3425	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
3426
3427	/**
3428	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
3429	*
3430	* For use during decoding.
3431	*/
3432	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
3433	/**
3434	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
3435	*
3436	* For use during decoding.
3437	*/
3438	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
3439
3440	/**
3441	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
3442	*
3443	* For use during decoding.
3444	*/
3445	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
3446	/**
3447	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
3448	*
3449	* For use during decoding.
3450	*/
3451	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
3452
3453	/**
3454	* Gets the effective VEX.VVVV value.
3455	*
3456	* The 4th bit is ignored if not 64-bit code.
3457	* @returns effective V-register value.
3458	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3459	*/
3460	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
3461	((a_pVCpu)->iem.s.enmCpuMode == IEMMODE_64BIT ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
3462
3463
3464	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3465
3466	/**
3467	* Check if the guest has entered VMX root operation.
3468	*/
3469	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
3470
3471	/**
3472	* Check if the guest has entered VMX non-root operation.
3473	*/
3474	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(a_pVCpu)))
3475
3476	/**
3477	* Check if the nested-guest has the given Pin-based VM-execution control set.
3478	*/
3479	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) \
3480	(CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
3481
3482	/**
3483	* Check if the nested-guest has the given Processor-based VM-execution control set.
3484	*/
3485	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) \
3486	(CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
3487
3488	/**
3489	* Check if the nested-guest has the given Secondary Processor-based VM-execution
3490	* control set.
3491	*/
3492	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) \
3493	(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
3494
3495	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
3496	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
3497
3498	/** Whether a shadow VMCS is present for the given VCPU. */
3499	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3500
3501	/** Gets the VMXON region pointer. */
3502	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
3503
3504	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
3505	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
3506
3507	/** Whether a current VMCS is present for the given VCPU. */
3508	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3509
3510	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
3511	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
3512	do \
3513	{ \
3514	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
3515	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
3516	} while (0)
3517
3518	/** Clears any current VMCS for the given VCPU. */
3519	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
3520	do \
3521	{ \
3522	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
3523	} while (0)
3524
3525	/**
3526	* Invokes the VMX VM-exit handler for an instruction intercept.
3527	*/
3528	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
3529	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
3530
3531	/**
3532	* Invokes the VMX VM-exit handler for an instruction intercept where the
3533	* instruction provides additional VM-exit information.
3534	*/
3535	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
3536	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
3537
3538	/**
3539	* Invokes the VMX VM-exit handler for a task switch.
3540	*/
3541	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
3542	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
3543
3544	/**
3545	* Invokes the VMX VM-exit handler for MWAIT.
3546	*/
3547	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
3548	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
3549
3550	/**
3551	* Invokes the VMX VM-exit handler for EPT faults.
3552	*/
3553	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
3554	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
3555
3556	/**
3557	* Invokes the VMX VM-exit handler.
3558	*/
3559	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
3560	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
3561
3562	#else
3563	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
3564	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
3565	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
3566	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
3567	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
3568	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3569	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3570	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3571	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3572	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3573	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
3574
3575	#endif
3576
3577	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3578	/**
3579	* Check if an SVM control/instruction intercept is set.
3580	*/
3581	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
3582	(CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
3583
3584	/**
3585	* Check if an SVM read CRx intercept is set.
3586	*/
3587	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3588	(CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3589
3590	/**
3591	* Check if an SVM write CRx intercept is set.
3592	*/
3593	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3594	(CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3595
3596	/**
3597	* Check if an SVM read DRx intercept is set.
3598	*/
3599	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3600	(CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3601
3602	/**
3603	* Check if an SVM write DRx intercept is set.
3604	*/
3605	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3606	(CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3607
3608	/**
3609	* Check if an SVM exception intercept is set.
3610	*/
3611	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
3612	(CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
3613
3614	/**
3615	* Invokes the SVM \#VMEXIT handler for the nested-guest.
3616	*/
3617	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3618	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
3619
3620	/**
3621	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
3622	* corresponding decode assist information.
3623	*/
3624	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
3625	do \
3626	{ \
3627	uint64_t uExitInfo1; \
3628	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
3629	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
3630	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
3631	else \
3632	uExitInfo1 = 0; \
3633	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
3634	} while (0)
3635
3636	/** Check and handles SVM nested-guest instruction intercept and updates
3637	* NRIP if needed.
3638	*/
3639	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3640	do \
3641	{ \
3642	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
3643	{ \
3644	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3645	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
3646	} \
3647	} while (0)
3648
3649	/** Checks and handles SVM nested-guest CR0 read intercept. */
3650	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) \
3651	do \
3652	{ \
3653	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
3654	{ /* probably likely */ } \
3655	else \
3656	{ \
3657	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3658	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
3659	} \
3660	} while (0)
3661
3662	/**
3663	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
3664	*/
3665	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) \
3666	do { \
3667	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
3668	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), IEM_GET_INSTR_LEN(a_pVCpu)); \
3669	} while (0)
3670
3671	#else
3672	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
3673	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3674	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3675	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3676	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3677	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
3678	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
3679	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
3680	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3681	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3682	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) do { } while (0)
3683
3684	#endif
3685
3686	/** @} */
3687
3688
3689
3690	/**
3691	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
3692	*/
3693	typedef union IEMSELDESC
3694	{
3695	/** The legacy view. */
3696	X86DESC Legacy;
3697	/** The long mode view. */
3698	X86DESC64 Long;
3699	} IEMSELDESC;
3700	/** Pointer to a selector descriptor table entry. */
3701	typedef IEMSELDESC *PIEMSELDESC;
3702
3703	/** @name Raising Exceptions.
3704	* @{ */
3705	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
3706	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
3707
3708	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
3709	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3710	#ifdef IEM_WITH_SETJMP
3711	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
3712	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
3713	#endif
3714	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
3715	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3716	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
3717	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
3718	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
3719	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3720	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
3721	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3722	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3723	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
3724	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3725	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3726	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3727	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3728	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3729	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3730	#ifdef IEM_WITH_SETJMP
3731	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3732	#endif
3733	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3734	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
3735	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3736	#ifdef IEM_WITH_SETJMP
3737	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
3738	#endif
3739	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3740	#ifdef IEM_WITH_SETJMP
3741	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
3742	#endif
3743	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3744	#ifdef IEM_WITH_SETJMP
3745	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
3746	#endif
3747	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
3748	#ifdef IEM_WITH_SETJMP
3749	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
3750	#endif
3751	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
3752	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3753	#ifdef IEM_WITH_SETJMP
3754	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3755	#endif
3756	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3757
3758	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
3759	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
3760	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
3761
3762	/**
3763	* Macro for calling iemCImplRaiseDivideError().
3764	*
3765	* This enables us to add/remove arguments and force different levels of
3766	* inlining as we wish.
3767	*
3768	* @return Strict VBox status code.
3769	*/
3770	#define IEMOP_RAISE_DIVIDE_ERROR() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseDivideError)
3771
3772	/**
3773	* Macro for calling iemCImplRaiseInvalidLockPrefix().
3774	*
3775	* This enables us to add/remove arguments and force different levels of
3776	* inlining as we wish.
3777	*
3778	* @return Strict VBox status code.
3779	*/
3780	#define IEMOP_RAISE_INVALID_LOCK_PREFIX() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidLockPrefix)
3781
3782	/**
3783	* Macro for calling iemCImplRaiseInvalidOpcode().
3784	*
3785	* This enables us to add/remove arguments and force different levels of
3786	* inlining as we wish.
3787	*
3788	* @return Strict VBox status code.
3789	*/
3790	#define IEMOP_RAISE_INVALID_OPCODE() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidOpcode)
3791	/** @} */
3792
3793	/** @name Register Access.
3794	* @{ */
3795	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
3796	IEMMODE enmEffOpSize) RT_NOEXCEPT;
3797	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
3798	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
3799	IEMMODE enmEffOpSize) RT_NOEXCEPT;
3800	VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
3801	VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
3802	VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
3803	/** @} */
3804
3805	/** @name FPU access and helpers.
3806	* @{ */
3807	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult) RT_NOEXCEPT;
3808	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3809	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult) RT_NOEXCEPT;
3810	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3811	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3812	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3813	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3814	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3815	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3816	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3817	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3818	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3819	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3820	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3821	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3822	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3823	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3824	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3825	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3826	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu) RT_NOEXCEPT;
3827	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3828	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu) RT_NOEXCEPT;
3829	void iemFpuStackPushOverflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3830	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3831	/** @} */
3832
3833	/** @name SSE+AVX SIMD access and helpers.
3834	* @{ */
3835	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
3836	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
3837	/** @} */
3838
3839	/** @name Memory access.
3840	* @{ */
3841
3842	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
3843	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
3844	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
3845	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
3846	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
3847	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
3848	* Users include FXSAVE & FXRSTOR. */
3849	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
3850
3851	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
3852	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
3853	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3854	#ifndef IN_RING3
3855	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3856	#endif
3857	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
3858	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
3859	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3860	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
3861
3862	#ifdef IEM_WITH_CODE_TLB
3863	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
3864	#else
3865	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
3866	#endif
3867	#ifdef IEM_WITH_SETJMP
3868	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3869	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3870	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3871	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3872	#else
3873	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
3874	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3875	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3876	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3877	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3878	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3879	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3880	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3881	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3882	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3883	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3884	#endif
3885
3886	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3887	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3888	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3889	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3890	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3891	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3892	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3893	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3894	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3895	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3896	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3897	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3898	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
3899	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
3900	#ifdef IEM_WITH_SETJMP
3901	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3902	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3903	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3904	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3905	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3906	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3907	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3908	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3909	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3910	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3911	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3912	#endif
3913
3914	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3915	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3916	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3917	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3918	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
3919
3920	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
3921	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
3922	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
3923	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
3924	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3925	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3926	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3927	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3928	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3929	#ifdef IEM_WITH_SETJMP
3930	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
3931	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
3932	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
3933	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
3934	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
3935	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
3936	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
3937	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
3938	#endif
3939
3940	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
3941	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
3942	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
3943	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
3944	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3945	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
3946	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3947	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3948	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3949	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3950	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
3951	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
3952	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
3953	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
3954	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
3955	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
3956	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
3957	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
3958	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3959	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3960	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3961	/** @} */
3962
3963	/** @name IEMAllCImpl.cpp
3964	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
3965	* @{ */
3966	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
3967	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
3968	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
3969	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
3970	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
3971	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
3972	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
3973	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
3974	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
3975	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
3976	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
3977	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
3978	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3979	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3980	IEM_CIMPL_PROTO_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3981	IEM_CIMPL_PROTO_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3982	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
3983	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
3984	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
3985	IEM_CIMPL_PROTO_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop);
3986	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
3987	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
3988	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
3989	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
3990	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
3991	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
3992	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
3993	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
3994	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
3995	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
3996	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
3997	IEM_CIMPL_PROTO_0(iemCImpl_sysret);
3998	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
3999	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
4000	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
4001	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
4002	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
4003	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
4004	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
4005	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
4006	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
4007	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4008	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4009	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4010	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4011	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
4012	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4013	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4014	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
4015	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4016	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4017	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
4018	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4019	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4020	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
4021	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
4022	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
4023	IEM_CIMPL_PROTO_0(iemCImpl_clts);
4024	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
4025	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
4026	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
4027	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
4028	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
4029	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
4030	IEM_CIMPL_PROTO_0(iemCImpl_invd);
4031	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
4032	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
4033	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
4034	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
4035	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
4036	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
4037	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
4038	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
4039	IEM_CIMPL_PROTO_1(iemCImpl_in_eAX_DX, uint8_t, cbReg);
4040	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
4041	IEM_CIMPL_PROTO_1(iemCImpl_out_DX_eAX, uint8_t, cbReg);
4042	IEM_CIMPL_PROTO_0(iemCImpl_cli);
4043	IEM_CIMPL_PROTO_0(iemCImpl_sti);
4044	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
4045	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
4046	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
4047	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
4048	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
4049	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
4050	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
4051	IEM_CIMPL_PROTO_0(iemCImpl_daa);
4052	IEM_CIMPL_PROTO_0(iemCImpl_das);
4053	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
4054	IEM_CIMPL_PROTO_0(iemCImpl_aas);
4055	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
4056	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
4057	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
4058	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
4059	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
4060	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
4061	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4062	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
4063	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4064	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4065	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4066	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4067	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4068	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4069	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4070	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4071	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4072	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4073	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4074	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
4075	IEM_CIMPL_PROTO_1(iemCImpl_fxch_underflow, uint8_t, iStReg);
4076	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop);
4077	/** @} */
4078
4079	/** @name IEMAllCImplStrInstr.cpp.h
4080	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
4081	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
4082	* @{ */
4083	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
4084	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
4085	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
4086	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
4087	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
4088	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
4089	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
4090	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
4091	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
4092	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4093	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4094
4095	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
4096	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
4097	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
4098	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
4099	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
4100	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
4101	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
4102	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
4103	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
4104	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4105	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4106
4107	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
4108	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
4109	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
4110	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
4111	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
4112	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
4113	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
4114	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
4115	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
4116	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4117	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4118
4119
4120	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
4121	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
4122	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
4123	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
4124	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
4125	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
4126	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
4127	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
4128	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
4129	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4130	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4131
4132	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
4133	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
4134	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
4135	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
4136	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
4137	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
4138	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
4139	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
4140	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
4141	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4142	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4143
4144	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
4145	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
4146	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
4147	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
4148	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
4149	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
4150	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
4151	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
4152	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
4153	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4154	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4155
4156	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
4157	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
4158	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
4159	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
4160	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
4161	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
4162	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
4163	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
4164	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
4165	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4166	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4167
4168
4169	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
4170	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
4171	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
4172	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
4173	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
4174	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
4175	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
4176	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
4177	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
4178	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4179	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4180
4181	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
4182	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
4183	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
4184	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
4185	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
4186	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
4187	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
4188	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
4189	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
4190	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4191	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4192
4193	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
4194	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
4195	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
4196	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
4197	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
4198	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
4199	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
4200	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
4201	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
4202	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4203	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4204
4205	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
4206	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
4207	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
4208	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
4209	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
4210	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
4211	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
4212	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
4213	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
4214	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4215	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4216	/** @} */
4217
4218	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4219	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
4220	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
4221	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
4222	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
4223	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
4224	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4225	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
4226	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
4227	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
4228	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
4229	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
4230	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
4231	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
4232	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4233	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4234	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4235	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4236	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4237	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4238	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
4239	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
4240	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
4241	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
4242	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
4243	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
4244	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
4245	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
4246	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
4247	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
4248	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
4249	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
4250	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
4251	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
4252	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
4253	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4254	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4255	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4256	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
4257	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
4258	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
4259	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField);
4260	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
4261	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
4262	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
4263	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
4264	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
4265	#endif
4266
4267	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4268	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
4269	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4270	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
4271	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
4272	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite) RT_NOEXCEPT;
4273	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
4274	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
4275	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
4276	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
4277	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
4278	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
4279	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
4280	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
4281	#endif
4282
4283	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
4284	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
4285	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
4286
4287
4288	extern const PFNIEMOP g_apfnOneByteMap[256];
4289
4290	/** @} */
4291
4292	RT_C_DECLS_END
4293
4294	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
4295

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 97469

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