IEMInternal.h@ 97472

Last change on this file since 97472 was 97472, checked in by vboxsync, 2 years ago
VMM/IEM: Enabled the try/throw/catch code for windows as well, results seems to indicate it's faster. bugref:9898
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1	/* $Id: IEMInternal.h 97472 2022-11-09 00:30:26Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41
42
43	RT_C_DECLS_BEGIN
44
45
46	/** @defgroup grp_iem_int Internals
47	* @ingroup grp_iem
48	* @internal
49	* @{
50	*/
51
52	/** For expanding symbol in slickedit and other products tagging and
53	* crossreferencing IEM symbols. */
54	#ifndef IEM_STATIC
55	# define IEM_STATIC static
56	#endif
57
58	/** @def IEM_WITH_SETJMP
59	* Enables alternative status code handling using setjmps.
60	*
61	* This adds a bit of expense via the setjmp() call since it saves all the
62	* non-volatile registers. However, it eliminates return code checks and allows
63	* for more optimal return value passing (return regs instead of stack buffer).
64	*/
65	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
66	# define IEM_WITH_SETJMP
67	#endif
68
69	/** @def IEM_WITH_THROW_CATCH
70	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
71	* mode code when IEM_WITH_SETJMP is in effect.
72	*
73	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
74	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
75	* result value improving by more than 1%. (Best out of three.)
76	*
77	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
78	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
79	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
80	* Linux, but it should be quite a bit faster for normal code.
81	*/
82	#if (defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
83	\|\| defined(DOXYGEN_RUNNING)
84	# define IEM_WITH_THROW_CATCH
85	#endif
86
87	/** @def IEM_DO_LONGJMP
88	*
89	* Wrapper around longjmp / throw.
90	*
91	* @param a_pVCpu The CPU handle.
92	* @param a_rc The status code jump back with / throw.
93	*/
94	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
95	# ifdef IEM_WITH_THROW_CATCH
96	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
97	# else
98	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
99	# endif
100	#endif
101
102	/** For use with IEM function that may do a longjmp (when enabled).
103	*
104	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
105	* attribute. So, we indicate that function that may be part of a longjmp may
106	* throw "exceptions" and that the compiler should definitely not generate and
107	* std::terminate calling unwind code.
108	*
109	* Here is one example of this ending in std::terminate:
110	* @code{.txt}
111	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
112	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
113	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
114	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
115	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
116	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
117	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
118	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
119	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
120	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
121	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
122	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
123	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
124	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
125	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
126	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
127	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
128	@endcode
129	*
130	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
131	*/
132	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
133	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
134	#else
135	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
136	#endif
137
138	#define IEM_IMPLEMENTS_TASKSWITCH
139
140	/** @def IEM_WITH_3DNOW
141	* Includes the 3DNow decoding. */
142	#define IEM_WITH_3DNOW
143
144	/** @def IEM_WITH_THREE_0F_38
145	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
146	#define IEM_WITH_THREE_0F_38
147
148	/** @def IEM_WITH_THREE_0F_3A
149	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
150	#define IEM_WITH_THREE_0F_3A
151
152	/** @def IEM_WITH_VEX
153	* Includes the VEX decoding. */
154	#define IEM_WITH_VEX
155
156	/** @def IEM_CFG_TARGET_CPU
157	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
158	*
159	* By default we allow this to be configured by the user via the
160	* CPUM/GuestCpuName config string, but this comes at a slight cost during
161	* decoding. So, for applications of this code where there is no need to
162	* be dynamic wrt target CPU, just modify this define.
163	*/
164	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
165	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
166	#endif
167
168	//#define IEM_WITH_CODE_TLB // - work in progress
169	//#define IEM_WITH_DATA_TLB // - work in progress
170
171
172	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
173	* Use unaligned accesses instead of elaborate byte assembly. */
174	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
175	# define IEM_USE_UNALIGNED_DATA_ACCESS
176	#endif
177
178	//#define IEM_LOG_MEMORY_WRITES
179
180	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
181	/** Instruction statistics. */
182	typedef struct IEMINSTRSTATS
183	{
184	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
185	# include "IEMInstructionStatisticsTmpl.h"
186	# undef IEM_DO_INSTR_STAT
187	} IEMINSTRSTATS;
188	#else
189	struct IEMINSTRSTATS;
190	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
191	#endif
192	/** Pointer to IEM instruction statistics. */
193	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
194
195
196	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
197	* @{ */
198	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
199	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
200	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
201	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
202	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
203	/** Selects the right variant from a_aArray.
204	* pVCpu is implicit in the caller context. */
205	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
206	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
207	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
208	* be used because the host CPU does not support the operation. */
209	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
210	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
211	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
212	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
213	* into the two.
214	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
215	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
216	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
217	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
218	#else
219	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
220	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
221	#endif
222	/** @} */
223
224	/**
225	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
226	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
227	*
228	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
229	* indicator.
230	*
231	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
232	*/
233	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
234	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
235	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
236	#else
237	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
238	#endif
239
240
241	/**
242	* Extended operand mode that includes a representation of 8-bit.
243	*
244	* This is used for packing down modes when invoking some C instruction
245	* implementations.
246	*/
247	typedef enum IEMMODEX
248	{
249	IEMMODEX_16BIT = IEMMODE_16BIT,
250	IEMMODEX_32BIT = IEMMODE_32BIT,
251	IEMMODEX_64BIT = IEMMODE_64BIT,
252	IEMMODEX_8BIT
253	} IEMMODEX;
254	AssertCompileSize(IEMMODEX, 4);
255
256
257	/**
258	* Branch types.
259	*/
260	typedef enum IEMBRANCH
261	{
262	IEMBRANCH_JUMP = 1,
263	IEMBRANCH_CALL,
264	IEMBRANCH_TRAP,
265	IEMBRANCH_SOFTWARE_INT,
266	IEMBRANCH_HARDWARE_INT
267	} IEMBRANCH;
268	AssertCompileSize(IEMBRANCH, 4);
269
270
271	/**
272	* INT instruction types.
273	*/
274	typedef enum IEMINT
275	{
276	/** INT n instruction (opcode 0xcd imm). */
277	IEMINT_INTN = 0,
278	/** Single byte INT3 instruction (opcode 0xcc). */
279	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
280	/** Single byte INTO instruction (opcode 0xce). */
281	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
282	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
283	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
284	} IEMINT;
285	AssertCompileSize(IEMINT, 4);
286
287
288	/**
289	* A FPU result.
290	*/
291	typedef struct IEMFPURESULT
292	{
293	/** The output value. */
294	RTFLOAT80U r80Result;
295	/** The output status. */
296	uint16_t FSW;
297	} IEMFPURESULT;
298	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
299	/** Pointer to a FPU result. */
300	typedef IEMFPURESULT *PIEMFPURESULT;
301	/** Pointer to a const FPU result. */
302	typedef IEMFPURESULT const *PCIEMFPURESULT;
303
304
305	/**
306	* A FPU result consisting of two output values and FSW.
307	*/
308	typedef struct IEMFPURESULTTWO
309	{
310	/** The first output value. */
311	RTFLOAT80U r80Result1;
312	/** The output status. */
313	uint16_t FSW;
314	/** The second output value. */
315	RTFLOAT80U r80Result2;
316	} IEMFPURESULTTWO;
317	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
318	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
319	/** Pointer to a FPU result consisting of two output values and FSW. */
320	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
321	/** Pointer to a const FPU result consisting of two output values and FSW. */
322	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
323
324
325	/**
326	* IEM TLB entry.
327	*
328	* Lookup assembly:
329	* @code{.asm}
330	; Calculate tag.
331	mov rax, [VA]
332	shl rax, 16
333	shr rax, 16 + X86_PAGE_SHIFT
334	or rax, [uTlbRevision]
335
336	; Do indexing.
337	movzx ecx, al
338	lea rcx, [pTlbEntries + rcx]
339
340	; Check tag.
341	cmp [rcx + IEMTLBENTRY.uTag], rax
342	jne .TlbMiss
343
344	; Check access.
345	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
346	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
347	cmp rax, [uTlbPhysRev]
348	jne .TlbMiss
349
350	; Calc address and we're done.
351	mov eax, X86_PAGE_OFFSET_MASK
352	and eax, [VA]
353	or rax, [rcx + IEMTLBENTRY.pMappingR3]
354	%ifdef VBOX_WITH_STATISTICS
355	inc qword [cTlbHits]
356	%endif
357	jmp .Done
358
359	.TlbMiss:
360	mov r8d, ACCESS_FLAGS
361	mov rdx, [VA]
362	mov rcx, [pVCpu]
363	call iemTlbTypeMiss
364	.Done:
365
366	@endcode
367	*
368	*/
369	typedef struct IEMTLBENTRY
370	{
371	/** The TLB entry tag.
372	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
373	* is ASSUMING a virtual address width of 48 bits.
374	*
375	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
376	*
377	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
378	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
379	* revision wraps around though, the tags needs to be zeroed.
380	*
381	* @note Try use SHRD instruction? After seeing
382	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
383	*
384	* @todo This will need to be reorganized for 57-bit wide virtual address and
385	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
386	* have to move the TLB entry versioning entirely to the
387	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
388	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
389	* consumed by PCID and ASID (12 + 6 = 18).
390	*/
391	uint64_t uTag;
392	/** Access flags and physical TLB revision.
393	*
394	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
395	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
396	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
397	* - Bit 3 - pgm phys/virt - not directly writable.
398	* - Bit 4 - pgm phys page - not directly readable.
399	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
400	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
401	* - Bit 7 - tlb entry - pMappingR3 member not valid.
402	* - Bits 63 thru 8 are used for the physical TLB revision number.
403	*
404	* We're using complemented bit meanings here because it makes it easy to check
405	* whether special action is required. For instance a user mode write access
406	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
407	* non-zero result would mean special handling needed because either it wasn't
408	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
409	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
410	* need to check any PTE flag.
411	*/
412	uint64_t fFlagsAndPhysRev;
413	/** The guest physical page address. */
414	uint64_t GCPhys;
415	/** Pointer to the ring-3 mapping. */
416	R3PTRTYPE(uint8_t *) pbMappingR3;
417	#if HC_ARCH_BITS == 32
418	uint32_t u32Padding1;
419	#endif
420	} IEMTLBENTRY;
421	AssertCompileSize(IEMTLBENTRY, 32);
422	/** Pointer to an IEM TLB entry. */
423	typedef IEMTLBENTRY *PIEMTLBENTRY;
424
425	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
426	* @{ */
427	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
428	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
429	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
430	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
431	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
432	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
433	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
434	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
435	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
436	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
437	/** @} */
438
439
440	/**
441	* An IEM TLB.
442	*
443	* We've got two of these, one for data and one for instructions.
444	*/
445	typedef struct IEMTLB
446	{
447	/** The TLB entries.
448	* We've choosen 256 because that way we can obtain the result directly from a
449	* 8-bit register without an additional AND instruction. */
450	IEMTLBENTRY aEntries[256];
451	/** The TLB revision.
452	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
453	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
454	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
455	* (The revision zero indicates an invalid TLB entry.)
456	*
457	* The initial value is choosen to cause an early wraparound. */
458	uint64_t uTlbRevision;
459	/** The TLB physical address revision - shadow of PGM variable.
460	*
461	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
462	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
463	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
464	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
465	*
466	* The initial value is choosen to cause an early wraparound. */
467	uint64_t volatile uTlbPhysRev;
468
469	/* Statistics: */
470
471	/** TLB hits (VBOX_WITH_STATISTICS only). */
472	uint64_t cTlbHits;
473	/** TLB misses. */
474	uint32_t cTlbMisses;
475	/** Slow read path. */
476	uint32_t cTlbSlowReadPath;
477	#if 0
478	/** TLB misses because of tag mismatch. */
479	uint32_t cTlbMissesTag;
480	/** TLB misses because of virtual access violation. */
481	uint32_t cTlbMissesVirtAccess;
482	/** TLB misses because of dirty bit. */
483	uint32_t cTlbMissesDirty;
484	/** TLB misses because of MMIO */
485	uint32_t cTlbMissesMmio;
486	/** TLB misses because of write access handlers. */
487	uint32_t cTlbMissesWriteHandler;
488	/** TLB misses because no r3(/r0) mapping. */
489	uint32_t cTlbMissesMapping;
490	#endif
491	/** Alignment padding. */
492	uint32_t au32Padding[3+5];
493	} IEMTLB;
494	AssertCompileSizeAlignment(IEMTLB, 64);
495	/** IEMTLB::uTlbRevision increment. */
496	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
497	/** IEMTLB::uTlbRevision mask. */
498	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
499	/** IEMTLB::uTlbPhysRev increment.
500	* @sa IEMTLBE_F_PHYS_REV */
501	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
502	/**
503	* Calculates the TLB tag for a virtual address.
504	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
505	* @param a_pTlb The TLB.
506	* @param a_GCPtr The virtual address.
507	*/
508	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
509	/**
510	* Calculates the TLB tag for a virtual address but without TLB revision.
511	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
512	* @param a_GCPtr The virtual address.
513	*/
514	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
515	/**
516	* Converts a TLB tag value into a TLB index.
517	* @returns Index into IEMTLB::aEntries.
518	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
519	*/
520	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
521	/**
522	* Converts a TLB tag value into a TLB index.
523	* @returns Index into IEMTLB::aEntries.
524	* @param a_pTlb The TLB.
525	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
526	*/
527	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
528
529
530	/**
531	* The per-CPU IEM state.
532	*/
533	typedef struct IEMCPU
534	{
535	/** Info status code that needs to be propagated to the IEM caller.
536	* This cannot be passed internally, as it would complicate all success
537	* checks within the interpreter making the code larger and almost impossible
538	* to get right. Instead, we'll store status codes to pass on here. Each
539	* source of these codes will perform appropriate sanity checks. */
540	int32_t rcPassUp; /* 0x00 */
541
542	/** The current CPU execution mode (CS). */
543	IEMMODE enmCpuMode; /* 0x04 */
544	/** The CPL. */
545	uint8_t uCpl; /* 0x05 */
546
547	/** Whether to bypass access handlers or not. */
548	bool fBypassHandlers; /* 0x06 */
549	/** Whether to disregard the lock prefix (implied or not). */
550	bool fDisregardLock; /* 0x07 */
551
552	/** @name Decoder state.
553	* @{ */
554	#ifdef IEM_WITH_CODE_TLB
555	/** The offset of the next instruction byte. */
556	uint32_t offInstrNextByte; /* 0x08 */
557	/** The number of bytes available at pbInstrBuf for the current instruction.
558	* This takes the max opcode length into account so that doesn't need to be
559	* checked separately. */
560	uint32_t cbInstrBuf; /* 0x0c */
561	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
562	* This can be NULL if the page isn't mappable for some reason, in which
563	* case we'll do fallback stuff.
564	*
565	* If we're executing an instruction from a user specified buffer,
566	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
567	* aligned pointer but pointer to the user data.
568	*
569	* For instructions crossing pages, this will start on the first page and be
570	* advanced to the next page by the time we've decoded the instruction. This
571	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
572	*/
573	uint8_t const pbInstrBuf; / 0x10 */
574	# if ARCH_BITS == 32
575	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
576	# endif
577	/** The program counter corresponding to pbInstrBuf.
578	* This is set to a non-canonical address when we need to invalidate it. */
579	uint64_t uInstrBufPc; /* 0x18 */
580	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
581	* This takes the CS segment limit into account. */
582	uint16_t cbInstrBufTotal; /* 0x20 */
583	/** Offset into pbInstrBuf of the first byte of the current instruction.
584	* Can be negative to efficiently handle cross page instructions. */
585	int16_t offCurInstrStart; /* 0x22 */
586
587	/** The prefix mask (IEM_OP_PRF_XXX). */
588	uint32_t fPrefixes; /* 0x24 */
589	/** The extra REX ModR/M register field bit (REX.R << 3). */
590	uint8_t uRexReg; /* 0x28 */
591	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
592	* (REX.B << 3). */
593	uint8_t uRexB; /* 0x29 */
594	/** The extra REX SIB index field bit (REX.X << 3). */
595	uint8_t uRexIndex; /* 0x2a */
596
597	/** The effective segment register (X86_SREG_XXX). */
598	uint8_t iEffSeg; /* 0x2b */
599
600	/** The offset of the ModR/M byte relative to the start of the instruction. */
601	uint8_t offModRm; /* 0x2c */
602	#else
603	/** The size of what has currently been fetched into abOpcode. */
604	uint8_t cbOpcode; /* 0x08 */
605	/** The current offset into abOpcode. */
606	uint8_t offOpcode; /* 0x09 */
607	/** The offset of the ModR/M byte relative to the start of the instruction. */
608	uint8_t offModRm; /* 0x0a */
609
610	/** The effective segment register (X86_SREG_XXX). */
611	uint8_t iEffSeg; /* 0x0b */
612
613	/** The prefix mask (IEM_OP_PRF_XXX). */
614	uint32_t fPrefixes; /* 0x0c */
615	/** The extra REX ModR/M register field bit (REX.R << 3). */
616	uint8_t uRexReg; /* 0x10 */
617	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
618	* (REX.B << 3). */
619	uint8_t uRexB; /* 0x11 */
620	/** The extra REX SIB index field bit (REX.X << 3). */
621	uint8_t uRexIndex; /* 0x12 */
622
623	#endif
624
625	/** The effective operand mode. */
626	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
627	/** The default addressing mode. */
628	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
629	/** The effective addressing mode. */
630	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
631	/** The default operand mode. */
632	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
633
634	/** Prefix index (VEX.pp) for two byte and three byte tables. */
635	uint8_t idxPrefix; /* 0x31, 0x17 */
636	/** 3rd VEX/EVEX/XOP register.
637	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
638	uint8_t uVex3rdReg; /* 0x32, 0x18 */
639	/** The VEX/EVEX/XOP length field. */
640	uint8_t uVexLength; /* 0x33, 0x19 */
641	/** Additional EVEX stuff. */
642	uint8_t fEvexStuff; /* 0x34, 0x1a */
643
644	/** Explicit alignment padding. */
645	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
646	/** The FPU opcode (FOP). */
647	uint16_t uFpuOpcode; /* 0x36, 0x1c */
648	#ifndef IEM_WITH_CODE_TLB
649	/** Explicit alignment padding. */
650	uint8_t abAlignment2b[2]; /* 0x1e */
651	#endif
652
653	/** The opcode bytes. */
654	uint8_t abOpcode[15]; /* 0x48, 0x20 */
655	/** Explicit alignment padding. */
656	#ifdef IEM_WITH_CODE_TLB
657	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
658	#else
659	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
660	#endif
661	/** @} */
662
663
664	/** The flags of the current exception / interrupt. */
665	uint32_t fCurXcpt; /* 0x48, 0x48 */
666	/** The current exception / interrupt. */
667	uint8_t uCurXcpt;
668	/** Exception / interrupt recursion depth. */
669	int8_t cXcptRecursions;
670
671	/** The number of active guest memory mappings. */
672	uint8_t cActiveMappings;
673	/** The next unused mapping index. */
674	uint8_t iNextMapping;
675	/** Records for tracking guest memory mappings. */
676	struct
677	{
678	/** The address of the mapped bytes. */
679	void *pv;
680	/** The access flags (IEM_ACCESS_XXX).
681	* IEM_ACCESS_INVALID if the entry is unused. */
682	uint32_t fAccess;
683	#if HC_ARCH_BITS == 64
684	uint32_t u32Alignment4; /*< Alignment padding. /
685	#endif
686	} aMemMappings[3];
687
688	/** Locking records for the mapped memory. */
689	union
690	{
691	PGMPAGEMAPLOCK Lock;
692	uint64_t au64Padding[2];
693	} aMemMappingLocks[3];
694
695	/** Bounce buffer info.
696	* This runs in parallel to aMemMappings. */
697	struct
698	{
699	/** The physical address of the first byte. */
700	RTGCPHYS GCPhysFirst;
701	/** The physical address of the second page. */
702	RTGCPHYS GCPhysSecond;
703	/** The number of bytes in the first page. */
704	uint16_t cbFirst;
705	/** The number of bytes in the second page. */
706	uint16_t cbSecond;
707	/** Whether it's unassigned memory. */
708	bool fUnassigned;
709	/** Explicit alignment padding. */
710	bool afAlignment5[3];
711	} aMemBbMappings[3];
712
713	/* Ensure that aBounceBuffers are aligned at a 32 byte boundrary. */
714	uint64_t abAlignment7[1];
715
716	/** Bounce buffer storage.
717	* This runs in parallel to aMemMappings and aMemBbMappings. */
718	struct
719	{
720	uint8_t ab[512];
721	} aBounceBuffers[3];
722
723
724	/** Pointer set jump buffer - ring-3 context. */
725	R3PTRTYPE(jmp_buf *) pJmpBufR3;
726	/** Pointer set jump buffer - ring-0 context. */
727	R0PTRTYPE(jmp_buf *) pJmpBufR0;
728
729	/** @todo Should move this near @a fCurXcpt later. */
730	/** The CR2 for the current exception / interrupt. */
731	uint64_t uCurXcptCr2;
732	/** The error code for the current exception / interrupt. */
733	uint32_t uCurXcptErr;
734
735	/** @name Statistics
736	* @{ */
737	/** The number of instructions we've executed. */
738	uint32_t cInstructions;
739	/** The number of potential exits. */
740	uint32_t cPotentialExits;
741	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
742	* This may contain uncommitted writes. */
743	uint32_t cbWritten;
744	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
745	uint32_t cRetInstrNotImplemented;
746	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
747	uint32_t cRetAspectNotImplemented;
748	/** Counts informational statuses returned (other than VINF_SUCCESS). */
749	uint32_t cRetInfStatuses;
750	/** Counts other error statuses returned. */
751	uint32_t cRetErrStatuses;
752	/** Number of times rcPassUp has been used. */
753	uint32_t cRetPassUpStatus;
754	/** Number of times RZ left with instruction commit pending for ring-3. */
755	uint32_t cPendingCommit;
756	/** Number of long jumps. */
757	uint32_t cLongJumps;
758	/** @} */
759
760	/** @name Target CPU information.
761	* @{ */
762	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
763	/** The target CPU. */
764	uint8_t uTargetCpu;
765	#else
766	uint8_t bTargetCpuPadding;
767	#endif
768	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
769	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
770	* native host support and the 2nd for when there is.
771	*
772	* The two values are typically indexed by a g_CpumHostFeatures bit.
773	*
774	* This is for instance used for the BSF & BSR instructions where AMD and
775	* Intel CPUs produce different EFLAGS. */
776	uint8_t aidxTargetCpuEflFlavour[2];
777
778	/** The CPU vendor. */
779	CPUMCPUVENDOR enmCpuVendor;
780	/** @} */
781
782	/** @name Host CPU information.
783	* @{ */
784	/** The CPU vendor. */
785	CPUMCPUVENDOR enmHostCpuVendor;
786	/** @} */
787
788	/** Counts RDMSR \#GP(0) LogRel(). */
789	uint8_t cLogRelRdMsr;
790	/** Counts WRMSR \#GP(0) LogRel(). */
791	uint8_t cLogRelWrMsr;
792	/** Alignment padding. */
793	uint8_t abAlignment8[42];
794
795	/** Data TLB.
796	* @remarks Must be 64-byte aligned. */
797	IEMTLB DataTlb;
798	/** Instruction TLB.
799	* @remarks Must be 64-byte aligned. */
800	IEMTLB CodeTlb;
801
802	/** Exception statistics. */
803	STAMCOUNTER aStatXcpts[32];
804	/** Interrupt statistics. */
805	uint32_t aStatInts[256];
806
807	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
808	/** Instruction statistics for ring-0/raw-mode. */
809	IEMINSTRSTATS StatsRZ;
810	/** Instruction statistics for ring-3. */
811	IEMINSTRSTATS StatsR3;
812	#endif
813	} IEMCPU;
814	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
815	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 8);
816	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 16);
817	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 32);
818	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
819	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
820	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
821
822	/** Pointer to the per-CPU IEM state. */
823	typedef IEMCPU *PIEMCPU;
824	/** Pointer to the const per-CPU IEM state. */
825	typedef IEMCPU const *PCIEMCPU;
826
827
828	/** @def IEM_GET_CTX
829	* Gets the guest CPU context for the calling EMT.
830	* @returns PCPUMCTX
831	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
832	*/
833	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
834
835	/** @def IEM_CTX_ASSERT
836	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
837	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
838	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
839	*/
840	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
841	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
842	(a_fExtrnMbz)))
843
844	/** @def IEM_CTX_IMPORT_RET
845	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
846	*
847	* Will call the keep to import the bits as needed.
848	*
849	* Returns on import failure.
850	*
851	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
852	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
853	*/
854	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
855	do { \
856	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
857	{ /* likely */ } \
858	else \
859	{ \
860	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
861	AssertRCReturn(rcCtxImport, rcCtxImport); \
862	} \
863	} while (0)
864
865	/** @def IEM_CTX_IMPORT_NORET
866	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
867	*
868	* Will call the keep to import the bits as needed.
869	*
870	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
871	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
872	*/
873	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
874	do { \
875	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
876	{ /* likely */ } \
877	else \
878	{ \
879	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
880	AssertLogRelRC(rcCtxImport); \
881	} \
882	} while (0)
883
884	/** @def IEM_CTX_IMPORT_JMP
885	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
886	*
887	* Will call the keep to import the bits as needed.
888	*
889	* Jumps on import failure.
890	*
891	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
892	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
893	*/
894	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
895	do { \
896	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
897	{ /* likely */ } \
898	else \
899	{ \
900	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
901	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
902	} \
903	} while (0)
904
905
906
907	/** @def IEM_GET_TARGET_CPU
908	* Gets the current IEMTARGETCPU value.
909	* @returns IEMTARGETCPU value.
910	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
911	*/
912	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
913	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
914	#else
915	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
916	#endif
917
918	/** @def IEM_GET_INSTR_LEN
919	* Gets the instruction length. */
920	#ifdef IEM_WITH_CODE_TLB
921	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
922	#else
923	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
924	#endif
925
926
927	/**
928	* Shared per-VM IEM data.
929	*/
930	typedef struct IEM
931	{
932	/** The VMX APIC-access page handler type. */
933	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
934	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
935	/** Set if the CPUID host call functionality is enabled. */
936	bool fCpuIdHostCall;
937	#endif
938	} IEM;
939
940
941
942	/** @name IEM_ACCESS_XXX - Access details.
943	* @{ */
944	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
945	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
946	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
947	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
948	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
949	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
950	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
951	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
952	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
953	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
954	/** The writes are partial, so if initialize the bounce buffer with the
955	* orignal RAM content. */
956	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
957	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
958	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
959	/** Bounce buffer with ring-3 write pending, first page. */
960	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
961	/** Bounce buffer with ring-3 write pending, second page. */
962	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
963	/** Not locked, accessed via the TLB. */
964	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
965	/** Valid bit mask. */
966	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
967	/** Shift count for the TLB flags (upper word). */
968	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
969
970	/** Read+write data alias. */
971	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
972	/** Write data alias. */
973	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
974	/** Read data alias. */
975	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
976	/** Instruction fetch alias. */
977	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
978	/** Stack write alias. */
979	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
980	/** Stack read alias. */
981	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
982	/** Stack read+write alias. */
983	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
984	/** Read system table alias. */
985	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
986	/** Read+write system table alias. */
987	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
988	/** @} */
989
990	/** @name Prefix constants (IEMCPU::fPrefixes)
991	* @{ */
992	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
993	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
994	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
995	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
996	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
997	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
998	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
999
1000	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
1001	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
1002	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
1003
1004	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
1005	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
1006	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
1007
1008	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
1009	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
1010	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
1011	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
1012	/** Mask with all the REX prefix flags.
1013	* This is generally for use when needing to undo the REX prefixes when they
1014	* are followed legacy prefixes and therefore does not immediately preceed
1015	* the first opcode byte.
1016	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
1017	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
1018
1019	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
1020	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
1021	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
1022	/** @} */
1023
1024	/** @name IEMOPFORM_XXX - Opcode forms
1025	* @note These are ORed together with IEMOPHINT_XXX.
1026	* @{ */
1027	/** ModR/M: reg, r/m */
1028	#define IEMOPFORM_RM 0
1029	/** ModR/M: reg, r/m (register) */
1030	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1031	/** ModR/M: reg, r/m (memory) */
1032	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1033	/** ModR/M: reg, r/m */
1034	#define IEMOPFORM_RMI 1
1035	/** ModR/M: reg, r/m (register) */
1036	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1037	/** ModR/M: reg, r/m (memory) */
1038	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1039	/** ModR/M: r/m, reg */
1040	#define IEMOPFORM_MR 2
1041	/** ModR/M: r/m (register), reg */
1042	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1043	/** ModR/M: r/m (memory), reg */
1044	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1045	/** ModR/M: r/m only */
1046	#define IEMOPFORM_M 3
1047	/** ModR/M: r/m only (register). */
1048	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
1049	/** ModR/M: r/m only (memory). */
1050	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
1051	/** ModR/M: reg only */
1052	#define IEMOPFORM_R 4
1053
1054	/** VEX+ModR/M: reg, r/m */
1055	#define IEMOPFORM_VEX_RM 8
1056	/** VEX+ModR/M: reg, r/m (register) */
1057	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
1058	/** VEX+ModR/M: reg, r/m (memory) */
1059	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
1060	/** VEX+ModR/M: r/m, reg */
1061	#define IEMOPFORM_VEX_MR 9
1062	/** VEX+ModR/M: r/m (register), reg */
1063	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
1064	/** VEX+ModR/M: r/m (memory), reg */
1065	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
1066	/** VEX+ModR/M: r/m only */
1067	#define IEMOPFORM_VEX_M 10
1068	/** VEX+ModR/M: r/m only (register). */
1069	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
1070	/** VEX+ModR/M: r/m only (memory). */
1071	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
1072	/** VEX+ModR/M: reg only */
1073	#define IEMOPFORM_VEX_R 11
1074	/** VEX+ModR/M: reg, vvvv, r/m */
1075	#define IEMOPFORM_VEX_RVM 12
1076	/** VEX+ModR/M: reg, vvvv, r/m (register). */
1077	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
1078	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
1079	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
1080	/** VEX+ModR/M: reg, r/m, vvvv */
1081	#define IEMOPFORM_VEX_RMV 13
1082	/** VEX+ModR/M: reg, r/m, vvvv (register). */
1083	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
1084	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1085	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
1086	/** VEX+ModR/M: reg, r/m, imm8 */
1087	#define IEMOPFORM_VEX_RMI 14
1088	/** VEX+ModR/M: reg, r/m, imm8 (register). */
1089	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
1090	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1091	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1092	/** VEX+ModR/M: r/m, vvvv, reg */
1093	#define IEMOPFORM_VEX_MVR 15
1094	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1095	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1096	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1097	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1098	/** VEX+ModR/M+/n: vvvv, r/m */
1099	#define IEMOPFORM_VEX_VM 16
1100	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1101	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1102	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1103	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1104
1105	/** Fixed register instruction, no R/M. */
1106	#define IEMOPFORM_FIXED 32
1107
1108	/** The r/m is a register. */
1109	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1110	/** The r/m is a memory access. */
1111	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1112	/** @} */
1113
1114	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1115	* @note These are ORed together with IEMOPFORM_XXX.
1116	* @{ */
1117	/** Ignores the operand size prefix (66h). */
1118	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1119	/** Ignores REX.W (aka WIG). */
1120	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1121	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1122	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1123	/** Allowed with the lock prefix. */
1124	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1125	/** The VEX.L value is ignored (aka LIG). */
1126	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1127	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1128	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1129	/** The VEX.V value must be zero. */
1130	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1131
1132	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1133	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1134	/** @} */
1135
1136	/**
1137	* Possible hardware task switch sources.
1138	*/
1139	typedef enum IEMTASKSWITCH
1140	{
1141	/** Task switch caused by an interrupt/exception. */
1142	IEMTASKSWITCH_INT_XCPT = 1,
1143	/** Task switch caused by a far CALL. */
1144	IEMTASKSWITCH_CALL,
1145	/** Task switch caused by a far JMP. */
1146	IEMTASKSWITCH_JUMP,
1147	/** Task switch caused by an IRET. */
1148	IEMTASKSWITCH_IRET
1149	} IEMTASKSWITCH;
1150	AssertCompileSize(IEMTASKSWITCH, 4);
1151
1152	/**
1153	* Possible CrX load (write) sources.
1154	*/
1155	typedef enum IEMACCESSCRX
1156	{
1157	/** CrX access caused by 'mov crX' instruction. */
1158	IEMACCESSCRX_MOV_CRX,
1159	/** CrX (CR0) write caused by 'lmsw' instruction. */
1160	IEMACCESSCRX_LMSW,
1161	/** CrX (CR0) write caused by 'clts' instruction. */
1162	IEMACCESSCRX_CLTS,
1163	/** CrX (CR0) read caused by 'smsw' instruction. */
1164	IEMACCESSCRX_SMSW
1165	} IEMACCESSCRX;
1166
1167	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1168	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1169	*
1170	* These flags provide further context to SLAT page-walk failures that could not be
1171	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1172	*
1173	* @{
1174	*/
1175	/** Translating a nested-guest linear address failed accessing a nested-guest
1176	* physical address. */
1177	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1178	/** Translating a nested-guest linear address failed accessing a
1179	* paging-structure entry or updating accessed/dirty bits. */
1180	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1181	/** @} */
1182
1183	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1184	# ifndef IN_RING3
1185	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1186	# endif
1187	#endif
1188
1189	/**
1190	* Indicates to the verifier that the given flag set is undefined.
1191	*
1192	* Can be invoked again to add more flags.
1193	*
1194	* This is a NOOP if the verifier isn't compiled in.
1195	*
1196	* @note We're temporarily keeping this until code is converted to new
1197	* disassembler style opcode handling.
1198	*/
1199	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1200
1201
1202	/** @def IEM_DECL_IMPL_TYPE
1203	* For typedef'ing an instruction implementation function.
1204	*
1205	* @param a_RetType The return type.
1206	* @param a_Name The name of the type.
1207	* @param a_ArgList The argument list enclosed in parentheses.
1208	*/
1209
1210	/** @def IEM_DECL_IMPL_DEF
1211	* For defining an instruction implementation function.
1212	*
1213	* @param a_RetType The return type.
1214	* @param a_Name The name of the type.
1215	* @param a_ArgList The argument list enclosed in parentheses.
1216	*/
1217
1218	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1219	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1220	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1221	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1222	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1223	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1224	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1225
1226	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1227	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1228	a_RetType (__fastcall a_Name) a_ArgList
1229	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1230	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1231	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1232	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1233
1234	#elif __cplusplus >= 201700 /* P0012R1 support */
1235	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1236	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1237	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1238	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1239	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1240	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1241
1242	#else
1243	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1244	a_RetType (VBOXCALL a_Name) a_ArgList
1245	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1246	a_RetType VBOXCALL a_Name a_ArgList
1247	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1248	a_RetType VBOXCALL a_Name a_ArgList
1249
1250	#endif
1251
1252	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1253	RT_C_DECLS_BEGIN
1254	extern uint8_t const g_afParity[256];
1255	RT_C_DECLS_END
1256
1257
1258	/** @name Arithmetic assignment operations on bytes (binary).
1259	* @{ */
1260	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1261	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1262	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1263	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1264	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1265	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1266	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1267	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1268	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1269	/** @} */
1270
1271	/** @name Arithmetic assignment operations on words (binary).
1272	* @{ */
1273	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1274	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1275	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1276	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1277	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1278	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1279	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1280	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1281	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1282	/** @} */
1283
1284	/** @name Arithmetic assignment operations on double words (binary).
1285	* @{ */
1286	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1287	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1288	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1289	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1290	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1291	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1292	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1293	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1294	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1295	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1296	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1297	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1298	/** @} */
1299
1300	/** @name Arithmetic assignment operations on quad words (binary).
1301	* @{ */
1302	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1303	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1304	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1305	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1306	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1307	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1308	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1309	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1310	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1311	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1312	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1313	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1314	/** @} */
1315
1316	/** @name Compare operations (thrown in with the binary ops).
1317	* @{ */
1318	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1319	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1320	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1321	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1322	/** @} */
1323
1324	/** @name Test operations (thrown in with the binary ops).
1325	* @{ */
1326	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1327	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1328	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1329	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1330	/** @} */
1331
1332	/** @name Bit operations operations (thrown in with the binary ops).
1333	* @{ */
1334	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1335	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1336	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1337	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1338	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1339	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1340	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1341	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1342	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1343	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1344	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1345	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1346	/** @} */
1347
1348	/** @name Arithmetic three operand operations on double words (binary).
1349	* @{ */
1350	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
1351	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1352	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1353	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1354	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1355	/** @} */
1356
1357	/** @name Arithmetic three operand operations on quad words (binary).
1358	* @{ */
1359	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
1360	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1361	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1362	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1363	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1364	/** @} */
1365
1366	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1367	* @{ */
1368	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1369	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1370	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1371	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1372	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1373	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1374	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1375	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1376	/** @} */
1377
1378	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1379	* @{ */
1380	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1381	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1382	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1383	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1384	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1385	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1386	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1387	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1388	/** @} */
1389
1390	/** @name MULX 32-bit and 64-bit.
1391	* @{ */
1392	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
1393	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1394	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1395
1396	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
1397	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1398	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1399	/** @} */
1400
1401
1402	/** @name Exchange memory with register operations.
1403	* @{ */
1404	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1405	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1406	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1407	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1408	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1409	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1410	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1411	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1412	/** @} */
1413
1414	/** @name Exchange and add operations.
1415	* @{ */
1416	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1417	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1418	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1419	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1420	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1421	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1422	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1423	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1424	/** @} */
1425
1426	/** @name Compare and exchange.
1427	* @{ */
1428	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1429	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1430	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1431	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1432	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1433	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1434	#if ARCH_BITS == 32
1435	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1436	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1437	#else
1438	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1439	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1440	#endif
1441	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1442	uint32_t *pEFlags));
1443	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1444	uint32_t *pEFlags));
1445	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1446	uint32_t *pEFlags));
1447	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1448	uint32_t *pEFlags));
1449	#ifndef RT_ARCH_ARM64
1450	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1451	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1452	#endif
1453	/** @} */
1454
1455	/** @name Memory ordering
1456	* @{ */
1457	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1458	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1459	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1460	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1461	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1462	#ifndef RT_ARCH_ARM64
1463	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1464	#endif
1465	/** @} */
1466
1467	/** @name Double precision shifts
1468	* @{ */
1469	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1470	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1471	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1472	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1473	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1474	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1475	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1476	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1477	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1478	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1479	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1480	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1481	/** @} */
1482
1483
1484	/** @name Bit search operations (thrown in with the binary ops).
1485	* @{ */
1486	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1487	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1488	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1489	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1490	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1491	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1492	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1493	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1494	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1495	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
1496	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
1497	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
1498	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
1499	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
1500	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
1501	/** @} */
1502
1503	/** @name Signed multiplication operations (thrown in with the binary ops).
1504	* @{ */
1505	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1506	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1507	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1508	/** @} */
1509
1510	/** @name Arithmetic assignment operations on bytes (unary).
1511	* @{ */
1512	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1513	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1514	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1515	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1516	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1517	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1518	/** @} */
1519
1520	/** @name Arithmetic assignment operations on words (unary).
1521	* @{ */
1522	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1523	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1524	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1525	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1526	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1527	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1528	/** @} */
1529
1530	/** @name Arithmetic assignment operations on double words (unary).
1531	* @{ */
1532	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1533	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1534	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1535	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1536	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1537	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1538	/** @} */
1539
1540	/** @name Arithmetic assignment operations on quad words (unary).
1541	* @{ */
1542	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1543	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1544	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1545	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1546	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1547	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1548	/** @} */
1549
1550
1551	/** @name Shift operations on bytes (Group 2).
1552	* @{ */
1553	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1554	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1555	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1556	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1557	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1558	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1559	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1560	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1561	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1562	/** @} */
1563
1564	/** @name Shift operations on words (Group 2).
1565	* @{ */
1566	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1567	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1568	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1569	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1570	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1571	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1572	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1573	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1574	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1575	/** @} */
1576
1577	/** @name Shift operations on double words (Group 2).
1578	* @{ */
1579	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1580	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1581	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1582	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1583	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1584	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1585	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1586	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1587	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1588	/** @} */
1589
1590	/** @name Shift operations on words (Group 2).
1591	* @{ */
1592	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1593	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1594	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1595	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1596	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1597	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1598	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1599	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1600	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1601	/** @} */
1602
1603	/** @name Multiplication and division operations.
1604	* @{ */
1605	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1606	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1607	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1608	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1609	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1610	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1611
1612	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1613	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1614	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1615	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1616	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1617	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1618
1619	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1620	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1621	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1622	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1623	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1624	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1625
1626	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1627	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1628	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1629	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1630	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1631	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1632	/** @} */
1633
1634	/** @name Byte Swap.
1635	* @{ */
1636	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1637	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1638	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1639	/** @} */
1640
1641	/** @name Misc.
1642	* @{ */
1643	FNIEMAIMPLBINU16 iemAImpl_arpl;
1644	/** @} */
1645
1646	/** @name RDRAND and RDSEED
1647	* @{ */
1648	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
1649	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
1650	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
1651	typedef FNIEMAIMPLRDRANDSEEDU16 *FNIEMAIMPLPRDRANDSEEDU16;
1652	typedef FNIEMAIMPLRDRANDSEEDU32 *FNIEMAIMPLPRDRANDSEEDU32;
1653	typedef FNIEMAIMPLRDRANDSEEDU64 *FNIEMAIMPLPRDRANDSEEDU64;
1654
1655	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
1656	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
1657	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
1658	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
1659	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
1660	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
1661	/** @} */
1662
1663	/** @name FPU operations taking a 32-bit float argument
1664	* @{ */
1665	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1666	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1667	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1668
1669	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1670	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1671	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1672
1673	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1674	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1675	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1676	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1677	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1678	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1679	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1680
1681	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1682	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1683	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1684	/** @} */
1685
1686	/** @name FPU operations taking a 64-bit float argument
1687	* @{ */
1688	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1689	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1690	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
1691
1692	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1693	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1694	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1695
1696	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
1697	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1698	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1699	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1700	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1701	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1702	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1703
1704	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1705	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1706	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1707	/** @} */
1708
1709	/** @name FPU operations taking a 80-bit float argument
1710	* @{ */
1711	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1712	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1713	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1714	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1715	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1716	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1717	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1718	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1719	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1720	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1721	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1722	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1723
1724	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
1725	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
1726	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
1727
1728	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1729	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1730	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1731	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1732	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1733
1734	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1735	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1736	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1737	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1738	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1739
1740	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1741	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1742	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1743	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1744	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
1745	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1746	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1747	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
1748	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
1749
1750	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1751	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1752	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1753	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1754
1755	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1756	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1757	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1758	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1759	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1760	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1761	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1762	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1763	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1764
1765	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1766	PCRTFLOAT80U pr80Val));
1767	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1768	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
1769	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1770	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
1771
1772	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1773	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1774	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1775
1776	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
1777	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1778	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
1779
1780	/** @} */
1781
1782	/** @name FPU operations taking a 16-bit signed integer argument
1783	* @{ */
1784	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1785	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1786	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1787	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1788	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
1789	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
1790
1791	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1792	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1793	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1794	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1795	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1796	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1797
1798	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1799	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1800	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
1801	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
1802
1803	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1804	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
1805	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
1806	/** @} */
1807
1808	/** @name FPU operations taking a 32-bit signed integer argument
1809	* @{ */
1810	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1811	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1812	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1813	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1814	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
1815	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
1816
1817	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1818	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1819	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1820	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1821	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1822	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1823
1824	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1825	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1826	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
1827	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
1828
1829	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1830	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
1831	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
1832	/** @} */
1833
1834	/** @name FPU operations taking a 64-bit signed integer argument
1835	* @{ */
1836	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1837	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
1838	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
1839
1840	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1841	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
1842	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
1843	/** @} */
1844
1845
1846	/** Temporary type representing a 256-bit vector register. */
1847	typedef struct { uint64_t au64[4]; } IEMVMM256;
1848	/** Temporary type pointing to a 256-bit vector register. */
1849	typedef IEMVMM256 *PIEMVMM256;
1850	/** Temporary type pointing to a const 256-bit vector register. */
1851	typedef IEMVMM256 *PCIEMVMM256;
1852
1853
1854	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1855	* @{ */
1856	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
1857	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1858	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1859	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1860	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1861	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
1862	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1863	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
1864	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
1865	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
1866	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
1867	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
1868	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1869	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
1870	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1871	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
1872	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
1873	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
1874	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
1875	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
1876	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1877	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
1878	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
1879	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
1880	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
1881	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
1882	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
1883	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
1884	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
1885	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
1886	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
1887	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
1888	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
1889	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
1890	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
1891	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
1892	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
1893	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
1894	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
1895	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
1896	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
1897	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
1898	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
1899	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
1900	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
1901	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
1902	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
1903	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
1904	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
1905	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
1906	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
1907	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
1908	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
1909	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
1910	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
1911	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
1912	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
1913
1914	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
1915	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
1916	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1917	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
1918	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
1919	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
1920	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
1921	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
1922	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
1923	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
1924	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
1925	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
1926	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
1927	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
1928	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
1929	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
1930	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
1931	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
1932	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
1933	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
1934	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
1935	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
1936	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
1937	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
1938	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
1939	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
1940	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
1941	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
1942	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
1943	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
1944	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
1945	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
1946	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
1947	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
1948	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
1949	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
1950	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
1951	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
1952	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
1953	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
1954	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
1955	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
1956	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
1957	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
1958	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
1959	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
1960	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
1961	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
1962	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
1963	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
1964	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
1965	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
1966	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
1967	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
1968	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
1969	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
1970	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
1971
1972	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
1973	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
1974	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
1975	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
1976	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
1977	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
1978	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
1979	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
1980	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
1981	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
1982	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
1983	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
1984	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
1985	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
1986	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
1987	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
1988	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
1989	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
1990	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
1991	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
1992	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
1993	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
1994	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
1995	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
1996	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
1997	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
1998	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
1999	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
2000	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
2001	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
2002	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
2003	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
2004	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
2005	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
2006	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
2007	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
2008	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
2009	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
2010	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
2011	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
2012	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
2013	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
2014	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
2015	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
2016	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
2017	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
2018	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
2019	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
2020	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
2021	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
2022	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
2023	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
2024	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
2025	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
2026	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
2027	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
2028	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
2029
2030	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
2031	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
2032	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
2033	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
2034
2035	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
2036	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
2037	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
2038	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
2039	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
2040	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
2041	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
2042	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
2043	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
2044	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
2045	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
2046	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
2047	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
2048	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
2049	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
2050	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
2051	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
2052	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
2053	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
2054	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
2055	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
2056	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
2057	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
2058	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
2059	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
2060	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
2061	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
2062	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
2063	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
2064	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
2065	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
2066	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
2067	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
2068	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
2069	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
2070	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
2071	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
2072	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
2073	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
2074	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
2075	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
2076	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
2077	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
2078	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
2079	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
2080	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
2081	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
2082	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
2083	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
2084	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
2085	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
2086	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
2087	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
2088	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
2089	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
2090	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
2091	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
2092
2093	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
2094	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
2095	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
2096	/** @} */
2097
2098	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2099	* @{ */
2100	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2101	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2102	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2103	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2104	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2105	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2106	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2107	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2108	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2109	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2110
2111	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2112	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2113	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2114	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2115	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2116	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2117	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2118	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2119	/** @} */
2120
2121	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2122	* @{ */
2123	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2124	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2125	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2126	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2127	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2128	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2129	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2130	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2131	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2132	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2133	/** @} */
2134
2135	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2136	* @{ */
2137	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2138	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2139	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2140	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2141	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
2142	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2143	#ifndef IEM_WITHOUT_ASSEMBLY
2144	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2145	#endif
2146	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2147	/** @} */
2148
2149	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2150	* @{ */
2151	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2152	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2153	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2154	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2155	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2156	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2157	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2158	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2159	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2160	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2161	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2162	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2163	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2164	/** @} */
2165
2166	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2167	* @{ */
2168	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
2169	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2170	#ifndef IEM_WITHOUT_ASSEMBLY
2171	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2172	#endif
2173	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2174	/** @} */
2175
2176	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
2177	* @{ */
2178	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
2179	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
2180	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
2181	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
2182	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
2183	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
2184
2185	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
2186	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
2187	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
2188	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
2189	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
2190	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
2191
2192	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
2193	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
2194	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
2195	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
2196	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
2197	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
2198
2199	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
2200	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
2201	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
2202	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
2203	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
2204	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
2205	/** @} */
2206
2207
2208	/** @name Media (SSE/MMX/AVX) operation: Sort this later
2209	* @{ */
2210	IEM_DECL_IMPL_DEF(void, iemAImpl_movsldup,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2211	IEM_DECL_IMPL_DEF(void, iemAImpl_movshdup,(PRTUINT128U puDst, PCRTUINT128U puSrc));
2212	IEM_DECL_IMPL_DEF(void, iemAImpl_movddup,(PRTUINT128U puDst, uint64_t uSrc));
2213
2214	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2215	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2216	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2217	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2218	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2219	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2220
2221	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2222	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2223	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2224	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2225	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2226
2227	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2228	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2229	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2230	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2231	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2232
2233	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2234	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2235	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2236	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2237	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2238
2239	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2240	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2241	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2242	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2243	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2244
2245	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2246	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2247	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2248	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2249	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2250
2251	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2252	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2253	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2254	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2255	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2256
2257	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2258	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2259	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2260	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2261	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2262
2263	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2264	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2265	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2266	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2267	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2268
2269	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2270	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2271	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2272	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2273	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2274
2275	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2276	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2277	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2278	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2279	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2280
2281	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2282	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2283	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2284	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2285	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2286
2287	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2288	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2289	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2290	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2291	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2292
2293	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2294	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2295	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2296	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2297	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2298
2299	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2300	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2301	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2302	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2303	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2304
2305	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2306	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2307
2308	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
2309	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
2310	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2311	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2312
2313	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
2314	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2315	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2316	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2317
2318	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2319	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2320	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2321	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2322	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2323
2324	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2325	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2326	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2327	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2328	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2329
2330
2331	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2332	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
2333	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2334	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
2335	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2336	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
2337
2338	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
2339	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
2340	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
2341	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
2342
2343	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
2344	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
2345	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
2346	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
2347
2348	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
2349	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
2350	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
2351	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
2352
2353	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
2354	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
2355	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
2356	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
2357	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
2358
2359	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
2360	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
2361	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
2362	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
2363	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
2364
2365	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
2366
2367	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
2368
2369
2370	typedef struct IEMPCMPISTRISRC
2371	{
2372	RTUINT128U uSrc1;
2373	RTUINT128U uSrc2;
2374	} IEMPCMPISTRISRC;
2375	typedef IEMPCMPISTRISRC *PIEMPCMPISTRISRC;
2376	typedef const IEMPCMPISTRISRC *PCIEMPCMPISTRISRC;
2377
2378	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpistri_u128,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRISRC pSrc, uint8_t bEvil));
2379	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpistri_u128_fallback,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRISRC pSrc, uint8_t bEvil));
2380
2381	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
2382	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
2383	/** @} */
2384
2385	/** @name Media Odds and Ends
2386	* @{ */
2387	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
2388	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
2389	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
2390	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
2391	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
2392	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
2393	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
2394	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
2395
2396	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
2397	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
2398	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
2399	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
2400
2401	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2402	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
2403	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2404	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
2405	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2406	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
2407	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2408	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
2409
2410	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
2411	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
2412
2413	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
2414	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
2415
2416	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
2417	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
2418
2419	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
2420	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
2421
2422	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
2423	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
2424	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
2425	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
2426
2427	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
2428	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
2429
2430	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
2431	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
2432	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
2433	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
2434
2435	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
2436	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
2437
2438
2439	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2440	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
2441
2442	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
2443	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
2444
2445	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
2446	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
2447
2448	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
2449	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
2450
2451	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
2452	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
2453
2454
2455	typedef struct IEMMEDIAF2XMMSRC
2456	{
2457	X86XMMREG uSrc1;
2458	X86XMMREG uSrc2;
2459	} IEMMEDIAF2XMMSRC;
2460	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
2461	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
2462
2463	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
2464	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
2465
2466	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
2467	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
2468	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
2469	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
2470
2471	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
2472	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
2473
2474	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
2475	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
2476
2477	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
2478	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
2479
2480	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
2481	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
2482
2483	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
2484	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
2485
2486	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
2487	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
2488
2489	/** @} */
2490
2491
2492	/** @name Function tables.
2493	* @{
2494	*/
2495
2496	/**
2497	* Function table for a binary operator providing implementation based on
2498	* operand size.
2499	*/
2500	typedef struct IEMOPBINSIZES
2501	{
2502	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
2503	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
2504	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
2505	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
2506	} IEMOPBINSIZES;
2507	/** Pointer to a binary operator function table. */
2508	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
2509
2510
2511	/**
2512	* Function table for a unary operator providing implementation based on
2513	* operand size.
2514	*/
2515	typedef struct IEMOPUNARYSIZES
2516	{
2517	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
2518	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
2519	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
2520	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
2521	} IEMOPUNARYSIZES;
2522	/** Pointer to a unary operator function table. */
2523	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
2524
2525
2526	/**
2527	* Function table for a shift operator providing implementation based on
2528	* operand size.
2529	*/
2530	typedef struct IEMOPSHIFTSIZES
2531	{
2532	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
2533	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
2534	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
2535	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
2536	} IEMOPSHIFTSIZES;
2537	/** Pointer to a shift operator function table. */
2538	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
2539
2540
2541	/**
2542	* Function table for a multiplication or division operation.
2543	*/
2544	typedef struct IEMOPMULDIVSIZES
2545	{
2546	PFNIEMAIMPLMULDIVU8 pfnU8;
2547	PFNIEMAIMPLMULDIVU16 pfnU16;
2548	PFNIEMAIMPLMULDIVU32 pfnU32;
2549	PFNIEMAIMPLMULDIVU64 pfnU64;
2550	} IEMOPMULDIVSIZES;
2551	/** Pointer to a multiplication or division operation function table. */
2552	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
2553
2554
2555	/**
2556	* Function table for a double precision shift operator providing implementation
2557	* based on operand size.
2558	*/
2559	typedef struct IEMOPSHIFTDBLSIZES
2560	{
2561	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
2562	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
2563	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
2564	} IEMOPSHIFTDBLSIZES;
2565	/** Pointer to a double precision shift function table. */
2566	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
2567
2568
2569	/**
2570	* Function table for media instruction taking two full sized media source
2571	* registers and one full sized destination register (AVX).
2572	*/
2573	typedef struct IEMOPMEDIAF3
2574	{
2575	PFNIEMAIMPLMEDIAF3U128 pfnU128;
2576	PFNIEMAIMPLMEDIAF3U256 pfnU256;
2577	} IEMOPMEDIAF3;
2578	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2579	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
2580
2581	/** @def IEMOPMEDIAF3_INIT_VARS_EX
2582	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2583	* given functions as initializers. For use in AVX functions where a pair of
2584	* functions are only used once and the function table need not be public. */
2585	#ifndef TST_IEM_CHECK_MC
2586	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2587	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2588	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2589	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2590	# else
2591	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2592	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2593	# endif
2594	#else
2595	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2596	#endif
2597	/** @def IEMOPMEDIAF3_INIT_VARS
2598	* Generate AVX function tables for the @a a_InstrNm instruction.
2599	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
2600	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
2601	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2602	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2603
2604	/**
2605	* Function table for media instruction taking two full sized media source
2606	* registers and one full sized destination register, but no additional state
2607	* (AVX).
2608	*/
2609	typedef struct IEMOPMEDIAOPTF3
2610	{
2611	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
2612	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
2613	} IEMOPMEDIAOPTF3;
2614	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2615	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
2616
2617	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
2618	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2619	* given functions as initializers. For use in AVX functions where a pair of
2620	* functions are only used once and the function table need not be public. */
2621	#ifndef TST_IEM_CHECK_MC
2622	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2623	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2624	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2625	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2626	# else
2627	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2628	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2629	# endif
2630	#else
2631	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2632	#endif
2633	/** @def IEMOPMEDIAOPTF3_INIT_VARS
2634	* Generate AVX function tables for the @a a_InstrNm instruction.
2635	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
2636	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
2637	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2638	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2639
2640	/**
2641	* Function table for media instruction taking one full sized media source
2642	* registers and one full sized destination register, but no additional state
2643	* (AVX).
2644	*/
2645	typedef struct IEMOPMEDIAOPTF2
2646	{
2647	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
2648	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
2649	} IEMOPMEDIAOPTF2;
2650	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
2651	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
2652
2653	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
2654	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2655	* given functions as initializers. For use in AVX functions where a pair of
2656	* functions are only used once and the function table need not be public. */
2657	#ifndef TST_IEM_CHECK_MC
2658	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2659	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2660	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2661	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2662	# else
2663	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2664	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2665	# endif
2666	#else
2667	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2668	#endif
2669	/** @def IEMOPMEDIAOPTF2_INIT_VARS
2670	* Generate AVX function tables for the @a a_InstrNm instruction.
2671	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
2672	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
2673	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2674	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2675
2676	/**
2677	* Function table for media instruction taking two full sized media source
2678	* registers and one full sized destination register and an 8-bit immediate, but no additional state
2679	* (AVX).
2680	*/
2681	typedef struct IEMOPMEDIAOPTF3IMM8
2682	{
2683	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
2684	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
2685	} IEMOPMEDIAOPTF3IMM8;
2686	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2687	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
2688
2689	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
2690	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2691	* given functions as initializers. For use in AVX functions where a pair of
2692	* functions are only used once and the function table need not be public. */
2693	#ifndef TST_IEM_CHECK_MC
2694	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2695	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2696	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2697	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2698	# else
2699	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2700	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2701	# endif
2702	#else
2703	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2704	#endif
2705	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
2706	* Generate AVX function tables for the @a a_InstrNm instruction.
2707	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
2708	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
2709	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2710	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2711	/** @} */
2712
2713
2714	/**
2715	* Function table for blend type instruction taking three full sized media source
2716	* registers and one full sized destination register, but no additional state
2717	* (AVX).
2718	*/
2719	typedef struct IEMOPBLENDOP
2720	{
2721	PFNIEMAIMPLAVXBLENDU128 pfnU128;
2722	PFNIEMAIMPLAVXBLENDU256 pfnU256;
2723	} IEMOPBLENDOP;
2724	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
2725	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
2726
2727	/** @def IEMOPBLENDOP_INIT_VARS_EX
2728	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2729	* given functions as initializers. For use in AVX functions where a pair of
2730	* functions are only used once and the function table need not be public. */
2731	#ifndef TST_IEM_CHECK_MC
2732	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2733	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2734	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2735	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2736	# else
2737	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2738	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2739	# endif
2740	#else
2741	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2742	#endif
2743	/** @def IEMOPBLENDOP_INIT_VARS
2744	* Generate AVX function tables for the @a a_InstrNm instruction.
2745	* @sa IEMOPBLENDOP_INIT_VARS_EX */
2746	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
2747	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2748	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2749
2750
2751	/** @name SSE/AVX single/double precision floating point operations.
2752	* @{ */
2753	/**
2754	* A SSE result.
2755	*/
2756	typedef struct IEMSSERESULT
2757	{
2758	/** The output value. */
2759	X86XMMREG uResult;
2760	/** The output status. */
2761	uint32_t MXCSR;
2762	} IEMSSERESULT;
2763	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
2764	/** Pointer to a SSE result. */
2765	typedef IEMSSERESULT *PIEMSSERESULT;
2766	/** Pointer to a const SSE result. */
2767	typedef IEMSSERESULT const *PCIEMSSERESULT;
2768
2769
2770	/**
2771	* A AVX128 result.
2772	*/
2773	typedef struct IEMAVX128RESULT
2774	{
2775	/** The output value. */
2776	X86XMMREG uResult;
2777	/** The output status. */
2778	uint32_t MXCSR;
2779	} IEMAVX128RESULT;
2780	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
2781	/** Pointer to a AVX128 result. */
2782	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
2783	/** Pointer to a const AVX128 result. */
2784	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
2785
2786
2787	/**
2788	* A AVX256 result.
2789	*/
2790	typedef struct IEMAVX256RESULT
2791	{
2792	/** The output value. */
2793	X86YMMREG uResult;
2794	/** The output status. */
2795	uint32_t MXCSR;
2796	} IEMAVX256RESULT;
2797	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
2798	/** Pointer to a AVX256 result. */
2799	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
2800	/** Pointer to a const AVX256 result. */
2801	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
2802
2803
2804	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2805	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
2806	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2807	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
2808	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2809	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
2810
2811	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2812	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
2813	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2814	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
2815	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2816	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
2817
2818	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
2819	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
2820
2821	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
2822	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
2823	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
2824	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
2825	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
2826	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
2827	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
2828	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
2829	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
2830	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
2831	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
2832	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
2833	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
2834	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
2835	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
2836	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
2837	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
2838	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
2839	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
2840	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
2841	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
2842	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
2843
2844	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
2845	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
2846	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
2847	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
2848	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
2849	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
2850
2851	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
2852	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
2853	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
2854	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
2855	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
2856	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
2857	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
2858	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
2859	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
2860	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
2861	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
2862	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
2863	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
2864	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
2865	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
2866	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
2867
2868	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
2869	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
2870	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
2871	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
2872	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
2873	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
2874	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
2875	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
2876	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
2877	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
2878	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
2879	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
2880	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
2881	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
2882	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
2883	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
2884	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
2885	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
2886	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
2887	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
2888	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
2889	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
2890
2891	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
2892	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
2893	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
2894	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
2895	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
2896	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
2897	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
2898	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
2899	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
2900	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
2901	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
2902	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
2903	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
2904	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
2905
2906	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
2907	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
2908	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
2909	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
2910	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
2911	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
2912	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
2913	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
2914	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
2915	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
2916	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
2917	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
2918	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
2919	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
2920	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
2921	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
2922	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
2923	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
2924	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
2925	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
2926	/** @} */
2927
2928	/** @name C instruction implementations for anything slightly complicated.
2929	* @{ */
2930
2931	/**
2932	* For typedef'ing or declaring a C instruction implementation function taking
2933	* no extra arguments.
2934	*
2935	* @param a_Name The name of the type.
2936	*/
2937	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
2938	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2939	/**
2940	* For defining a C instruction implementation function taking no extra
2941	* arguments.
2942	*
2943	* @param a_Name The name of the function
2944	*/
2945	# define IEM_CIMPL_DEF_0(a_Name) \
2946	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2947	/**
2948	* Prototype version of IEM_CIMPL_DEF_0.
2949	*/
2950	# define IEM_CIMPL_PROTO_0(a_Name) \
2951	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2952	/**
2953	* For calling a C instruction implementation function taking no extra
2954	* arguments.
2955	*
2956	* This special call macro adds default arguments to the call and allow us to
2957	* change these later.
2958	*
2959	* @param a_fn The name of the function.
2960	*/
2961	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
2962
2963	/**
2964	* For typedef'ing or declaring a C instruction implementation function taking
2965	* one extra argument.
2966	*
2967	* @param a_Name The name of the type.
2968	* @param a_Type0 The argument type.
2969	* @param a_Arg0 The argument name.
2970	*/
2971	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
2972	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2973	/**
2974	* For defining a C instruction implementation function taking one extra
2975	* argument.
2976	*
2977	* @param a_Name The name of the function
2978	* @param a_Type0 The argument type.
2979	* @param a_Arg0 The argument name.
2980	*/
2981	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
2982	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2983	/**
2984	* Prototype version of IEM_CIMPL_DEF_1.
2985	*/
2986	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
2987	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
2988	/**
2989	* For calling a C instruction implementation function taking one extra
2990	* argument.
2991	*
2992	* This special call macro adds default arguments to the call and allow us to
2993	* change these later.
2994	*
2995	* @param a_fn The name of the function.
2996	* @param a0 The name of the 1st argument.
2997	*/
2998	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
2999
3000	/**
3001	* For typedef'ing or declaring a C instruction implementation function taking
3002	* two extra arguments.
3003	*
3004	* @param a_Name The name of the type.
3005	* @param a_Type0 The type of the 1st argument
3006	* @param a_Arg0 The name of the 1st argument.
3007	* @param a_Type1 The type of the 2nd argument.
3008	* @param a_Arg1 The name of the 2nd argument.
3009	*/
3010	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3011	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3012	/**
3013	* For defining a C instruction implementation function taking two extra
3014	* arguments.
3015	*
3016	* @param a_Name The name of the function.
3017	* @param a_Type0 The type of the 1st argument
3018	* @param a_Arg0 The name of the 1st argument.
3019	* @param a_Type1 The type of the 2nd argument.
3020	* @param a_Arg1 The name of the 2nd argument.
3021	*/
3022	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3023	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3024	/**
3025	* Prototype version of IEM_CIMPL_DEF_2.
3026	*/
3027	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3028	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3029	/**
3030	* For calling a C instruction implementation function taking two extra
3031	* arguments.
3032	*
3033	* This special call macro adds default arguments to the call and allow us to
3034	* change these later.
3035	*
3036	* @param a_fn The name of the function.
3037	* @param a0 The name of the 1st argument.
3038	* @param a1 The name of the 2nd argument.
3039	*/
3040	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
3041
3042	/**
3043	* For typedef'ing or declaring a C instruction implementation function taking
3044	* three extra arguments.
3045	*
3046	* @param a_Name The name of the type.
3047	* @param a_Type0 The type of the 1st argument
3048	* @param a_Arg0 The name of the 1st argument.
3049	* @param a_Type1 The type of the 2nd argument.
3050	* @param a_Arg1 The name of the 2nd argument.
3051	* @param a_Type2 The type of the 3rd argument.
3052	* @param a_Arg2 The name of the 3rd argument.
3053	*/
3054	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3055	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3056	/**
3057	* For defining a C instruction implementation function taking three extra
3058	* arguments.
3059	*
3060	* @param a_Name The name of the function.
3061	* @param a_Type0 The type of the 1st argument
3062	* @param a_Arg0 The name of the 1st argument.
3063	* @param a_Type1 The type of the 2nd argument.
3064	* @param a_Arg1 The name of the 2nd argument.
3065	* @param a_Type2 The type of the 3rd argument.
3066	* @param a_Arg2 The name of the 3rd argument.
3067	*/
3068	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3069	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3070	/**
3071	* Prototype version of IEM_CIMPL_DEF_3.
3072	*/
3073	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3074	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3075	/**
3076	* For calling a C instruction implementation function taking three extra
3077	* arguments.
3078	*
3079	* This special call macro adds default arguments to the call and allow us to
3080	* change these later.
3081	*
3082	* @param a_fn The name of the function.
3083	* @param a0 The name of the 1st argument.
3084	* @param a1 The name of the 2nd argument.
3085	* @param a2 The name of the 3rd argument.
3086	*/
3087	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
3088
3089
3090	/**
3091	* For typedef'ing or declaring a C instruction implementation function taking
3092	* four extra arguments.
3093	*
3094	* @param a_Name The name of the type.
3095	* @param a_Type0 The type of the 1st argument
3096	* @param a_Arg0 The name of the 1st argument.
3097	* @param a_Type1 The type of the 2nd argument.
3098	* @param a_Arg1 The name of the 2nd argument.
3099	* @param a_Type2 The type of the 3rd argument.
3100	* @param a_Arg2 The name of the 3rd argument.
3101	* @param a_Type3 The type of the 4th argument.
3102	* @param a_Arg3 The name of the 4th argument.
3103	*/
3104	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3105	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
3106	/**
3107	* For defining a C instruction implementation function taking four extra
3108	* arguments.
3109	*
3110	* @param a_Name The name of the function.
3111	* @param a_Type0 The type of the 1st argument
3112	* @param a_Arg0 The name of the 1st argument.
3113	* @param a_Type1 The type of the 2nd argument.
3114	* @param a_Arg1 The name of the 2nd argument.
3115	* @param a_Type2 The type of the 3rd argument.
3116	* @param a_Arg2 The name of the 3rd argument.
3117	* @param a_Type3 The type of the 4th argument.
3118	* @param a_Arg3 The name of the 4th argument.
3119	*/
3120	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3121	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3122	a_Type2 a_Arg2, a_Type3 a_Arg3))
3123	/**
3124	* Prototype version of IEM_CIMPL_DEF_4.
3125	*/
3126	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3127	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3128	a_Type2 a_Arg2, a_Type3 a_Arg3))
3129	/**
3130	* For calling a C instruction implementation function taking four extra
3131	* arguments.
3132	*
3133	* This special call macro adds default arguments to the call and allow us to
3134	* change these later.
3135	*
3136	* @param a_fn The name of the function.
3137	* @param a0 The name of the 1st argument.
3138	* @param a1 The name of the 2nd argument.
3139	* @param a2 The name of the 3rd argument.
3140	* @param a3 The name of the 4th argument.
3141	*/
3142	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
3143
3144
3145	/**
3146	* For typedef'ing or declaring a C instruction implementation function taking
3147	* five extra arguments.
3148	*
3149	* @param a_Name The name of the type.
3150	* @param a_Type0 The type of the 1st argument
3151	* @param a_Arg0 The name of the 1st argument.
3152	* @param a_Type1 The type of the 2nd argument.
3153	* @param a_Arg1 The name of the 2nd argument.
3154	* @param a_Type2 The type of the 3rd argument.
3155	* @param a_Arg2 The name of the 3rd argument.
3156	* @param a_Type3 The type of the 4th argument.
3157	* @param a_Arg3 The name of the 4th argument.
3158	* @param a_Type4 The type of the 5th argument.
3159	* @param a_Arg4 The name of the 5th argument.
3160	*/
3161	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3162	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
3163	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
3164	a_Type3 a_Arg3, a_Type4 a_Arg4))
3165	/**
3166	* For defining a C instruction implementation function taking five extra
3167	* arguments.
3168	*
3169	* @param a_Name The name of the function.
3170	* @param a_Type0 The type of the 1st argument
3171	* @param a_Arg0 The name of the 1st argument.
3172	* @param a_Type1 The type of the 2nd argument.
3173	* @param a_Arg1 The name of the 2nd argument.
3174	* @param a_Type2 The type of the 3rd argument.
3175	* @param a_Arg2 The name of the 3rd argument.
3176	* @param a_Type3 The type of the 4th argument.
3177	* @param a_Arg3 The name of the 4th argument.
3178	* @param a_Type4 The type of the 5th argument.
3179	* @param a_Arg4 The name of the 5th argument.
3180	*/
3181	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3182	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3183	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3184	/**
3185	* Prototype version of IEM_CIMPL_DEF_5.
3186	*/
3187	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3188	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3189	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3190	/**
3191	* For calling a C instruction implementation function taking five extra
3192	* arguments.
3193	*
3194	* This special call macro adds default arguments to the call and allow us to
3195	* change these later.
3196	*
3197	* @param a_fn The name of the function.
3198	* @param a0 The name of the 1st argument.
3199	* @param a1 The name of the 2nd argument.
3200	* @param a2 The name of the 3rd argument.
3201	* @param a3 The name of the 4th argument.
3202	* @param a4 The name of the 5th argument.
3203	*/
3204	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
3205
3206	/** @} */
3207
3208
3209	/** @name Opcode Decoder Function Types.
3210	* @{ */
3211
3212	/** @typedef PFNIEMOP
3213	* Pointer to an opcode decoder function.
3214	*/
3215
3216	/** @def FNIEMOP_DEF
3217	* Define an opcode decoder function.
3218	*
3219	* We're using macors for this so that adding and removing parameters as well as
3220	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
3221	*
3222	* @param a_Name The function name.
3223	*/
3224
3225	/** @typedef PFNIEMOPRM
3226	* Pointer to an opcode decoder function with RM byte.
3227	*/
3228
3229	/** @def FNIEMOPRM_DEF
3230	* Define an opcode decoder function with RM byte.
3231	*
3232	* We're using macors for this so that adding and removing parameters as well as
3233	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
3234	*
3235	* @param a_Name The function name.
3236	*/
3237
3238	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3239	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
3240	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3241	# define FNIEMOP_DEF(a_Name) \
3242	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
3243	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3244	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3245	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3246	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3247
3248	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3249	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
3250	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3251	# define FNIEMOP_DEF(a_Name) \
3252	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3253	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3254	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3255	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3256	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3257
3258	#elif defined(__GNUC__)
3259	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3260	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3261	# define FNIEMOP_DEF(a_Name) \
3262	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
3263	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3264	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3265	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3266	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3267
3268	#else
3269	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3270	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3271	# define FNIEMOP_DEF(a_Name) \
3272	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3273	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3274	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3275	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3276	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3277
3278	#endif
3279	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
3280
3281	/**
3282	* Call an opcode decoder function.
3283	*
3284	* We're using macors for this so that adding and removing parameters can be
3285	* done as we please. See FNIEMOP_DEF.
3286	*/
3287	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
3288
3289	/**
3290	* Call a common opcode decoder function taking one extra argument.
3291	*
3292	* We're using macors for this so that adding and removing parameters can be
3293	* done as we please. See FNIEMOP_DEF_1.
3294	*/
3295	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
3296
3297	/**
3298	* Call a common opcode decoder function taking one extra argument.
3299	*
3300	* We're using macors for this so that adding and removing parameters can be
3301	* done as we please. See FNIEMOP_DEF_1.
3302	*/
3303	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
3304	/** @} */
3305
3306
3307	/** @name Misc Helpers
3308	* @{ */
3309
3310	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
3311	* due to GCC lacking knowledge about the value range of a switch. */
3312	#if RT_CPLUSPLUS_PREREQ(202000)
3313	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3314	#else
3315	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3316	#endif
3317
3318	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
3319	#if RT_CPLUSPLUS_PREREQ(202000)
3320	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
3321	#else
3322	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
3323	#endif
3324
3325	/**
3326	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3327	* occation.
3328	*/
3329	#ifdef LOG_ENABLED
3330	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3331	do { \
3332	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
3333	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3334	} while (0)
3335	#else
3336	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3337	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3338	#endif
3339
3340	/**
3341	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3342	* occation using the supplied logger statement.
3343	*
3344	* @param a_LoggerArgs What to log on failure.
3345	*/
3346	#ifdef LOG_ENABLED
3347	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3348	do { \
3349	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
3350	/LogFunc(a_LoggerArgs);/ \
3351	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3352	} while (0)
3353	#else
3354	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3355	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3356	#endif
3357
3358	/**
3359	* Check if we're currently executing in real or virtual 8086 mode.
3360	*
3361	* @returns @c true if it is, @c false if not.
3362	* @param a_pVCpu The IEM state of the current CPU.
3363	*/
3364	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (CPUMIsGuestInRealOrV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3365
3366	/**
3367	* Check if we're currently executing in virtual 8086 mode.
3368	*
3369	* @returns @c true if it is, @c false if not.
3370	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3371	*/
3372	#define IEM_IS_V86_MODE(a_pVCpu) (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3373
3374	/**
3375	* Check if we're currently executing in long mode.
3376	*
3377	* @returns @c true if it is, @c false if not.
3378	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3379	*/
3380	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
3381
3382	/**
3383	* Check if we're currently executing in a 64-bit code segment.
3384	*
3385	* @returns @c true if it is, @c false if not.
3386	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3387	*/
3388	#define IEM_IS_64BIT_CODE(a_pVCpu) (CPUMIsGuestIn64BitCodeEx(IEM_GET_CTX(a_pVCpu)))
3389
3390	/**
3391	* Check if we're currently executing in real mode.
3392	*
3393	* @returns @c true if it is, @c false if not.
3394	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3395	*/
3396	#define IEM_IS_REAL_MODE(a_pVCpu) (CPUMIsGuestInRealModeEx(IEM_GET_CTX(a_pVCpu)))
3397
3398	/**
3399	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
3400	* @returns PCCPUMFEATURES
3401	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3402	*/
3403	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
3404
3405	/**
3406	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
3407	* @returns PCCPUMFEATURES
3408	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3409	*/
3410	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
3411
3412	/**
3413	* Evaluates to true if we're presenting an Intel CPU to the guest.
3414	*/
3415	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
3416
3417	/**
3418	* Evaluates to true if we're presenting an AMD CPU to the guest.
3419	*/
3420	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
3421
3422	/**
3423	* Check if the address is canonical.
3424	*/
3425	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
3426
3427	/** Checks if the ModR/M byte is in register mode or not. */
3428	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
3429	/** Checks if the ModR/M byte is in memory mode or not. */
3430	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
3431
3432	/**
3433	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
3434	*
3435	* For use during decoding.
3436	*/
3437	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
3438	/**
3439	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
3440	*
3441	* For use during decoding.
3442	*/
3443	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
3444
3445	/**
3446	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
3447	*
3448	* For use during decoding.
3449	*/
3450	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
3451	/**
3452	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
3453	*
3454	* For use during decoding.
3455	*/
3456	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
3457
3458	/**
3459	* Gets the effective VEX.VVVV value.
3460	*
3461	* The 4th bit is ignored if not 64-bit code.
3462	* @returns effective V-register value.
3463	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3464	*/
3465	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
3466	((a_pVCpu)->iem.s.enmCpuMode == IEMMODE_64BIT ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
3467
3468
3469	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3470
3471	/**
3472	* Check if the guest has entered VMX root operation.
3473	*/
3474	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
3475
3476	/**
3477	* Check if the guest has entered VMX non-root operation.
3478	*/
3479	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(a_pVCpu)))
3480
3481	/**
3482	* Check if the nested-guest has the given Pin-based VM-execution control set.
3483	*/
3484	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) \
3485	(CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
3486
3487	/**
3488	* Check if the nested-guest has the given Processor-based VM-execution control set.
3489	*/
3490	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) \
3491	(CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
3492
3493	/**
3494	* Check if the nested-guest has the given Secondary Processor-based VM-execution
3495	* control set.
3496	*/
3497	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) \
3498	(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
3499
3500	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
3501	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
3502
3503	/** Whether a shadow VMCS is present for the given VCPU. */
3504	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3505
3506	/** Gets the VMXON region pointer. */
3507	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
3508
3509	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
3510	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
3511
3512	/** Whether a current VMCS is present for the given VCPU. */
3513	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3514
3515	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
3516	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
3517	do \
3518	{ \
3519	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
3520	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
3521	} while (0)
3522
3523	/** Clears any current VMCS for the given VCPU. */
3524	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
3525	do \
3526	{ \
3527	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
3528	} while (0)
3529
3530	/**
3531	* Invokes the VMX VM-exit handler for an instruction intercept.
3532	*/
3533	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
3534	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
3535
3536	/**
3537	* Invokes the VMX VM-exit handler for an instruction intercept where the
3538	* instruction provides additional VM-exit information.
3539	*/
3540	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
3541	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
3542
3543	/**
3544	* Invokes the VMX VM-exit handler for a task switch.
3545	*/
3546	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
3547	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
3548
3549	/**
3550	* Invokes the VMX VM-exit handler for MWAIT.
3551	*/
3552	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
3553	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
3554
3555	/**
3556	* Invokes the VMX VM-exit handler for EPT faults.
3557	*/
3558	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
3559	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
3560
3561	/**
3562	* Invokes the VMX VM-exit handler.
3563	*/
3564	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
3565	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
3566
3567	#else
3568	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
3569	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
3570	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
3571	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
3572	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
3573	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3574	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3575	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3576	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3577	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3578	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
3579
3580	#endif
3581
3582	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3583	/**
3584	* Check if an SVM control/instruction intercept is set.
3585	*/
3586	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
3587	(CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
3588
3589	/**
3590	* Check if an SVM read CRx intercept is set.
3591	*/
3592	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3593	(CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3594
3595	/**
3596	* Check if an SVM write CRx intercept is set.
3597	*/
3598	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3599	(CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3600
3601	/**
3602	* Check if an SVM read DRx intercept is set.
3603	*/
3604	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3605	(CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3606
3607	/**
3608	* Check if an SVM write DRx intercept is set.
3609	*/
3610	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3611	(CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3612
3613	/**
3614	* Check if an SVM exception intercept is set.
3615	*/
3616	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
3617	(CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
3618
3619	/**
3620	* Invokes the SVM \#VMEXIT handler for the nested-guest.
3621	*/
3622	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3623	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
3624
3625	/**
3626	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
3627	* corresponding decode assist information.
3628	*/
3629	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
3630	do \
3631	{ \
3632	uint64_t uExitInfo1; \
3633	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
3634	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
3635	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
3636	else \
3637	uExitInfo1 = 0; \
3638	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
3639	} while (0)
3640
3641	/** Check and handles SVM nested-guest instruction intercept and updates
3642	* NRIP if needed.
3643	*/
3644	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3645	do \
3646	{ \
3647	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
3648	{ \
3649	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3650	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
3651	} \
3652	} while (0)
3653
3654	/** Checks and handles SVM nested-guest CR0 read intercept. */
3655	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) \
3656	do \
3657	{ \
3658	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
3659	{ /* probably likely */ } \
3660	else \
3661	{ \
3662	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3663	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
3664	} \
3665	} while (0)
3666
3667	/**
3668	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
3669	*/
3670	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) \
3671	do { \
3672	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
3673	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), IEM_GET_INSTR_LEN(a_pVCpu)); \
3674	} while (0)
3675
3676	#else
3677	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
3678	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3679	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3680	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3681	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3682	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
3683	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
3684	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
3685	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3686	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3687	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) do { } while (0)
3688
3689	#endif
3690
3691	/** @} */
3692
3693
3694
3695	/**
3696	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
3697	*/
3698	typedef union IEMSELDESC
3699	{
3700	/** The legacy view. */
3701	X86DESC Legacy;
3702	/** The long mode view. */
3703	X86DESC64 Long;
3704	} IEMSELDESC;
3705	/** Pointer to a selector descriptor table entry. */
3706	typedef IEMSELDESC *PIEMSELDESC;
3707
3708	/** @name Raising Exceptions.
3709	* @{ */
3710	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
3711	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
3712
3713	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
3714	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3715	#ifdef IEM_WITH_SETJMP
3716	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
3717	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
3718	#endif
3719	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
3720	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3721	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
3722	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
3723	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
3724	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3725	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
3726	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3727	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3728	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
3729	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3730	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3731	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3732	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3733	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3734	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3735	#ifdef IEM_WITH_SETJMP
3736	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3737	#endif
3738	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3739	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
3740	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3741	#ifdef IEM_WITH_SETJMP
3742	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
3743	#endif
3744	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3745	#ifdef IEM_WITH_SETJMP
3746	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
3747	#endif
3748	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3749	#ifdef IEM_WITH_SETJMP
3750	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
3751	#endif
3752	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) RT_NOEXCEPT;
3753	#ifdef IEM_WITH_SETJMP
3754	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
3755	#endif
3756	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
3757	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3758	#ifdef IEM_WITH_SETJMP
3759	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3760	#endif
3761	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3762
3763	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
3764	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
3765	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
3766
3767	/**
3768	* Macro for calling iemCImplRaiseDivideError().
3769	*
3770	* This enables us to add/remove arguments and force different levels of
3771	* inlining as we wish.
3772	*
3773	* @return Strict VBox status code.
3774	*/
3775	#define IEMOP_RAISE_DIVIDE_ERROR() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseDivideError)
3776
3777	/**
3778	* Macro for calling iemCImplRaiseInvalidLockPrefix().
3779	*
3780	* This enables us to add/remove arguments and force different levels of
3781	* inlining as we wish.
3782	*
3783	* @return Strict VBox status code.
3784	*/
3785	#define IEMOP_RAISE_INVALID_LOCK_PREFIX() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidLockPrefix)
3786
3787	/**
3788	* Macro for calling iemCImplRaiseInvalidOpcode().
3789	*
3790	* This enables us to add/remove arguments and force different levels of
3791	* inlining as we wish.
3792	*
3793	* @return Strict VBox status code.
3794	*/
3795	#define IEMOP_RAISE_INVALID_OPCODE() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidOpcode)
3796	/** @} */
3797
3798	/** @name Register Access.
3799	* @{ */
3800	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
3801	IEMMODE enmEffOpSize) RT_NOEXCEPT;
3802	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
3803	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
3804	IEMMODE enmEffOpSize) RT_NOEXCEPT;
3805	VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
3806	VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
3807	VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
3808	/** @} */
3809
3810	/** @name FPU access and helpers.
3811	* @{ */
3812	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult) RT_NOEXCEPT;
3813	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3814	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult) RT_NOEXCEPT;
3815	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3816	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3817	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3818	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3819	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3820	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3821	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3822	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3823	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3824	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3825	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3826	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3827	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3828	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3829	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3830	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3831	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu) RT_NOEXCEPT;
3832	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3833	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu) RT_NOEXCEPT;
3834	void iemFpuStackPushOverflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3835	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3836	/** @} */
3837
3838	/** @name SSE+AVX SIMD access and helpers.
3839	* @{ */
3840	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
3841	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
3842	/** @} */
3843
3844	/** @name Memory access.
3845	* @{ */
3846
3847	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
3848	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
3849	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
3850	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
3851	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
3852	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
3853	* Users include FXSAVE & FXRSTOR. */
3854	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
3855
3856	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
3857	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
3858	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3859	#ifndef IN_RING3
3860	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3861	#endif
3862	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
3863	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
3864	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3865	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
3866
3867	#ifdef IEM_WITH_CODE_TLB
3868	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
3869	#else
3870	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
3871	#endif
3872	#ifdef IEM_WITH_SETJMP
3873	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3874	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3875	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3876	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3877	#else
3878	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
3879	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3880	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3881	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3882	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3883	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3884	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3885	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3886	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3887	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3888	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3889	#endif
3890
3891	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3892	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3893	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3894	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3895	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3896	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3897	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3898	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3899	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3900	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3901	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3902	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3903	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
3904	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
3905	#ifdef IEM_WITH_SETJMP
3906	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3907	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3908	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3909	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3910	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3911	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3912	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3913	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3914	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3915	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3916	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3917	#endif
3918
3919	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3920	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3921	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3922	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3923	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
3924
3925	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
3926	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
3927	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
3928	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
3929	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3930	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3931	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3932	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3933	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3934	#ifdef IEM_WITH_SETJMP
3935	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
3936	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
3937	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
3938	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
3939	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
3940	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
3941	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
3942	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
3943	#endif
3944
3945	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
3946	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
3947	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
3948	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
3949	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3950	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
3951	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3952	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3953	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3954	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3955	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
3956	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
3957	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
3958	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
3959	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
3960	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
3961	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
3962	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
3963	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3964	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3965	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3966	/** @} */
3967
3968	/** @name IEMAllCImpl.cpp
3969	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
3970	* @{ */
3971	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
3972	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
3973	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
3974	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
3975	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
3976	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
3977	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
3978	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
3979	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
3980	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
3981	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
3982	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
3983	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskSegment, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3984	IEM_CIMPL_PROTO_4(iemCImpl_BranchTaskGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3985	IEM_CIMPL_PROTO_4(iemCImpl_BranchCallGate, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3986	IEM_CIMPL_PROTO_4(iemCImpl_BranchSysSel, uint16_t, uSel, IEMBRANCH, enmBranch, IEMMODE, enmEffOpSize, PIEMSELDESC, pDesc);
3987	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
3988	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
3989	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
3990	IEM_CIMPL_PROTO_2(iemCImpl_retn, IEMMODE, enmEffOpSize, uint16_t, cbPop);
3991	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
3992	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
3993	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
3994	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
3995	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
3996	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
3997	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
3998	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
3999	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
4000	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
4001	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
4002	IEM_CIMPL_PROTO_0(iemCImpl_sysret);
4003	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
4004	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
4005	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
4006	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
4007	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
4008	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
4009	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
4010	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
4011	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
4012	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4013	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4014	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4015	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4016	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
4017	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4018	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4019	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
4020	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4021	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4022	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
4023	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4024	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4025	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
4026	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
4027	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
4028	IEM_CIMPL_PROTO_0(iemCImpl_clts);
4029	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
4030	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
4031	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
4032	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
4033	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
4034	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
4035	IEM_CIMPL_PROTO_0(iemCImpl_invd);
4036	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
4037	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
4038	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
4039	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
4040	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
4041	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
4042	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
4043	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
4044	IEM_CIMPL_PROTO_1(iemCImpl_in_eAX_DX, uint8_t, cbReg);
4045	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
4046	IEM_CIMPL_PROTO_1(iemCImpl_out_DX_eAX, uint8_t, cbReg);
4047	IEM_CIMPL_PROTO_0(iemCImpl_cli);
4048	IEM_CIMPL_PROTO_0(iemCImpl_sti);
4049	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
4050	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
4051	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
4052	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
4053	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
4054	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
4055	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
4056	IEM_CIMPL_PROTO_0(iemCImpl_daa);
4057	IEM_CIMPL_PROTO_0(iemCImpl_das);
4058	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
4059	IEM_CIMPL_PROTO_0(iemCImpl_aas);
4060	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
4061	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
4062	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
4063	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
4064	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
4065	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
4066	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4067	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
4068	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4069	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4070	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4071	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4072	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4073	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4074	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4075	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4076	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4077	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4078	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4079	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
4080	IEM_CIMPL_PROTO_1(iemCImpl_fxch_underflow, uint8_t, iStReg);
4081	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop);
4082	/** @} */
4083
4084	/** @name IEMAllCImplStrInstr.cpp.h
4085	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
4086	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
4087	* @{ */
4088	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
4089	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
4090	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
4091	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
4092	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
4093	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
4094	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
4095	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
4096	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
4097	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4098	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4099
4100	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
4101	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
4102	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
4103	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
4104	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
4105	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
4106	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
4107	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
4108	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
4109	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4110	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4111
4112	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
4113	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
4114	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
4115	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
4116	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
4117	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
4118	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
4119	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
4120	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
4121	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4122	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4123
4124
4125	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
4126	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
4127	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
4128	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
4129	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
4130	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
4131	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
4132	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
4133	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
4134	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4135	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4136
4137	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
4138	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
4139	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
4140	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
4141	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
4142	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
4143	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
4144	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
4145	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
4146	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4147	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4148
4149	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
4150	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
4151	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
4152	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
4153	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
4154	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
4155	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
4156	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
4157	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
4158	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4159	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4160
4161	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
4162	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
4163	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
4164	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
4165	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
4166	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
4167	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
4168	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
4169	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
4170	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4171	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4172
4173
4174	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
4175	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
4176	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
4177	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
4178	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
4179	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
4180	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
4181	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
4182	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
4183	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4184	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4185
4186	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
4187	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
4188	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
4189	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
4190	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
4191	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
4192	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
4193	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
4194	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
4195	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4196	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4197
4198	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
4199	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
4200	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
4201	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
4202	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
4203	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
4204	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
4205	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
4206	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
4207	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4208	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4209
4210	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
4211	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
4212	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
4213	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
4214	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
4215	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
4216	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
4217	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
4218	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
4219	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4220	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4221	/** @} */
4222
4223	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4224	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
4225	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
4226	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
4227	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
4228	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
4229	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4230	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
4231	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
4232	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
4233	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
4234	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
4235	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
4236	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
4237	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4238	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4239	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4240	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4241	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4242	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4243	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
4244	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
4245	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
4246	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
4247	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
4248	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
4249	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
4250	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
4251	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
4252	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
4253	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
4254	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
4255	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
4256	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
4257	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
4258	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4259	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4260	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4261	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
4262	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
4263	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
4264	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField);
4265	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
4266	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
4267	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
4268	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
4269	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
4270	#endif
4271
4272	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4273	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
4274	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4275	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
4276	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
4277	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite) RT_NOEXCEPT;
4278	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
4279	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
4280	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
4281	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
4282	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
4283	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
4284	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
4285	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
4286	#endif
4287
4288	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
4289	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
4290	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
4291
4292
4293	extern const PFNIEMOP g_apfnOneByteMap[256];
4294
4295	/** @} */
4296
4297	RT_C_DECLS_END
4298
4299	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
4300

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 97472

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