IEMInternal.h@ 98795

Last change on this file since 98795 was 98795, checked in by vboxsync, 22 months ago
VMM/IEM: s/g_apfnOneByteMap/g_apfnIemInterpretOnlyOneByteMap/ and other changes relating to compiling the instruction decoding and emulation bits more than once. bugref:10368
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 223.1 KB

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1	/* $Id: IEMInternal.h 98795 2023-03-01 00:05:10Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41
42
43	RT_C_DECLS_BEGIN
44
45
46	/** @defgroup grp_iem_int Internals
47	* @ingroup grp_iem
48	* @internal
49	* @{
50	*/
51
52	/** For expanding symbol in slickedit and other products tagging and
53	* crossreferencing IEM symbols. */
54	#ifndef IEM_STATIC
55	# define IEM_STATIC static
56	#endif
57
58	/** @def IEM_WITH_SETJMP
59	* Enables alternative status code handling using setjmps.
60	*
61	* This adds a bit of expense via the setjmp() call since it saves all the
62	* non-volatile registers. However, it eliminates return code checks and allows
63	* for more optimal return value passing (return regs instead of stack buffer).
64	*/
65	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
66	# define IEM_WITH_SETJMP
67	#endif
68
69	/** @def IEM_WITH_THROW_CATCH
70	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
71	* mode code when IEM_WITH_SETJMP is in effect.
72	*
73	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
74	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
75	* result value improving by more than 1%. (Best out of three.)
76	*
77	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
78	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
79	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
80	* Linux, but it should be quite a bit faster for normal code.
81	*/
82	#if (defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
83	\|\| defined(DOXYGEN_RUNNING)
84	# define IEM_WITH_THROW_CATCH
85	#endif
86
87	/** @def IEM_DO_LONGJMP
88	*
89	* Wrapper around longjmp / throw.
90	*
91	* @param a_pVCpu The CPU handle.
92	* @param a_rc The status code jump back with / throw.
93	*/
94	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
95	# ifdef IEM_WITH_THROW_CATCH
96	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
97	# else
98	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
99	# endif
100	#endif
101
102	/** For use with IEM function that may do a longjmp (when enabled).
103	*
104	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
105	* attribute. So, we indicate that function that may be part of a longjmp may
106	* throw "exceptions" and that the compiler should definitely not generate and
107	* std::terminate calling unwind code.
108	*
109	* Here is one example of this ending in std::terminate:
110	* @code{.txt}
111	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
112	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
113	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
114	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
115	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
116	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
117	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
118	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
119	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
120	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
121	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
122	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
123	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
124	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
125	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
126	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
127	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
128	@endcode
129	*
130	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
131	*/
132	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
133	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
134	#else
135	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
136	#endif
137
138	#define IEM_IMPLEMENTS_TASKSWITCH
139
140	/** @def IEM_WITH_3DNOW
141	* Includes the 3DNow decoding. */
142	#define IEM_WITH_3DNOW
143
144	/** @def IEM_WITH_THREE_0F_38
145	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
146	#define IEM_WITH_THREE_0F_38
147
148	/** @def IEM_WITH_THREE_0F_3A
149	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
150	#define IEM_WITH_THREE_0F_3A
151
152	/** @def IEM_WITH_VEX
153	* Includes the VEX decoding. */
154	#define IEM_WITH_VEX
155
156	/** @def IEM_CFG_TARGET_CPU
157	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
158	*
159	* By default we allow this to be configured by the user via the
160	* CPUM/GuestCpuName config string, but this comes at a slight cost during
161	* decoding. So, for applications of this code where there is no need to
162	* be dynamic wrt target CPU, just modify this define.
163	*/
164	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
165	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
166	#endif
167
168	//#define IEM_WITH_CODE_TLB // - work in progress
169	//#define IEM_WITH_DATA_TLB // - work in progress
170
171
172	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
173	* Use unaligned accesses instead of elaborate byte assembly. */
174	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
175	# define IEM_USE_UNALIGNED_DATA_ACCESS
176	#endif
177
178	//#define IEM_LOG_MEMORY_WRITES
179
180	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
181	/** Instruction statistics. */
182	typedef struct IEMINSTRSTATS
183	{
184	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
185	# include "IEMInstructionStatisticsTmpl.h"
186	# undef IEM_DO_INSTR_STAT
187	} IEMINSTRSTATS;
188	#else
189	struct IEMINSTRSTATS;
190	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
191	#endif
192	/** Pointer to IEM instruction statistics. */
193	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
194
195
196	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
197	* @{ */
198	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
199	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
200	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
201	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
202	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
203	/** Selects the right variant from a_aArray.
204	* pVCpu is implicit in the caller context. */
205	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
206	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
207	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
208	* be used because the host CPU does not support the operation. */
209	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
210	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
211	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
212	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
213	* into the two.
214	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
215	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
216	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
217	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
218	#else
219	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
220	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
221	#endif
222	/** @} */
223
224	/**
225	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
226	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
227	*
228	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
229	* indicator.
230	*
231	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
232	*/
233	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
234	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
235	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
236	#else
237	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
238	#endif
239
240
241	/**
242	* Extended operand mode that includes a representation of 8-bit.
243	*
244	* This is used for packing down modes when invoking some C instruction
245	* implementations.
246	*/
247	typedef enum IEMMODEX
248	{
249	IEMMODEX_16BIT = IEMMODE_16BIT,
250	IEMMODEX_32BIT = IEMMODE_32BIT,
251	IEMMODEX_64BIT = IEMMODE_64BIT,
252	IEMMODEX_8BIT
253	} IEMMODEX;
254	AssertCompileSize(IEMMODEX, 4);
255
256
257	/**
258	* Branch types.
259	*/
260	typedef enum IEMBRANCH
261	{
262	IEMBRANCH_JUMP = 1,
263	IEMBRANCH_CALL,
264	IEMBRANCH_TRAP,
265	IEMBRANCH_SOFTWARE_INT,
266	IEMBRANCH_HARDWARE_INT
267	} IEMBRANCH;
268	AssertCompileSize(IEMBRANCH, 4);
269
270
271	/**
272	* INT instruction types.
273	*/
274	typedef enum IEMINT
275	{
276	/** INT n instruction (opcode 0xcd imm). */
277	IEMINT_INTN = 0,
278	/** Single byte INT3 instruction (opcode 0xcc). */
279	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
280	/** Single byte INTO instruction (opcode 0xce). */
281	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
282	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
283	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
284	} IEMINT;
285	AssertCompileSize(IEMINT, 4);
286
287
288	/**
289	* A FPU result.
290	*/
291	typedef struct IEMFPURESULT
292	{
293	/** The output value. */
294	RTFLOAT80U r80Result;
295	/** The output status. */
296	uint16_t FSW;
297	} IEMFPURESULT;
298	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
299	/** Pointer to a FPU result. */
300	typedef IEMFPURESULT *PIEMFPURESULT;
301	/** Pointer to a const FPU result. */
302	typedef IEMFPURESULT const *PCIEMFPURESULT;
303
304
305	/**
306	* A FPU result consisting of two output values and FSW.
307	*/
308	typedef struct IEMFPURESULTTWO
309	{
310	/** The first output value. */
311	RTFLOAT80U r80Result1;
312	/** The output status. */
313	uint16_t FSW;
314	/** The second output value. */
315	RTFLOAT80U r80Result2;
316	} IEMFPURESULTTWO;
317	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
318	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
319	/** Pointer to a FPU result consisting of two output values and FSW. */
320	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
321	/** Pointer to a const FPU result consisting of two output values and FSW. */
322	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
323
324
325	/**
326	* IEM TLB entry.
327	*
328	* Lookup assembly:
329	* @code{.asm}
330	; Calculate tag.
331	mov rax, [VA]
332	shl rax, 16
333	shr rax, 16 + X86_PAGE_SHIFT
334	or rax, [uTlbRevision]
335
336	; Do indexing.
337	movzx ecx, al
338	lea rcx, [pTlbEntries + rcx]
339
340	; Check tag.
341	cmp [rcx + IEMTLBENTRY.uTag], rax
342	jne .TlbMiss
343
344	; Check access.
345	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
346	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
347	cmp rax, [uTlbPhysRev]
348	jne .TlbMiss
349
350	; Calc address and we're done.
351	mov eax, X86_PAGE_OFFSET_MASK
352	and eax, [VA]
353	or rax, [rcx + IEMTLBENTRY.pMappingR3]
354	%ifdef VBOX_WITH_STATISTICS
355	inc qword [cTlbHits]
356	%endif
357	jmp .Done
358
359	.TlbMiss:
360	mov r8d, ACCESS_FLAGS
361	mov rdx, [VA]
362	mov rcx, [pVCpu]
363	call iemTlbTypeMiss
364	.Done:
365
366	@endcode
367	*
368	*/
369	typedef struct IEMTLBENTRY
370	{
371	/** The TLB entry tag.
372	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
373	* is ASSUMING a virtual address width of 48 bits.
374	*
375	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
376	*
377	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
378	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
379	* revision wraps around though, the tags needs to be zeroed.
380	*
381	* @note Try use SHRD instruction? After seeing
382	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
383	*
384	* @todo This will need to be reorganized for 57-bit wide virtual address and
385	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
386	* have to move the TLB entry versioning entirely to the
387	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
388	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
389	* consumed by PCID and ASID (12 + 6 = 18).
390	*/
391	uint64_t uTag;
392	/** Access flags and physical TLB revision.
393	*
394	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
395	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
396	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
397	* - Bit 3 - pgm phys/virt - not directly writable.
398	* - Bit 4 - pgm phys page - not directly readable.
399	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
400	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
401	* - Bit 7 - tlb entry - pMappingR3 member not valid.
402	* - Bits 63 thru 8 are used for the physical TLB revision number.
403	*
404	* We're using complemented bit meanings here because it makes it easy to check
405	* whether special action is required. For instance a user mode write access
406	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
407	* non-zero result would mean special handling needed because either it wasn't
408	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
409	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
410	* need to check any PTE flag.
411	*/
412	uint64_t fFlagsAndPhysRev;
413	/** The guest physical page address. */
414	uint64_t GCPhys;
415	/** Pointer to the ring-3 mapping. */
416	R3PTRTYPE(uint8_t *) pbMappingR3;
417	#if HC_ARCH_BITS == 32
418	uint32_t u32Padding1;
419	#endif
420	} IEMTLBENTRY;
421	AssertCompileSize(IEMTLBENTRY, 32);
422	/** Pointer to an IEM TLB entry. */
423	typedef IEMTLBENTRY *PIEMTLBENTRY;
424
425	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
426	* @{ */
427	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
428	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
429	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
430	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
431	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
432	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
433	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
434	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
435	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
436	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
437	/** @} */
438
439
440	/**
441	* An IEM TLB.
442	*
443	* We've got two of these, one for data and one for instructions.
444	*/
445	typedef struct IEMTLB
446	{
447	/** The TLB entries.
448	* We've choosen 256 because that way we can obtain the result directly from a
449	* 8-bit register without an additional AND instruction. */
450	IEMTLBENTRY aEntries[256];
451	/** The TLB revision.
452	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
453	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
454	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
455	* (The revision zero indicates an invalid TLB entry.)
456	*
457	* The initial value is choosen to cause an early wraparound. */
458	uint64_t uTlbRevision;
459	/** The TLB physical address revision - shadow of PGM variable.
460	*
461	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
462	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
463	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
464	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
465	*
466	* The initial value is choosen to cause an early wraparound. */
467	uint64_t volatile uTlbPhysRev;
468
469	/* Statistics: */
470
471	/** TLB hits (VBOX_WITH_STATISTICS only). */
472	uint64_t cTlbHits;
473	/** TLB misses. */
474	uint32_t cTlbMisses;
475	/** Slow read path. */
476	uint32_t cTlbSlowReadPath;
477	#if 0
478	/** TLB misses because of tag mismatch. */
479	uint32_t cTlbMissesTag;
480	/** TLB misses because of virtual access violation. */
481	uint32_t cTlbMissesVirtAccess;
482	/** TLB misses because of dirty bit. */
483	uint32_t cTlbMissesDirty;
484	/** TLB misses because of MMIO */
485	uint32_t cTlbMissesMmio;
486	/** TLB misses because of write access handlers. */
487	uint32_t cTlbMissesWriteHandler;
488	/** TLB misses because no r3(/r0) mapping. */
489	uint32_t cTlbMissesMapping;
490	#endif
491	/** Alignment padding. */
492	uint32_t au32Padding[3+5];
493	} IEMTLB;
494	AssertCompileSizeAlignment(IEMTLB, 64);
495	/** IEMTLB::uTlbRevision increment. */
496	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
497	/** IEMTLB::uTlbRevision mask. */
498	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
499	/** IEMTLB::uTlbPhysRev increment.
500	* @sa IEMTLBE_F_PHYS_REV */
501	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
502	/**
503	* Calculates the TLB tag for a virtual address.
504	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
505	* @param a_pTlb The TLB.
506	* @param a_GCPtr The virtual address.
507	*/
508	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
509	/**
510	* Calculates the TLB tag for a virtual address but without TLB revision.
511	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
512	* @param a_GCPtr The virtual address.
513	*/
514	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
515	/**
516	* Converts a TLB tag value into a TLB index.
517	* @returns Index into IEMTLB::aEntries.
518	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
519	*/
520	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
521	/**
522	* Converts a TLB tag value into a TLB index.
523	* @returns Index into IEMTLB::aEntries.
524	* @param a_pTlb The TLB.
525	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
526	*/
527	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
528
529
530	/**
531	* The per-CPU IEM state.
532	*/
533	typedef struct IEMCPU
534	{
535	/** Info status code that needs to be propagated to the IEM caller.
536	* This cannot be passed internally, as it would complicate all success
537	* checks within the interpreter making the code larger and almost impossible
538	* to get right. Instead, we'll store status codes to pass on here. Each
539	* source of these codes will perform appropriate sanity checks. */
540	int32_t rcPassUp; /* 0x00 */
541
542	/** The current CPU execution mode (CS). */
543	IEMMODE enmCpuMode; /* 0x04 */
544	/** The CPL. */
545	uint8_t uCpl; /* 0x05 */
546
547	/** Whether to bypass access handlers or not. */
548	bool fBypassHandlers : 1; /* 0x06.0 */
549	/** Whether to disregard the lock prefix (implied or not). */
550	bool fDisregardLock : 1; /* 0x06.1 */
551	/** Whether there are pending hardware instruction breakpoints. */
552	bool fPendingInstructionBreakpoints : 1; /* 0x06.2 */
553	/** Whether there are pending hardware data breakpoints. */
554	bool fPendingDataBreakpoints : 1; /* 0x06.3 */
555	/** Whether there are pending hardware I/O breakpoints. */
556	bool fPendingIoBreakpoints : 1; /* 0x06.4 */
557
558	/* Unused/padding */
559	bool fUnused; /* 0x07 */
560
561	/** @name Decoder state.
562	* @{ */
563	#ifdef IEM_WITH_CODE_TLB
564	/** The offset of the next instruction byte. */
565	uint32_t offInstrNextByte; /* 0x08 */
566	/** The number of bytes available at pbInstrBuf for the current instruction.
567	* This takes the max opcode length into account so that doesn't need to be
568	* checked separately. */
569	uint32_t cbInstrBuf; /* 0x0c */
570	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
571	* This can be NULL if the page isn't mappable for some reason, in which
572	* case we'll do fallback stuff.
573	*
574	* If we're executing an instruction from a user specified buffer,
575	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
576	* aligned pointer but pointer to the user data.
577	*
578	* For instructions crossing pages, this will start on the first page and be
579	* advanced to the next page by the time we've decoded the instruction. This
580	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
581	*/
582	uint8_t const pbInstrBuf; / 0x10 */
583	# if ARCH_BITS == 32
584	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
585	# endif
586	/** The program counter corresponding to pbInstrBuf.
587	* This is set to a non-canonical address when we need to invalidate it. */
588	uint64_t uInstrBufPc; /* 0x18 */
589	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
590	* This takes the CS segment limit into account. */
591	uint16_t cbInstrBufTotal; /* 0x20 */
592	/** Offset into pbInstrBuf of the first byte of the current instruction.
593	* Can be negative to efficiently handle cross page instructions. */
594	int16_t offCurInstrStart; /* 0x22 */
595
596	/** The prefix mask (IEM_OP_PRF_XXX). */
597	uint32_t fPrefixes; /* 0x24 */
598	/** The extra REX ModR/M register field bit (REX.R << 3). */
599	uint8_t uRexReg; /* 0x28 */
600	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
601	* (REX.B << 3). */
602	uint8_t uRexB; /* 0x29 */
603	/** The extra REX SIB index field bit (REX.X << 3). */
604	uint8_t uRexIndex; /* 0x2a */
605
606	/** The effective segment register (X86_SREG_XXX). */
607	uint8_t iEffSeg; /* 0x2b */
608
609	/** The offset of the ModR/M byte relative to the start of the instruction. */
610	uint8_t offModRm; /* 0x2c */
611	#else /* !IEM_WITH_CODE_TLB */
612	/** The size of what has currently been fetched into abOpcode. */
613	uint8_t cbOpcode; /* 0x08 */
614	/** The current offset into abOpcode. */
615	uint8_t offOpcode; /* 0x09 */
616	/** The offset of the ModR/M byte relative to the start of the instruction. */
617	uint8_t offModRm; /* 0x0a */
618
619	/** The effective segment register (X86_SREG_XXX). */
620	uint8_t iEffSeg; /* 0x0b */
621
622	/** The prefix mask (IEM_OP_PRF_XXX). */
623	uint32_t fPrefixes; /* 0x0c */
624	/** The extra REX ModR/M register field bit (REX.R << 3). */
625	uint8_t uRexReg; /* 0x10 */
626	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
627	* (REX.B << 3). */
628	uint8_t uRexB; /* 0x11 */
629	/** The extra REX SIB index field bit (REX.X << 3). */
630	uint8_t uRexIndex; /* 0x12 */
631
632	#endif /* !IEM_WITH_CODE_TLB */
633
634	/** The effective operand mode. */
635	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
636	/** The default addressing mode. */
637	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
638	/** The effective addressing mode. */
639	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
640	/** The default operand mode. */
641	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
642
643	/** Prefix index (VEX.pp) for two byte and three byte tables. */
644	uint8_t idxPrefix; /* 0x31, 0x17 */
645	/** 3rd VEX/EVEX/XOP register.
646	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
647	uint8_t uVex3rdReg; /* 0x32, 0x18 */
648	/** The VEX/EVEX/XOP length field. */
649	uint8_t uVexLength; /* 0x33, 0x19 */
650	/** Additional EVEX stuff. */
651	uint8_t fEvexStuff; /* 0x34, 0x1a */
652
653	/** Explicit alignment padding. */
654	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
655	/** The FPU opcode (FOP). */
656	uint16_t uFpuOpcode; /* 0x36, 0x1c */
657	#ifndef IEM_WITH_CODE_TLB
658	/** Explicit alignment padding. */
659	uint8_t abAlignment2b[2]; /* 0x1e */
660	#endif
661
662	/** The opcode bytes. */
663	uint8_t abOpcode[15]; /* 0x48, 0x20 */
664	/** Explicit alignment padding. */
665	#ifdef IEM_WITH_CODE_TLB
666	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
667	#else
668	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
669	#endif
670	/** @} */
671
672
673	/** The flags of the current exception / interrupt. */
674	uint32_t fCurXcpt; /* 0x48, 0x48 */
675	/** The current exception / interrupt. */
676	uint8_t uCurXcpt;
677	/** Exception / interrupt recursion depth. */
678	int8_t cXcptRecursions;
679
680	/** The number of active guest memory mappings. */
681	uint8_t cActiveMappings;
682	/** The next unused mapping index. */
683	uint8_t iNextMapping;
684	/** Records for tracking guest memory mappings. */
685	struct
686	{
687	/** The address of the mapped bytes. */
688	void *pv;
689	/** The access flags (IEM_ACCESS_XXX).
690	* IEM_ACCESS_INVALID if the entry is unused. */
691	uint32_t fAccess;
692	#if HC_ARCH_BITS == 64
693	uint32_t u32Alignment4; /*< Alignment padding. /
694	#endif
695	} aMemMappings[3];
696
697	/** Locking records for the mapped memory. */
698	union
699	{
700	PGMPAGEMAPLOCK Lock;
701	uint64_t au64Padding[2];
702	} aMemMappingLocks[3];
703
704	/** Bounce buffer info.
705	* This runs in parallel to aMemMappings. */
706	struct
707	{
708	/** The physical address of the first byte. */
709	RTGCPHYS GCPhysFirst;
710	/** The physical address of the second page. */
711	RTGCPHYS GCPhysSecond;
712	/** The number of bytes in the first page. */
713	uint16_t cbFirst;
714	/** The number of bytes in the second page. */
715	uint16_t cbSecond;
716	/** Whether it's unassigned memory. */
717	bool fUnassigned;
718	/** Explicit alignment padding. */
719	bool afAlignment5[3];
720	} aMemBbMappings[3];
721
722	/* Ensure that aBounceBuffers are aligned at a 32 byte boundrary. */
723	uint64_t abAlignment7[1];
724
725	/** Bounce buffer storage.
726	* This runs in parallel to aMemMappings and aMemBbMappings. */
727	struct
728	{
729	uint8_t ab[512];
730	} aBounceBuffers[3];
731
732
733	/** Pointer set jump buffer - ring-3 context. */
734	R3PTRTYPE(jmp_buf *) pJmpBufR3;
735	/** Pointer set jump buffer - ring-0 context. */
736	R0PTRTYPE(jmp_buf *) pJmpBufR0;
737
738	/** @todo Should move this near @a fCurXcpt later. */
739	/** The CR2 for the current exception / interrupt. */
740	uint64_t uCurXcptCr2;
741	/** The error code for the current exception / interrupt. */
742	uint32_t uCurXcptErr;
743
744	/** @name Statistics
745	* @{ */
746	/** The number of instructions we've executed. */
747	uint32_t cInstructions;
748	/** The number of potential exits. */
749	uint32_t cPotentialExits;
750	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
751	* This may contain uncommitted writes. */
752	uint32_t cbWritten;
753	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
754	uint32_t cRetInstrNotImplemented;
755	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
756	uint32_t cRetAspectNotImplemented;
757	/** Counts informational statuses returned (other than VINF_SUCCESS). */
758	uint32_t cRetInfStatuses;
759	/** Counts other error statuses returned. */
760	uint32_t cRetErrStatuses;
761	/** Number of times rcPassUp has been used. */
762	uint32_t cRetPassUpStatus;
763	/** Number of times RZ left with instruction commit pending for ring-3. */
764	uint32_t cPendingCommit;
765	/** Number of long jumps. */
766	uint32_t cLongJumps;
767	/** @} */
768
769	/** @name Target CPU information.
770	* @{ */
771	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
772	/** The target CPU. */
773	uint8_t uTargetCpu;
774	#else
775	uint8_t bTargetCpuPadding;
776	#endif
777	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
778	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
779	* native host support and the 2nd for when there is.
780	*
781	* The two values are typically indexed by a g_CpumHostFeatures bit.
782	*
783	* This is for instance used for the BSF & BSR instructions where AMD and
784	* Intel CPUs produce different EFLAGS. */
785	uint8_t aidxTargetCpuEflFlavour[2];
786
787	/** The CPU vendor. */
788	CPUMCPUVENDOR enmCpuVendor;
789	/** @} */
790
791	/** @name Host CPU information.
792	* @{ */
793	/** The CPU vendor. */
794	CPUMCPUVENDOR enmHostCpuVendor;
795	/** @} */
796
797	/** Counts RDMSR \#GP(0) LogRel(). */
798	uint8_t cLogRelRdMsr;
799	/** Counts WRMSR \#GP(0) LogRel(). */
800	uint8_t cLogRelWrMsr;
801	/** Alignment padding. */
802	uint8_t abAlignment8[42];
803
804	/** Data TLB.
805	* @remarks Must be 64-byte aligned. */
806	IEMTLB DataTlb;
807	/** Instruction TLB.
808	* @remarks Must be 64-byte aligned. */
809	IEMTLB CodeTlb;
810
811	/** Exception statistics. */
812	STAMCOUNTER aStatXcpts[32];
813	/** Interrupt statistics. */
814	uint32_t aStatInts[256];
815
816	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
817	/** Instruction statistics for ring-0/raw-mode. */
818	IEMINSTRSTATS StatsRZ;
819	/** Instruction statistics for ring-3. */
820	IEMINSTRSTATS StatsR3;
821	#endif
822	} IEMCPU;
823	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
824	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 8);
825	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 16);
826	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 32);
827	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
828	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
829	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
830
831	/** Pointer to the per-CPU IEM state. */
832	typedef IEMCPU *PIEMCPU;
833	/** Pointer to the const per-CPU IEM state. */
834	typedef IEMCPU const *PCIEMCPU;
835
836
837	/** @def IEM_GET_CTX
838	* Gets the guest CPU context for the calling EMT.
839	* @returns PCPUMCTX
840	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
841	*/
842	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
843
844	/** @def IEM_CTX_ASSERT
845	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
846	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
847	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
848	*/
849	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
850	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
851	(a_fExtrnMbz)))
852
853	/** @def IEM_CTX_IMPORT_RET
854	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
855	*
856	* Will call the keep to import the bits as needed.
857	*
858	* Returns on import failure.
859	*
860	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
861	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
862	*/
863	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
864	do { \
865	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
866	{ /* likely */ } \
867	else \
868	{ \
869	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
870	AssertRCReturn(rcCtxImport, rcCtxImport); \
871	} \
872	} while (0)
873
874	/** @def IEM_CTX_IMPORT_NORET
875	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
876	*
877	* Will call the keep to import the bits as needed.
878	*
879	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
880	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
881	*/
882	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
883	do { \
884	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
885	{ /* likely */ } \
886	else \
887	{ \
888	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
889	AssertLogRelRC(rcCtxImport); \
890	} \
891	} while (0)
892
893	/** @def IEM_CTX_IMPORT_JMP
894	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
895	*
896	* Will call the keep to import the bits as needed.
897	*
898	* Jumps on import failure.
899	*
900	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
901	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
902	*/
903	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
904	do { \
905	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
906	{ /* likely */ } \
907	else \
908	{ \
909	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
910	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
911	} \
912	} while (0)
913
914
915
916	/** @def IEM_GET_TARGET_CPU
917	* Gets the current IEMTARGETCPU value.
918	* @returns IEMTARGETCPU value.
919	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
920	*/
921	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
922	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
923	#else
924	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
925	#endif
926
927	/** @def IEM_GET_INSTR_LEN
928	* Gets the instruction length. */
929	#ifdef IEM_WITH_CODE_TLB
930	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
931	#else
932	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
933	#endif
934
935
936	/**
937	* Shared per-VM IEM data.
938	*/
939	typedef struct IEM
940	{
941	/** The VMX APIC-access page handler type. */
942	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
943	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
944	/** Set if the CPUID host call functionality is enabled. */
945	bool fCpuIdHostCall;
946	#endif
947	} IEM;
948
949
950
951	/** @name IEM_ACCESS_XXX - Access details.
952	* @{ */
953	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
954	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
955	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
956	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
957	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
958	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
959	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
960	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
961	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
962	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
963	/** The writes are partial, so if initialize the bounce buffer with the
964	* orignal RAM content. */
965	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
966	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
967	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
968	/** Bounce buffer with ring-3 write pending, first page. */
969	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
970	/** Bounce buffer with ring-3 write pending, second page. */
971	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
972	/** Not locked, accessed via the TLB. */
973	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
974	/** Valid bit mask. */
975	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
976	/** Shift count for the TLB flags (upper word). */
977	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
978
979	/** Read+write data alias. */
980	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
981	/** Write data alias. */
982	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
983	/** Read data alias. */
984	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
985	/** Instruction fetch alias. */
986	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
987	/** Stack write alias. */
988	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
989	/** Stack read alias. */
990	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
991	/** Stack read+write alias. */
992	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
993	/** Read system table alias. */
994	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
995	/** Read+write system table alias. */
996	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
997	/** @} */
998
999	/** @name Prefix constants (IEMCPU::fPrefixes)
1000	* @{ */
1001	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
1002	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
1003	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
1004	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
1005	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
1006	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
1007	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
1008
1009	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
1010	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
1011	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
1012
1013	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
1014	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
1015	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
1016
1017	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
1018	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
1019	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
1020	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
1021	/** Mask with all the REX prefix flags.
1022	* This is generally for use when needing to undo the REX prefixes when they
1023	* are followed legacy prefixes and therefore does not immediately preceed
1024	* the first opcode byte.
1025	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
1026	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
1027
1028	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
1029	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
1030	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
1031	/** @} */
1032
1033	/** @name IEMOPFORM_XXX - Opcode forms
1034	* @note These are ORed together with IEMOPHINT_XXX.
1035	* @{ */
1036	/** ModR/M: reg, r/m */
1037	#define IEMOPFORM_RM 0
1038	/** ModR/M: reg, r/m (register) */
1039	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1040	/** ModR/M: reg, r/m (memory) */
1041	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1042	/** ModR/M: reg, r/m */
1043	#define IEMOPFORM_RMI 1
1044	/** ModR/M: reg, r/m (register) */
1045	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1046	/** ModR/M: reg, r/m (memory) */
1047	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1048	/** ModR/M: r/m, reg */
1049	#define IEMOPFORM_MR 2
1050	/** ModR/M: r/m (register), reg */
1051	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1052	/** ModR/M: r/m (memory), reg */
1053	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1054	/** ModR/M: r/m, reg */
1055	#define IEMOPFORM_MRI 3
1056	/** ModR/M: r/m (register), reg */
1057	#define IEMOPFORM_MRI_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1058	/** ModR/M: r/m (memory), reg */
1059	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1060	/** ModR/M: r/m only */
1061	#define IEMOPFORM_M 4
1062	/** ModR/M: r/m only (register). */
1063	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
1064	/** ModR/M: r/m only (memory). */
1065	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
1066	/** ModR/M: reg only */
1067	#define IEMOPFORM_R 5
1068
1069	/** VEX+ModR/M: reg, r/m */
1070	#define IEMOPFORM_VEX_RM 8
1071	/** VEX+ModR/M: reg, r/m (register) */
1072	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
1073	/** VEX+ModR/M: reg, r/m (memory) */
1074	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
1075	/** VEX+ModR/M: r/m, reg */
1076	#define IEMOPFORM_VEX_MR 9
1077	/** VEX+ModR/M: r/m (register), reg */
1078	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
1079	/** VEX+ModR/M: r/m (memory), reg */
1080	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
1081	/** VEX+ModR/M: r/m only */
1082	#define IEMOPFORM_VEX_M 10
1083	/** VEX+ModR/M: r/m only (register). */
1084	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
1085	/** VEX+ModR/M: r/m only (memory). */
1086	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
1087	/** VEX+ModR/M: reg only */
1088	#define IEMOPFORM_VEX_R 11
1089	/** VEX+ModR/M: reg, vvvv, r/m */
1090	#define IEMOPFORM_VEX_RVM 12
1091	/** VEX+ModR/M: reg, vvvv, r/m (register). */
1092	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
1093	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
1094	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
1095	/** VEX+ModR/M: reg, r/m, vvvv */
1096	#define IEMOPFORM_VEX_RMV 13
1097	/** VEX+ModR/M: reg, r/m, vvvv (register). */
1098	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
1099	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1100	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
1101	/** VEX+ModR/M: reg, r/m, imm8 */
1102	#define IEMOPFORM_VEX_RMI 14
1103	/** VEX+ModR/M: reg, r/m, imm8 (register). */
1104	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
1105	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1106	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1107	/** VEX+ModR/M: r/m, vvvv, reg */
1108	#define IEMOPFORM_VEX_MVR 15
1109	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1110	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1111	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1112	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1113	/** VEX+ModR/M+/n: vvvv, r/m */
1114	#define IEMOPFORM_VEX_VM 16
1115	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1116	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1117	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1118	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1119
1120	/** Fixed register instruction, no R/M. */
1121	#define IEMOPFORM_FIXED 32
1122
1123	/** The r/m is a register. */
1124	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1125	/** The r/m is a memory access. */
1126	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1127	/** @} */
1128
1129	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1130	* @note These are ORed together with IEMOPFORM_XXX.
1131	* @{ */
1132	/** Ignores the operand size prefix (66h). */
1133	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1134	/** Ignores REX.W (aka WIG). */
1135	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1136	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1137	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1138	/** Allowed with the lock prefix. */
1139	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1140	/** The VEX.L value is ignored (aka LIG). */
1141	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1142	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1143	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1144	/** The VEX.V value must be zero. */
1145	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1146
1147	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1148	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1149	/** @} */
1150
1151	/**
1152	* Possible hardware task switch sources.
1153	*/
1154	typedef enum IEMTASKSWITCH
1155	{
1156	/** Task switch caused by an interrupt/exception. */
1157	IEMTASKSWITCH_INT_XCPT = 1,
1158	/** Task switch caused by a far CALL. */
1159	IEMTASKSWITCH_CALL,
1160	/** Task switch caused by a far JMP. */
1161	IEMTASKSWITCH_JUMP,
1162	/** Task switch caused by an IRET. */
1163	IEMTASKSWITCH_IRET
1164	} IEMTASKSWITCH;
1165	AssertCompileSize(IEMTASKSWITCH, 4);
1166
1167	/**
1168	* Possible CrX load (write) sources.
1169	*/
1170	typedef enum IEMACCESSCRX
1171	{
1172	/** CrX access caused by 'mov crX' instruction. */
1173	IEMACCESSCRX_MOV_CRX,
1174	/** CrX (CR0) write caused by 'lmsw' instruction. */
1175	IEMACCESSCRX_LMSW,
1176	/** CrX (CR0) write caused by 'clts' instruction. */
1177	IEMACCESSCRX_CLTS,
1178	/** CrX (CR0) read caused by 'smsw' instruction. */
1179	IEMACCESSCRX_SMSW
1180	} IEMACCESSCRX;
1181
1182	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1183	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1184	*
1185	* These flags provide further context to SLAT page-walk failures that could not be
1186	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1187	*
1188	* @{
1189	*/
1190	/** Translating a nested-guest linear address failed accessing a nested-guest
1191	* physical address. */
1192	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1193	/** Translating a nested-guest linear address failed accessing a
1194	* paging-structure entry or updating accessed/dirty bits. */
1195	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1196	/** @} */
1197
1198	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1199	# ifndef IN_RING3
1200	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1201	# endif
1202	#endif
1203
1204	/**
1205	* Indicates to the verifier that the given flag set is undefined.
1206	*
1207	* Can be invoked again to add more flags.
1208	*
1209	* This is a NOOP if the verifier isn't compiled in.
1210	*
1211	* @note We're temporarily keeping this until code is converted to new
1212	* disassembler style opcode handling.
1213	*/
1214	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1215
1216
1217	/** @def IEM_DECL_IMPL_TYPE
1218	* For typedef'ing an instruction implementation function.
1219	*
1220	* @param a_RetType The return type.
1221	* @param a_Name The name of the type.
1222	* @param a_ArgList The argument list enclosed in parentheses.
1223	*/
1224
1225	/** @def IEM_DECL_IMPL_DEF
1226	* For defining an instruction implementation function.
1227	*
1228	* @param a_RetType The return type.
1229	* @param a_Name The name of the type.
1230	* @param a_ArgList The argument list enclosed in parentheses.
1231	*/
1232
1233	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1234	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1235	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1236	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1237	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1238	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1239	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1240
1241	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1242	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1243	a_RetType (__fastcall a_Name) a_ArgList
1244	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1245	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1246	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1247	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1248
1249	#elif __cplusplus >= 201700 /* P0012R1 support */
1250	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1251	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1252	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1253	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1254	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1255	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1256
1257	#else
1258	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1259	a_RetType (VBOXCALL a_Name) a_ArgList
1260	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1261	a_RetType VBOXCALL a_Name a_ArgList
1262	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1263	a_RetType VBOXCALL a_Name a_ArgList
1264
1265	#endif
1266
1267	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1268	RT_C_DECLS_BEGIN
1269	extern uint8_t const g_afParity[256];
1270	RT_C_DECLS_END
1271
1272
1273	/** @name Arithmetic assignment operations on bytes (binary).
1274	* @{ */
1275	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1276	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1277	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1278	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1279	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1280	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1281	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1282	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1283	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1284	/** @} */
1285
1286	/** @name Arithmetic assignment operations on words (binary).
1287	* @{ */
1288	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1289	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1290	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1291	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1292	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1293	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1294	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1295	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1296	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1297	/** @} */
1298
1299	/** @name Arithmetic assignment operations on double words (binary).
1300	* @{ */
1301	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1302	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1303	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1304	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1305	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1306	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1307	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1308	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1309	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1310	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1311	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1312	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1313	/** @} */
1314
1315	/** @name Arithmetic assignment operations on quad words (binary).
1316	* @{ */
1317	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1318	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1319	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1320	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1321	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1322	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1323	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1324	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1325	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1326	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1327	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1328	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1329	/** @} */
1330
1331	/** @name Compare operations (thrown in with the binary ops).
1332	* @{ */
1333	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1334	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1335	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1336	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1337	/** @} */
1338
1339	/** @name Test operations (thrown in with the binary ops).
1340	* @{ */
1341	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1342	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1343	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1344	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1345	/** @} */
1346
1347	/** @name Bit operations operations (thrown in with the binary ops).
1348	* @{ */
1349	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1350	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1351	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1352	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1353	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1354	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1355	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1356	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1357	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1358	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1359	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1360	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1361	/** @} */
1362
1363	/** @name Arithmetic three operand operations on double words (binary).
1364	* @{ */
1365	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
1366	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1367	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1368	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1369	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1370	/** @} */
1371
1372	/** @name Arithmetic three operand operations on quad words (binary).
1373	* @{ */
1374	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
1375	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1376	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1377	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1378	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1379	/** @} */
1380
1381	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1382	* @{ */
1383	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1384	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1385	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1386	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1387	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1388	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1389	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1390	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1391	/** @} */
1392
1393	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1394	* @{ */
1395	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1396	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1397	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1398	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1399	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1400	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1401	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1402	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1403	/** @} */
1404
1405	/** @name MULX 32-bit and 64-bit.
1406	* @{ */
1407	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
1408	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1409	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1410
1411	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
1412	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1413	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1414	/** @} */
1415
1416
1417	/** @name Exchange memory with register operations.
1418	* @{ */
1419	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1420	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1421	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1422	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1423	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1424	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1425	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1426	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1427	/** @} */
1428
1429	/** @name Exchange and add operations.
1430	* @{ */
1431	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1432	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1433	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1434	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1435	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1436	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1437	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1438	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1439	/** @} */
1440
1441	/** @name Compare and exchange.
1442	* @{ */
1443	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1444	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1445	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1446	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1447	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1448	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1449	#if ARCH_BITS == 32
1450	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1451	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1452	#else
1453	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1454	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1455	#endif
1456	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1457	uint32_t *pEFlags));
1458	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1459	uint32_t *pEFlags));
1460	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1461	uint32_t *pEFlags));
1462	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1463	uint32_t *pEFlags));
1464	#ifndef RT_ARCH_ARM64
1465	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1466	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1467	#endif
1468	/** @} */
1469
1470	/** @name Memory ordering
1471	* @{ */
1472	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1473	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1474	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1475	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1476	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1477	#ifndef RT_ARCH_ARM64
1478	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1479	#endif
1480	/** @} */
1481
1482	/** @name Double precision shifts
1483	* @{ */
1484	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1485	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1486	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1487	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1488	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1489	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1490	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1491	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1492	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1493	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1494	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1495	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1496	/** @} */
1497
1498
1499	/** @name Bit search operations (thrown in with the binary ops).
1500	* @{ */
1501	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1502	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1503	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1504	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1505	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1506	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1507	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1508	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1509	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1510	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
1511	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
1512	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
1513	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
1514	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
1515	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
1516	/** @} */
1517
1518	/** @name Signed multiplication operations (thrown in with the binary ops).
1519	* @{ */
1520	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1521	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1522	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1523	/** @} */
1524
1525	/** @name Arithmetic assignment operations on bytes (unary).
1526	* @{ */
1527	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1528	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1529	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1530	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1531	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1532	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1533	/** @} */
1534
1535	/** @name Arithmetic assignment operations on words (unary).
1536	* @{ */
1537	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1538	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1539	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1540	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1541	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1542	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1543	/** @} */
1544
1545	/** @name Arithmetic assignment operations on double words (unary).
1546	* @{ */
1547	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1548	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1549	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1550	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1551	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1552	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1553	/** @} */
1554
1555	/** @name Arithmetic assignment operations on quad words (unary).
1556	* @{ */
1557	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1558	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1559	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1560	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1561	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1562	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1563	/** @} */
1564
1565
1566	/** @name Shift operations on bytes (Group 2).
1567	* @{ */
1568	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1569	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1570	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1571	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1572	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1573	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1574	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1575	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1576	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1577	/** @} */
1578
1579	/** @name Shift operations on words (Group 2).
1580	* @{ */
1581	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1582	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1583	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1584	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1585	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1586	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1587	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1588	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1589	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1590	/** @} */
1591
1592	/** @name Shift operations on double words (Group 2).
1593	* @{ */
1594	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1595	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1596	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1597	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1598	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1599	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1600	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1601	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1602	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1603	/** @} */
1604
1605	/** @name Shift operations on words (Group 2).
1606	* @{ */
1607	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1608	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1609	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1610	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1611	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1612	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1613	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1614	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1615	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1616	/** @} */
1617
1618	/** @name Multiplication and division operations.
1619	* @{ */
1620	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1621	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1622	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1623	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1624	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1625	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1626
1627	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1628	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1629	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1630	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1631	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1632	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1633
1634	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1635	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1636	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1637	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1638	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1639	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1640
1641	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1642	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1643	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1644	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1645	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1646	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1647	/** @} */
1648
1649	/** @name Byte Swap.
1650	* @{ */
1651	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1652	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1653	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1654	/** @} */
1655
1656	/** @name Misc.
1657	* @{ */
1658	FNIEMAIMPLBINU16 iemAImpl_arpl;
1659	/** @} */
1660
1661	/** @name RDRAND and RDSEED
1662	* @{ */
1663	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
1664	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
1665	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
1666	typedef FNIEMAIMPLRDRANDSEEDU16 *FNIEMAIMPLPRDRANDSEEDU16;
1667	typedef FNIEMAIMPLRDRANDSEEDU32 *FNIEMAIMPLPRDRANDSEEDU32;
1668	typedef FNIEMAIMPLRDRANDSEEDU64 *FNIEMAIMPLPRDRANDSEEDU64;
1669
1670	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
1671	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
1672	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
1673	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
1674	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
1675	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
1676	/** @} */
1677
1678	/** @name FPU operations taking a 32-bit float argument
1679	* @{ */
1680	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1681	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1682	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1683
1684	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1685	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1686	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1687
1688	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1689	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1690	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1691	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1692	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1693	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1694	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1695
1696	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1697	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1698	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1699	/** @} */
1700
1701	/** @name FPU operations taking a 64-bit float argument
1702	* @{ */
1703	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1704	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1705	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
1706
1707	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1708	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1709	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1710
1711	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
1712	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1713	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1714	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1715	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1716	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1717	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1718
1719	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1720	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1721	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1722	/** @} */
1723
1724	/** @name FPU operations taking a 80-bit float argument
1725	* @{ */
1726	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1727	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1728	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1729	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1730	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1731	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1732	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1733	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1734	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1735	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1736	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1737	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1738
1739	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
1740	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
1741	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
1742
1743	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1744	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1745	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1746	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1747	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1748
1749	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1750	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1751	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1752	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1753	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1754
1755	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1756	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1757	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1758	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1759	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
1760	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1761	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1762	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
1763	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
1764
1765	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1766	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1767	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1768	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1769
1770	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1771	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1772	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1773	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1774	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1775	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1776	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1777	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1778	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1779
1780	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1781	PCRTFLOAT80U pr80Val));
1782	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1783	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
1784	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1785	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
1786
1787	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1788	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1789	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1790
1791	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
1792	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1793	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
1794
1795	/** @} */
1796
1797	/** @name FPU operations taking a 16-bit signed integer argument
1798	* @{ */
1799	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1800	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1801	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1802	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1803	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
1804	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
1805
1806	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1807	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1808	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1809	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1810	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1811	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1812
1813	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1814	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1815	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
1816	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
1817
1818	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1819	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
1820	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
1821	/** @} */
1822
1823	/** @name FPU operations taking a 32-bit signed integer argument
1824	* @{ */
1825	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1826	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1827	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1828	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1829	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
1830	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
1831
1832	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1833	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1834	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1835	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1836	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1837	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1838
1839	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1840	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1841	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
1842	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
1843
1844	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1845	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
1846	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
1847	/** @} */
1848
1849	/** @name FPU operations taking a 64-bit signed integer argument
1850	* @{ */
1851	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1852	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
1853	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
1854
1855	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1856	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
1857	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
1858	/** @} */
1859
1860
1861	/** Temporary type representing a 256-bit vector register. */
1862	typedef struct { uint64_t au64[4]; } IEMVMM256;
1863	/** Temporary type pointing to a 256-bit vector register. */
1864	typedef IEMVMM256 *PIEMVMM256;
1865	/** Temporary type pointing to a const 256-bit vector register. */
1866	typedef IEMVMM256 *PCIEMVMM256;
1867
1868
1869	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1870	* @{ */
1871	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
1872	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1873	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1874	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1875	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1876	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
1877	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1878	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
1879	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
1880	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
1881	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
1882	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
1883	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1884	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
1885	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1886	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
1887	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
1888	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
1889	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
1890	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
1891	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1892	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
1893	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
1894	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
1895	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
1896	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
1897	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
1898	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
1899	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
1900	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
1901	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
1902	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
1903	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
1904	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
1905	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
1906	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
1907	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
1908	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
1909	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
1910	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
1911	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
1912	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
1913	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
1914	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
1915	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
1916	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
1917	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
1918	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
1919	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
1920	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
1921	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
1922	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
1923	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
1924	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
1925	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
1926	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
1927	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
1928
1929	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
1930	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
1931	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1932	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
1933	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
1934	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
1935	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
1936	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
1937	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
1938	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
1939	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
1940	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
1941	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
1942	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
1943	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
1944	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
1945	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
1946	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
1947	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
1948	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
1949	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
1950	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
1951	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
1952	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
1953	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
1954	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
1955	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
1956	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
1957	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
1958	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
1959	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
1960	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
1961	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
1962	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
1963	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
1964	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
1965	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
1966	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
1967	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
1968	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
1969	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
1970	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
1971	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
1972	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
1973	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
1974	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
1975	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
1976	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
1977	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
1978	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
1979	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
1980	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
1981	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
1982	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
1983	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
1984	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
1985	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
1986
1987	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
1988	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
1989	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
1990	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
1991	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
1992	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
1993	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
1994	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
1995	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
1996	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
1997	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
1998	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
1999	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
2000	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
2001	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
2002	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
2003	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
2004	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
2005	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
2006	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
2007	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
2008	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
2009	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
2010	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
2011	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
2012	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
2013	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
2014	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
2015	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
2016	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
2017	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
2018	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
2019	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
2020	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
2021	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
2022	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
2023	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
2024	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
2025	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
2026	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
2027	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
2028	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
2029	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
2030	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
2031	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
2032	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
2033	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
2034	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
2035	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
2036	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
2037	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
2038	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
2039	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
2040	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
2041	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
2042	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
2043	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
2044
2045	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
2046	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
2047	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
2048	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
2049
2050	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
2051	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
2052	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
2053	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
2054	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
2055	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
2056	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
2057	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
2058	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
2059	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
2060	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
2061	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
2062	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
2063	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
2064	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
2065	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
2066	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
2067	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
2068	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
2069	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
2070	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
2071	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
2072	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
2073	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
2074	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
2075	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
2076	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
2077	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
2078	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
2079	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
2080	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
2081	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
2082	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
2083	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
2084	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
2085	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
2086	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
2087	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
2088	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
2089	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
2090	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
2091	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
2092	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
2093	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
2094	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
2095	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
2096	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
2097	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
2098	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
2099	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
2100	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
2101	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
2102	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
2103	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
2104	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
2105	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
2106	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
2107
2108	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
2109	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
2110	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
2111	/** @} */
2112
2113	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2114	* @{ */
2115	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2116	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2117	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2118	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2119	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2120	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2121	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2122	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2123	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2124	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2125
2126	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2127	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2128	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2129	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2130	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2131	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2132	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2133	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2134	/** @} */
2135
2136	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2137	* @{ */
2138	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2139	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2140	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2141	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2142	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2143	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2144	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2145	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2146	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2147	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2148	/** @} */
2149
2150	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2151	* @{ */
2152	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2153	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2154	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2155	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2156	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
2157	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2158	#ifndef IEM_WITHOUT_ASSEMBLY
2159	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2160	#endif
2161	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2162	/** @} */
2163
2164	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2165	* @{ */
2166	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2167	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2168	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2169	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2170	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2171	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2172	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2173	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2174	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2175	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2176	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2177	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2178	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2179	/** @} */
2180
2181	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2182	* @{ */
2183	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
2184	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2185	#ifndef IEM_WITHOUT_ASSEMBLY
2186	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2187	#endif
2188	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2189	/** @} */
2190
2191	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
2192	* @{ */
2193	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
2194	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
2195	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
2196	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
2197	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
2198	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
2199
2200	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
2201	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
2202	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
2203	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
2204	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
2205	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
2206
2207	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
2208	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
2209	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
2210	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
2211	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
2212	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
2213
2214	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
2215	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
2216	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
2217	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
2218	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
2219	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
2220	/** @} */
2221
2222
2223	/** @name Media (SSE/MMX/AVX) operation: Sort this later
2224	* @{ */
2225	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2226	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2227	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2228	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2229	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2230	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2231
2232	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2233	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2234	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2235	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2236	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2237
2238	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2239	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2240	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2241	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2242	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2243
2244	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2245	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2246	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2247	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2248	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2249
2250	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2251	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2252	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2253	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2254	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2255
2256	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2257	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2258	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2259	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2260	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2261
2262	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2263	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2264	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2265	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2266	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2267
2268	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2269	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2270	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2271	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2272	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2273
2274	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2275	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2276	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2277	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2278	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2279
2280	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2281	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2282	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2283	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2284	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2285
2286	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2287	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2288	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2289	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2290	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2291
2292	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2293	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2294	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2295	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2296	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2297
2298	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2299	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2300	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2301	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2302	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2303
2304	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2305	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2306	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2307	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2308	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2309
2310	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2311	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2312	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2313	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2314	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2315
2316	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2317	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2318
2319	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
2320	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
2321	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2322	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2323
2324	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
2325	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2326	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2327	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2328
2329	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2330	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2331	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2332	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2333	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2334
2335	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2336	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2337	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2338	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2339	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2340
2341
2342	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2343	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
2344	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2345	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
2346	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2347	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
2348
2349	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
2350	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
2351	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
2352	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
2353
2354	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
2355	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
2356	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
2357	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
2358
2359	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
2360	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
2361	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
2362	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
2363
2364	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
2365	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
2366	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
2367	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
2368	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
2369
2370	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
2371	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
2372	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
2373	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
2374	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
2375
2376	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
2377
2378	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
2379
2380	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
2381	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
2382	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
2383	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
2384	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
2385	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
2386	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2387	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2388
2389	typedef struct IEMPCMPISTRXSRC
2390	{
2391	RTUINT128U uSrc1;
2392	RTUINT128U uSrc2;
2393	} IEMPCMPISTRXSRC;
2394	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
2395	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
2396
2397	typedef struct IEMPCMPESTRXSRC
2398	{
2399	RTUINT128U uSrc1;
2400	RTUINT128U uSrc2;
2401	uint64_t u64Rax;
2402	uint64_t u64Rdx;
2403	} IEMPCMPESTRXSRC;
2404	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
2405	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
2406
2407	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpistri_u128,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2408	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpistri_u128_fallback,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2409	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpestri_u128,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2410	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpestri_u128_fallback,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2411
2412	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpistrm_u128,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2413	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpistrm_u128_fallback,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2414	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpestrm_u128,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2415	IEM_DECL_IMPL_DEF(void, iemAImpl_pcmpestrm_u128_fallback,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2416
2417	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
2418	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
2419	/** @} */
2420
2421	/** @name Media Odds and Ends
2422	* @{ */
2423	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
2424	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
2425	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
2426	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
2427	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
2428	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
2429	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
2430	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
2431
2432	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
2433	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
2434	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
2435	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
2436
2437	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2438	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
2439	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2440	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
2441	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2442	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
2443	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2444	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
2445
2446	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
2447	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
2448
2449	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
2450	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
2451
2452	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
2453	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
2454
2455	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
2456	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
2457
2458	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
2459	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
2460	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
2461	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
2462
2463	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
2464	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
2465
2466	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
2467	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
2468	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
2469	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
2470
2471	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
2472	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
2473
2474
2475	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2476	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
2477
2478	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
2479	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
2480
2481	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
2482	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
2483
2484	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
2485	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
2486
2487	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
2488	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
2489
2490
2491	typedef struct IEMMEDIAF2XMMSRC
2492	{
2493	X86XMMREG uSrc1;
2494	X86XMMREG uSrc2;
2495	} IEMMEDIAF2XMMSRC;
2496	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
2497	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
2498
2499	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
2500	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
2501
2502	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
2503	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
2504	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
2505	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
2506	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
2507	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
2508
2509	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
2510	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
2511
2512	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
2513	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
2514
2515	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
2516	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
2517
2518	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
2519	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
2520
2521	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
2522	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
2523
2524	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
2525	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
2526
2527	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
2528	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
2529
2530	/** @} */
2531
2532
2533	/** @name Function tables.
2534	* @{
2535	*/
2536
2537	/**
2538	* Function table for a binary operator providing implementation based on
2539	* operand size.
2540	*/
2541	typedef struct IEMOPBINSIZES
2542	{
2543	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
2544	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
2545	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
2546	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
2547	} IEMOPBINSIZES;
2548	/** Pointer to a binary operator function table. */
2549	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
2550
2551
2552	/**
2553	* Function table for a unary operator providing implementation based on
2554	* operand size.
2555	*/
2556	typedef struct IEMOPUNARYSIZES
2557	{
2558	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
2559	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
2560	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
2561	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
2562	} IEMOPUNARYSIZES;
2563	/** Pointer to a unary operator function table. */
2564	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
2565
2566
2567	/**
2568	* Function table for a shift operator providing implementation based on
2569	* operand size.
2570	*/
2571	typedef struct IEMOPSHIFTSIZES
2572	{
2573	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
2574	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
2575	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
2576	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
2577	} IEMOPSHIFTSIZES;
2578	/** Pointer to a shift operator function table. */
2579	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
2580
2581
2582	/**
2583	* Function table for a multiplication or division operation.
2584	*/
2585	typedef struct IEMOPMULDIVSIZES
2586	{
2587	PFNIEMAIMPLMULDIVU8 pfnU8;
2588	PFNIEMAIMPLMULDIVU16 pfnU16;
2589	PFNIEMAIMPLMULDIVU32 pfnU32;
2590	PFNIEMAIMPLMULDIVU64 pfnU64;
2591	} IEMOPMULDIVSIZES;
2592	/** Pointer to a multiplication or division operation function table. */
2593	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
2594
2595
2596	/**
2597	* Function table for a double precision shift operator providing implementation
2598	* based on operand size.
2599	*/
2600	typedef struct IEMOPSHIFTDBLSIZES
2601	{
2602	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
2603	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
2604	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
2605	} IEMOPSHIFTDBLSIZES;
2606	/** Pointer to a double precision shift function table. */
2607	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
2608
2609
2610	/**
2611	* Function table for media instruction taking two full sized media source
2612	* registers and one full sized destination register (AVX).
2613	*/
2614	typedef struct IEMOPMEDIAF3
2615	{
2616	PFNIEMAIMPLMEDIAF3U128 pfnU128;
2617	PFNIEMAIMPLMEDIAF3U256 pfnU256;
2618	} IEMOPMEDIAF3;
2619	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2620	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
2621
2622	/** @def IEMOPMEDIAF3_INIT_VARS_EX
2623	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2624	* given functions as initializers. For use in AVX functions where a pair of
2625	* functions are only used once and the function table need not be public. */
2626	#ifndef TST_IEM_CHECK_MC
2627	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2628	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2629	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2630	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2631	# else
2632	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2633	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2634	# endif
2635	#else
2636	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2637	#endif
2638	/** @def IEMOPMEDIAF3_INIT_VARS
2639	* Generate AVX function tables for the @a a_InstrNm instruction.
2640	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
2641	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
2642	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2643	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2644
2645	/**
2646	* Function table for media instruction taking two full sized media source
2647	* registers and one full sized destination register, but no additional state
2648	* (AVX).
2649	*/
2650	typedef struct IEMOPMEDIAOPTF3
2651	{
2652	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
2653	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
2654	} IEMOPMEDIAOPTF3;
2655	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2656	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
2657
2658	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
2659	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2660	* given functions as initializers. For use in AVX functions where a pair of
2661	* functions are only used once and the function table need not be public. */
2662	#ifndef TST_IEM_CHECK_MC
2663	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2664	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2665	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2666	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2667	# else
2668	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2669	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2670	# endif
2671	#else
2672	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2673	#endif
2674	/** @def IEMOPMEDIAOPTF3_INIT_VARS
2675	* Generate AVX function tables for the @a a_InstrNm instruction.
2676	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
2677	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
2678	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2679	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2680
2681	/**
2682	* Function table for media instruction taking one full sized media source
2683	* registers and one full sized destination register, but no additional state
2684	* (AVX).
2685	*/
2686	typedef struct IEMOPMEDIAOPTF2
2687	{
2688	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
2689	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
2690	} IEMOPMEDIAOPTF2;
2691	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
2692	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
2693
2694	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
2695	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2696	* given functions as initializers. For use in AVX functions where a pair of
2697	* functions are only used once and the function table need not be public. */
2698	#ifndef TST_IEM_CHECK_MC
2699	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2700	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2701	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2702	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2703	# else
2704	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2705	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2706	# endif
2707	#else
2708	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2709	#endif
2710	/** @def IEMOPMEDIAOPTF2_INIT_VARS
2711	* Generate AVX function tables for the @a a_InstrNm instruction.
2712	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
2713	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
2714	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2715	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2716
2717	/**
2718	* Function table for media instruction taking two full sized media source
2719	* registers and one full sized destination register and an 8-bit immediate, but no additional state
2720	* (AVX).
2721	*/
2722	typedef struct IEMOPMEDIAOPTF3IMM8
2723	{
2724	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
2725	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
2726	} IEMOPMEDIAOPTF3IMM8;
2727	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2728	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
2729
2730	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
2731	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2732	* given functions as initializers. For use in AVX functions where a pair of
2733	* functions are only used once and the function table need not be public. */
2734	#ifndef TST_IEM_CHECK_MC
2735	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2736	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2737	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2738	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2739	# else
2740	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2741	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2742	# endif
2743	#else
2744	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2745	#endif
2746	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
2747	* Generate AVX function tables for the @a a_InstrNm instruction.
2748	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
2749	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
2750	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2751	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2752	/** @} */
2753
2754
2755	/**
2756	* Function table for blend type instruction taking three full sized media source
2757	* registers and one full sized destination register, but no additional state
2758	* (AVX).
2759	*/
2760	typedef struct IEMOPBLENDOP
2761	{
2762	PFNIEMAIMPLAVXBLENDU128 pfnU128;
2763	PFNIEMAIMPLAVXBLENDU256 pfnU256;
2764	} IEMOPBLENDOP;
2765	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
2766	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
2767
2768	/** @def IEMOPBLENDOP_INIT_VARS_EX
2769	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2770	* given functions as initializers. For use in AVX functions where a pair of
2771	* functions are only used once and the function table need not be public. */
2772	#ifndef TST_IEM_CHECK_MC
2773	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2774	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2775	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2776	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2777	# else
2778	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2779	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2780	# endif
2781	#else
2782	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2783	#endif
2784	/** @def IEMOPBLENDOP_INIT_VARS
2785	* Generate AVX function tables for the @a a_InstrNm instruction.
2786	* @sa IEMOPBLENDOP_INIT_VARS_EX */
2787	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
2788	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2789	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2790
2791
2792	/** @name SSE/AVX single/double precision floating point operations.
2793	* @{ */
2794	/**
2795	* A SSE result.
2796	*/
2797	typedef struct IEMSSERESULT
2798	{
2799	/** The output value. */
2800	X86XMMREG uResult;
2801	/** The output status. */
2802	uint32_t MXCSR;
2803	} IEMSSERESULT;
2804	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
2805	/** Pointer to a SSE result. */
2806	typedef IEMSSERESULT *PIEMSSERESULT;
2807	/** Pointer to a const SSE result. */
2808	typedef IEMSSERESULT const *PCIEMSSERESULT;
2809
2810
2811	/**
2812	* A AVX128 result.
2813	*/
2814	typedef struct IEMAVX128RESULT
2815	{
2816	/** The output value. */
2817	X86XMMREG uResult;
2818	/** The output status. */
2819	uint32_t MXCSR;
2820	} IEMAVX128RESULT;
2821	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
2822	/** Pointer to a AVX128 result. */
2823	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
2824	/** Pointer to a const AVX128 result. */
2825	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
2826
2827
2828	/**
2829	* A AVX256 result.
2830	*/
2831	typedef struct IEMAVX256RESULT
2832	{
2833	/** The output value. */
2834	X86YMMREG uResult;
2835	/** The output status. */
2836	uint32_t MXCSR;
2837	} IEMAVX256RESULT;
2838	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
2839	/** Pointer to a AVX256 result. */
2840	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
2841	/** Pointer to a const AVX256 result. */
2842	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
2843
2844
2845	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2846	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
2847	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2848	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
2849	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2850	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
2851
2852	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2853	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
2854	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2855	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
2856	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2857	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
2858
2859	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
2860	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
2861
2862	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
2863	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
2864	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
2865	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
2866	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
2867	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
2868	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
2869	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
2870	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
2871	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
2872	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
2873	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
2874	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
2875	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
2876	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
2877	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
2878	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
2879	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
2880	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
2881	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
2882	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
2883	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
2884	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
2885
2886	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
2887	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
2888	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
2889	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
2890	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
2891	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
2892
2893	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
2894	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
2895	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
2896	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
2897	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
2898	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
2899	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
2900	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
2901	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
2902	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
2903	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
2904	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
2905	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
2906	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
2907	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
2908	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
2909	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
2910
2911	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
2912	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
2913	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
2914	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
2915	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
2916	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
2917	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
2918	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
2919	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
2920	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
2921	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
2922	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
2923	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
2924	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
2925	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
2926	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
2927	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
2928	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
2929	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
2930	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
2931	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
2932	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
2933
2934	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
2935	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
2936	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
2937	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
2938	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
2939	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
2940	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
2941	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
2942	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
2943	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
2944	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
2945	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
2946	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
2947	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
2948
2949	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
2950	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
2951	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
2952	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
2953	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
2954	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
2955	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
2956	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
2957	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
2958	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
2959	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
2960	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
2961	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
2962	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
2963	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
2964	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
2965	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
2966	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
2967	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
2968	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
2969	/** @} */
2970
2971	/** @name C instruction implementations for anything slightly complicated.
2972	* @{ */
2973
2974	/**
2975	* For typedef'ing or declaring a C instruction implementation function taking
2976	* no extra arguments.
2977	*
2978	* @param a_Name The name of the type.
2979	*/
2980	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
2981	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2982	/**
2983	* For defining a C instruction implementation function taking no extra
2984	* arguments.
2985	*
2986	* @param a_Name The name of the function
2987	*/
2988	# define IEM_CIMPL_DEF_0(a_Name) \
2989	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2990	/**
2991	* Prototype version of IEM_CIMPL_DEF_0.
2992	*/
2993	# define IEM_CIMPL_PROTO_0(a_Name) \
2994	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
2995	/**
2996	* For calling a C instruction implementation function taking no extra
2997	* arguments.
2998	*
2999	* This special call macro adds default arguments to the call and allow us to
3000	* change these later.
3001	*
3002	* @param a_fn The name of the function.
3003	*/
3004	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
3005
3006	/**
3007	* For typedef'ing or declaring a C instruction implementation function taking
3008	* one extra argument.
3009	*
3010	* @param a_Name The name of the type.
3011	* @param a_Type0 The argument type.
3012	* @param a_Arg0 The argument name.
3013	*/
3014	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
3015	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3016	/**
3017	* For defining a C instruction implementation function taking one extra
3018	* argument.
3019	*
3020	* @param a_Name The name of the function
3021	* @param a_Type0 The argument type.
3022	* @param a_Arg0 The argument name.
3023	*/
3024	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
3025	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3026	/**
3027	* Prototype version of IEM_CIMPL_DEF_1.
3028	*/
3029	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
3030	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3031	/**
3032	* For calling a C instruction implementation function taking one extra
3033	* argument.
3034	*
3035	* This special call macro adds default arguments to the call and allow us to
3036	* change these later.
3037	*
3038	* @param a_fn The name of the function.
3039	* @param a0 The name of the 1st argument.
3040	*/
3041	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
3042
3043	/**
3044	* For typedef'ing or declaring a C instruction implementation function taking
3045	* two extra arguments.
3046	*
3047	* @param a_Name The name of the type.
3048	* @param a_Type0 The type of the 1st argument
3049	* @param a_Arg0 The name of the 1st argument.
3050	* @param a_Type1 The type of the 2nd argument.
3051	* @param a_Arg1 The name of the 2nd argument.
3052	*/
3053	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3054	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3055	/**
3056	* For defining a C instruction implementation function taking two extra
3057	* arguments.
3058	*
3059	* @param a_Name The name of the function.
3060	* @param a_Type0 The type of the 1st argument
3061	* @param a_Arg0 The name of the 1st argument.
3062	* @param a_Type1 The type of the 2nd argument.
3063	* @param a_Arg1 The name of the 2nd argument.
3064	*/
3065	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3066	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3067	/**
3068	* Prototype version of IEM_CIMPL_DEF_2.
3069	*/
3070	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3071	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3072	/**
3073	* For calling a C instruction implementation function taking two extra
3074	* arguments.
3075	*
3076	* This special call macro adds default arguments to the call and allow us to
3077	* change these later.
3078	*
3079	* @param a_fn The name of the function.
3080	* @param a0 The name of the 1st argument.
3081	* @param a1 The name of the 2nd argument.
3082	*/
3083	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
3084
3085	/**
3086	* For typedef'ing or declaring a C instruction implementation function taking
3087	* three extra arguments.
3088	*
3089	* @param a_Name The name of the type.
3090	* @param a_Type0 The type of the 1st argument
3091	* @param a_Arg0 The name of the 1st argument.
3092	* @param a_Type1 The type of the 2nd argument.
3093	* @param a_Arg1 The name of the 2nd argument.
3094	* @param a_Type2 The type of the 3rd argument.
3095	* @param a_Arg2 The name of the 3rd argument.
3096	*/
3097	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3098	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3099	/**
3100	* For defining a C instruction implementation function taking three extra
3101	* arguments.
3102	*
3103	* @param a_Name The name of the function.
3104	* @param a_Type0 The type of the 1st argument
3105	* @param a_Arg0 The name of the 1st argument.
3106	* @param a_Type1 The type of the 2nd argument.
3107	* @param a_Arg1 The name of the 2nd argument.
3108	* @param a_Type2 The type of the 3rd argument.
3109	* @param a_Arg2 The name of the 3rd argument.
3110	*/
3111	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3112	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3113	/**
3114	* Prototype version of IEM_CIMPL_DEF_3.
3115	*/
3116	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3117	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3118	/**
3119	* For calling a C instruction implementation function taking three extra
3120	* arguments.
3121	*
3122	* This special call macro adds default arguments to the call and allow us to
3123	* change these later.
3124	*
3125	* @param a_fn The name of the function.
3126	* @param a0 The name of the 1st argument.
3127	* @param a1 The name of the 2nd argument.
3128	* @param a2 The name of the 3rd argument.
3129	*/
3130	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
3131
3132
3133	/**
3134	* For typedef'ing or declaring a C instruction implementation function taking
3135	* four extra arguments.
3136	*
3137	* @param a_Name The name of the type.
3138	* @param a_Type0 The type of the 1st argument
3139	* @param a_Arg0 The name of the 1st argument.
3140	* @param a_Type1 The type of the 2nd argument.
3141	* @param a_Arg1 The name of the 2nd argument.
3142	* @param a_Type2 The type of the 3rd argument.
3143	* @param a_Arg2 The name of the 3rd argument.
3144	* @param a_Type3 The type of the 4th argument.
3145	* @param a_Arg3 The name of the 4th argument.
3146	*/
3147	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3148	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
3149	/**
3150	* For defining a C instruction implementation function taking four extra
3151	* arguments.
3152	*
3153	* @param a_Name The name of the function.
3154	* @param a_Type0 The type of the 1st argument
3155	* @param a_Arg0 The name of the 1st argument.
3156	* @param a_Type1 The type of the 2nd argument.
3157	* @param a_Arg1 The name of the 2nd argument.
3158	* @param a_Type2 The type of the 3rd argument.
3159	* @param a_Arg2 The name of the 3rd argument.
3160	* @param a_Type3 The type of the 4th argument.
3161	* @param a_Arg3 The name of the 4th argument.
3162	*/
3163	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3164	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3165	a_Type2 a_Arg2, a_Type3 a_Arg3))
3166	/**
3167	* Prototype version of IEM_CIMPL_DEF_4.
3168	*/
3169	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3170	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3171	a_Type2 a_Arg2, a_Type3 a_Arg3))
3172	/**
3173	* For calling a C instruction implementation function taking four extra
3174	* arguments.
3175	*
3176	* This special call macro adds default arguments to the call and allow us to
3177	* change these later.
3178	*
3179	* @param a_fn The name of the function.
3180	* @param a0 The name of the 1st argument.
3181	* @param a1 The name of the 2nd argument.
3182	* @param a2 The name of the 3rd argument.
3183	* @param a3 The name of the 4th argument.
3184	*/
3185	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
3186
3187
3188	/**
3189	* For typedef'ing or declaring a C instruction implementation function taking
3190	* five extra arguments.
3191	*
3192	* @param a_Name The name of the type.
3193	* @param a_Type0 The type of the 1st argument
3194	* @param a_Arg0 The name of the 1st argument.
3195	* @param a_Type1 The type of the 2nd argument.
3196	* @param a_Arg1 The name of the 2nd argument.
3197	* @param a_Type2 The type of the 3rd argument.
3198	* @param a_Arg2 The name of the 3rd argument.
3199	* @param a_Type3 The type of the 4th argument.
3200	* @param a_Arg3 The name of the 4th argument.
3201	* @param a_Type4 The type of the 5th argument.
3202	* @param a_Arg4 The name of the 5th argument.
3203	*/
3204	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3205	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
3206	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
3207	a_Type3 a_Arg3, a_Type4 a_Arg4))
3208	/**
3209	* For defining a C instruction implementation function taking five extra
3210	* arguments.
3211	*
3212	* @param a_Name The name of the function.
3213	* @param a_Type0 The type of the 1st argument
3214	* @param a_Arg0 The name of the 1st argument.
3215	* @param a_Type1 The type of the 2nd argument.
3216	* @param a_Arg1 The name of the 2nd argument.
3217	* @param a_Type2 The type of the 3rd argument.
3218	* @param a_Arg2 The name of the 3rd argument.
3219	* @param a_Type3 The type of the 4th argument.
3220	* @param a_Arg3 The name of the 4th argument.
3221	* @param a_Type4 The type of the 5th argument.
3222	* @param a_Arg4 The name of the 5th argument.
3223	*/
3224	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3225	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3226	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3227	/**
3228	* Prototype version of IEM_CIMPL_DEF_5.
3229	*/
3230	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3231	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3232	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3233	/**
3234	* For calling a C instruction implementation function taking five extra
3235	* arguments.
3236	*
3237	* This special call macro adds default arguments to the call and allow us to
3238	* change these later.
3239	*
3240	* @param a_fn The name of the function.
3241	* @param a0 The name of the 1st argument.
3242	* @param a1 The name of the 2nd argument.
3243	* @param a2 The name of the 3rd argument.
3244	* @param a3 The name of the 4th argument.
3245	* @param a4 The name of the 5th argument.
3246	*/
3247	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
3248
3249	/** @} */
3250
3251
3252	/** @name Opcode Decoder Function Types.
3253	* @{ */
3254
3255	/** @typedef PFNIEMOP
3256	* Pointer to an opcode decoder function.
3257	*/
3258
3259	/** @def FNIEMOP_DEF
3260	* Define an opcode decoder function.
3261	*
3262	* We're using macors for this so that adding and removing parameters as well as
3263	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
3264	*
3265	* @param a_Name The function name.
3266	*/
3267
3268	/** @typedef PFNIEMOPRM
3269	* Pointer to an opcode decoder function with RM byte.
3270	*/
3271
3272	/** @def FNIEMOPRM_DEF
3273	* Define an opcode decoder function with RM byte.
3274	*
3275	* We're using macors for this so that adding and removing parameters as well as
3276	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
3277	*
3278	* @param a_Name The function name.
3279	*/
3280
3281	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3282	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
3283	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3284	# define FNIEMOP_DEF(a_Name) \
3285	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
3286	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3287	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3288	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3289	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3290
3291	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3292	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
3293	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3294	# define FNIEMOP_DEF(a_Name) \
3295	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3296	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3297	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3298	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3299	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3300
3301	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
3302	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3303	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3304	# define FNIEMOP_DEF(a_Name) \
3305	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
3306	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3307	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3308	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3309	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3310
3311	#else
3312	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3313	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3314	# define FNIEMOP_DEF(a_Name) \
3315	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3316	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3317	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3318	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3319	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3320
3321	#endif
3322	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
3323
3324	/**
3325	* Call an opcode decoder function.
3326	*
3327	* We're using macors for this so that adding and removing parameters can be
3328	* done as we please. See FNIEMOP_DEF.
3329	*/
3330	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
3331
3332	/**
3333	* Call a common opcode decoder function taking one extra argument.
3334	*
3335	* We're using macors for this so that adding and removing parameters can be
3336	* done as we please. See FNIEMOP_DEF_1.
3337	*/
3338	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
3339
3340	/**
3341	* Call a common opcode decoder function taking one extra argument.
3342	*
3343	* We're using macors for this so that adding and removing parameters can be
3344	* done as we please. See FNIEMOP_DEF_1.
3345	*/
3346	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
3347	/** @} */
3348
3349
3350	/** @name Misc Helpers
3351	* @{ */
3352
3353	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
3354	* due to GCC lacking knowledge about the value range of a switch. */
3355	#if RT_CPLUSPLUS_PREREQ(202000)
3356	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3357	#else
3358	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3359	#endif
3360
3361	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
3362	#if RT_CPLUSPLUS_PREREQ(202000)
3363	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
3364	#else
3365	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
3366	#endif
3367
3368	/**
3369	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3370	* occation.
3371	*/
3372	#ifdef LOG_ENABLED
3373	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3374	do { \
3375	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
3376	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3377	} while (0)
3378	#else
3379	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3380	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3381	#endif
3382
3383	/**
3384	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3385	* occation using the supplied logger statement.
3386	*
3387	* @param a_LoggerArgs What to log on failure.
3388	*/
3389	#ifdef LOG_ENABLED
3390	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3391	do { \
3392	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
3393	/LogFunc(a_LoggerArgs);/ \
3394	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3395	} while (0)
3396	#else
3397	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3398	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3399	#endif
3400
3401	/**
3402	* Check if we're currently executing in real or virtual 8086 mode.
3403	*
3404	* @returns @c true if it is, @c false if not.
3405	* @param a_pVCpu The IEM state of the current CPU.
3406	*/
3407	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (CPUMIsGuestInRealOrV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3408
3409	/**
3410	* Check if we're currently executing in virtual 8086 mode.
3411	*
3412	* @returns @c true if it is, @c false if not.
3413	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3414	*/
3415	#define IEM_IS_V86_MODE(a_pVCpu) (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3416
3417	/**
3418	* Check if we're currently executing in long mode.
3419	*
3420	* @returns @c true if it is, @c false if not.
3421	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3422	*/
3423	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
3424
3425	/**
3426	* Check if we're currently executing in a 64-bit code segment.
3427	*
3428	* @returns @c true if it is, @c false if not.
3429	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3430	*/
3431	#define IEM_IS_64BIT_CODE(a_pVCpu) (CPUMIsGuestIn64BitCodeEx(IEM_GET_CTX(a_pVCpu)))
3432
3433	/**
3434	* Check if we're currently executing in real mode.
3435	*
3436	* @returns @c true if it is, @c false if not.
3437	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3438	*/
3439	#define IEM_IS_REAL_MODE(a_pVCpu) (CPUMIsGuestInRealModeEx(IEM_GET_CTX(a_pVCpu)))
3440
3441	/**
3442	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
3443	* @returns PCCPUMFEATURES
3444	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3445	*/
3446	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
3447
3448	/**
3449	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
3450	* @returns PCCPUMFEATURES
3451	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3452	*/
3453	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
3454
3455	/**
3456	* Evaluates to true if we're presenting an Intel CPU to the guest.
3457	*/
3458	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
3459
3460	/**
3461	* Evaluates to true if we're presenting an AMD CPU to the guest.
3462	*/
3463	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
3464
3465	/**
3466	* Check if the address is canonical.
3467	*/
3468	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
3469
3470	/** Checks if the ModR/M byte is in register mode or not. */
3471	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
3472	/** Checks if the ModR/M byte is in memory mode or not. */
3473	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
3474
3475	/**
3476	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
3477	*
3478	* For use during decoding.
3479	*/
3480	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
3481	/**
3482	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
3483	*
3484	* For use during decoding.
3485	*/
3486	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
3487
3488	/**
3489	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
3490	*
3491	* For use during decoding.
3492	*/
3493	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
3494	/**
3495	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
3496	*
3497	* For use during decoding.
3498	*/
3499	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
3500
3501	/**
3502	* Gets the effective VEX.VVVV value.
3503	*
3504	* The 4th bit is ignored if not 64-bit code.
3505	* @returns effective V-register value.
3506	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3507	*/
3508	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
3509	((a_pVCpu)->iem.s.enmCpuMode == IEMMODE_64BIT ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
3510
3511
3512	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3513
3514	/**
3515	* Check if the guest has entered VMX root operation.
3516	*/
3517	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
3518
3519	/**
3520	* Check if the guest has entered VMX non-root operation.
3521	*/
3522	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(a_pVCpu)))
3523
3524	/**
3525	* Check if the nested-guest has the given Pin-based VM-execution control set.
3526	*/
3527	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) \
3528	(CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
3529
3530	/**
3531	* Check if the nested-guest has the given Processor-based VM-execution control set.
3532	*/
3533	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) \
3534	(CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
3535
3536	/**
3537	* Check if the nested-guest has the given Secondary Processor-based VM-execution
3538	* control set.
3539	*/
3540	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) \
3541	(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
3542
3543	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
3544	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
3545
3546	/** Whether a shadow VMCS is present for the given VCPU. */
3547	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3548
3549	/** Gets the VMXON region pointer. */
3550	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
3551
3552	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
3553	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
3554
3555	/** Whether a current VMCS is present for the given VCPU. */
3556	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3557
3558	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
3559	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
3560	do \
3561	{ \
3562	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
3563	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
3564	} while (0)
3565
3566	/** Clears any current VMCS for the given VCPU. */
3567	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
3568	do \
3569	{ \
3570	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
3571	} while (0)
3572
3573	/**
3574	* Invokes the VMX VM-exit handler for an instruction intercept.
3575	*/
3576	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
3577	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
3578
3579	/**
3580	* Invokes the VMX VM-exit handler for an instruction intercept where the
3581	* instruction provides additional VM-exit information.
3582	*/
3583	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
3584	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
3585
3586	/**
3587	* Invokes the VMX VM-exit handler for a task switch.
3588	*/
3589	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
3590	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
3591
3592	/**
3593	* Invokes the VMX VM-exit handler for MWAIT.
3594	*/
3595	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
3596	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
3597
3598	/**
3599	* Invokes the VMX VM-exit handler for EPT faults.
3600	*/
3601	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
3602	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
3603
3604	/**
3605	* Invokes the VMX VM-exit handler.
3606	*/
3607	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
3608	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
3609
3610	#else
3611	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
3612	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
3613	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
3614	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
3615	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
3616	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3617	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3618	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3619	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3620	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3621	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
3622
3623	#endif
3624
3625	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3626	/**
3627	* Check if an SVM control/instruction intercept is set.
3628	*/
3629	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
3630	(CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
3631
3632	/**
3633	* Check if an SVM read CRx intercept is set.
3634	*/
3635	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3636	(CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3637
3638	/**
3639	* Check if an SVM write CRx intercept is set.
3640	*/
3641	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3642	(CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3643
3644	/**
3645	* Check if an SVM read DRx intercept is set.
3646	*/
3647	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3648	(CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3649
3650	/**
3651	* Check if an SVM write DRx intercept is set.
3652	*/
3653	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3654	(CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3655
3656	/**
3657	* Check if an SVM exception intercept is set.
3658	*/
3659	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
3660	(CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
3661
3662	/**
3663	* Invokes the SVM \#VMEXIT handler for the nested-guest.
3664	*/
3665	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3666	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
3667
3668	/**
3669	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
3670	* corresponding decode assist information.
3671	*/
3672	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
3673	do \
3674	{ \
3675	uint64_t uExitInfo1; \
3676	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
3677	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
3678	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
3679	else \
3680	uExitInfo1 = 0; \
3681	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
3682	} while (0)
3683
3684	/** Check and handles SVM nested-guest instruction intercept and updates
3685	* NRIP if needed.
3686	*/
3687	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3688	do \
3689	{ \
3690	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
3691	{ \
3692	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3693	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
3694	} \
3695	} while (0)
3696
3697	/** Checks and handles SVM nested-guest CR0 read intercept. */
3698	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) \
3699	do \
3700	{ \
3701	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
3702	{ /* probably likely */ } \
3703	else \
3704	{ \
3705	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3706	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
3707	} \
3708	} while (0)
3709
3710	/**
3711	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
3712	*/
3713	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) \
3714	do { \
3715	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
3716	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), IEM_GET_INSTR_LEN(a_pVCpu)); \
3717	} while (0)
3718
3719	#else
3720	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
3721	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3722	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3723	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3724	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3725	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
3726	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
3727	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
3728	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3729	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3730	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) do { } while (0)
3731
3732	#endif
3733
3734	/** @} */
3735
3736	void iemInitPendingBreakpointsSlow(PVMCPUCC pVCpu);
3737
3738
3739	/**
3740	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
3741	*/
3742	typedef union IEMSELDESC
3743	{
3744	/** The legacy view. */
3745	X86DESC Legacy;
3746	/** The long mode view. */
3747	X86DESC64 Long;
3748	} IEMSELDESC;
3749	/** Pointer to a selector descriptor table entry. */
3750	typedef IEMSELDESC *PIEMSELDESC;
3751
3752	/** @name Raising Exceptions.
3753	* @{ */
3754	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
3755	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
3756
3757	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
3758	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3759	#ifdef IEM_WITH_SETJMP
3760	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
3761	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
3762	#endif
3763	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
3764	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3765	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
3766	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
3767	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
3768	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3769	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
3770	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3771	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3772	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
3773	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3774	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3775	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3776	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3777	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3778	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3779	#ifdef IEM_WITH_SETJMP
3780	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3781	#endif
3782	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3783	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
3784	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3785	#ifdef IEM_WITH_SETJMP
3786	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
3787	#endif
3788	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3789	#ifdef IEM_WITH_SETJMP
3790	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
3791	#endif
3792	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3793	#ifdef IEM_WITH_SETJMP
3794	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
3795	#endif
3796	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
3797	#ifdef IEM_WITH_SETJMP
3798	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
3799	#endif
3800	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
3801	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3802	#ifdef IEM_WITH_SETJMP
3803	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3804	#endif
3805	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3806
3807	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
3808	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
3809	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
3810
3811	/**
3812	* Macro for calling iemCImplRaiseDivideError().
3813	*
3814	* This enables us to add/remove arguments and force different levels of
3815	* inlining as we wish.
3816	*
3817	* @return Strict VBox status code.
3818	*/
3819	#define IEMOP_RAISE_DIVIDE_ERROR() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseDivideError)
3820
3821	/**
3822	* Macro for calling iemCImplRaiseInvalidLockPrefix().
3823	*
3824	* This enables us to add/remove arguments and force different levels of
3825	* inlining as we wish.
3826	*
3827	* @return Strict VBox status code.
3828	*/
3829	#define IEMOP_RAISE_INVALID_LOCK_PREFIX() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidLockPrefix)
3830
3831	/**
3832	* Macro for calling iemCImplRaiseInvalidOpcode().
3833	*
3834	* This enables us to add/remove arguments and force different levels of
3835	* inlining as we wish.
3836	*
3837	* @return Strict VBox status code.
3838	*/
3839	#define IEMOP_RAISE_INVALID_OPCODE() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidOpcode)
3840	/** @} */
3841
3842	/** @name Register Access.
3843	* @{ */
3844	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
3845	IEMMODE enmEffOpSize) RT_NOEXCEPT;
3846	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
3847	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
3848	IEMMODE enmEffOpSize) RT_NOEXCEPT;
3849	VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
3850	VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
3851	VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
3852	/** @} */
3853
3854	/** @name FPU access and helpers.
3855	* @{ */
3856	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult) RT_NOEXCEPT;
3857	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3858	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult) RT_NOEXCEPT;
3859	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3860	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3861	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3862	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3863	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3864	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3865	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3866	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3867	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3868	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3869	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3870	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3871	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3872	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3873	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3874	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3875	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu) RT_NOEXCEPT;
3876	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3877	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu) RT_NOEXCEPT;
3878	void iemFpuStackPushOverflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3879	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3880	/** @} */
3881
3882	/** @name SSE+AVX SIMD access and helpers.
3883	* @{ */
3884	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
3885	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
3886	/** @} */
3887
3888	/** @name Memory access.
3889	* @{ */
3890
3891	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
3892	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
3893	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
3894	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
3895	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
3896	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
3897	* Users include FXSAVE & FXRSTOR. */
3898	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
3899
3900	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
3901	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
3902	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3903	#ifndef IN_RING3
3904	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3905	#endif
3906	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
3907	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
3908	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3909	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
3910
3911	#ifdef IEM_WITH_CODE_TLB
3912	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
3913	#else
3914	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
3915	#endif
3916	#ifdef IEM_WITH_SETJMP
3917	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3918	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3919	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3920	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3921	#else
3922	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
3923	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3924	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3925	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3926	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3927	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3928	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3929	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3930	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3931	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3932	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3933	#endif
3934
3935	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3936	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3937	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3938	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3939	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3940	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3941	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3942	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3943	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3944	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3945	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3946	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3947	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
3948	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
3949	#ifdef IEM_WITH_SETJMP
3950	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3951	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3952	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3953	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3954	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3955	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3956	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3957	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3958	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3959	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3960	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
3961	#endif
3962
3963	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3964	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3965	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3966	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3967	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
3968
3969	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
3970	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
3971	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
3972	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
3973	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3974	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
3975	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3976	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
3977	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3978	#ifdef IEM_WITH_SETJMP
3979	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
3980	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
3981	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
3982	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
3983	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
3984	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
3985	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
3986	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
3987	#endif
3988
3989	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
3990	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
3991	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
3992	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
3993	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3994	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
3995	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3996	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3997	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
3998	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
3999	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4000	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4001	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
4002	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
4003	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
4004	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
4005	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
4006	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
4007	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4008	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4009	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4010	/** @} */
4011
4012	/** @name IEMAllCImpl.cpp
4013	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
4014	* @{ */
4015	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
4016	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
4017	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
4018	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
4019	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
4020	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
4021	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
4022	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
4023	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
4024	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
4025	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
4026	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
4027	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4028	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4029	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
4030	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
4031	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
4032	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
4033	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
4034	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
4035	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
4036	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
4037	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
4038	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
4039	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
4040	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
4041	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
4042	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
4043	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
4044	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
4045	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
4046	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
4047	IEM_CIMPL_PROTO_0(iemCImpl_sysret);
4048	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
4049	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
4050	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
4051	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
4052	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
4053	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
4054	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
4055	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
4056	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
4057	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4058	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4059	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4060	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4061	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
4062	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4063	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4064	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
4065	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4066	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4067	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
4068	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4069	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4070	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
4071	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
4072	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
4073	IEM_CIMPL_PROTO_0(iemCImpl_clts);
4074	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
4075	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
4076	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
4077	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
4078	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
4079	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
4080	IEM_CIMPL_PROTO_0(iemCImpl_invd);
4081	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
4082	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
4083	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
4084	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
4085	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
4086	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
4087	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
4088	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
4089	IEM_CIMPL_PROTO_1(iemCImpl_in_eAX_DX, uint8_t, cbReg);
4090	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
4091	IEM_CIMPL_PROTO_1(iemCImpl_out_DX_eAX, uint8_t, cbReg);
4092	IEM_CIMPL_PROTO_0(iemCImpl_cli);
4093	IEM_CIMPL_PROTO_0(iemCImpl_sti);
4094	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
4095	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
4096	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
4097	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
4098	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
4099	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
4100	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
4101	IEM_CIMPL_PROTO_0(iemCImpl_daa);
4102	IEM_CIMPL_PROTO_0(iemCImpl_das);
4103	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
4104	IEM_CIMPL_PROTO_0(iemCImpl_aas);
4105	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
4106	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
4107	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
4108	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
4109	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
4110	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
4111	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4112	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
4113	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4114	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4115	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4116	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4117	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4118	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4119	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4120	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4121	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4122	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4123	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4124	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
4125	IEM_CIMPL_PROTO_1(iemCImpl_fxch_underflow, uint8_t, iStReg);
4126	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop);
4127	/** @} */
4128
4129	/** @name IEMAllCImplStrInstr.cpp.h
4130	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
4131	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
4132	* @{ */
4133	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
4134	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
4135	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
4136	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
4137	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
4138	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
4139	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
4140	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
4141	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
4142	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4143	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4144
4145	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
4146	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
4147	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
4148	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
4149	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
4150	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
4151	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
4152	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
4153	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
4154	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4155	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4156
4157	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
4158	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
4159	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
4160	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
4161	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
4162	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
4163	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
4164	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
4165	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
4166	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4167	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4168
4169
4170	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
4171	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
4172	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
4173	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
4174	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
4175	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
4176	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
4177	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
4178	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
4179	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4180	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4181
4182	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
4183	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
4184	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
4185	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
4186	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
4187	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
4188	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
4189	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
4190	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
4191	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4192	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4193
4194	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
4195	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
4196	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
4197	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
4198	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
4199	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
4200	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
4201	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
4202	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
4203	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4204	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4205
4206	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
4207	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
4208	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
4209	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
4210	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
4211	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
4212	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
4213	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
4214	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
4215	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4216	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4217
4218
4219	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
4220	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
4221	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
4222	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
4223	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
4224	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
4225	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
4226	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
4227	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
4228	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4229	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4230
4231	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
4232	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
4233	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
4234	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
4235	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
4236	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
4237	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
4238	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
4239	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
4240	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4241	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4242
4243	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
4244	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
4245	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
4246	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
4247	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
4248	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
4249	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
4250	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
4251	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
4252	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4253	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4254
4255	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
4256	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
4257	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
4258	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
4259	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
4260	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
4261	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
4262	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
4263	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
4264	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4265	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4266	/** @} */
4267
4268	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4269	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
4270	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
4271	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
4272	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
4273	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
4274	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4275	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
4276	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
4277	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
4278	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
4279	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
4280	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
4281	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
4282	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4283	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4284	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4285	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4286	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4287	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4288	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
4289	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
4290	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
4291	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
4292	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
4293	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
4294	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
4295	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
4296	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
4297	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
4298	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
4299	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
4300	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
4301	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
4302	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
4303	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4304	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4305	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4306	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
4307	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
4308	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
4309	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint32_t *, pu32Dst, uint32_t, u32VmcsField);
4310	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
4311	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
4312	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
4313	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
4314	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
4315	#endif
4316
4317	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4318	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
4319	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4320	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
4321	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
4322	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite) RT_NOEXCEPT;
4323	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
4324	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
4325	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
4326	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
4327	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
4328	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
4329	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
4330	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
4331	#endif
4332
4333	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
4334	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
4335	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
4336
4337
4338	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
4339
4340	/** @} */
4341
4342	RT_C_DECLS_END
4343
4344	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
4345

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source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 98795

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