IEMInternal.h@ 99813

Last change on this file since 99813 was 99690, checked in by vboxsync, 20 months ago
VMM/IEM: scm fix. bugref:10369
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 225.5 KB

Line
1	/* $Id: IEMInternal.h 99690 2023-05-09 08:34:36Z vboxsync $ */
2	/** @file
3	* IEM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMInternal_h
29	#define VMM_INCLUDED_SRC_include_IEMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/iem.h>
36	#include <VBox/vmm/pgm.h>
37	#include <VBox/vmm/stam.h>
38	#include <VBox/param.h>
39
40	#include <iprt/setjmp-without-sigmask.h>
41
42
43	RT_C_DECLS_BEGIN
44
45
46	/** @defgroup grp_iem_int Internals
47	* @ingroup grp_iem
48	* @internal
49	* @{
50	*/
51
52	/** For expanding symbol in slickedit and other products tagging and
53	* crossreferencing IEM symbols. */
54	#ifndef IEM_STATIC
55	# define IEM_STATIC static
56	#endif
57
58	/** @def IEM_WITH_SETJMP
59	* Enables alternative status code handling using setjmps.
60	*
61	* This adds a bit of expense via the setjmp() call since it saves all the
62	* non-volatile registers. However, it eliminates return code checks and allows
63	* for more optimal return value passing (return regs instead of stack buffer).
64	*/
65	#if defined(DOXYGEN_RUNNING) \|\| defined(RT_OS_WINDOWS) \|\| 1
66	# define IEM_WITH_SETJMP
67	#endif
68
69	/** @def IEM_WITH_THROW_CATCH
70	* Enables using C++ throw/catch as an alternative to setjmp/longjmp in user
71	* mode code when IEM_WITH_SETJMP is in effect.
72	*
73	* With GCC 11.3.1 and code TLB on linux, using throw/catch instead of
74	* setjmp/long resulted in bs2-test-1 running 3.00% faster and all but on test
75	* result value improving by more than 1%. (Best out of three.)
76	*
77	* With Visual C++ 2019 and code TLB on windows, using throw/catch instead of
78	* setjmp/long resulted in bs2-test-1 running 3.68% faster and all but some of
79	* the MMIO and CPUID tests ran noticeably faster. Variation is greater than on
80	* Linux, but it should be quite a bit faster for normal code.
81	*/
82	#if (defined(IEM_WITH_SETJMP) && defined(IN_RING3) && (defined(__GNUC__) \|\| defined(_MSC_VER))) \
83	\|\| defined(DOXYGEN_RUNNING)
84	# define IEM_WITH_THROW_CATCH
85	#endif
86
87	/** @def IEM_DO_LONGJMP
88	*
89	* Wrapper around longjmp / throw.
90	*
91	* @param a_pVCpu The CPU handle.
92	* @param a_rc The status code jump back with / throw.
93	*/
94	#if defined(IEM_WITH_SETJMP) \|\| defined(DOXYGEN_RUNNING)
95	# ifdef IEM_WITH_THROW_CATCH
96	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) throw int(a_rc)
97	# else
98	# define IEM_DO_LONGJMP(a_pVCpu, a_rc) longjmp(*(a_pVCpu)->iem.s.CTX_SUFF(pJmpBuf), (a_rc))
99	# endif
100	#endif
101
102	/** For use with IEM function that may do a longjmp (when enabled).
103	*
104	* Visual C++ has trouble longjmp'ing from/over functions with the noexcept
105	* attribute. So, we indicate that function that may be part of a longjmp may
106	* throw "exceptions" and that the compiler should definitely not generate and
107	* std::terminate calling unwind code.
108	*
109	* Here is one example of this ending in std::terminate:
110	* @code{.txt}
111	00 00000041`cadfda10 00007ffc`5d5a1f9f ucrtbase!abort+0x4e
112	01 00000041`cadfda40 00007ffc`57af229a ucrtbase!terminate+0x1f
113	02 00000041`cadfda70 00007ffb`eec91030 VCRUNTIME140!__std_terminate+0xa [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\ehhelpers.cpp @ 192]
114	03 00000041`cadfdaa0 00007ffb`eec92c6d VCRUNTIME140_1!_CallSettingFrame+0x20 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\handlers.asm @ 50]
115	04 00000041`cadfdad0 00007ffb`eec93ae5 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToState+0x241 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 1085]
116	05 00000041`cadfdc00 00007ffb`eec92258 VCRUNTIME140_1!__FrameHandler4::FrameUnwindToEmptyState+0x2d [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 218]
117	06 00000041`cadfdc30 00007ffb`eec940e9 VCRUNTIME140_1!__InternalCxxFrameHandler<__FrameHandler4>+0x194 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\frame.cpp @ 304]
118	07 00000041`cadfdcd0 00007ffc`5f9f249f VCRUNTIME140_1!__CxxFrameHandler4+0xa9 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\risctrnsctrl.cpp @ 290]
119	08 00000041`cadfdd40 00007ffc`5f980939 ntdll!RtlpExecuteHandlerForUnwind+0xf
120	09 00000041`cadfdd70 00007ffc`5f9a0edd ntdll!RtlUnwindEx+0x339
121	0a 00000041`cadfe490 00007ffc`57aff976 ntdll!RtlUnwind+0xcd
122	0b 00000041`cadfea00 00007ffb`e1b5de01 VCRUNTIME140!__longjmp_internal+0xe6 [d:\agent\_work\1\s\src\vctools\crt\vcruntime\src\eh\amd64\longjmp.asm @ 140]
123	0c (Inline Function) --------`-------- VBoxVMM!iemOpcodeGetNextU8SlowJmp+0x95 [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 1155]
124	0d 00000041`cadfea50 00007ffb`e1b60f6b VBoxVMM!iemOpcodeGetNextU8Jmp+0xc1 [L:\vbox-intern\src\VBox\VMM\include\IEMInline.h @ 402]
125	0e 00000041`cadfea90 00007ffb`e1cc6201 VBoxVMM!IEMExecForExits+0xdb [L:\vbox-intern\src\VBox\VMM\VMMAll\IEMAll.cpp @ 10185]
126	0f 00000041`cadfec70 00007ffb`e1d0df8d VBoxVMM!EMHistoryExec+0x4f1 [L:\vbox-intern\src\VBox\VMM\VMMAll\EMAll.cpp @ 452]
127	10 00000041`cadfed60 00007ffb`e1d0d4c0 VBoxVMM!nemR3WinHandleExitCpuId+0x79d [L:\vbox-intern\src\VBox\VMM\VMMAll\NEMAllNativeTemplate-win.cpp.h @ 1829] @encode
128	@endcode
129	*
130	* @see https://developercommunity.visualstudio.com/t/fragile-behavior-of-longjmp-called-from-noexcept-f/1532859
131	*/
132	#if defined(IEM_WITH_SETJMP) && (defined(_MSC_VER) \|\| defined(IEM_WITH_THROW_CATCH))
133	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT_EX(false)
134	#else
135	# define IEM_NOEXCEPT_MAY_LONGJMP RT_NOEXCEPT
136	#endif
137
138	#define IEM_IMPLEMENTS_TASKSWITCH
139
140	/** @def IEM_WITH_3DNOW
141	* Includes the 3DNow decoding. */
142	#if (!defined(IEM_WITH_3DNOW) && !defined(IEM_WITHOUT_3DNOW)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
143	# define IEM_WITH_3DNOW
144	#endif
145
146	/** @def IEM_WITH_THREE_0F_38
147	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
148	#if (!defined(IEM_WITH_THREE_0F_38) && !defined(IEM_WITHOUT_THREE_0F_38)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
149	# define IEM_WITH_THREE_0F_38
150	#endif
151
152	/** @def IEM_WITH_THREE_0F_3A
153	* Includes the three byte opcode map for instrs starting with 0x0f 0x38. */
154	#if (!defined(IEM_WITH_THREE_0F_3A) && !defined(IEM_WITHOUT_THREE_0F_3A)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
155	# define IEM_WITH_THREE_0F_3A
156	#endif
157
158	/** @def IEM_WITH_VEX
159	* Includes the VEX decoding. */
160	#if (!defined(IEM_WITH_VEX) && !defined(IEM_WITHOUT_VEX)) \|\| defined(DOXYGEN_RUNNING) /* For doxygen, set in Config.kmk. */
161	# define IEM_WITH_VEX
162	#endif
163
164	/** @def IEM_CFG_TARGET_CPU
165	* The minimum target CPU for the IEM emulation (IEMTARGETCPU_XXX value).
166	*
167	* By default we allow this to be configured by the user via the
168	* CPUM/GuestCpuName config string, but this comes at a slight cost during
169	* decoding. So, for applications of this code where there is no need to
170	* be dynamic wrt target CPU, just modify this define.
171	*/
172	#if !defined(IEM_CFG_TARGET_CPU) \|\| defined(DOXYGEN_RUNNING)
173	# define IEM_CFG_TARGET_CPU IEMTARGETCPU_DYNAMIC
174	#endif
175
176	//#define IEM_WITH_CODE_TLB // - work in progress
177	//#define IEM_WITH_DATA_TLB // - work in progress
178
179
180	/** @def IEM_USE_UNALIGNED_DATA_ACCESS
181	* Use unaligned accesses instead of elaborate byte assembly. */
182	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86) \|\| defined(DOXYGEN_RUNNING)
183	# define IEM_USE_UNALIGNED_DATA_ACCESS
184	#endif
185
186	//#define IEM_LOG_MEMORY_WRITES
187
188	#if !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
189	/** Instruction statistics. */
190	typedef struct IEMINSTRSTATS
191	{
192	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) uint32_t a_Name;
193	# include "IEMInstructionStatisticsTmpl.h"
194	# undef IEM_DO_INSTR_STAT
195	} IEMINSTRSTATS;
196	#else
197	struct IEMINSTRSTATS;
198	typedef struct IEMINSTRSTATS IEMINSTRSTATS;
199	#endif
200	/** Pointer to IEM instruction statistics. */
201	typedef IEMINSTRSTATS *PIEMINSTRSTATS;
202
203
204	/** @name IEMTARGETCPU_EFL_BEHAVIOR_XXX - IEMCPU::aidxTargetCpuEflFlavour
205	* @{ */
206	#define IEMTARGETCPU_EFL_BEHAVIOR_NATIVE 0 /*< Native x86 EFLAGS result; Intel EFLAGS when on non-x86 hosts. /
207	#define IEMTARGETCPU_EFL_BEHAVIOR_INTEL 1 /*< Intel EFLAGS result. /
208	#define IEMTARGETCPU_EFL_BEHAVIOR_AMD 2 /*< AMD EFLAGS result /
209	#define IEMTARGETCPU_EFL_BEHAVIOR_RESERVED 3 /*< Reserved/dummy entry slot that's the same as 0. /
210	#define IEMTARGETCPU_EFL_BEHAVIOR_MASK 3 /*< For masking the index before use. /
211	/** Selects the right variant from a_aArray.
212	* pVCpu is implicit in the caller context. */
213	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT(a_aArray) \
214	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[1] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
215	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for when no native worker can
216	* be used because the host CPU does not support the operation. */
217	#define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_NON_NATIVE(a_aArray) \
218	(a_aArray[pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
219	/** Variation of IEMTARGETCPU_EFL_BEHAVIOR_SELECT for a two dimentional
220	* array paralleling IEMCPU::aidxTargetCpuEflFlavour and a single bit index
221	* into the two.
222	* @sa IEM_SELECT_NATIVE_OR_FALLBACK */
223	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
224	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
225	(a_aaArray[a_fNative][pVCpu->iem.s.aidxTargetCpuEflFlavour[a_fNative] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
226	#else
227	# define IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(a_aaArray, a_fNative) \
228	(a_aaArray[0][pVCpu->iem.s.aidxTargetCpuEflFlavour[0] & IEMTARGETCPU_EFL_BEHAVIOR_MASK])
229	#endif
230	/** @} */
231
232	/**
233	* Picks @a a_pfnNative or @a a_pfnFallback according to the host CPU feature
234	* indicator given by @a a_fCpumFeatureMember (CPUMFEATURES member).
235	*
236	* On non-x86 hosts, this will shortcut to the fallback w/o checking the
237	* indicator.
238	*
239	* @sa IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX
240	*/
241	#if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
242	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) \
243	(g_CpumHostFeatures.s.a_fCpumFeatureMember ? a_pfnNative : a_pfnFallback)
244	#else
245	# define IEM_SELECT_HOST_OR_FALLBACK(a_fCpumFeatureMember, a_pfnNative, a_pfnFallback) (a_pfnFallback)
246	#endif
247
248
249	/**
250	* Extended operand mode that includes a representation of 8-bit.
251	*
252	* This is used for packing down modes when invoking some C instruction
253	* implementations.
254	*/
255	typedef enum IEMMODEX
256	{
257	IEMMODEX_16BIT = IEMMODE_16BIT,
258	IEMMODEX_32BIT = IEMMODE_32BIT,
259	IEMMODEX_64BIT = IEMMODE_64BIT,
260	IEMMODEX_8BIT
261	} IEMMODEX;
262	AssertCompileSize(IEMMODEX, 4);
263
264
265	/**
266	* Branch types.
267	*/
268	typedef enum IEMBRANCH
269	{
270	IEMBRANCH_JUMP = 1,
271	IEMBRANCH_CALL,
272	IEMBRANCH_TRAP,
273	IEMBRANCH_SOFTWARE_INT,
274	IEMBRANCH_HARDWARE_INT
275	} IEMBRANCH;
276	AssertCompileSize(IEMBRANCH, 4);
277
278
279	/**
280	* INT instruction types.
281	*/
282	typedef enum IEMINT
283	{
284	/** INT n instruction (opcode 0xcd imm). */
285	IEMINT_INTN = 0,
286	/** Single byte INT3 instruction (opcode 0xcc). */
287	IEMINT_INT3 = IEM_XCPT_FLAGS_BP_INSTR,
288	/** Single byte INTO instruction (opcode 0xce). */
289	IEMINT_INTO = IEM_XCPT_FLAGS_OF_INSTR,
290	/** Single byte INT1 (ICEBP) instruction (opcode 0xf1). */
291	IEMINT_INT1 = IEM_XCPT_FLAGS_ICEBP_INSTR
292	} IEMINT;
293	AssertCompileSize(IEMINT, 4);
294
295
296	/**
297	* A FPU result.
298	*/
299	typedef struct IEMFPURESULT
300	{
301	/** The output value. */
302	RTFLOAT80U r80Result;
303	/** The output status. */
304	uint16_t FSW;
305	} IEMFPURESULT;
306	AssertCompileMemberOffset(IEMFPURESULT, FSW, 10);
307	/** Pointer to a FPU result. */
308	typedef IEMFPURESULT *PIEMFPURESULT;
309	/** Pointer to a const FPU result. */
310	typedef IEMFPURESULT const *PCIEMFPURESULT;
311
312
313	/**
314	* A FPU result consisting of two output values and FSW.
315	*/
316	typedef struct IEMFPURESULTTWO
317	{
318	/** The first output value. */
319	RTFLOAT80U r80Result1;
320	/** The output status. */
321	uint16_t FSW;
322	/** The second output value. */
323	RTFLOAT80U r80Result2;
324	} IEMFPURESULTTWO;
325	AssertCompileMemberOffset(IEMFPURESULTTWO, FSW, 10);
326	AssertCompileMemberOffset(IEMFPURESULTTWO, r80Result2, 12);
327	/** Pointer to a FPU result consisting of two output values and FSW. */
328	typedef IEMFPURESULTTWO *PIEMFPURESULTTWO;
329	/** Pointer to a const FPU result consisting of two output values and FSW. */
330	typedef IEMFPURESULTTWO const *PCIEMFPURESULTTWO;
331
332
333	/**
334	* IEM TLB entry.
335	*
336	* Lookup assembly:
337	* @code{.asm}
338	; Calculate tag.
339	mov rax, [VA]
340	shl rax, 16
341	shr rax, 16 + X86_PAGE_SHIFT
342	or rax, [uTlbRevision]
343
344	; Do indexing.
345	movzx ecx, al
346	lea rcx, [pTlbEntries + rcx]
347
348	; Check tag.
349	cmp [rcx + IEMTLBENTRY.uTag], rax
350	jne .TlbMiss
351
352	; Check access.
353	mov rax, ACCESS_FLAGS \| MAPPING_R3_NOT_VALID \| 0xffffff00
354	and rax, [rcx + IEMTLBENTRY.fFlagsAndPhysRev]
355	cmp rax, [uTlbPhysRev]
356	jne .TlbMiss
357
358	; Calc address and we're done.
359	mov eax, X86_PAGE_OFFSET_MASK
360	and eax, [VA]
361	or rax, [rcx + IEMTLBENTRY.pMappingR3]
362	%ifdef VBOX_WITH_STATISTICS
363	inc qword [cTlbHits]
364	%endif
365	jmp .Done
366
367	.TlbMiss:
368	mov r8d, ACCESS_FLAGS
369	mov rdx, [VA]
370	mov rcx, [pVCpu]
371	call iemTlbTypeMiss
372	.Done:
373
374	@endcode
375	*
376	*/
377	typedef struct IEMTLBENTRY
378	{
379	/** The TLB entry tag.
380	* Bits 35 thru 0 are made up of the virtual address shifted right 12 bits, this
381	* is ASSUMING a virtual address width of 48 bits.
382	*
383	* Bits 63 thru 36 are made up of the TLB revision (zero means invalid).
384	*
385	* The TLB lookup code uses the current TLB revision, which won't ever be zero,
386	* enabling an extremely cheap TLB invalidation most of the time. When the TLB
387	* revision wraps around though, the tags needs to be zeroed.
388	*
389	* @note Try use SHRD instruction? After seeing
390	* https://gmplib.org/~tege/x86-timing.pdf, maybe not.
391	*
392	* @todo This will need to be reorganized for 57-bit wide virtual address and
393	* PCID (currently 12 bits) and ASID (currently 6 bits) support. We'll
394	* have to move the TLB entry versioning entirely to the
395	* fFlagsAndPhysRev member then, 57 bit wide VAs means we'll only have
396	* 19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
397	* consumed by PCID and ASID (12 + 6 = 18).
398	*/
399	uint64_t uTag;
400	/** Access flags and physical TLB revision.
401	*
402	* - Bit 0 - page tables - not executable (X86_PTE_PAE_NX).
403	* - Bit 1 - page tables - not writable (complemented X86_PTE_RW).
404	* - Bit 2 - page tables - not user (complemented X86_PTE_US).
405	* - Bit 3 - pgm phys/virt - not directly writable.
406	* - Bit 4 - pgm phys page - not directly readable.
407	* - Bit 5 - page tables - not accessed (complemented X86_PTE_A).
408	* - Bit 6 - page tables - not dirty (complemented X86_PTE_D).
409	* - Bit 7 - tlb entry - pMappingR3 member not valid.
410	* - Bits 63 thru 8 are used for the physical TLB revision number.
411	*
412	* We're using complemented bit meanings here because it makes it easy to check
413	* whether special action is required. For instance a user mode write access
414	* would do a "TEST fFlags, (X86_PTE_RW \| X86_PTE_US \| X86_PTE_D)" and a
415	* non-zero result would mean special handling needed because either it wasn't
416	* writable, or it wasn't user, or the page wasn't dirty. A user mode read
417	* access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
418	* need to check any PTE flag.
419	*/
420	uint64_t fFlagsAndPhysRev;
421	/** The guest physical page address. */
422	uint64_t GCPhys;
423	/** Pointer to the ring-3 mapping. */
424	R3PTRTYPE(uint8_t *) pbMappingR3;
425	#if HC_ARCH_BITS == 32
426	uint32_t u32Padding1;
427	#endif
428	} IEMTLBENTRY;
429	AssertCompileSize(IEMTLBENTRY, 32);
430	/** Pointer to an IEM TLB entry. */
431	typedef IEMTLBENTRY *PIEMTLBENTRY;
432
433	/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
434	* @{ */
435	#define IEMTLBE_F_PT_NO_EXEC RT_BIT_64(0) /*< Page tables: Not executable. /
436	#define IEMTLBE_F_PT_NO_WRITE RT_BIT_64(1) /*< Page tables: Not writable. /
437	#define IEMTLBE_F_PT_NO_USER RT_BIT_64(2) /*< Page tables: Not user accessible (supervisor only). /
438	#define IEMTLBE_F_PG_NO_WRITE RT_BIT_64(3) /*< Phys page: Not writable (access handler, ROM, whatever). /
439	#define IEMTLBE_F_PG_NO_READ RT_BIT_64(4) /*< Phys page: Not readable (MMIO / access handler, ROM) /
440	#define IEMTLBE_F_PT_NO_ACCESSED RT_BIT_64(5) /*< Phys tables: Not accessed (need to be marked accessed). /
441	#define IEMTLBE_F_PT_NO_DIRTY RT_BIT_64(6) /*< Page tables: Not dirty (needs to be made dirty on write). /
442	#define IEMTLBE_F_NO_MAPPINGR3 RT_BIT_64(7) /*< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. /
443	#define IEMTLBE_F_PG_UNASSIGNED RT_BIT_64(8) /*< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). /
444	#define IEMTLBE_F_PHYS_REV UINT64_C(0xfffffffffffffe00) /*< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR /
445	/** @} */
446
447
448	/**
449	* An IEM TLB.
450	*
451	* We've got two of these, one for data and one for instructions.
452	*/
453	typedef struct IEMTLB
454	{
455	/** The TLB entries.
456	* We've choosen 256 because that way we can obtain the result directly from a
457	* 8-bit register without an additional AND instruction. */
458	IEMTLBENTRY aEntries[256];
459	/** The TLB revision.
460	* This is actually only 28 bits wide (see IEMTLBENTRY::uTag) and is incremented
461	* by adding RT_BIT_64(36) to it. When it wraps around and becomes zero, all
462	* the tags in the TLB must be zeroed and the revision set to RT_BIT_64(36).
463	* (The revision zero indicates an invalid TLB entry.)
464	*
465	* The initial value is choosen to cause an early wraparound. */
466	uint64_t uTlbRevision;
467	/** The TLB physical address revision - shadow of PGM variable.
468	*
469	* This is actually only 56 bits wide (see IEMTLBENTRY::fFlagsAndPhysRev) and is
470	* incremented by adding RT_BIT_64(8). When it wraps around and becomes zero,
471	* a rendezvous is called and each CPU wipe the IEMTLBENTRY::pMappingR3 as well
472	* as IEMTLBENTRY::fFlagsAndPhysRev bits 63 thru 8, 4, and 3.
473	*
474	* The initial value is choosen to cause an early wraparound. */
475	uint64_t volatile uTlbPhysRev;
476
477	/* Statistics: */
478
479	/** TLB hits (VBOX_WITH_STATISTICS only). */
480	uint64_t cTlbHits;
481	/** TLB misses. */
482	uint32_t cTlbMisses;
483	/** Slow read path. */
484	uint32_t cTlbSlowReadPath;
485	#if 0
486	/** TLB misses because of tag mismatch. */
487	uint32_t cTlbMissesTag;
488	/** TLB misses because of virtual access violation. */
489	uint32_t cTlbMissesVirtAccess;
490	/** TLB misses because of dirty bit. */
491	uint32_t cTlbMissesDirty;
492	/** TLB misses because of MMIO */
493	uint32_t cTlbMissesMmio;
494	/** TLB misses because of write access handlers. */
495	uint32_t cTlbMissesWriteHandler;
496	/** TLB misses because no r3(/r0) mapping. */
497	uint32_t cTlbMissesMapping;
498	#endif
499	/** Alignment padding. */
500	uint32_t au32Padding[3+5];
501	} IEMTLB;
502	AssertCompileSizeAlignment(IEMTLB, 64);
503	/** IEMTLB::uTlbRevision increment. */
504	#define IEMTLB_REVISION_INCR RT_BIT_64(36)
505	/** IEMTLB::uTlbRevision mask. */
506	#define IEMTLB_REVISION_MASK (~(RT_BIT_64(36) - 1))
507	/** IEMTLB::uTlbPhysRev increment.
508	* @sa IEMTLBE_F_PHYS_REV */
509	#define IEMTLB_PHYS_REV_INCR RT_BIT_64(9)
510	/**
511	* Calculates the TLB tag for a virtual address.
512	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
513	* @param a_pTlb The TLB.
514	* @param a_GCPtr The virtual address.
515	*/
516	#define IEMTLB_CALC_TAG(a_pTlb, a_GCPtr) ( IEMTLB_CALC_TAG_NO_REV(a_GCPtr) \| (a_pTlb)->uTlbRevision )
517	/**
518	* Calculates the TLB tag for a virtual address but without TLB revision.
519	* @returns Tag value for indexing and comparing with IEMTLB::uTag.
520	* @param a_GCPtr The virtual address.
521	*/
522	#define IEMTLB_CALC_TAG_NO_REV(a_GCPtr) ( (((a_GCPtr) << 16) >> (GUEST_PAGE_SHIFT + 16)) )
523	/**
524	* Converts a TLB tag value into a TLB index.
525	* @returns Index into IEMTLB::aEntries.
526	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
527	*/
528	#define IEMTLB_TAG_TO_INDEX(a_uTag) ( (uint8_t)(a_uTag) )
529	/**
530	* Converts a TLB tag value into a TLB index.
531	* @returns Index into IEMTLB::aEntries.
532	* @param a_pTlb The TLB.
533	* @param a_uTag Value returned by IEMTLB_CALC_TAG.
534	*/
535	#define IEMTLB_TAG_TO_ENTRY(a_pTlb, a_uTag) ( &(a_pTlb)->aEntries[IEMTLB_TAG_TO_INDEX(a_uTag)] )
536
537
538	/**
539	* The per-CPU IEM state.
540	*/
541	typedef struct IEMCPU
542	{
543	/** Info status code that needs to be propagated to the IEM caller.
544	* This cannot be passed internally, as it would complicate all success
545	* checks within the interpreter making the code larger and almost impossible
546	* to get right. Instead, we'll store status codes to pass on here. Each
547	* source of these codes will perform appropriate sanity checks. */
548	int32_t rcPassUp; /* 0x00 */
549
550	/** The current CPU execution mode (CS). */
551	IEMMODE enmCpuMode; /* 0x04 */
552	/** The CPL. */
553	uint8_t uCpl; /* 0x05 */
554
555	/** Whether to bypass access handlers or not. */
556	bool fBypassHandlers : 1; /* 0x06.0 */
557	/** Whether to disregard the lock prefix (implied or not). */
558	bool fDisregardLock : 1; /* 0x06.1 */
559	/** Whether there are pending hardware instruction breakpoints. */
560	bool fPendingInstructionBreakpoints : 1; /* 0x06.2 */
561	/** Whether there are pending hardware data breakpoints. */
562	bool fPendingDataBreakpoints : 1; /* 0x06.3 */
563	/** Whether there are pending hardware I/O breakpoints. */
564	bool fPendingIoBreakpoints : 1; /* 0x06.4 */
565
566	/* Unused/padding */
567	bool fUnused; /* 0x07 */
568
569	/** @name Decoder state.
570	* @{ */
571	#ifndef IEM_WITH_OPAQUE_DECODER_STATE
572	# ifdef IEM_WITH_CODE_TLB
573	/** The offset of the next instruction byte. */
574	uint32_t offInstrNextByte; /* 0x08 */
575	/** The number of bytes available at pbInstrBuf for the current instruction.
576	* This takes the max opcode length into account so that doesn't need to be
577	* checked separately. */
578	uint32_t cbInstrBuf; /* 0x0c */
579	/** Pointer to the page containing RIP, user specified buffer or abOpcode.
580	* This can be NULL if the page isn't mappable for some reason, in which
581	* case we'll do fallback stuff.
582	*
583	* If we're executing an instruction from a user specified buffer,
584	* IEMExecOneWithPrefetchedByPC and friends, this is not necessarily a page
585	* aligned pointer but pointer to the user data.
586	*
587	* For instructions crossing pages, this will start on the first page and be
588	* advanced to the next page by the time we've decoded the instruction. This
589	* therefore precludes stuff like <tt>pbInstrBuf[offInstrNextByte + cbInstrBuf - cbCurInstr]</tt>
590	*/
591	uint8_t const pbInstrBuf; / 0x10 */
592	# if ARCH_BITS == 32
593	uint32_t uInstrBufHigh; /** The high dword of the host context pbInstrBuf member. */
594	# endif
595	/** The program counter corresponding to pbInstrBuf.
596	* This is set to a non-canonical address when we need to invalidate it. */
597	uint64_t uInstrBufPc; /* 0x18 */
598	/** The number of bytes available at pbInstrBuf in total (for IEMExecLots).
599	* This takes the CS segment limit into account. */
600	uint16_t cbInstrBufTotal; /* 0x20 */
601	/** Offset into pbInstrBuf of the first byte of the current instruction.
602	* Can be negative to efficiently handle cross page instructions. */
603	int16_t offCurInstrStart; /* 0x22 */
604
605	/** The prefix mask (IEM_OP_PRF_XXX). */
606	uint32_t fPrefixes; /* 0x24 */
607	/** The extra REX ModR/M register field bit (REX.R << 3). */
608	uint8_t uRexReg; /* 0x28 */
609	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
610	* (REX.B << 3). */
611	uint8_t uRexB; /* 0x29 */
612	/** The extra REX SIB index field bit (REX.X << 3). */
613	uint8_t uRexIndex; /* 0x2a */
614
615	/** The effective segment register (X86_SREG_XXX). */
616	uint8_t iEffSeg; /* 0x2b */
617
618	/** The offset of the ModR/M byte relative to the start of the instruction. */
619	uint8_t offModRm; /* 0x2c */
620	# else /* !IEM_WITH_CODE_TLB */
621	/** The size of what has currently been fetched into abOpcode. */
622	uint8_t cbOpcode; /* 0x08 */
623	/** The current offset into abOpcode. */
624	uint8_t offOpcode; /* 0x09 */
625	/** The offset of the ModR/M byte relative to the start of the instruction. */
626	uint8_t offModRm; /* 0x0a */
627
628	/** The effective segment register (X86_SREG_XXX). */
629	uint8_t iEffSeg; /* 0x0b */
630
631	/** The prefix mask (IEM_OP_PRF_XXX). */
632	uint32_t fPrefixes; /* 0x0c */
633	/** The extra REX ModR/M register field bit (REX.R << 3). */
634	uint8_t uRexReg; /* 0x10 */
635	/** The extra REX ModR/M r/m field, SIB base and opcode reg bit
636	* (REX.B << 3). */
637	uint8_t uRexB; /* 0x11 */
638	/** The extra REX SIB index field bit (REX.X << 3). */
639	uint8_t uRexIndex; /* 0x12 */
640
641	# endif /* !IEM_WITH_CODE_TLB */
642
643	/** The effective operand mode. */
644	IEMMODE enmEffOpSize; /* 0x2d, 0x13 */
645	/** The default addressing mode. */
646	IEMMODE enmDefAddrMode; /* 0x2e, 0x14 */
647	/** The effective addressing mode. */
648	IEMMODE enmEffAddrMode; /* 0x2f, 0x15 */
649	/** The default operand mode. */
650	IEMMODE enmDefOpSize; /* 0x30, 0x16 */
651
652	/** Prefix index (VEX.pp) for two byte and three byte tables. */
653	uint8_t idxPrefix; /* 0x31, 0x17 */
654	/** 3rd VEX/EVEX/XOP register.
655	* Please use IEM_GET_EFFECTIVE_VVVV to access. */
656	uint8_t uVex3rdReg; /* 0x32, 0x18 */
657	/** The VEX/EVEX/XOP length field. */
658	uint8_t uVexLength; /* 0x33, 0x19 */
659	/** Additional EVEX stuff. */
660	uint8_t fEvexStuff; /* 0x34, 0x1a */
661
662	/** Explicit alignment padding. */
663	uint8_t abAlignment2a[1]; /* 0x35, 0x1b */
664	/** The FPU opcode (FOP). */
665	uint16_t uFpuOpcode; /* 0x36, 0x1c */
666	# ifndef IEM_WITH_CODE_TLB
667	/** Explicit alignment padding. */
668	uint8_t abAlignment2b[2]; /* 0x1e */
669	# endif
670
671	/** The opcode bytes. */
672	uint8_t abOpcode[15]; /* 0x48, 0x20 */
673	/** Explicit alignment padding. */
674	# ifdef IEM_WITH_CODE_TLB
675	uint8_t abAlignment2c[0x48 - 0x47]; /* 0x37 */
676	# else
677	uint8_t abAlignment2c[0x48 - 0x2f]; /* 0x2f */
678	# endif
679	#else /* IEM_WITH_OPAQUE_DECODER_STATE */
680	uint8_t abOpaqueDecoder[0x48 - 0x8];
681	#endif /* IEM_WITH_OPAQUE_DECODER_STATE */
682	/** @} */
683
684
685	/** The flags of the current exception / interrupt. */
686	uint32_t fCurXcpt; /* 0x48, 0x48 */
687	/** The current exception / interrupt. */
688	uint8_t uCurXcpt;
689	/** Exception / interrupt recursion depth. */
690	int8_t cXcptRecursions;
691
692	/** The number of active guest memory mappings. */
693	uint8_t cActiveMappings;
694	/** The next unused mapping index. */
695	uint8_t iNextMapping;
696	/** Records for tracking guest memory mappings. */
697	struct
698	{
699	/** The address of the mapped bytes. */
700	void *pv;
701	/** The access flags (IEM_ACCESS_XXX).
702	* IEM_ACCESS_INVALID if the entry is unused. */
703	uint32_t fAccess;
704	#if HC_ARCH_BITS == 64
705	uint32_t u32Alignment4; /*< Alignment padding. /
706	#endif
707	} aMemMappings[3];
708
709	/** Locking records for the mapped memory. */
710	union
711	{
712	PGMPAGEMAPLOCK Lock;
713	uint64_t au64Padding[2];
714	} aMemMappingLocks[3];
715
716	/** Bounce buffer info.
717	* This runs in parallel to aMemMappings. */
718	struct
719	{
720	/** The physical address of the first byte. */
721	RTGCPHYS GCPhysFirst;
722	/** The physical address of the second page. */
723	RTGCPHYS GCPhysSecond;
724	/** The number of bytes in the first page. */
725	uint16_t cbFirst;
726	/** The number of bytes in the second page. */
727	uint16_t cbSecond;
728	/** Whether it's unassigned memory. */
729	bool fUnassigned;
730	/** Explicit alignment padding. */
731	bool afAlignment5[3];
732	} aMemBbMappings[3];
733
734	/* Ensure that aBounceBuffers are aligned at a 32 byte boundrary. */
735	uint64_t abAlignment7[1];
736
737	/** Bounce buffer storage.
738	* This runs in parallel to aMemMappings and aMemBbMappings. */
739	struct
740	{
741	uint8_t ab[512];
742	} aBounceBuffers[3];
743
744
745	/** Pointer set jump buffer - ring-3 context. */
746	R3PTRTYPE(jmp_buf *) pJmpBufR3;
747	/** Pointer set jump buffer - ring-0 context. */
748	R0PTRTYPE(jmp_buf *) pJmpBufR0;
749
750	/** @todo Should move this near @a fCurXcpt later. */
751	/** The CR2 for the current exception / interrupt. */
752	uint64_t uCurXcptCr2;
753	/** The error code for the current exception / interrupt. */
754	uint32_t uCurXcptErr;
755
756	/** @name Statistics
757	* @{ */
758	/** The number of instructions we've executed. */
759	uint32_t cInstructions;
760	/** The number of potential exits. */
761	uint32_t cPotentialExits;
762	/** The number of bytes data or stack written (mostly for IEMExecOneEx).
763	* This may contain uncommitted writes. */
764	uint32_t cbWritten;
765	/** Counts the VERR_IEM_INSTR_NOT_IMPLEMENTED returns. */
766	uint32_t cRetInstrNotImplemented;
767	/** Counts the VERR_IEM_ASPECT_NOT_IMPLEMENTED returns. */
768	uint32_t cRetAspectNotImplemented;
769	/** Counts informational statuses returned (other than VINF_SUCCESS). */
770	uint32_t cRetInfStatuses;
771	/** Counts other error statuses returned. */
772	uint32_t cRetErrStatuses;
773	/** Number of times rcPassUp has been used. */
774	uint32_t cRetPassUpStatus;
775	/** Number of times RZ left with instruction commit pending for ring-3. */
776	uint32_t cPendingCommit;
777	/** Number of long jumps. */
778	uint32_t cLongJumps;
779	/** @} */
780
781	/** @name Target CPU information.
782	* @{ */
783	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
784	/** The target CPU. */
785	uint8_t uTargetCpu;
786	#else
787	uint8_t bTargetCpuPadding;
788	#endif
789	/** For selecting assembly works matching the target CPU EFLAGS behaviour, see
790	* IEMTARGETCPU_EFL_BEHAVIOR_XXX for values, with the 1st entry for when no
791	* native host support and the 2nd for when there is.
792	*
793	* The two values are typically indexed by a g_CpumHostFeatures bit.
794	*
795	* This is for instance used for the BSF & BSR instructions where AMD and
796	* Intel CPUs produce different EFLAGS. */
797	uint8_t aidxTargetCpuEflFlavour[2];
798
799	/** The CPU vendor. */
800	CPUMCPUVENDOR enmCpuVendor;
801	/** @} */
802
803	/** @name Host CPU information.
804	* @{ */
805	/** The CPU vendor. */
806	CPUMCPUVENDOR enmHostCpuVendor;
807	/** @} */
808
809	/** Counts RDMSR \#GP(0) LogRel(). */
810	uint8_t cLogRelRdMsr;
811	/** Counts WRMSR \#GP(0) LogRel(). */
812	uint8_t cLogRelWrMsr;
813	/** Alignment padding. */
814	uint8_t abAlignment8[42];
815
816	/** Data TLB.
817	* @remarks Must be 64-byte aligned. */
818	IEMTLB DataTlb;
819	/** Instruction TLB.
820	* @remarks Must be 64-byte aligned. */
821	IEMTLB CodeTlb;
822
823	/** Exception statistics. */
824	STAMCOUNTER aStatXcpts[32];
825	/** Interrupt statistics. */
826	uint32_t aStatInts[256];
827
828	#if defined(VBOX_WITH_STATISTICS) && !defined(IN_TSTVMSTRUCT) && !defined(DOXYGEN_RUNNING)
829	/** Instruction statistics for ring-0/raw-mode. */
830	IEMINSTRSTATS StatsRZ;
831	/** Instruction statistics for ring-3. */
832	IEMINSTRSTATS StatsR3;
833	#endif
834	} IEMCPU;
835	AssertCompileMemberOffset(IEMCPU, fCurXcpt, 0x48);
836	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 8);
837	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 16);
838	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 32);
839	AssertCompileMemberAlignment(IEMCPU, aBounceBuffers, 64);
840	AssertCompileMemberAlignment(IEMCPU, DataTlb, 64);
841	AssertCompileMemberAlignment(IEMCPU, CodeTlb, 64);
842
843	/** Pointer to the per-CPU IEM state. */
844	typedef IEMCPU *PIEMCPU;
845	/** Pointer to the const per-CPU IEM state. */
846	typedef IEMCPU const *PCIEMCPU;
847
848
849	/** @def IEM_GET_CTX
850	* Gets the guest CPU context for the calling EMT.
851	* @returns PCPUMCTX
852	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
853	*/
854	#define IEM_GET_CTX(a_pVCpu) (&(a_pVCpu)->cpum.GstCtx)
855
856	/** @def IEM_CTX_ASSERT
857	* Asserts that the @a a_fExtrnMbz is present in the CPU context.
858	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
859	* @param a_fExtrnMbz The mask of CPUMCTX_EXTRN_XXX flags that must be zero.
860	*/
861	#define IEM_CTX_ASSERT(a_pVCpu, a_fExtrnMbz) AssertMsg(!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnMbz)), \
862	("fExtrn=%#RX64 fExtrnMbz=%#RX64\n", (a_pVCpu)->cpum.GstCtx.fExtrn, \
863	(a_fExtrnMbz)))
864
865	/** @def IEM_CTX_IMPORT_RET
866	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
867	*
868	* Will call the keep to import the bits as needed.
869	*
870	* Returns on import failure.
871	*
872	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
873	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
874	*/
875	#define IEM_CTX_IMPORT_RET(a_pVCpu, a_fExtrnImport) \
876	do { \
877	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
878	{ /* likely */ } \
879	else \
880	{ \
881	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
882	AssertRCReturn(rcCtxImport, rcCtxImport); \
883	} \
884	} while (0)
885
886	/** @def IEM_CTX_IMPORT_NORET
887	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
888	*
889	* Will call the keep to import the bits as needed.
890	*
891	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
892	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
893	*/
894	#define IEM_CTX_IMPORT_NORET(a_pVCpu, a_fExtrnImport) \
895	do { \
896	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
897	{ /* likely */ } \
898	else \
899	{ \
900	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
901	AssertLogRelRC(rcCtxImport); \
902	} \
903	} while (0)
904
905	/** @def IEM_CTX_IMPORT_JMP
906	* Makes sure the CPU context bits given by @a a_fExtrnImport are imported.
907	*
908	* Will call the keep to import the bits as needed.
909	*
910	* Jumps on import failure.
911	*
912	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
913	* @param a_fExtrnImport The mask of CPUMCTX_EXTRN_XXX flags to import.
914	*/
915	#define IEM_CTX_IMPORT_JMP(a_pVCpu, a_fExtrnImport) \
916	do { \
917	if (!((a_pVCpu)->cpum.GstCtx.fExtrn & (a_fExtrnImport))) \
918	{ /* likely */ } \
919	else \
920	{ \
921	int rcCtxImport = CPUMImportGuestStateOnDemand(a_pVCpu, a_fExtrnImport); \
922	AssertRCStmt(rcCtxImport, IEM_DO_LONGJMP(pVCpu, rcCtxImport)); \
923	} \
924	} while (0)
925
926
927
928	/** @def IEM_GET_TARGET_CPU
929	* Gets the current IEMTARGETCPU value.
930	* @returns IEMTARGETCPU value.
931	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
932	*/
933	#if IEM_CFG_TARGET_CPU != IEMTARGETCPU_DYNAMIC
934	# define IEM_GET_TARGET_CPU(a_pVCpu) (IEM_CFG_TARGET_CPU)
935	#else
936	# define IEM_GET_TARGET_CPU(a_pVCpu) ((a_pVCpu)->iem.s.uTargetCpu)
937	#endif
938
939	/** @def IEM_GET_INSTR_LEN
940	* Gets the instruction length. */
941	#ifdef IEM_WITH_CODE_TLB
942	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offInstrNextByte - (uint32_t)(int32_t)(a_pVCpu)->iem.s.offCurInstrStart)
943	#else
944	# define IEM_GET_INSTR_LEN(a_pVCpu) ((a_pVCpu)->iem.s.offOpcode)
945	#endif
946
947
948	/**
949	* Shared per-VM IEM data.
950	*/
951	typedef struct IEM
952	{
953	/** The VMX APIC-access page handler type. */
954	PGMPHYSHANDLERTYPE hVmxApicAccessPage;
955	#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
956	/** Set if the CPUID host call functionality is enabled. */
957	bool fCpuIdHostCall;
958	#endif
959	} IEM;
960
961
962
963	/** @name IEM_ACCESS_XXX - Access details.
964	* @{ */
965	#define IEM_ACCESS_INVALID UINT32_C(0x000000ff)
966	#define IEM_ACCESS_TYPE_READ UINT32_C(0x00000001)
967	#define IEM_ACCESS_TYPE_WRITE UINT32_C(0x00000002)
968	#define IEM_ACCESS_TYPE_EXEC UINT32_C(0x00000004)
969	#define IEM_ACCESS_TYPE_MASK UINT32_C(0x00000007)
970	#define IEM_ACCESS_WHAT_CODE UINT32_C(0x00000010)
971	#define IEM_ACCESS_WHAT_DATA UINT32_C(0x00000020)
972	#define IEM_ACCESS_WHAT_STACK UINT32_C(0x00000030)
973	#define IEM_ACCESS_WHAT_SYS UINT32_C(0x00000040)
974	#define IEM_ACCESS_WHAT_MASK UINT32_C(0x00000070)
975	/** The writes are partial, so if initialize the bounce buffer with the
976	* orignal RAM content. */
977	#define IEM_ACCESS_PARTIAL_WRITE UINT32_C(0x00000100)
978	/** Used in aMemMappings to indicate that the entry is bounce buffered. */
979	#define IEM_ACCESS_BOUNCE_BUFFERED UINT32_C(0x00000200)
980	/** Bounce buffer with ring-3 write pending, first page. */
981	#define IEM_ACCESS_PENDING_R3_WRITE_1ST UINT32_C(0x00000400)
982	/** Bounce buffer with ring-3 write pending, second page. */
983	#define IEM_ACCESS_PENDING_R3_WRITE_2ND UINT32_C(0x00000800)
984	/** Not locked, accessed via the TLB. */
985	#define IEM_ACCESS_NOT_LOCKED UINT32_C(0x00001000)
986	/** Valid bit mask. */
987	#define IEM_ACCESS_VALID_MASK UINT32_C(0x00001fff)
988	/** Shift count for the TLB flags (upper word). */
989	#define IEM_ACCESS_SHIFT_TLB_FLAGS 16
990
991	/** Read+write data alias. */
992	#define IEM_ACCESS_DATA_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
993	/** Write data alias. */
994	#define IEM_ACCESS_DATA_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_DATA)
995	/** Read data alias. */
996	#define IEM_ACCESS_DATA_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_DATA)
997	/** Instruction fetch alias. */
998	#define IEM_ACCESS_INSTRUCTION (IEM_ACCESS_TYPE_EXEC \| IEM_ACCESS_WHAT_CODE)
999	/** Stack write alias. */
1000	#define IEM_ACCESS_STACK_W (IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1001	/** Stack read alias. */
1002	#define IEM_ACCESS_STACK_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_STACK)
1003	/** Stack read+write alias. */
1004	#define IEM_ACCESS_STACK_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_STACK)
1005	/** Read system table alias. */
1006	#define IEM_ACCESS_SYS_R (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_WHAT_SYS)
1007	/** Read+write system table alias. */
1008	#define IEM_ACCESS_SYS_RW (IEM_ACCESS_TYPE_READ \| IEM_ACCESS_TYPE_WRITE \| IEM_ACCESS_WHAT_SYS)
1009	/** @} */
1010
1011	/** @name Prefix constants (IEMCPU::fPrefixes)
1012	* @{ */
1013	#define IEM_OP_PRF_SEG_CS RT_BIT_32(0) /*< CS segment prefix (0x2e). /
1014	#define IEM_OP_PRF_SEG_SS RT_BIT_32(1) /*< SS segment prefix (0x36). /
1015	#define IEM_OP_PRF_SEG_DS RT_BIT_32(2) /*< DS segment prefix (0x3e). /
1016	#define IEM_OP_PRF_SEG_ES RT_BIT_32(3) /*< ES segment prefix (0x26). /
1017	#define IEM_OP_PRF_SEG_FS RT_BIT_32(4) /*< FS segment prefix (0x64). /
1018	#define IEM_OP_PRF_SEG_GS RT_BIT_32(5) /*< GS segment prefix (0x65). /
1019	#define IEM_OP_PRF_SEG_MASK UINT32_C(0x3f)
1020
1021	#define IEM_OP_PRF_SIZE_OP RT_BIT_32(8) /*< Operand size prefix (0x66). /
1022	#define IEM_OP_PRF_SIZE_REX_W RT_BIT_32(9) /*< REX.W prefix (0x48-0x4f). /
1023	#define IEM_OP_PRF_SIZE_ADDR RT_BIT_32(10) /*< Address size prefix (0x67). /
1024
1025	#define IEM_OP_PRF_LOCK RT_BIT_32(16) /*< Lock prefix (0xf0). /
1026	#define IEM_OP_PRF_REPNZ RT_BIT_32(17) /*< Repeat-not-zero prefix (0xf2). /
1027	#define IEM_OP_PRF_REPZ RT_BIT_32(18) /*< Repeat-if-zero prefix (0xf3). /
1028
1029	#define IEM_OP_PRF_REX RT_BIT_32(24) /*< Any REX prefix (0x40-0x4f). /
1030	#define IEM_OP_PRF_REX_R RT_BIT_32(25) /*< REX.R prefix (0x44,0x45,0x46,0x47,0x4c,0x4d,0x4e,0x4f). /
1031	#define IEM_OP_PRF_REX_B RT_BIT_32(26) /*< REX.B prefix (0x41,0x43,0x45,0x47,0x49,0x4b,0x4d,0x4f). /
1032	#define IEM_OP_PRF_REX_X RT_BIT_32(27) /*< REX.X prefix (0x42,0x43,0x46,0x47,0x4a,0x4b,0x4e,0x4f). /
1033	/** Mask with all the REX prefix flags.
1034	* This is generally for use when needing to undo the REX prefixes when they
1035	* are followed legacy prefixes and therefore does not immediately preceed
1036	* the first opcode byte.
1037	* For testing whether any REX prefix is present, use IEM_OP_PRF_REX instead. */
1038	#define IEM_OP_PRF_REX_MASK (IEM_OP_PRF_REX \| IEM_OP_PRF_REX_R \| IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X \| IEM_OP_PRF_SIZE_REX_W )
1039
1040	#define IEM_OP_PRF_VEX RT_BIT_32(28) /*< Indiciates VEX prefix. /
1041	#define IEM_OP_PRF_EVEX RT_BIT_32(29) /*< Indiciates EVEX prefix. /
1042	#define IEM_OP_PRF_XOP RT_BIT_32(30) /*< Indiciates XOP prefix. /
1043	/** @} */
1044
1045	/** @name IEMOPFORM_XXX - Opcode forms
1046	* @note These are ORed together with IEMOPHINT_XXX.
1047	* @{ */
1048	/** ModR/M: reg, r/m */
1049	#define IEMOPFORM_RM 0
1050	/** ModR/M: reg, r/m (register) */
1051	#define IEMOPFORM_RM_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1052	/** ModR/M: reg, r/m (memory) */
1053	#define IEMOPFORM_RM_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1054	/** ModR/M: reg, r/m */
1055	#define IEMOPFORM_RMI 1
1056	/** ModR/M: reg, r/m (register) */
1057	#define IEMOPFORM_RMI_REG (IEMOPFORM_RM \| IEMOPFORM_MOD3)
1058	/** ModR/M: reg, r/m (memory) */
1059	#define IEMOPFORM_RMI_MEM (IEMOPFORM_RM \| IEMOPFORM_NOT_MOD3)
1060	/** ModR/M: r/m, reg */
1061	#define IEMOPFORM_MR 2
1062	/** ModR/M: r/m (register), reg */
1063	#define IEMOPFORM_MR_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1064	/** ModR/M: r/m (memory), reg */
1065	#define IEMOPFORM_MR_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1066	/** ModR/M: r/m, reg */
1067	#define IEMOPFORM_MRI 3
1068	/** ModR/M: r/m (register), reg */
1069	#define IEMOPFORM_MRI_REG (IEMOPFORM_MR \| IEMOPFORM_MOD3)
1070	/** ModR/M: r/m (memory), reg */
1071	#define IEMOPFORM_MRI_MEM (IEMOPFORM_MR \| IEMOPFORM_NOT_MOD3)
1072	/** ModR/M: r/m only */
1073	#define IEMOPFORM_M 4
1074	/** ModR/M: r/m only (register). */
1075	#define IEMOPFORM_M_REG (IEMOPFORM_M \| IEMOPFORM_MOD3)
1076	/** ModR/M: r/m only (memory). */
1077	#define IEMOPFORM_M_MEM (IEMOPFORM_M \| IEMOPFORM_NOT_MOD3)
1078	/** ModR/M: reg only */
1079	#define IEMOPFORM_R 5
1080
1081	/** VEX+ModR/M: reg, r/m */
1082	#define IEMOPFORM_VEX_RM 8
1083	/** VEX+ModR/M: reg, r/m (register) */
1084	#define IEMOPFORM_VEX_RM_REG (IEMOPFORM_VEX_RM \| IEMOPFORM_MOD3)
1085	/** VEX+ModR/M: reg, r/m (memory) */
1086	#define IEMOPFORM_VEX_RM_MEM (IEMOPFORM_VEX_RM \| IEMOPFORM_NOT_MOD3)
1087	/** VEX+ModR/M: r/m, reg */
1088	#define IEMOPFORM_VEX_MR 9
1089	/** VEX+ModR/M: r/m (register), reg */
1090	#define IEMOPFORM_VEX_MR_REG (IEMOPFORM_VEX_MR \| IEMOPFORM_MOD3)
1091	/** VEX+ModR/M: r/m (memory), reg */
1092	#define IEMOPFORM_VEX_MR_MEM (IEMOPFORM_VEX_MR \| IEMOPFORM_NOT_MOD3)
1093	/** VEX+ModR/M: r/m only */
1094	#define IEMOPFORM_VEX_M 10
1095	/** VEX+ModR/M: r/m only (register). */
1096	#define IEMOPFORM_VEX_M_REG (IEMOPFORM_VEX_M \| IEMOPFORM_MOD3)
1097	/** VEX+ModR/M: r/m only (memory). */
1098	#define IEMOPFORM_VEX_M_MEM (IEMOPFORM_VEX_M \| IEMOPFORM_NOT_MOD3)
1099	/** VEX+ModR/M: reg only */
1100	#define IEMOPFORM_VEX_R 11
1101	/** VEX+ModR/M: reg, vvvv, r/m */
1102	#define IEMOPFORM_VEX_RVM 12
1103	/** VEX+ModR/M: reg, vvvv, r/m (register). */
1104	#define IEMOPFORM_VEX_RVM_REG (IEMOPFORM_VEX_RVM \| IEMOPFORM_MOD3)
1105	/** VEX+ModR/M: reg, vvvv, r/m (memory). */
1106	#define IEMOPFORM_VEX_RVM_MEM (IEMOPFORM_VEX_RVM \| IEMOPFORM_NOT_MOD3)
1107	/** VEX+ModR/M: reg, r/m, vvvv */
1108	#define IEMOPFORM_VEX_RMV 13
1109	/** VEX+ModR/M: reg, r/m, vvvv (register). */
1110	#define IEMOPFORM_VEX_RMV_REG (IEMOPFORM_VEX_RMV \| IEMOPFORM_MOD3)
1111	/** VEX+ModR/M: reg, r/m, vvvv (memory). */
1112	#define IEMOPFORM_VEX_RMV_MEM (IEMOPFORM_VEX_RMV \| IEMOPFORM_NOT_MOD3)
1113	/** VEX+ModR/M: reg, r/m, imm8 */
1114	#define IEMOPFORM_VEX_RMI 14
1115	/** VEX+ModR/M: reg, r/m, imm8 (register). */
1116	#define IEMOPFORM_VEX_RMI_REG (IEMOPFORM_VEX_RMI \| IEMOPFORM_MOD3)
1117	/** VEX+ModR/M: reg, r/m, imm8 (memory). */
1118	#define IEMOPFORM_VEX_RMI_MEM (IEMOPFORM_VEX_RMI \| IEMOPFORM_NOT_MOD3)
1119	/** VEX+ModR/M: r/m, vvvv, reg */
1120	#define IEMOPFORM_VEX_MVR 15
1121	/** VEX+ModR/M: r/m, vvvv, reg (register) */
1122	#define IEMOPFORM_VEX_MVR_REG (IEMOPFORM_VEX_MVR \| IEMOPFORM_MOD3)
1123	/** VEX+ModR/M: r/m, vvvv, reg (memory) */
1124	#define IEMOPFORM_VEX_MVR_MEM (IEMOPFORM_VEX_MVR \| IEMOPFORM_NOT_MOD3)
1125	/** VEX+ModR/M+/n: vvvv, r/m */
1126	#define IEMOPFORM_VEX_VM 16
1127	/** VEX+ModR/M+/n: vvvv, r/m (register) */
1128	#define IEMOPFORM_VEX_VM_REG (IEMOPFORM_VEX_VM \| IEMOPFORM_MOD3)
1129	/** VEX+ModR/M+/n: vvvv, r/m (memory) */
1130	#define IEMOPFORM_VEX_VM_MEM (IEMOPFORM_VEX_VM \| IEMOPFORM_NOT_MOD3)
1131
1132	/** Fixed register instruction, no R/M. */
1133	#define IEMOPFORM_FIXED 32
1134
1135	/** The r/m is a register. */
1136	#define IEMOPFORM_MOD3 RT_BIT_32(8)
1137	/** The r/m is a memory access. */
1138	#define IEMOPFORM_NOT_MOD3 RT_BIT_32(9)
1139	/** @} */
1140
1141	/** @name IEMOPHINT_XXX - Additional Opcode Hints
1142	* @note These are ORed together with IEMOPFORM_XXX.
1143	* @{ */
1144	/** Ignores the operand size prefix (66h). */
1145	#define IEMOPHINT_IGNORES_OZ_PFX RT_BIT_32(10)
1146	/** Ignores REX.W (aka WIG). */
1147	#define IEMOPHINT_IGNORES_REXW RT_BIT_32(11)
1148	/** Both the operand size prefixes (66h + REX.W) are ignored. */
1149	#define IEMOPHINT_IGNORES_OP_SIZES (IEMOPHINT_IGNORES_OZ_PFX \| IEMOPHINT_IGNORES_REXW)
1150	/** Allowed with the lock prefix. */
1151	#define IEMOPHINT_LOCK_ALLOWED RT_BIT_32(11)
1152	/** The VEX.L value is ignored (aka LIG). */
1153	#define IEMOPHINT_VEX_L_IGNORED RT_BIT_32(12)
1154	/** The VEX.L value must be zero (i.e. 128-bit width only). */
1155	#define IEMOPHINT_VEX_L_ZERO RT_BIT_32(13)
1156	/** The VEX.V value must be zero. */
1157	#define IEMOPHINT_VEX_V_ZERO RT_BIT_32(14)
1158
1159	/** Hint to IEMAllInstructionPython.py that this macro should be skipped. */
1160	#define IEMOPHINT_SKIP_PYTHON RT_BIT_32(31)
1161	/** @} */
1162
1163	/**
1164	* Possible hardware task switch sources.
1165	*/
1166	typedef enum IEMTASKSWITCH
1167	{
1168	/** Task switch caused by an interrupt/exception. */
1169	IEMTASKSWITCH_INT_XCPT = 1,
1170	/** Task switch caused by a far CALL. */
1171	IEMTASKSWITCH_CALL,
1172	/** Task switch caused by a far JMP. */
1173	IEMTASKSWITCH_JUMP,
1174	/** Task switch caused by an IRET. */
1175	IEMTASKSWITCH_IRET
1176	} IEMTASKSWITCH;
1177	AssertCompileSize(IEMTASKSWITCH, 4);
1178
1179	/**
1180	* Possible CrX load (write) sources.
1181	*/
1182	typedef enum IEMACCESSCRX
1183	{
1184	/** CrX access caused by 'mov crX' instruction. */
1185	IEMACCESSCRX_MOV_CRX,
1186	/** CrX (CR0) write caused by 'lmsw' instruction. */
1187	IEMACCESSCRX_LMSW,
1188	/** CrX (CR0) write caused by 'clts' instruction. */
1189	IEMACCESSCRX_CLTS,
1190	/** CrX (CR0) read caused by 'smsw' instruction. */
1191	IEMACCESSCRX_SMSW
1192	} IEMACCESSCRX;
1193
1194	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1195	/** @name IEM_SLAT_FAIL_XXX - Second-level address translation failure information.
1196	*
1197	* These flags provide further context to SLAT page-walk failures that could not be
1198	* determined by PGM (e.g, PGM is not privy to memory access permissions).
1199	*
1200	* @{
1201	*/
1202	/** Translating a nested-guest linear address failed accessing a nested-guest
1203	* physical address. */
1204	# define IEM_SLAT_FAIL_LINEAR_TO_PHYS_ADDR RT_BIT_32(0)
1205	/** Translating a nested-guest linear address failed accessing a
1206	* paging-structure entry or updating accessed/dirty bits. */
1207	# define IEM_SLAT_FAIL_LINEAR_TO_PAGE_TABLE RT_BIT_32(1)
1208	/** @} */
1209
1210	DECLCALLBACK(FNPGMPHYSHANDLER) iemVmxApicAccessPageHandler;
1211	# ifndef IN_RING3
1212	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) iemVmxApicAccessPagePfHandler;
1213	# endif
1214	#endif
1215
1216	/**
1217	* Indicates to the verifier that the given flag set is undefined.
1218	*
1219	* Can be invoked again to add more flags.
1220	*
1221	* This is a NOOP if the verifier isn't compiled in.
1222	*
1223	* @note We're temporarily keeping this until code is converted to new
1224	* disassembler style opcode handling.
1225	*/
1226	#define IEMOP_VERIFICATION_UNDEFINED_EFLAGS(a_fEfl) do { } while (0)
1227
1228
1229	/** @def IEM_DECL_IMPL_TYPE
1230	* For typedef'ing an instruction implementation function.
1231	*
1232	* @param a_RetType The return type.
1233	* @param a_Name The name of the type.
1234	* @param a_ArgList The argument list enclosed in parentheses.
1235	*/
1236
1237	/** @def IEM_DECL_IMPL_DEF
1238	* For defining an instruction implementation function.
1239	*
1240	* @param a_RetType The return type.
1241	* @param a_Name The name of the type.
1242	* @param a_ArgList The argument list enclosed in parentheses.
1243	*/
1244
1245	#if defined(__GNUC__) && defined(RT_ARCH_X86)
1246	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1247	__attribute__((__fastcall__)) a_RetType (a_Name) a_ArgList
1248	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1249	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1250	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1251	__attribute__((__fastcall__, __nothrow__)) a_RetType a_Name a_ArgList
1252
1253	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
1254	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1255	a_RetType (__fastcall a_Name) a_ArgList
1256	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1257	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1258	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1259	a_RetType __fastcall a_Name a_ArgList RT_NOEXCEPT
1260
1261	#elif __cplusplus >= 201700 /* P0012R1 support */
1262	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1263	a_RetType (VBOXCALL a_Name) a_ArgList RT_NOEXCEPT
1264	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1265	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1266	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1267	a_RetType VBOXCALL a_Name a_ArgList RT_NOEXCEPT
1268
1269	#else
1270	# define IEM_DECL_IMPL_TYPE(a_RetType, a_Name, a_ArgList) \
1271	a_RetType (VBOXCALL a_Name) a_ArgList
1272	# define IEM_DECL_IMPL_DEF(a_RetType, a_Name, a_ArgList) \
1273	a_RetType VBOXCALL a_Name a_ArgList
1274	# define IEM_DECL_IMPL_PROTO(a_RetType, a_Name, a_ArgList) \
1275	a_RetType VBOXCALL a_Name a_ArgList
1276
1277	#endif
1278
1279	/** Defined in IEMAllAImplC.cpp but also used by IEMAllAImplA.asm. */
1280	RT_C_DECLS_BEGIN
1281	extern uint8_t const g_afParity[256];
1282	RT_C_DECLS_END
1283
1284
1285	/** @name Arithmetic assignment operations on bytes (binary).
1286	* @{ */
1287	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8, (uint8_t pu8Dst, uint8_t u8Src, uint32_t pEFlags));
1288	typedef FNIEMAIMPLBINU8 *PFNIEMAIMPLBINU8;
1289	FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
1290	FNIEMAIMPLBINU8 iemAImpl_adc_u8, iemAImpl_adc_u8_locked;
1291	FNIEMAIMPLBINU8 iemAImpl_sub_u8, iemAImpl_sub_u8_locked;
1292	FNIEMAIMPLBINU8 iemAImpl_sbb_u8, iemAImpl_sbb_u8_locked;
1293	FNIEMAIMPLBINU8 iemAImpl_or_u8, iemAImpl_or_u8_locked;
1294	FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
1295	FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
1296	/** @} */
1297
1298	/** @name Arithmetic assignment operations on words (binary).
1299	* @{ */
1300	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16, (uint16_t pu16Dst, uint16_t u16Src, uint32_t pEFlags));
1301	typedef FNIEMAIMPLBINU16 *PFNIEMAIMPLBINU16;
1302	FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
1303	FNIEMAIMPLBINU16 iemAImpl_adc_u16, iemAImpl_adc_u16_locked;
1304	FNIEMAIMPLBINU16 iemAImpl_sub_u16, iemAImpl_sub_u16_locked;
1305	FNIEMAIMPLBINU16 iemAImpl_sbb_u16, iemAImpl_sbb_u16_locked;
1306	FNIEMAIMPLBINU16 iemAImpl_or_u16, iemAImpl_or_u16_locked;
1307	FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
1308	FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
1309	/** @} */
1310
1311	/** @name Arithmetic assignment operations on double words (binary).
1312	* @{ */
1313	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t pu32Dst, uint32_t u32Src, uint32_t pEFlags));
1314	typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
1315	FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
1316	FNIEMAIMPLBINU32 iemAImpl_adc_u32, iemAImpl_adc_u32_locked;
1317	FNIEMAIMPLBINU32 iemAImpl_sub_u32, iemAImpl_sub_u32_locked;
1318	FNIEMAIMPLBINU32 iemAImpl_sbb_u32, iemAImpl_sbb_u32_locked;
1319	FNIEMAIMPLBINU32 iemAImpl_or_u32, iemAImpl_or_u32_locked;
1320	FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
1321	FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
1322	FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
1323	FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
1324	FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
1325	/** @} */
1326
1327	/** @name Arithmetic assignment operations on quad words (binary).
1328	* @{ */
1329	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t pu64Dst, uint64_t u64Src, uint32_t pEFlags));
1330	typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
1331	FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
1332	FNIEMAIMPLBINU64 iemAImpl_adc_u64, iemAImpl_adc_u64_locked;
1333	FNIEMAIMPLBINU64 iemAImpl_sub_u64, iemAImpl_sub_u64_locked;
1334	FNIEMAIMPLBINU64 iemAImpl_sbb_u64, iemAImpl_sbb_u64_locked;
1335	FNIEMAIMPLBINU64 iemAImpl_or_u64, iemAImpl_or_u64_locked;
1336	FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
1337	FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
1338	FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
1339	FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
1340	FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
1341	/** @} */
1342
1343	/** @name Compare operations (thrown in with the binary ops).
1344	* @{ */
1345	FNIEMAIMPLBINU8 iemAImpl_cmp_u8;
1346	FNIEMAIMPLBINU16 iemAImpl_cmp_u16;
1347	FNIEMAIMPLBINU32 iemAImpl_cmp_u32;
1348	FNIEMAIMPLBINU64 iemAImpl_cmp_u64;
1349	/** @} */
1350
1351	/** @name Test operations (thrown in with the binary ops).
1352	* @{ */
1353	FNIEMAIMPLBINU8 iemAImpl_test_u8;
1354	FNIEMAIMPLBINU16 iemAImpl_test_u16;
1355	FNIEMAIMPLBINU32 iemAImpl_test_u32;
1356	FNIEMAIMPLBINU64 iemAImpl_test_u64;
1357	/** @} */
1358
1359	/** @name Bit operations operations (thrown in with the binary ops).
1360	* @{ */
1361	FNIEMAIMPLBINU16 iemAImpl_bt_u16;
1362	FNIEMAIMPLBINU32 iemAImpl_bt_u32;
1363	FNIEMAIMPLBINU64 iemAImpl_bt_u64;
1364	FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
1365	FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
1366	FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
1367	FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
1368	FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
1369	FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
1370	FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
1371	FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
1372	FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
1373	/** @} */
1374
1375	/** @name Arithmetic three operand operations on double words (binary).
1376	* @{ */
1377	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32, (uint32_t pu32Dst, uint32_t u32Src1, uint32_t u32Src2, uint32_t pEFlags));
1378	typedef FNIEMAIMPLBINVEXU32 *PFNIEMAIMPLBINVEXU32;
1379	FNIEMAIMPLBINVEXU32 iemAImpl_andn_u32, iemAImpl_andn_u32_fallback;
1380	FNIEMAIMPLBINVEXU32 iemAImpl_bextr_u32, iemAImpl_bextr_u32_fallback;
1381	FNIEMAIMPLBINVEXU32 iemAImpl_bzhi_u32, iemAImpl_bzhi_u32_fallback;
1382	/** @} */
1383
1384	/** @name Arithmetic three operand operations on quad words (binary).
1385	* @{ */
1386	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64, (uint64_t pu64Dst, uint64_t u64Src1, uint64_t u64Src2, uint32_t pEFlags));
1387	typedef FNIEMAIMPLBINVEXU64 *PFNIEMAIMPLBINVEXU64;
1388	FNIEMAIMPLBINVEXU64 iemAImpl_andn_u64, iemAImpl_andn_u64_fallback;
1389	FNIEMAIMPLBINVEXU64 iemAImpl_bextr_u64, iemAImpl_bextr_u64_fallback;
1390	FNIEMAIMPLBINVEXU64 iemAImpl_bzhi_u64, iemAImpl_bzhi_u64_fallback;
1391	/** @} */
1392
1393	/** @name Arithmetic three operand operations on double words w/o EFLAGS (binary).
1394	* @{ */
1395	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU32NOEFL, (uint32_t *pu32Dst, uint32_t u32Src1, uint32_t u32Src2));
1396	typedef FNIEMAIMPLBINVEXU32NOEFL *PFNIEMAIMPLBINVEXU32NOEFL;
1397	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pdep_u32, iemAImpl_pdep_u32_fallback;
1398	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_pext_u32, iemAImpl_pext_u32_fallback;
1399	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_sarx_u32, iemAImpl_sarx_u32_fallback;
1400	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shlx_u32, iemAImpl_shlx_u32_fallback;
1401	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_shrx_u32, iemAImpl_shrx_u32_fallback;
1402	FNIEMAIMPLBINVEXU32NOEFL iemAImpl_rorx_u32;
1403	/** @} */
1404
1405	/** @name Arithmetic three operand operations on quad words w/o EFLAGS (binary).
1406	* @{ */
1407	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINVEXU64NOEFL, (uint64_t *pu64Dst, uint64_t u64Src1, uint64_t u64Src2));
1408	typedef FNIEMAIMPLBINVEXU64NOEFL *PFNIEMAIMPLBINVEXU64NOEFL;
1409	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pdep_u64, iemAImpl_pdep_u64_fallback;
1410	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_pext_u64, iemAImpl_pext_u64_fallback;
1411	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_sarx_u64, iemAImpl_sarx_u64_fallback;
1412	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shlx_u64, iemAImpl_shlx_u64_fallback;
1413	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_shrx_u64, iemAImpl_shrx_u64_fallback;
1414	FNIEMAIMPLBINVEXU64NOEFL iemAImpl_rorx_u64;
1415	/** @} */
1416
1417	/** @name MULX 32-bit and 64-bit.
1418	* @{ */
1419	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU32, (uint32_t puDst1, uint32_t puDst2, uint32_t uSrc1, uint32_t uSrc2));
1420	typedef FNIEMAIMPLMULXVEXU32 *PFNIEMAIMPLMULXVEXU32;
1421	FNIEMAIMPLMULXVEXU32 iemAImpl_mulx_u32, iemAImpl_mulx_u32_fallback;
1422
1423	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMULXVEXU64, (uint64_t puDst1, uint64_t puDst2, uint64_t uSrc1, uint64_t uSrc2));
1424	typedef FNIEMAIMPLMULXVEXU64 *PFNIEMAIMPLMULXVEXU64;
1425	FNIEMAIMPLMULXVEXU64 iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback;
1426	/** @} */
1427
1428
1429	/** @name Exchange memory with register operations.
1430	* @{ */
1431	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_locked, (uint8_t pu8Mem, uint8_t pu8Reg));
1432	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_locked,(uint16_t pu16Mem, uint16_t pu16Reg));
1433	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_locked,(uint32_t pu32Mem, uint32_t pu32Reg));
1434	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_locked,(uint64_t pu64Mem, uint64_t pu64Reg));
1435	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u8_unlocked, (uint8_t pu8Mem, uint8_t pu8Reg));
1436	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u16_unlocked,(uint16_t pu16Mem, uint16_t pu16Reg));
1437	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u32_unlocked,(uint32_t pu32Mem, uint32_t pu32Reg));
1438	IEM_DECL_IMPL_DEF(void, iemAImpl_xchg_u64_unlocked,(uint64_t pu64Mem, uint64_t pu64Reg));
1439	/** @} */
1440
1441	/** @name Exchange and add operations.
1442	* @{ */
1443	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1444	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1445	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1446	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1447	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u8_locked, (uint8_t pu8Dst, uint8_t pu8Reg, uint32_t *pEFlags));
1448	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u16_locked,(uint16_t pu16Dst, uint16_t pu16Reg, uint32_t *pEFlags));
1449	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u32_locked,(uint32_t pu32Dst, uint32_t pu32Reg, uint32_t *pEFlags));
1450	IEM_DECL_IMPL_DEF(void, iemAImpl_xadd_u64_locked,(uint64_t pu64Dst, uint64_t pu64Reg, uint32_t *pEFlags));
1451	/** @} */
1452
1453	/** @name Compare and exchange.
1454	* @{ */
1455	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1456	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u8_locked, (uint8_t pu8Dst, uint8_t puAl, uint8_t uSrcReg, uint32_t *pEFlags));
1457	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16, (uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1458	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u16_locked,(uint16_t pu16Dst, uint16_t puAx, uint16_t uSrcReg, uint32_t *pEFlags));
1459	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32, (uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1460	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u32_locked,(uint32_t pu32Dst, uint32_t puEax, uint32_t uSrcReg, uint32_t *pEFlags));
1461	#if ARCH_BITS == 32
1462	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1463	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t puSrcReg, uint32_t pEFlags));
1464	#else
1465	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64, (uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1466	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg_u64_locked,(uint64_t pu64Dst, uint64_t puRax, uint64_t uSrcReg, uint32_t *pEFlags));
1467	#endif
1468	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1469	uint32_t *pEFlags));
1470	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg8b_locked,(uint64_t *pu64Dst, PRTUINT64U pu64EaxEdx, PRTUINT64U pu64EbxEcx,
1471	uint32_t *pEFlags));
1472	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1473	uint32_t *pEFlags));
1474	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_locked,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx, PRTUINT128U pu128RbxRcx,
1475	uint32_t *pEFlags));
1476	#ifndef RT_ARCH_ARM64
1477	IEM_DECL_IMPL_DEF(void, iemAImpl_cmpxchg16b_fallback,(PRTUINT128U pu128Dst, PRTUINT128U pu128RaxRdx,
1478	PRTUINT128U pu128RbxRcx, uint32_t *pEFlags));
1479	#endif
1480	/** @} */
1481
1482	/** @name Memory ordering
1483	* @{ */
1484	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEMFENCE,(void));
1485	typedef FNIEMAIMPLMEMFENCE *PFNIEMAIMPLMEMFENCE;
1486	IEM_DECL_IMPL_DEF(void, iemAImpl_mfence,(void));
1487	IEM_DECL_IMPL_DEF(void, iemAImpl_sfence,(void));
1488	IEM_DECL_IMPL_DEF(void, iemAImpl_lfence,(void));
1489	#ifndef RT_ARCH_ARM64
1490	IEM_DECL_IMPL_DEF(void, iemAImpl_alt_mem_fence,(void));
1491	#endif
1492	/** @} */
1493
1494	/** @name Double precision shifts
1495	* @{ */
1496	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU16,(uint16_t pu16Dst, uint16_t u16Src, uint8_t cShift, uint32_t pEFlags));
1497	typedef FNIEMAIMPLSHIFTDBLU16 *PFNIEMAIMPLSHIFTDBLU16;
1498	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU32,(uint32_t pu32Dst, uint32_t u32Src, uint8_t cShift, uint32_t pEFlags));
1499	typedef FNIEMAIMPLSHIFTDBLU32 *PFNIEMAIMPLSHIFTDBLU32;
1500	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTDBLU64,(uint64_t pu64Dst, uint64_t u64Src, uint8_t cShift, uint32_t pEFlags));
1501	typedef FNIEMAIMPLSHIFTDBLU64 *PFNIEMAIMPLSHIFTDBLU64;
1502	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shld_u16, iemAImpl_shld_u16_amd, iemAImpl_shld_u16_intel;
1503	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shld_u32, iemAImpl_shld_u32_amd, iemAImpl_shld_u32_intel;
1504	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shld_u64, iemAImpl_shld_u64_amd, iemAImpl_shld_u64_intel;
1505	FNIEMAIMPLSHIFTDBLU16 iemAImpl_shrd_u16, iemAImpl_shrd_u16_amd, iemAImpl_shrd_u16_intel;
1506	FNIEMAIMPLSHIFTDBLU32 iemAImpl_shrd_u32, iemAImpl_shrd_u32_amd, iemAImpl_shrd_u32_intel;
1507	FNIEMAIMPLSHIFTDBLU64 iemAImpl_shrd_u64, iemAImpl_shrd_u64_amd, iemAImpl_shrd_u64_intel;
1508	/** @} */
1509
1510
1511	/** @name Bit search operations (thrown in with the binary ops).
1512	* @{ */
1513	FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
1514	FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
1515	FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
1516	FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
1517	FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
1518	FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
1519	FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
1520	FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
1521	FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
1522	FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
1523	FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
1524	FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
1525	FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
1526	FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
1527	FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
1528	/** @} */
1529
1530	/** @name Signed multiplication operations (thrown in with the binary ops).
1531	* @{ */
1532	FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
1533	FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
1534	FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
1535	/** @} */
1536
1537	/** @name Arithmetic assignment operations on bytes (unary).
1538	* @{ */
1539	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU8, (uint8_t pu8Dst, uint32_t pEFlags));
1540	typedef FNIEMAIMPLUNARYU8 *PFNIEMAIMPLUNARYU8;
1541	FNIEMAIMPLUNARYU8 iemAImpl_inc_u8, iemAImpl_inc_u8_locked;
1542	FNIEMAIMPLUNARYU8 iemAImpl_dec_u8, iemAImpl_dec_u8_locked;
1543	FNIEMAIMPLUNARYU8 iemAImpl_not_u8, iemAImpl_not_u8_locked;
1544	FNIEMAIMPLUNARYU8 iemAImpl_neg_u8, iemAImpl_neg_u8_locked;
1545	/** @} */
1546
1547	/** @name Arithmetic assignment operations on words (unary).
1548	* @{ */
1549	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU16, (uint16_t pu16Dst, uint32_t pEFlags));
1550	typedef FNIEMAIMPLUNARYU16 *PFNIEMAIMPLUNARYU16;
1551	FNIEMAIMPLUNARYU16 iemAImpl_inc_u16, iemAImpl_inc_u16_locked;
1552	FNIEMAIMPLUNARYU16 iemAImpl_dec_u16, iemAImpl_dec_u16_locked;
1553	FNIEMAIMPLUNARYU16 iemAImpl_not_u16, iemAImpl_not_u16_locked;
1554	FNIEMAIMPLUNARYU16 iemAImpl_neg_u16, iemAImpl_neg_u16_locked;
1555	/** @} */
1556
1557	/** @name Arithmetic assignment operations on double words (unary).
1558	* @{ */
1559	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU32, (uint32_t pu32Dst, uint32_t pEFlags));
1560	typedef FNIEMAIMPLUNARYU32 *PFNIEMAIMPLUNARYU32;
1561	FNIEMAIMPLUNARYU32 iemAImpl_inc_u32, iemAImpl_inc_u32_locked;
1562	FNIEMAIMPLUNARYU32 iemAImpl_dec_u32, iemAImpl_dec_u32_locked;
1563	FNIEMAIMPLUNARYU32 iemAImpl_not_u32, iemAImpl_not_u32_locked;
1564	FNIEMAIMPLUNARYU32 iemAImpl_neg_u32, iemAImpl_neg_u32_locked;
1565	/** @} */
1566
1567	/** @name Arithmetic assignment operations on quad words (unary).
1568	* @{ */
1569	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLUNARYU64, (uint64_t pu64Dst, uint32_t pEFlags));
1570	typedef FNIEMAIMPLUNARYU64 *PFNIEMAIMPLUNARYU64;
1571	FNIEMAIMPLUNARYU64 iemAImpl_inc_u64, iemAImpl_inc_u64_locked;
1572	FNIEMAIMPLUNARYU64 iemAImpl_dec_u64, iemAImpl_dec_u64_locked;
1573	FNIEMAIMPLUNARYU64 iemAImpl_not_u64, iemAImpl_not_u64_locked;
1574	FNIEMAIMPLUNARYU64 iemAImpl_neg_u64, iemAImpl_neg_u64_locked;
1575	/** @} */
1576
1577
1578	/** @name Shift operations on bytes (Group 2).
1579	* @{ */
1580	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU8,(uint8_t pu8Dst, uint8_t cShift, uint32_t pEFlags));
1581	typedef FNIEMAIMPLSHIFTU8 *PFNIEMAIMPLSHIFTU8;
1582	FNIEMAIMPLSHIFTU8 iemAImpl_rol_u8, iemAImpl_rol_u8_amd, iemAImpl_rol_u8_intel;
1583	FNIEMAIMPLSHIFTU8 iemAImpl_ror_u8, iemAImpl_ror_u8_amd, iemAImpl_ror_u8_intel;
1584	FNIEMAIMPLSHIFTU8 iemAImpl_rcl_u8, iemAImpl_rcl_u8_amd, iemAImpl_rcl_u8_intel;
1585	FNIEMAIMPLSHIFTU8 iemAImpl_rcr_u8, iemAImpl_rcr_u8_amd, iemAImpl_rcr_u8_intel;
1586	FNIEMAIMPLSHIFTU8 iemAImpl_shl_u8, iemAImpl_shl_u8_amd, iemAImpl_shl_u8_intel;
1587	FNIEMAIMPLSHIFTU8 iemAImpl_shr_u8, iemAImpl_shr_u8_amd, iemAImpl_shr_u8_intel;
1588	FNIEMAIMPLSHIFTU8 iemAImpl_sar_u8, iemAImpl_sar_u8_amd, iemAImpl_sar_u8_intel;
1589	/** @} */
1590
1591	/** @name Shift operations on words (Group 2).
1592	* @{ */
1593	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU16,(uint16_t pu16Dst, uint8_t cShift, uint32_t pEFlags));
1594	typedef FNIEMAIMPLSHIFTU16 *PFNIEMAIMPLSHIFTU16;
1595	FNIEMAIMPLSHIFTU16 iemAImpl_rol_u16, iemAImpl_rol_u16_amd, iemAImpl_rol_u16_intel;
1596	FNIEMAIMPLSHIFTU16 iemAImpl_ror_u16, iemAImpl_ror_u16_amd, iemAImpl_ror_u16_intel;
1597	FNIEMAIMPLSHIFTU16 iemAImpl_rcl_u16, iemAImpl_rcl_u16_amd, iemAImpl_rcl_u16_intel;
1598	FNIEMAIMPLSHIFTU16 iemAImpl_rcr_u16, iemAImpl_rcr_u16_amd, iemAImpl_rcr_u16_intel;
1599	FNIEMAIMPLSHIFTU16 iemAImpl_shl_u16, iemAImpl_shl_u16_amd, iemAImpl_shl_u16_intel;
1600	FNIEMAIMPLSHIFTU16 iemAImpl_shr_u16, iemAImpl_shr_u16_amd, iemAImpl_shr_u16_intel;
1601	FNIEMAIMPLSHIFTU16 iemAImpl_sar_u16, iemAImpl_sar_u16_amd, iemAImpl_sar_u16_intel;
1602	/** @} */
1603
1604	/** @name Shift operations on double words (Group 2).
1605	* @{ */
1606	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU32,(uint32_t pu32Dst, uint8_t cShift, uint32_t pEFlags));
1607	typedef FNIEMAIMPLSHIFTU32 *PFNIEMAIMPLSHIFTU32;
1608	FNIEMAIMPLSHIFTU32 iemAImpl_rol_u32, iemAImpl_rol_u32_amd, iemAImpl_rol_u32_intel;
1609	FNIEMAIMPLSHIFTU32 iemAImpl_ror_u32, iemAImpl_ror_u32_amd, iemAImpl_ror_u32_intel;
1610	FNIEMAIMPLSHIFTU32 iemAImpl_rcl_u32, iemAImpl_rcl_u32_amd, iemAImpl_rcl_u32_intel;
1611	FNIEMAIMPLSHIFTU32 iemAImpl_rcr_u32, iemAImpl_rcr_u32_amd, iemAImpl_rcr_u32_intel;
1612	FNIEMAIMPLSHIFTU32 iemAImpl_shl_u32, iemAImpl_shl_u32_amd, iemAImpl_shl_u32_intel;
1613	FNIEMAIMPLSHIFTU32 iemAImpl_shr_u32, iemAImpl_shr_u32_amd, iemAImpl_shr_u32_intel;
1614	FNIEMAIMPLSHIFTU32 iemAImpl_sar_u32, iemAImpl_sar_u32_amd, iemAImpl_sar_u32_intel;
1615	/** @} */
1616
1617	/** @name Shift operations on words (Group 2).
1618	* @{ */
1619	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSHIFTU64,(uint64_t pu64Dst, uint8_t cShift, uint32_t pEFlags));
1620	typedef FNIEMAIMPLSHIFTU64 *PFNIEMAIMPLSHIFTU64;
1621	FNIEMAIMPLSHIFTU64 iemAImpl_rol_u64, iemAImpl_rol_u64_amd, iemAImpl_rol_u64_intel;
1622	FNIEMAIMPLSHIFTU64 iemAImpl_ror_u64, iemAImpl_ror_u64_amd, iemAImpl_ror_u64_intel;
1623	FNIEMAIMPLSHIFTU64 iemAImpl_rcl_u64, iemAImpl_rcl_u64_amd, iemAImpl_rcl_u64_intel;
1624	FNIEMAIMPLSHIFTU64 iemAImpl_rcr_u64, iemAImpl_rcr_u64_amd, iemAImpl_rcr_u64_intel;
1625	FNIEMAIMPLSHIFTU64 iemAImpl_shl_u64, iemAImpl_shl_u64_amd, iemAImpl_shl_u64_intel;
1626	FNIEMAIMPLSHIFTU64 iemAImpl_shr_u64, iemAImpl_shr_u64_amd, iemAImpl_shr_u64_intel;
1627	FNIEMAIMPLSHIFTU64 iemAImpl_sar_u64, iemAImpl_sar_u64_amd, iemAImpl_sar_u64_intel;
1628	/** @} */
1629
1630	/** @name Multiplication and division operations.
1631	* @{ */
1632	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU8,(uint16_t pu16AX, uint8_t u8FactorDivisor, uint32_t pEFlags));
1633	typedef FNIEMAIMPLMULDIVU8 *PFNIEMAIMPLMULDIVU8;
1634	FNIEMAIMPLMULDIVU8 iemAImpl_mul_u8, iemAImpl_mul_u8_amd, iemAImpl_mul_u8_intel;
1635	FNIEMAIMPLMULDIVU8 iemAImpl_imul_u8, iemAImpl_imul_u8_amd, iemAImpl_imul_u8_intel;
1636	FNIEMAIMPLMULDIVU8 iemAImpl_div_u8, iemAImpl_div_u8_amd, iemAImpl_div_u8_intel;
1637	FNIEMAIMPLMULDIVU8 iemAImpl_idiv_u8, iemAImpl_idiv_u8_amd, iemAImpl_idiv_u8_intel;
1638
1639	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU16,(uint16_t pu16AX, uint16_t pu16DX, uint16_t u16FactorDivisor, uint32_t *pEFlags));
1640	typedef FNIEMAIMPLMULDIVU16 *PFNIEMAIMPLMULDIVU16;
1641	FNIEMAIMPLMULDIVU16 iemAImpl_mul_u16, iemAImpl_mul_u16_amd, iemAImpl_mul_u16_intel;
1642	FNIEMAIMPLMULDIVU16 iemAImpl_imul_u16, iemAImpl_imul_u16_amd, iemAImpl_imul_u16_intel;
1643	FNIEMAIMPLMULDIVU16 iemAImpl_div_u16, iemAImpl_div_u16_amd, iemAImpl_div_u16_intel;
1644	FNIEMAIMPLMULDIVU16 iemAImpl_idiv_u16, iemAImpl_idiv_u16_amd, iemAImpl_idiv_u16_intel;
1645
1646	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU32,(uint32_t pu32EAX, uint32_t pu32EDX, uint32_t u32FactorDivisor, uint32_t *pEFlags));
1647	typedef FNIEMAIMPLMULDIVU32 *PFNIEMAIMPLMULDIVU32;
1648	FNIEMAIMPLMULDIVU32 iemAImpl_mul_u32, iemAImpl_mul_u32_amd, iemAImpl_mul_u32_intel;
1649	FNIEMAIMPLMULDIVU32 iemAImpl_imul_u32, iemAImpl_imul_u32_amd, iemAImpl_imul_u32_intel;
1650	FNIEMAIMPLMULDIVU32 iemAImpl_div_u32, iemAImpl_div_u32_amd, iemAImpl_div_u32_intel;
1651	FNIEMAIMPLMULDIVU32 iemAImpl_idiv_u32, iemAImpl_idiv_u32_amd, iemAImpl_idiv_u32_intel;
1652
1653	typedef IEM_DECL_IMPL_TYPE(int, FNIEMAIMPLMULDIVU64,(uint64_t pu64RAX, uint64_t pu64RDX, uint64_t u64FactorDivisor, uint32_t *pEFlags));
1654	typedef FNIEMAIMPLMULDIVU64 *PFNIEMAIMPLMULDIVU64;
1655	FNIEMAIMPLMULDIVU64 iemAImpl_mul_u64, iemAImpl_mul_u64_amd, iemAImpl_mul_u64_intel;
1656	FNIEMAIMPLMULDIVU64 iemAImpl_imul_u64, iemAImpl_imul_u64_amd, iemAImpl_imul_u64_intel;
1657	FNIEMAIMPLMULDIVU64 iemAImpl_div_u64, iemAImpl_div_u64_amd, iemAImpl_div_u64_intel;
1658	FNIEMAIMPLMULDIVU64 iemAImpl_idiv_u64, iemAImpl_idiv_u64_amd, iemAImpl_idiv_u64_intel;
1659	/** @} */
1660
1661	/** @name Byte Swap.
1662	* @{ */
1663	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u16,(uint32_t pu32Dst)); / Yes, 32-bit register access. */
1664	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u32,(uint32_t *pu32Dst));
1665	IEM_DECL_IMPL_TYPE(void, iemAImpl_bswap_u64,(uint64_t *pu64Dst));
1666	/** @} */
1667
1668	/** @name Misc.
1669	* @{ */
1670	FNIEMAIMPLBINU16 iemAImpl_arpl;
1671	/** @} */
1672
1673	/** @name RDRAND and RDSEED
1674	* @{ */
1675	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU16,(uint16_t puDst, uint32_t pEFlags));
1676	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU32,(uint32_t puDst, uint32_t pEFlags));
1677	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLRDRANDSEEDU64,(uint64_t puDst, uint32_t pEFlags));
1678	typedef FNIEMAIMPLRDRANDSEEDU16 *FNIEMAIMPLPRDRANDSEEDU16;
1679	typedef FNIEMAIMPLRDRANDSEEDU32 *FNIEMAIMPLPRDRANDSEEDU32;
1680	typedef FNIEMAIMPLRDRANDSEEDU64 *FNIEMAIMPLPRDRANDSEEDU64;
1681
1682	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdrand_u16, iemAImpl_rdrand_u16_fallback;
1683	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdrand_u32, iemAImpl_rdrand_u32_fallback;
1684	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdrand_u64, iemAImpl_rdrand_u64_fallback;
1685	FNIEMAIMPLRDRANDSEEDU16 iemAImpl_rdseed_u16, iemAImpl_rdseed_u16_fallback;
1686	FNIEMAIMPLRDRANDSEEDU32 iemAImpl_rdseed_u32, iemAImpl_rdseed_u32_fallback;
1687	FNIEMAIMPLRDRANDSEEDU64 iemAImpl_rdseed_u64, iemAImpl_rdseed_u64_fallback;
1688	/** @} */
1689
1690	/** @name ADOX and ADCX
1691	* @{ */
1692	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU32,(uint32_t puDst, uint32_t pfEFlags, uint32_t uSrc));
1693	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLADXU64,(uint64_t puDst, uint32_t pfEFlags, uint64_t uSrc));
1694	typedef FNIEMAIMPLADXU32 *PFNIEMAIMPLADXU32;
1695	typedef FNIEMAIMPLADXU64 *PFNIEMAIMPLADXU64;
1696
1697	FNIEMAIMPLADXU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
1698	FNIEMAIMPLADXU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
1699	FNIEMAIMPLADXU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
1700	FNIEMAIMPLADXU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
1701	/** @} */
1702
1703	/** @name FPU operations taking a 32-bit float argument
1704	* @{ */
1705	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1706	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1707	typedef FNIEMAIMPLFPUR32FSW *PFNIEMAIMPLFPUR32FSW;
1708
1709	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1710	PCRTFLOAT80U pr80Val1, PCRTFLOAT32U pr32Val2));
1711	typedef FNIEMAIMPLFPUR32 *PFNIEMAIMPLFPUR32;
1712
1713	FNIEMAIMPLFPUR32FSW iemAImpl_fcom_r80_by_r32;
1714	FNIEMAIMPLFPUR32 iemAImpl_fadd_r80_by_r32;
1715	FNIEMAIMPLFPUR32 iemAImpl_fmul_r80_by_r32;
1716	FNIEMAIMPLFPUR32 iemAImpl_fsub_r80_by_r32;
1717	FNIEMAIMPLFPUR32 iemAImpl_fsubr_r80_by_r32;
1718	FNIEMAIMPLFPUR32 iemAImpl_fdiv_r80_by_r32;
1719	FNIEMAIMPLFPUR32 iemAImpl_fdivr_r80_by_r32;
1720
1721	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT32U pr32Val));
1722	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r32,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1723	PRTFLOAT32U pr32Val, PCRTFLOAT80U pr80Val));
1724	/** @} */
1725
1726	/** @name FPU operations taking a 64-bit float argument
1727	* @{ */
1728	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1729	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1730	typedef FNIEMAIMPLFPUR64FSW *PFNIEMAIMPLFPUR64FSW;
1731
1732	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1733	PCRTFLOAT80U pr80Val1, PCRTFLOAT64U pr64Val2));
1734	typedef FNIEMAIMPLFPUR64 *PFNIEMAIMPLFPUR64;
1735
1736	FNIEMAIMPLFPUR64FSW iemAImpl_fcom_r80_by_r64;
1737	FNIEMAIMPLFPUR64 iemAImpl_fadd_r80_by_r64;
1738	FNIEMAIMPLFPUR64 iemAImpl_fmul_r80_by_r64;
1739	FNIEMAIMPLFPUR64 iemAImpl_fsub_r80_by_r64;
1740	FNIEMAIMPLFPUR64 iemAImpl_fsubr_r80_by_r64;
1741	FNIEMAIMPLFPUR64 iemAImpl_fdiv_r80_by_r64;
1742	FNIEMAIMPLFPUR64 iemAImpl_fdivr_r80_by_r64;
1743
1744	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT64U pr64Val));
1745	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r64,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1746	PRTFLOAT64U pr32Val, PCRTFLOAT80U pr80Val));
1747	/** @} */
1748
1749	/** @name FPU operations taking a 80-bit float argument
1750	* @{ */
1751	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1752	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1753	typedef FNIEMAIMPLFPUR80 *PFNIEMAIMPLFPUR80;
1754	FNIEMAIMPLFPUR80 iemAImpl_fadd_r80_by_r80;
1755	FNIEMAIMPLFPUR80 iemAImpl_fmul_r80_by_r80;
1756	FNIEMAIMPLFPUR80 iemAImpl_fsub_r80_by_r80;
1757	FNIEMAIMPLFPUR80 iemAImpl_fsubr_r80_by_r80;
1758	FNIEMAIMPLFPUR80 iemAImpl_fdiv_r80_by_r80;
1759	FNIEMAIMPLFPUR80 iemAImpl_fdivr_r80_by_r80;
1760	FNIEMAIMPLFPUR80 iemAImpl_fprem_r80_by_r80;
1761	FNIEMAIMPLFPUR80 iemAImpl_fprem1_r80_by_r80;
1762	FNIEMAIMPLFPUR80 iemAImpl_fscale_r80_by_r80;
1763
1764	FNIEMAIMPLFPUR80 iemAImpl_fpatan_r80_by_r80, iemAImpl_fpatan_r80_by_r80_amd, iemAImpl_fpatan_r80_by_r80_intel;
1765	FNIEMAIMPLFPUR80 iemAImpl_fyl2x_r80_by_r80, iemAImpl_fyl2x_r80_by_r80_amd, iemAImpl_fyl2x_r80_by_r80_intel;
1766	FNIEMAIMPLFPUR80 iemAImpl_fyl2xp1_r80_by_r80, iemAImpl_fyl2xp1_r80_by_r80_amd, iemAImpl_fyl2xp1_r80_by_r80_intel;
1767
1768	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1769	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1770	typedef FNIEMAIMPLFPUR80FSW *PFNIEMAIMPLFPUR80FSW;
1771	FNIEMAIMPLFPUR80FSW iemAImpl_fcom_r80_by_r80;
1772	FNIEMAIMPLFPUR80FSW iemAImpl_fucom_r80_by_r80;
1773
1774	typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLFPUR80EFL,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw,
1775	PCRTFLOAT80U pr80Val1, PCRTFLOAT80U pr80Val2));
1776	typedef FNIEMAIMPLFPUR80EFL *PFNIEMAIMPLFPUR80EFL;
1777	FNIEMAIMPLFPUR80EFL iemAImpl_fcomi_r80_by_r80;
1778	FNIEMAIMPLFPUR80EFL iemAImpl_fucomi_r80_by_r80;
1779
1780	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARY,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1781	typedef FNIEMAIMPLFPUR80UNARY *PFNIEMAIMPLFPUR80UNARY;
1782	FNIEMAIMPLFPUR80UNARY iemAImpl_fabs_r80;
1783	FNIEMAIMPLFPUR80UNARY iemAImpl_fchs_r80;
1784	FNIEMAIMPLFPUR80UNARY iemAImpl_f2xm1_r80, iemAImpl_f2xm1_r80_amd, iemAImpl_f2xm1_r80_intel;
1785	FNIEMAIMPLFPUR80UNARY iemAImpl_fsqrt_r80;
1786	FNIEMAIMPLFPUR80UNARY iemAImpl_frndint_r80;
1787	FNIEMAIMPLFPUR80UNARY iemAImpl_fsin_r80, iemAImpl_fsin_r80_amd, iemAImpl_fsin_r80_intel;
1788	FNIEMAIMPLFPUR80UNARY iemAImpl_fcos_r80, iemAImpl_fcos_r80_amd, iemAImpl_fcos_r80_intel;
1789
1790	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYFSW,(PCX86FXSTATE pFpuState, uint16_t *pu16Fsw, PCRTFLOAT80U pr80Val));
1791	typedef FNIEMAIMPLFPUR80UNARYFSW *PFNIEMAIMPLFPUR80UNARYFSW;
1792	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_ftst_r80;
1793	FNIEMAIMPLFPUR80UNARYFSW iemAImpl_fxam_r80;
1794
1795	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80LDCONST,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes));
1796	typedef FNIEMAIMPLFPUR80LDCONST *PFNIEMAIMPLFPUR80LDCONST;
1797	FNIEMAIMPLFPUR80LDCONST iemAImpl_fld1;
1798	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2t;
1799	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldl2e;
1800	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldpi;
1801	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldlg2;
1802	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldln2;
1803	FNIEMAIMPLFPUR80LDCONST iemAImpl_fldz;
1804
1805	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUR80UNARYTWO,(PCX86FXSTATE pFpuState, PIEMFPURESULTTWO pFpuResTwo,
1806	PCRTFLOAT80U pr80Val));
1807	typedef FNIEMAIMPLFPUR80UNARYTWO *PFNIEMAIMPLFPUR80UNARYTWO;
1808	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fptan_r80_r80, iemAImpl_fptan_r80_r80_amd, iemAImpl_fptan_r80_r80_intel;
1809	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fxtract_r80_r80;
1810	FNIEMAIMPLFPUR80UNARYTWO iemAImpl_fsincos_r80_r80, iemAImpl_fsincos_r80_r80_amd, iemAImpl_fsincos_r80_r80_intel;
1811
1812	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_r80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTFLOAT80U pr80Val));
1813	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_r80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1814	PRTFLOAT80U pr80Dst, PCRTFLOAT80U pr80Src));
1815
1816	IEM_DECL_IMPL_DEF(void, iemAImpl_fld_r80_from_d80,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, PCRTPBCD80U pd80Val));
1817	IEM_DECL_IMPL_DEF(void, iemAImpl_fst_r80_to_d80,(PCX86FXSTATE pFpuState, uint16_t *pu16FSW,
1818	PRTPBCD80U pd80Dst, PCRTFLOAT80U pr80Src));
1819
1820	/** @} */
1821
1822	/** @name FPU operations taking a 16-bit signed integer argument
1823	* @{ */
1824	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1825	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1826	typedef FNIEMAIMPLFPUI16 *PFNIEMAIMPLFPUI16;
1827	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI16,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1828	int16_t *pi16Dst, PCRTFLOAT80U pr80Src));
1829	typedef FNIEMAIMPLFPUSTR80TOI16 *PFNIEMAIMPLFPUSTR80TOI16;
1830
1831	FNIEMAIMPLFPUI16 iemAImpl_fiadd_r80_by_i16;
1832	FNIEMAIMPLFPUI16 iemAImpl_fimul_r80_by_i16;
1833	FNIEMAIMPLFPUI16 iemAImpl_fisub_r80_by_i16;
1834	FNIEMAIMPLFPUI16 iemAImpl_fisubr_r80_by_i16;
1835	FNIEMAIMPLFPUI16 iemAImpl_fidiv_r80_by_i16;
1836	FNIEMAIMPLFPUI16 iemAImpl_fidivr_r80_by_i16;
1837
1838	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI16FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1839	PCRTFLOAT80U pr80Val1, int16_t const *pi16Val2));
1840	typedef FNIEMAIMPLFPUI16FSW *PFNIEMAIMPLFPUI16FSW;
1841	FNIEMAIMPLFPUI16FSW iemAImpl_ficom_r80_by_i16;
1842
1843	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i16,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int16_t const *pi16Val));
1844	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fist_r80_to_i16;
1845	FNIEMAIMPLFPUSTR80TOI16 iemAImpl_fistt_r80_to_i16, iemAImpl_fistt_r80_to_i16_amd, iemAImpl_fistt_r80_to_i16_intel;
1846	/** @} */
1847
1848	/** @name FPU operations taking a 32-bit signed integer argument
1849	* @{ */
1850	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes,
1851	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1852	typedef FNIEMAIMPLFPUI32 *PFNIEMAIMPLFPUI32;
1853	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI32,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1854	int32_t *pi32Dst, PCRTFLOAT80U pr80Src));
1855	typedef FNIEMAIMPLFPUSTR80TOI32 *PFNIEMAIMPLFPUSTR80TOI32;
1856
1857	FNIEMAIMPLFPUI32 iemAImpl_fiadd_r80_by_i32;
1858	FNIEMAIMPLFPUI32 iemAImpl_fimul_r80_by_i32;
1859	FNIEMAIMPLFPUI32 iemAImpl_fisub_r80_by_i32;
1860	FNIEMAIMPLFPUI32 iemAImpl_fisubr_r80_by_i32;
1861	FNIEMAIMPLFPUI32 iemAImpl_fidiv_r80_by_i32;
1862	FNIEMAIMPLFPUI32 iemAImpl_fidivr_r80_by_i32;
1863
1864	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUI32FSW,(PCX86FXSTATE pFpuState, uint16_t *pFSW,
1865	PCRTFLOAT80U pr80Val1, int32_t const *pi32Val2));
1866	typedef FNIEMAIMPLFPUI32FSW *PFNIEMAIMPLFPUI32FSW;
1867	FNIEMAIMPLFPUI32FSW iemAImpl_ficom_r80_by_i32;
1868
1869	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i32,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int32_t const *pi32Val));
1870	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fist_r80_to_i32;
1871	FNIEMAIMPLFPUSTR80TOI32 iemAImpl_fistt_r80_to_i32;
1872	/** @} */
1873
1874	/** @name FPU operations taking a 64-bit signed integer argument
1875	* @{ */
1876	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPUSTR80TOI64,(PCX86FXSTATE pFpuState, uint16_t *pFpuRes,
1877	int64_t *pi64Dst, PCRTFLOAT80U pr80Src));
1878	typedef FNIEMAIMPLFPUSTR80TOI64 *PFNIEMAIMPLFPUSTR80TOI64;
1879
1880	IEM_DECL_IMPL_DEF(void, iemAImpl_fild_r80_from_i64,(PCX86FXSTATE pFpuState, PIEMFPURESULT pFpuRes, int64_t const *pi64Val));
1881	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fist_r80_to_i64;
1882	FNIEMAIMPLFPUSTR80TOI64 iemAImpl_fistt_r80_to_i64;
1883	/** @} */
1884
1885
1886	/** Temporary type representing a 256-bit vector register. */
1887	typedef struct { uint64_t au64[4]; } IEMVMM256;
1888	/** Temporary type pointing to a 256-bit vector register. */
1889	typedef IEMVMM256 *PIEMVMM256;
1890	/** Temporary type pointing to a const 256-bit vector register. */
1891	typedef IEMVMM256 *PCIEMVMM256;
1892
1893
1894	/** @name Media (SSE/MMX/AVX) operations: full1 + full2 -> full1.
1895	* @{ */
1896	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U64,(PCX86FXSTATE pFpuState, uint64_t puDst, uint64_t const puSrc));
1897	typedef FNIEMAIMPLMEDIAF2U64 *PFNIEMAIMPLMEDIAF2U64;
1898	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF2U128,(PCX86FXSTATE pFpuState, PRTUINT128U puDst, PCRTUINT128U puSrc));
1899	typedef FNIEMAIMPLMEDIAF2U128 *PFNIEMAIMPLMEDIAF2U128;
1900	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U128,(PX86XSAVEAREA pExtState, PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1901	typedef FNIEMAIMPLMEDIAF3U128 *PFNIEMAIMPLMEDIAF3U128;
1902	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAF3U256,(PX86XSAVEAREA pExtState, PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1903	typedef FNIEMAIMPLMEDIAF3U256 *PFNIEMAIMPLMEDIAF3U256;
1904	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U64,(uint64_t puDst, uint64_t const puSrc));
1905	typedef FNIEMAIMPLMEDIAOPTF2U64 *PFNIEMAIMPLMEDIAOPTF2U64;
1906	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128,(PRTUINT128U puDst, PCRTUINT128U puSrc));
1907	typedef FNIEMAIMPLMEDIAOPTF2U128 *PFNIEMAIMPLMEDIAOPTF2U128;
1908	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2));
1909	typedef FNIEMAIMPLMEDIAOPTF3U128 *PFNIEMAIMPLMEDIAOPTF3U128;
1910	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2));
1911	typedef FNIEMAIMPLMEDIAOPTF3U256 *PFNIEMAIMPLMEDIAOPTF3U256;
1912	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U256,(PRTUINT256U puDst, PCRTUINT256U puSrc));
1913	typedef FNIEMAIMPLMEDIAOPTF2U256 *PFNIEMAIMPLMEDIAOPTF2U256;
1914	FNIEMAIMPLMEDIAF2U64 iemAImpl_pshufb_u64, iemAImpl_pshufb_u64_fallback;
1915	FNIEMAIMPLMEDIAF2U64 iemAImpl_pand_u64, iemAImpl_pandn_u64, iemAImpl_por_u64, iemAImpl_pxor_u64;
1916	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpeqb_u64, iemAImpl_pcmpeqw_u64, iemAImpl_pcmpeqd_u64;
1917	FNIEMAIMPLMEDIAF2U64 iemAImpl_pcmpgtb_u64, iemAImpl_pcmpgtw_u64, iemAImpl_pcmpgtd_u64;
1918	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddb_u64, iemAImpl_paddsb_u64, iemAImpl_paddusb_u64;
1919	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddw_u64, iemAImpl_paddsw_u64, iemAImpl_paddusw_u64;
1920	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddd_u64;
1921	FNIEMAIMPLMEDIAF2U64 iemAImpl_paddq_u64;
1922	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubb_u64, iemAImpl_psubsb_u64, iemAImpl_psubusb_u64;
1923	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubw_u64, iemAImpl_psubsw_u64, iemAImpl_psubusw_u64;
1924	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubd_u64;
1925	FNIEMAIMPLMEDIAF2U64 iemAImpl_psubq_u64;
1926	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddwd_u64;
1927	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmullw_u64, iemAImpl_pmulhw_u64;
1928	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminub_u64, iemAImpl_pmaxub_u64;
1929	FNIEMAIMPLMEDIAF2U64 iemAImpl_pminsw_u64, iemAImpl_pmaxsw_u64;
1930	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsb_u64, iemAImpl_pabsb_u64_fallback;
1931	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsw_u64, iemAImpl_pabsw_u64_fallback;
1932	FNIEMAIMPLMEDIAF2U64 iemAImpl_pabsd_u64, iemAImpl_pabsd_u64_fallback;
1933	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignb_u64, iemAImpl_psignb_u64_fallback;
1934	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignw_u64, iemAImpl_psignw_u64_fallback;
1935	FNIEMAIMPLMEDIAF2U64 iemAImpl_psignd_u64, iemAImpl_psignd_u64_fallback;
1936	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddw_u64, iemAImpl_phaddw_u64_fallback;
1937	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddd_u64, iemAImpl_phaddd_u64_fallback;
1938	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubw_u64, iemAImpl_phsubw_u64_fallback;
1939	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubd_u64, iemAImpl_phsubd_u64_fallback;
1940	FNIEMAIMPLMEDIAF2U64 iemAImpl_phaddsw_u64, iemAImpl_phaddsw_u64_fallback;
1941	FNIEMAIMPLMEDIAF2U64 iemAImpl_phsubsw_u64, iemAImpl_phsubsw_u64_fallback;
1942	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmaddubsw_u64, iemAImpl_pmaddubsw_u64_fallback;
1943	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmulhrsw_u64, iemAImpl_pmulhrsw_u64_fallback;
1944	FNIEMAIMPLMEDIAF2U64 iemAImpl_pmuludq_u64;
1945	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllw_u64, iemAImpl_psrlw_u64, iemAImpl_psraw_u64;
1946	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pslld_u64, iemAImpl_psrld_u64, iemAImpl_psrad_u64;
1947	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psllq_u64, iemAImpl_psrlq_u64;
1948	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packsswb_u64, iemAImpl_packuswb_u64;
1949	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_packssdw_u64;
1950	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pmulhuw_u64;
1951	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_pavgb_u64, iemAImpl_pavgw_u64;
1952	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_psadbw_u64;
1953
1954	FNIEMAIMPLMEDIAF2U128 iemAImpl_pshufb_u128, iemAImpl_pshufb_u128_fallback;
1955	FNIEMAIMPLMEDIAF2U128 iemAImpl_pand_u128, iemAImpl_pandn_u128, iemAImpl_por_u128, iemAImpl_pxor_u128;
1956	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqb_u128, iemAImpl_pcmpeqw_u128, iemAImpl_pcmpeqd_u128;
1957	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpeqq_u128, iemAImpl_pcmpeqq_u128_fallback;
1958	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtb_u128, iemAImpl_pcmpgtw_u128, iemAImpl_pcmpgtd_u128;
1959	FNIEMAIMPLMEDIAF2U128 iemAImpl_pcmpgtq_u128, iemAImpl_pcmpgtq_u128_fallback;
1960	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddb_u128, iemAImpl_paddsb_u128, iemAImpl_paddusb_u128;
1961	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddw_u128, iemAImpl_paddsw_u128, iemAImpl_paddusw_u128;
1962	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddd_u128;
1963	FNIEMAIMPLMEDIAF2U128 iemAImpl_paddq_u128;
1964	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubb_u128, iemAImpl_psubsb_u128, iemAImpl_psubusb_u128;
1965	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubw_u128, iemAImpl_psubsw_u128, iemAImpl_psubusw_u128;
1966	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubd_u128;
1967	FNIEMAIMPLMEDIAF2U128 iemAImpl_psubq_u128;
1968	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmullw_u128, iemAImpl_pmullw_u128_fallback;
1969	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhw_u128;
1970	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulld_u128, iemAImpl_pmulld_u128_fallback;
1971	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddwd_u128;
1972	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminub_u128;
1973	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminud_u128, iemAImpl_pminud_u128_fallback;
1974	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminuw_u128, iemAImpl_pminuw_u128_fallback;
1975	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsb_u128, iemAImpl_pminsb_u128_fallback;
1976	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsd_u128, iemAImpl_pminsd_u128_fallback;
1977	FNIEMAIMPLMEDIAF2U128 iemAImpl_pminsw_u128, iemAImpl_pminsw_u128_fallback;
1978	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxub_u128;
1979	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxud_u128, iemAImpl_pmaxud_u128_fallback;
1980	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxuw_u128, iemAImpl_pmaxuw_u128_fallback;
1981	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsb_u128, iemAImpl_pmaxsb_u128_fallback;
1982	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsw_u128;
1983	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaxsd_u128, iemAImpl_pmaxsd_u128_fallback;
1984	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsb_u128, iemAImpl_pabsb_u128_fallback;
1985	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsw_u128, iemAImpl_pabsw_u128_fallback;
1986	FNIEMAIMPLMEDIAF2U128 iemAImpl_pabsd_u128, iemAImpl_pabsd_u128_fallback;
1987	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignb_u128, iemAImpl_psignb_u128_fallback;
1988	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignw_u128, iemAImpl_psignw_u128_fallback;
1989	FNIEMAIMPLMEDIAF2U128 iemAImpl_psignd_u128, iemAImpl_psignd_u128_fallback;
1990	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddw_u128, iemAImpl_phaddw_u128_fallback;
1991	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddd_u128, iemAImpl_phaddd_u128_fallback;
1992	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubw_u128, iemAImpl_phsubw_u128_fallback;
1993	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubd_u128, iemAImpl_phsubd_u128_fallback;
1994	FNIEMAIMPLMEDIAF2U128 iemAImpl_phaddsw_u128, iemAImpl_phaddsw_u128_fallback;
1995	FNIEMAIMPLMEDIAF2U128 iemAImpl_phsubsw_u128, iemAImpl_phsubsw_u128_fallback;
1996	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmaddubsw_u128, iemAImpl_pmaddubsw_u128_fallback;
1997	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmulhrsw_u128, iemAImpl_pmulhrsw_u128_fallback;
1998	FNIEMAIMPLMEDIAF2U128 iemAImpl_pmuludq_u128;
1999	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packsswb_u128, iemAImpl_packuswb_u128;
2000	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_packssdw_u128, iemAImpl_packusdw_u128;
2001	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllw_u128, iemAImpl_psrlw_u128, iemAImpl_psraw_u128;
2002	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pslld_u128, iemAImpl_psrld_u128, iemAImpl_psrad_u128;
2003	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psllq_u128, iemAImpl_psrlq_u128;
2004	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmulhuw_u128;
2005	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pavgb_u128, iemAImpl_pavgw_u128;
2006	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_psadbw_u128;
2007	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_pmuldq_u128, iemAImpl_pmuldq_u128_fallback;
2008	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpcklps_u128, iemAImpl_unpcklpd_u128;
2009	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_unpckhps_u128, iemAImpl_unpckhpd_u128;
2010	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_phminposuw_u128, iemAImpl_phminposuw_u128_fallback;
2011
2012	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpshufb_u128, iemAImpl_vpshufb_u128_fallback;
2013	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpand_u128, iemAImpl_vpand_u128_fallback;
2014	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpandn_u128, iemAImpl_vpandn_u128_fallback;
2015	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpor_u128, iemAImpl_vpor_u128_fallback;
2016	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpxor_u128, iemAImpl_vpxor_u128_fallback;
2017	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqb_u128, iemAImpl_vpcmpeqb_u128_fallback;
2018	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqw_u128, iemAImpl_vpcmpeqw_u128_fallback;
2019	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqd_u128, iemAImpl_vpcmpeqd_u128_fallback;
2020	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpeqq_u128, iemAImpl_vpcmpeqq_u128_fallback;
2021	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtb_u128, iemAImpl_vpcmpgtb_u128_fallback;
2022	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtw_u128, iemAImpl_vpcmpgtw_u128_fallback;
2023	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtd_u128, iemAImpl_vpcmpgtd_u128_fallback;
2024	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpcmpgtq_u128, iemAImpl_vpcmpgtq_u128_fallback;
2025	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddb_u128, iemAImpl_vpaddb_u128_fallback;
2026	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddw_u128, iemAImpl_vpaddw_u128_fallback;
2027	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddd_u128, iemAImpl_vpaddd_u128_fallback;
2028	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpaddq_u128, iemAImpl_vpaddq_u128_fallback;
2029	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubb_u128, iemAImpl_vpsubb_u128_fallback;
2030	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubw_u128, iemAImpl_vpsubw_u128_fallback;
2031	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubd_u128, iemAImpl_vpsubd_u128_fallback;
2032	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpsubq_u128, iemAImpl_vpsubq_u128_fallback;
2033	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminub_u128, iemAImpl_vpminub_u128_fallback;
2034	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminuw_u128, iemAImpl_vpminuw_u128_fallback;
2035	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminud_u128, iemAImpl_vpminud_u128_fallback;
2036	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsb_u128, iemAImpl_vpminsb_u128_fallback;
2037	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsw_u128, iemAImpl_vpminsw_u128_fallback;
2038	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpminsd_u128, iemAImpl_vpminsd_u128_fallback;
2039	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxub_u128, iemAImpl_vpmaxub_u128_fallback;
2040	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxuw_u128, iemAImpl_vpmaxuw_u128_fallback;
2041	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxud_u128, iemAImpl_vpmaxud_u128_fallback;
2042	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsb_u128, iemAImpl_vpmaxsb_u128_fallback;
2043	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsw_u128, iemAImpl_vpmaxsw_u128_fallback;
2044	FNIEMAIMPLMEDIAF3U128 iemAImpl_vpmaxsd_u128, iemAImpl_vpmaxsd_u128_fallback;
2045	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpacksswb_u128, iemAImpl_vpacksswb_u128_fallback;
2046	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackssdw_u128, iemAImpl_vpackssdw_u128_fallback;
2047	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackuswb_u128, iemAImpl_vpackuswb_u128_fallback;
2048	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpackusdw_u128, iemAImpl_vpackusdw_u128_fallback;
2049	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmullw_u128, iemAImpl_vpmullw_u128_fallback;
2050	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulld_u128, iemAImpl_vpmulld_u128_fallback;
2051	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhw_u128, iemAImpl_vpmulhw_u128_fallback;
2052	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhuw_u128, iemAImpl_vpmulhuw_u128_fallback;
2053	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgb_u128, iemAImpl_vpavgb_u128_fallback;
2054	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpavgw_u128, iemAImpl_vpavgw_u128_fallback;
2055	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignb_u128, iemAImpl_vpsignb_u128_fallback;
2056	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignw_u128, iemAImpl_vpsignw_u128_fallback;
2057	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsignd_u128, iemAImpl_vpsignd_u128_fallback;
2058	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddw_u128, iemAImpl_vphaddw_u128_fallback;
2059	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddd_u128, iemAImpl_vphaddd_u128_fallback;
2060	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubw_u128, iemAImpl_vphsubw_u128_fallback;
2061	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubd_u128, iemAImpl_vphsubd_u128_fallback;
2062	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphaddsw_u128, iemAImpl_vphaddsw_u128_fallback;
2063	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vphsubsw_u128, iemAImpl_vphsubsw_u128_fallback;
2064	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmaddubsw_u128, iemAImpl_vpmaddubsw_u128_fallback;
2065	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmulhrsw_u128, iemAImpl_vpmulhrsw_u128_fallback;
2066	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpsadbw_u128, iemAImpl_vpsadbw_u128_fallback;
2067	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuldq_u128, iemAImpl_vpmuldq_u128_fallback;
2068	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpmuludq_u128, iemAImpl_vpmuludq_u128_fallback;
2069
2070	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsb_u128, iemAImpl_vpabsb_u128_fallback;
2071	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsw_u128, iemAImpl_vpabsd_u128_fallback;
2072	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vpabsd_u128, iemAImpl_vpabsw_u128_fallback;
2073	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vphminposuw_u128, iemAImpl_vphminposuw_u128_fallback;
2074
2075	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpshufb_u256, iemAImpl_vpshufb_u256_fallback;
2076	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpand_u256, iemAImpl_vpand_u256_fallback;
2077	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpandn_u256, iemAImpl_vpandn_u256_fallback;
2078	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpor_u256, iemAImpl_vpor_u256_fallback;
2079	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpxor_u256, iemAImpl_vpxor_u256_fallback;
2080	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqb_u256, iemAImpl_vpcmpeqb_u256_fallback;
2081	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqw_u256, iemAImpl_vpcmpeqw_u256_fallback;
2082	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqd_u256, iemAImpl_vpcmpeqd_u256_fallback;
2083	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpeqq_u256, iemAImpl_vpcmpeqq_u256_fallback;
2084	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtb_u256, iemAImpl_vpcmpgtb_u256_fallback;
2085	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtw_u256, iemAImpl_vpcmpgtw_u256_fallback;
2086	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtd_u256, iemAImpl_vpcmpgtd_u256_fallback;
2087	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpcmpgtq_u256, iemAImpl_vpcmpgtq_u256_fallback;
2088	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddb_u256, iemAImpl_vpaddb_u256_fallback;
2089	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddw_u256, iemAImpl_vpaddw_u256_fallback;
2090	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddd_u256, iemAImpl_vpaddd_u256_fallback;
2091	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpaddq_u256, iemAImpl_vpaddq_u256_fallback;
2092	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubb_u256, iemAImpl_vpsubb_u256_fallback;
2093	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubw_u256, iemAImpl_vpsubw_u256_fallback;
2094	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubd_u256, iemAImpl_vpsubd_u256_fallback;
2095	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpsubq_u256, iemAImpl_vpsubq_u256_fallback;
2096	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminub_u256, iemAImpl_vpminub_u256_fallback;
2097	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminuw_u256, iemAImpl_vpminuw_u256_fallback;
2098	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminud_u256, iemAImpl_vpminud_u256_fallback;
2099	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsb_u256, iemAImpl_vpminsb_u256_fallback;
2100	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsw_u256, iemAImpl_vpminsw_u256_fallback;
2101	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpminsd_u256, iemAImpl_vpminsd_u256_fallback;
2102	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxub_u256, iemAImpl_vpmaxub_u256_fallback;
2103	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxuw_u256, iemAImpl_vpmaxuw_u256_fallback;
2104	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxud_u256, iemAImpl_vpmaxud_u256_fallback;
2105	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsb_u256, iemAImpl_vpmaxsb_u256_fallback;
2106	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsw_u256, iemAImpl_vpmaxsw_u256_fallback;
2107	FNIEMAIMPLMEDIAF3U256 iemAImpl_vpmaxsd_u256, iemAImpl_vpmaxsd_u256_fallback;
2108	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpacksswb_u256, iemAImpl_vpacksswb_u256_fallback;
2109	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackssdw_u256, iemAImpl_vpackssdw_u256_fallback;
2110	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackuswb_u256, iemAImpl_vpackuswb_u256_fallback;
2111	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpackusdw_u256, iemAImpl_vpackusdw_u256_fallback;
2112	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmullw_u256, iemAImpl_vpmullw_u256_fallback;
2113	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulld_u256, iemAImpl_vpmulld_u256_fallback;
2114	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhw_u256, iemAImpl_vpmulhw_u256_fallback;
2115	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhuw_u256, iemAImpl_vpmulhuw_u256_fallback;
2116	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgb_u256, iemAImpl_vpavgb_u256_fallback;
2117	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpavgw_u256, iemAImpl_vpavgw_u256_fallback;
2118	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignb_u256, iemAImpl_vpsignb_u256_fallback;
2119	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignw_u256, iemAImpl_vpsignw_u256_fallback;
2120	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsignd_u256, iemAImpl_vpsignd_u256_fallback;
2121	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddw_u256, iemAImpl_vphaddw_u256_fallback;
2122	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddd_u256, iemAImpl_vphaddd_u256_fallback;
2123	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubw_u256, iemAImpl_vphsubw_u256_fallback;
2124	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubd_u256, iemAImpl_vphsubd_u256_fallback;
2125	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphaddsw_u256, iemAImpl_vphaddsw_u256_fallback;
2126	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vphsubsw_u256, iemAImpl_vphsubsw_u256_fallback;
2127	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmaddubsw_u256, iemAImpl_vpmaddubsw_u256_fallback;
2128	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmulhrsw_u256, iemAImpl_vpmulhrsw_u256_fallback;
2129	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpsadbw_u256, iemAImpl_vpsadbw_u256_fallback;
2130	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuldq_u256, iemAImpl_vpmuldq_u256_fallback;
2131	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpmuludq_u256, iemAImpl_vpmuludq_u256_fallback;
2132
2133	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsb_u256, iemAImpl_vpabsb_u256_fallback;
2134	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsw_u256, iemAImpl_vpabsw_u256_fallback;
2135	FNIEMAIMPLMEDIAOPTF2U256 iemAImpl_vpabsd_u256, iemAImpl_vpabsd_u256_fallback;
2136	/** @} */
2137
2138	/** @name Media (SSE/MMX/AVX) operations: lowhalf1 + lowhalf1 -> full1.
2139	* @{ */
2140	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpcklbw_u64, iemAImpl_punpcklwd_u64, iemAImpl_punpckldq_u64;
2141	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpcklbw_u128, iemAImpl_punpcklwd_u128, iemAImpl_punpckldq_u128, iemAImpl_punpcklqdq_u128;
2142	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpcklbw_u128, iemAImpl_vpunpcklbw_u128_fallback,
2143	iemAImpl_vpunpcklwd_u128, iemAImpl_vpunpcklwd_u128_fallback,
2144	iemAImpl_vpunpckldq_u128, iemAImpl_vpunpckldq_u128_fallback,
2145	iemAImpl_vpunpcklqdq_u128, iemAImpl_vpunpcklqdq_u128_fallback,
2146	iemAImpl_vunpcklps_u128, iemAImpl_vunpcklps_u128_fallback,
2147	iemAImpl_vunpcklpd_u128, iemAImpl_vunpcklpd_u128_fallback,
2148	iemAImpl_vunpckhps_u128, iemAImpl_vunpckhps_u128_fallback,
2149	iemAImpl_vunpckhpd_u128, iemAImpl_vunpckhpd_u128_fallback;
2150
2151	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpcklbw_u256, iemAImpl_vpunpcklbw_u256_fallback,
2152	iemAImpl_vpunpcklwd_u256, iemAImpl_vpunpcklwd_u256_fallback,
2153	iemAImpl_vpunpckldq_u256, iemAImpl_vpunpckldq_u256_fallback,
2154	iemAImpl_vpunpcklqdq_u256, iemAImpl_vpunpcklqdq_u256_fallback,
2155	iemAImpl_vunpcklps_u256, iemAImpl_vunpcklps_u256_fallback,
2156	iemAImpl_vunpcklpd_u256, iemAImpl_vunpcklpd_u256_fallback,
2157	iemAImpl_vunpckhps_u256, iemAImpl_vunpckhps_u256_fallback,
2158	iemAImpl_vunpckhpd_u256, iemAImpl_vunpckhpd_u256_fallback;
2159	/** @} */
2160
2161	/** @name Media (SSE/MMX/AVX) operations: hihalf1 + hihalf2 -> full1.
2162	* @{ */
2163	FNIEMAIMPLMEDIAOPTF2U64 iemAImpl_punpckhbw_u64, iemAImpl_punpckhwd_u64, iemAImpl_punpckhdq_u64;
2164	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_punpckhbw_u128, iemAImpl_punpckhwd_u128, iemAImpl_punpckhdq_u128, iemAImpl_punpckhqdq_u128;
2165	FNIEMAIMPLMEDIAOPTF3U128 iemAImpl_vpunpckhbw_u128, iemAImpl_vpunpckhbw_u128_fallback,
2166	iemAImpl_vpunpckhwd_u128, iemAImpl_vpunpckhwd_u128_fallback,
2167	iemAImpl_vpunpckhdq_u128, iemAImpl_vpunpckhdq_u128_fallback,
2168	iemAImpl_vpunpckhqdq_u128, iemAImpl_vpunpckhqdq_u128_fallback;
2169	FNIEMAIMPLMEDIAOPTF3U256 iemAImpl_vpunpckhbw_u256, iemAImpl_vpunpckhbw_u256_fallback,
2170	iemAImpl_vpunpckhwd_u256, iemAImpl_vpunpckhwd_u256_fallback,
2171	iemAImpl_vpunpckhdq_u256, iemAImpl_vpunpckhdq_u256_fallback,
2172	iemAImpl_vpunpckhqdq_u256, iemAImpl_vpunpckhqdq_u256_fallback;
2173	/** @} */
2174
2175	/** @name Media (SSE/MMX/AVX) operation: Packed Shuffle Stuff (evil)
2176	* @{ */
2177	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2178	typedef FNIEMAIMPLMEDIAPSHUFU128 *PFNIEMAIMPLMEDIAPSHUFU128;
2179	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHUFU256,(PRTUINT256U puDst, PCRTUINT256U puSrc, uint8_t bEvil));
2180	typedef FNIEMAIMPLMEDIAPSHUFU256 *PFNIEMAIMPLMEDIAPSHUFU256;
2181	IEM_DECL_IMPL_DEF(void, iemAImpl_pshufw_u64,(uint64_t puDst, uint64_t const puSrc, uint8_t bEvil));
2182	FNIEMAIMPLMEDIAPSHUFU128 iemAImpl_pshufhw_u128, iemAImpl_pshuflw_u128, iemAImpl_pshufd_u128;
2183	#ifndef IEM_WITHOUT_ASSEMBLY
2184	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256, iemAImpl_vpshuflw_u256, iemAImpl_vpshufd_u256;
2185	#endif
2186	FNIEMAIMPLMEDIAPSHUFU256 iemAImpl_vpshufhw_u256_fallback, iemAImpl_vpshuflw_u256_fallback, iemAImpl_vpshufd_u256_fallback;
2187	/** @} */
2188
2189	/** @name Media (SSE/MMX/AVX) operation: Shift Immediate Stuff (evil)
2190	* @{ */
2191	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU64,(uint64_t *puDst, uint8_t bShift));
2192	typedef FNIEMAIMPLMEDIAPSHIFTU64 *PFNIEMAIMPLMEDIAPSHIFTU64;
2193	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU128,(PRTUINT128U puDst, uint8_t bShift));
2194	typedef FNIEMAIMPLMEDIAPSHIFTU128 *PFNIEMAIMPLMEDIAPSHIFTU128;
2195	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAPSHIFTU256,(PRTUINT256U puDst, uint8_t bShift));
2196	typedef FNIEMAIMPLMEDIAPSHIFTU256 *PFNIEMAIMPLMEDIAPSHIFTU256;
2197	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psllw_imm_u64, iemAImpl_pslld_imm_u64, iemAImpl_psllq_imm_u64;
2198	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psrlw_imm_u64, iemAImpl_psrld_imm_u64, iemAImpl_psrlq_imm_u64;
2199	FNIEMAIMPLMEDIAPSHIFTU64 iemAImpl_psraw_imm_u64, iemAImpl_psrad_imm_u64;
2200	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psllw_imm_u128, iemAImpl_pslld_imm_u128, iemAImpl_psllq_imm_u128;
2201	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psrlw_imm_u128, iemAImpl_psrld_imm_u128, iemAImpl_psrlq_imm_u128;
2202	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_psraw_imm_u128, iemAImpl_psrad_imm_u128;
2203	FNIEMAIMPLMEDIAPSHIFTU128 iemAImpl_pslldq_imm_u128, iemAImpl_psrldq_imm_u128;
2204	/** @} */
2205
2206	/** @name Media (SSE/MMX/AVX) operation: Move Byte Mask
2207	* @{ */
2208	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u64,(uint64_t pu64Dst, uint64_t const puSrc));
2209	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovmskb_u128,(uint64_t *pu64Dst, PCRTUINT128U puSrc));
2210	#ifndef IEM_WITHOUT_ASSEMBLY
2211	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2212	#endif
2213	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovmskb_u256_fallback,(uint64_t *pu64Dst, PCRTUINT256U puSrc));
2214	/** @} */
2215
2216	/** @name Media (SSE/MMX/AVX) operations: Variable Blend Packed Bytes/R32/R64.
2217	* @{ */
2218	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puMask));
2219	typedef FNIEMAIMPLBLENDU128 *PFNIEMAIMPLBLENDU128;
2220	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, PCRTUINT128U puMask));
2221	typedef FNIEMAIMPLAVXBLENDU128 *PFNIEMAIMPLAVXBLENDU128;
2222	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLAVXBLENDU256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, PCRTUINT256U puMask));
2223	typedef FNIEMAIMPLAVXBLENDU256 *PFNIEMAIMPLAVXBLENDU256;
2224
2225	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128;
2226	FNIEMAIMPLBLENDU128 iemAImpl_pblendvb_u128_fallback;
2227	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128;
2228	FNIEMAIMPLAVXBLENDU128 iemAImpl_vpblendvb_u128_fallback;
2229	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256;
2230	FNIEMAIMPLAVXBLENDU256 iemAImpl_vpblendvb_u256_fallback;
2231
2232	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128;
2233	FNIEMAIMPLBLENDU128 iemAImpl_blendvps_u128_fallback;
2234	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128;
2235	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvps_u128_fallback;
2236	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256;
2237	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvps_u256_fallback;
2238
2239	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128;
2240	FNIEMAIMPLBLENDU128 iemAImpl_blendvpd_u128_fallback;
2241	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128;
2242	FNIEMAIMPLAVXBLENDU128 iemAImpl_vblendvpd_u128_fallback;
2243	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256;
2244	FNIEMAIMPLAVXBLENDU256 iemAImpl_vblendvpd_u256_fallback;
2245	/** @} */
2246
2247
2248	/** @name Media (SSE/MMX/AVX) operation: Sort this later
2249	* @{ */
2250	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2251	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovsldup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2252	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2253	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovshdup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2254	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rr,(PX86XSAVEAREA pXState, uint8_t iYRegDst, uint8_t iYRegSrc));
2255	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovddup_256_rm,(PX86XSAVEAREA pXState, uint8_t iYRegDst, PCRTUINT256U pSrc));
2256
2257	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2258	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2259	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2260	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2261	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2262
2263	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2264	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2265	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2266	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2267	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2268
2269	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2270	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2271	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2272	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2273	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2274
2275	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2276	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2277	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2278	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2279	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2280
2281	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2282	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2283	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2284	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2285	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2286
2287	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2288	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2289	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2290	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2291	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovsxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2292
2293	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2294	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128,(PRTUINT128U puDst, uint64_t uSrc));
2295	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2296	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2297	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbw_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2298
2299	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2300	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128,(PRTUINT128U puDst, uint32_t uSrc));
2301	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2302	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2303	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2304
2305	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2306	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128,(PRTUINT128U puDst, uint16_t uSrc));
2307	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u128_fallback,(PRTUINT128U puDst, uint16_t uSrc));
2308	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2309	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxbq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2310
2311	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2312	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128,(PRTUINT128U puDst, uint64_t uSrc));
2313	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2314	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2315	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwd_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2316
2317	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2318	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128,(PRTUINT128U puDst, uint32_t uSrc));
2319	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u128_fallback,(PRTUINT128U puDst, uint32_t uSrc));
2320	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2321	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxwq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2322
2323	IEM_DECL_IMPL_DEF(void, iemAImpl_pmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2324	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128,(PRTUINT128U puDst, uint64_t uSrc));
2325	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u128_fallback,(PRTUINT128U puDst, uint64_t uSrc));
2326	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2327	IEM_DECL_IMPL_DEF(void, iemAImpl_vpmovzxdq_u256_fallback,(PRTUINT256U puDst, PCRTUINT128U puSrc));
2328
2329	IEM_DECL_IMPL_DEF(void, iemAImpl_shufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2330	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2331	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2332	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2333	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufpd_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2334
2335	IEM_DECL_IMPL_DEF(void, iemAImpl_shufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2336	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2337	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2338	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2339	IEM_DECL_IMPL_DEF(void, iemAImpl_vshufps_u256_fallback,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2340
2341	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2342	IEM_DECL_IMPL_DEF(void, iemAImpl_palignr_u64_fallback,(uint64_t *pu64Dst, uint64_t u64Src, uint8_t bEvil));
2343
2344	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u64,(uint64_t *pu64Dst, uint16_t u16Src, uint8_t bEvil));
2345	IEM_DECL_IMPL_DEF(void, iemAImpl_pinsrw_u128,(PRTUINT128U puDst, uint16_t u16Src, uint8_t bEvil));
2346	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2347	IEM_DECL_IMPL_DEF(void, iemAImpl_vpinsrw_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint16_t u16Src, uint8_t bEvil));
2348
2349	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u64,(uint16_t *pu16Dst, uint64_t u64Src, uint8_t bEvil));
2350	IEM_DECL_IMPL_DEF(void, iemAImpl_pextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2351	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2352	IEM_DECL_IMPL_DEF(void, iemAImpl_vpextrw_u128_fallback,(uint16_t *pu16Dst, PCRTUINT128U puSrc, uint8_t bEvil));
2353
2354	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2355	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2356	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2357	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2358	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskps_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2359
2360	IEM_DECL_IMPL_DEF(void, iemAImpl_movmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2361	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2362	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u128_fallback,(uint8_t *pu8Dst, PCRTUINT128U puSrc));
2363	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2364	IEM_DECL_IMPL_DEF(void, iemAImpl_vmovmskpd_u256_fallback,(uint8_t *pu8Dst, PCRTUINT256U puSrc));
2365
2366
2367	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF2U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc, uint8_t bEvil));
2368	typedef FNIEMAIMPLMEDIAOPTF2U128IMM8 *PFNIEMAIMPLMEDIAOPTF2U128IMM8;
2369	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U128IMM8,(PRTUINT128U puDst, PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint8_t bEvil));
2370	typedef FNIEMAIMPLMEDIAOPTF3U128IMM8 *PFNIEMAIMPLMEDIAOPTF3U128IMM8;
2371	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMEDIAOPTF3U256IMM8,(PRTUINT256U puDst, PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint8_t bEvil));
2372	typedef FNIEMAIMPLMEDIAOPTF3U256IMM8 *PFNIEMAIMPLMEDIAOPTF3U256IMM8;
2373
2374	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_palignr_u128, iemAImpl_palignr_u128_fallback;
2375	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pblendw_u128, iemAImpl_pblendw_u128_fallback;
2376	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendps_u128, iemAImpl_blendps_u128_fallback;
2377	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_blendpd_u128, iemAImpl_blendpd_u128_fallback;
2378
2379	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpalignr_u128, iemAImpl_vpalignr_u128_fallback;
2380	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpblendw_u128, iemAImpl_vpblendw_u128_fallback;
2381	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendps_u128, iemAImpl_vblendps_u128_fallback;
2382	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vblendpd_u128, iemAImpl_vblendpd_u128_fallback;
2383
2384	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpalignr_u256, iemAImpl_vpalignr_u256_fallback;
2385	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vpblendw_u256, iemAImpl_vpblendw_u256_fallback;
2386	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendps_u256, iemAImpl_vblendps_u256_fallback;
2387	FNIEMAIMPLMEDIAOPTF3U256IMM8 iemAImpl_vblendpd_u256, iemAImpl_vblendpd_u256_fallback;
2388
2389	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesimc_u128, iemAImpl_aesimc_u128_fallback;
2390	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenc_u128, iemAImpl_aesenc_u128_fallback;
2391	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesenclast_u128, iemAImpl_aesenclast_u128_fallback;
2392	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdec_u128, iemAImpl_aesdec_u128_fallback;
2393	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_aesdeclast_u128, iemAImpl_aesdeclast_u128_fallback;
2394
2395	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback;
2396	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenc_u128, iemAImpl_vaesenc_u128_fallback;
2397	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesenclast_u128, iemAImpl_vaesenclast_u128_fallback;
2398	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdec_u128, iemAImpl_vaesdec_u128_fallback;
2399	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_vaesdeclast_u128, iemAImpl_vaesdeclast_u128_fallback;
2400
2401	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_aeskeygenassist_u128, iemAImpl_aeskeygenassist_u128_fallback;
2402
2403	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback;
2404
2405	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1nexte_u128, iemAImpl_sha1nexte_u128_fallback;
2406	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg1_u128, iemAImpl_sha1msg1_u128_fallback;
2407	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha1msg2_u128, iemAImpl_sha1msg2_u128_fallback;
2408	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg1_u128, iemAImpl_sha256msg1_u128_fallback;
2409	FNIEMAIMPLMEDIAOPTF2U128 iemAImpl_sha256msg2_u128, iemAImpl_sha256msg2_u128_fallback;
2410	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_sha1rnds4_u128, iemAImpl_sha1rnds4_u128_fallback;
2411	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2412	IEM_DECL_IMPL_DEF(void, iemAImpl_sha256rnds2_u128_fallback,(PRTUINT128U puDst, PCRTUINT128U puSrc, PCRTUINT128U puXmm0Constants));
2413
2414	typedef struct IEMPCMPISTRXSRC
2415	{
2416	RTUINT128U uSrc1;
2417	RTUINT128U uSrc2;
2418	} IEMPCMPISTRXSRC;
2419	typedef IEMPCMPISTRXSRC *PIEMPCMPISTRXSRC;
2420	typedef const IEMPCMPISTRXSRC *PCIEMPCMPISTRXSRC;
2421
2422	typedef struct IEMPCMPESTRXSRC
2423	{
2424	RTUINT128U uSrc1;
2425	RTUINT128U uSrc2;
2426	uint64_t u64Rax;
2427	uint64_t u64Rdx;
2428	} IEMPCMPESTRXSRC;
2429	typedef IEMPCMPESTRXSRC *PIEMPCMPESTRXSRC;
2430	typedef const IEMPCMPESTRXSRC *PCIEMPCMPESTRXSRC;
2431
2432	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2433	typedef FNIEMAIMPLPCMPISTRIU128IMM8 *PFNIEMAIMPLPCMPISTRIU128IMM8;
2434	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRIU128IMM8,(uint32_t pu32Ecx, uint32_t pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2435	typedef FNIEMAIMPLPCMPESTRIU128IMM8 *PFNIEMAIMPLPCMPESTRIU128IMM8;
2436
2437	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPISTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPISTRXSRC pSrc, uint8_t bEvil));
2438	typedef FNIEMAIMPLPCMPISTRMU128IMM8 *PFNIEMAIMPLPCMPISTRMU128IMM8;
2439	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLPCMPESTRMU128IMM8,(PRTUINT128U puDst, uint32_t *pEFlags, PCIEMPCMPESTRXSRC pSrc, uint8_t bEvil));
2440	typedef FNIEMAIMPLPCMPESTRMU128IMM8 *PFNIEMAIMPLPCMPESTRMU128IMM8;
2441
2442	FNIEMAIMPLPCMPISTRIU128IMM8 iemAImpl_pcmpistri_u128, iemAImpl_pcmpistri_u128_fallback;
2443	FNIEMAIMPLPCMPESTRIU128IMM8 iemAImpl_pcmpestri_u128, iemAImpl_pcmpestri_u128_fallback;
2444	FNIEMAIMPLPCMPISTRMU128IMM8 iemAImpl_pcmpistrm_u128, iemAImpl_pcmpistrm_u128_fallback;
2445	FNIEMAIMPLPCMPESTRMU128IMM8 iemAImpl_pcmpestrm_u128, iemAImpl_pcmpestrm_u128_fallback;
2446
2447	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_pclmulqdq_u128, iemAImpl_pclmulqdq_u128_fallback;
2448	FNIEMAIMPLMEDIAOPTF3U128IMM8 iemAImpl_vpclmulqdq_u128, iemAImpl_vpclmulqdq_u128_fallback;
2449
2450	FNIEMAIMPLMEDIAOPTF2U128IMM8 iemAImpl_mpsadbw_u128, iemAImpl_mpsadbw_u128_fallback;
2451	/** @} */
2452
2453	/** @name Media Odds and Ends
2454	* @{ */
2455	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U8,(uint32_t *puDst, uint8_t uSrc));
2456	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U16,(uint32_t *puDst, uint16_t uSrc));
2457	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U32,(uint32_t *puDst, uint32_t uSrc));
2458	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLCR32U64,(uint32_t *puDst, uint64_t uSrc));
2459	FNIEMAIMPLCR32U8 iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback;
2460	FNIEMAIMPLCR32U16 iemAImpl_crc32_u16, iemAImpl_crc32_u16_fallback;
2461	FNIEMAIMPLCR32U32 iemAImpl_crc32_u32, iemAImpl_crc32_u32_fallback;
2462	FNIEMAIMPLCR32U64 iemAImpl_crc32_u64, iemAImpl_crc32_u64_fallback;
2463
2464	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags));
2465	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags));
2466	FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128;
2467	FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback;
2468
2469	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2470	typedef FNIEMAIMPLSSEF2I32U64 *PFNIEMAIMPLSSEF2I32U64;
2471	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint64_t pu64Src)); / pu64Src is a double precision floating point. */
2472	typedef FNIEMAIMPLSSEF2I64U64 *PFNIEMAIMPLSSEF2I64U64;
2473	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I32U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int32_t pi32Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2474	typedef FNIEMAIMPLSSEF2I32U32 *PFNIEMAIMPLSSEF2I32U32;
2475	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2I64U32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, int64_t pi64Dst, const uint32_t pu32Src)); / pu32Src is a single precision floating point. */
2476	typedef FNIEMAIMPLSSEF2I64U32 *PFNIEMAIMPLSSEF2I64U32;
2477
2478	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
2479	FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
2480
2481	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
2482	FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
2483
2484	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvttss2si_i32_r32;
2485	FNIEMAIMPLSSEF2I32U32 iemAImpl_cvtss2si_i32_r32;
2486
2487	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvttss2si_i64_r32;
2488	FNIEMAIMPLSSEF2I64U32 iemAImpl_cvtss2si_i64_r32;
2489
2490	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int32_t pi32Src));
2491	typedef FNIEMAIMPLSSEF2R32I32 *PFNIEMAIMPLSSEF2R32I32;
2492	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R32I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT32U pr32Dst, const int64_t pi64Src));
2493	typedef FNIEMAIMPLSSEF2R32I64 *PFNIEMAIMPLSSEF2R32I64;
2494
2495	FNIEMAIMPLSSEF2R32I32 iemAImpl_cvtsi2ss_r32_i32;
2496	FNIEMAIMPLSSEF2R32I64 iemAImpl_cvtsi2ss_r32_i64;
2497
2498	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I32,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int32_t pi32Src));
2499	typedef FNIEMAIMPLSSEF2R64I32 *PFNIEMAIMPLSSEF2R64I32;
2500	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLSSEF2R64I64,(PCX86FXSTATE pFpuState, uint32_t pfMxcsr, PRTFLOAT64U pr64Dst, const int64_t pi64Src));
2501	typedef FNIEMAIMPLSSEF2R64I64 *PFNIEMAIMPLSSEF2R64I64;
2502
2503	FNIEMAIMPLSSEF2R64I32 iemAImpl_cvtsi2sd_r64_i32;
2504	FNIEMAIMPLSSEF2R64I64 iemAImpl_cvtsi2sd_r64_i64;
2505
2506
2507	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFLMXCSR128,(uint32_t pfMxcsr, uint32_t pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2508	typedef FNIEMAIMPLF2EFLMXCSR128 *PFNIEMAIMPLF2EFLMXCSR128;
2509
2510	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomiss_u128;
2511	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomiss_u128, iemAImpl_vucomiss_u128_fallback;
2512
2513	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_ucomisd_u128;
2514	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vucomisd_u128, iemAImpl_vucomisd_u128_fallback;
2515
2516	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comiss_u128;
2517	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomiss_u128, iemAImpl_vcomiss_u128_fallback;
2518
2519	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128;
2520	FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback;
2521
2522
2523	typedef struct IEMMEDIAF2XMMSRC
2524	{
2525	X86XMMREG uSrc1;
2526	X86XMMREG uSrc2;
2527	} IEMMEDIAF2XMMSRC;
2528	typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC;
2529	typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC;
2530
2531	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil));
2532	typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8;
2533
2534	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128;
2535	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128;
2536	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128;
2537	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128;
2538	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundss_u128;
2539	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundsd_u128;
2540
2541	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundps_u128, iemAImpl_roundps_u128_fallback;
2542	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_roundpd_u128, iemAImpl_roundpd_u128_fallback;
2543
2544	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dpps_u128, iemAImpl_dpps_u128_fallback;
2545	FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_dppd_u128, iemAImpl_dppd_u128_fallback;
2546
2547	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U128,(uint32_t pfMxcsr, uint64_t pu64Dst, PCX86XMMREG pSrc));
2548	typedef FNIEMAIMPLMXCSRU64U128 *PFNIEMAIMPLMXCSRU64U128;
2549
2550	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvtpd2pi_u128;
2551	FNIEMAIMPLMXCSRU64U128 iemAImpl_cvttpd2pi_u128;
2552
2553	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU128U64,(uint32_t *pfMxcsr, PX86XMMREG pDst, uint64_t u64Src));
2554	typedef FNIEMAIMPLMXCSRU128U64 *PFNIEMAIMPLMXCSRU128U64;
2555
2556	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2ps_u128;
2557	FNIEMAIMPLMXCSRU128U64 iemAImpl_cvtpi2pd_u128;
2558
2559	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRU64U64,(uint32_t pfMxcsr, uint64_t pu64Dst, uint64_t u64Src));
2560	typedef FNIEMAIMPLMXCSRU64U64 *PFNIEMAIMPLMXCSRU64U64;
2561
2562	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvtps2pi_u128;
2563	FNIEMAIMPLMXCSRU64U64 iemAImpl_cvttps2pi_u128;
2564
2565	/** @} */
2566
2567
2568	/** @name Function tables.
2569	* @{
2570	*/
2571
2572	/**
2573	* Function table for a binary operator providing implementation based on
2574	* operand size.
2575	*/
2576	typedef struct IEMOPBINSIZES
2577	{
2578	PFNIEMAIMPLBINU8 pfnNormalU8, pfnLockedU8;
2579	PFNIEMAIMPLBINU16 pfnNormalU16, pfnLockedU16;
2580	PFNIEMAIMPLBINU32 pfnNormalU32, pfnLockedU32;
2581	PFNIEMAIMPLBINU64 pfnNormalU64, pfnLockedU64;
2582	} IEMOPBINSIZES;
2583	/** Pointer to a binary operator function table. */
2584	typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
2585
2586
2587	/**
2588	* Function table for a unary operator providing implementation based on
2589	* operand size.
2590	*/
2591	typedef struct IEMOPUNARYSIZES
2592	{
2593	PFNIEMAIMPLUNARYU8 pfnNormalU8, pfnLockedU8;
2594	PFNIEMAIMPLUNARYU16 pfnNormalU16, pfnLockedU16;
2595	PFNIEMAIMPLUNARYU32 pfnNormalU32, pfnLockedU32;
2596	PFNIEMAIMPLUNARYU64 pfnNormalU64, pfnLockedU64;
2597	} IEMOPUNARYSIZES;
2598	/** Pointer to a unary operator function table. */
2599	typedef IEMOPUNARYSIZES const *PCIEMOPUNARYSIZES;
2600
2601
2602	/**
2603	* Function table for a shift operator providing implementation based on
2604	* operand size.
2605	*/
2606	typedef struct IEMOPSHIFTSIZES
2607	{
2608	PFNIEMAIMPLSHIFTU8 pfnNormalU8;
2609	PFNIEMAIMPLSHIFTU16 pfnNormalU16;
2610	PFNIEMAIMPLSHIFTU32 pfnNormalU32;
2611	PFNIEMAIMPLSHIFTU64 pfnNormalU64;
2612	} IEMOPSHIFTSIZES;
2613	/** Pointer to a shift operator function table. */
2614	typedef IEMOPSHIFTSIZES const *PCIEMOPSHIFTSIZES;
2615
2616
2617	/**
2618	* Function table for a multiplication or division operation.
2619	*/
2620	typedef struct IEMOPMULDIVSIZES
2621	{
2622	PFNIEMAIMPLMULDIVU8 pfnU8;
2623	PFNIEMAIMPLMULDIVU16 pfnU16;
2624	PFNIEMAIMPLMULDIVU32 pfnU32;
2625	PFNIEMAIMPLMULDIVU64 pfnU64;
2626	} IEMOPMULDIVSIZES;
2627	/** Pointer to a multiplication or division operation function table. */
2628	typedef IEMOPMULDIVSIZES const *PCIEMOPMULDIVSIZES;
2629
2630
2631	/**
2632	* Function table for a double precision shift operator providing implementation
2633	* based on operand size.
2634	*/
2635	typedef struct IEMOPSHIFTDBLSIZES
2636	{
2637	PFNIEMAIMPLSHIFTDBLU16 pfnNormalU16;
2638	PFNIEMAIMPLSHIFTDBLU32 pfnNormalU32;
2639	PFNIEMAIMPLSHIFTDBLU64 pfnNormalU64;
2640	} IEMOPSHIFTDBLSIZES;
2641	/** Pointer to a double precision shift function table. */
2642	typedef IEMOPSHIFTDBLSIZES const *PCIEMOPSHIFTDBLSIZES;
2643
2644
2645	/**
2646	* Function table for media instruction taking two full sized media source
2647	* registers and one full sized destination register (AVX).
2648	*/
2649	typedef struct IEMOPMEDIAF3
2650	{
2651	PFNIEMAIMPLMEDIAF3U128 pfnU128;
2652	PFNIEMAIMPLMEDIAF3U256 pfnU256;
2653	} IEMOPMEDIAF3;
2654	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2655	typedef IEMOPMEDIAF3 const *PCIEMOPMEDIAF3;
2656
2657	/** @def IEMOPMEDIAF3_INIT_VARS_EX
2658	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2659	* given functions as initializers. For use in AVX functions where a pair of
2660	* functions are only used once and the function table need not be public. */
2661	#ifndef TST_IEM_CHECK_MC
2662	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2663	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2664	static IEMOPMEDIAF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2665	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2666	# else
2667	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2668	static IEMOPMEDIAF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2669	# endif
2670	#else
2671	# define IEMOPMEDIAF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2672	#endif
2673	/** @def IEMOPMEDIAF3_INIT_VARS
2674	* Generate AVX function tables for the @a a_InstrNm instruction.
2675	* @sa IEMOPMEDIAF3_INIT_VARS_EX */
2676	#define IEMOPMEDIAF3_INIT_VARS(a_InstrNm) \
2677	IEMOPMEDIAF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2678	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2679
2680	/**
2681	* Function table for media instruction taking two full sized media source
2682	* registers and one full sized destination register, but no additional state
2683	* (AVX).
2684	*/
2685	typedef struct IEMOPMEDIAOPTF3
2686	{
2687	PFNIEMAIMPLMEDIAOPTF3U128 pfnU128;
2688	PFNIEMAIMPLMEDIAOPTF3U256 pfnU256;
2689	} IEMOPMEDIAOPTF3;
2690	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2691	typedef IEMOPMEDIAOPTF3 const *PCIEMOPMEDIAOPTF3;
2692
2693	/** @def IEMOPMEDIAOPTF3_INIT_VARS_EX
2694	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2695	* given functions as initializers. For use in AVX functions where a pair of
2696	* functions are only used once and the function table need not be public. */
2697	#ifndef TST_IEM_CHECK_MC
2698	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2699	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2700	static IEMOPMEDIAOPTF3 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2701	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2702	# else
2703	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2704	static IEMOPMEDIAOPTF3 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2705	# endif
2706	#else
2707	# define IEMOPMEDIAOPTF3_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2708	#endif
2709	/** @def IEMOPMEDIAOPTF3_INIT_VARS
2710	* Generate AVX function tables for the @a a_InstrNm instruction.
2711	* @sa IEMOPMEDIAOPTF3_INIT_VARS_EX */
2712	#define IEMOPMEDIAOPTF3_INIT_VARS(a_InstrNm) \
2713	IEMOPMEDIAOPTF3_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2714	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2715
2716	/**
2717	* Function table for media instruction taking one full sized media source
2718	* registers and one full sized destination register, but no additional state
2719	* (AVX).
2720	*/
2721	typedef struct IEMOPMEDIAOPTF2
2722	{
2723	PFNIEMAIMPLMEDIAOPTF2U128 pfnU128;
2724	PFNIEMAIMPLMEDIAOPTF2U256 pfnU256;
2725	} IEMOPMEDIAOPTF2;
2726	/** Pointer to a media operation function table for 2 full sized ops (AVX). */
2727	typedef IEMOPMEDIAOPTF2 const *PCIEMOPMEDIAOPTF2;
2728
2729	/** @def IEMOPMEDIAOPTF2_INIT_VARS_EX
2730	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2731	* given functions as initializers. For use in AVX functions where a pair of
2732	* functions are only used once and the function table need not be public. */
2733	#ifndef TST_IEM_CHECK_MC
2734	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2735	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2736	static IEMOPMEDIAOPTF2 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2737	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2738	# else
2739	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2740	static IEMOPMEDIAOPTF2 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2741	# endif
2742	#else
2743	# define IEMOPMEDIAOPTF2_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2744	#endif
2745	/** @def IEMOPMEDIAOPTF2_INIT_VARS
2746	* Generate AVX function tables for the @a a_InstrNm instruction.
2747	* @sa IEMOPMEDIAOPTF2_INIT_VARS_EX */
2748	#define IEMOPMEDIAOPTF2_INIT_VARS(a_InstrNm) \
2749	IEMOPMEDIAOPTF2_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2750	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2751
2752	/**
2753	* Function table for media instruction taking two full sized media source
2754	* registers and one full sized destination register and an 8-bit immediate, but no additional state
2755	* (AVX).
2756	*/
2757	typedef struct IEMOPMEDIAOPTF3IMM8
2758	{
2759	PFNIEMAIMPLMEDIAOPTF3U128IMM8 pfnU128;
2760	PFNIEMAIMPLMEDIAOPTF3U256IMM8 pfnU256;
2761	} IEMOPMEDIAOPTF3IMM8;
2762	/** Pointer to a media operation function table for 3 full sized ops (AVX). */
2763	typedef IEMOPMEDIAOPTF3IMM8 const *PCIEMOPMEDIAOPTF3IMM8;
2764
2765	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX
2766	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2767	* given functions as initializers. For use in AVX functions where a pair of
2768	* functions are only used once and the function table need not be public. */
2769	#ifndef TST_IEM_CHECK_MC
2770	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2771	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2772	static IEMOPMEDIAOPTF3IMM8 const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2773	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2774	# else
2775	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2776	static IEMOPMEDIAOPTF3IMM8 const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2777	# endif
2778	#else
2779	# define IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2780	#endif
2781	/** @def IEMOPMEDIAOPTF3IMM8_INIT_VARS
2782	* Generate AVX function tables for the @a a_InstrNm instruction.
2783	* @sa IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX */
2784	#define IEMOPMEDIAOPTF3IMM8_INIT_VARS(a_InstrNm) \
2785	IEMOPMEDIAOPTF3IMM8_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2786	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2787	/** @} */
2788
2789
2790	/**
2791	* Function table for blend type instruction taking three full sized media source
2792	* registers and one full sized destination register, but no additional state
2793	* (AVX).
2794	*/
2795	typedef struct IEMOPBLENDOP
2796	{
2797	PFNIEMAIMPLAVXBLENDU128 pfnU128;
2798	PFNIEMAIMPLAVXBLENDU256 pfnU256;
2799	} IEMOPBLENDOP;
2800	/** Pointer to a media operation function table for 4 full sized ops (AVX). */
2801	typedef IEMOPBLENDOP const *PCIEMOPBLENDOP;
2802
2803	/** @def IEMOPBLENDOP_INIT_VARS_EX
2804	* Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the
2805	* given functions as initializers. For use in AVX functions where a pair of
2806	* functions are only used once and the function table need not be public. */
2807	#ifndef TST_IEM_CHECK_MC
2808	# if (defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
2809	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2810	static IEMOPBLENDOP const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \
2811	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2812	# else
2813	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \
2814	static IEMOPBLENDOP const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 }
2815	# endif
2816	#else
2817	# define IEMOPBLENDOP_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0
2818	#endif
2819	/** @def IEMOPBLENDOP_INIT_VARS
2820	* Generate AVX function tables for the @a a_InstrNm instruction.
2821	* @sa IEMOPBLENDOP_INIT_VARS_EX */
2822	#define IEMOPBLENDOP_INIT_VARS(a_InstrNm) \
2823	IEMOPBLENDOP_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256),\
2824	RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback))
2825
2826
2827	/** @name SSE/AVX single/double precision floating point operations.
2828	* @{ */
2829	/**
2830	* A SSE result.
2831	*/
2832	typedef struct IEMSSERESULT
2833	{
2834	/** The output value. */
2835	X86XMMREG uResult;
2836	/** The output status. */
2837	uint32_t MXCSR;
2838	} IEMSSERESULT;
2839	AssertCompileMemberOffset(IEMSSERESULT, MXCSR, 128 / 8);
2840	/** Pointer to a SSE result. */
2841	typedef IEMSSERESULT *PIEMSSERESULT;
2842	/** Pointer to a const SSE result. */
2843	typedef IEMSSERESULT const *PCIEMSSERESULT;
2844
2845
2846	/**
2847	* A AVX128 result.
2848	*/
2849	typedef struct IEMAVX128RESULT
2850	{
2851	/** The output value. */
2852	X86XMMREG uResult;
2853	/** The output status. */
2854	uint32_t MXCSR;
2855	} IEMAVX128RESULT;
2856	AssertCompileMemberOffset(IEMAVX128RESULT, MXCSR, 128 / 8);
2857	/** Pointer to a AVX128 result. */
2858	typedef IEMAVX128RESULT *PIEMAVX128RESULT;
2859	/** Pointer to a const AVX128 result. */
2860	typedef IEMAVX128RESULT const *PCIEMAVX128RESULT;
2861
2862
2863	/**
2864	* A AVX256 result.
2865	*/
2866	typedef struct IEMAVX256RESULT
2867	{
2868	/** The output value. */
2869	X86YMMREG uResult;
2870	/** The output status. */
2871	uint32_t MXCSR;
2872	} IEMAVX256RESULT;
2873	AssertCompileMemberOffset(IEMAVX256RESULT, MXCSR, 256 / 8);
2874	/** Pointer to a AVX256 result. */
2875	typedef IEMAVX256RESULT *PIEMAVX256RESULT;
2876	/** Pointer to a const AVX256 result. */
2877	typedef IEMAVX256RESULT const *PCIEMAVX256RESULT;
2878
2879
2880	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2881	typedef FNIEMAIMPLFPSSEF2U128 *PFNIEMAIMPLFPSSEF2U128;
2882	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R32,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2883	typedef FNIEMAIMPLFPSSEF2U128R32 *PFNIEMAIMPLFPSSEF2U128R32;
2884	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPSSEF2U128R64,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2885	typedef FNIEMAIMPLFPSSEF2U128R64 *PFNIEMAIMPLFPSSEF2U128R64;
2886
2887	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2));
2888	typedef FNIEMAIMPLFPAVXF3U128 *PFNIEMAIMPLFPAVXF3U128;
2889	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R32,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT32U pr32Src2));
2890	typedef FNIEMAIMPLFPAVXF3U128R32 *PFNIEMAIMPLFPAVXF3U128R32;
2891	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U128R64,(PX86XSAVEAREA pExtState, PIEMAVX128RESULT pResult, PCX86XMMREG puSrc1, PCRTFLOAT64U pr64Src2));
2892	typedef FNIEMAIMPLFPAVXF3U128R64 *PFNIEMAIMPLFPAVXF3U128R64;
2893
2894	typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLFPAVXF3U256,(PX86XSAVEAREA pExtState, PIEMAVX256RESULT pResult, PCX86YMMREG puSrc1, PCX86YMMREG puSrc2));
2895	typedef FNIEMAIMPLFPAVXF3U256 *PFNIEMAIMPLFPAVXF3U256;
2896
2897	FNIEMAIMPLFPSSEF2U128 iemAImpl_addps_u128;
2898	FNIEMAIMPLFPSSEF2U128 iemAImpl_addpd_u128;
2899	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulps_u128;
2900	FNIEMAIMPLFPSSEF2U128 iemAImpl_mulpd_u128;
2901	FNIEMAIMPLFPSSEF2U128 iemAImpl_subps_u128;
2902	FNIEMAIMPLFPSSEF2U128 iemAImpl_subpd_u128;
2903	FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
2904	FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
2905	FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
2906	FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
2907	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxps_u128;
2908	FNIEMAIMPLFPSSEF2U128 iemAImpl_maxpd_u128;
2909	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddps_u128;
2910	FNIEMAIMPLFPSSEF2U128 iemAImpl_haddpd_u128;
2911	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubps_u128;
2912	FNIEMAIMPLFPSSEF2U128 iemAImpl_hsubpd_u128;
2913	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtps_u128;
2914	FNIEMAIMPLFPSSEF2U128 iemAImpl_rsqrtps_u128;
2915	FNIEMAIMPLFPSSEF2U128 iemAImpl_sqrtpd_u128;
2916	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubps_u128;
2917	FNIEMAIMPLFPSSEF2U128 iemAImpl_addsubpd_u128;
2918	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2ps_u128;
2919	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2pd_u128;
2920
2921	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2ps_u128;
2922	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtps2dq_u128;
2923	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttps2dq_u128;
2924	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvttpd2dq_u128;
2925	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtdq2pd_u128;
2926	FNIEMAIMPLFPSSEF2U128 iemAImpl_cvtpd2dq_u128;
2927
2928	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_addss_u128_r32;
2929	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_addsd_u128_r64;
2930	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_mulss_u128_r32;
2931	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_mulsd_u128_r64;
2932	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_subss_u128_r32;
2933	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_subsd_u128_r64;
2934	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_minss_u128_r32;
2935	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_minsd_u128_r64;
2936	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_divss_u128_r32;
2937	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_divsd_u128_r64;
2938	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_maxss_u128_r32;
2939	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_maxsd_u128_r64;
2940	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_cvtss2sd_u128_r32;
2941	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_cvtsd2ss_u128_r64;
2942	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_sqrtss_u128_r32;
2943	FNIEMAIMPLFPSSEF2U128R64 iemAImpl_sqrtsd_u128_r64;
2944	FNIEMAIMPLFPSSEF2U128R32 iemAImpl_rsqrtss_u128_r32;
2945
2946	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
2947	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddpd_u128, iemAImpl_vaddpd_u128_fallback;
2948	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulps_u128, iemAImpl_vmulps_u128_fallback;
2949	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmulpd_u128, iemAImpl_vmulpd_u128_fallback;
2950	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubps_u128, iemAImpl_vsubps_u128_fallback;
2951	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsubpd_u128, iemAImpl_vsubpd_u128_fallback;
2952	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
2953	FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
2954	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
2955	FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
2956	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxps_u128, iemAImpl_vmaxps_u128_fallback;
2957	FNIEMAIMPLFPAVXF3U128 iemAImpl_vmaxpd_u128, iemAImpl_vmaxpd_u128_fallback;
2958	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddps_u128, iemAImpl_vhaddps_u128_fallback;
2959	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhaddpd_u128, iemAImpl_vhaddpd_u128_fallback;
2960	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubps_u128, iemAImpl_vhsubps_u128_fallback;
2961	FNIEMAIMPLFPAVXF3U128 iemAImpl_vhsubpd_u128, iemAImpl_vhsubpd_u128_fallback;
2962	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtps_u128, iemAImpl_vsqrtps_u128_fallback;
2963	FNIEMAIMPLFPAVXF3U128 iemAImpl_vsqrtpd_u128, iemAImpl_vsqrtpd_u128_fallback;
2964	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubps_u128, iemAImpl_vaddsubps_u128_fallback;
2965	FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddsubpd_u128, iemAImpl_vaddsubpd_u128_fallback;
2966	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtpd2ps_u128, iemAImpl_vcvtpd2ps_u128_fallback;
2967	FNIEMAIMPLFPAVXF3U128 iemAImpl_vcvtps2pd_u128, iemAImpl_vcvtps2pd_u128_fallback;
2968
2969	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vaddss_u128_r32, iemAImpl_vaddss_u128_r32_fallback;
2970	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vaddsd_u128_r64, iemAImpl_vaddsd_u128_r64_fallback;
2971	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmulss_u128_r32, iemAImpl_vmulss_u128_r32_fallback;
2972	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmulsd_u128_r64, iemAImpl_vmulsd_u128_r64_fallback;
2973	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsubss_u128_r32, iemAImpl_vsubss_u128_r32_fallback;
2974	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsubsd_u128_r64, iemAImpl_vsubsd_u128_r64_fallback;
2975	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vminss_u128_r32, iemAImpl_vminss_u128_r32_fallback;
2976	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vminsd_u128_r64, iemAImpl_vminsd_u128_r64_fallback;
2977	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vdivss_u128_r32, iemAImpl_vdivss_u128_r32_fallback;
2978	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vdivsd_u128_r64, iemAImpl_vdivsd_u128_r64_fallback;
2979	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vmaxss_u128_r32, iemAImpl_vmaxss_u128_r32_fallback;
2980	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vmaxsd_u128_r64, iemAImpl_vmaxsd_u128_r64_fallback;
2981	FNIEMAIMPLFPAVXF3U128R32 iemAImpl_vsqrtss_u128_r32, iemAImpl_vsqrtss_u128_r32_fallback;
2982	FNIEMAIMPLFPAVXF3U128R64 iemAImpl_vsqrtsd_u128_r64, iemAImpl_vsqrtsd_u128_r64_fallback;
2983
2984	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
2985	FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddpd_u256, iemAImpl_vaddpd_u256_fallback;
2986	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulps_u256, iemAImpl_vmulps_u256_fallback;
2987	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmulpd_u256, iemAImpl_vmulpd_u256_fallback;
2988	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubps_u256, iemAImpl_vsubps_u256_fallback;
2989	FNIEMAIMPLFPAVXF3U256 iemAImpl_vsubpd_u256, iemAImpl_vsubpd_u256_fallback;
2990	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
2991	FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
2992	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
2993	FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
2994	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxps_u256, iemAImpl_vmaxps_u256_fallback;
2995	FNIEMAIMPLFPAVXF3U256 iemAImpl_vmaxpd_u256, iemAImpl_vmaxpd_u256_fallback;
2996	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddps_u256, iemAImpl_vhaddps_u256_fallback;
2997	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddpd_u256, iemAImpl_vhaddpd_u256_fallback;
2998	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubps_u256, iemAImpl_vhsubps_u256_fallback;
2999	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhsubpd_u256, iemAImpl_vhsubpd_u256_fallback;
3000	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubps_u256, iemAImpl_vhaddsubps_u256_fallback;
3001	FNIEMAIMPLFPAVXF3U256 iemAImpl_vhaddsubpd_u256, iemAImpl_vhaddsubpd_u256_fallback;
3002	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtpd2ps_u256, iemAImpl_vcvtpd2ps_u256_fallback;
3003	FNIEMAIMPLFPAVXF3U256 iemAImpl_vcvtps2pd_u256, iemAImpl_vcvtps2pd_u256_fallback;
3004	/** @} */
3005
3006	/** @name C instruction implementations for anything slightly complicated.
3007	* @{ */
3008
3009	/**
3010	* For typedef'ing or declaring a C instruction implementation function taking
3011	* no extra arguments.
3012	*
3013	* @param a_Name The name of the type.
3014	*/
3015	# define IEM_CIMPL_DECL_TYPE_0(a_Name) \
3016	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3017	/**
3018	* For defining a C instruction implementation function taking no extra
3019	* arguments.
3020	*
3021	* @param a_Name The name of the function
3022	*/
3023	# define IEM_CIMPL_DEF_0(a_Name) \
3024	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3025	/**
3026	* Prototype version of IEM_CIMPL_DEF_0.
3027	*/
3028	# define IEM_CIMPL_PROTO_0(a_Name) \
3029	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr))
3030	/**
3031	* For calling a C instruction implementation function taking no extra
3032	* arguments.
3033	*
3034	* This special call macro adds default arguments to the call and allow us to
3035	* change these later.
3036	*
3037	* @param a_fn The name of the function.
3038	*/
3039	# define IEM_CIMPL_CALL_0(a_fn) a_fn(pVCpu, cbInstr)
3040
3041	/**
3042	* For typedef'ing or declaring a C instruction implementation function taking
3043	* one extra argument.
3044	*
3045	* @param a_Name The name of the type.
3046	* @param a_Type0 The argument type.
3047	* @param a_Arg0 The argument name.
3048	*/
3049	# define IEM_CIMPL_DECL_TYPE_1(a_Name, a_Type0, a_Arg0) \
3050	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3051	/**
3052	* For defining a C instruction implementation function taking one extra
3053	* argument.
3054	*
3055	* @param a_Name The name of the function
3056	* @param a_Type0 The argument type.
3057	* @param a_Arg0 The argument name.
3058	*/
3059	# define IEM_CIMPL_DEF_1(a_Name, a_Type0, a_Arg0) \
3060	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3061	/**
3062	* Prototype version of IEM_CIMPL_DEF_1.
3063	*/
3064	# define IEM_CIMPL_PROTO_1(a_Name, a_Type0, a_Arg0) \
3065	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0))
3066	/**
3067	* For calling a C instruction implementation function taking one extra
3068	* argument.
3069	*
3070	* This special call macro adds default arguments to the call and allow us to
3071	* change these later.
3072	*
3073	* @param a_fn The name of the function.
3074	* @param a0 The name of the 1st argument.
3075	*/
3076	# define IEM_CIMPL_CALL_1(a_fn, a0) a_fn(pVCpu, cbInstr, (a0))
3077
3078	/**
3079	* For typedef'ing or declaring a C instruction implementation function taking
3080	* two extra arguments.
3081	*
3082	* @param a_Name The name of the type.
3083	* @param a_Type0 The type of the 1st argument
3084	* @param a_Arg0 The name of the 1st argument.
3085	* @param a_Type1 The type of the 2nd argument.
3086	* @param a_Arg1 The name of the 2nd argument.
3087	*/
3088	# define IEM_CIMPL_DECL_TYPE_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3089	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3090	/**
3091	* For defining a C instruction implementation function taking two extra
3092	* arguments.
3093	*
3094	* @param a_Name The name of the function.
3095	* @param a_Type0 The type of the 1st argument
3096	* @param a_Arg0 The name of the 1st argument.
3097	* @param a_Type1 The type of the 2nd argument.
3098	* @param a_Arg1 The name of the 2nd argument.
3099	*/
3100	# define IEM_CIMPL_DEF_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3101	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3102	/**
3103	* Prototype version of IEM_CIMPL_DEF_2.
3104	*/
3105	# define IEM_CIMPL_PROTO_2(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1) \
3106	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1))
3107	/**
3108	* For calling a C instruction implementation function taking two extra
3109	* arguments.
3110	*
3111	* This special call macro adds default arguments to the call and allow us to
3112	* change these later.
3113	*
3114	* @param a_fn The name of the function.
3115	* @param a0 The name of the 1st argument.
3116	* @param a1 The name of the 2nd argument.
3117	*/
3118	# define IEM_CIMPL_CALL_2(a_fn, a0, a1) a_fn(pVCpu, cbInstr, (a0), (a1))
3119
3120	/**
3121	* For typedef'ing or declaring a C instruction implementation function taking
3122	* three extra arguments.
3123	*
3124	* @param a_Name The name of the type.
3125	* @param a_Type0 The type of the 1st argument
3126	* @param a_Arg0 The name of the 1st argument.
3127	* @param a_Type1 The type of the 2nd argument.
3128	* @param a_Arg1 The name of the 2nd argument.
3129	* @param a_Type2 The type of the 3rd argument.
3130	* @param a_Arg2 The name of the 3rd argument.
3131	*/
3132	# define IEM_CIMPL_DECL_TYPE_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3133	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3134	/**
3135	* For defining a C instruction implementation function taking three extra
3136	* arguments.
3137	*
3138	* @param a_Name The name of the function.
3139	* @param a_Type0 The type of the 1st argument
3140	* @param a_Arg0 The name of the 1st argument.
3141	* @param a_Type1 The type of the 2nd argument.
3142	* @param a_Arg1 The name of the 2nd argument.
3143	* @param a_Type2 The type of the 3rd argument.
3144	* @param a_Arg2 The name of the 3rd argument.
3145	*/
3146	# define IEM_CIMPL_DEF_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3147	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3148	/**
3149	* Prototype version of IEM_CIMPL_DEF_3.
3150	*/
3151	# define IEM_CIMPL_PROTO_3(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2) \
3152	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2))
3153	/**
3154	* For calling a C instruction implementation function taking three extra
3155	* arguments.
3156	*
3157	* This special call macro adds default arguments to the call and allow us to
3158	* change these later.
3159	*
3160	* @param a_fn The name of the function.
3161	* @param a0 The name of the 1st argument.
3162	* @param a1 The name of the 2nd argument.
3163	* @param a2 The name of the 3rd argument.
3164	*/
3165	# define IEM_CIMPL_CALL_3(a_fn, a0, a1, a2) a_fn(pVCpu, cbInstr, (a0), (a1), (a2))
3166
3167
3168	/**
3169	* For typedef'ing or declaring a C instruction implementation function taking
3170	* four extra arguments.
3171	*
3172	* @param a_Name The name of the type.
3173	* @param a_Type0 The type of the 1st argument
3174	* @param a_Arg0 The name of the 1st argument.
3175	* @param a_Type1 The type of the 2nd argument.
3176	* @param a_Arg1 The name of the 2nd argument.
3177	* @param a_Type2 The type of the 3rd argument.
3178	* @param a_Arg2 The name of the 3rd argument.
3179	* @param a_Type3 The type of the 4th argument.
3180	* @param a_Arg3 The name of the 4th argument.
3181	*/
3182	# define IEM_CIMPL_DECL_TYPE_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3183	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, a_Type3 a_Arg3))
3184	/**
3185	* For defining a C instruction implementation function taking four extra
3186	* arguments.
3187	*
3188	* @param a_Name The name of the function.
3189	* @param a_Type0 The type of the 1st argument
3190	* @param a_Arg0 The name of the 1st argument.
3191	* @param a_Type1 The type of the 2nd argument.
3192	* @param a_Arg1 The name of the 2nd argument.
3193	* @param a_Type2 The type of the 3rd argument.
3194	* @param a_Arg2 The name of the 3rd argument.
3195	* @param a_Type3 The type of the 4th argument.
3196	* @param a_Arg3 The name of the 4th argument.
3197	*/
3198	# define IEM_CIMPL_DEF_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3199	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3200	a_Type2 a_Arg2, a_Type3 a_Arg3))
3201	/**
3202	* Prototype version of IEM_CIMPL_DEF_4.
3203	*/
3204	# define IEM_CIMPL_PROTO_4(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3) \
3205	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3206	a_Type2 a_Arg2, a_Type3 a_Arg3))
3207	/**
3208	* For calling a C instruction implementation function taking four extra
3209	* arguments.
3210	*
3211	* This special call macro adds default arguments to the call and allow us to
3212	* change these later.
3213	*
3214	* @param a_fn The name of the function.
3215	* @param a0 The name of the 1st argument.
3216	* @param a1 The name of the 2nd argument.
3217	* @param a2 The name of the 3rd argument.
3218	* @param a3 The name of the 4th argument.
3219	*/
3220	# define IEM_CIMPL_CALL_4(a_fn, a0, a1, a2, a3) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3))
3221
3222
3223	/**
3224	* For typedef'ing or declaring a C instruction implementation function taking
3225	* five extra arguments.
3226	*
3227	* @param a_Name The name of the type.
3228	* @param a_Type0 The type of the 1st argument
3229	* @param a_Arg0 The name of the 1st argument.
3230	* @param a_Type1 The type of the 2nd argument.
3231	* @param a_Arg1 The name of the 2nd argument.
3232	* @param a_Type2 The type of the 3rd argument.
3233	* @param a_Arg2 The name of the 3rd argument.
3234	* @param a_Type3 The type of the 4th argument.
3235	* @param a_Arg3 The name of the 4th argument.
3236	* @param a_Type4 The type of the 5th argument.
3237	* @param a_Arg4 The name of the 5th argument.
3238	*/
3239	# define IEM_CIMPL_DECL_TYPE_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3240	IEM_DECL_IMPL_TYPE(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, \
3241	a_Type0 a_Arg0, a_Type1 a_Arg1, a_Type2 a_Arg2, \
3242	a_Type3 a_Arg3, a_Type4 a_Arg4))
3243	/**
3244	* For defining a C instruction implementation function taking five extra
3245	* arguments.
3246	*
3247	* @param a_Name The name of the function.
3248	* @param a_Type0 The type of the 1st argument
3249	* @param a_Arg0 The name of the 1st argument.
3250	* @param a_Type1 The type of the 2nd argument.
3251	* @param a_Arg1 The name of the 2nd argument.
3252	* @param a_Type2 The type of the 3rd argument.
3253	* @param a_Arg2 The name of the 3rd argument.
3254	* @param a_Type3 The type of the 4th argument.
3255	* @param a_Arg3 The name of the 4th argument.
3256	* @param a_Type4 The type of the 5th argument.
3257	* @param a_Arg4 The name of the 5th argument.
3258	*/
3259	# define IEM_CIMPL_DEF_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3260	IEM_DECL_IMPL_DEF(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3261	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3262	/**
3263	* Prototype version of IEM_CIMPL_DEF_5.
3264	*/
3265	# define IEM_CIMPL_PROTO_5(a_Name, a_Type0, a_Arg0, a_Type1, a_Arg1, a_Type2, a_Arg2, a_Type3, a_Arg3, a_Type4, a_Arg4) \
3266	IEM_DECL_IMPL_PROTO(VBOXSTRICTRC, a_Name, (PVMCPUCC pVCpu, uint8_t cbInstr, a_Type0 a_Arg0, a_Type1 a_Arg1, \
3267	a_Type2 a_Arg2, a_Type3 a_Arg3, a_Type4 a_Arg4))
3268	/**
3269	* For calling a C instruction implementation function taking five extra
3270	* arguments.
3271	*
3272	* This special call macro adds default arguments to the call and allow us to
3273	* change these later.
3274	*
3275	* @param a_fn The name of the function.
3276	* @param a0 The name of the 1st argument.
3277	* @param a1 The name of the 2nd argument.
3278	* @param a2 The name of the 3rd argument.
3279	* @param a3 The name of the 4th argument.
3280	* @param a4 The name of the 5th argument.
3281	*/
3282	# define IEM_CIMPL_CALL_5(a_fn, a0, a1, a2, a3, a4) a_fn(pVCpu, cbInstr, (a0), (a1), (a2), (a3), (a4))
3283
3284	/** @} */
3285
3286
3287	/** @name Opcode Decoder Function Types.
3288	* @{ */
3289
3290	/** @typedef PFNIEMOP
3291	* Pointer to an opcode decoder function.
3292	*/
3293
3294	/** @def FNIEMOP_DEF
3295	* Define an opcode decoder function.
3296	*
3297	* We're using macors for this so that adding and removing parameters as well as
3298	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL
3299	*
3300	* @param a_Name The function name.
3301	*/
3302
3303	/** @typedef PFNIEMOPRM
3304	* Pointer to an opcode decoder function with RM byte.
3305	*/
3306
3307	/** @def FNIEMOPRM_DEF
3308	* Define an opcode decoder function with RM byte.
3309	*
3310	* We're using macors for this so that adding and removing parameters as well as
3311	* tweaking compiler specific attributes becomes easier. See FNIEMOP_CALL_1
3312	*
3313	* @param a_Name The function name.
3314	*/
3315
3316	#if defined(__GNUC__) && defined(RT_ARCH_X86)
3317	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOP)(PVMCPUCC pVCpu);
3318	typedef VBOXSTRICTRC (__attribute__((__fastcall__)) * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3319	# define FNIEMOP_DEF(a_Name) \
3320	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu)
3321	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3322	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3323	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3324	IEM_STATIC VBOXSTRICTRC __attribute__((__fastcall__, __nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3325
3326	#elif defined(_MSC_VER) && defined(RT_ARCH_X86)
3327	typedef VBOXSTRICTRC (__fastcall * PFNIEMOP)(PVMCPUCC pVCpu);
3328	typedef VBOXSTRICTRC (__fastcall * PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3329	# define FNIEMOP_DEF(a_Name) \
3330	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3331	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3332	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3333	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3334	IEM_STATIC /__declspec(naked)/ VBOXSTRICTRC __fastcall a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3335
3336	#elif defined(__GNUC__) && !defined(IEM_WITH_THROW_CATCH)
3337	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3338	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3339	# define FNIEMOP_DEF(a_Name) \
3340	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu)
3341	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3342	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0)
3343	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3344	IEM_STATIC VBOXSTRICTRC __attribute__((__nothrow__)) a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1)
3345
3346	#else
3347	typedef VBOXSTRICTRC (* PFNIEMOP)(PVMCPUCC pVCpu);
3348	typedef VBOXSTRICTRC (* PFNIEMOPRM)(PVMCPUCC pVCpu, uint8_t bRm);
3349	# define FNIEMOP_DEF(a_Name) \
3350	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP
3351	# define FNIEMOP_DEF_1(a_Name, a_Type0, a_Name0) \
3352	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0) IEM_NOEXCEPT_MAY_LONGJMP
3353	# define FNIEMOP_DEF_2(a_Name, a_Type0, a_Name0, a_Type1, a_Name1) \
3354	IEM_STATIC VBOXSTRICTRC a_Name(PVMCPUCC pVCpu, a_Type0 a_Name0, a_Type1 a_Name1) IEM_NOEXCEPT_MAY_LONGJMP
3355
3356	#endif
3357	#define FNIEMOPRM_DEF(a_Name) FNIEMOP_DEF_1(a_Name, uint8_t, bRm)
3358
3359	/**
3360	* Call an opcode decoder function.
3361	*
3362	* We're using macors for this so that adding and removing parameters can be
3363	* done as we please. See FNIEMOP_DEF.
3364	*/
3365	#define FNIEMOP_CALL(a_pfn) (a_pfn)(pVCpu)
3366
3367	/**
3368	* Call a common opcode decoder function taking one extra argument.
3369	*
3370	* We're using macors for this so that adding and removing parameters can be
3371	* done as we please. See FNIEMOP_DEF_1.
3372	*/
3373	#define FNIEMOP_CALL_1(a_pfn, a0) (a_pfn)(pVCpu, a0)
3374
3375	/**
3376	* Call a common opcode decoder function taking one extra argument.
3377	*
3378	* We're using macors for this so that adding and removing parameters can be
3379	* done as we please. See FNIEMOP_DEF_1.
3380	*/
3381	#define FNIEMOP_CALL_2(a_pfn, a0, a1) (a_pfn)(pVCpu, a0, a1)
3382	/** @} */
3383
3384
3385	/** @name Misc Helpers
3386	* @{ */
3387
3388	/** Used to shut up GCC warnings about variables that 'may be used uninitialized'
3389	* due to GCC lacking knowledge about the value range of a switch. */
3390	#if RT_CPLUSPLUS_PREREQ(202000)
3391	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: [[unlikely]] AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3392	#else
3393	# define IEM_NOT_REACHED_DEFAULT_CASE_RET() default: AssertFailedReturn(VERR_IPE_NOT_REACHED_DEFAULT_CASE)
3394	#endif
3395
3396	/** Variant of IEM_NOT_REACHED_DEFAULT_CASE_RET that returns a custom value. */
3397	#if RT_CPLUSPLUS_PREREQ(202000)
3398	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: [[unlikely]] AssertFailedReturn(a_RetValue)
3399	#else
3400	# define IEM_NOT_REACHED_DEFAULT_CASE_RET2(a_RetValue) default: AssertFailedReturn(a_RetValue)
3401	#endif
3402
3403	/**
3404	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3405	* occation.
3406	*/
3407	#ifdef LOG_ENABLED
3408	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3409	do { \
3410	/Log/ LogAlways(("%s: returning IEM_RETURN_ASPECT_NOT_IMPLEMENTED (line %d)\n", __FUNCTION__, __LINE__)); \
3411	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3412	} while (0)
3413	#else
3414	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED() \
3415	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3416	#endif
3417
3418	/**
3419	* Returns IEM_RETURN_ASPECT_NOT_IMPLEMENTED, and in debug builds logs the
3420	* occation using the supplied logger statement.
3421	*
3422	* @param a_LoggerArgs What to log on failure.
3423	*/
3424	#ifdef LOG_ENABLED
3425	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3426	do { \
3427	LogAlways((LOG_FN_FMT ": ", __PRETTY_FUNCTION__)); LogAlways(a_LoggerArgs); \
3428	/LogFunc(a_LoggerArgs);/ \
3429	return VERR_IEM_ASPECT_NOT_IMPLEMENTED; \
3430	} while (0)
3431	#else
3432	# define IEM_RETURN_ASPECT_NOT_IMPLEMENTED_LOG(a_LoggerArgs) \
3433	return VERR_IEM_ASPECT_NOT_IMPLEMENTED
3434	#endif
3435
3436	/**
3437	* Check if we're currently executing in real or virtual 8086 mode.
3438	*
3439	* @returns @c true if it is, @c false if not.
3440	* @param a_pVCpu The IEM state of the current CPU.
3441	*/
3442	#define IEM_IS_REAL_OR_V86_MODE(a_pVCpu) (CPUMIsGuestInRealOrV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3443
3444	/**
3445	* Check if we're currently executing in virtual 8086 mode.
3446	*
3447	* @returns @c true if it is, @c false if not.
3448	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3449	*/
3450	#define IEM_IS_V86_MODE(a_pVCpu) (CPUMIsGuestInV86ModeEx(IEM_GET_CTX(a_pVCpu)))
3451
3452	/**
3453	* Check if we're currently executing in long mode.
3454	*
3455	* @returns @c true if it is, @c false if not.
3456	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3457	*/
3458	#define IEM_IS_LONG_MODE(a_pVCpu) (CPUMIsGuestInLongModeEx(IEM_GET_CTX(a_pVCpu)))
3459
3460	/**
3461	* Check if we're currently executing in a 64-bit code segment.
3462	*
3463	* @returns @c true if it is, @c false if not.
3464	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3465	*/
3466	#define IEM_IS_64BIT_CODE(a_pVCpu) (CPUMIsGuestIn64BitCodeEx(IEM_GET_CTX(a_pVCpu)))
3467
3468	/**
3469	* Check if we're currently executing in real mode.
3470	*
3471	* @returns @c true if it is, @c false if not.
3472	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3473	*/
3474	#define IEM_IS_REAL_MODE(a_pVCpu) (CPUMIsGuestInRealModeEx(IEM_GET_CTX(a_pVCpu)))
3475
3476	/**
3477	* Returns a (const) pointer to the CPUMFEATURES for the guest CPU.
3478	* @returns PCCPUMFEATURES
3479	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3480	*/
3481	#define IEM_GET_GUEST_CPU_FEATURES(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->cpum.ro.GuestFeatures))
3482
3483	/**
3484	* Returns a (const) pointer to the CPUMFEATURES for the host CPU.
3485	* @returns PCCPUMFEATURES
3486	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3487	*/
3488	#define IEM_GET_HOST_CPU_FEATURES(a_pVCpu) (&g_CpumHostFeatures.s)
3489
3490	/**
3491	* Evaluates to true if we're presenting an Intel CPU to the guest.
3492	*/
3493	#define IEM_IS_GUEST_CPU_INTEL(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL )
3494
3495	/**
3496	* Evaluates to true if we're presenting an AMD CPU to the guest.
3497	*/
3498	#define IEM_IS_GUEST_CPU_AMD(a_pVCpu) ( (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_AMD \|\| (a_pVCpu)->iem.s.enmCpuVendor == CPUMCPUVENDOR_HYGON )
3499
3500	/**
3501	* Check if the address is canonical.
3502	*/
3503	#define IEM_IS_CANONICAL(a_u64Addr) X86_IS_CANONICAL(a_u64Addr)
3504
3505	/** Checks if the ModR/M byte is in register mode or not. */
3506	#define IEM_IS_MODRM_REG_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) == (3 << X86_MODRM_MOD_SHIFT) )
3507	/** Checks if the ModR/M byte is in memory mode or not. */
3508	#define IEM_IS_MODRM_MEM_MODE(a_bRm) ( ((a_bRm) & X86_MODRM_MOD_MASK) != (3 << X86_MODRM_MOD_SHIFT) )
3509
3510	/**
3511	* Gets the register (reg) part of a ModR/M encoding, with REX.R added in.
3512	*
3513	* For use during decoding.
3514	*/
3515	#define IEM_GET_MODRM_REG(a_pVCpu, a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) \| (a_pVCpu)->iem.s.uRexReg )
3516	/**
3517	* Gets the r/m part of a ModR/M encoding as a register index, with REX.B added in.
3518	*
3519	* For use during decoding.
3520	*/
3521	#define IEM_GET_MODRM_RM(a_pVCpu, a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) \| (a_pVCpu)->iem.s.uRexB )
3522
3523	/**
3524	* Gets the register (reg) part of a ModR/M encoding, without REX.R.
3525	*
3526	* For use during decoding.
3527	*/
3528	#define IEM_GET_MODRM_REG_8(a_bRm) ( (((a_bRm) >> X86_MODRM_REG_SHIFT) & X86_MODRM_REG_SMASK) )
3529	/**
3530	* Gets the r/m part of a ModR/M encoding as a register index, without REX.B.
3531	*
3532	* For use during decoding.
3533	*/
3534	#define IEM_GET_MODRM_RM_8(a_bRm) ( ((a_bRm) & X86_MODRM_RM_MASK) )
3535
3536	/**
3537	* Combines the prefix REX and ModR/M byte for passing to
3538	* iemOpHlpCalcRmEffAddrThreadedAddr64().
3539	*
3540	* @returns The ModRM byte but with bit 3 set to REX.B and bit 4 to REX.X.
3541	* The two bits are part of the REG sub-field, which isn't needed in
3542	* iemOpHlpCalcRmEffAddrThreadedAddr64().
3543	*
3544	* For use during decoding/recompiling.
3545	*/
3546	#define IEM_GET_MODRM_EX(a_pVCpu, a_bRm) \
3547	( ((a_bRm) & ~X86_MODRM_REG_MASK) \
3548	\| (uint8_t)( (pVCpu->iem.s.fPrefixes & (IEM_OP_PRF_REX_B \| IEM_OP_PRF_REX_X)) >> (26 - 3) ) )
3549	AssertCompile(IEM_OP_PRF_REX_B == RT_BIT_32(26));
3550	AssertCompile(IEM_OP_PRF_REX_X == RT_BIT_32(27));
3551
3552	/**
3553	* Gets the effective VEX.VVVV value.
3554	*
3555	* The 4th bit is ignored if not 64-bit code.
3556	* @returns effective V-register value.
3557	* @param a_pVCpu The cross context virtual CPU structure of the calling thread.
3558	*/
3559	#define IEM_GET_EFFECTIVE_VVVV(a_pVCpu) \
3560	((a_pVCpu)->iem.s.enmCpuMode == IEMMODE_64BIT ? (a_pVCpu)->iem.s.uVex3rdReg : (a_pVCpu)->iem.s.uVex3rdReg & 7)
3561
3562
3563	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
3564
3565	/**
3566	* Check if the guest has entered VMX root operation.
3567	*/
3568	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxRootMode(IEM_GET_CTX(a_pVCpu)))
3569
3570	/**
3571	* Check if the guest has entered VMX non-root operation.
3572	*/
3573	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(a_pVCpu)))
3574
3575	/**
3576	* Check if the nested-guest has the given Pin-based VM-execution control set.
3577	*/
3578	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_PinCtl) \
3579	(CPUMIsGuestVmxPinCtlsSet(IEM_GET_CTX(a_pVCpu), (a_PinCtl)))
3580
3581	/**
3582	* Check if the nested-guest has the given Processor-based VM-execution control set.
3583	*/
3584	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_ProcCtl) \
3585	(CPUMIsGuestVmxProcCtlsSet(IEM_GET_CTX(a_pVCpu), (a_ProcCtl)))
3586
3587	/**
3588	* Check if the nested-guest has the given Secondary Processor-based VM-execution
3589	* control set.
3590	*/
3591	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_ProcCtl2) \
3592	(CPUMIsGuestVmxProcCtls2Set(IEM_GET_CTX(a_pVCpu), (a_ProcCtl2)))
3593
3594	/** Gets the guest-physical address of the shadows VMCS for the given VCPU. */
3595	# define IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysShadowVmcs)
3596
3597	/** Whether a shadow VMCS is present for the given VCPU. */
3598	# define IEM_VMX_HAS_SHADOW_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_SHADOW_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3599
3600	/** Gets the VMXON region pointer. */
3601	# define IEM_VMX_GET_VMXON_PTR(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmxon)
3602
3603	/** Gets the guest-physical address of the current VMCS for the given VCPU. */
3604	# define IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) ((a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs)
3605
3606	/** Whether a current VMCS is present for the given VCPU. */
3607	# define IEM_VMX_HAS_CURRENT_VMCS(a_pVCpu) RT_BOOL(IEM_VMX_GET_CURRENT_VMCS(a_pVCpu) != NIL_RTGCPHYS)
3608
3609	/** Assigns the guest-physical address of the current VMCS for the given VCPU. */
3610	# define IEM_VMX_SET_CURRENT_VMCS(a_pVCpu, a_GCPhysVmcs) \
3611	do \
3612	{ \
3613	Assert((a_GCPhysVmcs) != NIL_RTGCPHYS); \
3614	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = (a_GCPhysVmcs); \
3615	} while (0)
3616
3617	/** Clears any current VMCS for the given VCPU. */
3618	# define IEM_VMX_CLEAR_CURRENT_VMCS(a_pVCpu) \
3619	do \
3620	{ \
3621	(a_pVCpu)->cpum.GstCtx.hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS; \
3622	} while (0)
3623
3624	/**
3625	* Invokes the VMX VM-exit handler for an instruction intercept.
3626	*/
3627	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) \
3628	do { return iemVmxVmexitInstr((a_pVCpu), (a_uExitReason), (a_cbInstr)); } while (0)
3629
3630	/**
3631	* Invokes the VMX VM-exit handler for an instruction intercept where the
3632	* instruction provides additional VM-exit information.
3633	*/
3634	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) \
3635	do { return iemVmxVmexitInstrNeedsInfo((a_pVCpu), (a_uExitReason), (a_uInstrId), (a_cbInstr)); } while (0)
3636
3637	/**
3638	* Invokes the VMX VM-exit handler for a task switch.
3639	*/
3640	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) \
3641	do { return iemVmxVmexitTaskSwitch((a_pVCpu), (a_enmTaskSwitch), (a_SelNewTss), (a_cbInstr)); } while (0)
3642
3643	/**
3644	* Invokes the VMX VM-exit handler for MWAIT.
3645	*/
3646	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) \
3647	do { return iemVmxVmexitInstrMwait((a_pVCpu), (a_fMonitorArmed), (a_cbInstr)); } while (0)
3648
3649	/**
3650	* Invokes the VMX VM-exit handler for EPT faults.
3651	*/
3652	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) \
3653	do { return iemVmxVmexitEpt(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr); } while (0)
3654
3655	/**
3656	* Invokes the VMX VM-exit handler.
3657	*/
3658	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) \
3659	do { return iemVmxVmexit((a_pVCpu), (a_uExitReason), (a_uExitQual)); } while (0)
3660
3661	#else
3662	# define IEM_VMX_IS_ROOT_MODE(a_pVCpu) (false)
3663	# define IEM_VMX_IS_NON_ROOT_MODE(a_pVCpu) (false)
3664	# define IEM_VMX_IS_PINCTLS_SET(a_pVCpu, a_cbInstr) (false)
3665	# define IEM_VMX_IS_PROCCTLS_SET(a_pVCpu, a_cbInstr) (false)
3666	# define IEM_VMX_IS_PROCCTLS2_SET(a_pVCpu, a_cbInstr) (false)
3667	# define IEM_VMX_VMEXIT_INSTR_RET(a_pVCpu, a_uExitReason, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3668	# define IEM_VMX_VMEXIT_INSTR_NEEDS_INFO_RET(a_pVCpu, a_uExitReason, a_uInstrId, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3669	# define IEM_VMX_VMEXIT_TASK_SWITCH_RET(a_pVCpu, a_enmTaskSwitch, a_SelNewTss, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3670	# define IEM_VMX_VMEXIT_MWAIT_RET(a_pVCpu, a_fMonitorArmed, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3671	# define IEM_VMX_VMEXIT_EPT_RET(a_pVCpu, a_pPtWalk, a_fAccess, a_fSlatFail, a_cbInstr) do { return VERR_VMX_IPE_1; } while (0)
3672	# define IEM_VMX_VMEXIT_TRIPLE_FAULT_RET(a_pVCpu, a_uExitReason, a_uExitQual) do { return VERR_VMX_IPE_1; } while (0)
3673
3674	#endif
3675
3676	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
3677	/**
3678	* Check if an SVM control/instruction intercept is set.
3679	*/
3680	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) \
3681	(CPUMIsGuestSvmCtrlInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_Intercept)))
3682
3683	/**
3684	* Check if an SVM read CRx intercept is set.
3685	*/
3686	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3687	(CPUMIsGuestSvmReadCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3688
3689	/**
3690	* Check if an SVM write CRx intercept is set.
3691	*/
3692	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) \
3693	(CPUMIsGuestSvmWriteCRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uCr)))
3694
3695	/**
3696	* Check if an SVM read DRx intercept is set.
3697	*/
3698	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3699	(CPUMIsGuestSvmReadDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3700
3701	/**
3702	* Check if an SVM write DRx intercept is set.
3703	*/
3704	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) \
3705	(CPUMIsGuestSvmWriteDRxInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uDr)))
3706
3707	/**
3708	* Check if an SVM exception intercept is set.
3709	*/
3710	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) \
3711	(CPUMIsGuestSvmXcptInterceptSet(a_pVCpu, IEM_GET_CTX(a_pVCpu), (a_uVector)))
3712
3713	/**
3714	* Invokes the SVM \#VMEXIT handler for the nested-guest.
3715	*/
3716	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3717	do { return iemSvmVmexit((a_pVCpu), (a_uExitCode), (a_uExitInfo1), (a_uExitInfo2)); } while (0)
3718
3719	/**
3720	* Invokes the 'MOV CRx' SVM \#VMEXIT handler after constructing the
3721	* corresponding decode assist information.
3722	*/
3723	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) \
3724	do \
3725	{ \
3726	uint64_t uExitInfo1; \
3727	if ( IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmDecodeAssists \
3728	&& (a_enmAccessCrX) == IEMACCESSCRX_MOV_CRX) \
3729	uExitInfo1 = SVM_EXIT1_MOV_CRX_MASK \| ((a_iGReg) & 7); \
3730	else \
3731	uExitInfo1 = 0; \
3732	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, uExitInfo1, 0); \
3733	} while (0)
3734
3735	/** Check and handles SVM nested-guest instruction intercept and updates
3736	* NRIP if needed.
3737	*/
3738	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) \
3739	do \
3740	{ \
3741	if (IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept)) \
3742	{ \
3743	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3744	IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2); \
3745	} \
3746	} while (0)
3747
3748	/** Checks and handles SVM nested-guest CR0 read intercept. */
3749	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) \
3750	do \
3751	{ \
3752	if (!IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, 0)) \
3753	{ /* probably likely */ } \
3754	else \
3755	{ \
3756	IEM_SVM_UPDATE_NRIP(a_pVCpu); \
3757	IEM_SVM_VMEXIT_RET(a_pVCpu, SVM_EXIT_READ_CR0, a_uExitInfo1, a_uExitInfo2); \
3758	} \
3759	} while (0)
3760
3761	/**
3762	* Updates the NextRIP (NRI) field in the nested-guest VMCB.
3763	*/
3764	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) \
3765	do { \
3766	if (IEM_GET_GUEST_CPU_FEATURES(a_pVCpu)->fSvmNextRipSave) \
3767	CPUMGuestSvmUpdateNRip(a_pVCpu, IEM_GET_CTX(a_pVCpu), IEM_GET_INSTR_LEN(a_pVCpu)); \
3768	} while (0)
3769
3770	#else
3771	# define IEM_SVM_IS_CTRL_INTERCEPT_SET(a_pVCpu, a_Intercept) (false)
3772	# define IEM_SVM_IS_READ_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3773	# define IEM_SVM_IS_WRITE_CR_INTERCEPT_SET(a_pVCpu, a_uCr) (false)
3774	# define IEM_SVM_IS_READ_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3775	# define IEM_SVM_IS_WRITE_DR_INTERCEPT_SET(a_pVCpu, a_uDr) (false)
3776	# define IEM_SVM_IS_XCPT_INTERCEPT_SET(a_pVCpu, a_uVector) (false)
3777	# define IEM_SVM_VMEXIT_RET(a_pVCpu, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { return VERR_SVM_IPE_1; } while (0)
3778	# define IEM_SVM_CRX_VMEXIT_RET(a_pVCpu, a_uExitCode, a_enmAccessCrX, a_iGReg) do { return VERR_SVM_IPE_1; } while (0)
3779	# define IEM_SVM_CHECK_INSTR_INTERCEPT(a_pVCpu, a_Intercept, a_uExitCode, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3780	# define IEM_SVM_CHECK_READ_CR0_INTERCEPT(a_pVCpu, a_uExitInfo1, a_uExitInfo2) do { } while (0)
3781	# define IEM_SVM_UPDATE_NRIP(a_pVCpu) do { } while (0)
3782
3783	#endif
3784
3785	/** @} */
3786
3787	void iemInitPendingBreakpointsSlow(PVMCPUCC pVCpu);
3788
3789
3790	/**
3791	* Selector descriptor table entry as fetched by iemMemFetchSelDesc.
3792	*/
3793	typedef union IEMSELDESC
3794	{
3795	/** The legacy view. */
3796	X86DESC Legacy;
3797	/** The long mode view. */
3798	X86DESC64 Long;
3799	} IEMSELDESC;
3800	/** Pointer to a selector descriptor table entry. */
3801	typedef IEMSELDESC *PIEMSELDESC;
3802
3803	/** @name Raising Exceptions.
3804	* @{ */
3805	VBOXSTRICTRC iemTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, uint32_t uNextEip, uint32_t fFlags,
3806	uint16_t uErr, uint64_t uCr2, RTSEL SelTSS, PIEMSELDESC pNewDescTSS) RT_NOEXCEPT;
3807
3808	VBOXSTRICTRC iemRaiseXcptOrInt(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector, uint32_t fFlags,
3809	uint16_t uErr, uint64_t uCr2) RT_NOEXCEPT;
3810	#ifdef IEM_WITH_SETJMP
3811	DECL_NO_RETURN(void) iemRaiseXcptOrIntJmp(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t u8Vector,
3812	uint32_t fFlags, uint16_t uErr, uint64_t uCr2) IEM_NOEXCEPT_MAY_LONGJMP;
3813	#endif
3814	VBOXSTRICTRC iemRaiseDivideError(PVMCPUCC pVCpu) RT_NOEXCEPT;
3815	VBOXSTRICTRC iemRaiseDebugException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3816	VBOXSTRICTRC iemRaiseBoundRangeExceeded(PVMCPUCC pVCpu) RT_NOEXCEPT;
3817	VBOXSTRICTRC iemRaiseUndefinedOpcode(PVMCPUCC pVCpu) RT_NOEXCEPT;
3818	VBOXSTRICTRC iemRaiseDeviceNotAvailable(PVMCPUCC pVCpu) RT_NOEXCEPT;
3819	VBOXSTRICTRC iemRaiseTaskSwitchFaultWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3820	VBOXSTRICTRC iemRaiseTaskSwitchFaultCurrentTSS(PVMCPUCC pVCpu) RT_NOEXCEPT;
3821	VBOXSTRICTRC iemRaiseTaskSwitchFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3822	VBOXSTRICTRC iemRaiseTaskSwitchFaultBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3823	/VBOXSTRICTRC iemRaiseSelectorNotPresent(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;/
3824	VBOXSTRICTRC iemRaiseSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3825	VBOXSTRICTRC iemRaiseSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3826	VBOXSTRICTRC iemRaiseStackSelectorNotPresentBySelector(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3827	VBOXSTRICTRC iemRaiseStackSelectorNotPresentWithErr(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3828	VBOXSTRICTRC iemRaiseGeneralProtectionFault(PVMCPUCC pVCpu, uint16_t uErr) RT_NOEXCEPT;
3829	VBOXSTRICTRC iemRaiseGeneralProtectionFault0(PVMCPUCC pVCpu) RT_NOEXCEPT;
3830	#ifdef IEM_WITH_SETJMP
3831	DECL_NO_RETURN(void) iemRaiseGeneralProtectionFault0Jmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3832	#endif
3833	VBOXSTRICTRC iemRaiseGeneralProtectionFaultBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3834	VBOXSTRICTRC iemRaiseNotCanonical(PVMCPUCC pVCpu) RT_NOEXCEPT;
3835	VBOXSTRICTRC iemRaiseSelectorBounds(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3836	#ifdef IEM_WITH_SETJMP
3837	DECL_NO_RETURN(void) iemRaiseSelectorBoundsJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
3838	#endif
3839	VBOXSTRICTRC iemRaiseSelectorBoundsBySelector(PVMCPUCC pVCpu, RTSEL Sel) RT_NOEXCEPT;
3840	#ifdef IEM_WITH_SETJMP
3841	DECL_NO_RETURN(void) iemRaiseSelectorBoundsBySelectorJmp(PVMCPUCC pVCpu, RTSEL Sel) IEM_NOEXCEPT_MAY_LONGJMP;
3842	#endif
3843	VBOXSTRICTRC iemRaiseSelectorInvalidAccess(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) RT_NOEXCEPT;
3844	#ifdef IEM_WITH_SETJMP
3845	DECL_NO_RETURN(void) iemRaiseSelectorInvalidAccessJmp(PVMCPUCC pVCpu, uint32_t iSegReg, uint32_t fAccess) IEM_NOEXCEPT_MAY_LONGJMP;
3846	#endif
3847	VBOXSTRICTRC iemRaisePageFault(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) RT_NOEXCEPT;
3848	#ifdef IEM_WITH_SETJMP
3849	DECL_NO_RETURN(void) iemRaisePageFaultJmp(PVMCPUCC pVCpu, RTGCPTR GCPtrWhere, uint32_t cbAccess, uint32_t fAccess, int rc) IEM_NOEXCEPT_MAY_LONGJMP;
3850	#endif
3851	VBOXSTRICTRC iemRaiseMathFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
3852	VBOXSTRICTRC iemRaiseAlignmentCheckException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3853	#ifdef IEM_WITH_SETJMP
3854	DECL_NO_RETURN(void) iemRaiseAlignmentCheckExceptionJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3855	#endif
3856	VBOXSTRICTRC iemRaiseSimdFpException(PVMCPUCC pVCpu) RT_NOEXCEPT;
3857
3858	IEM_CIMPL_DEF_0(iemCImplRaiseDivideError);
3859	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidLockPrefix);
3860	IEM_CIMPL_DEF_0(iemCImplRaiseInvalidOpcode);
3861
3862	/**
3863	* Macro for calling iemCImplRaiseDivideError().
3864	*
3865	* This enables us to add/remove arguments and force different levels of
3866	* inlining as we wish.
3867	*
3868	* @return Strict VBox status code.
3869	*/
3870	#define IEMOP_RAISE_DIVIDE_ERROR() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseDivideError)
3871
3872	/**
3873	* Macro for calling iemCImplRaiseInvalidLockPrefix().
3874	*
3875	* This enables us to add/remove arguments and force different levels of
3876	* inlining as we wish.
3877	*
3878	* @return Strict VBox status code.
3879	*/
3880	#define IEMOP_RAISE_INVALID_LOCK_PREFIX() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidLockPrefix)
3881
3882	/**
3883	* Macro for calling iemCImplRaiseInvalidOpcode().
3884	*
3885	* This enables us to add/remove arguments and force different levels of
3886	* inlining as we wish.
3887	*
3888	* @return Strict VBox status code.
3889	*/
3890	#define IEMOP_RAISE_INVALID_OPCODE() IEM_MC_DEFER_TO_CIMPL_0(iemCImplRaiseInvalidOpcode)
3891	/** @} */
3892
3893	/** @name Register Access.
3894	* @{ */
3895	VBOXSTRICTRC iemRegRipRelativeJumpS8AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int8_t offNextInstr,
3896	IEMMODE enmEffOpSize) RT_NOEXCEPT;
3897	VBOXSTRICTRC iemRegRipRelativeJumpS16AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int16_t offNextInstr) RT_NOEXCEPT;
3898	VBOXSTRICTRC iemRegRipRelativeJumpS32AndFinishClearingRF(PVMCPUCC pVCpu, uint8_t cbInstr, int32_t offNextInstr,
3899	IEMMODE enmEffOpSize) RT_NOEXCEPT;
3900	VBOXSTRICTRC iemRegRipJumpU16AndFinishClearningRF(PVMCPUCC pVCpu, uint16_t uNewRip) RT_NOEXCEPT;
3901	VBOXSTRICTRC iemRegRipJumpU32AndFinishClearningRF(PVMCPUCC pVCpu, uint32_t uNewRip) RT_NOEXCEPT;
3902	VBOXSTRICTRC iemRegRipJumpU64AndFinishClearningRF(PVMCPUCC pVCpu, uint64_t uNewRip) RT_NOEXCEPT;
3903	/** @} */
3904
3905	/** @name FPU access and helpers.
3906	* @{ */
3907	void iemFpuPushResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult) RT_NOEXCEPT;
3908	void iemFpuPushResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3909	void iemFpuPushResultTwo(PVMCPUCC pVCpu, PIEMFPURESULTTWO pResult) RT_NOEXCEPT;
3910	void iemFpuStoreResult(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3911	void iemFpuStoreResultThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg) RT_NOEXCEPT;
3912	void iemFpuStoreResultWithMemOp(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3913	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3914	void iemFpuStoreResultWithMemOpThenPop(PVMCPUCC pVCpu, PIEMFPURESULT pResult, uint8_t iStReg,
3915	uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3916	void iemFpuUpdateOpcodeAndIp(PVMCPUCC pVCpu) RT_NOEXCEPT;
3917	void iemFpuUpdateFSW(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3918	void iemFpuUpdateFSWThenPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3919	void iemFpuUpdateFSWWithMemOp(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3920	void iemFpuUpdateFSWThenPopPop(PVMCPUCC pVCpu, uint16_t u16FSW) RT_NOEXCEPT;
3921	void iemFpuUpdateFSWWithMemOpThenPop(PVMCPUCC pVCpu, uint16_t u16FSW, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3922	void iemFpuStackUnderflow(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3923	void iemFpuStackUnderflowWithMemOp(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3924	void iemFpuStackUnderflowThenPop(PVMCPUCC pVCpu, uint8_t iStReg) RT_NOEXCEPT;
3925	void iemFpuStackUnderflowWithMemOpThenPop(PVMCPUCC pVCpu, uint8_t iStReg, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3926	void iemFpuStackUnderflowThenPopPop(PVMCPUCC pVCpu) RT_NOEXCEPT;
3927	void iemFpuStackPushUnderflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3928	void iemFpuStackPushUnderflowTwo(PVMCPUCC pVCpu) RT_NOEXCEPT;
3929	void iemFpuStackPushOverflow(PVMCPUCC pVCpu) RT_NOEXCEPT;
3930	void iemFpuStackPushOverflowWithMemOp(PVMCPUCC pVCpu, uint8_t iEffSeg, RTGCPTR GCPtrEff) RT_NOEXCEPT;
3931	/** @} */
3932
3933	/** @name SSE+AVX SIMD access and helpers.
3934	* @{ */
3935	void iemSseStoreResult(PVMCPUCC pVCpu, PCIEMSSERESULT pResult, uint8_t iXmmReg) RT_NOEXCEPT;
3936	void iemSseUpdateMxcsr(PVMCPUCC pVCpu, uint32_t fMxcsr) RT_NOEXCEPT;
3937	/** @} */
3938
3939	/** @name Memory access.
3940	* @{ */
3941
3942	/** Report a \#GP instead of \#AC and do not restrict to ring-3 */
3943	#define IEM_MEMMAP_F_ALIGN_GP RT_BIT_32(16)
3944	/** SSE access that should report a \#GP instead of \#AC, unless MXCSR.MM=1
3945	* when it works like normal \#AC. Always used with IEM_MEMMAP_F_ALIGN_GP. */
3946	#define IEM_MEMMAP_F_ALIGN_SSE RT_BIT_32(17)
3947	/** If \#AC is applicable, raise it. Always used with IEM_MEMMAP_F_ALIGN_GP.
3948	* Users include FXSAVE & FXRSTOR. */
3949	#define IEM_MEMMAP_F_ALIGN_GP_OR_AC RT_BIT_32(18)
3950
3951	VBOXSTRICTRC iemMemMap(PVMCPUCC pVCpu, void **ppvMem, size_t cbMem, uint8_t iSegReg, RTGCPTR GCPtrMem,
3952	uint32_t fAccess, uint32_t uAlignCtl) RT_NOEXCEPT;
3953	VBOXSTRICTRC iemMemCommitAndUnmap(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3954	#ifndef IN_RING3
3955	VBOXSTRICTRC iemMemCommitAndUnmapPostponeTroubleToR3(PVMCPUCC pVCpu, void *pvMem, uint32_t fAccess) RT_NOEXCEPT;
3956	#endif
3957	void iemMemRollback(PVMCPUCC pVCpu) RT_NOEXCEPT;
3958	VBOXSTRICTRC iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
3959	VBOXSTRICTRC iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
3960	VBOXSTRICTRC iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
3961
3962	#ifdef IEM_WITH_CODE_TLB
3963	void iemOpcodeFetchBytesJmp(PVMCPUCC pVCpu, size_t cbDst, void *pvDst) IEM_NOEXCEPT_MAY_LONGJMP;
3964	#else
3965	VBOXSTRICTRC iemOpcodeFetchMoreBytes(PVMCPUCC pVCpu, size_t cbMin) RT_NOEXCEPT;
3966	#endif
3967	#ifdef IEM_WITH_SETJMP
3968	uint8_t iemOpcodeGetNextU8SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3969	uint16_t iemOpcodeGetNextU16SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3970	uint32_t iemOpcodeGetNextU32SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3971	uint64_t iemOpcodeGetNextU64SlowJmp(PVMCPUCC pVCpu) IEM_NOEXCEPT_MAY_LONGJMP;
3972	#else
3973	VBOXSTRICTRC iemOpcodeGetNextU8Slow(PVMCPUCC pVCpu, uint8_t *pb) RT_NOEXCEPT;
3974	VBOXSTRICTRC iemOpcodeGetNextS8SxU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3975	VBOXSTRICTRC iemOpcodeGetNextS8SxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3976	VBOXSTRICTRC iemOpcodeGetNextS8SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3977	VBOXSTRICTRC iemOpcodeGetNextU16Slow(PVMCPUCC pVCpu, uint16_t *pu16) RT_NOEXCEPT;
3978	VBOXSTRICTRC iemOpcodeGetNextU16ZxU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3979	VBOXSTRICTRC iemOpcodeGetNextU16ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3980	VBOXSTRICTRC iemOpcodeGetNextU32Slow(PVMCPUCC pVCpu, uint32_t *pu32) RT_NOEXCEPT;
3981	VBOXSTRICTRC iemOpcodeGetNextU32ZxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3982	VBOXSTRICTRC iemOpcodeGetNextS32SxU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3983	VBOXSTRICTRC iemOpcodeGetNextU64Slow(PVMCPUCC pVCpu, uint64_t *pu64) RT_NOEXCEPT;
3984	#endif
3985
3986	VBOXSTRICTRC iemMemFetchDataU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3987	VBOXSTRICTRC iemMemFetchDataU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3988	VBOXSTRICTRC iemMemFetchDataU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3989	VBOXSTRICTRC iemMemFetchDataU32_ZX_U64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3990	VBOXSTRICTRC iemMemFetchDataU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3991	VBOXSTRICTRC iemMemFetchDataU64AlignedU128(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3992	VBOXSTRICTRC iemMemFetchDataR80(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3993	VBOXSTRICTRC iemMemFetchDataD80(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3994	VBOXSTRICTRC iemMemFetchDataU128(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3995	VBOXSTRICTRC iemMemFetchDataU128AlignedSse(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3996	VBOXSTRICTRC iemMemFetchDataU256(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3997	VBOXSTRICTRC iemMemFetchDataU256AlignedSse(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
3998	VBOXSTRICTRC iemMemFetchDataXdtr(PVMCPUCC pVCpu, uint16_t *pcbLimit, PRTGCPTR pGCPtrBase, uint8_t iSegReg,
3999	RTGCPTR GCPtrMem, IEMMODE enmOpSize) RT_NOEXCEPT;
4000	#ifdef IEM_WITH_SETJMP
4001	uint8_t iemMemFetchDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4002	uint16_t iemMemFetchDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4003	uint32_t iemMemFetchDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4004	uint64_t iemMemFetchDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4005	uint64_t iemMemFetchDataU64AlignedU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4006	void iemMemFetchDataR80Jmp(PVMCPUCC pVCpu, PRTFLOAT80U pr80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4007	void iemMemFetchDataD80Jmp(PVMCPUCC pVCpu, PRTPBCD80U pd80Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4008	void iemMemFetchDataU128Jmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4009	void iemMemFetchDataU128AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT128U pu128Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4010	void iemMemFetchDataU256Jmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4011	void iemMemFetchDataU256AlignedSseJmp(PVMCPUCC pVCpu, PRTUINT256U pu256Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) IEM_NOEXCEPT_MAY_LONGJMP;
4012	#endif
4013
4014	VBOXSTRICTRC iemMemFetchSysU8(PVMCPUCC pVCpu, uint8_t *pu8Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4015	VBOXSTRICTRC iemMemFetchSysU16(PVMCPUCC pVCpu, uint16_t *pu16Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4016	VBOXSTRICTRC iemMemFetchSysU32(PVMCPUCC pVCpu, uint32_t *pu32Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4017	VBOXSTRICTRC iemMemFetchSysU64(PVMCPUCC pVCpu, uint64_t *pu64Dst, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4018	VBOXSTRICTRC iemMemFetchSelDesc(PVMCPUCC pVCpu, PIEMSELDESC pDesc, uint16_t uSel, uint8_t uXcpt) RT_NOEXCEPT;
4019
4020	VBOXSTRICTRC iemMemStoreDataU8(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) RT_NOEXCEPT;
4021	VBOXSTRICTRC iemMemStoreDataU16(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) RT_NOEXCEPT;
4022	VBOXSTRICTRC iemMemStoreDataU32(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) RT_NOEXCEPT;
4023	VBOXSTRICTRC iemMemStoreDataU64(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) RT_NOEXCEPT;
4024	VBOXSTRICTRC iemMemStoreDataU128(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4025	VBOXSTRICTRC iemMemStoreDataU128AlignedSse(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) RT_NOEXCEPT;
4026	VBOXSTRICTRC iemMemStoreDataU256(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4027	VBOXSTRICTRC iemMemStoreDataU256AlignedAvx(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) RT_NOEXCEPT;
4028	VBOXSTRICTRC iemMemStoreDataXdtr(PVMCPUCC pVCpu, uint16_t cbLimit, RTGCPTR GCPtrBase, uint8_t iSegReg, RTGCPTR GCPtrMem) RT_NOEXCEPT;
4029	#ifdef IEM_WITH_SETJMP
4030	void iemMemStoreDataU8Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint8_t u8Value) IEM_NOEXCEPT_MAY_LONGJMP;
4031	void iemMemStoreDataU16Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint16_t u16Value) IEM_NOEXCEPT_MAY_LONGJMP;
4032	void iemMemStoreDataU32Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint32_t u32Value) IEM_NOEXCEPT_MAY_LONGJMP;
4033	void iemMemStoreDataU64Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, uint64_t u64Value) IEM_NOEXCEPT_MAY_LONGJMP;
4034	void iemMemStoreDataU128Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4035	void iemMemStoreDataU128AlignedSseJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, RTUINT128U u128Value) IEM_NOEXCEPT_MAY_LONGJMP;
4036	void iemMemStoreDataU256Jmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4037	void iemMemStoreDataU256AlignedAvxJmp(PVMCPUCC pVCpu, uint8_t iSegReg, RTGCPTR GCPtrMem, PCRTUINT256U pu256Value) IEM_NOEXCEPT_MAY_LONGJMP;
4038	#endif
4039
4040	VBOXSTRICTRC iemMemStackPushBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4041	void *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4042	VBOXSTRICTRC iemMemStackPushCommitSpecial(PVMCPUCC pVCpu, void *pvMem, uint64_t uNewRsp) RT_NOEXCEPT;
4043	VBOXSTRICTRC iemMemStackPushU16(PVMCPUCC pVCpu, uint16_t u16Value) RT_NOEXCEPT;
4044	VBOXSTRICTRC iemMemStackPushU32(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4045	VBOXSTRICTRC iemMemStackPushU64(PVMCPUCC pVCpu, uint64_t u64Value) RT_NOEXCEPT;
4046	VBOXSTRICTRC iemMemStackPushU16Ex(PVMCPUCC pVCpu, uint16_t u16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4047	VBOXSTRICTRC iemMemStackPushU32Ex(PVMCPUCC pVCpu, uint32_t u32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4048	VBOXSTRICTRC iemMemStackPushU64Ex(PVMCPUCC pVCpu, uint64_t u64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4049	VBOXSTRICTRC iemMemStackPushU32SReg(PVMCPUCC pVCpu, uint32_t u32Value) RT_NOEXCEPT;
4050	VBOXSTRICTRC iemMemStackPopBeginSpecial(PVMCPUCC pVCpu, size_t cbMem, uint32_t cbAlign,
4051	void const *ppvMem, uint64_t puNewRsp) RT_NOEXCEPT;
4052	VBOXSTRICTRC iemMemStackPopContinueSpecial(PVMCPUCC pVCpu, size_t off, size_t cbMem,
4053	void const **ppvMem, uint64_t uCurNewRsp) RT_NOEXCEPT;
4054	VBOXSTRICTRC iemMemStackPopDoneSpecial(PVMCPUCC pVCpu, void const *pvMem) RT_NOEXCEPT;
4055	VBOXSTRICTRC iemMemStackPopU16(PVMCPUCC pVCpu, uint16_t *pu16Value) RT_NOEXCEPT;
4056	VBOXSTRICTRC iemMemStackPopU32(PVMCPUCC pVCpu, uint32_t *pu32Value) RT_NOEXCEPT;
4057	VBOXSTRICTRC iemMemStackPopU64(PVMCPUCC pVCpu, uint64_t *pu64Value) RT_NOEXCEPT;
4058	VBOXSTRICTRC iemMemStackPopU16Ex(PVMCPUCC pVCpu, uint16_t *pu16Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4059	VBOXSTRICTRC iemMemStackPopU32Ex(PVMCPUCC pVCpu, uint32_t *pu32Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4060	VBOXSTRICTRC iemMemStackPopU64Ex(PVMCPUCC pVCpu, uint64_t *pu64Value, PRTUINT64U pTmpRsp) RT_NOEXCEPT;
4061	/** @} */
4062
4063	/** @name IEMAllCImpl.cpp
4064	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/'
4065	* @{ */
4066	IEM_CIMPL_PROTO_0(iemCImpl_popa_16);
4067	IEM_CIMPL_PROTO_0(iemCImpl_popa_32);
4068	IEM_CIMPL_PROTO_0(iemCImpl_pusha_16);
4069	IEM_CIMPL_PROTO_0(iemCImpl_pusha_32);
4070	IEM_CIMPL_PROTO_1(iemCImpl_pushf, IEMMODE, enmEffOpSize);
4071	IEM_CIMPL_PROTO_1(iemCImpl_popf, IEMMODE, enmEffOpSize);
4072	IEM_CIMPL_PROTO_1(iemCImpl_call_16, uint16_t, uNewPC);
4073	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_16, int16_t, offDisp);
4074	IEM_CIMPL_PROTO_1(iemCImpl_call_32, uint32_t, uNewPC);
4075	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_32, int32_t, offDisp);
4076	IEM_CIMPL_PROTO_1(iemCImpl_call_64, uint64_t, uNewPC);
4077	IEM_CIMPL_PROTO_1(iemCImpl_call_rel_64, int64_t, offDisp);
4078	IEM_CIMPL_PROTO_3(iemCImpl_FarJmp, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4079	IEM_CIMPL_PROTO_3(iemCImpl_callf, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4080	typedef IEM_CIMPL_DECL_TYPE_3(FNIEMCIMPLFARBRANCH, uint16_t, uSel, uint64_t, offSeg, IEMMODE, enmEffOpSize);
4081	typedef FNIEMCIMPLFARBRANCH *PFNIEMCIMPLFARBRANCH;
4082	IEM_CIMPL_PROTO_2(iemCImpl_retf, IEMMODE, enmEffOpSize, uint16_t, cbPop);
4083	IEM_CIMPL_PROTO_0(iemCImpl_retn_16);
4084	IEM_CIMPL_PROTO_0(iemCImpl_retn_32);
4085	IEM_CIMPL_PROTO_0(iemCImpl_retn_64);
4086	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_16, uint16_t, cbPop);
4087	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_32, uint16_t, cbPop);
4088	IEM_CIMPL_PROTO_1(iemCImpl_retn_iw_64, uint16_t, cbPop);
4089	IEM_CIMPL_PROTO_3(iemCImpl_enter, IEMMODE, enmEffOpSize, uint16_t, cbFrame, uint8_t, cParameters);
4090	IEM_CIMPL_PROTO_1(iemCImpl_leave, IEMMODE, enmEffOpSize);
4091	IEM_CIMPL_PROTO_2(iemCImpl_int, uint8_t, u8Int, IEMINT, enmInt);
4092	IEM_CIMPL_PROTO_1(iemCImpl_iret_real_v8086, IEMMODE, enmEffOpSize);
4093	IEM_CIMPL_PROTO_4(iemCImpl_iret_prot_v8086, uint32_t, uNewEip, uint16_t, uNewCs, uint32_t, uNewFlags, uint64_t, uNewRsp);
4094	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot_NestedTask, IEMMODE, enmEffOpSize);
4095	IEM_CIMPL_PROTO_1(iemCImpl_iret_prot, IEMMODE, enmEffOpSize);
4096	IEM_CIMPL_PROTO_1(iemCImpl_iret_64bit, IEMMODE, enmEffOpSize);
4097	IEM_CIMPL_PROTO_1(iemCImpl_iret, IEMMODE, enmEffOpSize);
4098	IEM_CIMPL_PROTO_0(iemCImpl_loadall286);
4099	IEM_CIMPL_PROTO_0(iemCImpl_syscall);
4100	IEM_CIMPL_PROTO_0(iemCImpl_sysret);
4101	IEM_CIMPL_PROTO_0(iemCImpl_sysenter);
4102	IEM_CIMPL_PROTO_1(iemCImpl_sysexit, IEMMODE, enmEffOpSize);
4103	IEM_CIMPL_PROTO_2(iemCImpl_LoadSReg, uint8_t, iSegReg, uint16_t, uSel);
4104	IEM_CIMPL_PROTO_2(iemCImpl_load_SReg, uint8_t, iSegReg, uint16_t, uSel);
4105	IEM_CIMPL_PROTO_2(iemCImpl_pop_Sreg, uint8_t, iSegReg, IEMMODE, enmEffOpSize);
4106	IEM_CIMPL_PROTO_5(iemCImpl_load_SReg_Greg, uint16_t, uSel, uint64_t, offSeg, uint8_t, iSegReg, uint8_t, iGReg, IEMMODE, enmEffOpSize);
4107	IEM_CIMPL_PROTO_2(iemCImpl_VerX, uint16_t, uSel, bool, fWrite);
4108	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u64, uint64_t *, pu64Dst, uint16_t, uSel, bool, fIsLar);
4109	IEM_CIMPL_PROTO_3(iemCImpl_LarLsl_u16, uint16_t *, pu16Dst, uint16_t, uSel, bool, fIsLar);
4110	IEM_CIMPL_PROTO_3(iemCImpl_lgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4111	IEM_CIMPL_PROTO_2(iemCImpl_sgdt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4112	IEM_CIMPL_PROTO_3(iemCImpl_lidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc, IEMMODE, enmEffOpSize);
4113	IEM_CIMPL_PROTO_2(iemCImpl_sidt, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4114	IEM_CIMPL_PROTO_1(iemCImpl_lldt, uint16_t, uNewLdt);
4115	IEM_CIMPL_PROTO_2(iemCImpl_sldt_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4116	IEM_CIMPL_PROTO_2(iemCImpl_sldt_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4117	IEM_CIMPL_PROTO_1(iemCImpl_ltr, uint16_t, uNewTr);
4118	IEM_CIMPL_PROTO_2(iemCImpl_str_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4119	IEM_CIMPL_PROTO_2(iemCImpl_str_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4120	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Cd, uint8_t, iGReg, uint8_t, iCrReg);
4121	IEM_CIMPL_PROTO_2(iemCImpl_smsw_reg, uint8_t, iGReg, uint8_t, enmEffOpSize);
4122	IEM_CIMPL_PROTO_2(iemCImpl_smsw_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4123	IEM_CIMPL_PROTO_4(iemCImpl_load_CrX, uint8_t, iCrReg, uint64_t, uNewCrX, IEMACCESSCRX, enmAccessCrX, uint8_t, iGReg);
4124	IEM_CIMPL_PROTO_2(iemCImpl_mov_Cd_Rd, uint8_t, iCrReg, uint8_t, iGReg);
4125	IEM_CIMPL_PROTO_2(iemCImpl_lmsw, uint16_t, u16NewMsw, RTGCPTR, GCPtrEffDst);
4126	IEM_CIMPL_PROTO_0(iemCImpl_clts);
4127	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Dd, uint8_t, iGReg, uint8_t, iDrReg);
4128	IEM_CIMPL_PROTO_2(iemCImpl_mov_Dd_Rd, uint8_t, iDrReg, uint8_t, iGReg);
4129	IEM_CIMPL_PROTO_2(iemCImpl_mov_Rd_Td, uint8_t, iGReg, uint8_t, iTrReg);
4130	IEM_CIMPL_PROTO_2(iemCImpl_mov_Td_Rd, uint8_t, iTrReg, uint8_t, iGReg);
4131	IEM_CIMPL_PROTO_1(iemCImpl_invlpg, RTGCPTR, GCPtrPage);
4132	IEM_CIMPL_PROTO_3(iemCImpl_invpcid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvpcidDesc, uint64_t, uInvpcidType);
4133	IEM_CIMPL_PROTO_0(iemCImpl_invd);
4134	IEM_CIMPL_PROTO_0(iemCImpl_wbinvd);
4135	IEM_CIMPL_PROTO_0(iemCImpl_rsm);
4136	IEM_CIMPL_PROTO_0(iemCImpl_rdtsc);
4137	IEM_CIMPL_PROTO_0(iemCImpl_rdtscp);
4138	IEM_CIMPL_PROTO_0(iemCImpl_rdpmc);
4139	IEM_CIMPL_PROTO_0(iemCImpl_rdmsr);
4140	IEM_CIMPL_PROTO_0(iemCImpl_wrmsr);
4141	IEM_CIMPL_PROTO_3(iemCImpl_in, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
4142	IEM_CIMPL_PROTO_1(iemCImpl_in_eAX_DX, uint8_t, cbReg);
4143	IEM_CIMPL_PROTO_3(iemCImpl_out, uint16_t, u16Port, bool, fImm, uint8_t, cbReg);
4144	IEM_CIMPL_PROTO_1(iemCImpl_out_DX_eAX, uint8_t, cbReg);
4145	IEM_CIMPL_PROTO_0(iemCImpl_cli);
4146	IEM_CIMPL_PROTO_0(iemCImpl_sti);
4147	IEM_CIMPL_PROTO_0(iemCImpl_hlt);
4148	IEM_CIMPL_PROTO_1(iemCImpl_monitor, uint8_t, iEffSeg);
4149	IEM_CIMPL_PROTO_0(iemCImpl_mwait);
4150	IEM_CIMPL_PROTO_0(iemCImpl_swapgs);
4151	IEM_CIMPL_PROTO_0(iemCImpl_cpuid);
4152	IEM_CIMPL_PROTO_1(iemCImpl_aad, uint8_t, bImm);
4153	IEM_CIMPL_PROTO_1(iemCImpl_aam, uint8_t, bImm);
4154	IEM_CIMPL_PROTO_0(iemCImpl_daa);
4155	IEM_CIMPL_PROTO_0(iemCImpl_das);
4156	IEM_CIMPL_PROTO_0(iemCImpl_aaa);
4157	IEM_CIMPL_PROTO_0(iemCImpl_aas);
4158	IEM_CIMPL_PROTO_3(iemCImpl_bound_16, int16_t, idxArray, int16_t, idxLowerBound, int16_t, idxUpperBound);
4159	IEM_CIMPL_PROTO_3(iemCImpl_bound_32, int32_t, idxArray, int32_t, idxLowerBound, int32_t, idxUpperBound);
4160	IEM_CIMPL_PROTO_0(iemCImpl_xgetbv);
4161	IEM_CIMPL_PROTO_0(iemCImpl_xsetbv);
4162	IEM_CIMPL_PROTO_4(iemCImpl_cmpxchg16b_fallback_rendezvous, PRTUINT128U, pu128Dst, PRTUINT128U, pu128RaxRdx,
4163	PRTUINT128U, pu128RbxRcx, uint32_t *, pEFlags);
4164	IEM_CIMPL_PROTO_2(iemCImpl_clflush_clflushopt, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4165	IEM_CIMPL_PROTO_1(iemCImpl_finit, bool, fCheckXcpts);
4166	IEM_CIMPL_PROTO_3(iemCImpl_fxsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4167	IEM_CIMPL_PROTO_3(iemCImpl_fxrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4168	IEM_CIMPL_PROTO_3(iemCImpl_xsave, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4169	IEM_CIMPL_PROTO_3(iemCImpl_xrstor, uint8_t, iEffSeg, RTGCPTR, GCPtrEff, IEMMODE, enmEffOpSize);
4170	IEM_CIMPL_PROTO_2(iemCImpl_stmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4171	IEM_CIMPL_PROTO_2(iemCImpl_vstmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4172	IEM_CIMPL_PROTO_2(iemCImpl_ldmxcsr, uint8_t, iEffSeg, RTGCPTR, GCPtrEff);
4173	IEM_CIMPL_PROTO_3(iemCImpl_fnstenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4174	IEM_CIMPL_PROTO_3(iemCImpl_fnsave, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffDst);
4175	IEM_CIMPL_PROTO_3(iemCImpl_fldenv, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4176	IEM_CIMPL_PROTO_3(iemCImpl_frstor, IEMMODE, enmEffOpSize, uint8_t, iEffSeg, RTGCPTR, GCPtrEffSrc);
4177	IEM_CIMPL_PROTO_1(iemCImpl_fldcw, uint16_t, u16Fcw);
4178	IEM_CIMPL_PROTO_1(iemCImpl_fxch_underflow, uint8_t, iStReg);
4179	IEM_CIMPL_PROTO_3(iemCImpl_fcomi_fucomi, uint8_t, iStReg, PFNIEMAIMPLFPUR80EFL, pfnAImpl, bool, fPop);
4180	/** @} */
4181
4182	/** @name IEMAllCImplStrInstr.cpp.h
4183	* @note sed -e '/IEM_CIMPL_DEF_/!d' -e 's/IEM_CIMPL_DEF_/IEM_CIMPL_PROTO_/' -e 's/$/;/' -e 's/RT_CONCAT4(//' \
4184	* -e 's/,ADDR_SIZE)/64/g' -e 's/,OP_SIZE,/64/g' -e 's/,OP_rAX,/rax/g' IEMAllCImplStrInstr.cpp.h
4185	* @{ */
4186	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr16, uint8_t, iEffSeg);
4187	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr16, uint8_t, iEffSeg);
4188	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m16);
4189	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m16);
4190	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr16, uint8_t, iEffSeg);
4191	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m16);
4192	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m16, int8_t, iEffSeg);
4193	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr16, bool, fIoChecked);
4194	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr16, bool, fIoChecked);
4195	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4196	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4197
4198	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr16, uint8_t, iEffSeg);
4199	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr16, uint8_t, iEffSeg);
4200	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m16);
4201	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m16);
4202	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr16, uint8_t, iEffSeg);
4203	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m16);
4204	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m16, int8_t, iEffSeg);
4205	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr16, bool, fIoChecked);
4206	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr16, bool, fIoChecked);
4207	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4208	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4209
4210	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr16, uint8_t, iEffSeg);
4211	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr16, uint8_t, iEffSeg);
4212	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m16);
4213	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m16);
4214	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr16, uint8_t, iEffSeg);
4215	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m16);
4216	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m16, int8_t, iEffSeg);
4217	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr16, bool, fIoChecked);
4218	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr16, bool, fIoChecked);
4219	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4220	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr16, uint8_t, iEffSeg, bool, fIoChecked);
4221
4222
4223	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr32, uint8_t, iEffSeg);
4224	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr32, uint8_t, iEffSeg);
4225	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m32);
4226	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m32);
4227	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr32, uint8_t, iEffSeg);
4228	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m32);
4229	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m32, int8_t, iEffSeg);
4230	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr32, bool, fIoChecked);
4231	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr32, bool, fIoChecked);
4232	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4233	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4234
4235	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr32, uint8_t, iEffSeg);
4236	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr32, uint8_t, iEffSeg);
4237	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m32);
4238	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m32);
4239	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr32, uint8_t, iEffSeg);
4240	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m32);
4241	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m32, int8_t, iEffSeg);
4242	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr32, bool, fIoChecked);
4243	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr32, bool, fIoChecked);
4244	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4245	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4246
4247	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr32, uint8_t, iEffSeg);
4248	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr32, uint8_t, iEffSeg);
4249	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m32);
4250	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m32);
4251	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr32, uint8_t, iEffSeg);
4252	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m32);
4253	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m32, int8_t, iEffSeg);
4254	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr32, bool, fIoChecked);
4255	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr32, bool, fIoChecked);
4256	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4257	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4258
4259	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr32, uint8_t, iEffSeg);
4260	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr32, uint8_t, iEffSeg);
4261	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m32);
4262	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m32);
4263	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr32, uint8_t, iEffSeg);
4264	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m32);
4265	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m32, int8_t, iEffSeg);
4266	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr32, bool, fIoChecked);
4267	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr32, bool, fIoChecked);
4268	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4269	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr32, uint8_t, iEffSeg, bool, fIoChecked);
4270
4271
4272	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op8_addr64, uint8_t, iEffSeg);
4273	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op8_addr64, uint8_t, iEffSeg);
4274	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_al_m64);
4275	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_al_m64);
4276	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op8_addr64, uint8_t, iEffSeg);
4277	IEM_CIMPL_PROTO_0(iemCImpl_stos_al_m64);
4278	IEM_CIMPL_PROTO_1(iemCImpl_lods_al_m64, int8_t, iEffSeg);
4279	IEM_CIMPL_PROTO_1(iemCImpl_ins_op8_addr64, bool, fIoChecked);
4280	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op8_addr64, bool, fIoChecked);
4281	IEM_CIMPL_PROTO_2(iemCImpl_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4282	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op8_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4283
4284	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op16_addr64, uint8_t, iEffSeg);
4285	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op16_addr64, uint8_t, iEffSeg);
4286	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_ax_m64);
4287	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_ax_m64);
4288	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op16_addr64, uint8_t, iEffSeg);
4289	IEM_CIMPL_PROTO_0(iemCImpl_stos_ax_m64);
4290	IEM_CIMPL_PROTO_1(iemCImpl_lods_ax_m64, int8_t, iEffSeg);
4291	IEM_CIMPL_PROTO_1(iemCImpl_ins_op16_addr64, bool, fIoChecked);
4292	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op16_addr64, bool, fIoChecked);
4293	IEM_CIMPL_PROTO_2(iemCImpl_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4294	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op16_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4295
4296	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op32_addr64, uint8_t, iEffSeg);
4297	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op32_addr64, uint8_t, iEffSeg);
4298	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_eax_m64);
4299	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_eax_m64);
4300	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op32_addr64, uint8_t, iEffSeg);
4301	IEM_CIMPL_PROTO_0(iemCImpl_stos_eax_m64);
4302	IEM_CIMPL_PROTO_1(iemCImpl_lods_eax_m64, int8_t, iEffSeg);
4303	IEM_CIMPL_PROTO_1(iemCImpl_ins_op32_addr64, bool, fIoChecked);
4304	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op32_addr64, bool, fIoChecked);
4305	IEM_CIMPL_PROTO_2(iemCImpl_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4306	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op32_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4307
4308	IEM_CIMPL_PROTO_1(iemCImpl_repe_cmps_op64_addr64, uint8_t, iEffSeg);
4309	IEM_CIMPL_PROTO_1(iemCImpl_repne_cmps_op64_addr64, uint8_t, iEffSeg);
4310	IEM_CIMPL_PROTO_0(iemCImpl_repe_scas_rax_m64);
4311	IEM_CIMPL_PROTO_0(iemCImpl_repne_scas_rax_m64);
4312	IEM_CIMPL_PROTO_1(iemCImpl_rep_movs_op64_addr64, uint8_t, iEffSeg);
4313	IEM_CIMPL_PROTO_0(iemCImpl_stos_rax_m64);
4314	IEM_CIMPL_PROTO_1(iemCImpl_lods_rax_m64, int8_t, iEffSeg);
4315	IEM_CIMPL_PROTO_1(iemCImpl_ins_op64_addr64, bool, fIoChecked);
4316	IEM_CIMPL_PROTO_1(iemCImpl_rep_ins_op64_addr64, bool, fIoChecked);
4317	IEM_CIMPL_PROTO_2(iemCImpl_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4318	IEM_CIMPL_PROTO_2(iemCImpl_rep_outs_op64_addr64, uint8_t, iEffSeg, bool, fIoChecked);
4319	/** @} */
4320
4321	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
4322	VBOXSTRICTRC iemVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t u64ExitQual) RT_NOEXCEPT;
4323	VBOXSTRICTRC iemVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr) RT_NOEXCEPT;
4324	VBOXSTRICTRC iemVmxVmexitInstrNeedsInfo(PVMCPUCC pVCpu, uint32_t uExitReason, VMXINSTRID uInstrId, uint8_t cbInstr) RT_NOEXCEPT;
4325	VBOXSTRICTRC iemVmxVmexitTaskSwitch(PVMCPUCC pVCpu, IEMTASKSWITCH enmTaskSwitch, RTSEL SelNewTss, uint8_t cbInstr) RT_NOEXCEPT;
4326	VBOXSTRICTRC iemVmxVmexitEvent(PVMCPUCC pVCpu, uint8_t uVector, uint32_t fFlags, uint32_t uErrCode, uint64_t uCr2, uint8_t cbInstr) RT_NOEXCEPT;
4327	VBOXSTRICTRC iemVmxVmexitEventDoubleFault(PVMCPUCC pVCpu) RT_NOEXCEPT;
4328	VBOXSTRICTRC iemVmxVmexitEpt(PVMCPUCC pVCpu, PPGMPTWALK pWalk, uint32_t fAccess, uint32_t fSlatFail, uint8_t cbInstr) RT_NOEXCEPT;
4329	VBOXSTRICTRC iemVmxVmexitPreemptTimer(PVMCPUCC pVCpu) RT_NOEXCEPT;
4330	VBOXSTRICTRC iemVmxVmexitInstrMwait(PVMCPUCC pVCpu, bool fMonitorHwArmed, uint8_t cbInstr) RT_NOEXCEPT;
4331	VBOXSTRICTRC iemVmxVmexitInstrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port,
4332	bool fImm, uint8_t cbAccess, uint8_t cbInstr) RT_NOEXCEPT;
4333	VBOXSTRICTRC iemVmxVmexitInstrStrIo(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint16_t u16Port, uint8_t cbAccess,
4334	bool fRep, VMXEXITINSTRINFO ExitInstrInfo, uint8_t cbInstr) RT_NOEXCEPT;
4335	VBOXSTRICTRC iemVmxVmexitInstrMovDrX(PVMCPUCC pVCpu, VMXINSTRID uInstrId, uint8_t iDrReg, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4336	VBOXSTRICTRC iemVmxVmexitInstrMovToCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4337	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr8(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4338	VBOXSTRICTRC iemVmxVmexitInstrMovToCr3(PVMCPUCC pVCpu, uint64_t uNewCr3, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4339	VBOXSTRICTRC iemVmxVmexitInstrMovFromCr3(PVMCPUCC pVCpu, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4340	VBOXSTRICTRC iemVmxVmexitInstrMovToCr0Cr4(PVMCPUCC pVCpu, uint8_t iCrReg, uint64_t *puNewCrX, uint8_t iGReg, uint8_t cbInstr) RT_NOEXCEPT;
4341	VBOXSTRICTRC iemVmxVmexitInstrClts(PVMCPUCC pVCpu, uint8_t cbInstr) RT_NOEXCEPT;
4342	VBOXSTRICTRC iemVmxVmexitInstrLmsw(PVMCPUCC pVCpu, uint32_t uGuestCr0, uint16_t *pu16NewMsw,
4343	RTGCPTR GCPtrEffDst, uint8_t cbInstr) RT_NOEXCEPT;
4344	VBOXSTRICTRC iemVmxVmexitInstrInvlpg(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, uint8_t cbInstr) RT_NOEXCEPT;
4345	VBOXSTRICTRC iemVmxApicWriteEmulation(PVMCPUCC pVCpu) RT_NOEXCEPT;
4346	VBOXSTRICTRC iemVmxVirtApicAccessUnused(PVMCPUCC pVCpu, PRTGCPHYS pGCPhysAccess, size_t cbAccess, uint32_t fAccess) RT_NOEXCEPT;
4347	uint32_t iemVmxVirtApicReadRaw32(PVMCPUCC pVCpu, uint16_t offReg) RT_NOEXCEPT;
4348	void iemVmxVirtApicWriteRaw32(PVMCPUCC pVCpu, uint16_t offReg, uint32_t uReg) RT_NOEXCEPT;
4349	VBOXSTRICTRC iemVmxInvvpid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrInvvpidDesc,
4350	uint64_t u64InvvpidType, PCVMXVEXITINFO pExitInfo) RT_NOEXCEPT;
4351	bool iemVmxIsRdmsrWrmsrInterceptSet(PCVMCPU pVCpu, uint32_t uExitReason, uint32_t idMsr) RT_NOEXCEPT;
4352	IEM_CIMPL_PROTO_0(iemCImpl_vmxoff);
4353	IEM_CIMPL_PROTO_2(iemCImpl_vmxon, uint8_t, iEffSeg, RTGCPTR, GCPtrVmxon);
4354	IEM_CIMPL_PROTO_0(iemCImpl_vmlaunch);
4355	IEM_CIMPL_PROTO_0(iemCImpl_vmresume);
4356	IEM_CIMPL_PROTO_2(iemCImpl_vmptrld, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4357	IEM_CIMPL_PROTO_2(iemCImpl_vmptrst, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4358	IEM_CIMPL_PROTO_2(iemCImpl_vmclear, uint8_t, iEffSeg, RTGCPTR, GCPtrVmcs);
4359	IEM_CIMPL_PROTO_2(iemCImpl_vmwrite_reg, uint64_t, u64Val, uint64_t, u64VmcsField);
4360	IEM_CIMPL_PROTO_3(iemCImpl_vmwrite_mem, uint8_t, iEffSeg, RTGCPTR, GCPtrVal, uint32_t, u64VmcsField);
4361	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg64, uint64_t *, pu64Dst, uint64_t, u64VmcsField);
4362	IEM_CIMPL_PROTO_2(iemCImpl_vmread_reg32, uint64_t *, pu32Dst, uint32_t, u32VmcsField);
4363	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg64, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u64VmcsField);
4364	IEM_CIMPL_PROTO_3(iemCImpl_vmread_mem_reg32, uint8_t, iEffSeg, RTGCPTR, GCPtrDst, uint32_t, u32VmcsField);
4365	IEM_CIMPL_PROTO_3(iemCImpl_invvpid, uint8_t, iEffSeg, RTGCPTR, GCPtrInvvpidDesc, uint64_t, uInvvpidType);
4366	IEM_CIMPL_PROTO_3(iemCImpl_invept, uint8_t, iEffSeg, RTGCPTR, GCPtrInveptDesc, uint64_t, uInveptType);
4367	IEM_CIMPL_PROTO_0(iemCImpl_vmx_pause);
4368	#endif
4369
4370	#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
4371	VBOXSTRICTRC iemSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2) RT_NOEXCEPT;
4372	VBOXSTRICTRC iemHandleSvmEventIntercept(PVMCPUCC pVCpu, uint8_t u8Vector, uint32_t fFlags, uint32_t uErr, uint64_t uCr2) RT_NOEXCEPT;
4373	VBOXSTRICTRC iemSvmHandleIOIntercept(PVMCPUCC pVCpu, uint16_t u16Port, SVMIOIOTYPE enmIoType, uint8_t cbReg,
4374	uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo, uint8_t cbInstr) RT_NOEXCEPT;
4375	VBOXSTRICTRC iemSvmHandleMsrIntercept(PVMCPUCC pVCpu, uint32_t idMsr, bool fWrite) RT_NOEXCEPT;
4376	IEM_CIMPL_PROTO_0(iemCImpl_vmrun);
4377	IEM_CIMPL_PROTO_0(iemCImpl_vmload);
4378	IEM_CIMPL_PROTO_0(iemCImpl_vmsave);
4379	IEM_CIMPL_PROTO_0(iemCImpl_clgi);
4380	IEM_CIMPL_PROTO_0(iemCImpl_stgi);
4381	IEM_CIMPL_PROTO_0(iemCImpl_invlpga);
4382	IEM_CIMPL_PROTO_0(iemCImpl_skinit);
4383	IEM_CIMPL_PROTO_0(iemCImpl_svm_pause);
4384	#endif
4385
4386	IEM_CIMPL_PROTO_0(iemCImpl_vmcall); /* vmx */
4387	IEM_CIMPL_PROTO_0(iemCImpl_vmmcall); /* svm */
4388	IEM_CIMPL_PROTO_1(iemCImpl_Hypercall, uint16_t, uDisOpcode); /* both */
4389
4390
4391	extern const PFNIEMOP g_apfnIemInterpretOnlyOneByteMap[256];
4392
4393	/** @} */
4394
4395	RT_C_DECLS_END
4396
4397	#endif /* !VMM_INCLUDED_SRC_include_IEMInternal_h */
4398

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/include/IEMInternal.h@ 99813

Download in other formats: