VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 100567

Last change on this file since 100567 was 100567, checked in by vboxsync, 17 months ago

VMM/IEM: Implement vbroadcast{ss,sd,f128} instruction emulation, bugref:9898
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1/* $Id: IEMMc.h 100567 2023-07-13 19:19:33Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44
45/** Internal macro. */
46#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
47 do \
48 { \
49 VBOXSTRICTRC rcStrict2 = a_Expr; \
50 if (rcStrict2 != VINF_SUCCESS) \
51 return rcStrict2; \
52 } while (0)
53
54
55/** Advances RIP, finishes the instruction and returns.
56 * This may include raising debug exceptions and such. */
57#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
58/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
59#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
60 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
61/** Sets RIP (may trigger \#GP), finishes the instruction and returns.
62 * @note only usable in 16-bit op size mode. */
63#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
64 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
65/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
66#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
67 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
68/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
69#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJumpU16AndFinishClearningRF((pVCpu), (a_u16NewIP))
70/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
71#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJumpU32AndFinishClearningRF((pVCpu), (a_u32NewIP))
72/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
73#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJumpU64AndFinishClearningRF((pVCpu), (a_u64NewIP))
74
75#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
76#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
77 do { \
78 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)))) \
79 { /* probable */ } \
80 else return iemRaiseDeviceNotAvailable(pVCpu); \
81 } while (0)
82#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
83 do { \
84 if (RT_LIKELY(!((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)))) \
85 { /* probable */ } \
86 else return iemRaiseDeviceNotAvailable(pVCpu); \
87 } while (0)
88#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
89 do { \
90 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES))) \
91 { /* probable */ } \
92 else return iemRaiseMathFault(pVCpu); \
93 } while (0)
94#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
95 do { \
96 /* Since none of the bits we compare from XCR0, CR4 and CR0 overlap, it can \
97 be reduced to a single compare branch in the more probably code path. */ \
98 if (RT_LIKELY( ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) \
99 | (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
100 | (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)) \
101 == (XSAVE_C_YMM | XSAVE_C_SSE | X86_CR4_OSXSAVE))) \
102 { /* probable */ } \
103 else if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
104 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)) \
105 return iemRaiseUndefinedOpcode(pVCpu); \
106 else \
107 return iemRaiseDeviceNotAvailable(pVCpu); \
108 } while (0)
109AssertCompile(!((XSAVE_C_YMM | XSAVE_C_SSE) & X86_CR4_OSXSAVE));
110AssertCompile(!((XSAVE_C_YMM | XSAVE_C_SSE) & X86_CR0_TS));
111AssertCompile(!(X86_CR4_OSXSAVE & X86_CR0_TS));
112#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
113 do { \
114 /* Since the CR4 and CR0 bits doesn't overlap, it can be reduced to a
115 single compare branch in the more probable code path. */ \
116 if (RT_LIKELY( ( (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
117 | (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
118 == X86_CR4_OSFXSR)) \
119 { /* likely */ } \
120 else if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
121 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
122 return iemRaiseUndefinedOpcode(pVCpu); \
123 else \
124 return iemRaiseDeviceNotAvailable(pVCpu); \
125 } while (0)
126AssertCompile(!((X86_CR0_EM | X86_CR0_TS) & X86_CR4_OSFXSR));
127#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
128 do { \
129 /* Since the two CR0 bits doesn't overlap with FSW.ES, this can be reduced to a
130 single compare branch in the more probable code path. */ \
131 if (RT_LIKELY(!( (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
132 | (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES)))) \
133 { /* probable */ } \
134 else if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
135 return iemRaiseUndefinedOpcode(pVCpu); \
136 else if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
137 return iemRaiseDeviceNotAvailable(pVCpu); \
138 else \
139 return iemRaiseMathFault(pVCpu); \
140 } while (0)
141AssertCompile(!((X86_CR0_EM | X86_CR0_TS) & X86_FSW_ES));
142#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
143 do { \
144 if (RT_LIKELY(IEM_GET_CPL(pVCpu) == 0)) { /* probable */ } \
145 else return iemRaiseGeneralProtectionFault0(pVCpu); \
146 } while (0)
147#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
148 do { \
149 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
150 else return iemRaiseGeneralProtectionFault0(pVCpu); \
151 } while (0)
152#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
153 do { \
154 if (RT_LIKELY( ((pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE) | IEM_GET_CPU_MODE(pVCpu)) \
155 == (X86_CR4_FSGSBASE | IEMMODE_64BIT))) \
156 { /* probable */ } \
157 else return iemRaiseUndefinedOpcode(pVCpu); \
158 } while (0)
159AssertCompile(X86_CR4_FSGSBASE > UINT8_MAX);
160#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
161 do { \
162 if (RT_LIKELY(IEM_IS_CANONICAL(a_u64Addr))) { /* likely */ } \
163 else return iemRaiseGeneralProtectionFault0(pVCpu); \
164 } while (0)
165#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
166 do { \
167 if (RT_LIKELY(( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
168 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) == 0)) \
169 { /* probable */ } \
170 else \
171 { \
172 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT) \
173 return iemRaiseSimdFpException(pVCpu); \
174 return iemRaiseUndefinedOpcode(pVCpu); \
175 } \
176 } while (0)
177#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
178 do { \
179 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
180 return iemRaiseSimdFpException(pVCpu); \
181 return iemRaiseUndefinedOpcode(pVCpu); \
182 } while (0)
183
184
185#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
186#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
187#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
188#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
189#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
190#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
191#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
192 uint32_t a_Name; \
193 uint32_t *a_pName = &a_Name
194#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
195 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
196
197#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
198#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
199#define IEM_MC_ASSIGN_U8_SX_U64(a_u64VarOrArg, a_u8CVariableOrConst) \
200 (a_u64VarOrArg) = (int8_t)(a_u8CVariableOrConst)
201#define IEM_MC_ASSIGN_U32_SX_U64(a_u64VarOrArg, a_u32CVariableOrConst) \
202 (a_u64VarOrArg) = (int32_t)(a_u32CVariableOrConst)
203
204#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
205#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
206#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
207#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
208#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
209#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
210#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
211#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
212#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
213#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
214#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
215#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
216#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
217#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
218#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
219#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
220#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
221#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
222 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
223 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
224 } while (0)
225#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
226 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
227 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
228 } while (0)
229#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
230 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
231 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
232 } while (0)
233/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
234#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
235 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
236 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
237 } while (0)
238#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
239 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
240 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
241 } while (0)
242/** @note Not for IOPL or IF testing or modification. */
243#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
244#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
245#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
246#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
247
248#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
249#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
250#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
251#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
252#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
253#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
254#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
255#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
256#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
257#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
258#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
259/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
260#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
261 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
262 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
263 } while (0)
264#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
265 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
266 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
267 } while (0)
268#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
269 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
270
271
272#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
273#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
274/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
275 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
276#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
277#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
278#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
279#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
280#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
281#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
282/** @note Not for IOPL or IF testing or modification.
283 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
284#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
285#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
286
287#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
288#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
289#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
290 do { \
291 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
292 *pu32Reg += (a_u32Value); \
293 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
294 } while (0)
295#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
296
297#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
298#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
299#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
300 do { \
301 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
302 *pu32Reg -= (a_u32Value); \
303 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
304 } while (0)
305#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
306#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
307
308#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
309#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
310#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
311#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
312#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
313#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
314#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
315
316#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
317#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
318#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
319#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
320
321#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
322#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
323#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
324
325#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
326#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
327#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
328
329#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
330#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
331#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
332
333#define IEM_MC_SHR_LOCAL_U8(a_u8Local, a_cShift) do { (a_u8Local) >>= (a_cShift); } while (0)
334
335#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
336#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
337#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
338
339#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
340
341#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
342
343#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
344#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
345#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
346 do { \
347 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
348 *pu32Reg &= (a_u32Value); \
349 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
350 } while (0)
351#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
352
353#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
354#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
355#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
356 do { \
357 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
358 *pu32Reg |= (a_u32Value); \
359 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
360 } while (0)
361#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
362
363#define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) (a_u16Local) = RT_BSWAP_U16((a_u16Local));
364#define IEM_MC_BSWAP_LOCAL_U32(a_u32Local) (a_u32Local) = RT_BSWAP_U32((a_u32Local));
365#define IEM_MC_BSWAP_LOCAL_U64(a_u64Local) (a_u64Local) = RT_BSWAP_U64((a_u64Local));
366
367/** @note Not for IOPL or IF modification. */
368#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
369/** @note Not for IOPL or IF modification. */
370#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
371/** @note Not for IOPL or IF modification. */
372#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
373
374#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
375
376/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
377#define IEM_MC_FPU_TO_MMX_MODE() do { \
378 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
379 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
380 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
381 } while (0)
382
383/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
384#define IEM_MC_FPU_FROM_MMX_MODE() do { \
385 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
386 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
387 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
388 } while (0)
389
390#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
391 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
392#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
393 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
394#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
395 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
396 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
397 } while (0)
398#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
399 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
400 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
401 } while (0)
402#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
403 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
404#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
405 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
406#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
407 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
408#define IEM_MC_MODIFIED_MREG(a_iMReg) \
409 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
410#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
411 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
412
413#define IEM_MC_CLEAR_XREG_U32_MASK(a_iXReg, a_bMask) \
414 do { if ((a_bMask) & (1 << 0)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = 0; \
415 if ((a_bMask) & (1 << 1)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[1] = 0; \
416 if ((a_bMask) & (1 << 2)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[2] = 0; \
417 if ((a_bMask) & (1 << 3)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[3] = 0; \
418 } while (0)
419#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
420 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
421 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
422 } while (0)
423#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
424 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
425 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
426 } while (0)
427#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) \
428 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQWord)]; } while (0)
429#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg, a_iDWord) \
430 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDWord)]; } while (0)
431#define IEM_MC_FETCH_XREG_U16(a_u16Value, a_iXReg, a_iWord) \
432 do { (a_u16Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iWord)]; } while (0)
433#define IEM_MC_FETCH_XREG_U8( a_u8Value, a_iXReg, a_iByte) \
434 do { (a_u8Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iByte)]; } while (0)
435#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
436 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
437 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
438 } while (0)
439#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
440 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
441 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
442 } while (0)
443#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
444 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
445#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
446 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
447#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) \
448 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_u64Value); } while (0)
449#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) \
450 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_u32Value); } while (0)
451#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u16Value) \
452 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iWord)] = (a_u16Value); } while (0)
453#define IEM_MC_STORE_XREG_U8(a_iXReg, a_iByte, a_u8Value) \
454 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iByte)] = (a_u8Value); } while (0)
455
456#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
457 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
458 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
459 } while (0)
460
461#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) \
462 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDwDst)] = (a_u128Value).au32[(a_iDwSrc)]; } while (0)
463#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
464 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
465#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
466 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
467#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
468 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
469 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
470 } while (0)
471#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
472 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
473#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
474 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
475#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
476 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
477#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
478 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
479#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
480 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
481#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
482 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
483#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
484 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
485#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
486 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
487#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
488 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
489 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
490 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
491 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
492 } while (0)
493
494#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
495 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
496 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
497 } while (0)
498#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
499 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
500 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
501 } while (0)
502#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
503 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
504 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
505 } while (0)
506#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
507 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
508 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
509 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
510 } while (0)
511#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
512 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
513 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
514 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
515 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
516 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
517 } while (0)
518#define IEM_MC_STORE_YREG_U64(a_iYRegDst, a_iQword, a_u64Value) \
519 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iYRegDst)].au64[(a_iQword)] = (a_u64Value); } while (0)
520#define IEM_MC_STORE_YREG_U32(a_iYRegDst, a_iDword, a_u32Value) \
521 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iYRegDst)].au32[(a_iDword)] = (a_u32Value); } while (0)
522#define IEM_MC_STORE_YREGHI_U64(a_iYRegDst, a_iQword, a_u64Value) \
523 do { pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(a_iYRegDst)].au64[(a_iQword)] = (a_u64Value); } while (0)
524#define IEM_MC_STORE_YREGHI_U32(a_iYRegDst, a_iDword, a_u32Value) \
525 do { pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(a_iYRegDst)].au32[(a_iDword)] = (a_u32Value); } while (0)
526
527#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
528#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
529 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
530 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
531 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
532 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
533 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
534 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
535 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
536 } while (0)
537#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
538 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
539 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
540 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
541 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
542 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
543 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
544 } while (0)
545#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
546 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
547 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
548 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
549 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
550 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
551 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
552 } while (0)
553#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
554 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
555 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
556 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
557 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
558 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
559 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
560 } while (0)
561
562#define IEM_MC_STORE_YREG_BROADCAST_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
563 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
564 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
565 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
566 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
567 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
568 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
569 } while (0)
570
571#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
572 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
573#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
574 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
575#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
576 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
577#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
578 do { uintptr_t const iYRegTmp = (a_iYReg); \
579 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
580 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
581 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
582 } while (0)
583
584#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
585 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
586 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
587 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
588 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
589 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
590 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
591 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
592 } while (0)
593#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
594 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
595 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
596 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
597 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
598 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
599 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
600 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
601 } while (0)
602#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
603 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
604 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
605 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
606 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
607 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
608 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
609 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
610 } while (0)
611
612#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
613 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
614 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
615 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
616 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
617 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
618 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
619 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
620 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
621 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
622 } while (0)
623#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
624 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
625 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
626 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
627 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
628 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
629 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
630 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
631 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
632 } while (0)
633#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
634 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
635 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
636 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
637 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
638 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
639 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
640 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
641 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
642 } while (0)
643#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
644 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
645 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
646 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
647 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
648 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
649 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
650 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
651 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
652 } while (0)
653#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
654 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
655 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
656 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
657 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
658 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
659 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
660 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
661 } while (0)
662#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
663 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
664 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
665 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
666 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
667 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
668 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
669 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
670 } while (0)
671
672#ifndef IEM_WITH_SETJMP
673# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
674 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
675# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
676 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
677# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
678 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
679#else
680# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
681 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
682# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
683 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
684# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
685 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
686#endif
687
688#ifndef IEM_WITH_SETJMP
689# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
690 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
691# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
692 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
693# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
694 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
695#else
696# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
697 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
698# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
699 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
700# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
701 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
702#endif
703
704#ifndef IEM_WITH_SETJMP
705# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
706 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
707# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
708 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
709# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
710 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
711#else
712# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
713 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
714# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
715 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
716# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
717 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
718#endif
719
720#ifdef SOME_UNUSED_FUNCTION
721# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
722 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
723#endif
724
725#ifndef IEM_WITH_SETJMP
726# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
727 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
728# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
729 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
730# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
731 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
732# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
733 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
734#else
735# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
736 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
737# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
738 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
739# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
740 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
741# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
742 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
743#endif
744
745#ifndef IEM_WITH_SETJMP
746# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
747 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
748# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
749 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
750# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
751 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
752# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
753 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
754#else
755# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
756 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
757# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
758 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
759# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
760 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
761# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
762 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
763#endif
764
765#ifndef IEM_WITH_SETJMP
766# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
767 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
768# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
769 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
770# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
771 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
772
773# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
774 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
775# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
776 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
777# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
778 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
779# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
780 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
781# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
782 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
783#else
784# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
785 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
786# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
787 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
788# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
789 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
790
791# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
792 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
793# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
794 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
795# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
796 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
797# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
798 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
799# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
800 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
801#endif
802
803#ifndef IEM_WITH_SETJMP
804# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
805 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
806# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
807 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
808# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
809 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
810
811# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
812 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
813# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
814 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
815# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
816 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
817#else
818# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
819 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
820# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
821 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
822# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
823 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
824
825# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
826 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
827# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
828 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
829# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
830 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
831#endif
832
833
834
835#ifndef IEM_WITH_SETJMP
836# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
837 do { \
838 uint8_t u8Tmp; \
839 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
840 (a_u16Dst) = u8Tmp; \
841 } while (0)
842# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
843 do { \
844 uint8_t u8Tmp; \
845 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
846 (a_u32Dst) = u8Tmp; \
847 } while (0)
848# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
849 do { \
850 uint8_t u8Tmp; \
851 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
852 (a_u64Dst) = u8Tmp; \
853 } while (0)
854# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
855 do { \
856 uint16_t u16Tmp; \
857 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
858 (a_u32Dst) = u16Tmp; \
859 } while (0)
860# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
861 do { \
862 uint16_t u16Tmp; \
863 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
864 (a_u64Dst) = u16Tmp; \
865 } while (0)
866# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
867 do { \
868 uint32_t u32Tmp; \
869 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
870 (a_u64Dst) = u32Tmp; \
871 } while (0)
872#else /* IEM_WITH_SETJMP */
873# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
874 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
875# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
876 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
877# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
878 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
879# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
880 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
881# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
882 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
883# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
884 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
885#endif /* IEM_WITH_SETJMP */
886
887#ifndef IEM_WITH_SETJMP
888# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
889 do { \
890 uint8_t u8Tmp; \
891 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
892 (a_u16Dst) = (int8_t)u8Tmp; \
893 } while (0)
894# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
895 do { \
896 uint8_t u8Tmp; \
897 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
898 (a_u32Dst) = (int8_t)u8Tmp; \
899 } while (0)
900# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
901 do { \
902 uint8_t u8Tmp; \
903 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
904 (a_u64Dst) = (int8_t)u8Tmp; \
905 } while (0)
906# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
907 do { \
908 uint16_t u16Tmp; \
909 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
910 (a_u32Dst) = (int16_t)u16Tmp; \
911 } while (0)
912# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
913 do { \
914 uint16_t u16Tmp; \
915 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
916 (a_u64Dst) = (int16_t)u16Tmp; \
917 } while (0)
918# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
919 do { \
920 uint32_t u32Tmp; \
921 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
922 (a_u64Dst) = (int32_t)u32Tmp; \
923 } while (0)
924#else /* IEM_WITH_SETJMP */
925# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
926 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
927# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
928 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
929# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
930 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
931# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
932 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
933# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
934 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
935# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
936 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
937#endif /* IEM_WITH_SETJMP */
938
939#ifndef IEM_WITH_SETJMP
940# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
941 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
942# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
943 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
944# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
945 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
946# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
947 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
948#else
949# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
950 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
951# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
952 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
953# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
954 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
955# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
956 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
957#endif
958
959#ifndef IEM_WITH_SETJMP
960# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
961 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
962# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
963 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
964# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
965 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
966# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
967 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
968#else
969# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
970 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
971# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
972 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
973# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
974 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
975# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
976 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
977#endif
978
979#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
980#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
981#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
982#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
983#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
984#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
985#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
986 do { \
987 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
988 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
989 } while (0)
990#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
991 do { \
992 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
993 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
994 } while (0)
995
996#ifndef IEM_WITH_SETJMP
997# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
998 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
999# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1000 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1001#else
1002# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1003 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1004# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1005 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1006#endif
1007
1008#ifndef IEM_WITH_SETJMP
1009# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1010 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1011# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1012 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1013#else
1014# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1015 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1016# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1017 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1018#endif
1019
1020
1021#define IEM_MC_PUSH_U16(a_u16Value) \
1022 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1023#define IEM_MC_PUSH_U32(a_u32Value) \
1024 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1025#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
1026 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
1027#define IEM_MC_PUSH_U64(a_u64Value) \
1028 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1029
1030#define IEM_MC_POP_U16(a_pu16Value) \
1031 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1032#define IEM_MC_POP_U32(a_pu32Value) \
1033 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1034#define IEM_MC_POP_U64(a_pu64Value) \
1035 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1036
1037#define IEM_MC_POP_EX_U16(a_pu16Value, a_) \
1038 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16Ex(pVCpu, (a_pu16Value), (a_pNewRsp)))
1039#define IEM_MC_POP_EX_U32(a_pu32Value) \
1040 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1041#define IEM_MC_POP_EX_U64(a_pu64Value) \
1042 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1043
1044/** Maps guest memory for direct or bounce buffered access.
1045 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1046 * @remarks May return.
1047 */
1048#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1049 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1050 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1051
1052/** Maps guest memory for direct or bounce buffered access.
1053 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1054 * @remarks May return.
1055 */
1056#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1057 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1058 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1059
1060/** Commits the memory and unmaps the guest memory.
1061 * @remarks May return.
1062 */
1063#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1064 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1065
1066/** Commits the memory and unmaps the guest memory unless the FPU status word
1067 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1068 * that would cause FLD not to store.
1069 *
1070 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1071 * store, while \#P will not.
1072 *
1073 * @remarks May in theory return - for now.
1074 */
1075#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1076 do { \
1077 if ( !(a_u16FSW & X86_FSW_ES) \
1078 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1079 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1080 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1081 } while (0)
1082
1083/** Calculate efficient address from R/M. */
1084#ifndef IEM_WITH_SETJMP
1085# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
1086 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (a_bRm), (a_cbImmAndRspOffset), &(a_GCPtrEff)))
1087#else
1088# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
1089 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (a_bRm), (a_cbImmAndRspOffset)))
1090#endif
1091
1092#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1093#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1094#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1095#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1096#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1097#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1098#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1099
1100/** @name IEM_CIMPL_F_XXX - State change clues for CIMPL calls.
1101 *
1102 * These clues are mainly for the recompiler, so that it can
1103 *
1104 * @{ */
1105#define IEM_CIMPL_F_MODE RT_BIT_32(0) /**< Execution flags may change (IEMCPU::fExec). */
1106#define IEM_CIMPL_F_BRANCH RT_BIT_32(1) /**< Branches (changes RIP, maybe CS). */
1107#define IEM_CIMPL_F_RFLAGS RT_BIT_32(2) /**< May change significant portions of RFLAGS. */
1108#define IEM_CIMPL_F_STATUS_FLAGS RT_BIT_32(3) /**< May change the status bits (X86_EFL_STATUS_BITS) in RFLAGS . */
1109#define IEM_CIMPL_F_VMEXIT RT_BIT_32(4) /**< May trigger a VM exit. */
1110#define IEM_CIMPL_F_FPU RT_BIT_32(5) /**< May modify FPU state. */
1111#define IEM_CIMPL_F_REP RT_BIT_32(6) /**< REP prefixed instruction which may yield before updating PC. */
1112#define IEM_CIMPL_F_END_TB RT_BIT_32(7)
1113/** Convenience: Raise exception (technically unnecessary, since it shouldn't return VINF_SUCCESS). */
1114#define IEM_CIMPL_F_XCPT (IEM_CIMPL_F_MODE | IEM_CIMPL_F_BRANCH | IEM_CIMPL_F_RFLAGS | IEM_CIMPL_F_VMEXIT)
1115/** @} */
1116
1117/** @def IEM_MC_CALL_CIMPL_HLP_RET
1118 * Helper macro for check that all important IEM_CIMPL_F_XXX bits are set.
1119 */
1120#ifdef VBOX_STRICT
1121#define IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, a_CallExpr) \
1122 do { \
1123 uint8_t const cbInstr = IEM_GET_INSTR_LEN(pVCpu); /* may be flushed */ \
1124 uint16_t const uCsBefore = pVCpu->cpum.GstCtx.cs.Sel; \
1125 uint64_t const uRipBefore = pVCpu->cpum.GstCtx.rip; \
1126 uint32_t const fEflBefore = pVCpu->cpum.GstCtx.eflags.u; \
1127 uint32_t const fExecBefore = pVCpu->iem.s.fExec; \
1128 VBOXSTRICTRC const rcStrictHlp = a_CallExpr; \
1129 if (rcStrictHlp == VINF_SUCCESS) \
1130 { \
1131 AssertMsg( ((a_fFlags) & IEM_CIMPL_F_BRANCH) \
1132 || ( uRipBefore + cbInstr == pVCpu->cpum.GstCtx.rip \
1133 && uCsBefore == pVCpu->cpum.GstCtx.cs.Sel) \
1134 || ( ((a_fFlags) & IEM_CIMPL_F_REP) \
1135 && uRipBefore == pVCpu->cpum.GstCtx.rip \
1136 && uCsBefore == pVCpu->cpum.GstCtx.cs.Sel), \
1137 ("CS:RIP=%04x:%08RX64 + %x -> %04x:%08RX64, expected %04x:%08RX64\n", uCsBefore, uRipBefore, cbInstr, \
1138 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uCsBefore, uRipBefore + cbInstr)); \
1139 if ((a_fFlags) & IEM_CIMPL_F_RFLAGS) \
1140 { /* No need to check fEflBefore */ Assert(!((a_fFlags) & IEM_CIMPL_F_STATUS_FLAGS)); } \
1141 else if ((a_fFlags) & IEM_CIMPL_F_STATUS_FLAGS) \
1142 AssertMsg( (pVCpu->cpum.GstCtx.eflags.u & ~(X86_EFL_STATUS_BITS | X86_EFL_RF)) \
1143 == (fEflBefore & ~(X86_EFL_STATUS_BITS | X86_EFL_RF)), \
1144 ("EFL=%#RX32 -> %#RX32\n", fEflBefore, pVCpu->cpum.GstCtx.eflags.u)); \
1145 else \
1146 AssertMsg( (pVCpu->cpum.GstCtx.eflags.u & ~(X86_EFL_RF)) \
1147 == (fEflBefore & ~(X86_EFL_RF)), \
1148 ("EFL=%#RX32 -> %#RX32\n", fEflBefore, pVCpu->cpum.GstCtx.eflags.u)); \
1149 if (!((a_fFlags) & IEM_CIMPL_F_MODE)) \
1150 { \
1151 uint32_t fExecRecalc = iemCalcExecFlags(pVCpu) | (pVCpu->iem.s.fExec & IEM_F_USER_OPTS); \
1152 AssertMsg(fExecBefore == fExecRecalc, \
1153 ("fExec=%#x -> %#x (diff %#x)\n", fExecBefore, fExecRecalc, fExecBefore ^ fExecRecalc)); \
1154 } \
1155 } \
1156 return rcStrictHlp; \
1157 } while (0)
1158#else
1159# define IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, a_CallExpr) return a_CallExpr
1160#endif
1161
1162/**
1163 * Defers the rest of the instruction emulation to a C implementation routine
1164 * and returns, only taking the standard parameters.
1165 *
1166 * @param a_fFlags IEM_CIMPL_F_XXX.
1167 * @param a_pfnCImpl The pointer to the C routine.
1168 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1169 */
1170#define IEM_MC_CALL_CIMPL_0(a_fFlags, a_pfnCImpl) \
1171 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu)))
1172
1173/**
1174 * Defers the rest of instruction emulation to a C implementation routine and
1175 * returns, taking one argument in addition to the standard ones.
1176 *
1177 * @param a_fFlags IEM_CIMPL_F_XXX.
1178 * @param a_pfnCImpl The pointer to the C routine.
1179 * @param a0 The argument.
1180 */
1181#define IEM_MC_CALL_CIMPL_1(a_fFlags, a_pfnCImpl, a0) \
1182 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0))
1183
1184/**
1185 * Defers the rest of the instruction emulation to a C implementation routine
1186 * and returns, taking two arguments in addition to the standard ones.
1187 *
1188 * @param a_fFlags IEM_CIMPL_F_XXX.
1189 * @param a_pfnCImpl The pointer to the C routine.
1190 * @param a0 The first extra argument.
1191 * @param a1 The second extra argument.
1192 */
1193#define IEM_MC_CALL_CIMPL_2(a_fFlags, a_pfnCImpl, a0, a1) \
1194 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1))
1195
1196/**
1197 * Defers the rest of the instruction emulation to a C implementation routine
1198 * and returns, taking three arguments in addition to the standard ones.
1199 *
1200 * @param a_fFlags IEM_CIMPL_F_XXX.
1201 * @param a_pfnCImpl The pointer to the C routine.
1202 * @param a0 The first extra argument.
1203 * @param a1 The second extra argument.
1204 * @param a2 The third extra argument.
1205 */
1206#define IEM_MC_CALL_CIMPL_3(a_fFlags, a_pfnCImpl, a0, a1, a2) \
1207 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2))
1208
1209/**
1210 * Defers the rest of the instruction emulation to a C implementation routine
1211 * and returns, taking four arguments in addition to the standard ones.
1212 *
1213 * @param a_fFlags IEM_CIMPL_F_XXX.
1214 * @param a_pfnCImpl The pointer to the C routine.
1215 * @param a0 The first extra argument.
1216 * @param a1 The second extra argument.
1217 * @param a2 The third extra argument.
1218 * @param a3 The fourth extra argument.
1219 */
1220#define IEM_MC_CALL_CIMPL_4(a_fFlags, a_pfnCImpl, a0, a1, a2, a3) \
1221 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3))
1222
1223/**
1224 * Defers the rest of the instruction emulation to a C implementation routine
1225 * and returns, taking two arguments in addition to the standard ones.
1226 *
1227 * @param a_fFlags IEM_CIMPL_F_XXX.
1228 * @param a_pfnCImpl The pointer to the C routine.
1229 * @param a0 The first extra argument.
1230 * @param a1 The second extra argument.
1231 * @param a2 The third extra argument.
1232 * @param a3 The fourth extra argument.
1233 * @param a4 The fifth extra argument.
1234 */
1235#define IEM_MC_CALL_CIMPL_5(a_fFlags, a_pfnCImpl, a0, a1, a2, a3, a4) \
1236 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4))
1237
1238/**
1239 * Defers the entire instruction emulation to a C implementation routine and
1240 * returns, only taking the standard parameters.
1241 *
1242 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1243 *
1244 * @param a_fFlags IEM_CIMPL_F_XXX.
1245 * @param a_pfnCImpl The pointer to the C routine.
1246 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1247 */
1248#define IEM_MC_DEFER_TO_CIMPL_0_RET(a_fFlags, a_pfnCImpl) \
1249 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu)))
1250
1251/**
1252 * Defers the entire instruction emulation to a C implementation routine and
1253 * returns, taking one argument in addition to the standard ones.
1254 *
1255 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1256 *
1257 * @param a_fFlags IEM_CIMPL_F_XXX.
1258 * @param a_pfnCImpl The pointer to the C routine.
1259 * @param a0 The argument.
1260 */
1261#define IEM_MC_DEFER_TO_CIMPL_1_RET(a_fFlags, a_pfnCImpl, a0) \
1262 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0))
1263
1264/**
1265 * Defers the entire instruction emulation to a C implementation routine and
1266 * returns, taking two arguments in addition to the standard ones.
1267 *
1268 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1269 *
1270 * @param a_fFlags IEM_CIMPL_F_XXX.
1271 * @param a_pfnCImpl The pointer to the C routine.
1272 * @param a0 The first extra argument.
1273 * @param a1 The second extra argument.
1274 */
1275#define IEM_MC_DEFER_TO_CIMPL_2_RET(a_fFlags, a_pfnCImpl, a0, a1) \
1276 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1))
1277
1278/**
1279 * Defers the entire instruction emulation to a C implementation routine and
1280 * returns, taking three arguments in addition to the standard ones.
1281 *
1282 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1283 *
1284 * @param a_fFlags IEM_CIMPL_F_XXX.
1285 * @param a_pfnCImpl The pointer to the C routine.
1286 * @param a0 The first extra argument.
1287 * @param a1 The second extra argument.
1288 * @param a2 The third extra argument.
1289 */
1290#define IEM_MC_DEFER_TO_CIMPL_3_RET(a_fFlags, a_pfnCImpl, a0, a1, a2) \
1291 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2))
1292
1293
1294/**
1295 * Calls a FPU assembly implementation taking one visible argument.
1296 *
1297 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1298 * @param a0 The first extra argument.
1299 */
1300#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1301 do { \
1302 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1303 } while (0)
1304
1305/**
1306 * Calls a FPU assembly implementation taking two visible arguments.
1307 *
1308 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1309 * @param a0 The first extra argument.
1310 * @param a1 The second extra argument.
1311 */
1312#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1313 do { \
1314 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1315 } while (0)
1316
1317/**
1318 * Calls a FPU assembly implementation taking three visible arguments.
1319 *
1320 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1321 * @param a0 The first extra argument.
1322 * @param a1 The second extra argument.
1323 * @param a2 The third extra argument.
1324 */
1325#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1326 do { \
1327 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1328 } while (0)
1329
1330#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1331 do { \
1332 (a_FpuData).FSW = (a_FSW); \
1333 (a_FpuData).r80Result = *(a_pr80Value); \
1334 } while (0)
1335
1336/** Pushes FPU result onto the stack. */
1337#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1338 iemFpuPushResult(pVCpu, &a_FpuData)
1339/** Pushes FPU result onto the stack and sets the FPUDP. */
1340#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1341 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1342
1343/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1344#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1345 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1346
1347/** Stores FPU result in a stack register. */
1348#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1349 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1350/** Stores FPU result in a stack register and pops the stack. */
1351#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1352 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1353/** Stores FPU result in a stack register and sets the FPUDP. */
1354#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1355 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1356/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1357 * stack. */
1358#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1359 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1360
1361/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1362#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1363 iemFpuUpdateOpcodeAndIp(pVCpu)
1364/** Free a stack register (for FFREE and FFREEP). */
1365#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1366 iemFpuStackFree(pVCpu, a_iStReg)
1367/** Increment the FPU stack pointer. */
1368#define IEM_MC_FPU_STACK_INC_TOP() \
1369 iemFpuStackIncTop(pVCpu)
1370/** Decrement the FPU stack pointer. */
1371#define IEM_MC_FPU_STACK_DEC_TOP() \
1372 iemFpuStackDecTop(pVCpu)
1373
1374/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1375#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1376 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1377/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1378#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1379 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1380/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1381#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1382 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1383/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1384#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1385 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1386/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1387 * stack. */
1388#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1389 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1390/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1391#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1392 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1393
1394/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1395#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1396 iemFpuStackUnderflow(pVCpu, a_iStDst)
1397/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1398 * stack. */
1399#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1400 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1401/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1402 * FPUDS. */
1403#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1404 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1405/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1406 * FPUDS. Pops stack. */
1407#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1408 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1409/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1410 * stack twice. */
1411#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1412 iemFpuStackUnderflowThenPopPop(pVCpu)
1413/** Raises a FPU stack underflow exception for an instruction pushing a result
1414 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1415#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1416 iemFpuStackPushUnderflow(pVCpu)
1417/** Raises a FPU stack underflow exception for an instruction pushing a result
1418 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1419#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1420 iemFpuStackPushUnderflowTwo(pVCpu)
1421
1422/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1423 * FPUIP, FPUCS and FOP. */
1424#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1425 iemFpuStackPushOverflow(pVCpu)
1426/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1427 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1428#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1429 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1430/** Prepares for using the FPU state.
1431 * Ensures that we can use the host FPU in the current context (RC+R0.
1432 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1433#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1434/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1435#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1436/** Actualizes the guest FPU state so it can be accessed and modified. */
1437#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1438
1439/** Stores SSE SIMD result updating MXCSR. */
1440#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1441 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1442/** Updates MXCSR. */
1443#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1444 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1445
1446/** Prepares for using the SSE state.
1447 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1448 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1449#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1450/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1451#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1452/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1453#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1454
1455/** Prepares for using the AVX state.
1456 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1457 * Ensures the guest AVX state in the CPUMCTX is up to date.
1458 * @note This will include the AVX512 state too when support for it is added
1459 * due to the zero extending feature of VEX instruction. */
1460#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1461/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1462#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1463/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1464#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1465
1466/**
1467 * Calls a MMX assembly implementation taking two visible arguments.
1468 *
1469 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1470 * @param a0 The first extra argument.
1471 * @param a1 The second extra argument.
1472 */
1473#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1474 do { \
1475 IEM_MC_PREPARE_FPU_USAGE(); \
1476 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1477 } while (0)
1478
1479/**
1480 * Calls a MMX assembly implementation taking three visible arguments.
1481 *
1482 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1483 * @param a0 The first extra argument.
1484 * @param a1 The second extra argument.
1485 * @param a2 The third extra argument.
1486 */
1487#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1488 do { \
1489 IEM_MC_PREPARE_FPU_USAGE(); \
1490 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1491 } while (0)
1492
1493
1494/**
1495 * Calls a SSE assembly implementation taking two visible arguments.
1496 *
1497 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1498 * @param a0 The first extra argument.
1499 * @param a1 The second extra argument.
1500 */
1501#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1502 do { \
1503 IEM_MC_PREPARE_SSE_USAGE(); \
1504 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1505 } while (0)
1506
1507/**
1508 * Calls a SSE assembly implementation taking three visible arguments.
1509 *
1510 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1511 * @param a0 The first extra argument.
1512 * @param a1 The second extra argument.
1513 * @param a2 The third extra argument.
1514 */
1515#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1516 do { \
1517 IEM_MC_PREPARE_SSE_USAGE(); \
1518 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1519 } while (0)
1520
1521
1522/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1523 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1524#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1525 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1526
1527/**
1528 * Calls a AVX assembly implementation taking two visible arguments.
1529 *
1530 * There is one implicit zero'th argument, a pointer to the extended state.
1531 *
1532 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1533 * @param a1 The first extra argument.
1534 * @param a2 The second extra argument.
1535 */
1536#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1537 do { \
1538 IEM_MC_PREPARE_AVX_USAGE(); \
1539 a_pfnAImpl(pXState, (a1), (a2)); \
1540 } while (0)
1541
1542/**
1543 * Calls a AVX assembly implementation taking three visible arguments.
1544 *
1545 * There is one implicit zero'th argument, a pointer to the extended state.
1546 *
1547 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1548 * @param a1 The first extra argument.
1549 * @param a2 The second extra argument.
1550 * @param a3 The third extra argument.
1551 */
1552#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1553 do { \
1554 IEM_MC_PREPARE_AVX_USAGE(); \
1555 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1556 } while (0)
1557
1558/** @note Not for IOPL or IF testing. */
1559#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1560/** @note Not for IOPL or IF testing. */
1561#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1562/** @note Not for IOPL or IF testing. */
1563#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1564/** @note Not for IOPL or IF testing. */
1565#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1566/** @note Not for IOPL or IF testing. */
1567#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1568 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1569 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1570/** @note Not for IOPL or IF testing. */
1571#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1572 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1573 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1574/** @note Not for IOPL or IF testing. */
1575#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1576 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1577 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1578 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1579/** @note Not for IOPL or IF testing. */
1580#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1581 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1582 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1583 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1584#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1585#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1586#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1587/** @note Not for IOPL or IF testing. */
1588#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1589 if ( pVCpu->cpum.GstCtx.cx != 0 \
1590 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1591/** @note Not for IOPL or IF testing. */
1592#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1593 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1594 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1595/** @note Not for IOPL or IF testing. */
1596#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1597 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1598 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1599/** @note Not for IOPL or IF testing. */
1600#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1601 if ( pVCpu->cpum.GstCtx.cx != 0 \
1602 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1603/** @note Not for IOPL or IF testing. */
1604#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1605 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1606 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1607/** @note Not for IOPL or IF testing. */
1608#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1609 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1610 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1611#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1612#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1613
1614#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1615 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80; } while (0)
1616#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1617 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1618#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1619 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1620#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1621 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1622#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1623 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1624#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1625 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1626#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1627 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1628#define IEM_MC_IF_FCW_IM() \
1629 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1630#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1631 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1632 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1633
1634#define IEM_MC_ELSE() } else {
1635#define IEM_MC_ENDIF() } do {} while (0)
1636
1637/** @} */
1638
1639#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1640
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