VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 101516

Last change on this file since 101516 was 101484, checked in by vboxsync, 16 months ago

VMM/IEM: Basic register allocator sketches that incorporates simple skipping of guest register value loads. Sketched out varable and argument managmenet. Start telling GDB our jitted code to help with backtraces. ++ bugref:10371
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1/* $Id: IEMMc.h 101484 2023-10-18 01:32:17Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42
43#define IEM_MC_BEGIN(a_cArgs, a_cLocals, a_fMcFlags, a_fCImplFlags) {
44#define IEM_MC_END() }
45
46/** Internal macro. */
47#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
48 do \
49 { \
50 VBOXSTRICTRC rcStrict2 = a_Expr; \
51 if (rcStrict2 == VINF_SUCCESS) \
52 { /* likely */ } \
53 else \
54 return rcStrict2; \
55 } while (0)
56
57
58/** Advances RIP, finishes the instruction and returns.
59 * This may include raising debug exceptions and such. */
60#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
61/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
62#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
63 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
64/** Sets RIP (may trigger \#GP), finishes the instruction and returns.
65 * @note only usable in 16-bit op size mode. */
66#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
67 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
68/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
69#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
70 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
71/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
72#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJumpU16AndFinishClearningRF((pVCpu), (a_u16NewIP))
73/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
74#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJumpU32AndFinishClearningRF((pVCpu), (a_u32NewIP))
75/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
76#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJumpU64AndFinishClearningRF((pVCpu), (a_u64NewIP))
77
78#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
79#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
80 do { \
81 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)))) \
82 { /* probable */ } \
83 else return iemRaiseDeviceNotAvailable(pVCpu); \
84 } while (0)
85#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
86 do { \
87 if (RT_LIKELY(!((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)))) \
88 { /* probable */ } \
89 else return iemRaiseDeviceNotAvailable(pVCpu); \
90 } while (0)
91#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
92 do { \
93 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES))) \
94 { /* probable */ } \
95 else return iemRaiseMathFault(pVCpu); \
96 } while (0)
97#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
98 do { \
99 /* Since none of the bits we compare from XCR0, CR4 and CR0 overlap, it can \
100 be reduced to a single compare branch in the more probably code path. */ \
101 if (RT_LIKELY( ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) \
102 | (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
103 | (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)) \
104 == (XSAVE_C_YMM | XSAVE_C_SSE | X86_CR4_OSXSAVE))) \
105 { /* probable */ } \
106 else if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
107 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)) \
108 return iemRaiseUndefinedOpcode(pVCpu); \
109 else \
110 return iemRaiseDeviceNotAvailable(pVCpu); \
111 } while (0)
112AssertCompile(!((XSAVE_C_YMM | XSAVE_C_SSE) & X86_CR4_OSXSAVE));
113AssertCompile(!((XSAVE_C_YMM | XSAVE_C_SSE) & X86_CR0_TS));
114AssertCompile(!(X86_CR4_OSXSAVE & X86_CR0_TS));
115#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
116 do { \
117 /* Since the CR4 and CR0 bits doesn't overlap, it can be reduced to a
118 single compare branch in the more probable code path. */ \
119 if (RT_LIKELY( ( (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
120 | (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
121 == X86_CR4_OSFXSR)) \
122 { /* likely */ } \
123 else if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
124 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
125 return iemRaiseUndefinedOpcode(pVCpu); \
126 else \
127 return iemRaiseDeviceNotAvailable(pVCpu); \
128 } while (0)
129AssertCompile(!((X86_CR0_EM | X86_CR0_TS) & X86_CR4_OSFXSR));
130#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
131 do { \
132 /* Since the two CR0 bits doesn't overlap with FSW.ES, this can be reduced to a
133 single compare branch in the more probable code path. */ \
134 if (RT_LIKELY(!( (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
135 | (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES)))) \
136 { /* probable */ } \
137 else if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
138 return iemRaiseUndefinedOpcode(pVCpu); \
139 else if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
140 return iemRaiseDeviceNotAvailable(pVCpu); \
141 else \
142 return iemRaiseMathFault(pVCpu); \
143 } while (0)
144AssertCompile(!((X86_CR0_EM | X86_CR0_TS) & X86_FSW_ES));
145/** @todo recomp: this one is slightly problematic as the recompiler doesn't
146 * count the CPL into the TB key. However it is safe enough for now, as
147 * it calls iemRaiseGeneralProtectionFault0 directly so no calls will be
148 * emitted for it. */
149#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
150 do { \
151 if (RT_LIKELY(IEM_GET_CPL(pVCpu) == 0)) { /* probable */ } \
152 else return iemRaiseGeneralProtectionFault0(pVCpu); \
153 } while (0)
154#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
155 do { \
156 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
157 else return iemRaiseGeneralProtectionFault0(pVCpu); \
158 } while (0)
159#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
160 do { \
161 if (RT_LIKELY( ((pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE) | IEM_GET_CPU_MODE(pVCpu)) \
162 == (X86_CR4_FSGSBASE | IEMMODE_64BIT))) \
163 { /* probable */ } \
164 else return iemRaiseUndefinedOpcode(pVCpu); \
165 } while (0)
166AssertCompile(X86_CR4_FSGSBASE > UINT8_MAX);
167#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
168 do { \
169 if (RT_LIKELY(IEM_IS_CANONICAL(a_u64Addr))) { /* likely */ } \
170 else return iemRaiseGeneralProtectionFault0(pVCpu); \
171 } while (0)
172#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
173 do { \
174 if (RT_LIKELY(( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
175 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) == 0)) \
176 { /* probable */ } \
177 else \
178 { \
179 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT) \
180 return iemRaiseSimdFpException(pVCpu); \
181 return iemRaiseUndefinedOpcode(pVCpu); \
182 } \
183 } while (0)
184#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
185 do { \
186 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
187 return iemRaiseSimdFpException(pVCpu); \
188 return iemRaiseUndefinedOpcode(pVCpu); \
189 } while (0)
190
191
192#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
193#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
194#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
195#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
196#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
197#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
198/** @note IEMAllInstPython.py duplicates the expansion. */
199#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
200 uint32_t a_Name; \
201 uint32_t *a_pName = &a_Name
202#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
203 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
204
205#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
206#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
207#define IEM_MC_ASSIGN_U8_SX_U64(a_u64VarOrArg, a_u8CVariableOrConst) \
208 (a_u64VarOrArg) = (int8_t)(a_u8CVariableOrConst)
209#define IEM_MC_ASSIGN_U32_SX_U64(a_u64VarOrArg, a_u32CVariableOrConst) \
210 (a_u64VarOrArg) = (int32_t)(a_u32CVariableOrConst)
211
212#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
213#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
214#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
215#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
216#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
217#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
218#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
219#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
220#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
221#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
222#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
223#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
224#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
225#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
226#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
227#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
228#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
229#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
230 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
231 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
232 } while (0)
233#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
234 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
235 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
236 } while (0)
237#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
238 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
239 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
240 } while (0)
241/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
242#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
243 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
244 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
245 } while (0)
246#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
247 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
248 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
249 } while (0)
250/** @note Not for IOPL or IF testing or modification. */
251#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
252#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
253#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
254#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
255
256#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
257#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
258#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
259#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
260#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
261#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
262#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
263#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
264#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
265#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
266#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
267/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
268#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
269 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
270 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
271 } while (0)
272#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
273 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
274 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
275 } while (0)
276#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
277 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
278
279
280#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
281#define IEM_MC_REF_GREG_U8_CONST(a_pu8Dst, a_iGReg) (a_pu8Dst) = (uint8_t const *)iemGRegRefU8( pVCpu, (a_iGReg))
282#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
283#define IEM_MC_REF_GREG_U16_CONST(a_pu16Dst, a_iGReg) (a_pu16Dst) = (uint16_t const *)iemGRegRefU16(pVCpu, (a_iGReg))
284/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
285 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
286#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
287#define IEM_MC_REF_GREG_U32_CONST(a_pu32Dst, a_iGReg) (a_pu32Dst) = (uint32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
288#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
289#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
290#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
291#define IEM_MC_REF_GREG_U64_CONST(a_pu64Dst, a_iGReg) (a_pu64Dst) = (uint64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
292#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
293#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
294/** @note Not for IOPL or IF testing or modification.
295 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
296#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
297#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
298
299#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
300#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
301#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
302 do { \
303 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
304 *pu32Reg += (a_u32Value); \
305 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
306 } while (0)
307#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
308
309#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
310#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
311#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
312 do { \
313 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
314 *pu32Reg -= (a_u32Value); \
315 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
316 } while (0)
317#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
318#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
319
320#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
321#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
322#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
323#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
324#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
325#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
326#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
327
328#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
329#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
330#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
331#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
332
333#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
334#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
335#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
336
337#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
338#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
339#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
340
341#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
342#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
343#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
344
345#define IEM_MC_SHR_LOCAL_U8(a_u8Local, a_cShift) do { (a_u8Local) >>= (a_cShift); } while (0)
346
347#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
348#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
349#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
350
351#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
352
353#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
354
355#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
356#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
357#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
358 do { \
359 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
360 *pu32Reg &= (a_u32Value); \
361 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
362 } while (0)
363#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
364
365#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
366#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
367#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
368 do { \
369 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
370 *pu32Reg |= (a_u32Value); \
371 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
372 } while (0)
373#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
374
375#define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) (a_u16Local) = RT_BSWAP_U16((a_u16Local));
376#define IEM_MC_BSWAP_LOCAL_U32(a_u32Local) (a_u32Local) = RT_BSWAP_U32((a_u32Local));
377#define IEM_MC_BSWAP_LOCAL_U64(a_u64Local) (a_u64Local) = RT_BSWAP_U64((a_u64Local));
378
379/** @note Not for IOPL or IF modification. */
380#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
381/** @note Not for IOPL or IF modification. */
382#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
383/** @note Not for IOPL or IF modification. */
384#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
385
386#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
387
388/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
389#define IEM_MC_FPU_TO_MMX_MODE() do { \
390 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
391 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
392 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
393 } while (0)
394
395/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
396#define IEM_MC_FPU_FROM_MMX_MODE() do { \
397 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
398 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
399 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
400 } while (0)
401
402#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
403 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
404#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
405 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
406#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
407 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
408 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
409 } while (0)
410#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
411 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
412 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
413 } while (0)
414#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
415 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
416#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
417 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
418#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
419 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
420#define IEM_MC_MODIFIED_MREG(a_iMReg) \
421 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
422#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
423 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
424
425#define IEM_MC_CLEAR_XREG_U32_MASK(a_iXReg, a_bMask) \
426 do { if ((a_bMask) & (1 << 0)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = 0; \
427 if ((a_bMask) & (1 << 1)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[1] = 0; \
428 if ((a_bMask) & (1 << 2)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[2] = 0; \
429 if ((a_bMask) & (1 << 3)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[3] = 0; \
430 } while (0)
431#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
432 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
433 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
434 } while (0)
435#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
436 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
437 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
438 } while (0)
439#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) \
440 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQWord)]; } while (0)
441#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg, a_iDWord) \
442 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDWord)]; } while (0)
443#define IEM_MC_FETCH_XREG_U16(a_u16Value, a_iXReg, a_iWord) \
444 do { (a_u16Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iWord)]; } while (0)
445#define IEM_MC_FETCH_XREG_U8( a_u8Value, a_iXReg, a_iByte) \
446 do { (a_u8Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iByte)]; } while (0)
447#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
448 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
449 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
450 } while (0)
451#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
452 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
453 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
454 } while (0)
455#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
456 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
457#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
458 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
459#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) \
460 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_u64Value); } while (0)
461#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) \
462 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_u32Value); } while (0)
463#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u16Value) \
464 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iWord)] = (a_u16Value); } while (0)
465#define IEM_MC_STORE_XREG_U8(a_iXReg, a_iByte, a_u8Value) \
466 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iByte)] = (a_u8Value); } while (0)
467
468#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
469 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
470 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
471 } while (0)
472
473#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) \
474 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDwDst)] = (a_u128Value).au32[(a_iDwSrc)]; } while (0)
475#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
476 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
477#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
478 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
479#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
480 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
481 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
482 } while (0)
483#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
484 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
485
486#define IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX(a_iXRegDst, a_u8Src) \
487 do { uintptr_t const iXRegDstTmp = (a_iXRegDst); \
488 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[0] = (a_u8Src); \
489 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[1] = (a_u8Src); \
490 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[2] = (a_u8Src); \
491 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[3] = (a_u8Src); \
492 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[4] = (a_u8Src); \
493 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[5] = (a_u8Src); \
494 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[6] = (a_u8Src); \
495 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[7] = (a_u8Src); \
496 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[8] = (a_u8Src); \
497 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[9] = (a_u8Src); \
498 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[10] = (a_u8Src); \
499 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[11] = (a_u8Src); \
500 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[12] = (a_u8Src); \
501 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[13] = (a_u8Src); \
502 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[14] = (a_u8Src); \
503 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[15] = (a_u8Src); \
504 IEM_MC_CLEAR_YREG_128_UP(iXRegDstTmp); \
505 } while (0)
506#define IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX(a_iXRegDst, a_u16Src) \
507 do { uintptr_t const iXRegDstTmp = (a_iXRegDst); \
508 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[0] = (a_u16Src); \
509 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[1] = (a_u16Src); \
510 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[2] = (a_u16Src); \
511 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[3] = (a_u16Src); \
512 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[4] = (a_u16Src); \
513 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[5] = (a_u16Src); \
514 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[6] = (a_u16Src); \
515 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[7] = (a_u16Src); \
516 IEM_MC_CLEAR_YREG_128_UP(iXRegDstTmp); \
517 } while (0)
518#define IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(a_iXRegDst, a_u32Src) \
519 do { uintptr_t const iXRegDstTmp = (a_iXRegDst); \
520 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au32[0] = (a_u32Src); \
521 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au32[1] = (a_u32Src); \
522 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au32[2] = (a_u32Src); \
523 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au32[3] = (a_u32Src); \
524 IEM_MC_CLEAR_YREG_128_UP(iXRegDstTmp); \
525 } while (0)
526#define IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX(a_iXRegDst, a_u64Src) \
527 do { uintptr_t const iXRegDstTmp = (a_iXRegDst); \
528 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au64[0] = (a_u64Src); \
529 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au64[1] = (a_u64Src); \
530 IEM_MC_CLEAR_YREG_128_UP(iXRegDstTmp); \
531 } while (0)
532
533#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
534 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
535#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
536 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
537#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
538 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
539#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
540 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
541#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
542 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
543#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
544 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
545#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
546 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
547#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
548 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
549 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
550 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
551 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
552 } while (0)
553
554#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
555 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
556 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
557 } while (0)
558#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
559 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
560 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
561 } while (0)
562#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
563 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
564 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
565 } while (0)
566#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
567 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
568 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
569 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
570 } while (0)
571#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
572 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
573 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
574 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
575 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
576 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
577 } while (0)
578
579#define IEM_MC_STORE_YREG_U128(a_iYRegDst, a_iDQword, a_u128Value) \
580 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
581 if ((a_iDQword) == 0) \
582 { \
583 pVCpu->cpum.GstCtx.XState.x87.aXMM[(iYRegDstTmp)].au64[0] = (a_u128Value).au64[0]; \
584 pVCpu->cpum.GstCtx.XState.x87.aXMM[(iYRegDstTmp)].au64[1] = (a_u128Value).au64[1]; \
585 } \
586 else \
587 { \
588 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(iYRegDstTmp)].au64[0] = (a_u128Value).au64[0]; \
589 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(iYRegDstTmp)].au64[1] = (a_u128Value).au64[1]; \
590 } \
591 } while (0)
592
593#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
594#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
595 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
596 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
597 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
598 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
599 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
600 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
601 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
602 } while (0)
603#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
604 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
605 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
606 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
607 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
608 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
609 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
610 } while (0)
611#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
612 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
613 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
614 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
615 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
616 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
617 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
618 } while (0)
619#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
620 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
621 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
622 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
623 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
624 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
625 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
626 } while (0)
627
628#define IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX(a_iYRegDst, a_u8Src) \
629 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
630 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[0] = (a_u8Src); \
631 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[1] = (a_u8Src); \
632 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[2] = (a_u8Src); \
633 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[3] = (a_u8Src); \
634 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[4] = (a_u8Src); \
635 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[5] = (a_u8Src); \
636 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[6] = (a_u8Src); \
637 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[7] = (a_u8Src); \
638 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[8] = (a_u8Src); \
639 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[9] = (a_u8Src); \
640 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[10] = (a_u8Src); \
641 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[11] = (a_u8Src); \
642 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[12] = (a_u8Src); \
643 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[13] = (a_u8Src); \
644 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[14] = (a_u8Src); \
645 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[15] = (a_u8Src); \
646 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[0] = (a_u8Src); \
647 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[1] = (a_u8Src); \
648 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[2] = (a_u8Src); \
649 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[3] = (a_u8Src); \
650 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[4] = (a_u8Src); \
651 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[5] = (a_u8Src); \
652 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[6] = (a_u8Src); \
653 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[7] = (a_u8Src); \
654 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[8] = (a_u8Src); \
655 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[9] = (a_u8Src); \
656 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[10] = (a_u8Src); \
657 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[11] = (a_u8Src); \
658 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[12] = (a_u8Src); \
659 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[13] = (a_u8Src); \
660 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[14] = (a_u8Src); \
661 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[15] = (a_u8Src); \
662 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
663 } while (0)
664#define IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX(a_iYRegDst, a_u16Src) \
665 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
666 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[0] = (a_u16Src); \
667 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[1] = (a_u16Src); \
668 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[2] = (a_u16Src); \
669 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[3] = (a_u16Src); \
670 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[4] = (a_u16Src); \
671 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[5] = (a_u16Src); \
672 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[6] = (a_u16Src); \
673 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[7] = (a_u16Src); \
674 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[0] = (a_u16Src); \
675 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[1] = (a_u16Src); \
676 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[2] = (a_u16Src); \
677 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[3] = (a_u16Src); \
678 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[4] = (a_u16Src); \
679 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[5] = (a_u16Src); \
680 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[6] = (a_u16Src); \
681 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[7] = (a_u16Src); \
682 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
683 } while (0)
684#define IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
685 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
686 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
687 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = (a_u32Src); \
688 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[2] = (a_u32Src); \
689 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[3] = (a_u32Src); \
690 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au32[0] = (a_u32Src); \
691 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au32[1] = (a_u32Src); \
692 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au32[2] = (a_u32Src); \
693 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au32[3] = (a_u32Src); \
694 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
695 } while (0)
696#define IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
697 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
698 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
699 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Src); \
700 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u64Src); \
701 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u64Src); \
702 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
703 } while (0)
704#define IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
705 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
706 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
707 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
708 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
709 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
710 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
711 } while (0)
712
713#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
714 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
715#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
716 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
717#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
718 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
719#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
720 do { uintptr_t const iYRegTmp = (a_iYReg); \
721 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
722 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
723 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
724 } while (0)
725
726#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
727 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
728 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
729 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
730 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
731 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
732 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
733 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
734 } while (0)
735#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
736 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
737 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
738 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
739 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
740 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
741 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
742 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
743 } while (0)
744#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
745 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
746 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
747 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
748 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
749 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
750 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
751 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
752 } while (0)
753
754#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
755 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
756 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
757 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
758 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
759 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
760 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
761 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
762 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
763 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
764 } while (0)
765#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
766 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
767 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
768 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
769 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
770 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
771 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
772 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
773 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
774 } while (0)
775#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
776 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
777 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
778 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
779 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
780 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
781 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
782 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
783 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
784 } while (0)
785#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
786 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
787 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
788 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
789 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
790 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
791 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
792 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
793 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
794 } while (0)
795#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
796 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
797 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
798 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
799 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
800 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
801 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
802 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
803 } while (0)
804#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
805 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
806 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
807 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
808 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
809 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
810 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
811 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
812 } while (0)
813
814#ifndef IEM_WITH_SETJMP
815# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
816 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
817# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
818 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
819# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
820 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
821#else
822# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
823 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
824# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
825 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
826# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
827 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
828
829# define IEM_MC_FETCH_MEM_FLAT_U8(a_u8Dst, a_GCPtrMem) \
830 ((a_u8Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
831# define IEM_MC_FETCH_MEM16_FLAT_U8(a_u8Dst, a_GCPtrMem16) \
832 ((a_u8Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem16)))
833# define IEM_MC_FETCH_MEM32_FLAT_U8(a_u8Dst, a_GCPtrMem32) \
834 ((a_u8Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem32)))
835#endif
836
837#ifndef IEM_WITH_SETJMP
838# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
839 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
840# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
841 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
842# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
843 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
844#else
845# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
846 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
847# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
848 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
849# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
850 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
851
852# define IEM_MC_FETCH_MEM_FLAT_U16(a_u16Dst, a_GCPtrMem) \
853 ((a_u16Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
854# define IEM_MC_FETCH_MEM_FLAT_U16_DISP(a_u16Dst, a_GCPtrMem, a_offDisp) \
855 ((a_u16Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem) + (a_offDisp)))
856# define IEM_MC_FETCH_MEM_FLAT_I16(a_i16Dst, a_GCPtrMem) \
857 ((a_i16Dst) = (int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
858#endif
859
860#ifndef IEM_WITH_SETJMP
861# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
862 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
863# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
864 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
865# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
866 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
867#else
868# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
869 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
870# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
871 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
872# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
873 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
874
875# define IEM_MC_FETCH_MEM_FLAT_U32(a_u32Dst, a_GCPtrMem) \
876 ((a_u32Dst) = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
877# define IEM_MC_FETCH_MEM_FLAT_U32_DISP(a_u32Dst, a_GCPtrMem, a_offDisp) \
878 ((a_u32Dst) = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem) + (a_offDisp)))
879# define IEM_MC_FETCH_MEM_FLAT_I32(a_i32Dst, a_GCPtrMem) \
880 ((a_i32Dst) = (int32_t)iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
881#endif
882
883#ifdef SOME_UNUSED_FUNCTION
884# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
885 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
886#endif
887
888#ifndef IEM_WITH_SETJMP
889# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
890 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
891# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
892 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
893# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
894 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
895# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
896 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
897#else
898# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
899 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
900# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
901 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
902# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
903 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
904# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
905 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
906
907# define IEM_MC_FETCH_MEM_FLAT_U64(a_u64Dst, a_GCPtrMem) \
908 ((a_u64Dst) = iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem)))
909# define IEM_MC_FETCH_MEM_FLAT_U64_DISP(a_u64Dst, a_GCPtrMem, a_offDisp) \
910 ((a_u64Dst) = iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem) + (a_offDisp)))
911# define IEM_MC_FETCH_MEM_FLAT_U64_ALIGN_U128(a_u64Dst, a_GCPtrMem) \
912 ((a_u64Dst) = iemMemFlatFetchDataU64AlignedU128Jmp(pVCpu, (a_GCPtrMem)))
913# define IEM_MC_FETCH_MEM_FLAT_I64(a_i64Dst, a_GCPtrMem) \
914 ((a_i64Dst) = (int64_t)iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem)))
915#endif
916
917#ifndef IEM_WITH_SETJMP
918# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
919 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
920# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
921 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
922# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
923 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
924# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
925 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
926#else
927# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
928 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
929# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
930 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
931# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
932 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
933# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
934 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
935
936# define IEM_MC_FETCH_MEM_FLAT_R32(a_r32Dst, a_GCPtrMem) \
937 ((a_r32Dst).u = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
938# define IEM_MC_FETCH_MEM_FLAT_R64(a_r64Dst, a_GCPtrMem) \
939 ((a_r64Dst).u = iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem)))
940# define IEM_MC_FETCH_MEM_FLAT_R80(a_r80Dst, a_GCPtrMem) \
941 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), UINT8_MAX, (a_GCPtrMem))
942# define IEM_MC_FETCH_MEM_FLAT_D80(a_d80Dst, a_GCPtrMem) \
943 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), UINT8_MAX, (a_GCPtrMem))
944#endif
945
946#ifndef IEM_WITH_SETJMP
947# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
948 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
949# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
950 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
951# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
952 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
953
954# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
955 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
956# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
957 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
958# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
959 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
960# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
961 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
962# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
963 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
964#else
965# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
966 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
967# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
968 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
969# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
970 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
971
972# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
973 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
974# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
975 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
976# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
977 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
978# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
979 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
980# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
981 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
982
983# define IEM_MC_FETCH_MEM_FLAT_U128(a_u128Dst, a_GCPtrMem) \
984 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), UINT8_MAX, (a_GCPtrMem))
985# define IEM_MC_FETCH_MEM_FLAT_U128_NO_AC(a_u128Dst, a_GCPtrMem) \
986 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), UINT8_MAX, (a_GCPtrMem))
987# define IEM_MC_FETCH_MEM_FLAT_U128_ALIGN_SSE(a_u128Dst, a_GCPtrMem) \
988 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), UINT8_MAX, (a_GCPtrMem))
989
990# define IEM_MC_FETCH_MEM_FLAT_XMM(a_XmmDst, a_GCPtrMem) \
991 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, UINT8_MAX, (a_GCPtrMem))
992# define IEM_MC_FETCH_MEM_FLAT_XMM_NO_AC(a_XmmDst, a_GCPtrMem) \
993 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, UINT8_MAX, (a_GCPtrMem))
994# define IEM_MC_FETCH_MEM_FLAT_XMM_ALIGN_SSE(a_XmmDst, a_GCPtrMem) \
995 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, UINT8_MAX, (a_GCPtrMem))
996# define IEM_MC_FETCH_MEM_FLAT_XMM_U32(a_XmmDst, a_iDWord, a_GCPtrMem) \
997 (a_XmmDst).au32[(a_iDWord)] = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem))
998# define IEM_MC_FETCH_MEM_FLAT_XMM_U64(a_XmmDst, a_iQWord, a_GCPtrMem) \
999 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, UINT8_MAX, (a_GCPtrMem))
1000#endif
1001
1002#ifndef IEM_WITH_SETJMP
1003# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
1004 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
1005# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
1006 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
1007# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
1008 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
1009
1010# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
1011 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
1012# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
1013 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
1014# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
1015 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
1016#else
1017# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
1018 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
1019# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
1020 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
1021# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
1022 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
1023
1024# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
1025 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
1026# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
1027 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
1028# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
1029 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
1030
1031# define IEM_MC_FETCH_MEM_FLAT_U256(a_u256Dst, a_GCPtrMem) \
1032 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), UINT8_MAX, (a_GCPtrMem))
1033# define IEM_MC_FETCH_MEM_FLAT_U256_NO_AC(a_u256Dst, a_GCPtrMem) \
1034 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), UINT8_MAX, (a_GCPtrMem))
1035# define IEM_MC_FETCH_MEM_FLAT_U256_ALIGN_AVX(a_u256Dst, a_GCPtrMem) \
1036 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), UINT8_MAX, (a_GCPtrMem))
1037
1038# define IEM_MC_FETCH_MEM_FLAT_YMM(a_YmmDst, a_GCPtrMem) \
1039 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, UINT8_MAX, (a_GCPtrMem))
1040# define IEM_MC_FETCH_MEM_FLAT_YMM_NO_AC(a_YmmDst, a_GCPtrMem) \
1041 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, UINT8_MAX, (a_GCPtrMem))
1042# define IEM_MC_FETCH_MEM_FLAT_YMM_ALIGN_AVX(a_YmmDst, a_GCPtrMem) \
1043 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, UINT8_MAX, (a_GCPtrMem))
1044#endif
1045
1046
1047
1048#ifndef IEM_WITH_SETJMP
1049# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
1050 do { \
1051 uint8_t u8Tmp; \
1052 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1053 (a_u16Dst) = u8Tmp; \
1054 } while (0)
1055# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1056 do { \
1057 uint8_t u8Tmp; \
1058 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1059 (a_u32Dst) = u8Tmp; \
1060 } while (0)
1061# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1062 do { \
1063 uint8_t u8Tmp; \
1064 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1065 (a_u64Dst) = u8Tmp; \
1066 } while (0)
1067# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1068 do { \
1069 uint16_t u16Tmp; \
1070 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
1071 (a_u32Dst) = u16Tmp; \
1072 } while (0)
1073# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1074 do { \
1075 uint16_t u16Tmp; \
1076 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
1077 (a_u64Dst) = u16Tmp; \
1078 } while (0)
1079# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1080 do { \
1081 uint32_t u32Tmp; \
1082 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
1083 (a_u64Dst) = u32Tmp; \
1084 } while (0)
1085#else /* IEM_WITH_SETJMP */
1086# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
1087 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1088# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1089 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1090# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1091 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1092# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1093 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1094# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1095 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1096# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1097 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1098
1099# define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U16(a_u16Dst, a_GCPtrMem) \
1100 ((a_u16Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1101# define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U32(a_u32Dst, a_GCPtrMem) \
1102 ((a_u32Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1103# define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U64(a_u64Dst, a_GCPtrMem) \
1104 ((a_u64Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1105# define IEM_MC_FETCH_MEM_FLAT_U16_ZX_U32(a_u32Dst, a_GCPtrMem) \
1106 ((a_u32Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
1107# define IEM_MC_FETCH_MEM_FLAT_U16_ZX_U64(a_u64Dst, a_GCPtrMem) \
1108 ((a_u64Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
1109# define IEM_MC_FETCH_MEM_FLAT_U32_ZX_U64(a_u64Dst, a_GCPtrMem) \
1110 ((a_u64Dst) = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
1111#endif /* IEM_WITH_SETJMP */
1112
1113#ifndef IEM_WITH_SETJMP
1114# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
1115 do { \
1116 uint8_t u8Tmp; \
1117 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1118 (a_u16Dst) = (int8_t)u8Tmp; \
1119 } while (0)
1120# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1121 do { \
1122 uint8_t u8Tmp; \
1123 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1124 (a_u32Dst) = (int8_t)u8Tmp; \
1125 } while (0)
1126# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1127 do { \
1128 uint8_t u8Tmp; \
1129 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1130 (a_u64Dst) = (int8_t)u8Tmp; \
1131 } while (0)
1132# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1133 do { \
1134 uint16_t u16Tmp; \
1135 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
1136 (a_u32Dst) = (int16_t)u16Tmp; \
1137 } while (0)
1138# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1139 do { \
1140 uint16_t u16Tmp; \
1141 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
1142 (a_u64Dst) = (int16_t)u16Tmp; \
1143 } while (0)
1144# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1145 do { \
1146 uint32_t u32Tmp; \
1147 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
1148 (a_u64Dst) = (int32_t)u32Tmp; \
1149 } while (0)
1150#else /* IEM_WITH_SETJMP */
1151# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
1152 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1153# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1154 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1155# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1156 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1157# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1158 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1159# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1160 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1161# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1162 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1163
1164# define IEM_MC_FETCH_MEM_FLAT_U8_SX_U16(a_u16Dst, a_GCPtrMem) \
1165 ((a_u16Dst) = (int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1166# define IEM_MC_FETCH_MEM_FLAT_U8_SX_U32(a_u32Dst, a_GCPtrMem) \
1167 ((a_u32Dst) = (int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1168# define IEM_MC_FETCH_MEM_FLAT_U8_SX_U64(a_u64Dst, a_GCPtrMem) \
1169 ((a_u64Dst) = (int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1170# define IEM_MC_FETCH_MEM_FLAT_U16_SX_U32(a_u32Dst, a_GCPtrMem) \
1171 ((a_u32Dst) = (int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
1172# define IEM_MC_FETCH_MEM_FLAT_U16_SX_U64(a_u64Dst, a_GCPtrMem) \
1173 ((a_u64Dst) = (int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
1174# define IEM_MC_FETCH_MEM_FLAT_U32_SX_U64(a_u64Dst, a_GCPtrMem) \
1175 ((a_u64Dst) = (int32_t)iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
1176#endif /* IEM_WITH_SETJMP */
1177
1178#ifndef IEM_WITH_SETJMP
1179# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
1180 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
1181# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
1182 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
1183# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
1184 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
1185# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
1186 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
1187#else
1188# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
1189 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
1190# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
1191 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
1192# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
1193 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
1194# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
1195 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
1196
1197# define IEM_MC_STORE_MEM_FLAT_U8(a_GCPtrMem, a_u8Value) \
1198 iemMemFlatStoreDataU8Jmp(pVCpu, (a_GCPtrMem), (a_u8Value))
1199# define IEM_MC_STORE_MEM_FLAT_U16(a_GCPtrMem, a_u16Value) \
1200 iemMemFlatStoreDataU16Jmp(pVCpu, (a_GCPtrMem), (a_u16Value))
1201# define IEM_MC_STORE_MEM_FLAT_U32(a_GCPtrMem, a_u32Value) \
1202 iemMemFlatStoreDataU32Jmp(pVCpu, (a_GCPtrMem), (a_u32Value))
1203# define IEM_MC_STORE_MEM_FLAT_U64(a_GCPtrMem, a_u64Value) \
1204 iemMemFlatStoreDataU64Jmp(pVCpu, (a_GCPtrMem), (a_u64Value))
1205#endif
1206
1207#ifndef IEM_WITH_SETJMP
1208# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
1209 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
1210# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
1211 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
1212# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
1213 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
1214# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1215 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
1216#else
1217# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
1218 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
1219# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
1220 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
1221# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
1222 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
1223# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1224 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
1225
1226# define IEM_MC_STORE_MEM_FLAT_U8_CONST(a_GCPtrMem, a_u8C) \
1227 iemMemFlatStoreDataU8Jmp(pVCpu, (a_GCPtrMem), (a_u8C))
1228# define IEM_MC_STORE_MEM_FLAT_U16_CONST(a_GCPtrMem, a_u16C) \
1229 iemMemFlatStoreDataU16Jmp(pVCpu, (a_GCPtrMem), (a_u16C))
1230# define IEM_MC_STORE_MEM_FLAT_U32_CONST(a_GCPtrMem, a_u32C) \
1231 iemMemFlatStoreDataU32Jmp(pVCpu, (a_GCPtrMem), (a_u32C))
1232# define IEM_MC_STORE_MEM_FLAT_U64_CONST(a_GCPtrMem, a_u64C) \
1233 iemMemFlatStoreDataU64Jmp(pVCpu, (a_GCPtrMem), (a_u64C))
1234#endif
1235
1236#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
1237#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
1238#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
1239#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
1240#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
1241#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
1242#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
1243 do { \
1244 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1245 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
1246 } while (0)
1247#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
1248 do { \
1249 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1250 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
1251 } while (0)
1252
1253#ifndef IEM_WITH_SETJMP
1254# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1255 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1256# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1257 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1258#else
1259# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1260 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1261# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1262 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1263
1264# define IEM_MC_STORE_MEM_FLAT_U128(a_GCPtrMem, a_u128Value) \
1265 iemMemStoreDataU128Jmp(pVCpu, UINT8_MAX, (a_GCPtrMem), (a_u128Value))
1266# define IEM_MC_STORE_MEM_FLAT_U128_ALIGN_SSE(a_GCPtrMem, a_u128Value) \
1267 iemMemStoreDataU128AlignedSseJmp(pVCpu, UINT8_MAX, (a_GCPtrMem), (a_u128Value))
1268#endif
1269
1270#ifndef IEM_WITH_SETJMP
1271# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1272 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1273# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1274 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1275#else
1276# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1277 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1278# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1279 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1280
1281# define IEM_MC_STORE_MEM_FLAT_U256(a_GCPtrMem, a_u256Value) \
1282 iemMemStoreDataU256Jmp(pVCpu, UINT8_MAX, (a_GCPtrMem), &(a_u256Value))
1283# define IEM_MC_STORE_MEM_FLAT_U256_ALIGN_AVX(a_GCPtrMem, a_u256Value) \
1284 iemMemStoreDataU256AlignedAvxJmp(pVCpu, UINT8_MAX, (a_GCPtrMem), &(a_u256Value))
1285#endif
1286
1287/* Regular stack push and pop: */
1288#ifndef IEM_WITH_SETJMP
1289# define IEM_MC_PUSH_U16(a_u16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1290# define IEM_MC_PUSH_U32(a_u32Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1291# define IEM_MC_PUSH_U32_SREG(a_uSegVal) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_uSegVal)))
1292# define IEM_MC_PUSH_U64(a_u64Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1293
1294# define IEM_MC_POP_U16(a_pu16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1295# define IEM_MC_POP_U32(a_pu32Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1296# define IEM_MC_POP_U64(a_pu64Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1297#else
1298# define IEM_MC_PUSH_U16(a_u16Value) iemMemStackPushU16Jmp(pVCpu, (a_u16Value))
1299# define IEM_MC_PUSH_U32(a_u32Value) iemMemStackPushU32Jmp(pVCpu, (a_u32Value))
1300# define IEM_MC_PUSH_U32_SREG(a_uSegVal) iemMemStackPushU32SRegJmp(pVCpu, (a_uSegVal))
1301# define IEM_MC_PUSH_U64(a_u64Value) iemMemStackPushU64Jmp(pVCpu, (a_u64Value))
1302
1303# define IEM_MC_POP_U16(a_pu16Value) (*(a_pu16Value) = iemMemStackPopU16Jmp(pVCpu))
1304# define IEM_MC_POP_U32(a_pu32Value) (*(a_pu32Value) = iemMemStackPopU32Jmp(pVCpu))
1305# define IEM_MC_POP_U64(a_pu64Value) (*(a_pu64Value) = iemMemStackPopU64Jmp(pVCpu))
1306#endif
1307
1308/* 32-bit flat stack push and pop: */
1309#ifndef IEM_WITH_SETJMP
1310# define IEM_MC_FLAT32_PUSH_U16(a_u16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1311# define IEM_MC_FLAT32_PUSH_U32(a_u32Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1312# define IEM_MC_FLAT32_PUSH_U32_SREG(a_uSegVal) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_uSegVal)))
1313
1314# define IEM_MC_FLAT32_POP_U16(a_pu16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1315# define IEM_MC_FLAT32_POP_U32(a_pu32Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1316#else
1317# define IEM_MC_FLAT32_PUSH_U16(a_u16Value) iemMemFlat32StackPushU16Jmp(pVCpu, (a_u16Value))
1318# define IEM_MC_FLAT32_PUSH_U32(a_u32Value) iemMemFlat32StackPushU32Jmp(pVCpu, (a_u32Value))
1319# define IEM_MC_FLAT32_PUSH_U32_SREG(a_uSegVal) iemMemFlat32StackPushU32SRegJmp(pVCpu, (a_uSegVal))
1320
1321# define IEM_MC_FLAT32_POP_U16(a_pu16Value) (*(a_pu16Value) = iemMemFlat32StackPopU16Jmp(pVCpu))
1322# define IEM_MC_FLAT32_POP_U32(a_pu32Value) (*(a_pu32Value) = iemMemFlat32StackPopU32Jmp(pVCpu))
1323#endif
1324
1325/* 64-bit flat stack push and pop: */
1326#ifndef IEM_WITH_SETJMP
1327# define IEM_MC_FLAT64_PUSH_U16(a_u16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1328# define IEM_MC_FLAT64_PUSH_U64(a_u64Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1329
1330# define IEM_MC_FLAT64_POP_U16(a_pu16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1331# define IEM_MC_FLAT64_POP_U64(a_pu64Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1332#else
1333# define IEM_MC_FLAT64_PUSH_U16(a_u16Value) iemMemFlat64StackPushU16Jmp(pVCpu, (a_u16Value))
1334# define IEM_MC_FLAT64_PUSH_U64(a_u64Value) iemMemFlat64StackPushU64Jmp(pVCpu, (a_u64Value))
1335
1336# define IEM_MC_FLAT64_POP_U16(a_pu16Value) (*(a_pu16Value) = iemMemFlat64StackPopU16Jmp(pVCpu))
1337# define IEM_MC_FLAT64_POP_U64(a_pu64Value) (*(a_pu64Value) = iemMemFlat64StackPopU64Jmp(pVCpu))
1338#endif
1339
1340
1341/** Maps guest memory for direct or bounce buffered access.
1342 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1343 * @remarks May return.
1344 * @deprecated
1345 */
1346#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1347 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1348 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1349
1350/** Flat variant of IEM_MC_MEM_MAP.
1351 * @deprecated
1352 */
1353#define IEM_MC_MEM_FLAT_MAP(a_pMem, a_fAccess, a_GCPtrMem, a_iArg) \
1354 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), UINT8_MAX, \
1355 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1356
1357/** Maps guest memory for direct or bounce buffered access.
1358 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1359 * @remarks May return.
1360 * @deprecated
1361 */
1362#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1363 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1364 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1365
1366/** Flat variant of IEM_MC_MEM_MAP_EX.
1367 * @deprecated
1368 */
1369#define IEM_MC_MEM_FLAT_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_GCPtrMem, a_cbAlign, a_iArg) \
1370 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), UINT8_MAX, \
1371 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1372
1373/** Commits the memory and unmaps the guest memory.
1374 * @remarks May return.
1375 * @deprecated
1376 */
1377#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1378 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1379
1380
1381/* 8-bit */
1382
1383/**
1384 * Maps guest memory for byte read+write direct (or bounce) buffer acccess.
1385 *
1386 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1387 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1388 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1389 * @param[in] a_GCPtrMem The memory address.
1390 * @remarks Will return/long jump on errors.
1391 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1392 */
1393#ifndef IEM_WITH_SETJMP
1394# define IEM_MC_MEM_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1395 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), sizeof(uint8_t), (a_iSeg), \
1396 (a_GCPtrMem), IEM_ACCESS_DATA_RW, 0)); \
1397 a_bUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4); \
1398 } while (0)
1399#else
1400# define IEM_MC_MEM_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1401 (a_pu8Mem) = iemMemMapDataU8RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1402#endif
1403
1404/**
1405 * Maps guest memory for byte writeonly direct (or bounce) buffer acccess.
1406 *
1407 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1408 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1409 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1410 * @param[in] a_GCPtrMem The memory address.
1411 * @remarks Will return/long jump on errors.
1412 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1413 */
1414#ifndef IEM_WITH_SETJMP
1415# define IEM_MC_MEM_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1416 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), sizeof(uint8_t), (a_iSeg), \
1417 (a_GCPtrMem), IEM_ACCESS_DATA_W, 0)); \
1418 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_WRITE << 4); \
1419 } while (0)
1420#else
1421# define IEM_MC_MEM_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1422 (a_pu8Mem) = iemMemMapDataU8WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1423#endif
1424
1425/**
1426 * Maps guest memory for byte readonly direct (or bounce) buffer acccess.
1427 *
1428 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1429 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1430 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1431 * @param[in] a_GCPtrMem The memory address.
1432 * @remarks Will return/long jump on errors.
1433 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1434 */
1435#ifndef IEM_WITH_SETJMP
1436# define IEM_MC_MEM_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1437 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), sizeof(uint8_t), (a_iSeg), \
1438 (a_GCPtrMem), IEM_ACCESS_DATA_R, 0)); \
1439 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_READ << 4); \
1440 } while (0)
1441#else
1442# define IEM_MC_MEM_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1443 (a_pu8Mem) = iemMemMapDataU8RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1444#endif
1445
1446/**
1447 * Maps guest memory for byte read+write direct (or bounce) buffer acccess, flat
1448 * address variant.
1449 *
1450 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1451 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1452 * @param[in] a_GCPtrMem The memory address.
1453 * @remarks Will return/long jump on errors.
1454 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1455 */
1456#ifndef IEM_WITH_SETJMP
1457# define IEM_MC_MEM_FLAT_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1458 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), sizeof(uint8_t), UINT8_MAX, \
1459 (a_GCPtrMem), IEM_ACCESS_DATA_RW, 0)); \
1460 a_bUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4); \
1461 } while (0)
1462#else
1463# define IEM_MC_MEM_FLAT_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
1464 (a_pu8Mem) = iemMemFlatMapDataU8RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1465#endif
1466
1467/**
1468 * Maps guest memory for byte writeonly direct (or bounce) buffer acccess, flat
1469 * address variant.
1470 *
1471 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1472 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1473 * @param[in] a_GCPtrMem The memory address.
1474 * @remarks Will return/long jump on errors.
1475 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1476 */
1477#ifndef IEM_WITH_SETJMP
1478# define IEM_MC_MEM_FLAT_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1479 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), sizeof(uint8_t), UINT8_MAX, \
1480 (a_GCPtrMem), IEM_ACCESS_DATA_W, 0)); \
1481 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_WRITE << 4); \
1482 } while (0)
1483#else
1484# define IEM_MC_MEM_FLAT_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
1485 (a_pu8Mem) = iemMemFlatMapDataU8WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1486#endif
1487
1488/**
1489 * Maps guest memory for byte readonly direct (or bounce) buffer acccess, flat
1490 * address variant.
1491 *
1492 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1493 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1494 * @param[in] a_GCPtrMem The memory address.
1495 * @remarks Will return/long jump on errors.
1496 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1497 */
1498#ifndef IEM_WITH_SETJMP
1499# define IEM_MC_MEM_FLAT_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1500 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), sizeof(uint8_t), UINT8_MAX, \
1501 (a_GCPtrMem), IEM_ACCESS_DATA_R, 0)); \
1502 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_READ << 4); \
1503 } while (0)
1504#else
1505# define IEM_MC_MEM_FLAT_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
1506 (a_pu8Mem) = iemMemFlatMapDataU8RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1507#endif
1508
1509
1510/* 16-bit */
1511
1512/**
1513 * Maps guest memory for word read+write direct (or bounce) buffer acccess.
1514 *
1515 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1516 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1517 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1518 * @param[in] a_GCPtrMem The memory address.
1519 * @remarks Will return/long jump on errors.
1520 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1521 */
1522#ifndef IEM_WITH_SETJMP
1523# define IEM_MC_MEM_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1524 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), sizeof(uint16_t), (a_iSeg), \
1525 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint16_t) - 1)); \
1526 a_bUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4); \
1527 } while (0)
1528#else
1529# define IEM_MC_MEM_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1530 (a_pu16Mem) = iemMemMapDataU16RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1531#endif
1532
1533/**
1534 * Maps guest memory for word writeonly direct (or bounce) buffer acccess.
1535 *
1536 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1537 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1538 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1539 * @param[in] a_GCPtrMem The memory address.
1540 * @remarks Will return/long jump on errors.
1541 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1542 */
1543#ifndef IEM_WITH_SETJMP
1544# define IEM_MC_MEM_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1545 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), sizeof(uint16_t), (a_iSeg), \
1546 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint16_t) - 1)); \
1547 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_WRITE << 4); \
1548 } while (0)
1549#else
1550# define IEM_MC_MEM_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1551 (a_pu16Mem) = iemMemMapDataU16WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1552#endif
1553
1554/**
1555 * Maps guest memory for word readonly direct (or bounce) buffer acccess.
1556 *
1557 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1558 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1559 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1560 * @param[in] a_GCPtrMem The memory address.
1561 * @remarks Will return/long jump on errors.
1562 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1563 */
1564#ifndef IEM_WITH_SETJMP
1565# define IEM_MC_MEM_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1566 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), sizeof(uint16_t), (a_iSeg), \
1567 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint16_t) - 1)); \
1568 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_READ << 4); \
1569 } while (0)
1570#else
1571# define IEM_MC_MEM_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1572 (a_pu16Mem) = iemMemMapDataU16RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1573#endif
1574
1575/**
1576 * Maps guest memory for word read+write direct (or bounce) buffer acccess, flat
1577 * address variant.
1578 *
1579 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1580 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1581 * @param[in] a_GCPtrMem The memory address.
1582 * @remarks Will return/long jump on errors.
1583 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1584 */
1585#ifndef IEM_WITH_SETJMP
1586# define IEM_MC_MEM_FLAT_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1587 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), sizeof(uint16_t), UINT8_MAX, \
1588 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint16_t) - 1)); \
1589 a_bUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4); \
1590 } while (0)
1591#else
1592# define IEM_MC_MEM_FLAT_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
1593 (a_pu16Mem) = iemMemFlatMapDataU16RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1594#endif
1595
1596/**
1597 * Maps guest memory for word writeonly direct (or bounce) buffer acccess, flat
1598 * address variant.
1599 *
1600 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1601 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1602 * @param[in] a_GCPtrMem The memory address.
1603 * @remarks Will return/long jump on errors.
1604 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1605 */
1606#ifndef IEM_WITH_SETJMP
1607# define IEM_MC_MEM_FLAT_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1608 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), sizeof(uint16_t), UINT8_MAX, \
1609 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint16_t) - 1)); \
1610 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_WRITE << 4); \
1611 } while (0)
1612#else
1613# define IEM_MC_MEM_FLAT_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
1614 (a_pu16Mem) = iemMemFlatMapDataU16WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1615#endif
1616
1617/**
1618 * Maps guest memory for word readonly direct (or bounce) buffer acccess, flat
1619 * address variant.
1620 *
1621 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1622 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1623 * @param[in] a_GCPtrMem The memory address.
1624 * @remarks Will return/long jump on errors.
1625 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1626 */
1627#ifndef IEM_WITH_SETJMP
1628# define IEM_MC_MEM_FLAT_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1629 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), sizeof(uint16_t), UINT8_MAX, \
1630 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint16_t) - 1)); \
1631 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_READ << 4); \
1632 } while (0)
1633#else
1634# define IEM_MC_MEM_FLAT_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
1635 (a_pu16Mem) = iemMemFlatMapDataU16RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1636#endif
1637
1638
1639/* 32-bit */
1640
1641/**
1642 * Maps guest memory for dword read+write direct (or bounce) buffer acccess.
1643 *
1644 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1645 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1646 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1647 * @param[in] a_GCPtrMem The memory address.
1648 * @remarks Will return/long jump on errors.
1649 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1650 */
1651#ifndef IEM_WITH_SETJMP
1652# define IEM_MC_MEM_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1653 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), sizeof(uint32_t), (a_iSeg), \
1654 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint32_t) - 1)); \
1655 a_bUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4); \
1656 } while (0)
1657#else
1658# define IEM_MC_MEM_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1659 (a_pu32Mem) = iemMemMapDataU32RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1660#endif
1661
1662/**
1663 * Maps guest memory for dword writeonly direct (or bounce) buffer acccess.
1664 *
1665 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1666 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1667 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1668 * @param[in] a_GCPtrMem The memory address.
1669 * @remarks Will return/long jump on errors.
1670 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1671 */
1672#ifndef IEM_WITH_SETJMP
1673# define IEM_MC_MEM_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1674 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), sizeof(uint32_t), (a_iSeg), \
1675 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint32_t) - 1)); \
1676 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_WRITE << 4); \
1677 } while (0)
1678#else
1679# define IEM_MC_MEM_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1680 (a_pu32Mem) = iemMemMapDataU32WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1681#endif
1682
1683/**
1684 * Maps guest memory for dword readonly direct (or bounce) buffer acccess.
1685 *
1686 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1687 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1688 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1689 * @param[in] a_GCPtrMem The memory address.
1690 * @remarks Will return/long jump on errors.
1691 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1692 */
1693#ifndef IEM_WITH_SETJMP
1694# define IEM_MC_MEM_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1695 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), sizeof(uint32_t), (a_iSeg), \
1696 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint32_t) - 1)); \
1697 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_READ << 4); \
1698 } while (0)
1699#else
1700# define IEM_MC_MEM_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1701 (a_pu32Mem) = iemMemMapDataU32RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1702#endif
1703
1704/**
1705 * Maps guest memory for dword read+write direct (or bounce) buffer acccess,
1706 * flat address variant.
1707 *
1708 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1709 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1710 * @param[in] a_GCPtrMem The memory address.
1711 * @remarks Will return/long jump on errors.
1712 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1713 */
1714#ifndef IEM_WITH_SETJMP
1715# define IEM_MC_MEM_FLAT_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1716 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), sizeof(uint32_t), UINT8_MAX, \
1717 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint32_t) - 1)); \
1718 a_bUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4); \
1719 } while (0)
1720#else
1721# define IEM_MC_MEM_FLAT_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
1722 (a_pu32Mem) = iemMemFlatMapDataU32RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1723#endif
1724
1725/**
1726 * Maps guest memory for dword writeonly direct (or bounce) buffer acccess, flat
1727 * address variant.
1728 *
1729 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1730 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1731 * @param[in] a_GCPtrMem The memory address.
1732 * @remarks Will return/long jump on errors.
1733 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1734 */
1735#ifndef IEM_WITH_SETJMP
1736# define IEM_MC_MEM_FLAT_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1737 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), sizeof(uint32_t), UINT8_MAX, \
1738 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint32_t) - 1)); \
1739 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_WRITE << 4); \
1740 } while (0)
1741#else
1742# define IEM_MC_MEM_FLAT_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
1743 (a_pu32Mem) = iemMemFlatMapDataU32WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1744#endif
1745
1746/**
1747 * Maps guest memory for dword readonly direct (or bounce) buffer acccess, flat
1748 * address variant.
1749 *
1750 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1751 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1752 * @param[in] a_GCPtrMem The memory address.
1753 * @remarks Will return/long jump on errors.
1754 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1755 */
1756#ifndef IEM_WITH_SETJMP
1757# define IEM_MC_MEM_FLAT_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1758 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), sizeof(uint32_t), UINT8_MAX, \
1759 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint32_t) - 1)); \
1760 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_READ << 4); \
1761 } while (0)
1762#else
1763# define IEM_MC_MEM_FLAT_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
1764 (a_pu32Mem) = iemMemFlatMapDataU32RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1765#endif
1766
1767
1768/* 64-bit */
1769
1770/**
1771 * Maps guest memory for qword read+write direct (or bounce) buffer acccess.
1772 *
1773 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
1774 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1775 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1776 * @param[in] a_GCPtrMem The memory address.
1777 * @remarks Will return/long jump on errors.
1778 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1779 */
1780#ifndef IEM_WITH_SETJMP
1781# define IEM_MC_MEM_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1782 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), sizeof(uint64_t), (a_iSeg), \
1783 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint64_t) - 1)); \
1784 a_bUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4); \
1785 } while (0)
1786#else
1787# define IEM_MC_MEM_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1788 (a_pu64Mem) = iemMemMapDataU64RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1789#endif
1790
1791/**
1792 * Maps guest memory for qword writeonly direct (or bounce) buffer acccess.
1793 *
1794 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
1795 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1796 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1797 * @param[in] a_GCPtrMem The memory address.
1798 * @remarks Will return/long jump on errors.
1799 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1800 */
1801#ifndef IEM_WITH_SETJMP
1802# define IEM_MC_MEM_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1803 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), sizeof(uint64_t), (a_iSeg), \
1804 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1)); \
1805 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_WRITE << 4); \
1806 } while (0)
1807#else
1808# define IEM_MC_MEM_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1809 (a_pu64Mem) = iemMemMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1810#endif
1811
1812/**
1813 * Maps guest memory for qword readonly direct (or bounce) buffer acccess.
1814 *
1815 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
1816 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1817 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1818 * @param[in] a_GCPtrMem The memory address.
1819 * @remarks Will return/long jump on errors.
1820 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1821 */
1822#ifndef IEM_WITH_SETJMP
1823# define IEM_MC_MEM_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) do { \
1824 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), sizeof(uint64_t), (a_iSeg), \
1825 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint64_t) - 1)); \
1826 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_READ << 4); \
1827 } while (0)
1828#else
1829# define IEM_MC_MEM_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1830 (a_pu64Mem) = iemMemMapDataU64RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1831#endif
1832
1833/**
1834 * Maps guest memory for qword read+write direct (or bounce) buffer acccess,
1835 * flat address variant.
1836 *
1837 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
1838 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1839 * @param[in] a_GCPtrMem The memory address.
1840 * @remarks Will return/long jump on errors.
1841 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1842 */
1843#ifndef IEM_WITH_SETJMP
1844# define IEM_MC_MEM_FLAT_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1845 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), sizeof(uint64_t), UINT8_MAX, \
1846 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint64_t) - 1)); \
1847 a_bUnmapInfo = 1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4); \
1848 } while (0)
1849#else
1850# define IEM_MC_MEM_FLAT_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
1851 (a_pu64Mem) = iemMemFlatMapDataU64RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1852#endif
1853
1854/**
1855 * Maps guest memory for qword writeonly direct (or bounce) buffer acccess, flat
1856 * address variant.
1857 *
1858 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
1859 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1860 * @param[in] a_GCPtrMem The memory address.
1861 * @remarks Will return/long jump on errors.
1862 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1863 */
1864#ifndef IEM_WITH_SETJMP
1865# define IEM_MC_MEM_FLAT_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1866 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), sizeof(uint64_t), UINT8_MAX, \
1867 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1)); \
1868 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_WRITE << 4); \
1869 } while (0)
1870#else
1871# define IEM_MC_MEM_FLAT_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
1872 (a_pu64Mem) = iemMemFlatMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1873#endif
1874
1875/**
1876 * Maps guest memory for qword readonly direct (or bounce) buffer acccess, flat
1877 * address variant.
1878 *
1879 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
1880 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1881 * @param[in] a_GCPtrMem The memory address.
1882 * @remarks Will return/long jump on errors.
1883 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1884 */
1885#ifndef IEM_WITH_SETJMP
1886# define IEM_MC_MEM_FLAT_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) do { \
1887 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), sizeof(uint64_t), UINT8_MAX, \
1888 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint64_t) - 1)); \
1889 a_bUnmapInfo = 1 | (IEM_ACCESS_TYPE_READ << 4); \
1890 } while (0)
1891#else
1892# define IEM_MC_MEM_FLAT_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
1893 (a_pu64Mem) = iemMemFlatMapDataU64RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1894#endif
1895
1896
1897/* commit + unmap */
1898
1899/** Commits the memory and unmaps guest memory previously mapped RW.
1900 * @remarks May return.
1901 */
1902#ifndef IEM_WITH_SETJMP
1903# define IEM_MC_MEM_COMMIT_AND_UNMAP_RW(a_pvMem, a_bMapInfo) do { \
1904 RT_NOREF_PV(a_bMapInfo); Assert(a_bMapInfo == (1 | ((IEM_ACCESS_TYPE_READ | IEM_ACCESS_TYPE_WRITE) << 4)) ); \
1905 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), IEM_ACCESS_DATA_RW)); \
1906 } while (0)
1907#else
1908# define IEM_MC_MEM_COMMIT_AND_UNMAP_RW(a_pvMem, a_bMapInfo) \
1909 iemMemCommitAndUnmapRwJmp(pVCpu, (a_pvMem), (a_bMapInfo))
1910#endif
1911
1912/** Commits the memory and unmaps guest memory previously mapped W.
1913 * @remarks May return.
1914 */
1915#ifndef IEM_WITH_SETJMP
1916# define IEM_MC_MEM_COMMIT_AND_UNMAP_WO(a_pvMem, a_bMapInfo) do { \
1917 RT_NOREF_PV(a_bMapInfo); Assert(a_bMapInfo == (1 | (IEM_ACCESS_TYPE_WRITE << 4)) ); \
1918 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), IEM_ACCESS_DATA_W)); \
1919 } while (0)
1920#else
1921# define IEM_MC_MEM_COMMIT_AND_UNMAP_WO(a_pvMem, a_bMapInfo) \
1922 iemMemCommitAndUnmapWoJmp(pVCpu, (a_pvMem), (a_bMapInfo))
1923#endif
1924
1925/** Commits the memory and unmaps guest memory previously mapped R.
1926 * @remarks May return.
1927 */
1928#ifndef IEM_WITH_SETJMP
1929# define IEM_MC_MEM_COMMIT_AND_UNMAP_RO(a_pvMem, a_bMapInfo) do { \
1930 RT_NOREF_PV(a_bMapInfo); Assert(a_bMapInfo == (1 | (IEM_ACCESS_TYPE_READ << 4)) ); \
1931 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (void *)(a_pvMem), IEM_ACCESS_DATA_R)); \
1932 } while (0)
1933#else
1934# define IEM_MC_MEM_COMMIT_AND_UNMAP_RO(a_pvMem, a_bMapInfo) \
1935 iemMemCommitAndUnmapRoJmp(pVCpu, (a_pvMem), (a_bMapInfo))
1936#endif
1937
1938
1939/** Commits the memory and unmaps the guest memory unless the FPU status word
1940 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1941 * that would cause FLD not to store.
1942 *
1943 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1944 * store, while \#P will not.
1945 *
1946 * @remarks May in theory return - for now.
1947 */
1948#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1949 do { \
1950 if ( !(a_u16FSW & X86_FSW_ES) \
1951 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1952 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1953 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1954 } while (0)
1955
1956
1957
1958/** Calculate efficient address from R/M. */
1959#ifndef IEM_WITH_SETJMP
1960# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
1961 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (a_bRm), (a_cbImmAndRspOffset), &(a_GCPtrEff)))
1962#else
1963# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
1964 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (a_bRm), (a_cbImmAndRspOffset)))
1965#endif
1966
1967#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1968#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1969#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1970#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1971#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1972#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1973#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1974
1975
1976/** @def IEM_MC_CALL_CIMPL_HLP_RET
1977 * Helper macro for check that all important IEM_CIMPL_F_XXX bits are set.
1978 */
1979#ifdef VBOX_STRICT
1980#define IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, a_CallExpr) \
1981 do { \
1982 uint8_t const cbInstr = IEM_GET_INSTR_LEN(pVCpu); /* may be flushed */ \
1983 uint16_t const uCsBefore = pVCpu->cpum.GstCtx.cs.Sel; \
1984 uint64_t const uRipBefore = pVCpu->cpum.GstCtx.rip; \
1985 uint32_t const fEflBefore = pVCpu->cpum.GstCtx.eflags.u; \
1986 uint32_t const fExecBefore = pVCpu->iem.s.fExec; \
1987 VBOXSTRICTRC const rcStrictHlp = a_CallExpr; \
1988 if (rcStrictHlp == VINF_SUCCESS) \
1989 { \
1990 AssertMsg( ((a_fFlags) & IEM_CIMPL_F_BRANCH_ANY) \
1991 || ( uRipBefore + cbInstr == pVCpu->cpum.GstCtx.rip \
1992 && uCsBefore == pVCpu->cpum.GstCtx.cs.Sel) \
1993 || ( ((a_fFlags) & IEM_CIMPL_F_REP) \
1994 && uRipBefore == pVCpu->cpum.GstCtx.rip \
1995 && uCsBefore == pVCpu->cpum.GstCtx.cs.Sel), \
1996 ("CS:RIP=%04x:%08RX64 + %x -> %04x:%08RX64, expected %04x:%08RX64\n", uCsBefore, uRipBefore, cbInstr, \
1997 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uCsBefore, uRipBefore + cbInstr)); \
1998 if ((a_fFlags) & IEM_CIMPL_F_RFLAGS) \
1999 { /* No need to check fEflBefore */ Assert(!((a_fFlags) & IEM_CIMPL_F_STATUS_FLAGS)); } \
2000 else if ((a_fFlags) & IEM_CIMPL_F_STATUS_FLAGS) \
2001 AssertMsg( (pVCpu->cpum.GstCtx.eflags.u & ~(X86_EFL_STATUS_BITS | X86_EFL_RF)) \
2002 == (fEflBefore & ~(X86_EFL_STATUS_BITS | X86_EFL_RF)), \
2003 ("EFL=%#RX32 -> %#RX32\n", fEflBefore, pVCpu->cpum.GstCtx.eflags.u)); \
2004 else \
2005 AssertMsg( (pVCpu->cpum.GstCtx.eflags.u & ~(X86_EFL_RF)) \
2006 == (fEflBefore & ~(X86_EFL_RF)), \
2007 ("EFL=%#RX32 -> %#RX32\n", fEflBefore, pVCpu->cpum.GstCtx.eflags.u)); \
2008 if (!((a_fFlags) & IEM_CIMPL_F_MODE)) \
2009 { \
2010 uint32_t fExecRecalc = iemCalcExecFlags(pVCpu) | (pVCpu->iem.s.fExec & IEM_F_USER_OPTS); \
2011 AssertMsg( fExecBefore == fExecRecalc \
2012 /* in case ES, DS or SS was external initially (happens alot with HM): */ \
2013 || ( fExecBefore == (fExecRecalc & ~IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK) \
2014 && (fExecRecalc & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT), \
2015 ("fExec=%#x -> %#x (diff %#x)\n", fExecBefore, fExecRecalc, fExecBefore ^ fExecRecalc)); \
2016 } \
2017 } \
2018 return rcStrictHlp; \
2019 } while (0)
2020#else
2021# define IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, a_CallExpr) return a_CallExpr
2022#endif
2023
2024/**
2025 * Defers the rest of the instruction emulation to a C implementation routine
2026 * and returns, only taking the standard parameters.
2027 *
2028 * @param a_fFlags IEM_CIMPL_F_XXX.
2029 * @param a_pfnCImpl The pointer to the C routine.
2030 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
2031 */
2032#define IEM_MC_CALL_CIMPL_0(a_fFlags, a_pfnCImpl) \
2033 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu)))
2034
2035/**
2036 * Defers the rest of instruction emulation to a C implementation routine and
2037 * returns, taking one argument in addition to the standard ones.
2038 *
2039 * @param a_fFlags IEM_CIMPL_F_XXX.
2040 * @param a_pfnCImpl The pointer to the C routine.
2041 * @param a0 The argument.
2042 */
2043#define IEM_MC_CALL_CIMPL_1(a_fFlags, a_pfnCImpl, a0) \
2044 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0))
2045
2046/**
2047 * Defers the rest of the instruction emulation to a C implementation routine
2048 * and returns, taking two arguments in addition to the standard ones.
2049 *
2050 * @param a_fFlags IEM_CIMPL_F_XXX.
2051 * @param a_pfnCImpl The pointer to the C routine.
2052 * @param a0 The first extra argument.
2053 * @param a1 The second extra argument.
2054 */
2055#define IEM_MC_CALL_CIMPL_2(a_fFlags, a_pfnCImpl, a0, a1) \
2056 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1))
2057
2058/**
2059 * Defers the rest of the instruction emulation to a C implementation routine
2060 * and returns, taking three arguments in addition to the standard ones.
2061 *
2062 * @param a_fFlags IEM_CIMPL_F_XXX.
2063 * @param a_pfnCImpl The pointer to the C routine.
2064 * @param a0 The first extra argument.
2065 * @param a1 The second extra argument.
2066 * @param a2 The third extra argument.
2067 */
2068#define IEM_MC_CALL_CIMPL_3(a_fFlags, a_pfnCImpl, a0, a1, a2) \
2069 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2))
2070
2071/**
2072 * Defers the rest of the instruction emulation to a C implementation routine
2073 * and returns, taking four arguments in addition to the standard ones.
2074 *
2075 * @param a_fFlags IEM_CIMPL_F_XXX.
2076 * @param a_pfnCImpl The pointer to the C routine.
2077 * @param a0 The first extra argument.
2078 * @param a1 The second extra argument.
2079 * @param a2 The third extra argument.
2080 * @param a3 The fourth extra argument.
2081 */
2082#define IEM_MC_CALL_CIMPL_4(a_fFlags, a_pfnCImpl, a0, a1, a2, a3) \
2083 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3))
2084
2085/**
2086 * Defers the rest of the instruction emulation to a C implementation routine
2087 * and returns, taking two arguments in addition to the standard ones.
2088 *
2089 * @param a_fFlags IEM_CIMPL_F_XXX.
2090 * @param a_pfnCImpl The pointer to the C routine.
2091 * @param a0 The first extra argument.
2092 * @param a1 The second extra argument.
2093 * @param a2 The third extra argument.
2094 * @param a3 The fourth extra argument.
2095 * @param a4 The fifth extra argument.
2096 */
2097#define IEM_MC_CALL_CIMPL_5(a_fFlags, a_pfnCImpl, a0, a1, a2, a3, a4) \
2098 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4))
2099
2100/**
2101 * Defers the entire instruction emulation to a C implementation routine and
2102 * returns, only taking the standard parameters.
2103 *
2104 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
2105 *
2106 * @param a_fFlags IEM_CIMPL_F_XXX.
2107 * @param a_pfnCImpl The pointer to the C routine.
2108 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
2109 */
2110#define IEM_MC_DEFER_TO_CIMPL_0_RET(a_fFlags, a_pfnCImpl) \
2111 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu)))
2112
2113/**
2114 * Defers the entire instruction emulation to a C implementation routine and
2115 * returns, taking one argument in addition to the standard ones.
2116 *
2117 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
2118 *
2119 * @param a_fFlags IEM_CIMPL_F_XXX.
2120 * @param a_pfnCImpl The pointer to the C routine.
2121 * @param a0 The argument.
2122 */
2123#define IEM_MC_DEFER_TO_CIMPL_1_RET(a_fFlags, a_pfnCImpl, a0) \
2124 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0))
2125
2126/**
2127 * Defers the entire instruction emulation to a C implementation routine and
2128 * returns, taking two arguments in addition to the standard ones.
2129 *
2130 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
2131 *
2132 * @param a_fFlags IEM_CIMPL_F_XXX.
2133 * @param a_pfnCImpl The pointer to the C routine.
2134 * @param a0 The first extra argument.
2135 * @param a1 The second extra argument.
2136 */
2137#define IEM_MC_DEFER_TO_CIMPL_2_RET(a_fFlags, a_pfnCImpl, a0, a1) \
2138 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1))
2139
2140/**
2141 * Defers the entire instruction emulation to a C implementation routine and
2142 * returns, taking three arguments in addition to the standard ones.
2143 *
2144 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
2145 *
2146 * @param a_fFlags IEM_CIMPL_F_XXX.
2147 * @param a_pfnCImpl The pointer to the C routine.
2148 * @param a0 The first extra argument.
2149 * @param a1 The second extra argument.
2150 * @param a2 The third extra argument.
2151 */
2152#define IEM_MC_DEFER_TO_CIMPL_3_RET(a_fFlags, a_pfnCImpl, a0, a1, a2) \
2153 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2))
2154
2155
2156/**
2157 * Calls a FPU assembly implementation taking one visible argument.
2158 *
2159 * @param a_pfnAImpl Pointer to the assembly FPU routine.
2160 * @param a0 The first extra argument.
2161 */
2162#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
2163 do { \
2164 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
2165 } while (0)
2166
2167/**
2168 * Calls a FPU assembly implementation taking two visible arguments.
2169 *
2170 * @param a_pfnAImpl Pointer to the assembly FPU routine.
2171 * @param a0 The first extra argument.
2172 * @param a1 The second extra argument.
2173 */
2174#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
2175 do { \
2176 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
2177 } while (0)
2178
2179/**
2180 * Calls a FPU assembly implementation taking three visible arguments.
2181 *
2182 * @param a_pfnAImpl Pointer to the assembly FPU routine.
2183 * @param a0 The first extra argument.
2184 * @param a1 The second extra argument.
2185 * @param a2 The third extra argument.
2186 */
2187#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
2188 do { \
2189 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
2190 } while (0)
2191
2192#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
2193 do { \
2194 (a_FpuData).FSW = (a_FSW); \
2195 (a_FpuData).r80Result = *(a_pr80Value); \
2196 } while (0)
2197
2198/** Pushes FPU result onto the stack. */
2199#define IEM_MC_PUSH_FPU_RESULT(a_FpuData, a_uFpuOpcode) \
2200 iemFpuPushResult(pVCpu, &a_FpuData, a_uFpuOpcode)
2201/** Pushes FPU result onto the stack and sets the FPUDP. */
2202#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2203 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2204
2205/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
2206#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo, a_uFpuOpcode) \
2207 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo, a_uFpuOpcode)
2208
2209/** Stores FPU result in a stack register. */
2210#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg, a_uFpuOpcode) \
2211 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg, a_uFpuOpcode)
2212/** Stores FPU result in a stack register and pops the stack. */
2213#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg, a_uFpuOpcode) \
2214 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg, a_uFpuOpcode)
2215/** Stores FPU result in a stack register and sets the FPUDP. */
2216#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2217 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2218/** Stores FPU result in a stack register, sets the FPUDP, and pops the
2219 * stack. */
2220#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2221 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2222
2223/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
2224#define IEM_MC_UPDATE_FPU_OPCODE_IP(a_uFpuOpcode) \
2225 iemFpuUpdateOpcodeAndIp(pVCpu, a_uFpuOpcode)
2226/** Free a stack register (for FFREE and FFREEP). */
2227#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
2228 iemFpuStackFree(pVCpu, a_iStReg)
2229/** Increment the FPU stack pointer. */
2230#define IEM_MC_FPU_STACK_INC_TOP() \
2231 iemFpuStackIncTop(pVCpu)
2232/** Decrement the FPU stack pointer. */
2233#define IEM_MC_FPU_STACK_DEC_TOP() \
2234 iemFpuStackDecTop(pVCpu)
2235
2236/** Updates the FSW, FOP, FPUIP, and FPUCS. */
2237#define IEM_MC_UPDATE_FSW(a_u16FSW, a_uFpuOpcode) \
2238 iemFpuUpdateFSW(pVCpu, a_u16FSW, a_uFpuOpcode)
2239/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
2240#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW, a_uFpuOpcode) \
2241 iemFpuUpdateFSW(pVCpu, a_u16FSW, a_uFpuOpcode)
2242/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
2243#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2244 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2245/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
2246#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW, a_uFpuOpcode) \
2247 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW, a_uFpuOpcode)
2248/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
2249 * stack. */
2250#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2251 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2252/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
2253#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW, a_uFpuOpcode) \
2254 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW, a_uFpuOpcode)
2255
2256/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
2257#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst, a_uFpuOpcode) \
2258 iemFpuStackUnderflow(pVCpu, a_iStDst, a_uFpuOpcode)
2259/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
2260 * stack. */
2261#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst, a_uFpuOpcode) \
2262 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst, a_uFpuOpcode)
2263/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
2264 * FPUDS. */
2265#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2266 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2267/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
2268 * FPUDS. Pops stack. */
2269#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2270 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2271/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
2272 * stack twice. */
2273#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP(a_uFpuOpcode) \
2274 iemFpuStackUnderflowThenPopPop(pVCpu, a_uFpuOpcode)
2275/** Raises a FPU stack underflow exception for an instruction pushing a result
2276 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
2277#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW(a_uFpuOpcode) \
2278 iemFpuStackPushUnderflow(pVCpu, a_uFpuOpcode)
2279/** Raises a FPU stack underflow exception for an instruction pushing a result
2280 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
2281#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO(a_uFpuOpcode) \
2282 iemFpuStackPushUnderflowTwo(pVCpu, a_uFpuOpcode)
2283
2284/** Raises a FPU stack overflow exception as part of a push attempt. Sets
2285 * FPUIP, FPUCS and FOP. */
2286#define IEM_MC_FPU_STACK_PUSH_OVERFLOW(a_uFpuOpcode) \
2287 iemFpuStackPushOverflow(pVCpu, a_uFpuOpcode)
2288/** Raises a FPU stack overflow exception as part of a push attempt. Sets
2289 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
2290#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2291 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2292/** Prepares for using the FPU state.
2293 * Ensures that we can use the host FPU in the current context (RC+R0.
2294 * Ensures the guest FPU state in the CPUMCTX is up to date. */
2295#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
2296/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
2297#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
2298/** Actualizes the guest FPU state so it can be accessed and modified. */
2299#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
2300
2301/** Stores SSE SIMD result updating MXCSR. */
2302#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
2303 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
2304/** Updates MXCSR. */
2305#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
2306 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
2307
2308/** Prepares for using the SSE state.
2309 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
2310 * Ensures the guest SSE state in the CPUMCTX is up to date. */
2311#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
2312/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
2313#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
2314/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
2315#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
2316
2317/** Prepares for using the AVX state.
2318 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
2319 * Ensures the guest AVX state in the CPUMCTX is up to date.
2320 * @note This will include the AVX512 state too when support for it is added
2321 * due to the zero extending feature of VEX instruction. */
2322#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
2323/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
2324#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
2325/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
2326#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
2327
2328/**
2329 * Calls a MMX assembly implementation taking two visible arguments.
2330 *
2331 * @param a_pfnAImpl Pointer to the assembly MMX routine.
2332 * @param a0 The first extra argument.
2333 * @param a1 The second extra argument.
2334 */
2335#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
2336 do { \
2337 IEM_MC_PREPARE_FPU_USAGE(); \
2338 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
2339 } while (0)
2340
2341/**
2342 * Calls a MMX assembly implementation taking three visible arguments.
2343 *
2344 * @param a_pfnAImpl Pointer to the assembly MMX routine.
2345 * @param a0 The first extra argument.
2346 * @param a1 The second extra argument.
2347 * @param a2 The third extra argument.
2348 */
2349#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
2350 do { \
2351 IEM_MC_PREPARE_FPU_USAGE(); \
2352 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
2353 } while (0)
2354
2355
2356/**
2357 * Calls a SSE assembly implementation taking two visible arguments.
2358 *
2359 * @param a_pfnAImpl Pointer to the assembly SSE routine.
2360 * @param a0 The first extra argument.
2361 * @param a1 The second extra argument.
2362 */
2363#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
2364 do { \
2365 IEM_MC_PREPARE_SSE_USAGE(); \
2366 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
2367 } while (0)
2368
2369/**
2370 * Calls a SSE assembly implementation taking three visible arguments.
2371 *
2372 * @param a_pfnAImpl Pointer to the assembly SSE routine.
2373 * @param a0 The first extra argument.
2374 * @param a1 The second extra argument.
2375 * @param a2 The third extra argument.
2376 */
2377#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
2378 do { \
2379 IEM_MC_PREPARE_SSE_USAGE(); \
2380 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
2381 } while (0)
2382
2383
2384/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
2385 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ...
2386 * @note IEMAllInstPython.py duplicates the expansion. */
2387#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
2388 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
2389
2390/**
2391 * Calls a AVX assembly implementation taking two visible arguments.
2392 *
2393 * There is one implicit zero'th argument, a pointer to the extended state.
2394 *
2395 * @param a_pfnAImpl Pointer to the assembly AVX routine.
2396 * @param a1 The first extra argument.
2397 * @param a2 The second extra argument.
2398 */
2399#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
2400 do { \
2401 IEM_MC_PREPARE_AVX_USAGE(); \
2402 a_pfnAImpl(pXState, (a1), (a2)); \
2403 } while (0)
2404
2405/**
2406 * Calls a AVX assembly implementation taking three visible arguments.
2407 *
2408 * There is one implicit zero'th argument, a pointer to the extended state.
2409 *
2410 * @param a_pfnAImpl Pointer to the assembly AVX routine.
2411 * @param a1 The first extra argument.
2412 * @param a2 The second extra argument.
2413 * @param a3 The third extra argument.
2414 */
2415#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
2416 do { \
2417 IEM_MC_PREPARE_AVX_USAGE(); \
2418 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
2419 } while (0)
2420
2421/** @note Not for IOPL or IF testing. */
2422#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
2423/** @note Not for IOPL or IF testing. */
2424#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
2425/** @note Not for IOPL or IF testing. */
2426#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
2427/** @note Not for IOPL or IF testing. */
2428#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
2429/** @note Not for IOPL or IF testing. */
2430#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
2431 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
2432 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
2433/** @note Not for IOPL or IF testing. */
2434#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
2435 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
2436 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
2437/** @note Not for IOPL or IF testing. */
2438#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
2439 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
2440 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
2441 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
2442/** @note Not for IOPL or IF testing. */
2443#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
2444 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
2445 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
2446 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
2447#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
2448#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
2449#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
2450/** @note Not for IOPL or IF testing. */
2451#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
2452 if ( pVCpu->cpum.GstCtx.cx != 0 \
2453 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2454/** @note Not for IOPL or IF testing. */
2455#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
2456 if ( pVCpu->cpum.GstCtx.ecx != 0 \
2457 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2458/** @note Not for IOPL or IF testing. */
2459#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
2460 if ( pVCpu->cpum.GstCtx.rcx != 0 \
2461 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2462/** @note Not for IOPL or IF testing. */
2463#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
2464 if ( pVCpu->cpum.GstCtx.cx != 0 \
2465 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2466/** @note Not for IOPL or IF testing. */
2467#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
2468 if ( pVCpu->cpum.GstCtx.ecx != 0 \
2469 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2470/** @note Not for IOPL or IF testing. */
2471#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
2472 if ( pVCpu->cpum.GstCtx.rcx != 0 \
2473 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2474#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
2475#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
2476
2477#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
2478 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80; } while (0)
2479#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
2480 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
2481#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
2482 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
2483#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
2484 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
2485#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
2486 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
2487#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
2488 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
2489#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
2490 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
2491#define IEM_MC_IF_FCW_IM() \
2492 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
2493#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
2494 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
2495 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
2496
2497#define IEM_MC_ELSE() } else {
2498#define IEM_MC_ENDIF() } do {} while (0)
2499
2500/** @} */
2501
2502#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
2503
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