VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 102569

Last change on this file since 102569 was 102569, checked in by vboxsync, 14 months ago

VMM/IEM: Little unmap assertion fix / optimization. bugref:10371
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1/* $Id: IEMMc.h 102569 2023-12-11 13:37:11Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42
43#define IEM_MC_BEGIN(a_cArgs, a_cLocals, a_fMcFlags, a_fCImplFlags) {
44#define IEM_MC_END() }
45
46/** Internal macro. */
47#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
48 do \
49 { \
50 VBOXSTRICTRC rcStrict2 = a_Expr; \
51 if (rcStrict2 == VINF_SUCCESS) \
52 { /* likely */ } \
53 else \
54 return rcStrict2; \
55 } while (0)
56
57
58/** Dummy MC that prevents native recompilation. */
59#define IEM_MC_NO_NATIVE_RECOMPILE() ((void)0)
60
61/** Advances RIP, finishes the instruction and returns.
62 * This may include raising debug exceptions and such. */
63#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
64/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
65#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
66 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
67/** Sets RIP (may trigger \#GP), finishes the instruction and returns.
68 * @note only usable in 16-bit op size mode. */
69#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
70 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
71/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
72#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
73 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
74/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
75#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJumpU16AndFinishClearningRF((pVCpu), (a_u16NewIP))
76/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
77#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJumpU32AndFinishClearningRF((pVCpu), (a_u32NewIP))
78/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
79#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJumpU64AndFinishClearningRF((pVCpu), (a_u64NewIP))
80
81#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
82#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
83 do { \
84 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)))) \
85 { /* probable */ } \
86 else return iemRaiseDeviceNotAvailable(pVCpu); \
87 } while (0)
88#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
89 do { \
90 if (RT_LIKELY(!((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)))) \
91 { /* probable */ } \
92 else return iemRaiseDeviceNotAvailable(pVCpu); \
93 } while (0)
94#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
95 do { \
96 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES))) \
97 { /* probable */ } \
98 else return iemRaiseMathFault(pVCpu); \
99 } while (0)
100#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
101 do { \
102 /* Since none of the bits we compare from XCR0, CR4 and CR0 overlap, it can \
103 be reduced to a single compare branch in the more probably code path. */ \
104 if (RT_LIKELY( ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) \
105 | (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
106 | (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)) \
107 == (XSAVE_C_YMM | XSAVE_C_SSE | X86_CR4_OSXSAVE))) \
108 { /* probable */ } \
109 else if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
110 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)) \
111 return iemRaiseUndefinedOpcode(pVCpu); \
112 else \
113 return iemRaiseDeviceNotAvailable(pVCpu); \
114 } while (0)
115AssertCompile(!((XSAVE_C_YMM | XSAVE_C_SSE) & X86_CR4_OSXSAVE));
116AssertCompile(!((XSAVE_C_YMM | XSAVE_C_SSE) & X86_CR0_TS));
117AssertCompile(!(X86_CR4_OSXSAVE & X86_CR0_TS));
118#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
119 do { \
120 /* Since the CR4 and CR0 bits doesn't overlap, it can be reduced to a
121 single compare branch in the more probable code path. */ \
122 if (RT_LIKELY( ( (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
123 | (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
124 == X86_CR4_OSFXSR)) \
125 { /* likely */ } \
126 else if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
127 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
128 return iemRaiseUndefinedOpcode(pVCpu); \
129 else \
130 return iemRaiseDeviceNotAvailable(pVCpu); \
131 } while (0)
132AssertCompile(!((X86_CR0_EM | X86_CR0_TS) & X86_CR4_OSFXSR));
133#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
134 do { \
135 /* Since the two CR0 bits doesn't overlap with FSW.ES, this can be reduced to a
136 single compare branch in the more probable code path. */ \
137 if (RT_LIKELY(!( (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
138 | (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES)))) \
139 { /* probable */ } \
140 else if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
141 return iemRaiseUndefinedOpcode(pVCpu); \
142 else if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
143 return iemRaiseDeviceNotAvailable(pVCpu); \
144 else \
145 return iemRaiseMathFault(pVCpu); \
146 } while (0)
147AssertCompile(!((X86_CR0_EM | X86_CR0_TS) & X86_FSW_ES));
148/** @todo recomp: this one is slightly problematic as the recompiler doesn't
149 * count the CPL into the TB key. However it is safe enough for now, as
150 * it calls iemRaiseGeneralProtectionFault0 directly so no calls will be
151 * emitted for it. */
152#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
153 do { \
154 if (RT_LIKELY(IEM_GET_CPL(pVCpu) == 0)) { /* probable */ } \
155 else return iemRaiseGeneralProtectionFault0(pVCpu); \
156 } while (0)
157#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
158 do { \
159 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
160 else return iemRaiseGeneralProtectionFault0(pVCpu); \
161 } while (0)
162#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
163 do { \
164 if (RT_LIKELY( ((pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE) | IEM_GET_CPU_MODE(pVCpu)) \
165 == (X86_CR4_FSGSBASE | IEMMODE_64BIT))) \
166 { /* probable */ } \
167 else return iemRaiseUndefinedOpcode(pVCpu); \
168 } while (0)
169AssertCompile(X86_CR4_FSGSBASE > UINT8_MAX);
170#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
171 do { \
172 if (RT_LIKELY(IEM_IS_CANONICAL(a_u64Addr))) { /* likely */ } \
173 else return iemRaiseGeneralProtectionFault0(pVCpu); \
174 } while (0)
175#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
176 do { \
177 if (RT_LIKELY(( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
178 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) == 0)) \
179 { /* probable */ } \
180 else \
181 { \
182 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT) \
183 return iemRaiseSimdFpException(pVCpu); \
184 return iemRaiseUndefinedOpcode(pVCpu); \
185 } \
186 } while (0)
187#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
188 do { \
189 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
190 return iemRaiseSimdFpException(pVCpu); \
191 return iemRaiseUndefinedOpcode(pVCpu); \
192 } while (0)
193
194
195#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
196#define IEM_MC_LOCAL_ASSIGN(a_Type, a_Name, a_Value) a_Type a_Name = (a_Value)
197#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
198/** @deprecated Use IEM_MC_ARG_LOCAL_REF instead! */
199#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
200#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
201#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
202#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
203/** @note IEMAllInstPython.py duplicates the expansion. */
204#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
205 uint32_t a_Name; \
206 uint32_t *a_pName = &a_Name
207#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
208 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
209
210/** ASSUMES the source variable not used after this statement. */
211#define IEM_MC_ASSIGN_TO_SMALLER(a_VarDst, a_VarSrcEol) (a_VarDst) = (a_VarSrcEol)
212
213#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
214#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
215#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
216#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
217#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
218#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
219#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
220#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
221#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
222#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
223#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
224#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
225#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
226#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
227#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
228#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
229#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
230#define IEM_MC_FETCH_GREG_PAIR_U32(a_u64Dst, a_iGRegLo, a_iGRegHi) do { \
231 (a_u64Dst).s.Lo = iemGRegFetchU32(pVCpu, (a_iGRegLo)); \
232 (a_u64Dst).s.Hi = iemGRegFetchU32(pVCpu, (a_iGRegHi)); \
233 } while(0)
234#define IEM_MC_FETCH_GREG_PAIR_U64(a_u128Dst, a_iGRegLo, a_iGRegHi) do { \
235 (a_u128Dst).s.Lo = iemGRegFetchU64(pVCpu, (a_iGRegLo)); \
236 (a_u128Dst).s.Hi = iemGRegFetchU64(pVCpu, (a_iGRegHi)); \
237 } while(0)
238#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
239 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
240 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
241 } while (0)
242#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
243 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
244 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
245 } while (0)
246#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
247 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
248 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
249 } while (0)
250/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
251#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
252 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
253 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
254 } while (0)
255#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
256 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
257 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
258 } while (0)
259/** @note Not for IOPL or IF testing or modification. */
260#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
261#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
262#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
263#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
264
265#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
266#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
267#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
268#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
269#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
270#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
271#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
272#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
273#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
274#define IEM_MC_STORE_GREG_PAIR_U32(a_iGRegLo, a_iGRegHi, a_u64Value) do { \
275 *iemGRegRefU64(pVCpu, (a_iGRegLo)) = (uint32_t)(a_u64Value).s.Lo; \
276 *iemGRegRefU64(pVCpu, (a_iGRegHi)) = (uint32_t)(a_u64Value).s.Hi; \
277 } while(0)
278#define IEM_MC_STORE_GREG_PAIR_U64(a_iGRegLo, a_iGRegHi, a_u128Value) do { \
279 *iemGRegRefU64(pVCpu, (a_iGRegLo)) = (uint64_t)(a_u128Value).s.Lo; \
280 *iemGRegRefU64(pVCpu, (a_iGRegHi)) = (uint64_t)(a_u128Value).s.Hi; \
281 } while(0)
282#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
283
284/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
285#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
286 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
287 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
288 } while (0)
289#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
290 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
291 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
292 } while (0)
293#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
294 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
295
296
297#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
298#define IEM_MC_REF_GREG_U8_CONST(a_pu8Dst, a_iGReg) (a_pu8Dst) = (uint8_t const *)iemGRegRefU8( pVCpu, (a_iGReg))
299#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
300#define IEM_MC_REF_GREG_U16_CONST(a_pu16Dst, a_iGReg) (a_pu16Dst) = (uint16_t const *)iemGRegRefU16(pVCpu, (a_iGReg))
301/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
302 * Use IEM_MC_CLEAR_HIGH_GREG_U64! */
303#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
304#define IEM_MC_REF_GREG_U32_CONST(a_pu32Dst, a_iGReg) (a_pu32Dst) = (uint32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
305#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
306#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
307#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
308#define IEM_MC_REF_GREG_U64_CONST(a_pu64Dst, a_iGReg) (a_pu64Dst) = (uint64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
309#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
310#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
311/** @note Not for IOPL or IF testing or modification.
312 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
313#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
314#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
315
316#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
317#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
318 do { \
319 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
320 *pu32Reg += (a_u32Value); \
321 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
322 } while (0)
323#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
324
325#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u8Const) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u8Const)
326#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u8Const) \
327 do { \
328 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
329 *pu32Reg -= (a_u8Const); \
330 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
331 } while (0)
332#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u8Const) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u8Const)
333#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
334
335#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
336#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
337#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
338#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
339#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
340#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
341#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
342
343#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
344#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
345#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
346#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
347
348#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
349#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
350#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
351
352#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
353#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
354#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
355
356#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
357#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
358#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
359
360#define IEM_MC_SHR_LOCAL_U8(a_u8Local, a_cShift) do { (a_u8Local) >>= (a_cShift); } while (0)
361
362#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
363#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
364#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
365
366#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
367
368#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
369
370#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
371#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
372#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
373 do { \
374 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
375 *pu32Reg &= (a_u32Value); \
376 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
377 } while (0)
378#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
379
380#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
381#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
382#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
383 do { \
384 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
385 *pu32Reg |= (a_u32Value); \
386 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
387 } while (0)
388#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
389
390#define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) (a_u16Local) = RT_BSWAP_U16((a_u16Local));
391#define IEM_MC_BSWAP_LOCAL_U32(a_u32Local) (a_u32Local) = RT_BSWAP_U32((a_u32Local));
392#define IEM_MC_BSWAP_LOCAL_U64(a_u64Local) (a_u64Local) = RT_BSWAP_U64((a_u64Local));
393
394/** @note Not for IOPL or IF modification. */
395#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
396/** @note Not for IOPL or IF modification. */
397#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
398/** @note Not for IOPL or IF modification. */
399#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
400
401#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
402
403/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
404#define IEM_MC_FPU_TO_MMX_MODE() do { \
405 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
406 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
407 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
408 } while (0)
409
410/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
411#define IEM_MC_FPU_FROM_MMX_MODE() do { \
412 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
413 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
414 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
415 } while (0)
416
417#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
418 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
419#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
420 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
421#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
422 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
423 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
424 } while (0)
425#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
426 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
427 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
428 } while (0)
429#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
430 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
431#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
432 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
433#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
434 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
435#define IEM_MC_MODIFIED_MREG(a_iMReg) \
436 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
437#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
438 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
439
440#define IEM_MC_CLEAR_XREG_U32_MASK(a_iXReg, a_bMask) \
441 do { if ((a_bMask) & (1 << 0)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = 0; \
442 if ((a_bMask) & (1 << 1)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[1] = 0; \
443 if ((a_bMask) & (1 << 2)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[2] = 0; \
444 if ((a_bMask) & (1 << 3)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[3] = 0; \
445 } while (0)
446#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
447 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
448 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
449 } while (0)
450#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
451 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
452 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
453 } while (0)
454#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) \
455 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQWord)]; } while (0)
456#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg, a_iDWord) \
457 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDWord)]; } while (0)
458#define IEM_MC_FETCH_XREG_U16(a_u16Value, a_iXReg, a_iWord) \
459 do { (a_u16Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iWord)]; } while (0)
460#define IEM_MC_FETCH_XREG_U8( a_u8Value, a_iXReg, a_iByte) \
461 do { (a_u8Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iByte)]; } while (0)
462#define IEM_MC_FETCH_XREG_PAIR_U128(a_Dst, a_iXReg1, a_iXReg2) \
463 do { (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
464 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
465 (a_Dst).uSrc2.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg2)].au64[0]; \
466 (a_Dst).uSrc2.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg2)].au64[1]; \
467 } while (0)
468#define IEM_MC_FETCH_XREG_PAIR_XMM(a_Dst, a_iXReg1, a_iXReg2) \
469 do { (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
470 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
471 (a_Dst).uSrc2.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg2)].au64[0]; \
472 (a_Dst).uSrc2.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg2)].au64[1]; \
473 } while (0)
474#define IEM_MC_FETCH_XREG_PAIR_U128_AND_RAX_RDX_U64(a_Dst, a_iXReg1, a_iXReg2) \
475 do { (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
476 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
477 (a_Dst).uSrc2.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg2)].au64[0]; \
478 (a_Dst).uSrc2.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg2)].au64[1]; \
479 (a_Dst).u64Rax = pVCpu->cpum.GstCtx.rax; \
480 (a_Dst).u64Rdx = pVCpu->cpum.GstCtx.rdx; \
481 } while (0)
482#define IEM_MC_FETCH_XREG_PAIR_U128_AND_EAX_EDX_U32_SX_U64(a_Dst, a_iXReg1, a_iXReg2) \
483 do { (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
484 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
485 (a_Dst).uSrc2.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg2)].au64[0]; \
486 (a_Dst).uSrc2.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg2)].au64[1]; \
487 (a_Dst).u64Rax = (int64_t)(int32_t)pVCpu->cpum.GstCtx.eax; \
488 (a_Dst).u64Rdx = (int64_t)(int32_t)pVCpu->cpum.GstCtx.edx; \
489 } while (0)
490#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
491 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
492 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
493 } while (0)
494#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
495 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
496 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
497 } while (0)
498#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
499 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
500#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
501 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
502#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) \
503 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_u64Value); } while (0)
504#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) \
505 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_u32Value); } while (0)
506#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u16Value) \
507 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iWord)] = (a_u16Value); } while (0)
508#define IEM_MC_STORE_XREG_U8(a_iXReg, a_iByte, a_u8Value) \
509 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iByte)] = (a_u8Value); } while (0)
510
511#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
512 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
513 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
514 } while (0)
515
516#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) \
517 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDwDst)] = (a_u128Value).au32[(a_iDwSrc)]; } while (0)
518#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
519 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
520#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
521 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
522#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
523 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
524 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
525 } while (0)
526#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
527 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
528
529#define IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX(a_iXRegDst, a_u8Src) \
530 do { uintptr_t const iXRegDstTmp = (a_iXRegDst); \
531 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[0] = (a_u8Src); \
532 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[1] = (a_u8Src); \
533 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[2] = (a_u8Src); \
534 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[3] = (a_u8Src); \
535 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[4] = (a_u8Src); \
536 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[5] = (a_u8Src); \
537 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[6] = (a_u8Src); \
538 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[7] = (a_u8Src); \
539 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[8] = (a_u8Src); \
540 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[9] = (a_u8Src); \
541 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[10] = (a_u8Src); \
542 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[11] = (a_u8Src); \
543 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[12] = (a_u8Src); \
544 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[13] = (a_u8Src); \
545 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[14] = (a_u8Src); \
546 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au8[15] = (a_u8Src); \
547 IEM_MC_CLEAR_YREG_128_UP(iXRegDstTmp); \
548 } while (0)
549#define IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX(a_iXRegDst, a_u16Src) \
550 do { uintptr_t const iXRegDstTmp = (a_iXRegDst); \
551 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[0] = (a_u16Src); \
552 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[1] = (a_u16Src); \
553 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[2] = (a_u16Src); \
554 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[3] = (a_u16Src); \
555 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[4] = (a_u16Src); \
556 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[5] = (a_u16Src); \
557 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[6] = (a_u16Src); \
558 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au16[7] = (a_u16Src); \
559 IEM_MC_CLEAR_YREG_128_UP(iXRegDstTmp); \
560 } while (0)
561#define IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(a_iXRegDst, a_u32Src) \
562 do { uintptr_t const iXRegDstTmp = (a_iXRegDst); \
563 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au32[0] = (a_u32Src); \
564 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au32[1] = (a_u32Src); \
565 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au32[2] = (a_u32Src); \
566 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au32[3] = (a_u32Src); \
567 IEM_MC_CLEAR_YREG_128_UP(iXRegDstTmp); \
568 } while (0)
569#define IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX(a_iXRegDst, a_u64Src) \
570 do { uintptr_t const iXRegDstTmp = (a_iXRegDst); \
571 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au64[0] = (a_u64Src); \
572 pVCpu->cpum.GstCtx.XState.x87.aXMM[iXRegDstTmp].au64[1] = (a_u64Src); \
573 IEM_MC_CLEAR_YREG_128_UP(iXRegDstTmp); \
574 } while (0)
575
576#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
577 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
578#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
579 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
580#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
581 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
582#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
583 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
584#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
585 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
586#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
587 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
588#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
589 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
590#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
591 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
592 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
593 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
594 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
595 } while (0)
596
597#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
598 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
599 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
600 } while (0)
601#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
602 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
603 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
604 } while (0)
605#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
606 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
607 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
608 } while (0)
609#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
610 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
611 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
612 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
613 } while (0)
614#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
615 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
616 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
617 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
618 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
619 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
620 } while (0)
621
622#define IEM_MC_STORE_YREG_U128(a_iYRegDst, a_iDQword, a_u128Value) \
623 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
624 if ((a_iDQword) == 0) \
625 { \
626 pVCpu->cpum.GstCtx.XState.x87.aXMM[(iYRegDstTmp)].au64[0] = (a_u128Value).au64[0]; \
627 pVCpu->cpum.GstCtx.XState.x87.aXMM[(iYRegDstTmp)].au64[1] = (a_u128Value).au64[1]; \
628 } \
629 else \
630 { \
631 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(iYRegDstTmp)].au64[0] = (a_u128Value).au64[0]; \
632 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[(iYRegDstTmp)].au64[1] = (a_u128Value).au64[1]; \
633 } \
634 } while (0)
635
636#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
637#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
638 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
639 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
640 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
641 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
642 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
643 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
644 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
645 } while (0)
646#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
647 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
648 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
649 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
650 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
651 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
652 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
653 } while (0)
654#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
655 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
656 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
657 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
658 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
659 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
660 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
661 } while (0)
662#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
663 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
664 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
665 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
666 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
667 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
668 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
669 } while (0)
670
671#define IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX(a_iYRegDst, a_u8Src) \
672 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
673 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[0] = (a_u8Src); \
674 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[1] = (a_u8Src); \
675 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[2] = (a_u8Src); \
676 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[3] = (a_u8Src); \
677 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[4] = (a_u8Src); \
678 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[5] = (a_u8Src); \
679 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[6] = (a_u8Src); \
680 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[7] = (a_u8Src); \
681 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[8] = (a_u8Src); \
682 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[9] = (a_u8Src); \
683 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[10] = (a_u8Src); \
684 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[11] = (a_u8Src); \
685 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[12] = (a_u8Src); \
686 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[13] = (a_u8Src); \
687 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[14] = (a_u8Src); \
688 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au8[15] = (a_u8Src); \
689 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[0] = (a_u8Src); \
690 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[1] = (a_u8Src); \
691 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[2] = (a_u8Src); \
692 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[3] = (a_u8Src); \
693 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[4] = (a_u8Src); \
694 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[5] = (a_u8Src); \
695 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[6] = (a_u8Src); \
696 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[7] = (a_u8Src); \
697 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[8] = (a_u8Src); \
698 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[9] = (a_u8Src); \
699 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[10] = (a_u8Src); \
700 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[11] = (a_u8Src); \
701 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[12] = (a_u8Src); \
702 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[13] = (a_u8Src); \
703 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[14] = (a_u8Src); \
704 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au8[15] = (a_u8Src); \
705 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
706 } while (0)
707#define IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX(a_iYRegDst, a_u16Src) \
708 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
709 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[0] = (a_u16Src); \
710 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[1] = (a_u16Src); \
711 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[2] = (a_u16Src); \
712 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[3] = (a_u16Src); \
713 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[4] = (a_u16Src); \
714 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[5] = (a_u16Src); \
715 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[6] = (a_u16Src); \
716 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au16[7] = (a_u16Src); \
717 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[0] = (a_u16Src); \
718 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[1] = (a_u16Src); \
719 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[2] = (a_u16Src); \
720 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[3] = (a_u16Src); \
721 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[4] = (a_u16Src); \
722 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[5] = (a_u16Src); \
723 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[6] = (a_u16Src); \
724 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au16[7] = (a_u16Src); \
725 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
726 } while (0)
727#define IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
728 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
729 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
730 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = (a_u32Src); \
731 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[2] = (a_u32Src); \
732 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[3] = (a_u32Src); \
733 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au32[0] = (a_u32Src); \
734 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au32[1] = (a_u32Src); \
735 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au32[2] = (a_u32Src); \
736 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au32[3] = (a_u32Src); \
737 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
738 } while (0)
739#define IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
740 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
741 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
742 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Src); \
743 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u64Src); \
744 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u64Src); \
745 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
746 } while (0)
747#define IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
748 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
749 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
750 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
751 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
752 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
753 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
754 } while (0)
755
756#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
757 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
758#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
759 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
760#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
761 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
762#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
763 do { uintptr_t const iYRegTmp = (a_iYReg); \
764 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
765 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
766 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
767 } while (0)
768
769#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
770 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
771 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
772 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
773 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
774 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
775 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
776 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
777 } while (0)
778#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
779 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
780 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
781 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
782 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
783 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
784 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
785 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
786 } while (0)
787#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
788 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
789 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
790 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
791 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
792 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
793 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
794 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
795 } while (0)
796
797#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
798 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
799 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
800 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
801 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
802 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
803 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
804 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
805 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
806 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
807 } while (0)
808#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
809 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
810 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
811 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
812 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
813 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
814 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
815 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
816 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
817 } while (0)
818#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
819 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
820 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
821 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
822 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
823 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
824 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
825 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
826 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
827 } while (0)
828#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
829 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
830 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
831 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
832 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
833 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
834 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
835 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
836 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
837 } while (0)
838#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
839 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
840 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
841 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
842 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
843 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
844 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
845 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
846 } while (0)
847#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
848 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
849 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
850 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
851 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
852 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
853 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
854 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
855 } while (0)
856
857#ifndef IEM_WITH_SETJMP
858# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
859 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
860# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
861 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
862# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
863 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
864#else
865# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
866 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
867# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
868 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
869# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
870 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
871
872# define IEM_MC_FETCH_MEM_FLAT_U8(a_u8Dst, a_GCPtrMem) \
873 ((a_u8Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
874# define IEM_MC_FETCH_MEM16_FLAT_U8(a_u8Dst, a_GCPtrMem16) \
875 ((a_u8Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem16)))
876# define IEM_MC_FETCH_MEM32_FLAT_U8(a_u8Dst, a_GCPtrMem32) \
877 ((a_u8Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem32)))
878#endif
879
880#ifndef IEM_WITH_SETJMP
881# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
882 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
883# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
884 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
885# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
886 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
887#else
888# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
889 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
890# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
891 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
892# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
893 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
894
895# define IEM_MC_FETCH_MEM_FLAT_U16(a_u16Dst, a_GCPtrMem) \
896 ((a_u16Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
897# define IEM_MC_FETCH_MEM_FLAT_U16_DISP(a_u16Dst, a_GCPtrMem, a_offDisp) \
898 ((a_u16Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem) + (a_offDisp)))
899# define IEM_MC_FETCH_MEM_FLAT_I16(a_i16Dst, a_GCPtrMem) \
900 ((a_i16Dst) = (int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
901#endif
902
903#ifndef IEM_WITH_SETJMP
904# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
905 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
906# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
907 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
908# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
909 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
910#else
911# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
912 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
913# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
914 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
915# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
916 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
917
918# define IEM_MC_FETCH_MEM_FLAT_U32(a_u32Dst, a_GCPtrMem) \
919 ((a_u32Dst) = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
920# define IEM_MC_FETCH_MEM_FLAT_U32_DISP(a_u32Dst, a_GCPtrMem, a_offDisp) \
921 ((a_u32Dst) = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem) + (a_offDisp)))
922# define IEM_MC_FETCH_MEM_FLAT_I32(a_i32Dst, a_GCPtrMem) \
923 ((a_i32Dst) = (int32_t)iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
924#endif
925
926#ifndef IEM_WITH_SETJMP
927# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
928 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
929# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
930 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
931# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
932 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
933# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
934 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
935#else
936# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
937 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
938# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
939 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
940# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
941 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
942# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
943 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
944
945# define IEM_MC_FETCH_MEM_FLAT_U64(a_u64Dst, a_GCPtrMem) \
946 ((a_u64Dst) = iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem)))
947# define IEM_MC_FETCH_MEM_FLAT_U64_DISP(a_u64Dst, a_GCPtrMem, a_offDisp) \
948 ((a_u64Dst) = iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem) + (a_offDisp)))
949# define IEM_MC_FETCH_MEM_FLAT_U64_ALIGN_U128(a_u64Dst, a_GCPtrMem) \
950 ((a_u64Dst) = iemMemFlatFetchDataU64AlignedU128Jmp(pVCpu, (a_GCPtrMem)))
951# define IEM_MC_FETCH_MEM_FLAT_I64(a_i64Dst, a_GCPtrMem) \
952 ((a_i64Dst) = (int64_t)iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem)))
953#endif
954
955#ifndef IEM_WITH_SETJMP
956# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
957 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
958# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
959 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
960# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
961 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
962# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
963 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
964#else
965# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
966 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
967# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
968 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
969# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
970 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
971# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
972 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
973
974# define IEM_MC_FETCH_MEM_FLAT_R32(a_r32Dst, a_GCPtrMem) \
975 ((a_r32Dst).u = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
976# define IEM_MC_FETCH_MEM_FLAT_R64(a_r64Dst, a_GCPtrMem) \
977 ((a_r64Dst).u = iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem)))
978# define IEM_MC_FETCH_MEM_FLAT_R80(a_r80Dst, a_GCPtrMem) \
979 iemMemFlatFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_GCPtrMem))
980# define IEM_MC_FETCH_MEM_FLAT_D80(a_d80Dst, a_GCPtrMem) \
981 iemMemFlatFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_GCPtrMem))
982#endif
983
984#ifndef IEM_WITH_SETJMP
985# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
986 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
987# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
988 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
989# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
990 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
991
992# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
993 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
994# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
995 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
996# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
997 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
998# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
999 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
1000# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
1001 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
1002
1003# define IEM_MC_FETCH_MEM_U128_AND_XREG_U128(a_u128Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
1004 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_Dst).uSrc2, (a_iSeg2), (a_GCPtrMem2))); \
1005 (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1006 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1007 } while (0)
1008
1009# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE_AND_XREG_XMM(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
1010 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_Dst).uSrc2.uXmm, (a_iSeg2), (a_GCPtrMem2))); \
1011 (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1012 (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1013 } while (0)
1014
1015# define IEM_MC_FETCH_MEM_XMM_U32_AND_XREG_XMM(a_Dst, a_iXReg1, a_iDWord2, a_iSeg2, a_GCPtrMem2) do { \
1016 (a_Dst).uSrc2.uXmm.au64[0] = 0; \
1017 (a_Dst).uSrc2.uXmm.au64[1] = 0; \
1018 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_Dst).uSrc2.uXmm.au32[(a_iDWord2)], (a_iSeg2), (a_GCPtrMem2))); \
1019 (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1020 (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1021 } while (0)
1022
1023# define IEM_MC_FETCH_MEM_XMM_U64_AND_XREG_XMM(a_Dst, a_iXReg1, a_iQWord2, a_iSeg2, a_GCPtrMem2) do { \
1024 (a_Dst).uSrc2.uXmm.au64[1] = 0; \
1025 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_Dst).uSrc2.uXmm.au64[(a_iQWord2)], (a_iSeg2), (a_GCPtrMem2))); \
1026 (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1027 (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1028 } while (0)
1029
1030# define IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_RAX_RDX_U64(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
1031 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_Dst).uSrc2, (a_iSeg2), (a_GCPtrMem2))); \
1032 (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1033 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1034 (a_Dst).u64Rax = pVCpu->cpum.GstCtx.rax; \
1035 (a_Dst).u64Rdx = pVCpu->cpum.GstCtx.rdx; \
1036 } while (0)
1037# define IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_EAX_EDX_U32_SX_U64(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
1038 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_Dst).uSrc2, (a_iSeg2), (a_GCPtrMem2))); \
1039 (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1040 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1041 (a_Dst).u64Rax = (int64_t)(int32_t)pVCpu->cpum.GstCtx.eax; \
1042 (a_Dst).u64Rdx = (int64_t)(int32_t)pVCpu->cpum.GstCtx.edx; \
1043 } while (0)
1044
1045#else
1046# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
1047 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
1048# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
1049 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
1050# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
1051 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
1052
1053# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
1054 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
1055# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
1056 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
1057# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
1058 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
1059# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
1060 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
1061# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
1062 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
1063
1064# define IEM_MC_FETCH_MEM_FLAT_U128(a_u128Dst, a_GCPtrMem) \
1065 iemMemFlatFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_GCPtrMem))
1066# define IEM_MC_FETCH_MEM_FLAT_U128_NO_AC(a_u128Dst, a_GCPtrMem) \
1067 iemMemFlatFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_GCPtrMem))
1068# define IEM_MC_FETCH_MEM_FLAT_U128_ALIGN_SSE(a_u128Dst, a_GCPtrMem) \
1069 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), UINT8_MAX, (a_GCPtrMem))
1070
1071# define IEM_MC_FETCH_MEM_FLAT_XMM(a_XmmDst, a_GCPtrMem) \
1072 iemMemFlatFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_GCPtrMem))
1073# define IEM_MC_FETCH_MEM_FLAT_XMM_NO_AC(a_XmmDst, a_GCPtrMem) \
1074 iemMemFlatFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_GCPtrMem))
1075# define IEM_MC_FETCH_MEM_FLAT_XMM_ALIGN_SSE(a_XmmDst, a_GCPtrMem) \
1076 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, UINT8_MAX, (a_GCPtrMem))
1077# define IEM_MC_FETCH_MEM_FLAT_XMM_U32(a_XmmDst, a_iDWord, a_GCPtrMem) \
1078 (a_XmmDst).au32[(a_iDWord)] = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem))
1079# define IEM_MC_FETCH_MEM_FLAT_XMM_U64(a_XmmDst, a_iQWord, a_GCPtrMem) \
1080 (a_XmmDst).au64[(a_iQWord)] = iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem))
1081
1082# define IEM_MC_FETCH_MEM_U128_AND_XREG_U128(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
1083 iemMemFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_iSeg2), (a_GCPtrMem2)); \
1084 (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1085 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1086 } while (0)
1087# define IEM_MC_FETCH_MEM_FLAT_U128_AND_XREG_U128(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
1088 iemMemFlatFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_GCPtrMem2)); \
1089 (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1090 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1091 } while (0)
1092
1093# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE_AND_XREG_XMM(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
1094 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_Dst).uSrc2.uXmm, (a_iSeg2), (a_GCPtrMem2)); \
1095 (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1096 (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1097 } while (0)
1098# define IEM_MC_FETCH_MEM_FLAT_XMM_ALIGN_SSE_AND_XREG_XMM(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
1099 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_Dst).uSrc2.uXmm, UINT8_MAX, (a_GCPtrMem2)); \
1100 (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1101 (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1102 } while (0)
1103
1104# define IEM_MC_FETCH_MEM_XMM_U32_AND_XREG_XMM(a_Dst, a_iXReg1, a_iDWord2, a_iSeg2, a_GCPtrMem2) do { \
1105 (a_Dst).uSrc2.uXmm.au64[0] = 0; \
1106 (a_Dst).uSrc2.uXmm.au64[1] = 0; \
1107 (a_Dst).uSrc2.uXmm.au32[(a_iDWord2)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg2), (a_GCPtrMem2)); \
1108 (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1109 (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1110 } while (0)
1111# define IEM_MC_FETCH_MEM_FLAT_XMM_U32_AND_XREG_XMM(a_Dst, a_iXReg1, a_iDWord2, a_GCPtrMem2) do { \
1112 (a_Dst).uSrc2.uXmm.au64[0] = 0; \
1113 (a_Dst).uSrc2.uXmm.au64[1] = 0; \
1114 (a_Dst).uSrc2.uXmm.au32[(a_iDWord2)] = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem2)); \
1115 (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1116 (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1117 } while (0)
1118
1119# define IEM_MC_FETCH_MEM_XMM_U64_AND_XREG_XMM(a_Dst, a_iXReg1, a_iQWord2, a_iSeg2, a_GCPtrMem2) do { \
1120 (a_Dst).uSrc2.uXmm.au64[!(a_iQWord2)] = 0; \
1121 (a_Dst).uSrc2.uXmm.au64[(a_iQWord2)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg2), (a_GCPtrMem2)); \
1122 (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1123 (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1124 } while (0)
1125# define IEM_MC_FETCH_MEM_FLAT_XMM_U64_AND_XREG_XMM(a_Dst, a_iXReg1, a_iQWord2, a_GCPtrMem2) do { \
1126 (a_Dst).uSrc2.uXmm.au64[1] = 0; \
1127 (a_Dst).uSrc2.uXmm.au64[(a_iQWord2)] = iemMemFlatFetchDataU64Jmp(pVCpu, (a_GCPtrMem2)); \
1128 (a_Dst).uSrc1.uXmm.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1129 (a_Dst).uSrc1.uXmm.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1130 } while (0)
1131
1132
1133# define IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_RAX_RDX_U64(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
1134 iemMemFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_iSeg2), (a_GCPtrMem2)); \
1135 (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1136 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1137 (a_Dst).u64Rax = pVCpu->cpum.GstCtx.rax; \
1138 (a_Dst).u64Rdx = pVCpu->cpum.GstCtx.rdx; \
1139 } while (0)
1140# define IEM_MC_FETCH_MEM_U128_AND_XREG_U128_AND_EAX_EDX_U32_SX_U64(a_Dst, a_iXReg1, a_iSeg2, a_GCPtrMem2) do { \
1141 iemMemFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_iSeg2), (a_GCPtrMem2)); \
1142 (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1143 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1144 (a_Dst).u64Rax = (int64_t)(int32_t)pVCpu->cpum.GstCtx.eax; \
1145 (a_Dst).u64Rdx = (int64_t)(int32_t)pVCpu->cpum.GstCtx.edx; \
1146 } while (0)
1147
1148# define IEM_MC_FETCH_MEM_FLAT_U128_AND_XREG_U128_AND_RAX_RDX_U64(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
1149 iemMemFlatFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_GCPtrMem2)); \
1150 (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1151 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1152 (a_Dst).u64Rax = pVCpu->cpum.GstCtx.rax; \
1153 (a_Dst).u64Rdx = pVCpu->cpum.GstCtx.rdx; \
1154 } while (0)
1155# define IEM_MC_FETCH_MEM_FLAT_U128_AND_XREG_U128_AND_EAX_EDX_U32_SX_U64(a_Dst, a_iXReg1, a_GCPtrMem2) do { \
1156 iemMemFlatFetchDataU128Jmp(pVCpu, &(a_Dst).uSrc2, (a_GCPtrMem2)); \
1157 (a_Dst).uSrc1.au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[0]; \
1158 (a_Dst).uSrc1.au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg1)].au64[1]; \
1159 (a_Dst).u64Rax = (int64_t)(int32_t)pVCpu->cpum.GstCtx.eax; \
1160 (a_Dst).u64Rdx = (int64_t)(int32_t)pVCpu->cpum.GstCtx.edx; \
1161 } while (0)
1162
1163#endif
1164
1165#ifndef IEM_WITH_SETJMP
1166# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
1167 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
1168# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
1169 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
1170# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
1171 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
1172
1173# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
1174 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
1175# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
1176 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
1177# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
1178 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
1179#else
1180# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
1181 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
1182# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
1183 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
1184# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
1185 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
1186
1187# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
1188 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
1189# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
1190 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
1191# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
1192 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
1193
1194# define IEM_MC_FETCH_MEM_FLAT_U256(a_u256Dst, a_GCPtrMem) \
1195 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), UINT8_MAX, (a_GCPtrMem))
1196# define IEM_MC_FETCH_MEM_FLAT_U256_NO_AC(a_u256Dst, a_GCPtrMem) \
1197 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), UINT8_MAX, (a_GCPtrMem))
1198# define IEM_MC_FETCH_MEM_FLAT_U256_ALIGN_AVX(a_u256Dst, a_GCPtrMem) \
1199 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), UINT8_MAX, (a_GCPtrMem))
1200
1201# define IEM_MC_FETCH_MEM_FLAT_YMM(a_YmmDst, a_GCPtrMem) \
1202 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, UINT8_MAX, (a_GCPtrMem))
1203# define IEM_MC_FETCH_MEM_FLAT_YMM_NO_AC(a_YmmDst, a_GCPtrMem) \
1204 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, UINT8_MAX, (a_GCPtrMem))
1205# define IEM_MC_FETCH_MEM_FLAT_YMM_ALIGN_AVX(a_YmmDst, a_GCPtrMem) \
1206 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, UINT8_MAX, (a_GCPtrMem))
1207#endif
1208
1209
1210
1211#ifndef IEM_WITH_SETJMP
1212# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
1213 do { \
1214 uint8_t u8Tmp; \
1215 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1216 (a_u16Dst) = u8Tmp; \
1217 } while (0)
1218# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1219 do { \
1220 uint8_t u8Tmp; \
1221 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1222 (a_u32Dst) = u8Tmp; \
1223 } while (0)
1224# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1225 do { \
1226 uint8_t u8Tmp; \
1227 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1228 (a_u64Dst) = u8Tmp; \
1229 } while (0)
1230# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1231 do { \
1232 uint16_t u16Tmp; \
1233 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
1234 (a_u32Dst) = u16Tmp; \
1235 } while (0)
1236# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1237 do { \
1238 uint16_t u16Tmp; \
1239 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
1240 (a_u64Dst) = u16Tmp; \
1241 } while (0)
1242# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1243 do { \
1244 uint32_t u32Tmp; \
1245 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
1246 (a_u64Dst) = u32Tmp; \
1247 } while (0)
1248#else /* IEM_WITH_SETJMP */
1249# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
1250 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1251# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1252 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1253# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1254 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1255# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1256 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1257# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1258 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1259# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1260 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1261
1262# define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U16(a_u16Dst, a_GCPtrMem) \
1263 ((a_u16Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1264# define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U32(a_u32Dst, a_GCPtrMem) \
1265 ((a_u32Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1266# define IEM_MC_FETCH_MEM_FLAT_U8_ZX_U64(a_u64Dst, a_GCPtrMem) \
1267 ((a_u64Dst) = iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1268# define IEM_MC_FETCH_MEM_FLAT_U16_ZX_U32(a_u32Dst, a_GCPtrMem) \
1269 ((a_u32Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
1270# define IEM_MC_FETCH_MEM_FLAT_U16_ZX_U64(a_u64Dst, a_GCPtrMem) \
1271 ((a_u64Dst) = iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
1272# define IEM_MC_FETCH_MEM_FLAT_U32_ZX_U64(a_u64Dst, a_GCPtrMem) \
1273 ((a_u64Dst) = iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
1274#endif /* IEM_WITH_SETJMP */
1275
1276#ifndef IEM_WITH_SETJMP
1277# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
1278 do { \
1279 uint8_t u8Tmp; \
1280 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1281 (a_u16Dst) = (int8_t)u8Tmp; \
1282 } while (0)
1283# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1284 do { \
1285 uint8_t u8Tmp; \
1286 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1287 (a_u32Dst) = (int8_t)u8Tmp; \
1288 } while (0)
1289# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1290 do { \
1291 uint8_t u8Tmp; \
1292 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
1293 (a_u64Dst) = (int8_t)u8Tmp; \
1294 } while (0)
1295# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1296 do { \
1297 uint16_t u16Tmp; \
1298 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
1299 (a_u32Dst) = (int16_t)u16Tmp; \
1300 } while (0)
1301# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1302 do { \
1303 uint16_t u16Tmp; \
1304 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
1305 (a_u64Dst) = (int16_t)u16Tmp; \
1306 } while (0)
1307# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1308 do { \
1309 uint32_t u32Tmp; \
1310 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
1311 (a_u64Dst) = (int32_t)u32Tmp; \
1312 } while (0)
1313#else /* IEM_WITH_SETJMP */
1314# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
1315 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1316# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1317 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1318# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1319 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1320# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
1321 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1322# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1323 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1324# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
1325 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
1326
1327# define IEM_MC_FETCH_MEM_FLAT_U8_SX_U16(a_u16Dst, a_GCPtrMem) \
1328 ((a_u16Dst) = (int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1329# define IEM_MC_FETCH_MEM_FLAT_U8_SX_U32(a_u32Dst, a_GCPtrMem) \
1330 ((a_u32Dst) = (int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1331# define IEM_MC_FETCH_MEM_FLAT_U8_SX_U64(a_u64Dst, a_GCPtrMem) \
1332 ((a_u64Dst) = (int8_t)iemMemFlatFetchDataU8Jmp(pVCpu, (a_GCPtrMem)))
1333# define IEM_MC_FETCH_MEM_FLAT_U16_SX_U32(a_u32Dst, a_GCPtrMem) \
1334 ((a_u32Dst) = (int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
1335# define IEM_MC_FETCH_MEM_FLAT_U16_SX_U64(a_u64Dst, a_GCPtrMem) \
1336 ((a_u64Dst) = (int16_t)iemMemFlatFetchDataU16Jmp(pVCpu, (a_GCPtrMem)))
1337# define IEM_MC_FETCH_MEM_FLAT_U32_SX_U64(a_u64Dst, a_GCPtrMem) \
1338 ((a_u64Dst) = (int32_t)iemMemFlatFetchDataU32Jmp(pVCpu, (a_GCPtrMem)))
1339#endif /* IEM_WITH_SETJMP */
1340
1341#ifndef IEM_WITH_SETJMP
1342# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
1343 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
1344# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
1345 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
1346# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
1347 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
1348# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
1349 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
1350#else
1351# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
1352 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
1353# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
1354 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
1355# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
1356 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
1357# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
1358 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
1359
1360# define IEM_MC_STORE_MEM_FLAT_U8(a_GCPtrMem, a_u8Value) \
1361 iemMemFlatStoreDataU8Jmp(pVCpu, (a_GCPtrMem), (a_u8Value))
1362# define IEM_MC_STORE_MEM_FLAT_U16(a_GCPtrMem, a_u16Value) \
1363 iemMemFlatStoreDataU16Jmp(pVCpu, (a_GCPtrMem), (a_u16Value))
1364# define IEM_MC_STORE_MEM_FLAT_U32(a_GCPtrMem, a_u32Value) \
1365 iemMemFlatStoreDataU32Jmp(pVCpu, (a_GCPtrMem), (a_u32Value))
1366# define IEM_MC_STORE_MEM_FLAT_U64(a_GCPtrMem, a_u64Value) \
1367 iemMemFlatStoreDataU64Jmp(pVCpu, (a_GCPtrMem), (a_u64Value))
1368#endif
1369
1370#ifndef IEM_WITH_SETJMP
1371# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
1372 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
1373# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
1374 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
1375# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
1376 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
1377# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1378 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
1379#else
1380# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
1381 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
1382# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
1383 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
1384# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
1385 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
1386# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1387 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
1388
1389# define IEM_MC_STORE_MEM_FLAT_U8_CONST(a_GCPtrMem, a_u8C) \
1390 iemMemFlatStoreDataU8Jmp(pVCpu, (a_GCPtrMem), (a_u8C))
1391# define IEM_MC_STORE_MEM_FLAT_U16_CONST(a_GCPtrMem, a_u16C) \
1392 iemMemFlatStoreDataU16Jmp(pVCpu, (a_GCPtrMem), (a_u16C))
1393# define IEM_MC_STORE_MEM_FLAT_U32_CONST(a_GCPtrMem, a_u32C) \
1394 iemMemFlatStoreDataU32Jmp(pVCpu, (a_GCPtrMem), (a_u32C))
1395# define IEM_MC_STORE_MEM_FLAT_U64_CONST(a_GCPtrMem, a_u64C) \
1396 iemMemFlatStoreDataU64Jmp(pVCpu, (a_GCPtrMem), (a_u64C))
1397#endif
1398
1399#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
1400#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
1401#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
1402#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
1403#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
1404#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
1405#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
1406 do { \
1407 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1408 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
1409 } while (0)
1410#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
1411 do { \
1412 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1413 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
1414 } while (0)
1415
1416#ifndef IEM_WITH_SETJMP
1417# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1418 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u128Value)))
1419# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1420 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1421#else
1422# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1423 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u128Value))
1424# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1425 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1426
1427# define IEM_MC_STORE_MEM_FLAT_U128(a_GCPtrMem, a_u128Value) \
1428 iemMemFlatStoreDataU128Jmp(pVCpu, (a_GCPtrMem), &(a_u128Value))
1429# define IEM_MC_STORE_MEM_FLAT_U128_ALIGN_SSE(a_GCPtrMem, a_u128Value) \
1430 iemMemStoreDataU128AlignedSseJmp(pVCpu, UINT8_MAX, (a_GCPtrMem), (a_u128Value))
1431#endif
1432
1433#ifndef IEM_WITH_SETJMP
1434# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1435 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1436# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1437 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1438#else
1439# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1440 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1441# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1442 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1443
1444# define IEM_MC_STORE_MEM_FLAT_U256(a_GCPtrMem, a_u256Value) \
1445 iemMemStoreDataU256Jmp(pVCpu, UINT8_MAX, (a_GCPtrMem), &(a_u256Value))
1446# define IEM_MC_STORE_MEM_FLAT_U256_ALIGN_AVX(a_GCPtrMem, a_u256Value) \
1447 iemMemStoreDataU256AlignedAvxJmp(pVCpu, UINT8_MAX, (a_GCPtrMem), &(a_u256Value))
1448#endif
1449
1450/* Regular stack push and pop: */
1451#ifndef IEM_WITH_SETJMP
1452# define IEM_MC_PUSH_U16(a_u16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1453# define IEM_MC_PUSH_U32(a_u32Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1454# define IEM_MC_PUSH_U32_SREG(a_uSegVal) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_uSegVal)))
1455# define IEM_MC_PUSH_U64(a_u64Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1456
1457# define IEM_MC_POP_U16(a_pu16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1458# define IEM_MC_POP_U32(a_pu32Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1459# define IEM_MC_POP_U64(a_pu64Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1460#else
1461# define IEM_MC_PUSH_U16(a_u16Value) iemMemStackPushU16Jmp(pVCpu, (a_u16Value))
1462# define IEM_MC_PUSH_U32(a_u32Value) iemMemStackPushU32Jmp(pVCpu, (a_u32Value))
1463# define IEM_MC_PUSH_U32_SREG(a_uSegVal) iemMemStackPushU32SRegJmp(pVCpu, (a_uSegVal))
1464# define IEM_MC_PUSH_U64(a_u64Value) iemMemStackPushU64Jmp(pVCpu, (a_u64Value))
1465
1466# define IEM_MC_POP_U16(a_pu16Value) (*(a_pu16Value) = iemMemStackPopU16Jmp(pVCpu))
1467# define IEM_MC_POP_U32(a_pu32Value) (*(a_pu32Value) = iemMemStackPopU32Jmp(pVCpu))
1468# define IEM_MC_POP_U64(a_pu64Value) (*(a_pu64Value) = iemMemStackPopU64Jmp(pVCpu))
1469#endif
1470
1471/* 32-bit flat stack push and pop: */
1472#ifndef IEM_WITH_SETJMP
1473# define IEM_MC_FLAT32_PUSH_U16(a_u16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1474# define IEM_MC_FLAT32_PUSH_U32(a_u32Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1475# define IEM_MC_FLAT32_PUSH_U32_SREG(a_uSegVal) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_uSegVal)))
1476
1477# define IEM_MC_FLAT32_POP_U16(a_pu16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1478# define IEM_MC_FLAT32_POP_U32(a_pu32Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1479#else
1480# define IEM_MC_FLAT32_PUSH_U16(a_u16Value) iemMemFlat32StackPushU16Jmp(pVCpu, (a_u16Value))
1481# define IEM_MC_FLAT32_PUSH_U32(a_u32Value) iemMemFlat32StackPushU32Jmp(pVCpu, (a_u32Value))
1482# define IEM_MC_FLAT32_PUSH_U32_SREG(a_uSegVal) iemMemFlat32StackPushU32SRegJmp(pVCpu, (a_uSegVal))
1483
1484# define IEM_MC_FLAT32_POP_U16(a_pu16Value) (*(a_pu16Value) = iemMemFlat32StackPopU16Jmp(pVCpu))
1485# define IEM_MC_FLAT32_POP_U32(a_pu32Value) (*(a_pu32Value) = iemMemFlat32StackPopU32Jmp(pVCpu))
1486#endif
1487
1488/* 64-bit flat stack push and pop: */
1489#ifndef IEM_WITH_SETJMP
1490# define IEM_MC_FLAT64_PUSH_U16(a_u16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1491# define IEM_MC_FLAT64_PUSH_U64(a_u64Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1492
1493# define IEM_MC_FLAT64_POP_U16(a_pu16Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1494# define IEM_MC_FLAT64_POP_U64(a_pu64Value) IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1495#else
1496# define IEM_MC_FLAT64_PUSH_U16(a_u16Value) iemMemFlat64StackPushU16Jmp(pVCpu, (a_u16Value))
1497# define IEM_MC_FLAT64_PUSH_U64(a_u64Value) iemMemFlat64StackPushU64Jmp(pVCpu, (a_u64Value))
1498
1499# define IEM_MC_FLAT64_POP_U16(a_pu16Value) (*(a_pu16Value) = iemMemFlat64StackPopU16Jmp(pVCpu))
1500# define IEM_MC_FLAT64_POP_U64(a_pu64Value) (*(a_pu64Value) = iemMemFlat64StackPopU64Jmp(pVCpu))
1501#endif
1502
1503
1504/* 8-bit */
1505
1506/**
1507 * Maps guest memory for byte read+write direct (or bounce) buffer acccess.
1508 *
1509 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1510 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1511 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1512 * @param[in] a_GCPtrMem The memory address.
1513 * @remarks Will return/long jump on errors.
1514 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1515 */
1516#ifndef IEM_WITH_SETJMP
1517# define IEM_MC_MEM_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1518 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), &(a_bUnmapInfo), sizeof(uint8_t), (a_iSeg), \
1519 (a_GCPtrMem), IEM_ACCESS_DATA_RW, 0))
1520#else
1521# define IEM_MC_MEM_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1522 (a_pu8Mem) = iemMemMapDataU8RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1523#endif
1524
1525/**
1526 * Maps guest memory for byte writeonly direct (or bounce) buffer acccess.
1527 *
1528 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1529 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1530 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1531 * @param[in] a_GCPtrMem The memory address.
1532 * @remarks Will return/long jump on errors.
1533 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1534 */
1535#ifndef IEM_WITH_SETJMP
1536# define IEM_MC_MEM_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1537 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), &(a_bUnmapInfo), sizeof(uint8_t), (a_iSeg), \
1538 (a_GCPtrMem), IEM_ACCESS_DATA_W, 0))
1539#else
1540# define IEM_MC_MEM_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1541 (a_pu8Mem) = iemMemMapDataU8WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1542#endif
1543
1544/**
1545 * Maps guest memory for byte readonly direct (or bounce) buffer acccess.
1546 *
1547 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1548 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1549 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1550 * @param[in] a_GCPtrMem The memory address.
1551 * @remarks Will return/long jump on errors.
1552 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1553 */
1554#ifndef IEM_WITH_SETJMP
1555# define IEM_MC_MEM_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1556 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), &(a_bUnmapInfo), sizeof(uint8_t), (a_iSeg), \
1557 (a_GCPtrMem), IEM_ACCESS_DATA_R, 0))
1558#else
1559# define IEM_MC_MEM_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1560 (a_pu8Mem) = iemMemMapDataU8RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1561#endif
1562
1563/**
1564 * Maps guest memory for byte read+write direct (or bounce) buffer acccess, flat
1565 * address variant.
1566 *
1567 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1568 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1569 * @param[in] a_GCPtrMem The memory address.
1570 * @remarks Will return/long jump on errors.
1571 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1572 */
1573#ifndef IEM_WITH_SETJMP
1574# define IEM_MC_MEM_FLAT_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
1575 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), &(a_bUnmapInfo), sizeof(uint8_t), UINT8_MAX, \
1576 (a_GCPtrMem), IEM_ACCESS_DATA_RW, 0))
1577#else
1578# define IEM_MC_MEM_FLAT_MAP_U8_RW(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
1579 (a_pu8Mem) = iemMemFlatMapDataU8RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1580#endif
1581
1582/**
1583 * Maps guest memory for byte writeonly direct (or bounce) buffer acccess, flat
1584 * address variant.
1585 *
1586 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1587 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1588 * @param[in] a_GCPtrMem The memory address.
1589 * @remarks Will return/long jump on errors.
1590 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1591 */
1592#ifndef IEM_WITH_SETJMP
1593# define IEM_MC_MEM_FLAT_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
1594 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), &(a_bUnmapInfo), sizeof(uint8_t), UINT8_MAX, \
1595 (a_GCPtrMem), IEM_ACCESS_DATA_W, 0))
1596#else
1597# define IEM_MC_MEM_FLAT_MAP_U8_WO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
1598 (a_pu8Mem) = iemMemFlatMapDataU8WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1599#endif
1600
1601/**
1602 * Maps guest memory for byte readonly direct (or bounce) buffer acccess, flat
1603 * address variant.
1604 *
1605 * @param[out] a_pu8Mem Where to return the pointer to the mapping.
1606 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1607 * @param[in] a_GCPtrMem The memory address.
1608 * @remarks Will return/long jump on errors.
1609 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1610 */
1611#ifndef IEM_WITH_SETJMP
1612# define IEM_MC_MEM_FLAT_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
1613 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu8Mem), &(a_bUnmapInfo), sizeof(uint8_t), UINT8_MAX, \
1614 (a_GCPtrMem), IEM_ACCESS_DATA_R, 0))
1615#else
1616# define IEM_MC_MEM_FLAT_MAP_U8_RO(a_pu8Mem, a_bUnmapInfo, a_GCPtrMem) \
1617 (a_pu8Mem) = iemMemFlatMapDataU8RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1618#endif
1619
1620
1621/* 16-bit */
1622
1623/**
1624 * Maps guest memory for word read+write direct (or bounce) buffer acccess.
1625 *
1626 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1627 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1628 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1629 * @param[in] a_GCPtrMem The memory address.
1630 * @remarks Will return/long jump on errors.
1631 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1632 */
1633#ifndef IEM_WITH_SETJMP
1634# define IEM_MC_MEM_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1635 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), &(a_bUnmapInfo), sizeof(uint16_t), (a_iSeg), \
1636 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint16_t) - 1))
1637#else
1638# define IEM_MC_MEM_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1639 (a_pu16Mem) = iemMemMapDataU16RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1640#endif
1641
1642/**
1643 * Maps guest memory for word writeonly direct (or bounce) buffer acccess.
1644 *
1645 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1646 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1647 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1648 * @param[in] a_GCPtrMem The memory address.
1649 * @remarks Will return/long jump on errors.
1650 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1651 */
1652#ifndef IEM_WITH_SETJMP
1653# define IEM_MC_MEM_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1654 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), &(a_bUnmapInfo), sizeof(uint16_t), (a_iSeg), \
1655 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint16_t) - 1))
1656#else
1657# define IEM_MC_MEM_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1658 (a_pu16Mem) = iemMemMapDataU16WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1659#endif
1660
1661/**
1662 * Maps guest memory for word readonly direct (or bounce) buffer acccess.
1663 *
1664 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1665 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1666 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1667 * @param[in] a_GCPtrMem The memory address.
1668 * @remarks Will return/long jump on errors.
1669 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1670 */
1671#ifndef IEM_WITH_SETJMP
1672# define IEM_MC_MEM_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1673 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), &(a_bUnmapInfo), sizeof(uint16_t), (a_iSeg), \
1674 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint16_t) - 1))
1675#else
1676# define IEM_MC_MEM_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1677 (a_pu16Mem) = iemMemMapDataU16RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1678#endif
1679
1680/**
1681 * Maps guest memory for word read+write direct (or bounce) buffer acccess, flat
1682 * address variant.
1683 *
1684 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1685 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1686 * @param[in] a_GCPtrMem The memory address.
1687 * @remarks Will return/long jump on errors.
1688 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1689 */
1690#ifndef IEM_WITH_SETJMP
1691# define IEM_MC_MEM_FLAT_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
1692 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), &(a_bUnmapInfo), sizeof(uint16_t), UINT8_MAX, \
1693 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint16_t) - 1))
1694#else
1695# define IEM_MC_MEM_FLAT_MAP_U16_RW(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
1696 (a_pu16Mem) = iemMemFlatMapDataU16RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1697#endif
1698
1699/**
1700 * Maps guest memory for word writeonly direct (or bounce) buffer acccess, flat
1701 * address variant.
1702 *
1703 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1704 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1705 * @param[in] a_GCPtrMem The memory address.
1706 * @remarks Will return/long jump on errors.
1707 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1708 */
1709#ifndef IEM_WITH_SETJMP
1710# define IEM_MC_MEM_FLAT_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
1711 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), &(a_bUnmapInfo), sizeof(uint16_t), UINT8_MAX, \
1712 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint16_t) - 1))
1713#else
1714# define IEM_MC_MEM_FLAT_MAP_U16_WO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
1715 (a_pu16Mem) = iemMemFlatMapDataU16WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1716#endif
1717
1718/**
1719 * Maps guest memory for word readonly direct (or bounce) buffer acccess, flat
1720 * address variant.
1721 *
1722 * @param[out] a_pu16Mem Where to return the pointer to the mapping.
1723 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1724 * @param[in] a_GCPtrMem The memory address.
1725 * @remarks Will return/long jump on errors.
1726 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1727 */
1728#ifndef IEM_WITH_SETJMP
1729# define IEM_MC_MEM_FLAT_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
1730 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu16Mem), &(a_bUnmapInfo), sizeof(uint16_t), UINT8_MAX, \
1731 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint16_t) - 1))
1732#else
1733# define IEM_MC_MEM_FLAT_MAP_U16_RO(a_pu16Mem, a_bUnmapInfo, a_GCPtrMem) \
1734 (a_pu16Mem) = iemMemFlatMapDataU16RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1735#endif
1736
1737/** int16_t alias. */
1738#ifndef IEM_WITH_SETJMP
1739# define IEM_MC_MEM_MAP_I16_WO(a_pi16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1740 IEM_MC_MEM_MAP_U16_WO(a_pi16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem)
1741#else
1742# define IEM_MC_MEM_MAP_I16_WO(a_pi16Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1743 (a_pi16Mem) = (int16_t *)iemMemMapDataU16WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1744#endif
1745
1746/** Flat int16_t alias. */
1747#ifndef IEM_WITH_SETJMP
1748# define IEM_MC_MEM_FLAT_MAP_I16_WO(a_pi16Mem, a_bUnmapInfo, a_GCPtrMem) \
1749 IEM_MC_MEM_FLAT_MAP_U16_WO(a_pi16Mem, a_bUnmapInfo, a_GCPtrMem)
1750#else
1751# define IEM_MC_MEM_FLAT_MAP_I16_WO(a_pi16Mem, a_bUnmapInfo, a_GCPtrMem) \
1752 (a_pi16Mem) = (int16_t *)iemMemFlatMapDataU16WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1753#endif
1754
1755
1756/* 32-bit */
1757
1758/**
1759 * Maps guest memory for dword read+write direct (or bounce) buffer acccess.
1760 *
1761 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1762 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1763 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1764 * @param[in] a_GCPtrMem The memory address.
1765 * @remarks Will return/long jump on errors.
1766 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1767 */
1768#ifndef IEM_WITH_SETJMP
1769# define IEM_MC_MEM_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1770 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), &(a_bUnmapInfo), sizeof(uint32_t), (a_iSeg), \
1771 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint32_t) - 1))
1772#else
1773# define IEM_MC_MEM_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1774 (a_pu32Mem) = iemMemMapDataU32RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1775#endif
1776
1777/**
1778 * Maps guest memory for dword writeonly direct (or bounce) buffer acccess.
1779 *
1780 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1781 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1782 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1783 * @param[in] a_GCPtrMem The memory address.
1784 * @remarks Will return/long jump on errors.
1785 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1786 */
1787#ifndef IEM_WITH_SETJMP
1788# define IEM_MC_MEM_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1789 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), &(a_bUnmapInfo), sizeof(uint32_t), (a_iSeg), \
1790 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint32_t) - 1))
1791#else
1792# define IEM_MC_MEM_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1793 (a_pu32Mem) = iemMemMapDataU32WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1794#endif
1795
1796/**
1797 * Maps guest memory for dword readonly direct (or bounce) buffer acccess.
1798 *
1799 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1800 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1801 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1802 * @param[in] a_GCPtrMem The memory address.
1803 * @remarks Will return/long jump on errors.
1804 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1805 */
1806#ifndef IEM_WITH_SETJMP
1807# define IEM_MC_MEM_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1808 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), &(a_bUnmapInfo), sizeof(uint32_t), (a_iSeg), \
1809 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint32_t) - 1))
1810#else
1811# define IEM_MC_MEM_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1812 (a_pu32Mem) = iemMemMapDataU32RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1813#endif
1814
1815/**
1816 * Maps guest memory for dword read+write direct (or bounce) buffer acccess,
1817 * flat address variant.
1818 *
1819 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1820 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1821 * @param[in] a_GCPtrMem The memory address.
1822 * @remarks Will return/long jump on errors.
1823 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1824 */
1825#ifndef IEM_WITH_SETJMP
1826# define IEM_MC_MEM_FLAT_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
1827 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), &(a_bUnmapInfo), sizeof(uint32_t), UINT8_MAX, \
1828 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint32_t) - 1))
1829#else
1830# define IEM_MC_MEM_FLAT_MAP_U32_RW(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
1831 (a_pu32Mem) = iemMemFlatMapDataU32RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1832#endif
1833
1834/**
1835 * Maps guest memory for dword writeonly direct (or bounce) buffer acccess, flat
1836 * address variant.
1837 *
1838 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1839 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1840 * @param[in] a_GCPtrMem The memory address.
1841 * @remarks Will return/long jump on errors.
1842 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1843 */
1844#ifndef IEM_WITH_SETJMP
1845# define IEM_MC_MEM_FLAT_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
1846 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), &(a_bUnmapInfo), sizeof(uint32_t), UINT8_MAX, \
1847 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint32_t) - 1))
1848#else
1849# define IEM_MC_MEM_FLAT_MAP_U32_WO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
1850 (a_pu32Mem) = iemMemFlatMapDataU32WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1851#endif
1852
1853/**
1854 * Maps guest memory for dword readonly direct (or bounce) buffer acccess, flat
1855 * address variant.
1856 *
1857 * @param[out] a_pu32Mem Where to return the pointer to the mapping.
1858 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1859 * @param[in] a_GCPtrMem The memory address.
1860 * @remarks Will return/long jump on errors.
1861 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1862 */
1863#ifndef IEM_WITH_SETJMP
1864# define IEM_MC_MEM_FLAT_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
1865 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu32Mem), &(a_bUnmapInfo), sizeof(uint32_t), UINT8_MAX, \
1866 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint32_t) - 1))
1867#else
1868# define IEM_MC_MEM_FLAT_MAP_U32_RO(a_pu32Mem, a_bUnmapInfo, a_GCPtrMem) \
1869 (a_pu32Mem) = iemMemFlatMapDataU32RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1870#endif
1871
1872/** int32_t alias. */
1873#ifndef IEM_WITH_SETJMP
1874# define IEM_MC_MEM_MAP_I32_WO(a_pi32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1875 IEM_MC_MEM_MAP_U32_WO(a_pi32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem)
1876#else
1877# define IEM_MC_MEM_MAP_I32_WO(a_pi32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1878 (a_pi32Mem) = (int32_t *)iemMemMapDataU32WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1879#endif
1880
1881/** Flat int32_t alias. */
1882#ifndef IEM_WITH_SETJMP
1883# define IEM_MC_MEM_FLAT_MAP_I32_WO(a_pi32Mem, a_bUnmapInfo, a_GCPtrMem) \
1884 IEM_MC_MEM_FLAT_MAP_U32_WO(a_pi32Mem, a_bUnmapInfo, a_GCPtrMem)
1885#else
1886# define IEM_MC_MEM_FLAT_MAP_I32_WO(a_pi32Mem, a_bUnmapInfo, a_GCPtrMem) \
1887 (a_pi32Mem) = (int32_t *)iemMemFlatMapDataU32WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1888#endif
1889
1890/** RTFLOAT32U alias. */
1891#ifndef IEM_WITH_SETJMP
1892# define IEM_MC_MEM_MAP_R32_WO(a_pr32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1893 IEM_MC_MEM_MAP_U32_WO(a_pr32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem)
1894#else
1895# define IEM_MC_MEM_MAP_R32_WO(a_pr32Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1896 (a_pr32Mem) = (PRTFLOAT32U)iemMemMapDataU32WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1897#endif
1898
1899/** Flat RTFLOAT32U alias. */
1900#ifndef IEM_WITH_SETJMP
1901# define IEM_MC_MEM_FLAT_MAP_R32_WO(a_pr32Mem, a_bUnmapInfo, a_GCPtrMem) \
1902 IEM_MC_MEM_FLAT_MAP_U32_WO(a_pr32Mem, a_bUnmapInfo, a_GCPtrMem)
1903#else
1904# define IEM_MC_MEM_FLAT_MAP_R32_WO(a_pr32Mem, a_bUnmapInfo, a_GCPtrMem) \
1905 (a_pr32Mem) = (PRTFLOAT32U)iemMemFlatMapDataU32WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1906#endif
1907
1908
1909/* 64-bit */
1910
1911/**
1912 * Maps guest memory for qword read+write direct (or bounce) buffer acccess.
1913 *
1914 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
1915 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1916 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1917 * @param[in] a_GCPtrMem The memory address.
1918 * @remarks Will return/long jump on errors.
1919 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1920 */
1921#ifndef IEM_WITH_SETJMP
1922# define IEM_MC_MEM_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1923 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), &(a_bUnmapInfo), sizeof(uint64_t), (a_iSeg), \
1924 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint64_t) - 1))
1925#else
1926# define IEM_MC_MEM_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1927 (a_pu64Mem) = iemMemMapDataU64RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1928#endif
1929
1930/**
1931 * Maps guest memory for qword writeonly direct (or bounce) buffer acccess.
1932 *
1933 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
1934 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1935 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1936 * @param[in] a_GCPtrMem The memory address.
1937 * @remarks Will return/long jump on errors.
1938 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1939 */
1940#ifndef IEM_WITH_SETJMP
1941# define IEM_MC_MEM_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1942 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), &(a_bUnmapInfo), sizeof(uint64_t), (a_iSeg), \
1943 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1))
1944#else
1945# define IEM_MC_MEM_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1946 (a_pu64Mem) = iemMemMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1947#endif
1948
1949/**
1950 * Maps guest memory for qword readonly direct (or bounce) buffer acccess.
1951 *
1952 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
1953 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1954 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
1955 * @param[in] a_GCPtrMem The memory address.
1956 * @remarks Will return/long jump on errors.
1957 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
1958 */
1959#ifndef IEM_WITH_SETJMP
1960# define IEM_MC_MEM_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1961 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), &(a_bUnmapInfo), sizeof(uint64_t), (a_iSeg), \
1962 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint64_t) - 1))
1963#else
1964# define IEM_MC_MEM_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
1965 (a_pu64Mem) = iemMemMapDataU64RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
1966#endif
1967
1968/**
1969 * Maps guest memory for qword read+write direct (or bounce) buffer acccess,
1970 * flat address variant.
1971 *
1972 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
1973 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1974 * @param[in] a_GCPtrMem The memory address.
1975 * @remarks Will return/long jump on errors.
1976 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
1977 */
1978#ifndef IEM_WITH_SETJMP
1979# define IEM_MC_MEM_FLAT_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
1980 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), &(a_bUnmapInfo), sizeof(uint64_t), UINT8_MAX, \
1981 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(uint64_t) - 1))
1982#else
1983# define IEM_MC_MEM_FLAT_MAP_U64_RW(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
1984 (a_pu64Mem) = iemMemFlatMapDataU64RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
1985#endif
1986
1987/**
1988 * Maps guest memory for qword writeonly direct (or bounce) buffer acccess, flat
1989 * address variant.
1990 *
1991 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
1992 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
1993 * @param[in] a_GCPtrMem The memory address.
1994 * @remarks Will return/long jump on errors.
1995 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
1996 */
1997#ifndef IEM_WITH_SETJMP
1998# define IEM_MC_MEM_FLAT_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
1999 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), &(a_bUnmapInfo), sizeof(uint64_t), UINT8_MAX, \
2000 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1))
2001#else
2002# define IEM_MC_MEM_FLAT_MAP_U64_WO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
2003 (a_pu64Mem) = iemMemFlatMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
2004#endif
2005
2006/**
2007 * Maps guest memory for qword readonly direct (or bounce) buffer acccess, flat
2008 * address variant.
2009 *
2010 * @param[out] a_pu64Mem Where to return the pointer to the mapping.
2011 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
2012 * @param[in] a_GCPtrMem The memory address.
2013 * @remarks Will return/long jump on errors.
2014 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
2015 */
2016#ifndef IEM_WITH_SETJMP
2017# define IEM_MC_MEM_FLAT_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
2018 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu64Mem), &(a_bUnmapInfo), sizeof(uint64_t), UINT8_MAX, \
2019 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(uint64_t) - 1))
2020#else
2021# define IEM_MC_MEM_FLAT_MAP_U64_RO(a_pu64Mem, a_bUnmapInfo, a_GCPtrMem) \
2022 (a_pu64Mem) = iemMemFlatMapDataU64RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
2023#endif
2024
2025/** int64_t alias. */
2026#ifndef IEM_WITH_SETJMP
2027# define IEM_MC_MEM_MAP_I64_WO(a_pi64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
2028 IEM_MC_MEM_MAP_U64_WO(a_pi64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem)
2029#else
2030# define IEM_MC_MEM_MAP_I64_WO(a_pi64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
2031 (a_pi64Mem) = (int64_t *)iemMemMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
2032#endif
2033
2034/** Flat int64_t alias. */
2035#ifndef IEM_WITH_SETJMP
2036# define IEM_MC_MEM_FLAT_MAP_I64_WO(a_pi64Mem, a_bUnmapInfo, a_GCPtrMem) \
2037 IEM_MC_MEM_FLAT_MAP_U64_WO(a_pi64Mem, a_bUnmapInfo, a_GCPtrMem)
2038#else
2039# define IEM_MC_MEM_FLAT_MAP_I64_WO(a_pi64Mem, a_bUnmapInfo, a_GCPtrMem) \
2040 (a_pi64Mem) = (int64_t *)iemMemFlatMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
2041#endif
2042
2043/** RTFLOAT64U alias. */
2044#ifndef IEM_WITH_SETJMP
2045# define IEM_MC_MEM_MAP_R64_WO(a_pr64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
2046 IEM_MC_MEM_MAP_U64_WO(a_pr64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem)
2047#else
2048# define IEM_MC_MEM_MAP_R64_WO(a_pr64Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
2049 (a_pr64Mem) = (PRTFLOAT64U)iemMemMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
2050#endif
2051
2052/** Flat RTFLOAT64U alias. */
2053#ifndef IEM_WITH_SETJMP
2054# define IEM_MC_MEM_FLAT_MAP_R64_WO(a_pr64Mem, a_bUnmapInfo, a_GCPtrMem) \
2055 IEM_MC_MEM_FLAT_MAP_U64_WO(a_pr64Mem, a_bUnmapInfo, a_GCPtrMem)
2056#else
2057# define IEM_MC_MEM_FLAT_MAP_R64_WO(a_pr64Mem, a_bUnmapInfo, a_GCPtrMem) \
2058 (a_pr64Mem) = (PRTFLOAT64U)iemMemFlatMapDataU64WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
2059#endif
2060
2061
2062/* 128-bit */
2063
2064/**
2065 * Maps guest memory for dqword read+write direct (or bounce) buffer acccess.
2066 *
2067 * @param[out] a_pu128Mem Where to return the pointer to the mapping.
2068 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
2069 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
2070 * @param[in] a_GCPtrMem The memory address.
2071 * @remarks Will return/long jump on errors.
2072 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
2073 */
2074#ifndef IEM_WITH_SETJMP
2075# define IEM_MC_MEM_MAP_U128_RW(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
2076 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu128Mem), &(a_bUnmapInfo), sizeof(RTUINT128U), (a_iSeg), \
2077 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(RTUINT128U) - 1))
2078#else
2079# define IEM_MC_MEM_MAP_U128_RW(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
2080 (a_pu128Mem) = iemMemMapDataU128RwJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
2081#endif
2082
2083/**
2084 * Maps guest memory for dqword writeonly direct (or bounce) buffer acccess.
2085 *
2086 * @param[out] a_pu128Mem Where to return the pointer to the mapping.
2087 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
2088 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
2089 * @param[in] a_GCPtrMem The memory address.
2090 * @remarks Will return/long jump on errors.
2091 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
2092 */
2093#ifndef IEM_WITH_SETJMP
2094# define IEM_MC_MEM_MAP_U128_WO(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
2095 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu128Mem), &(a_bUnmapInfo), sizeof(RTUINT128), (a_iSeg), \
2096 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(RTUINT128) - 1))
2097#else
2098# define IEM_MC_MEM_MAP_U128_WO(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
2099 (a_pu128Mem) = iemMemMapDataU128WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
2100#endif
2101
2102/**
2103 * Maps guest memory for dqword readonly direct (or bounce) buffer acccess.
2104 *
2105 * @param[out] a_pu128Mem Where to return the pointer to the mapping.
2106 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
2107 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
2108 * @param[in] a_GCPtrMem The memory address.
2109 * @remarks Will return/long jump on errors.
2110 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
2111 */
2112#ifndef IEM_WITH_SETJMP
2113# define IEM_MC_MEM_MAP_U128_RO(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
2114 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu128Mem), &(a_bUnmapInfo), sizeof(RTUINT128), (a_iSeg), \
2115 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(RTUINT128) - 1))
2116#else
2117# define IEM_MC_MEM_MAP_U128_RO(a_pu128Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
2118 (a_pu128Mem) = iemMemMapDataU128RoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
2119#endif
2120
2121/**
2122 * Maps guest memory for dqword read+write direct (or bounce) buffer acccess,
2123 * flat address variant.
2124 *
2125 * @param[out] a_pu128Mem Where to return the pointer to the mapping.
2126 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
2127 * @param[in] a_GCPtrMem The memory address.
2128 * @remarks Will return/long jump on errors.
2129 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RW
2130 */
2131#ifndef IEM_WITH_SETJMP
2132# define IEM_MC_MEM_FLAT_MAP_U128_RW(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
2133 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu128Mem), &(a_bUnmapInfo), sizeof(RTUINT128), UINT8_MAX, \
2134 (a_GCPtrMem), IEM_ACCESS_DATA_RW, sizeof(RTUINT128) - 1))
2135#else
2136# define IEM_MC_MEM_FLAT_MAP_U128_RW(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
2137 (a_pu128Mem) = iemMemFlatMapDataU128RwJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
2138#endif
2139
2140/**
2141 * Maps guest memory for dqword writeonly direct (or bounce) buffer acccess,
2142 * flat address variant.
2143 *
2144 * @param[out] a_pu128Mem Where to return the pointer to the mapping.
2145 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
2146 * @param[in] a_GCPtrMem The memory address.
2147 * @remarks Will return/long jump on errors.
2148 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
2149 */
2150#ifndef IEM_WITH_SETJMP
2151# define IEM_MC_MEM_FLAT_MAP_U128_WO(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
2152 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu128Mem), &(a_bUnmapInfo), sizeof(RTUINT128), UINT8_MAX, \
2153 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(RTUINT128) - 1))
2154#else
2155# define IEM_MC_MEM_FLAT_MAP_U128_WO(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
2156 (a_pu128Mem) = iemMemFlatMapDataU128WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
2157#endif
2158
2159/**
2160 * Maps guest memory for dqword readonly direct (or bounce) buffer acccess, flat
2161 * address variant.
2162 *
2163 * @param[out] a_pu128Mem Where to return the pointer to the mapping.
2164 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
2165 * @param[in] a_GCPtrMem The memory address.
2166 * @remarks Will return/long jump on errors.
2167 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_RO
2168 */
2169#ifndef IEM_WITH_SETJMP
2170# define IEM_MC_MEM_FLAT_MAP_U128_RO(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
2171 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pu128Mem), &(a_bUnmapInfo), sizeof(RTUINT128), UINT8_MAX, \
2172 (a_GCPtrMem), IEM_ACCESS_DATA_R, sizeof(RTUINT128) - 1))
2173#else
2174# define IEM_MC_MEM_FLAT_MAP_U128_RO(a_pu128Mem, a_bUnmapInfo, a_GCPtrMem) \
2175 (a_pu128Mem) = iemMemFlatMapDataU128RoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
2176#endif
2177
2178
2179/* misc */
2180
2181/**
2182 * Maps guest memory for 80-bit float writeonly direct (or bounce) buffer acccess.
2183 *
2184 * @param[out] a_pr80Mem Where to return the pointer to the mapping.
2185 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
2186 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
2187 * @param[in] a_GCPtrMem The memory address.
2188 * @remarks Will return/long jump on errors.
2189 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
2190 */
2191#ifndef IEM_WITH_SETJMP
2192# define IEM_MC_MEM_MAP_R80_WO(a_pr80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
2193 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pr80Mem), &(a_bUnmapInfo), sizeof(RTFLOAT80U), (a_iSeg), \
2194 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1))
2195#else
2196# define IEM_MC_MEM_MAP_R80_WO(a_pr80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
2197 (a_pr80Mem) = iemMemMapDataR80WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
2198#endif
2199
2200/**
2201 * Maps guest memory for 80-bit float writeonly direct (or bounce) buffer acccess.
2202 *
2203 * @param[out] a_pr80Mem Where to return the pointer to the mapping.
2204 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
2205 * @param[in] a_GCPtrMem The memory address.
2206 * @remarks Will return/long jump on errors.
2207 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
2208 */
2209#ifndef IEM_WITH_SETJMP
2210# define IEM_MC_MEM_FLAT_MAP_R80_WO(a_pr80Mem, a_bUnmapInfo, a_GCPtrMem) \
2211 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pr80Mem), &(a_bUnmapInfo), sizeof(RTFLOAT80U), UINT8_MAX, \
2212 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1))
2213#else
2214# define IEM_MC_MEM_FLAT_MAP_R80_WO(a_pr80Mem, a_bUnmapInfo, a_GCPtrMem) \
2215 (a_pr80Mem) = iemMemFlatMapDataR80WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
2216#endif
2217
2218
2219/**
2220 * Maps guest memory for 80-bit BCD writeonly direct (or bounce) buffer acccess.
2221 *
2222 * @param[out] a_pd80Mem Where to return the pointer to the mapping.
2223 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
2224 * @param[in] a_iSeg The segment register to access via. No UINT8_MAX!
2225 * @param[in] a_GCPtrMem The memory address.
2226 * @remarks Will return/long jump on errors.
2227 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
2228 */
2229#ifndef IEM_WITH_SETJMP
2230# define IEM_MC_MEM_MAP_D80_WO(a_pd80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
2231 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pd80Mem), &(a_bUnmapInfo), sizeof(RTFLOAT80U), (a_iSeg), \
2232 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1))
2233#else
2234# define IEM_MC_MEM_MAP_D80_WO(a_pd80Mem, a_bUnmapInfo, a_iSeg, a_GCPtrMem) \
2235 (a_pd80Mem) = iemMemMapDataD80WoJmp(pVCpu, &(a_bUnmapInfo), (a_iSeg), (a_GCPtrMem))
2236#endif
2237
2238/**
2239 * Maps guest memory for 80-bit BCD writeonly direct (or bounce) buffer acccess.
2240 *
2241 * @param[out] a_pd80Mem Where to return the pointer to the mapping.
2242 * @param[out] a_bUnmapInfo Where to return umapping instructions. uint8_t.
2243 * @param[in] a_GCPtrMem The memory address.
2244 * @remarks Will return/long jump on errors.
2245 * @see IEM_MC_MEM_COMMIT_AND_UNMAP_WO
2246 */
2247#ifndef IEM_WITH_SETJMP
2248# define IEM_MC_MEM_FLAT_MAP_D80_WO(a_pd80Mem, a_bUnmapInfo, a_GCPtrMem) \
2249 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pd80Mem), &(a_bUnmapInfo), sizeof(RTFLOAT80U), UINT8_MAX, \
2250 (a_GCPtrMem), IEM_ACCESS_DATA_W, sizeof(uint64_t) - 1))
2251#else
2252# define IEM_MC_MEM_FLAT_MAP_D80_WO(a_pd80Mem, a_bUnmapInfo, a_GCPtrMem) \
2253 (a_pd80Mem) = iemMemFlatMapDataD80WoJmp(pVCpu, &(a_bUnmapInfo), (a_GCPtrMem))
2254#endif
2255
2256
2257
2258/* commit + unmap */
2259
2260/** Commits the memory and unmaps guest memory previously mapped RW.
2261 * @remarks May return.
2262 * @note Implictly frees the a_bMapInfo variable.
2263 */
2264#ifndef IEM_WITH_SETJMP
2265# define IEM_MC_MEM_COMMIT_AND_UNMAP_RW(a_bMapInfo) IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, a_bMapInfo))
2266#else
2267# define IEM_MC_MEM_COMMIT_AND_UNMAP_RW(a_bMapInfo) iemMemCommitAndUnmapRwJmp(pVCpu, (a_bMapInfo))
2268#endif
2269
2270/** Commits the memory and unmaps guest memory previously mapped W.
2271 * @remarks May return.
2272 * @note Implictly frees the a_bMapInfo variable.
2273 */
2274#ifndef IEM_WITH_SETJMP
2275# define IEM_MC_MEM_COMMIT_AND_UNMAP_WO(a_bMapInfo) IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, a_bMapInfo))
2276#else
2277# define IEM_MC_MEM_COMMIT_AND_UNMAP_WO(a_bMapInfo) iemMemCommitAndUnmapWoJmp(pVCpu, (a_bMapInfo))
2278#endif
2279
2280/** Commits the memory and unmaps guest memory previously mapped R.
2281 * @remarks May return.
2282 * @note Implictly frees the a_bMapInfo variable.
2283 */
2284#ifndef IEM_WITH_SETJMP
2285# define IEM_MC_MEM_COMMIT_AND_UNMAP_RO(a_bMapInfo) IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, a_bMapInfo))
2286#else
2287# define IEM_MC_MEM_COMMIT_AND_UNMAP_RO(a_bMapInfo) iemMemCommitAndUnmapRoJmp(pVCpu, (a_bMapInfo))
2288#endif
2289
2290
2291/** Commits the memory and unmaps the guest memory unless the FPU status word
2292 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
2293 * that would cause FLD not to store.
2294 *
2295 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
2296 * store, while \#P will not.
2297 *
2298 * @remarks May in theory return - for now.
2299 * @note Implictly frees both the a_bMapInfo and a_u16FSW variables.
2300 */
2301#ifndef IEM_WITH_SETJMP
2302# define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE_WO(a_bMapInfo, a_u16FSW) do { \
2303 if ( !(a_u16FSW & X86_FSW_ES) \
2304 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
2305 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
2306 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, a_bMapInfo)); \
2307 else \
2308 iemMemRollbackAndUnmap(pVCpu, (a_pvMem), IEM_ACCESS_DATA_W); \
2309 } while (0)
2310#else
2311# define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE_WO(a_bMapInfo, a_u16FSW) do { \
2312 if ( !(a_u16FSW & X86_FSW_ES) \
2313 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
2314 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
2315 iemMemCommitAndUnmapWoJmp(pVCpu, a_bMapInfo); \
2316 else \
2317 iemMemRollbackAndUnmapWo(pVCpu, a_bMapInfo); \
2318 } while (0)
2319#endif
2320
2321/** Rolls back (conceptually only, assumes no writes) and unmaps the guest memory.
2322 * @note Implictly frees the a_bMapInfo variable. */
2323#ifndef IEM_WITH_SETJMP
2324# define IEM_MC_MEM_ROLLBACK_AND_UNMAP_WO(a_bMapInfo) iemMemRollbackAndUnmap(pVCpu, a_bMapInfo)
2325#else
2326# define IEM_MC_MEM_ROLLBACK_AND_UNMAP_WO(a_bMapInfo) iemMemRollbackAndUnmapWo(pVCpu, a_bMapInfo)
2327#endif
2328
2329
2330
2331/** Calculate efficient address from R/M. */
2332#ifndef IEM_WITH_SETJMP
2333# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
2334 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (a_bRm), (a_cbImmAndRspOffset), &(a_GCPtrEff)))
2335#else
2336# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, a_bRm, a_cbImmAndRspOffset) \
2337 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (a_bRm), (a_cbImmAndRspOffset)))
2338#endif
2339
2340#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
2341#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
2342#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
2343#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
2344#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
2345#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
2346#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
2347
2348
2349/** @def IEM_MC_CALL_CIMPL_HLP_RET
2350 * Helper macro for check that all important IEM_CIMPL_F_XXX bits are set.
2351 */
2352#ifdef VBOX_STRICT
2353#define IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, a_CallExpr) \
2354 do { \
2355 uint8_t const cbInstr = IEM_GET_INSTR_LEN(pVCpu); /* may be flushed */ \
2356 uint16_t const uCsBefore = pVCpu->cpum.GstCtx.cs.Sel; \
2357 uint64_t const uRipBefore = pVCpu->cpum.GstCtx.rip; \
2358 uint32_t const fEflBefore = pVCpu->cpum.GstCtx.eflags.u; \
2359 uint32_t const fExecBefore = pVCpu->iem.s.fExec; \
2360 VBOXSTRICTRC const rcStrictHlp = a_CallExpr; \
2361 if (rcStrictHlp == VINF_SUCCESS) \
2362 { \
2363 AssertMsg( ((a_fFlags) & IEM_CIMPL_F_BRANCH_ANY) \
2364 || ( uRipBefore + cbInstr == pVCpu->cpum.GstCtx.rip \
2365 && uCsBefore == pVCpu->cpum.GstCtx.cs.Sel) \
2366 || ( ((a_fFlags) & IEM_CIMPL_F_REP) \
2367 && uRipBefore == pVCpu->cpum.GstCtx.rip \
2368 && uCsBefore == pVCpu->cpum.GstCtx.cs.Sel), \
2369 ("CS:RIP=%04x:%08RX64 + %x -> %04x:%08RX64, expected %04x:%08RX64\n", uCsBefore, uRipBefore, cbInstr, \
2370 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uCsBefore, uRipBefore + cbInstr)); \
2371 if ((a_fFlags) & IEM_CIMPL_F_RFLAGS) \
2372 { /* No need to check fEflBefore */ Assert(!((a_fFlags) & IEM_CIMPL_F_STATUS_FLAGS)); } \
2373 else if ((a_fFlags) & IEM_CIMPL_F_STATUS_FLAGS) \
2374 AssertMsg( (pVCpu->cpum.GstCtx.eflags.u & ~(X86_EFL_STATUS_BITS | X86_EFL_RF)) \
2375 == (fEflBefore & ~(X86_EFL_STATUS_BITS | X86_EFL_RF)), \
2376 ("EFL=%#RX32 -> %#RX32\n", fEflBefore, pVCpu->cpum.GstCtx.eflags.u)); \
2377 else \
2378 AssertMsg( (pVCpu->cpum.GstCtx.eflags.u & ~(X86_EFL_RF)) \
2379 == (fEflBefore & ~(X86_EFL_RF)), \
2380 ("EFL=%#RX32 -> %#RX32\n", fEflBefore, pVCpu->cpum.GstCtx.eflags.u)); \
2381 if (!((a_fFlags) & IEM_CIMPL_F_MODE)) \
2382 { \
2383 uint32_t fExecRecalc = iemCalcExecFlags(pVCpu) | (pVCpu->iem.s.fExec & IEM_F_USER_OPTS); \
2384 AssertMsg( fExecBefore == fExecRecalc \
2385 /* in case ES, DS or SS was external initially (happens alot with HM): */ \
2386 || ( fExecBefore == (fExecRecalc & ~IEM_F_MODE_X86_FLAT_OR_PRE_386_MASK) \
2387 && (fExecRecalc & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_32BIT), \
2388 ("fExec=%#x -> %#x (diff %#x)\n", fExecBefore, fExecRecalc, fExecBefore ^ fExecRecalc)); \
2389 } \
2390 } \
2391 return rcStrictHlp; \
2392 } while (0)
2393#else
2394# define IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, a_CallExpr) return a_CallExpr
2395#endif
2396
2397/**
2398 * Defers the rest of the instruction emulation to a C implementation routine
2399 * and returns, only taking the standard parameters.
2400 *
2401 * @param a_fFlags IEM_CIMPL_F_XXX.
2402 * @param a_fGstShwFlush Guest shadow register copies needing to be flushed
2403 * in the native recompiler.
2404 * @param a_pfnCImpl The pointer to the C routine.
2405 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
2406 */
2407#define IEM_MC_CALL_CIMPL_0(a_fFlags, a_fGstShwFlush, a_pfnCImpl) \
2408 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu)))
2409
2410/**
2411 * Defers the rest of instruction emulation to a C implementation routine and
2412 * returns, taking one argument in addition to the standard ones.
2413 *
2414 * @param a_fFlags IEM_CIMPL_F_XXX.
2415 * @param a_fGstShwFlush Guest shadow register copies needing to be flushed
2416 * in the native recompiler.
2417 * @param a_pfnCImpl The pointer to the C routine.
2418 * @param a0 The argument.
2419 */
2420#define IEM_MC_CALL_CIMPL_1(a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0) \
2421 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0))
2422
2423/**
2424 * Defers the rest of the instruction emulation to a C implementation routine
2425 * and returns, taking two arguments in addition to the standard ones.
2426 *
2427 * @param a_fFlags IEM_CIMPL_F_XXX.
2428 * @param a_fGstShwFlush Guest shadow register copies needing to be flushed
2429 * in the native recompiler.
2430 * @param a_pfnCImpl The pointer to the C routine.
2431 * @param a0 The first extra argument.
2432 * @param a1 The second extra argument.
2433 */
2434#define IEM_MC_CALL_CIMPL_2(a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1) \
2435 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1))
2436
2437/**
2438 * Defers the rest of the instruction emulation to a C implementation routine
2439 * and returns, taking three arguments in addition to the standard ones.
2440 *
2441 * @param a_fFlags IEM_CIMPL_F_XXX.
2442 * @param a_fGstShwFlush Guest shadow register copies needing to be flushed
2443 * in the native recompiler.
2444 * @param a_pfnCImpl The pointer to the C routine.
2445 * @param a0 The first extra argument.
2446 * @param a1 The second extra argument.
2447 * @param a2 The third extra argument.
2448 */
2449#define IEM_MC_CALL_CIMPL_3(a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2) \
2450 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2))
2451
2452/**
2453 * Defers the rest of the instruction emulation to a C implementation routine
2454 * and returns, taking four arguments in addition to the standard ones.
2455 *
2456 * @param a_fFlags IEM_CIMPL_F_XXX.
2457 * @param a_fGstShwFlush Guest shadow register copies needing to be flushed
2458 * in the native recompiler.
2459 * @param a_pfnCImpl The pointer to the C routine.
2460 * @param a0 The first extra argument.
2461 * @param a1 The second extra argument.
2462 * @param a2 The third extra argument.
2463 * @param a3 The fourth extra argument.
2464 */
2465#define IEM_MC_CALL_CIMPL_4(a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3) \
2466 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3))
2467
2468/**
2469 * Defers the rest of the instruction emulation to a C implementation routine
2470 * and returns, taking two arguments in addition to the standard ones.
2471 *
2472 * @param a_fFlags IEM_CIMPL_F_XXX.
2473 * @param a_fGstShwFlush Guest shadow register copies needing to be flushed
2474 * in the native recompiler.
2475 * @param a_pfnCImpl The pointer to the C routine.
2476 * @param a0 The first extra argument.
2477 * @param a1 The second extra argument.
2478 * @param a2 The third extra argument.
2479 * @param a3 The fourth extra argument.
2480 * @param a4 The fifth extra argument.
2481 */
2482#define IEM_MC_CALL_CIMPL_5(a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2, a3, a4) \
2483 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4))
2484
2485/**
2486 * Defers the entire instruction emulation to a C implementation routine and
2487 * returns, only taking the standard parameters.
2488 *
2489 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
2490 *
2491 * @param a_fFlags IEM_CIMPL_F_XXX.
2492 * @param a_fGstShwFlush Guest shadow register copies needing to be flushed
2493 * in the native recompiler.
2494 * @param a_pfnCImpl The pointer to the C routine.
2495 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
2496 */
2497#define IEM_MC_DEFER_TO_CIMPL_0_RET(a_fFlags, a_fGstShwFlush, a_pfnCImpl) \
2498 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu)))
2499
2500/**
2501 * Defers the entire instruction emulation to a C implementation routine and
2502 * returns, taking one argument in addition to the standard ones.
2503 *
2504 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
2505 *
2506 * @param a_fFlags IEM_CIMPL_F_XXX.
2507 * @param a_fGstShwFlush Guest shadow register copies needing to be flushed
2508 * in the native recompiler.
2509 * @param a_pfnCImpl The pointer to the C routine.
2510 * @param a0 The argument.
2511 */
2512#define IEM_MC_DEFER_TO_CIMPL_1_RET(a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0) \
2513 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0))
2514
2515/**
2516 * Defers the entire instruction emulation to a C implementation routine and
2517 * returns, taking two arguments in addition to the standard ones.
2518 *
2519 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
2520 *
2521 * @param a_fFlags IEM_CIMPL_F_XXX.
2522 * @param a_fGstShwFlush Guest shadow register copies needing to be flushed
2523 * in the native recompiler.
2524 * @param a_pfnCImpl The pointer to the C routine.
2525 * @param a0 The first extra argument.
2526 * @param a1 The second extra argument.
2527 */
2528#define IEM_MC_DEFER_TO_CIMPL_2_RET(a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1) \
2529 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1))
2530
2531/**
2532 * Defers the entire instruction emulation to a C implementation routine and
2533 * returns, taking three arguments in addition to the standard ones.
2534 *
2535 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
2536 *
2537 * @param a_fFlags IEM_CIMPL_F_XXX.
2538 * @param a_fGstShwFlush Guest shadow register copies needing to be flushed
2539 * in the native recompiler.
2540 * @param a_pfnCImpl The pointer to the C routine.
2541 * @param a0 The first extra argument.
2542 * @param a1 The second extra argument.
2543 * @param a2 The third extra argument.
2544 */
2545#define IEM_MC_DEFER_TO_CIMPL_3_RET(a_fFlags, a_fGstShwFlush, a_pfnCImpl, a0, a1, a2) \
2546 IEM_MC_CALL_CIMPL_HLP_RET(a_fFlags, (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2))
2547
2548
2549/**
2550 * Calls a FPU assembly implementation taking one visible argument.
2551 *
2552 * @param a_pfnAImpl Pointer to the assembly FPU routine.
2553 * @param a0 The first extra argument.
2554 */
2555#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
2556 do { \
2557 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
2558 } while (0)
2559
2560/**
2561 * Calls a FPU assembly implementation taking two visible arguments.
2562 *
2563 * @param a_pfnAImpl Pointer to the assembly FPU routine.
2564 * @param a0 The first extra argument.
2565 * @param a1 The second extra argument.
2566 */
2567#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
2568 do { \
2569 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
2570 } while (0)
2571
2572/**
2573 * Calls a FPU assembly implementation taking three visible arguments.
2574 *
2575 * @param a_pfnAImpl Pointer to the assembly FPU routine.
2576 * @param a0 The first extra argument.
2577 * @param a1 The second extra argument.
2578 * @param a2 The third extra argument.
2579 */
2580#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
2581 do { \
2582 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
2583 } while (0)
2584
2585#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
2586 do { \
2587 (a_FpuData).FSW = (a_FSW); \
2588 (a_FpuData).r80Result = *(a_pr80Value); \
2589 } while (0)
2590
2591/** Pushes FPU result onto the stack. */
2592#define IEM_MC_PUSH_FPU_RESULT(a_FpuData, a_uFpuOpcode) \
2593 iemFpuPushResult(pVCpu, &a_FpuData, a_uFpuOpcode)
2594/** Pushes FPU result onto the stack and sets the FPUDP. */
2595#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2596 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2597
2598/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
2599#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo, a_uFpuOpcode) \
2600 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo, a_uFpuOpcode)
2601
2602/** Stores FPU result in a stack register. */
2603#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg, a_uFpuOpcode) \
2604 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg, a_uFpuOpcode)
2605/** Stores FPU result in a stack register and pops the stack. */
2606#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg, a_uFpuOpcode) \
2607 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg, a_uFpuOpcode)
2608/** Stores FPU result in a stack register and sets the FPUDP. */
2609#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2610 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2611/** Stores FPU result in a stack register, sets the FPUDP, and pops the
2612 * stack. */
2613#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2614 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2615
2616/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
2617#define IEM_MC_UPDATE_FPU_OPCODE_IP(a_uFpuOpcode) \
2618 iemFpuUpdateOpcodeAndIp(pVCpu, a_uFpuOpcode)
2619/** Free a stack register (for FFREE and FFREEP). */
2620#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
2621 iemFpuStackFree(pVCpu, a_iStReg)
2622/** Increment the FPU stack pointer. */
2623#define IEM_MC_FPU_STACK_INC_TOP() \
2624 iemFpuStackIncTop(pVCpu)
2625/** Decrement the FPU stack pointer. */
2626#define IEM_MC_FPU_STACK_DEC_TOP() \
2627 iemFpuStackDecTop(pVCpu)
2628
2629/** Updates the FSW, FOP, FPUIP, and FPUCS. */
2630#define IEM_MC_UPDATE_FSW(a_u16FSW, a_uFpuOpcode) \
2631 iemFpuUpdateFSW(pVCpu, a_u16FSW, a_uFpuOpcode)
2632/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
2633#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW, a_uFpuOpcode) \
2634 iemFpuUpdateFSW(pVCpu, a_u16FSW, a_uFpuOpcode)
2635/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
2636#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2637 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2638/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
2639#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW, a_uFpuOpcode) \
2640 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW, a_uFpuOpcode)
2641/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
2642 * stack. */
2643#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2644 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2645/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
2646#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW, a_uFpuOpcode) \
2647 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW, a_uFpuOpcode)
2648
2649/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
2650#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst, a_uFpuOpcode) \
2651 iemFpuStackUnderflow(pVCpu, a_iStDst, a_uFpuOpcode)
2652/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
2653 * stack. */
2654#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst, a_uFpuOpcode) \
2655 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst, a_uFpuOpcode)
2656/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
2657 * FPUDS. */
2658#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2659 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2660/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
2661 * FPUDS. Pops stack. */
2662#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2663 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2664/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
2665 * stack twice. */
2666#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP(a_uFpuOpcode) \
2667 iemFpuStackUnderflowThenPopPop(pVCpu, a_uFpuOpcode)
2668/** Raises a FPU stack underflow exception for an instruction pushing a result
2669 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
2670#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW(a_uFpuOpcode) \
2671 iemFpuStackPushUnderflow(pVCpu, a_uFpuOpcode)
2672/** Raises a FPU stack underflow exception for an instruction pushing a result
2673 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
2674#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO(a_uFpuOpcode) \
2675 iemFpuStackPushUnderflowTwo(pVCpu, a_uFpuOpcode)
2676
2677/** Raises a FPU stack overflow exception as part of a push attempt. Sets
2678 * FPUIP, FPUCS and FOP. */
2679#define IEM_MC_FPU_STACK_PUSH_OVERFLOW(a_uFpuOpcode) \
2680 iemFpuStackPushOverflow(pVCpu, a_uFpuOpcode)
2681/** Raises a FPU stack overflow exception as part of a push attempt. Sets
2682 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
2683#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff, a_uFpuOpcode) \
2684 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff, a_uFpuOpcode)
2685/** Prepares for using the FPU state.
2686 * Ensures that we can use the host FPU in the current context (RC+R0.
2687 * Ensures the guest FPU state in the CPUMCTX is up to date. */
2688#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
2689/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
2690#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
2691/** Actualizes the guest FPU state so it can be accessed and modified. */
2692#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
2693
2694/** Stores SSE SIMD result updating MXCSR. */
2695#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
2696 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
2697/** Updates MXCSR. */
2698#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
2699 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
2700
2701/** Prepares for using the SSE state.
2702 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
2703 * Ensures the guest SSE state in the CPUMCTX is up to date. */
2704#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
2705/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
2706#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
2707/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
2708#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
2709
2710/** Prepares for using the AVX state.
2711 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
2712 * Ensures the guest AVX state in the CPUMCTX is up to date.
2713 * @note This will include the AVX512 state too when support for it is added
2714 * due to the zero extending feature of VEX instruction. */
2715#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
2716/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
2717#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
2718/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
2719#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
2720
2721/**
2722 * Calls a MMX assembly implementation taking two visible arguments.
2723 *
2724 * @param a_pfnAImpl Pointer to the assembly MMX routine.
2725 * @param a0 The first extra argument.
2726 * @param a1 The second extra argument.
2727 */
2728#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
2729 do { \
2730 IEM_MC_PREPARE_FPU_USAGE(); \
2731 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
2732 } while (0)
2733
2734/**
2735 * Calls a MMX assembly implementation taking three visible arguments.
2736 *
2737 * @param a_pfnAImpl Pointer to the assembly MMX routine.
2738 * @param a0 The first extra argument.
2739 * @param a1 The second extra argument.
2740 * @param a2 The third extra argument.
2741 */
2742#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
2743 do { \
2744 IEM_MC_PREPARE_FPU_USAGE(); \
2745 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
2746 } while (0)
2747
2748
2749/**
2750 * Calls a SSE assembly implementation taking two visible arguments.
2751 *
2752 * @param a_pfnAImpl Pointer to the assembly SSE routine.
2753 * @param a0 The first extra argument.
2754 * @param a1 The second extra argument.
2755 */
2756#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
2757 do { \
2758 IEM_MC_PREPARE_SSE_USAGE(); \
2759 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
2760 } while (0)
2761
2762/**
2763 * Calls a SSE assembly implementation taking three visible arguments.
2764 *
2765 * @param a_pfnAImpl Pointer to the assembly SSE routine.
2766 * @param a0 The first extra argument.
2767 * @param a1 The second extra argument.
2768 * @param a2 The third extra argument.
2769 */
2770#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
2771 do { \
2772 IEM_MC_PREPARE_SSE_USAGE(); \
2773 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
2774 } while (0)
2775
2776
2777/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
2778 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ...
2779 * @note IEMAllInstPython.py duplicates the expansion. */
2780#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
2781 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
2782
2783/**
2784 * Calls a AVX assembly implementation taking two visible arguments.
2785 *
2786 * There is one implicit zero'th argument, a pointer to the extended state.
2787 *
2788 * @param a_pfnAImpl Pointer to the assembly AVX routine.
2789 * @param a1 The first extra argument.
2790 * @param a2 The second extra argument.
2791 */
2792#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
2793 do { \
2794 IEM_MC_PREPARE_AVX_USAGE(); \
2795 a_pfnAImpl(pXState, (a1), (a2)); \
2796 } while (0)
2797
2798/**
2799 * Calls a AVX assembly implementation taking three visible arguments.
2800 *
2801 * There is one implicit zero'th argument, a pointer to the extended state.
2802 *
2803 * @param a_pfnAImpl Pointer to the assembly AVX routine.
2804 * @param a1 The first extra argument.
2805 * @param a2 The second extra argument.
2806 * @param a3 The third extra argument.
2807 */
2808#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
2809 do { \
2810 IEM_MC_PREPARE_AVX_USAGE(); \
2811 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
2812 } while (0)
2813
2814/** @note Not for IOPL or IF testing. */
2815#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
2816/** @note Not for IOPL or IF testing. */
2817#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
2818/** @note Not for IOPL or IF testing. */
2819#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
2820/** @note Not for IOPL or IF testing. */
2821#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
2822/** @note Not for IOPL or IF testing. */
2823#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
2824 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
2825 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
2826/** @note Not for IOPL or IF testing. */
2827#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
2828 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
2829 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
2830/** @note Not for IOPL or IF testing. */
2831#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
2832 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
2833 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
2834 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
2835/** @note Not for IOPL or IF testing. */
2836#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
2837 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
2838 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
2839 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
2840#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
2841#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
2842#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
2843/** @note Not for IOPL or IF testing. */
2844#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
2845 if ( pVCpu->cpum.GstCtx.cx != 0 \
2846 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2847/** @note Not for IOPL or IF testing. */
2848#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
2849 if ( pVCpu->cpum.GstCtx.ecx != 0 \
2850 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2851/** @note Not for IOPL or IF testing. */
2852#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
2853 if ( pVCpu->cpum.GstCtx.rcx != 0 \
2854 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2855/** @note Not for IOPL or IF testing. */
2856#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
2857 if ( pVCpu->cpum.GstCtx.cx != 0 \
2858 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2859/** @note Not for IOPL or IF testing. */
2860#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
2861 if ( pVCpu->cpum.GstCtx.ecx != 0 \
2862 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2863/** @note Not for IOPL or IF testing. */
2864#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
2865 if ( pVCpu->cpum.GstCtx.rcx != 0 \
2866 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
2867#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
2868#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
2869
2870#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
2871 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80; } while (0)
2872#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
2873 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
2874#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
2875 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
2876#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
2877 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
2878#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
2879 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
2880#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
2881 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
2882#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
2883 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
2884#define IEM_MC_IF_FCW_IM() \
2885 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
2886#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
2887 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
2888 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
2889
2890#define IEM_MC_ELSE() } else {
2891#define IEM_MC_ENDIF() } do {} while (0)
2892
2893
2894/** Recompiler debugging: Flush guest register shadow copies. */
2895#define IEM_MC_HINT_FLUSH_GUEST_SHADOW(g_fGstShwFlush) ((void)0)
2896
2897/** @} */
2898
2899#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
2900
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