VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 95487

Last change on this file since 95487 was 95487, checked in by vboxsync, 2 years ago

VMM/IEM: vpshufhw, vpshuflw and vpshufd, brushing up pshufw, pshufhw, pshuflw and pshufd. bugref:9898
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1/* $Id: IEMMc.h 95487 2022-07-03 14:02:39Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
19#define VMM_INCLUDED_SRC_include_IEMMc_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24
25/** @name "Microcode" macros.
26 *
27 * The idea is that we should be able to use the same code to interpret
28 * instructions as well as recompiler instructions. Thus this obfuscation.
29 *
30 * @{
31 */
32#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
33#define IEM_MC_END() }
34#define IEM_MC_PAUSE() do {} while (0)
35#define IEM_MC_CONTINUE() do {} while (0)
36
37/** Internal macro. */
38#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
39 do \
40 { \
41 VBOXSTRICTRC rcStrict2 = a_Expr; \
42 if (rcStrict2 != VINF_SUCCESS) \
43 return rcStrict2; \
44 } while (0)
45
46
47#define IEM_MC_ADVANCE_RIP() iemRegUpdateRipAndClearRF(pVCpu)
48#define IEM_MC_REL_JMP_S8(a_i8) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS8(pVCpu, a_i8))
49#define IEM_MC_REL_JMP_S16(a_i16) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS16(pVCpu, a_i16))
50#define IEM_MC_REL_JMP_S32(a_i32) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS32(pVCpu, a_i32))
51#define IEM_MC_SET_RIP_U16(a_u16NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u16NewIP)))
52#define IEM_MC_SET_RIP_U32(a_u32NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u32NewIP)))
53#define IEM_MC_SET_RIP_U64(a_u64NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u64NewIP)))
54#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
55#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
56 do { \
57 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
58 return iemRaiseDeviceNotAvailable(pVCpu); \
59 } while (0)
60#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
61 do { \
62 if ((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)) \
63 return iemRaiseDeviceNotAvailable(pVCpu); \
64 } while (0)
65#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
66 do { \
67 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
68 return iemRaiseMathFault(pVCpu); \
69 } while (0)
70#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
71 do { \
72 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
73 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
74 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx2) \
75 return iemRaiseUndefinedOpcode(pVCpu); \
76 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
77 return iemRaiseDeviceNotAvailable(pVCpu); \
78 } while (0)
79#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
80 do { \
81 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
82 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
83 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) \
84 return iemRaiseUndefinedOpcode(pVCpu); \
85 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
86 return iemRaiseDeviceNotAvailable(pVCpu); \
87 } while (0)
88#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
89 do { \
90 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
91 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
92 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse41) \
93 return iemRaiseUndefinedOpcode(pVCpu); \
94 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
95 return iemRaiseDeviceNotAvailable(pVCpu); \
96 } while (0)
97#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
98 do { \
99 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
100 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
101 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42) \
102 return iemRaiseUndefinedOpcode(pVCpu); \
103 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
104 return iemRaiseDeviceNotAvailable(pVCpu); \
105 } while (0)
106#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
107 do { \
108 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
109 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
110 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse3) \
111 return iemRaiseUndefinedOpcode(pVCpu); \
112 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
113 return iemRaiseDeviceNotAvailable(pVCpu); \
114 } while (0)
115#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
116 do { \
117 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
118 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
119 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) \
120 return iemRaiseUndefinedOpcode(pVCpu); \
121 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
122 return iemRaiseDeviceNotAvailable(pVCpu); \
123 } while (0)
124#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
125 do { \
126 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
127 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
128 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) \
129 return iemRaiseUndefinedOpcode(pVCpu); \
130 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
131 return iemRaiseDeviceNotAvailable(pVCpu); \
132 } while (0)
133#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
134 do { \
135 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
136 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMmx) \
137 return iemRaiseUndefinedOpcode(pVCpu); \
138 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
139 return iemRaiseDeviceNotAvailable(pVCpu); \
140 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
141 return iemRaiseMathFault(pVCpu); \
142 } while (0)
143#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(a_fSupported) \
144 do { \
145 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
146 || !(a_fSupported)) \
147 return iemRaiseUndefinedOpcode(pVCpu); \
148 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
149 return iemRaiseDeviceNotAvailable(pVCpu); \
150 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
151 return iemRaiseMathFault(pVCpu); \
152 } while (0)
153#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() \
154 do { \
155 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
156 || ( !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse \
157 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAmdMmxExts) ) \
158 return iemRaiseUndefinedOpcode(pVCpu); \
159 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
160 return iemRaiseDeviceNotAvailable(pVCpu); \
161 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
162 return iemRaiseMathFault(pVCpu); \
163 } while (0)
164#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
165 do { \
166 if (pVCpu->iem.s.uCpl != 0) \
167 return iemRaiseGeneralProtectionFault0(pVCpu); \
168 } while (0)
169#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
170 do { \
171 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
172 else return iemRaiseGeneralProtectionFault0(pVCpu); \
173 } while (0)
174#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
175 do { \
176 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
177 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase \
178 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
179 return iemRaiseUndefinedOpcode(pVCpu); \
180 } while (0)
181#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
182 do { \
183 if (!IEM_IS_CANONICAL(a_u64Addr)) \
184 return iemRaiseGeneralProtectionFault0(pVCpu); \
185 } while (0)
186
187
188#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
189#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
190#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
191#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
192#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
193#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
194#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
195 uint32_t a_Name; \
196 uint32_t *a_pName = &a_Name
197#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
198 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
199
200#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
201#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
202
203#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
204#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
205#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
206#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
207#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
208#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
209#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
210#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
211#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
212#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
213#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
214#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
215#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
216#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
217#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
218#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
219#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
220#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
221 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
222 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
223 } while (0)
224#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
225 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
226 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
227 } while (0)
228#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
229 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
230 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
231 } while (0)
232/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
233#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
234 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
235 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
236 } while (0)
237#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
238 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
239 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
240 } while (0)
241/** @note Not for IOPL or IF testing or modification. */
242#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
243#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
244#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
245#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
246
247#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
248#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
249#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
250#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
251#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
252#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
253#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
254#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
255#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
256#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
257/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
258#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
259 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
260 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
261 } while (0)
262#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
263 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
264 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
265 } while (0)
266#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
267 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
268
269
270#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
271#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
272/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
273 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
274#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
275#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
276/** @note Not for IOPL or IF testing or modification. */
277#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.u
278
279#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
280#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
281#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
282 do { \
283 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
284 *pu32Reg += (a_u32Value); \
285 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
286 } while (0)
287#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
288
289#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
290#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
291#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
292 do { \
293 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
294 *pu32Reg -= (a_u32Value); \
295 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
296 } while (0)
297#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
298#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
299
300#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
301#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
302#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
303#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
304#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
305#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
306#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
307
308#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
309#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
310#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
311#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
312
313#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
314#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
315#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
316
317#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
318#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
319#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
320
321#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
322#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
323#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
324
325#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
326#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
327#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
328
329#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
330
331#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
332
333#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
334#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
335#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
336 do { \
337 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
338 *pu32Reg &= (a_u32Value); \
339 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
340 } while (0)
341#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
342
343#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
344#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
345#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
346 do { \
347 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
348 *pu32Reg |= (a_u32Value); \
349 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
350 } while (0)
351#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
352
353
354/** @note Not for IOPL or IF modification. */
355#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
356/** @note Not for IOPL or IF modification. */
357#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
358/** @note Not for IOPL or IF modification. */
359#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
360
361#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
362
363/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
364#define IEM_MC_FPU_TO_MMX_MODE() do { \
365 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
366 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
367 } while (0)
368
369/** Switches the FPU state from MMX mode (FTW=0xffff). */
370#define IEM_MC_FPU_FROM_MMX_MODE() do { \
371 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
372 } while (0)
373
374#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
375 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
376#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
377 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
378#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
379 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
380 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
381 } while (0)
382#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
383 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
384 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
385 } while (0)
386#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
387 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
388#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
389 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
390#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
391 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
392#define IEM_MC_MODIFIED_MREG(a_iMReg) \
393 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
394#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
395 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
396
397#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
398 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
399 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
400 } while (0)
401#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) \
402 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; } while (0)
403#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) \
404 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0]; } while (0)
405#define IEM_MC_FETCH_XREG_HI_U64(a_u64Value, a_iXReg) \
406 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; } while (0)
407#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
408 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
409 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
410 } while (0)
411#define IEM_MC_STORE_XREG_U64(a_iXReg, a_u64Value) \
412 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); } while (0)
413#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
414 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
415 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
416 } while (0)
417#define IEM_MC_STORE_XREG_U32(a_iXReg, a_u32Value) \
418 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = (a_u32Value); } while (0)
419#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
420 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
421 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
422 } while (0)
423#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
424 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
425#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
426 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
427#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
428 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
429#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
430 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
431#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
432 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
433 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
434 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
435 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
436 } while (0)
437
438#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
439 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
440 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
441 } while (0)
442#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
443 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
444 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
445 } while (0)
446#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
447 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
448 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
449 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
450 } while (0)
451#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
452 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
453 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
454 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
455 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
456 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
457 } while (0)
458
459#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
460#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
461 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
462 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
463 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
464 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
465 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
466 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
467 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
468 } while (0)
469#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
470 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
471 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
472 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
473 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
474 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
475 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
476 } while (0)
477#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
478 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
479 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
480 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
481 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
482 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
483 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
484 } while (0)
485#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
486 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
487 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
488 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
489 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
490 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
491 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
492 } while (0)
493
494#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
495 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
496#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
497 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
498#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
499 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
500#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
501 do { uintptr_t const iYRegTmp = (a_iYReg); \
502 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
503 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
504 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
505 } while (0)
506
507#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
508 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
509 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
510 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
511 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
512 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
513 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
514 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
515 } while (0)
516#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
517 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
518 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
519 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
520 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
521 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
522 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
523 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
524 } while (0)
525#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
526 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
527 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
528 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
529 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
530 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
531 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
532 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
533 } while (0)
534
535#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
536 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
537 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
538 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
539 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
540 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
541 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
542 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
543 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
544 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
545 } while (0)
546#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
547 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
548 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
549 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
550 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
551 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
552 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
553 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
554 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
555 } while (0)
556#define IEM_MC_MERGE_YREG_U64HI_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
557 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
558 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
559 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
560 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
561 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
562 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
563 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
564 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
565 } while (0)
566#define IEM_MC_MERGE_YREG_U64LOCAL_U64_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
567 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
568 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
569 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
570 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
571 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
572 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
573 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
574 } while (0)
575
576#ifndef IEM_WITH_SETJMP
577# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
578 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
579# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
580 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
581# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
582 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
583#else
584# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
585 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
586# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
587 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
588# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
589 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
590#endif
591
592#ifndef IEM_WITH_SETJMP
593# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
594 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
595# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
596 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
597# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
598 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
599#else
600# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
601 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
602# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
603 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
604# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
605 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
606#endif
607
608#ifndef IEM_WITH_SETJMP
609# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
610 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
611# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
612 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
613# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
614 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
615#else
616# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
617 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
618# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
619 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
620# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
621 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
622#endif
623
624#ifdef SOME_UNUSED_FUNCTION
625# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
626 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
627#endif
628
629#ifndef IEM_WITH_SETJMP
630# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
631 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
632# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
633 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
634# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
635 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
636# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
637 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
638#else
639# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
640 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
641# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
642 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
643# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
644 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
645# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
646 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
647#endif
648
649#ifndef IEM_WITH_SETJMP
650# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
651 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u32, (a_iSeg), (a_GCPtrMem)))
652# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
653 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).au64[0], (a_iSeg), (a_GCPtrMem)))
654# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
655 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
656# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
657 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
658#else
659# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
660 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
661# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
662 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
663# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
664 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
665# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
666 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
667#endif
668
669#ifndef IEM_WITH_SETJMP
670# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
671 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
672# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
673 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
674# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
675 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
676#else
677# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
678 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
679# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
680 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
681# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
682 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
683#endif
684
685#ifndef IEM_WITH_SETJMP
686# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
687 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
688# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
689 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
690# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
691 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
692#else
693# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
694 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
695# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
696 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
697# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
698 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
699#endif
700
701
702
703#ifndef IEM_WITH_SETJMP
704# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
705 do { \
706 uint8_t u8Tmp; \
707 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
708 (a_u16Dst) = u8Tmp; \
709 } while (0)
710# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
711 do { \
712 uint8_t u8Tmp; \
713 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
714 (a_u32Dst) = u8Tmp; \
715 } while (0)
716# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
717 do { \
718 uint8_t u8Tmp; \
719 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
720 (a_u64Dst) = u8Tmp; \
721 } while (0)
722# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
723 do { \
724 uint16_t u16Tmp; \
725 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
726 (a_u32Dst) = u16Tmp; \
727 } while (0)
728# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
729 do { \
730 uint16_t u16Tmp; \
731 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
732 (a_u64Dst) = u16Tmp; \
733 } while (0)
734# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
735 do { \
736 uint32_t u32Tmp; \
737 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
738 (a_u64Dst) = u32Tmp; \
739 } while (0)
740#else /* IEM_WITH_SETJMP */
741# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
742 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
743# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
744 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
745# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
746 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
747# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
748 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
749# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
750 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
751# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
752 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
753#endif /* IEM_WITH_SETJMP */
754
755#ifndef IEM_WITH_SETJMP
756# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
757 do { \
758 uint8_t u8Tmp; \
759 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
760 (a_u16Dst) = (int8_t)u8Tmp; \
761 } while (0)
762# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
763 do { \
764 uint8_t u8Tmp; \
765 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
766 (a_u32Dst) = (int8_t)u8Tmp; \
767 } while (0)
768# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
769 do { \
770 uint8_t u8Tmp; \
771 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
772 (a_u64Dst) = (int8_t)u8Tmp; \
773 } while (0)
774# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
775 do { \
776 uint16_t u16Tmp; \
777 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
778 (a_u32Dst) = (int16_t)u16Tmp; \
779 } while (0)
780# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
781 do { \
782 uint16_t u16Tmp; \
783 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
784 (a_u64Dst) = (int16_t)u16Tmp; \
785 } while (0)
786# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
787 do { \
788 uint32_t u32Tmp; \
789 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
790 (a_u64Dst) = (int32_t)u32Tmp; \
791 } while (0)
792#else /* IEM_WITH_SETJMP */
793# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
794 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
795# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
796 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
797# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
798 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
799# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
800 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
801# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
802 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
803# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
804 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
805#endif /* IEM_WITH_SETJMP */
806
807#ifndef IEM_WITH_SETJMP
808# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
809 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
810# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
811 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
812# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
813 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
814# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
815 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
816#else
817# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
818 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
819# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
820 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
821# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
822 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
823# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
824 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
825#endif
826
827#ifndef IEM_WITH_SETJMP
828# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
829 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
830# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
831 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
832# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
833 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
834# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
835 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
836#else
837# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
838 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
839# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
840 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
841# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
842 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
843# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
844 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
845#endif
846
847#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
848#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
849#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
850#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
851#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
852#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
853#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
854 do { \
855 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
856 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
857 } while (0)
858#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
859 do { \
860 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
861 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
862 } while (0)
863
864#ifndef IEM_WITH_SETJMP
865# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
866 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
867# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
868 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
869#else
870# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
871 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
872# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
873 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
874#endif
875
876#ifndef IEM_WITH_SETJMP
877# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
878 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
879# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
880 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
881#else
882# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
883 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
884# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
885 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
886#endif
887
888
889#define IEM_MC_PUSH_U16(a_u16Value) \
890 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
891#define IEM_MC_PUSH_U32(a_u32Value) \
892 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
893#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
894 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
895#define IEM_MC_PUSH_U64(a_u64Value) \
896 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
897
898#define IEM_MC_POP_U16(a_pu16Value) \
899 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
900#define IEM_MC_POP_U32(a_pu32Value) \
901 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
902#define IEM_MC_POP_U64(a_pu64Value) \
903 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
904
905/** Maps guest memory for direct or bounce buffered access.
906 * The purpose is to pass it to an operand implementation, thus the a_iArg.
907 * @remarks May return.
908 */
909#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
910 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
911 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
912
913/** Maps guest memory for direct or bounce buffered access.
914 * The purpose is to pass it to an operand implementation, thus the a_iArg.
915 * @remarks May return.
916 */
917#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
918 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
919 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
920
921/** Commits the memory and unmaps the guest memory.
922 * @remarks May return.
923 */
924#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
925 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
926
927/** Commits the memory and unmaps the guest memory unless the FPU status word
928 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
929 * that would cause FLD not to store.
930 *
931 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
932 * store, while \#P will not.
933 *
934 * @remarks May in theory return - for now.
935 */
936#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
937 do { \
938 if ( !(a_u16FSW & X86_FSW_ES) \
939 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
940 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
941 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
942 } while (0)
943
944/** Calculate efficient address from R/M. */
945#ifndef IEM_WITH_SETJMP
946# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
947 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
948#else
949# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
950 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
951#endif
952
953#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
954#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
955#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
956#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
957#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
958#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
959#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
960
961/**
962 * Defers the rest of the instruction emulation to a C implementation routine
963 * and returns, only taking the standard parameters.
964 *
965 * @param a_pfnCImpl The pointer to the C routine.
966 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
967 */
968#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
969
970/**
971 * Defers the rest of instruction emulation to a C implementation routine and
972 * returns, taking one argument in addition to the standard ones.
973 *
974 * @param a_pfnCImpl The pointer to the C routine.
975 * @param a0 The argument.
976 */
977#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
978
979/**
980 * Defers the rest of the instruction emulation to a C implementation routine
981 * and returns, taking two arguments in addition to the standard ones.
982 *
983 * @param a_pfnCImpl The pointer to the C routine.
984 * @param a0 The first extra argument.
985 * @param a1 The second extra argument.
986 */
987#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
988
989/**
990 * Defers the rest of the instruction emulation to a C implementation routine
991 * and returns, taking three arguments in addition to the standard ones.
992 *
993 * @param a_pfnCImpl The pointer to the C routine.
994 * @param a0 The first extra argument.
995 * @param a1 The second extra argument.
996 * @param a2 The third extra argument.
997 */
998#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
999
1000/**
1001 * Defers the rest of the instruction emulation to a C implementation routine
1002 * and returns, taking four arguments in addition to the standard ones.
1003 *
1004 * @param a_pfnCImpl The pointer to the C routine.
1005 * @param a0 The first extra argument.
1006 * @param a1 The second extra argument.
1007 * @param a2 The third extra argument.
1008 * @param a3 The fourth extra argument.
1009 */
1010#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1011
1012/**
1013 * Defers the rest of the instruction emulation to a C implementation routine
1014 * and returns, taking two arguments in addition to the standard ones.
1015 *
1016 * @param a_pfnCImpl The pointer to the C routine.
1017 * @param a0 The first extra argument.
1018 * @param a1 The second extra argument.
1019 * @param a2 The third extra argument.
1020 * @param a3 The fourth extra argument.
1021 * @param a4 The fifth extra argument.
1022 */
1023#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1024
1025/**
1026 * Defers the entire instruction emulation to a C implementation routine and
1027 * returns, only taking the standard parameters.
1028 *
1029 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1030 *
1031 * @param a_pfnCImpl The pointer to the C routine.
1032 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1033 */
1034#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1035
1036/**
1037 * Defers the entire instruction emulation to a C implementation routine and
1038 * returns, taking one argument in addition to the standard ones.
1039 *
1040 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1041 *
1042 * @param a_pfnCImpl The pointer to the C routine.
1043 * @param a0 The argument.
1044 */
1045#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1046
1047/**
1048 * Defers the entire instruction emulation to a C implementation routine and
1049 * returns, taking two arguments in addition to the standard ones.
1050 *
1051 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1052 *
1053 * @param a_pfnCImpl The pointer to the C routine.
1054 * @param a0 The first extra argument.
1055 * @param a1 The second extra argument.
1056 */
1057#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1058
1059/**
1060 * Defers the entire instruction emulation to a C implementation routine and
1061 * returns, taking three arguments in addition to the standard ones.
1062 *
1063 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1064 *
1065 * @param a_pfnCImpl The pointer to the C routine.
1066 * @param a0 The first extra argument.
1067 * @param a1 The second extra argument.
1068 * @param a2 The third extra argument.
1069 */
1070#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1071
1072/**
1073 * Calls a FPU assembly implementation taking one visible argument.
1074 *
1075 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1076 * @param a0 The first extra argument.
1077 */
1078#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1079 do { \
1080 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1081 } while (0)
1082
1083/**
1084 * Calls a FPU assembly implementation taking two visible arguments.
1085 *
1086 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1087 * @param a0 The first extra argument.
1088 * @param a1 The second extra argument.
1089 */
1090#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1091 do { \
1092 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1093 } while (0)
1094
1095/**
1096 * Calls a FPU assembly implementation taking three visible arguments.
1097 *
1098 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1099 * @param a0 The first extra argument.
1100 * @param a1 The second extra argument.
1101 * @param a2 The third extra argument.
1102 */
1103#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1104 do { \
1105 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1106 } while (0)
1107
1108#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1109 do { \
1110 (a_FpuData).FSW = (a_FSW); \
1111 (a_FpuData).r80Result = *(a_pr80Value); \
1112 } while (0)
1113
1114/** Pushes FPU result onto the stack. */
1115#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1116 iemFpuPushResult(pVCpu, &a_FpuData)
1117/** Pushes FPU result onto the stack and sets the FPUDP. */
1118#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1119 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1120
1121/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1122#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1123 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1124
1125/** Stores FPU result in a stack register. */
1126#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1127 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1128/** Stores FPU result in a stack register and pops the stack. */
1129#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1130 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1131/** Stores FPU result in a stack register and sets the FPUDP. */
1132#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1133 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1134/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1135 * stack. */
1136#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1137 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1138
1139/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1140#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1141 iemFpuUpdateOpcodeAndIp(pVCpu)
1142/** Free a stack register (for FFREE and FFREEP). */
1143#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1144 iemFpuStackFree(pVCpu, a_iStReg)
1145/** Increment the FPU stack pointer. */
1146#define IEM_MC_FPU_STACK_INC_TOP() \
1147 iemFpuStackIncTop(pVCpu)
1148/** Decrement the FPU stack pointer. */
1149#define IEM_MC_FPU_STACK_DEC_TOP() \
1150 iemFpuStackDecTop(pVCpu)
1151
1152/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1153#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1154 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1155/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1156#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1157 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1158/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1159#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1160 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1161/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1162#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1163 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1164/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1165 * stack. */
1166#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1167 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1168/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1169#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1170 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1171
1172/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1173#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1174 iemFpuStackUnderflow(pVCpu, a_iStDst)
1175/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1176 * stack. */
1177#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1178 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1179/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1180 * FPUDS. */
1181#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1182 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1183/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1184 * FPUDS. Pops stack. */
1185#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1186 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1187/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1188 * stack twice. */
1189#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1190 iemFpuStackUnderflowThenPopPop(pVCpu)
1191/** Raises a FPU stack underflow exception for an instruction pushing a result
1192 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1193#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1194 iemFpuStackPushUnderflow(pVCpu)
1195/** Raises a FPU stack underflow exception for an instruction pushing a result
1196 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1197#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1198 iemFpuStackPushUnderflowTwo(pVCpu)
1199
1200/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1201 * FPUIP, FPUCS and FOP. */
1202#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1203 iemFpuStackPushOverflow(pVCpu)
1204/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1205 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1206#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1207 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1208/** Prepares for using the FPU state.
1209 * Ensures that we can use the host FPU in the current context (RC+R0.
1210 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1211#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1212/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1213#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1214/** Actualizes the guest FPU state so it can be accessed and modified. */
1215#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1216
1217/** Prepares for using the SSE state.
1218 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1219 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1220#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1221/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1222#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1223/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1224#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1225
1226/** Prepares for using the AVX state.
1227 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1228 * Ensures the guest AVX state in the CPUMCTX is up to date.
1229 * @note This will include the AVX512 state too when support for it is added
1230 * due to the zero extending feature of VEX instruction. */
1231#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1232/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1233#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1234/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1235#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1236
1237/**
1238 * Calls a MMX assembly implementation taking two visible arguments.
1239 *
1240 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1241 * @param a0 The first extra argument.
1242 * @param a1 The second extra argument.
1243 */
1244#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1245 do { \
1246 IEM_MC_PREPARE_FPU_USAGE(); \
1247 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1248 } while (0)
1249
1250/**
1251 * Calls a MMX assembly implementation taking three visible arguments.
1252 *
1253 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1254 * @param a0 The first extra argument.
1255 * @param a1 The second extra argument.
1256 * @param a2 The third extra argument.
1257 */
1258#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1259 do { \
1260 IEM_MC_PREPARE_FPU_USAGE(); \
1261 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1262 } while (0)
1263
1264
1265/**
1266 * Calls a SSE assembly implementation taking two visible arguments.
1267 *
1268 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1269 * @param a0 The first extra argument.
1270 * @param a1 The second extra argument.
1271 */
1272#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1273 do { \
1274 IEM_MC_PREPARE_SSE_USAGE(); \
1275 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1276 } while (0)
1277
1278/**
1279 * Calls a SSE assembly implementation taking three visible arguments.
1280 *
1281 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1282 * @param a0 The first extra argument.
1283 * @param a1 The second extra argument.
1284 * @param a2 The third extra argument.
1285 */
1286#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1287 do { \
1288 IEM_MC_PREPARE_SSE_USAGE(); \
1289 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1290 } while (0)
1291
1292
1293/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1294 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1295#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1296 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1297
1298/**
1299 * Calls a AVX assembly implementation taking two visible arguments.
1300 *
1301 * There is one implicit zero'th argument, a pointer to the extended state.
1302 *
1303 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1304 * @param a1 The first extra argument.
1305 * @param a2 The second extra argument.
1306 */
1307#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1308 do { \
1309 IEM_MC_PREPARE_AVX_USAGE(); \
1310 a_pfnAImpl(pXState, (a1), (a2)); \
1311 } while (0)
1312
1313/**
1314 * Calls a AVX assembly implementation taking three visible arguments.
1315 *
1316 * There is one implicit zero'th argument, a pointer to the extended state.
1317 *
1318 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1319 * @param a1 The first extra argument.
1320 * @param a2 The second extra argument.
1321 * @param a3 The third extra argument.
1322 */
1323#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1324 do { \
1325 IEM_MC_PREPARE_AVX_USAGE(); \
1326 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1327 } while (0)
1328
1329/** @note Not for IOPL or IF testing. */
1330#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1331/** @note Not for IOPL or IF testing. */
1332#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1333/** @note Not for IOPL or IF testing. */
1334#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1335/** @note Not for IOPL or IF testing. */
1336#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1337/** @note Not for IOPL or IF testing. */
1338#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1339 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1340 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1341/** @note Not for IOPL or IF testing. */
1342#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1343 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1344 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1345/** @note Not for IOPL or IF testing. */
1346#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1347 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1348 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1349 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1350/** @note Not for IOPL or IF testing. */
1351#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1352 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1353 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1354 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1355#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1356#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1357#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1358/** @note Not for IOPL or IF testing. */
1359#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1360 if ( pVCpu->cpum.GstCtx.cx != 0 \
1361 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1362/** @note Not for IOPL or IF testing. */
1363#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1364 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1365 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1366/** @note Not for IOPL or IF testing. */
1367#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1368 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1369 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1370/** @note Not for IOPL or IF testing. */
1371#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1372 if ( pVCpu->cpum.GstCtx.cx != 0 \
1373 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1374/** @note Not for IOPL or IF testing. */
1375#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1376 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1377 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1378/** @note Not for IOPL or IF testing. */
1379#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1380 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1381 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1382#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1383#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1384
1385#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1386 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1387#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1388 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1389#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1390 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1391#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1392 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1393#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1394 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1395#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1396 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1397#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1398 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1399#define IEM_MC_IF_FCW_IM() \
1400 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1401
1402#define IEM_MC_ELSE() } else {
1403#define IEM_MC_ENDIF() } do {} while (0)
1404
1405/** @} */
1406
1407#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1408
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