VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 95522

Last change on this file since 95522 was 95499, checked in by vboxsync, 3 years ago

VMM/IEM: [v]pshufhb. bugref:9898
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1/* $Id: IEMMc.h 95499 2022-07-04 12:52:29Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
19#define VMM_INCLUDED_SRC_include_IEMMc_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24
25/** @name "Microcode" macros.
26 *
27 * The idea is that we should be able to use the same code to interpret
28 * instructions as well as recompiler instructions. Thus this obfuscation.
29 *
30 * @{
31 */
32#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
33#define IEM_MC_END() }
34#define IEM_MC_PAUSE() do {} while (0)
35#define IEM_MC_CONTINUE() do {} while (0)
36
37/** Internal macro. */
38#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
39 do \
40 { \
41 VBOXSTRICTRC rcStrict2 = a_Expr; \
42 if (rcStrict2 != VINF_SUCCESS) \
43 return rcStrict2; \
44 } while (0)
45
46
47#define IEM_MC_ADVANCE_RIP() iemRegUpdateRipAndClearRF(pVCpu)
48#define IEM_MC_REL_JMP_S8(a_i8) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS8(pVCpu, a_i8))
49#define IEM_MC_REL_JMP_S16(a_i16) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS16(pVCpu, a_i16))
50#define IEM_MC_REL_JMP_S32(a_i32) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS32(pVCpu, a_i32))
51#define IEM_MC_SET_RIP_U16(a_u16NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u16NewIP)))
52#define IEM_MC_SET_RIP_U32(a_u32NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u32NewIP)))
53#define IEM_MC_SET_RIP_U64(a_u64NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u64NewIP)))
54#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
55#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
56 do { \
57 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
58 return iemRaiseDeviceNotAvailable(pVCpu); \
59 } while (0)
60#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
61 do { \
62 if ((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)) \
63 return iemRaiseDeviceNotAvailable(pVCpu); \
64 } while (0)
65#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
66 do { \
67 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
68 return iemRaiseMathFault(pVCpu); \
69 } while (0)
70#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
71 do { \
72 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
73 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
74 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx2) \
75 return iemRaiseUndefinedOpcode(pVCpu); \
76 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
77 return iemRaiseDeviceNotAvailable(pVCpu); \
78 } while (0)
79#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
80 do { \
81 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
82 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
83 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) \
84 return iemRaiseUndefinedOpcode(pVCpu); \
85 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
86 return iemRaiseDeviceNotAvailable(pVCpu); \
87 } while (0)
88#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
89 do { \
90 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
91 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
92 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42) \
93 return iemRaiseUndefinedOpcode(pVCpu); \
94 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
95 return iemRaiseDeviceNotAvailable(pVCpu); \
96 } while (0)
97#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
98 do { \
99 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
100 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
101 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse41) \
102 return iemRaiseUndefinedOpcode(pVCpu); \
103 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
104 return iemRaiseDeviceNotAvailable(pVCpu); \
105 } while (0)
106#define IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT() \
107 do { \
108 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
109 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
110 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3) \
111 return iemRaiseUndefinedOpcode(pVCpu); \
112 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
113 return iemRaiseDeviceNotAvailable(pVCpu); \
114 } while (0)
115#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
116 do { \
117 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
118 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
119 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse3) \
120 return iemRaiseUndefinedOpcode(pVCpu); \
121 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
122 return iemRaiseDeviceNotAvailable(pVCpu); \
123 } while (0)
124#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
125 do { \
126 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
127 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
128 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) \
129 return iemRaiseUndefinedOpcode(pVCpu); \
130 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
131 return iemRaiseDeviceNotAvailable(pVCpu); \
132 } while (0)
133#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
134 do { \
135 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
136 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
137 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) \
138 return iemRaiseUndefinedOpcode(pVCpu); \
139 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
140 return iemRaiseDeviceNotAvailable(pVCpu); \
141 } while (0)
142#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
143 do { \
144 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
145 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMmx) \
146 return iemRaiseUndefinedOpcode(pVCpu); \
147 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
148 return iemRaiseDeviceNotAvailable(pVCpu); \
149 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
150 return iemRaiseMathFault(pVCpu); \
151 } while (0)
152#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(a_fSupported) \
153 do { \
154 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
155 || !(a_fSupported)) \
156 return iemRaiseUndefinedOpcode(pVCpu); \
157 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
158 return iemRaiseDeviceNotAvailable(pVCpu); \
159 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
160 return iemRaiseMathFault(pVCpu); \
161 } while (0)
162#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() \
163 do { \
164 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
165 || ( !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse \
166 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAmdMmxExts) ) \
167 return iemRaiseUndefinedOpcode(pVCpu); \
168 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
169 return iemRaiseDeviceNotAvailable(pVCpu); \
170 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
171 return iemRaiseMathFault(pVCpu); \
172 } while (0)
173#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
174 do { \
175 if (pVCpu->iem.s.uCpl != 0) \
176 return iemRaiseGeneralProtectionFault0(pVCpu); \
177 } while (0)
178#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
179 do { \
180 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
181 else return iemRaiseGeneralProtectionFault0(pVCpu); \
182 } while (0)
183#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
184 do { \
185 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
186 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase \
187 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
188 return iemRaiseUndefinedOpcode(pVCpu); \
189 } while (0)
190#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
191 do { \
192 if (!IEM_IS_CANONICAL(a_u64Addr)) \
193 return iemRaiseGeneralProtectionFault0(pVCpu); \
194 } while (0)
195
196
197#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
198#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
199#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
200#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
201#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
202#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
203#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
204 uint32_t a_Name; \
205 uint32_t *a_pName = &a_Name
206#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
207 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
208
209#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
210#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
211
212#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
213#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
214#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
215#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
216#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
217#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
218#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
219#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
220#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
221#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
222#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
223#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
224#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
225#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
226#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
227#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
228#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
229#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
230 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
231 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
232 } while (0)
233#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
234 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
235 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
236 } while (0)
237#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
238 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
239 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
240 } while (0)
241/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
242#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
243 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
244 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
245 } while (0)
246#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
247 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
248 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
249 } while (0)
250/** @note Not for IOPL or IF testing or modification. */
251#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
252#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
253#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
254#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
255
256#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
257#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
258#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
259#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
260#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
261#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
262#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
263#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
264#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
265#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
266/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
267#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
268 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
269 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
270 } while (0)
271#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
272 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
273 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
274 } while (0)
275#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
276 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
277
278
279#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
280#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
281/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
282 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
283#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
284#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
285/** @note Not for IOPL or IF testing or modification. */
286#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.u
287
288#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
289#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
290#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
291 do { \
292 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
293 *pu32Reg += (a_u32Value); \
294 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
295 } while (0)
296#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
297
298#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
299#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
300#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
301 do { \
302 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
303 *pu32Reg -= (a_u32Value); \
304 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
305 } while (0)
306#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
307#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
308
309#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
310#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
311#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
312#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
313#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
314#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
315#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
316
317#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
318#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
319#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
320#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
321
322#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
323#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
324#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
325
326#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
327#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
328#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
329
330#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
331#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
332#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
333
334#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
335#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
336#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
337
338#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
339
340#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
341
342#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
343#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
344#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
345 do { \
346 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
347 *pu32Reg &= (a_u32Value); \
348 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
349 } while (0)
350#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
351
352#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
353#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
354#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
355 do { \
356 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
357 *pu32Reg |= (a_u32Value); \
358 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
359 } while (0)
360#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
361
362
363/** @note Not for IOPL or IF modification. */
364#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
365/** @note Not for IOPL or IF modification. */
366#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
367/** @note Not for IOPL or IF modification. */
368#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
369
370#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
371
372/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
373#define IEM_MC_FPU_TO_MMX_MODE() do { \
374 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
375 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
376 } while (0)
377
378/** Switches the FPU state from MMX mode (FTW=0xffff). */
379#define IEM_MC_FPU_FROM_MMX_MODE() do { \
380 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
381 } while (0)
382
383#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
384 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
385#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
386 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
387#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
388 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
389 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
390 } while (0)
391#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
392 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
393 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
394 } while (0)
395#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
396 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
397#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
398 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
399#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
400 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
401#define IEM_MC_MODIFIED_MREG(a_iMReg) \
402 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
403#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
404 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
405
406#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
407 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
408 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
409 } while (0)
410#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) \
411 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; } while (0)
412#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) \
413 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0]; } while (0)
414#define IEM_MC_FETCH_XREG_HI_U64(a_u64Value, a_iXReg) \
415 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; } while (0)
416#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
417 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
418 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
419 } while (0)
420#define IEM_MC_STORE_XREG_U64(a_iXReg, a_u64Value) \
421 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); } while (0)
422#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
423 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
424 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
425 } while (0)
426#define IEM_MC_STORE_XREG_U32(a_iXReg, a_u32Value) \
427 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = (a_u32Value); } while (0)
428#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
429 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
430 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
431 } while (0)
432#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
433 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
434#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
435 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
436#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
437 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
438#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
439 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
440#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
441 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
442 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
443 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
444 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
445 } while (0)
446
447#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
448 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
449 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
450 } while (0)
451#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
452 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
453 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
454 } while (0)
455#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
456 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
457 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
458 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
459 } while (0)
460#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
461 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
462 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
463 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
464 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
465 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
466 } while (0)
467
468#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
469#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
470 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
471 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
472 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
473 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
474 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
475 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
476 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
477 } while (0)
478#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
479 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
480 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
481 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
482 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
483 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
484 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
485 } while (0)
486#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
487 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
488 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
489 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
490 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
491 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
492 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
493 } while (0)
494#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
495 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
496 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
497 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
498 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
499 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
500 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
501 } while (0)
502
503#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
504 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
505#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
506 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
507#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
508 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
509#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
510 do { uintptr_t const iYRegTmp = (a_iYReg); \
511 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
512 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
513 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
514 } while (0)
515
516#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
517 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
518 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
519 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
520 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
521 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
522 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
523 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
524 } while (0)
525#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
526 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
527 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
528 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
529 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
530 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
531 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
532 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
533 } while (0)
534#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
535 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
536 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
537 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
538 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
539 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
540 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
541 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
542 } while (0)
543
544#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
545 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
546 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
547 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
548 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
549 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
550 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
551 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
552 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
553 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
554 } while (0)
555#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
556 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
557 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
558 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
559 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
560 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
561 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
562 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
563 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
564 } while (0)
565#define IEM_MC_MERGE_YREG_U64HI_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
566 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
567 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
568 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
569 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
570 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
571 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
572 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
573 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
574 } while (0)
575#define IEM_MC_MERGE_YREG_U64LOCAL_U64_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
576 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
577 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
578 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
579 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
580 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
581 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
582 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
583 } while (0)
584
585#ifndef IEM_WITH_SETJMP
586# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
587 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
588# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
589 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
590# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
591 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
592#else
593# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
594 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
595# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
596 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
597# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
598 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
599#endif
600
601#ifndef IEM_WITH_SETJMP
602# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
603 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
604# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
605 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
606# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
607 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
608#else
609# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
610 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
611# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
612 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
613# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
614 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
615#endif
616
617#ifndef IEM_WITH_SETJMP
618# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
619 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
620# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
621 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
622# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
623 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
624#else
625# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
626 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
627# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
628 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
629# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
630 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
631#endif
632
633#ifdef SOME_UNUSED_FUNCTION
634# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
635 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
636#endif
637
638#ifndef IEM_WITH_SETJMP
639# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
640 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
641# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
642 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
643# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
644 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
645# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
646 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
647#else
648# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
649 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
650# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
651 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
652# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
653 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
654# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
655 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
656#endif
657
658#ifndef IEM_WITH_SETJMP
659# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
660 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u32, (a_iSeg), (a_GCPtrMem)))
661# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
662 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).au64[0], (a_iSeg), (a_GCPtrMem)))
663# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
664 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
665# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
666 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
667#else
668# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
669 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
670# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
671 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
672# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
673 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
674# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
675 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
676#endif
677
678#ifndef IEM_WITH_SETJMP
679# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
680 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
681# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
682 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
683# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
684 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
685#else
686# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
687 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
688# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
689 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
690# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
691 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
692#endif
693
694#ifndef IEM_WITH_SETJMP
695# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
696 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
697# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
698 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
699# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
700 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
701#else
702# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
703 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
704# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
705 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
706# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
707 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
708#endif
709
710
711
712#ifndef IEM_WITH_SETJMP
713# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
714 do { \
715 uint8_t u8Tmp; \
716 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
717 (a_u16Dst) = u8Tmp; \
718 } while (0)
719# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
720 do { \
721 uint8_t u8Tmp; \
722 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
723 (a_u32Dst) = u8Tmp; \
724 } while (0)
725# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
726 do { \
727 uint8_t u8Tmp; \
728 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
729 (a_u64Dst) = u8Tmp; \
730 } while (0)
731# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
732 do { \
733 uint16_t u16Tmp; \
734 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
735 (a_u32Dst) = u16Tmp; \
736 } while (0)
737# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
738 do { \
739 uint16_t u16Tmp; \
740 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
741 (a_u64Dst) = u16Tmp; \
742 } while (0)
743# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
744 do { \
745 uint32_t u32Tmp; \
746 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
747 (a_u64Dst) = u32Tmp; \
748 } while (0)
749#else /* IEM_WITH_SETJMP */
750# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
751 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
752# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
753 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
754# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
755 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
756# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
757 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
758# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
759 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
760# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
761 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
762#endif /* IEM_WITH_SETJMP */
763
764#ifndef IEM_WITH_SETJMP
765# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
766 do { \
767 uint8_t u8Tmp; \
768 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
769 (a_u16Dst) = (int8_t)u8Tmp; \
770 } while (0)
771# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
772 do { \
773 uint8_t u8Tmp; \
774 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
775 (a_u32Dst) = (int8_t)u8Tmp; \
776 } while (0)
777# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
778 do { \
779 uint8_t u8Tmp; \
780 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
781 (a_u64Dst) = (int8_t)u8Tmp; \
782 } while (0)
783# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
784 do { \
785 uint16_t u16Tmp; \
786 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
787 (a_u32Dst) = (int16_t)u16Tmp; \
788 } while (0)
789# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
790 do { \
791 uint16_t u16Tmp; \
792 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
793 (a_u64Dst) = (int16_t)u16Tmp; \
794 } while (0)
795# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
796 do { \
797 uint32_t u32Tmp; \
798 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
799 (a_u64Dst) = (int32_t)u32Tmp; \
800 } while (0)
801#else /* IEM_WITH_SETJMP */
802# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
803 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
804# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
805 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
806# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
807 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
808# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
809 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
810# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
811 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
812# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
813 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
814#endif /* IEM_WITH_SETJMP */
815
816#ifndef IEM_WITH_SETJMP
817# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
818 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
819# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
820 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
821# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
822 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
823# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
824 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
825#else
826# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
827 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
828# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
829 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
830# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
831 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
832# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
833 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
834#endif
835
836#ifndef IEM_WITH_SETJMP
837# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
838 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
839# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
840 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
841# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
842 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
843# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
844 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
845#else
846# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
847 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
848# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
849 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
850# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
851 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
852# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
853 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
854#endif
855
856#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
857#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
858#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
859#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
860#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
861#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
862#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
863 do { \
864 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
865 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
866 } while (0)
867#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
868 do { \
869 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
870 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
871 } while (0)
872
873#ifndef IEM_WITH_SETJMP
874# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
875 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
876# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
877 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
878#else
879# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
880 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
881# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
882 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
883#endif
884
885#ifndef IEM_WITH_SETJMP
886# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
887 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
888# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
889 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
890#else
891# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
892 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
893# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
894 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
895#endif
896
897
898#define IEM_MC_PUSH_U16(a_u16Value) \
899 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
900#define IEM_MC_PUSH_U32(a_u32Value) \
901 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
902#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
903 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
904#define IEM_MC_PUSH_U64(a_u64Value) \
905 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
906
907#define IEM_MC_POP_U16(a_pu16Value) \
908 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
909#define IEM_MC_POP_U32(a_pu32Value) \
910 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
911#define IEM_MC_POP_U64(a_pu64Value) \
912 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
913
914/** Maps guest memory for direct or bounce buffered access.
915 * The purpose is to pass it to an operand implementation, thus the a_iArg.
916 * @remarks May return.
917 */
918#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
919 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
920 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
921
922/** Maps guest memory for direct or bounce buffered access.
923 * The purpose is to pass it to an operand implementation, thus the a_iArg.
924 * @remarks May return.
925 */
926#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
927 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
928 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
929
930/** Commits the memory and unmaps the guest memory.
931 * @remarks May return.
932 */
933#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
934 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
935
936/** Commits the memory and unmaps the guest memory unless the FPU status word
937 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
938 * that would cause FLD not to store.
939 *
940 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
941 * store, while \#P will not.
942 *
943 * @remarks May in theory return - for now.
944 */
945#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
946 do { \
947 if ( !(a_u16FSW & X86_FSW_ES) \
948 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
949 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
950 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
951 } while (0)
952
953/** Calculate efficient address from R/M. */
954#ifndef IEM_WITH_SETJMP
955# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
956 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
957#else
958# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
959 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
960#endif
961
962#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
963#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
964#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
965#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
966#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
967#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
968#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
969
970/**
971 * Defers the rest of the instruction emulation to a C implementation routine
972 * and returns, only taking the standard parameters.
973 *
974 * @param a_pfnCImpl The pointer to the C routine.
975 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
976 */
977#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
978
979/**
980 * Defers the rest of instruction emulation to a C implementation routine and
981 * returns, taking one argument in addition to the standard ones.
982 *
983 * @param a_pfnCImpl The pointer to the C routine.
984 * @param a0 The argument.
985 */
986#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
987
988/**
989 * Defers the rest of the instruction emulation to a C implementation routine
990 * and returns, taking two arguments in addition to the standard ones.
991 *
992 * @param a_pfnCImpl The pointer to the C routine.
993 * @param a0 The first extra argument.
994 * @param a1 The second extra argument.
995 */
996#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
997
998/**
999 * Defers the rest of the instruction emulation to a C implementation routine
1000 * and returns, taking three arguments in addition to the standard ones.
1001 *
1002 * @param a_pfnCImpl The pointer to the C routine.
1003 * @param a0 The first extra argument.
1004 * @param a1 The second extra argument.
1005 * @param a2 The third extra argument.
1006 */
1007#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1008
1009/**
1010 * Defers the rest of the instruction emulation to a C implementation routine
1011 * and returns, taking four arguments in addition to the standard ones.
1012 *
1013 * @param a_pfnCImpl The pointer to the C routine.
1014 * @param a0 The first extra argument.
1015 * @param a1 The second extra argument.
1016 * @param a2 The third extra argument.
1017 * @param a3 The fourth extra argument.
1018 */
1019#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1020
1021/**
1022 * Defers the rest of the instruction emulation to a C implementation routine
1023 * and returns, taking two arguments in addition to the standard ones.
1024 *
1025 * @param a_pfnCImpl The pointer to the C routine.
1026 * @param a0 The first extra argument.
1027 * @param a1 The second extra argument.
1028 * @param a2 The third extra argument.
1029 * @param a3 The fourth extra argument.
1030 * @param a4 The fifth extra argument.
1031 */
1032#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1033
1034/**
1035 * Defers the entire instruction emulation to a C implementation routine and
1036 * returns, only taking the standard parameters.
1037 *
1038 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1039 *
1040 * @param a_pfnCImpl The pointer to the C routine.
1041 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1042 */
1043#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1044
1045/**
1046 * Defers the entire instruction emulation to a C implementation routine and
1047 * returns, taking one argument in addition to the standard ones.
1048 *
1049 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1050 *
1051 * @param a_pfnCImpl The pointer to the C routine.
1052 * @param a0 The argument.
1053 */
1054#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1055
1056/**
1057 * Defers the entire instruction emulation to a C implementation routine and
1058 * returns, taking two arguments in addition to the standard ones.
1059 *
1060 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1061 *
1062 * @param a_pfnCImpl The pointer to the C routine.
1063 * @param a0 The first extra argument.
1064 * @param a1 The second extra argument.
1065 */
1066#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1067
1068/**
1069 * Defers the entire instruction emulation to a C implementation routine and
1070 * returns, taking three arguments in addition to the standard ones.
1071 *
1072 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1073 *
1074 * @param a_pfnCImpl The pointer to the C routine.
1075 * @param a0 The first extra argument.
1076 * @param a1 The second extra argument.
1077 * @param a2 The third extra argument.
1078 */
1079#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1080
1081/**
1082 * Calls a FPU assembly implementation taking one visible argument.
1083 *
1084 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1085 * @param a0 The first extra argument.
1086 */
1087#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1088 do { \
1089 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1090 } while (0)
1091
1092/**
1093 * Calls a FPU assembly implementation taking two visible arguments.
1094 *
1095 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1096 * @param a0 The first extra argument.
1097 * @param a1 The second extra argument.
1098 */
1099#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1100 do { \
1101 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1102 } while (0)
1103
1104/**
1105 * Calls a FPU assembly implementation taking three visible arguments.
1106 *
1107 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1108 * @param a0 The first extra argument.
1109 * @param a1 The second extra argument.
1110 * @param a2 The third extra argument.
1111 */
1112#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1113 do { \
1114 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1115 } while (0)
1116
1117#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1118 do { \
1119 (a_FpuData).FSW = (a_FSW); \
1120 (a_FpuData).r80Result = *(a_pr80Value); \
1121 } while (0)
1122
1123/** Pushes FPU result onto the stack. */
1124#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1125 iemFpuPushResult(pVCpu, &a_FpuData)
1126/** Pushes FPU result onto the stack and sets the FPUDP. */
1127#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1128 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1129
1130/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1131#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1132 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1133
1134/** Stores FPU result in a stack register. */
1135#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1136 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1137/** Stores FPU result in a stack register and pops the stack. */
1138#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1139 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1140/** Stores FPU result in a stack register and sets the FPUDP. */
1141#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1142 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1143/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1144 * stack. */
1145#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1146 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1147
1148/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1149#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1150 iemFpuUpdateOpcodeAndIp(pVCpu)
1151/** Free a stack register (for FFREE and FFREEP). */
1152#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1153 iemFpuStackFree(pVCpu, a_iStReg)
1154/** Increment the FPU stack pointer. */
1155#define IEM_MC_FPU_STACK_INC_TOP() \
1156 iemFpuStackIncTop(pVCpu)
1157/** Decrement the FPU stack pointer. */
1158#define IEM_MC_FPU_STACK_DEC_TOP() \
1159 iemFpuStackDecTop(pVCpu)
1160
1161/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1162#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1163 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1164/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1165#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1166 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1167/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1168#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1169 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1170/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1171#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1172 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1173/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1174 * stack. */
1175#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1176 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1177/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1178#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1179 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1180
1181/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1182#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1183 iemFpuStackUnderflow(pVCpu, a_iStDst)
1184/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1185 * stack. */
1186#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1187 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1188/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1189 * FPUDS. */
1190#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1191 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1192/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1193 * FPUDS. Pops stack. */
1194#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1195 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1196/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1197 * stack twice. */
1198#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1199 iemFpuStackUnderflowThenPopPop(pVCpu)
1200/** Raises a FPU stack underflow exception for an instruction pushing a result
1201 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1202#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1203 iemFpuStackPushUnderflow(pVCpu)
1204/** Raises a FPU stack underflow exception for an instruction pushing a result
1205 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1206#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1207 iemFpuStackPushUnderflowTwo(pVCpu)
1208
1209/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1210 * FPUIP, FPUCS and FOP. */
1211#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1212 iemFpuStackPushOverflow(pVCpu)
1213/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1214 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1215#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1216 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1217/** Prepares for using the FPU state.
1218 * Ensures that we can use the host FPU in the current context (RC+R0.
1219 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1220#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1221/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1222#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1223/** Actualizes the guest FPU state so it can be accessed and modified. */
1224#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1225
1226/** Prepares for using the SSE state.
1227 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1228 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1229#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1230/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1231#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1232/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1233#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1234
1235/** Prepares for using the AVX state.
1236 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1237 * Ensures the guest AVX state in the CPUMCTX is up to date.
1238 * @note This will include the AVX512 state too when support for it is added
1239 * due to the zero extending feature of VEX instruction. */
1240#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1241/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1242#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1243/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1244#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1245
1246/**
1247 * Calls a MMX assembly implementation taking two visible arguments.
1248 *
1249 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1250 * @param a0 The first extra argument.
1251 * @param a1 The second extra argument.
1252 */
1253#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1254 do { \
1255 IEM_MC_PREPARE_FPU_USAGE(); \
1256 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1257 } while (0)
1258
1259/**
1260 * Calls a MMX assembly implementation taking three visible arguments.
1261 *
1262 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1263 * @param a0 The first extra argument.
1264 * @param a1 The second extra argument.
1265 * @param a2 The third extra argument.
1266 */
1267#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1268 do { \
1269 IEM_MC_PREPARE_FPU_USAGE(); \
1270 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1271 } while (0)
1272
1273
1274/**
1275 * Calls a SSE assembly implementation taking two visible arguments.
1276 *
1277 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1278 * @param a0 The first extra argument.
1279 * @param a1 The second extra argument.
1280 */
1281#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1282 do { \
1283 IEM_MC_PREPARE_SSE_USAGE(); \
1284 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1285 } while (0)
1286
1287/**
1288 * Calls a SSE assembly implementation taking three visible arguments.
1289 *
1290 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1291 * @param a0 The first extra argument.
1292 * @param a1 The second extra argument.
1293 * @param a2 The third extra argument.
1294 */
1295#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1296 do { \
1297 IEM_MC_PREPARE_SSE_USAGE(); \
1298 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1299 } while (0)
1300
1301
1302/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1303 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1304#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1305 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1306
1307/**
1308 * Calls a AVX assembly implementation taking two visible arguments.
1309 *
1310 * There is one implicit zero'th argument, a pointer to the extended state.
1311 *
1312 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1313 * @param a1 The first extra argument.
1314 * @param a2 The second extra argument.
1315 */
1316#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1317 do { \
1318 IEM_MC_PREPARE_AVX_USAGE(); \
1319 a_pfnAImpl(pXState, (a1), (a2)); \
1320 } while (0)
1321
1322/**
1323 * Calls a AVX assembly implementation taking three visible arguments.
1324 *
1325 * There is one implicit zero'th argument, a pointer to the extended state.
1326 *
1327 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1328 * @param a1 The first extra argument.
1329 * @param a2 The second extra argument.
1330 * @param a3 The third extra argument.
1331 */
1332#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1333 do { \
1334 IEM_MC_PREPARE_AVX_USAGE(); \
1335 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1336 } while (0)
1337
1338/** @note Not for IOPL or IF testing. */
1339#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1340/** @note Not for IOPL or IF testing. */
1341#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1342/** @note Not for IOPL or IF testing. */
1343#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1344/** @note Not for IOPL or IF testing. */
1345#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1346/** @note Not for IOPL or IF testing. */
1347#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1348 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1349 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1350/** @note Not for IOPL or IF testing. */
1351#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1352 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1353 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1354/** @note Not for IOPL or IF testing. */
1355#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1356 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1357 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1358 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1359/** @note Not for IOPL or IF testing. */
1360#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1361 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1362 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1363 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1364#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1365#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1366#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1367/** @note Not for IOPL or IF testing. */
1368#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1369 if ( pVCpu->cpum.GstCtx.cx != 0 \
1370 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1371/** @note Not for IOPL or IF testing. */
1372#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1373 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1374 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1375/** @note Not for IOPL or IF testing. */
1376#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1377 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1378 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1379/** @note Not for IOPL or IF testing. */
1380#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1381 if ( pVCpu->cpum.GstCtx.cx != 0 \
1382 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1383/** @note Not for IOPL or IF testing. */
1384#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1385 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1386 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1387/** @note Not for IOPL or IF testing. */
1388#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1389 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1390 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1391#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1392#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1393
1394#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1395 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1396#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1397 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1398#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1399 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1400#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1401 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1402#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1403 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1404#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1405 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1406#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1407 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1408#define IEM_MC_IF_FCW_IM() \
1409 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1410
1411#define IEM_MC_ELSE() } else {
1412#define IEM_MC_ENDIF() } do {} while (0)
1413
1414/** @} */
1415
1416#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1417
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