VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 95540

Last change on this file since 95540 was 95540, checked in by vboxsync, 2 years ago

VMM/IEM: vmovlhps, vmovhps, vmovhpd. bugref:9898
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File size: 76.3 KB
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1/* $Id: IEMMc.h 95540 2022-07-06 20:44:32Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
19#define VMM_INCLUDED_SRC_include_IEMMc_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24
25/** @name "Microcode" macros.
26 *
27 * The idea is that we should be able to use the same code to interpret
28 * instructions as well as recompiler instructions. Thus this obfuscation.
29 *
30 * @{
31 */
32#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
33#define IEM_MC_END() }
34#define IEM_MC_PAUSE() do {} while (0)
35#define IEM_MC_CONTINUE() do {} while (0)
36
37/** Internal macro. */
38#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
39 do \
40 { \
41 VBOXSTRICTRC rcStrict2 = a_Expr; \
42 if (rcStrict2 != VINF_SUCCESS) \
43 return rcStrict2; \
44 } while (0)
45
46
47#define IEM_MC_ADVANCE_RIP() iemRegUpdateRipAndClearRF(pVCpu)
48#define IEM_MC_REL_JMP_S8(a_i8) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS8(pVCpu, a_i8))
49#define IEM_MC_REL_JMP_S16(a_i16) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS16(pVCpu, a_i16))
50#define IEM_MC_REL_JMP_S32(a_i32) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS32(pVCpu, a_i32))
51#define IEM_MC_SET_RIP_U16(a_u16NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u16NewIP)))
52#define IEM_MC_SET_RIP_U32(a_u32NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u32NewIP)))
53#define IEM_MC_SET_RIP_U64(a_u64NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u64NewIP)))
54#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
55#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
56 do { \
57 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
58 return iemRaiseDeviceNotAvailable(pVCpu); \
59 } while (0)
60#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
61 do { \
62 if ((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)) \
63 return iemRaiseDeviceNotAvailable(pVCpu); \
64 } while (0)
65#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
66 do { \
67 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
68 return iemRaiseMathFault(pVCpu); \
69 } while (0)
70#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
71 do { \
72 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
73 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
74 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx2) \
75 return iemRaiseUndefinedOpcode(pVCpu); \
76 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
77 return iemRaiseDeviceNotAvailable(pVCpu); \
78 } while (0)
79#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
80 do { \
81 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
82 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
83 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) \
84 return iemRaiseUndefinedOpcode(pVCpu); \
85 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
86 return iemRaiseDeviceNotAvailable(pVCpu); \
87 } while (0)
88#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
89 do { \
90 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
91 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
92 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42) \
93 return iemRaiseUndefinedOpcode(pVCpu); \
94 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
95 return iemRaiseDeviceNotAvailable(pVCpu); \
96 } while (0)
97#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
98 do { \
99 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
100 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
101 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse41) \
102 return iemRaiseUndefinedOpcode(pVCpu); \
103 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
104 return iemRaiseDeviceNotAvailable(pVCpu); \
105 } while (0)
106#define IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT() \
107 do { \
108 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
109 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
110 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3) \
111 return iemRaiseUndefinedOpcode(pVCpu); \
112 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
113 return iemRaiseDeviceNotAvailable(pVCpu); \
114 } while (0)
115#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
116 do { \
117 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
118 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
119 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse3) \
120 return iemRaiseUndefinedOpcode(pVCpu); \
121 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
122 return iemRaiseDeviceNotAvailable(pVCpu); \
123 } while (0)
124#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
125 do { \
126 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
127 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
128 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) \
129 return iemRaiseUndefinedOpcode(pVCpu); \
130 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
131 return iemRaiseDeviceNotAvailable(pVCpu); \
132 } while (0)
133#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
134 do { \
135 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
136 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
137 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) \
138 return iemRaiseUndefinedOpcode(pVCpu); \
139 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
140 return iemRaiseDeviceNotAvailable(pVCpu); \
141 } while (0)
142#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
143 do { \
144 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
145 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMmx) \
146 return iemRaiseUndefinedOpcode(pVCpu); \
147 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
148 return iemRaiseDeviceNotAvailable(pVCpu); \
149 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
150 return iemRaiseMathFault(pVCpu); \
151 } while (0)
152#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(a_fSupported) \
153 do { \
154 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
155 || !(a_fSupported)) \
156 return iemRaiseUndefinedOpcode(pVCpu); \
157 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
158 return iemRaiseDeviceNotAvailable(pVCpu); \
159 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
160 return iemRaiseMathFault(pVCpu); \
161 } while (0)
162#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() \
163 do { \
164 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
165 || ( !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse \
166 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAmdMmxExts) ) \
167 return iemRaiseUndefinedOpcode(pVCpu); \
168 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
169 return iemRaiseDeviceNotAvailable(pVCpu); \
170 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
171 return iemRaiseMathFault(pVCpu); \
172 } while (0)
173#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
174 do { \
175 if (pVCpu->iem.s.uCpl != 0) \
176 return iemRaiseGeneralProtectionFault0(pVCpu); \
177 } while (0)
178#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
179 do { \
180 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
181 else return iemRaiseGeneralProtectionFault0(pVCpu); \
182 } while (0)
183#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
184 do { \
185 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
186 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase \
187 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
188 return iemRaiseUndefinedOpcode(pVCpu); \
189 } while (0)
190#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
191 do { \
192 if (!IEM_IS_CANONICAL(a_u64Addr)) \
193 return iemRaiseGeneralProtectionFault0(pVCpu); \
194 } while (0)
195
196
197#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
198#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
199#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
200#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
201#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
202#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
203#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
204 uint32_t a_Name; \
205 uint32_t *a_pName = &a_Name
206#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
207 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
208
209#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
210#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
211
212#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
213#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
214#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
215#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
216#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
217#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
218#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
219#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
220#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
221#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
222#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
223#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
224#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
225#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
226#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
227#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
228#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
229#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
230 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
231 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
232 } while (0)
233#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
234 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
235 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
236 } while (0)
237#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
238 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
239 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
240 } while (0)
241/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
242#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
243 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
244 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
245 } while (0)
246#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
247 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
248 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
249 } while (0)
250/** @note Not for IOPL or IF testing or modification. */
251#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
252#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
253#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
254#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
255
256#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
257#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
258#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
259#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
260#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
261#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
262#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
263#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
264#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
265#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
266/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
267#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
268 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
269 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
270 } while (0)
271#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
272 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
273 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
274 } while (0)
275#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
276 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
277
278
279#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
280#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
281/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
282 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
283#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
284#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
285/** @note Not for IOPL or IF testing or modification. */
286#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.u
287
288#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
289#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
290#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
291 do { \
292 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
293 *pu32Reg += (a_u32Value); \
294 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
295 } while (0)
296#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
297
298#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
299#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
300#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
301 do { \
302 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
303 *pu32Reg -= (a_u32Value); \
304 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
305 } while (0)
306#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
307#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
308
309#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
310#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
311#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
312#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
313#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
314#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
315#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
316
317#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
318#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
319#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
320#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
321
322#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
323#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
324#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
325
326#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
327#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
328#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
329
330#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
331#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
332#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
333
334#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
335#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
336#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
337
338#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
339
340#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
341
342#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
343#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
344#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
345 do { \
346 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
347 *pu32Reg &= (a_u32Value); \
348 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
349 } while (0)
350#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
351
352#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
353#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
354#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
355 do { \
356 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
357 *pu32Reg |= (a_u32Value); \
358 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
359 } while (0)
360#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
361
362
363/** @note Not for IOPL or IF modification. */
364#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
365/** @note Not for IOPL or IF modification. */
366#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
367/** @note Not for IOPL or IF modification. */
368#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
369
370#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
371
372/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
373#define IEM_MC_FPU_TO_MMX_MODE() do { \
374 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
375 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
376 } while (0)
377
378/** Switches the FPU state from MMX mode (FTW=0xffff). */
379#define IEM_MC_FPU_FROM_MMX_MODE() do { \
380 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
381 } while (0)
382
383#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
384 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
385#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
386 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
387#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
388 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
389 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
390 } while (0)
391#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
392 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
393 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
394 } while (0)
395#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
396 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
397#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
398 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
399#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
400 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
401#define IEM_MC_MODIFIED_MREG(a_iMReg) \
402 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
403#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
404 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
405
406#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
407 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
408 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
409 } while (0)
410#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) \
411 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; } while (0)
412#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) \
413 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0]; } while (0)
414#define IEM_MC_FETCH_XREG_HI_U64(a_u64Value, a_iXReg) \
415 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; } while (0)
416#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
417 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
418 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
419 } while (0)
420#define IEM_MC_STORE_XREG_U64(a_iXReg, a_u64Value) \
421 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); } while (0)
422#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
423 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
424 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
425 } while (0)
426#define IEM_MC_STORE_XREG_U32(a_iXReg, a_u32Value) \
427 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = (a_u32Value); } while (0)
428#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
429 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
430 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
431 } while (0)
432#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
433 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
434#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
435 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
436#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
437 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
438#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
439 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
440#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
441 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
442 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
443 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
444 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
445 } while (0)
446
447#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
448 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
449 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
450 } while (0)
451#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
452 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
453 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
454 } while (0)
455#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
456 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
457 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
458 } while (0)
459#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
460 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
461 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
462 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
463 } while (0)
464#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
465 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
466 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
467 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
468 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
469 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
470 } while (0)
471
472#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
473#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
474 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
475 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
476 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
477 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
478 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
479 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
480 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
481 } while (0)
482#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
483 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
484 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
485 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
486 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
487 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
488 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
489 } while (0)
490#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
491 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
492 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
493 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
494 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
495 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
496 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
497 } while (0)
498#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
499 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
500 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
501 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
502 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
503 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
504 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
505 } while (0)
506
507#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
508 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
509#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
510 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
511#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
512 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
513#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
514 do { uintptr_t const iYRegTmp = (a_iYReg); \
515 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
516 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
517 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
518 } while (0)
519
520#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
521 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
522 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
523 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
524 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
525 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
526 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
527 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
528 } while (0)
529#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
530 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
531 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
532 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
533 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
534 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
535 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
536 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
537 } while (0)
538#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
539 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
540 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
541 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
542 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
543 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
544 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
545 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
546 } while (0)
547
548#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
549 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
550 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
551 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
552 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
553 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
554 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
555 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
556 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
557 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
558 } while (0)
559#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
560 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
561 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
562 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
563 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
564 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
565 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
566 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
567 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
568 } while (0)
569#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
570 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
571 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
572 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
573 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
574 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
575 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
576 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
577 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
578 } while (0)
579#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
580 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
581 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
582 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
583 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
584 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
585 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
586 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
587 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
588 } while (0)
589#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
590 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
591 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
592 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
593 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
594 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
595 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
596 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
597 } while (0)
598#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
599 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
600 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
601 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
602 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
603 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
604 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
605 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
606 } while (0)
607
608#ifndef IEM_WITH_SETJMP
609# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
610 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
611# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
612 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
613# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
614 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
615#else
616# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
617 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
618# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
619 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
620# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
621 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
622#endif
623
624#ifndef IEM_WITH_SETJMP
625# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
626 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
627# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
628 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
629# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
630 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
631#else
632# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
633 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
634# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
635 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
636# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
637 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
638#endif
639
640#ifndef IEM_WITH_SETJMP
641# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
642 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
643# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
644 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
645# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
646 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
647#else
648# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
649 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
650# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
651 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
652# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
653 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
654#endif
655
656#ifdef SOME_UNUSED_FUNCTION
657# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
658 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
659#endif
660
661#ifndef IEM_WITH_SETJMP
662# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
663 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
664# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
665 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
666# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
667 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
668# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
669 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
670#else
671# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
672 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
673# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
674 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
675# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
676 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
677# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
678 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
679#endif
680
681#ifndef IEM_WITH_SETJMP
682# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
683 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u32, (a_iSeg), (a_GCPtrMem)))
684# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
685 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).au64[0], (a_iSeg), (a_GCPtrMem)))
686# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
687 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
688# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
689 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
690#else
691# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
692 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
693# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
694 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
695# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
696 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
697# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
698 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
699#endif
700
701#ifndef IEM_WITH_SETJMP
702# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
703 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
704# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
705 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
706# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
707 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
708#else
709# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
710 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
711# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
712 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
713# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
714 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
715#endif
716
717#ifndef IEM_WITH_SETJMP
718# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
719 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
720# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
721 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
722# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
723 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
724#else
725# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
726 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
727# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
728 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
729# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
730 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
731#endif
732
733
734
735#ifndef IEM_WITH_SETJMP
736# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
737 do { \
738 uint8_t u8Tmp; \
739 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
740 (a_u16Dst) = u8Tmp; \
741 } while (0)
742# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
743 do { \
744 uint8_t u8Tmp; \
745 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
746 (a_u32Dst) = u8Tmp; \
747 } while (0)
748# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
749 do { \
750 uint8_t u8Tmp; \
751 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
752 (a_u64Dst) = u8Tmp; \
753 } while (0)
754# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
755 do { \
756 uint16_t u16Tmp; \
757 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
758 (a_u32Dst) = u16Tmp; \
759 } while (0)
760# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
761 do { \
762 uint16_t u16Tmp; \
763 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
764 (a_u64Dst) = u16Tmp; \
765 } while (0)
766# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
767 do { \
768 uint32_t u32Tmp; \
769 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
770 (a_u64Dst) = u32Tmp; \
771 } while (0)
772#else /* IEM_WITH_SETJMP */
773# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
774 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
775# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
776 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
777# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
778 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
779# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
780 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
781# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
782 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
783# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
784 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
785#endif /* IEM_WITH_SETJMP */
786
787#ifndef IEM_WITH_SETJMP
788# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
789 do { \
790 uint8_t u8Tmp; \
791 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
792 (a_u16Dst) = (int8_t)u8Tmp; \
793 } while (0)
794# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
795 do { \
796 uint8_t u8Tmp; \
797 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
798 (a_u32Dst) = (int8_t)u8Tmp; \
799 } while (0)
800# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
801 do { \
802 uint8_t u8Tmp; \
803 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
804 (a_u64Dst) = (int8_t)u8Tmp; \
805 } while (0)
806# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
807 do { \
808 uint16_t u16Tmp; \
809 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
810 (a_u32Dst) = (int16_t)u16Tmp; \
811 } while (0)
812# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
813 do { \
814 uint16_t u16Tmp; \
815 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
816 (a_u64Dst) = (int16_t)u16Tmp; \
817 } while (0)
818# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
819 do { \
820 uint32_t u32Tmp; \
821 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
822 (a_u64Dst) = (int32_t)u32Tmp; \
823 } while (0)
824#else /* IEM_WITH_SETJMP */
825# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
826 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
827# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
828 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
829# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
830 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
831# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
832 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
833# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
834 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
835# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
836 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
837#endif /* IEM_WITH_SETJMP */
838
839#ifndef IEM_WITH_SETJMP
840# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
841 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
842# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
843 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
844# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
845 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
846# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
847 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
848#else
849# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
850 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
851# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
852 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
853# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
854 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
855# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
856 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
857#endif
858
859#ifndef IEM_WITH_SETJMP
860# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
861 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
862# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
863 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
864# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
865 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
866# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
867 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
868#else
869# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
870 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
871# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
872 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
873# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
874 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
875# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
876 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
877#endif
878
879#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
880#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
881#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
882#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
883#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
884#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
885#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
886 do { \
887 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
888 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
889 } while (0)
890#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
891 do { \
892 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
893 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
894 } while (0)
895
896#ifndef IEM_WITH_SETJMP
897# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
898 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
899# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
900 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
901#else
902# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
903 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
904# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
905 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
906#endif
907
908#ifndef IEM_WITH_SETJMP
909# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
910 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
911# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
912 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
913#else
914# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
915 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
916# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
917 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
918#endif
919
920
921#define IEM_MC_PUSH_U16(a_u16Value) \
922 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
923#define IEM_MC_PUSH_U32(a_u32Value) \
924 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
925#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
926 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
927#define IEM_MC_PUSH_U64(a_u64Value) \
928 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
929
930#define IEM_MC_POP_U16(a_pu16Value) \
931 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
932#define IEM_MC_POP_U32(a_pu32Value) \
933 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
934#define IEM_MC_POP_U64(a_pu64Value) \
935 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
936
937/** Maps guest memory for direct or bounce buffered access.
938 * The purpose is to pass it to an operand implementation, thus the a_iArg.
939 * @remarks May return.
940 */
941#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
942 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
943 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
944
945/** Maps guest memory for direct or bounce buffered access.
946 * The purpose is to pass it to an operand implementation, thus the a_iArg.
947 * @remarks May return.
948 */
949#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
950 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
951 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
952
953/** Commits the memory and unmaps the guest memory.
954 * @remarks May return.
955 */
956#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
957 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
958
959/** Commits the memory and unmaps the guest memory unless the FPU status word
960 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
961 * that would cause FLD not to store.
962 *
963 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
964 * store, while \#P will not.
965 *
966 * @remarks May in theory return - for now.
967 */
968#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
969 do { \
970 if ( !(a_u16FSW & X86_FSW_ES) \
971 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
972 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
973 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
974 } while (0)
975
976/** Calculate efficient address from R/M. */
977#ifndef IEM_WITH_SETJMP
978# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
979 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
980#else
981# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
982 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
983#endif
984
985#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
986#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
987#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
988#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
989#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
990#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
991#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
992
993/**
994 * Defers the rest of the instruction emulation to a C implementation routine
995 * and returns, only taking the standard parameters.
996 *
997 * @param a_pfnCImpl The pointer to the C routine.
998 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
999 */
1000#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1001
1002/**
1003 * Defers the rest of instruction emulation to a C implementation routine and
1004 * returns, taking one argument in addition to the standard ones.
1005 *
1006 * @param a_pfnCImpl The pointer to the C routine.
1007 * @param a0 The argument.
1008 */
1009#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1010
1011/**
1012 * Defers the rest of the instruction emulation to a C implementation routine
1013 * and returns, taking two arguments in addition to the standard ones.
1014 *
1015 * @param a_pfnCImpl The pointer to the C routine.
1016 * @param a0 The first extra argument.
1017 * @param a1 The second extra argument.
1018 */
1019#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1020
1021/**
1022 * Defers the rest of the instruction emulation to a C implementation routine
1023 * and returns, taking three arguments in addition to the standard ones.
1024 *
1025 * @param a_pfnCImpl The pointer to the C routine.
1026 * @param a0 The first extra argument.
1027 * @param a1 The second extra argument.
1028 * @param a2 The third extra argument.
1029 */
1030#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1031
1032/**
1033 * Defers the rest of the instruction emulation to a C implementation routine
1034 * and returns, taking four arguments in addition to the standard ones.
1035 *
1036 * @param a_pfnCImpl The pointer to the C routine.
1037 * @param a0 The first extra argument.
1038 * @param a1 The second extra argument.
1039 * @param a2 The third extra argument.
1040 * @param a3 The fourth extra argument.
1041 */
1042#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1043
1044/**
1045 * Defers the rest of the instruction emulation to a C implementation routine
1046 * and returns, taking two arguments in addition to the standard ones.
1047 *
1048 * @param a_pfnCImpl The pointer to the C routine.
1049 * @param a0 The first extra argument.
1050 * @param a1 The second extra argument.
1051 * @param a2 The third extra argument.
1052 * @param a3 The fourth extra argument.
1053 * @param a4 The fifth extra argument.
1054 */
1055#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1056
1057/**
1058 * Defers the entire instruction emulation to a C implementation routine and
1059 * returns, only taking the standard parameters.
1060 *
1061 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1062 *
1063 * @param a_pfnCImpl The pointer to the C routine.
1064 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1065 */
1066#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1067
1068/**
1069 * Defers the entire instruction emulation to a C implementation routine and
1070 * returns, taking one argument in addition to the standard ones.
1071 *
1072 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1073 *
1074 * @param a_pfnCImpl The pointer to the C routine.
1075 * @param a0 The argument.
1076 */
1077#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1078
1079/**
1080 * Defers the entire instruction emulation to a C implementation routine and
1081 * returns, taking two arguments in addition to the standard ones.
1082 *
1083 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1084 *
1085 * @param a_pfnCImpl The pointer to the C routine.
1086 * @param a0 The first extra argument.
1087 * @param a1 The second extra argument.
1088 */
1089#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1090
1091/**
1092 * Defers the entire instruction emulation to a C implementation routine and
1093 * returns, taking three arguments in addition to the standard ones.
1094 *
1095 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1096 *
1097 * @param a_pfnCImpl The pointer to the C routine.
1098 * @param a0 The first extra argument.
1099 * @param a1 The second extra argument.
1100 * @param a2 The third extra argument.
1101 */
1102#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1103
1104/**
1105 * Calls a FPU assembly implementation taking one visible argument.
1106 *
1107 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1108 * @param a0 The first extra argument.
1109 */
1110#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1111 do { \
1112 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1113 } while (0)
1114
1115/**
1116 * Calls a FPU assembly implementation taking two visible arguments.
1117 *
1118 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1119 * @param a0 The first extra argument.
1120 * @param a1 The second extra argument.
1121 */
1122#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1123 do { \
1124 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1125 } while (0)
1126
1127/**
1128 * Calls a FPU assembly implementation taking three visible arguments.
1129 *
1130 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1131 * @param a0 The first extra argument.
1132 * @param a1 The second extra argument.
1133 * @param a2 The third extra argument.
1134 */
1135#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1136 do { \
1137 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1138 } while (0)
1139
1140#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1141 do { \
1142 (a_FpuData).FSW = (a_FSW); \
1143 (a_FpuData).r80Result = *(a_pr80Value); \
1144 } while (0)
1145
1146/** Pushes FPU result onto the stack. */
1147#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1148 iemFpuPushResult(pVCpu, &a_FpuData)
1149/** Pushes FPU result onto the stack and sets the FPUDP. */
1150#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1151 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1152
1153/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1154#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1155 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1156
1157/** Stores FPU result in a stack register. */
1158#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1159 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1160/** Stores FPU result in a stack register and pops the stack. */
1161#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1162 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1163/** Stores FPU result in a stack register and sets the FPUDP. */
1164#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1165 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1166/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1167 * stack. */
1168#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1169 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1170
1171/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1172#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1173 iemFpuUpdateOpcodeAndIp(pVCpu)
1174/** Free a stack register (for FFREE and FFREEP). */
1175#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1176 iemFpuStackFree(pVCpu, a_iStReg)
1177/** Increment the FPU stack pointer. */
1178#define IEM_MC_FPU_STACK_INC_TOP() \
1179 iemFpuStackIncTop(pVCpu)
1180/** Decrement the FPU stack pointer. */
1181#define IEM_MC_FPU_STACK_DEC_TOP() \
1182 iemFpuStackDecTop(pVCpu)
1183
1184/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1185#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1186 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1187/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1188#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1189 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1190/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1191#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1192 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1193/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1194#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1195 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1196/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1197 * stack. */
1198#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1199 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1200/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1201#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1202 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1203
1204/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1205#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1206 iemFpuStackUnderflow(pVCpu, a_iStDst)
1207/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1208 * stack. */
1209#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1210 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1211/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1212 * FPUDS. */
1213#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1214 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1215/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1216 * FPUDS. Pops stack. */
1217#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1218 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1219/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1220 * stack twice. */
1221#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1222 iemFpuStackUnderflowThenPopPop(pVCpu)
1223/** Raises a FPU stack underflow exception for an instruction pushing a result
1224 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1225#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1226 iemFpuStackPushUnderflow(pVCpu)
1227/** Raises a FPU stack underflow exception for an instruction pushing a result
1228 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1229#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1230 iemFpuStackPushUnderflowTwo(pVCpu)
1231
1232/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1233 * FPUIP, FPUCS and FOP. */
1234#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1235 iemFpuStackPushOverflow(pVCpu)
1236/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1237 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1238#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1239 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1240/** Prepares for using the FPU state.
1241 * Ensures that we can use the host FPU in the current context (RC+R0.
1242 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1243#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1244/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1245#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1246/** Actualizes the guest FPU state so it can be accessed and modified. */
1247#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1248
1249/** Prepares for using the SSE state.
1250 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1251 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1252#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1253/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1254#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1255/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1256#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1257
1258/** Prepares for using the AVX state.
1259 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1260 * Ensures the guest AVX state in the CPUMCTX is up to date.
1261 * @note This will include the AVX512 state too when support for it is added
1262 * due to the zero extending feature of VEX instruction. */
1263#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1264/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1265#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1266/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1267#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1268
1269/**
1270 * Calls a MMX assembly implementation taking two visible arguments.
1271 *
1272 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1273 * @param a0 The first extra argument.
1274 * @param a1 The second extra argument.
1275 */
1276#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1277 do { \
1278 IEM_MC_PREPARE_FPU_USAGE(); \
1279 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1280 } while (0)
1281
1282/**
1283 * Calls a MMX assembly implementation taking three visible arguments.
1284 *
1285 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1286 * @param a0 The first extra argument.
1287 * @param a1 The second extra argument.
1288 * @param a2 The third extra argument.
1289 */
1290#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1291 do { \
1292 IEM_MC_PREPARE_FPU_USAGE(); \
1293 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1294 } while (0)
1295
1296
1297/**
1298 * Calls a SSE assembly implementation taking two visible arguments.
1299 *
1300 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1301 * @param a0 The first extra argument.
1302 * @param a1 The second extra argument.
1303 */
1304#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1305 do { \
1306 IEM_MC_PREPARE_SSE_USAGE(); \
1307 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1308 } while (0)
1309
1310/**
1311 * Calls a SSE assembly implementation taking three visible arguments.
1312 *
1313 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1314 * @param a0 The first extra argument.
1315 * @param a1 The second extra argument.
1316 * @param a2 The third extra argument.
1317 */
1318#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1319 do { \
1320 IEM_MC_PREPARE_SSE_USAGE(); \
1321 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1322 } while (0)
1323
1324
1325/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1326 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1327#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1328 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1329
1330/**
1331 * Calls a AVX assembly implementation taking two visible arguments.
1332 *
1333 * There is one implicit zero'th argument, a pointer to the extended state.
1334 *
1335 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1336 * @param a1 The first extra argument.
1337 * @param a2 The second extra argument.
1338 */
1339#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1340 do { \
1341 IEM_MC_PREPARE_AVX_USAGE(); \
1342 a_pfnAImpl(pXState, (a1), (a2)); \
1343 } while (0)
1344
1345/**
1346 * Calls a AVX assembly implementation taking three visible arguments.
1347 *
1348 * There is one implicit zero'th argument, a pointer to the extended state.
1349 *
1350 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1351 * @param a1 The first extra argument.
1352 * @param a2 The second extra argument.
1353 * @param a3 The third extra argument.
1354 */
1355#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1356 do { \
1357 IEM_MC_PREPARE_AVX_USAGE(); \
1358 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1359 } while (0)
1360
1361/** @note Not for IOPL or IF testing. */
1362#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1363/** @note Not for IOPL or IF testing. */
1364#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1365/** @note Not for IOPL or IF testing. */
1366#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1367/** @note Not for IOPL or IF testing. */
1368#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1369/** @note Not for IOPL or IF testing. */
1370#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1371 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1372 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1373/** @note Not for IOPL or IF testing. */
1374#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1375 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1376 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1377/** @note Not for IOPL or IF testing. */
1378#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1379 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1380 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1381 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1382/** @note Not for IOPL or IF testing. */
1383#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1384 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1385 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1386 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1387#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1388#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1389#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1390/** @note Not for IOPL or IF testing. */
1391#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1392 if ( pVCpu->cpum.GstCtx.cx != 0 \
1393 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1394/** @note Not for IOPL or IF testing. */
1395#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1396 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1397 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1398/** @note Not for IOPL or IF testing. */
1399#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1400 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1401 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1402/** @note Not for IOPL or IF testing. */
1403#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1404 if ( pVCpu->cpum.GstCtx.cx != 0 \
1405 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1406/** @note Not for IOPL or IF testing. */
1407#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1408 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1409 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1410/** @note Not for IOPL or IF testing. */
1411#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1412 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1413 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1414#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1415#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1416
1417#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1418 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1419#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1420 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1421#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1422 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1423#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1424 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1425#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1426 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1427#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1428 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1429#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1430 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1431#define IEM_MC_IF_FCW_IM() \
1432 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1433
1434#define IEM_MC_ELSE() } else {
1435#define IEM_MC_ENDIF() } do {} while (0)
1436
1437/** @} */
1438
1439#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1440
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