VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 97269

Last change on this file since 97269 was 97231, checked in by vboxsync, 3 years ago

VMM/CPUM: Define our own X86EFLAGS/X86RFLAGS structures so we can use reserved bits for internal state.
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1/* $Id: IEMMc.h 97231 2022-10-19 09:12:57Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44#define IEM_MC_PAUSE() do {} while (0)
45#define IEM_MC_CONTINUE() do {} while (0)
46
47/** Internal macro. */
48#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
49 do \
50 { \
51 VBOXSTRICTRC rcStrict2 = a_Expr; \
52 if (rcStrict2 != VINF_SUCCESS) \
53 return rcStrict2; \
54 } while (0)
55
56
57#define IEM_MC_ADVANCE_RIP() iemRegUpdateRipAndClearRF(pVCpu)
58#define IEM_MC_REL_JMP_S8(a_i8) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS8(pVCpu, a_i8))
59#define IEM_MC_REL_JMP_S16(a_i16) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS16(pVCpu, a_i16))
60#define IEM_MC_REL_JMP_S32(a_i32) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS32(pVCpu, a_i32))
61#define IEM_MC_SET_RIP_U16(a_u16NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u16NewIP)))
62#define IEM_MC_SET_RIP_U32(a_u32NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u32NewIP)))
63#define IEM_MC_SET_RIP_U64(a_u64NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u64NewIP)))
64#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
65#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
66 do { \
67 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
68 return iemRaiseDeviceNotAvailable(pVCpu); \
69 } while (0)
70#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
71 do { \
72 if ((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)) \
73 return iemRaiseDeviceNotAvailable(pVCpu); \
74 } while (0)
75#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
76 do { \
77 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
78 return iemRaiseMathFault(pVCpu); \
79 } while (0)
80#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
81 do { \
82 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
83 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
84 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx2) \
85 return iemRaiseUndefinedOpcode(pVCpu); \
86 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
87 return iemRaiseDeviceNotAvailable(pVCpu); \
88 } while (0)
89#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
90 do { \
91 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
92 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
93 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) \
94 return iemRaiseUndefinedOpcode(pVCpu); \
95 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
96 return iemRaiseDeviceNotAvailable(pVCpu); \
97 } while (0)
98#define IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT() \
99 do { \
100 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
101 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
102 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAesNi) \
103 return iemRaiseUndefinedOpcode(pVCpu); \
104 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
105 return iemRaiseDeviceNotAvailable(pVCpu); \
106 } while (0)
107#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
108 do { \
109 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
110 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
111 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42) \
112 return iemRaiseUndefinedOpcode(pVCpu); \
113 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
114 return iemRaiseDeviceNotAvailable(pVCpu); \
115 } while (0)
116#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
117 do { \
118 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
119 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
120 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse41) \
121 return iemRaiseUndefinedOpcode(pVCpu); \
122 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
123 return iemRaiseDeviceNotAvailable(pVCpu); \
124 } while (0)
125#define IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT() \
126 do { \
127 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
128 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
129 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3) \
130 return iemRaiseUndefinedOpcode(pVCpu); \
131 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
132 return iemRaiseDeviceNotAvailable(pVCpu); \
133 } while (0)
134#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
135 do { \
136 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
137 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
138 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse3) \
139 return iemRaiseUndefinedOpcode(pVCpu); \
140 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
141 return iemRaiseDeviceNotAvailable(pVCpu); \
142 } while (0)
143#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
144 do { \
145 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
146 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
147 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) \
148 return iemRaiseUndefinedOpcode(pVCpu); \
149 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
150 return iemRaiseDeviceNotAvailable(pVCpu); \
151 } while (0)
152#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
153 do { \
154 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
155 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
156 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) \
157 return iemRaiseUndefinedOpcode(pVCpu); \
158 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
159 return iemRaiseDeviceNotAvailable(pVCpu); \
160 } while (0)
161#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
162 do { \
163 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
164 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMmx) \
165 return iemRaiseUndefinedOpcode(pVCpu); \
166 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
167 return iemRaiseDeviceNotAvailable(pVCpu); \
168 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
169 return iemRaiseMathFault(pVCpu); \
170 } while (0)
171#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(a_fSupported) \
172 do { \
173 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
174 || !(a_fSupported)) \
175 return iemRaiseUndefinedOpcode(pVCpu); \
176 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
177 return iemRaiseDeviceNotAvailable(pVCpu); \
178 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
179 return iemRaiseMathFault(pVCpu); \
180 } while (0)
181#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() \
182 do { \
183 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
184 || ( !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse \
185 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAmdMmxExts) ) \
186 return iemRaiseUndefinedOpcode(pVCpu); \
187 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
188 return iemRaiseDeviceNotAvailable(pVCpu); \
189 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
190 return iemRaiseMathFault(pVCpu); \
191 } while (0)
192#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
193 do { \
194 if (pVCpu->iem.s.uCpl != 0) \
195 return iemRaiseGeneralProtectionFault0(pVCpu); \
196 } while (0)
197#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
198 do { \
199 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
200 else return iemRaiseGeneralProtectionFault0(pVCpu); \
201 } while (0)
202#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
203 do { \
204 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
205 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase \
206 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
207 return iemRaiseUndefinedOpcode(pVCpu); \
208 } while (0)
209#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
210 do { \
211 if (!IEM_IS_CANONICAL(a_u64Addr)) \
212 return iemRaiseGeneralProtectionFault0(pVCpu); \
213 } while (0)
214#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
215 do { \
216 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
217 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) \
218 { \
219 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
220 return iemRaiseSimdFpException(pVCpu); \
221 else \
222 return iemRaiseUndefinedOpcode(pVCpu); \
223 } \
224 } while (0)
225#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
226 do { \
227 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
228 return iemRaiseSimdFpException(pVCpu); \
229 else \
230 return iemRaiseUndefinedOpcode(pVCpu); \
231 } while (0)
232#define IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT() \
233 do { \
234 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
235 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
236 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPclMul) \
237 return iemRaiseUndefinedOpcode(pVCpu); \
238 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
239 return iemRaiseDeviceNotAvailable(pVCpu); \
240 } while (0)
241
242
243#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
244#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
245#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
246#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
247#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
248#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
249#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
250 uint32_t a_Name; \
251 uint32_t *a_pName = &a_Name
252#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
253 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
254
255#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
256#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
257
258#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
259#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
260#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
261#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
262#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
263#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
264#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
265#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
266#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
267#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
268#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
269#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
270#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
271#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
272#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
273#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
274#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
275#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
276 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
277 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
278 } while (0)
279#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
280 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
281 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
282 } while (0)
283#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
284 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
285 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
286 } while (0)
287/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
288#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
289 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
290 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
291 } while (0)
292#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
293 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
294 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
295 } while (0)
296/** @note Not for IOPL or IF testing or modification. */
297#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
298#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
299#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
300#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
301
302#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
303#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
304#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
305#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
306#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
307#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
308#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
309#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
310#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
311#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
312#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
313/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
314#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
315 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
316 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
317 } while (0)
318#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
319 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
320 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
321 } while (0)
322#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
323 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
324
325
326#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
327#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
328/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
329 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
330#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
331#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
332#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
333#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
334#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
335#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
336/** @note Not for IOPL or IF testing or modification.
337 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
338#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
339#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
340
341#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
342#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
343#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
344 do { \
345 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
346 *pu32Reg += (a_u32Value); \
347 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
348 } while (0)
349#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
350
351#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
352#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
353#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
354 do { \
355 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
356 *pu32Reg -= (a_u32Value); \
357 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
358 } while (0)
359#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
360#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
361
362#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
363#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
364#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
365#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
366#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
367#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
368#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
369
370#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
371#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
372#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
373#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
374
375#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
376#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
377#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
378
379#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
380#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
381#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
382
383#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
384#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
385#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
386
387#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
388#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
389#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
390
391#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
392
393#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
394
395#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
396#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
397#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
398 do { \
399 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
400 *pu32Reg &= (a_u32Value); \
401 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
402 } while (0)
403#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
404
405#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
406#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
407#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
408 do { \
409 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
410 *pu32Reg |= (a_u32Value); \
411 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
412 } while (0)
413#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
414
415
416/** @note Not for IOPL or IF modification. */
417#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
418/** @note Not for IOPL or IF modification. */
419#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
420/** @note Not for IOPL or IF modification. */
421#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
422
423#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
424
425/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
426#define IEM_MC_FPU_TO_MMX_MODE() do { \
427 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
428 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
429 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
430 } while (0)
431
432/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
433#define IEM_MC_FPU_FROM_MMX_MODE() do { \
434 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
435 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
436 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
437 } while (0)
438
439#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
440 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
441#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
442 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
443#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
444 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
445 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
446 } while (0)
447#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
448 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
449 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
450 } while (0)
451#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
452 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
453#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
454 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
455#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
456 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
457#define IEM_MC_MODIFIED_MREG(a_iMReg) \
458 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
459#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
460 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
461
462#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
463 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
464 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
465 } while (0)
466#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
467 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
468 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
469 } while (0)
470#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) \
471 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; } while (0)
472#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) \
473 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0]; } while (0)
474#define IEM_MC_FETCH_XREG_HI_U64(a_u64Value, a_iXReg) \
475 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; } while (0)
476#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
477 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
478 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
479 } while (0)
480#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
481 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
482 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
483 } while (0)
484#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
485 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
486#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
487 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
488#define IEM_MC_STORE_XREG_U64(a_iXReg, a_u64Value) \
489 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); } while (0)
490#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
491 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
492 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
493 } while (0)
494#define IEM_MC_STORE_XREG_U32(a_iXReg, a_u32Value) \
495 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = (a_u32Value); } while (0)
496#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
497 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
498#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
499 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
500#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
501 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
502 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
503 } while (0)
504#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
505 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
506#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
507 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
508#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
509 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
510#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
511 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
512#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
513 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
514#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
515 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
516#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
517 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
518#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
519 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
520#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
521 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
522 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
523 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
524 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
525 } while (0)
526
527#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
528 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
529 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
530 } while (0)
531#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
532 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
533 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
534 } while (0)
535#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
536 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
537 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
538 } while (0)
539#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
540 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
541 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
542 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
543 } while (0)
544#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
545 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
546 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
547 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
548 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
549 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
550 } while (0)
551
552#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
553#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
554 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
555 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
556 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
557 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
558 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
559 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
560 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
561 } while (0)
562#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
563 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
564 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
565 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
566 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
567 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
568 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
569 } while (0)
570#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
571 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
572 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
573 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
574 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
575 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
576 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
577 } while (0)
578#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
579 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
580 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
581 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
582 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
583 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
584 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
585 } while (0)
586
587#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
588 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
589#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
590 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
591#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
592 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
593#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
594 do { uintptr_t const iYRegTmp = (a_iYReg); \
595 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
596 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
597 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
598 } while (0)
599
600#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
601 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
602 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
603 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
604 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
605 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
606 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
607 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
608 } while (0)
609#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
610 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
611 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
612 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
613 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
614 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
615 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
616 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
617 } while (0)
618#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
619 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
620 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
621 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
622 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
623 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
624 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
625 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
626 } while (0)
627
628#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
629 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
630 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
631 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
632 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
633 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
634 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
635 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
636 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
637 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
638 } while (0)
639#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
640 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
641 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
642 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
643 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
644 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
645 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
646 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
647 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
648 } while (0)
649#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
650 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
651 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
652 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
653 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
654 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
655 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
656 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
657 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
658 } while (0)
659#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
660 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
661 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
662 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
663 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
664 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
665 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
666 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
667 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
668 } while (0)
669#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
670 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
671 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
672 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
673 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
674 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
675 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
676 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
677 } while (0)
678#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
679 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
680 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
681 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
682 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
683 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
684 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
685 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
686 } while (0)
687
688#ifndef IEM_WITH_SETJMP
689# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
690 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
691# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
692 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
693# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
694 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
695#else
696# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
697 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
698# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
699 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
700# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
701 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
702#endif
703
704#ifndef IEM_WITH_SETJMP
705# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
706 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
707# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
708 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
709# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
710 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
711#else
712# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
713 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
714# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
715 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
716# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
717 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
718#endif
719
720#ifndef IEM_WITH_SETJMP
721# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
722 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
723# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
724 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
725# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
726 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
727#else
728# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
729 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
730# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
731 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
732# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
733 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
734#endif
735
736#ifdef SOME_UNUSED_FUNCTION
737# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
738 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
739#endif
740
741#ifndef IEM_WITH_SETJMP
742# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
743 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
744# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
745 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
746# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
747 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
748# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
749 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
750#else
751# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
752 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
753# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
754 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
755# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
756 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
757# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
758 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
759#endif
760
761#ifndef IEM_WITH_SETJMP
762# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
763 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
764# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
765 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
766# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
767 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
768# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
769 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
770#else
771# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
772 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
773# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
774 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
775# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
776 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
777# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
778 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
779#endif
780
781#ifndef IEM_WITH_SETJMP
782# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
783 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
784# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
785 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
786# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
787 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
788
789# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
790 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
791# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
792 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
793# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
794 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
795# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
796 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
797# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
798 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
799#else
800# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
801 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
802# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
803 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
804# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
805 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
806
807# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
808 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
809# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
810 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
811# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
812 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
813# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
814 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
815# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
816 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
817#endif
818
819#ifndef IEM_WITH_SETJMP
820# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
821 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
822# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
823 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
824# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
825 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
826
827# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
828 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
829# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
830 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
831# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
832 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
833#else
834# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
835 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
836# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
837 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
838# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
839 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
840
841# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
842 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
843# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
844 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
845# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
846 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
847#endif
848
849
850
851#ifndef IEM_WITH_SETJMP
852# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
853 do { \
854 uint8_t u8Tmp; \
855 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
856 (a_u16Dst) = u8Tmp; \
857 } while (0)
858# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
859 do { \
860 uint8_t u8Tmp; \
861 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
862 (a_u32Dst) = u8Tmp; \
863 } while (0)
864# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
865 do { \
866 uint8_t u8Tmp; \
867 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
868 (a_u64Dst) = u8Tmp; \
869 } while (0)
870# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
871 do { \
872 uint16_t u16Tmp; \
873 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
874 (a_u32Dst) = u16Tmp; \
875 } while (0)
876# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
877 do { \
878 uint16_t u16Tmp; \
879 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
880 (a_u64Dst) = u16Tmp; \
881 } while (0)
882# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
883 do { \
884 uint32_t u32Tmp; \
885 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
886 (a_u64Dst) = u32Tmp; \
887 } while (0)
888#else /* IEM_WITH_SETJMP */
889# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
890 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
891# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
892 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
893# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
894 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
895# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
896 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
897# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
898 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
899# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
900 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
901#endif /* IEM_WITH_SETJMP */
902
903#ifndef IEM_WITH_SETJMP
904# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
905 do { \
906 uint8_t u8Tmp; \
907 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
908 (a_u16Dst) = (int8_t)u8Tmp; \
909 } while (0)
910# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
911 do { \
912 uint8_t u8Tmp; \
913 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
914 (a_u32Dst) = (int8_t)u8Tmp; \
915 } while (0)
916# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
917 do { \
918 uint8_t u8Tmp; \
919 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
920 (a_u64Dst) = (int8_t)u8Tmp; \
921 } while (0)
922# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
923 do { \
924 uint16_t u16Tmp; \
925 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
926 (a_u32Dst) = (int16_t)u16Tmp; \
927 } while (0)
928# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
929 do { \
930 uint16_t u16Tmp; \
931 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
932 (a_u64Dst) = (int16_t)u16Tmp; \
933 } while (0)
934# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
935 do { \
936 uint32_t u32Tmp; \
937 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
938 (a_u64Dst) = (int32_t)u32Tmp; \
939 } while (0)
940#else /* IEM_WITH_SETJMP */
941# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
942 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
943# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
944 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
945# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
946 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
947# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
948 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
949# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
950 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
951# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
952 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
953#endif /* IEM_WITH_SETJMP */
954
955#ifndef IEM_WITH_SETJMP
956# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
957 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
958# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
959 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
960# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
961 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
962# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
963 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
964#else
965# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
966 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
967# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
968 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
969# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
970 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
971# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
972 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
973#endif
974
975#ifndef IEM_WITH_SETJMP
976# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
977 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
978# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
979 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
980# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
981 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
982# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
983 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
984#else
985# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
986 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
987# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
988 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
989# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
990 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
991# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
992 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
993#endif
994
995#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
996#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
997#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
998#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
999#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
1000#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
1001#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
1002 do { \
1003 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1004 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
1005 } while (0)
1006#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
1007 do { \
1008 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1009 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
1010 } while (0)
1011
1012#ifndef IEM_WITH_SETJMP
1013# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1014 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1015# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1016 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1017#else
1018# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1019 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1020# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1021 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1022#endif
1023
1024#ifndef IEM_WITH_SETJMP
1025# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1026 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1027# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1028 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1029#else
1030# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1031 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1032# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1033 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1034#endif
1035
1036
1037#define IEM_MC_PUSH_U16(a_u16Value) \
1038 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1039#define IEM_MC_PUSH_U32(a_u32Value) \
1040 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1041#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
1042 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
1043#define IEM_MC_PUSH_U64(a_u64Value) \
1044 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1045
1046#define IEM_MC_POP_U16(a_pu16Value) \
1047 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1048#define IEM_MC_POP_U32(a_pu32Value) \
1049 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1050#define IEM_MC_POP_U64(a_pu64Value) \
1051 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1052
1053/** Maps guest memory for direct or bounce buffered access.
1054 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1055 * @remarks May return.
1056 */
1057#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1058 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1059 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1060
1061/** Maps guest memory for direct or bounce buffered access.
1062 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1063 * @remarks May return.
1064 */
1065#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1066 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1067 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1068
1069/** Commits the memory and unmaps the guest memory.
1070 * @remarks May return.
1071 */
1072#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1073 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1074
1075/** Commits the memory and unmaps the guest memory unless the FPU status word
1076 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1077 * that would cause FLD not to store.
1078 *
1079 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1080 * store, while \#P will not.
1081 *
1082 * @remarks May in theory return - for now.
1083 */
1084#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1085 do { \
1086 if ( !(a_u16FSW & X86_FSW_ES) \
1087 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1088 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1089 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1090 } while (0)
1091
1092/** Calculate efficient address from R/M. */
1093#ifndef IEM_WITH_SETJMP
1094# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1095 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1096#else
1097# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1098 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1099#endif
1100
1101#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1102#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1103#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1104#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1105#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1106#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1107#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1108
1109/**
1110 * Defers the rest of the instruction emulation to a C implementation routine
1111 * and returns, only taking the standard parameters.
1112 *
1113 * @param a_pfnCImpl The pointer to the C routine.
1114 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1115 */
1116#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1117
1118/**
1119 * Defers the rest of instruction emulation to a C implementation routine and
1120 * returns, taking one argument in addition to the standard ones.
1121 *
1122 * @param a_pfnCImpl The pointer to the C routine.
1123 * @param a0 The argument.
1124 */
1125#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1126
1127/**
1128 * Defers the rest of the instruction emulation to a C implementation routine
1129 * and returns, taking two arguments in addition to the standard ones.
1130 *
1131 * @param a_pfnCImpl The pointer to the C routine.
1132 * @param a0 The first extra argument.
1133 * @param a1 The second extra argument.
1134 */
1135#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1136
1137/**
1138 * Defers the rest of the instruction emulation to a C implementation routine
1139 * and returns, taking three arguments in addition to the standard ones.
1140 *
1141 * @param a_pfnCImpl The pointer to the C routine.
1142 * @param a0 The first extra argument.
1143 * @param a1 The second extra argument.
1144 * @param a2 The third extra argument.
1145 */
1146#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1147
1148/**
1149 * Defers the rest of the instruction emulation to a C implementation routine
1150 * and returns, taking four arguments in addition to the standard ones.
1151 *
1152 * @param a_pfnCImpl The pointer to the C routine.
1153 * @param a0 The first extra argument.
1154 * @param a1 The second extra argument.
1155 * @param a2 The third extra argument.
1156 * @param a3 The fourth extra argument.
1157 */
1158#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1159
1160/**
1161 * Defers the rest of the instruction emulation to a C implementation routine
1162 * and returns, taking two arguments in addition to the standard ones.
1163 *
1164 * @param a_pfnCImpl The pointer to the C routine.
1165 * @param a0 The first extra argument.
1166 * @param a1 The second extra argument.
1167 * @param a2 The third extra argument.
1168 * @param a3 The fourth extra argument.
1169 * @param a4 The fifth extra argument.
1170 */
1171#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1172
1173/**
1174 * Defers the entire instruction emulation to a C implementation routine and
1175 * returns, only taking the standard parameters.
1176 *
1177 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1178 *
1179 * @param a_pfnCImpl The pointer to the C routine.
1180 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1181 */
1182#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1183
1184/**
1185 * Defers the entire instruction emulation to a C implementation routine and
1186 * returns, taking one argument in addition to the standard ones.
1187 *
1188 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1189 *
1190 * @param a_pfnCImpl The pointer to the C routine.
1191 * @param a0 The argument.
1192 */
1193#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1194
1195/**
1196 * Defers the entire instruction emulation to a C implementation routine and
1197 * returns, taking two arguments in addition to the standard ones.
1198 *
1199 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1200 *
1201 * @param a_pfnCImpl The pointer to the C routine.
1202 * @param a0 The first extra argument.
1203 * @param a1 The second extra argument.
1204 */
1205#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1206
1207/**
1208 * Defers the entire instruction emulation to a C implementation routine and
1209 * returns, taking three arguments in addition to the standard ones.
1210 *
1211 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1212 *
1213 * @param a_pfnCImpl The pointer to the C routine.
1214 * @param a0 The first extra argument.
1215 * @param a1 The second extra argument.
1216 * @param a2 The third extra argument.
1217 */
1218#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1219
1220/**
1221 * Calls a FPU assembly implementation taking one visible argument.
1222 *
1223 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1224 * @param a0 The first extra argument.
1225 */
1226#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1227 do { \
1228 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1229 } while (0)
1230
1231/**
1232 * Calls a FPU assembly implementation taking two visible arguments.
1233 *
1234 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1235 * @param a0 The first extra argument.
1236 * @param a1 The second extra argument.
1237 */
1238#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1239 do { \
1240 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1241 } while (0)
1242
1243/**
1244 * Calls a FPU assembly implementation taking three visible arguments.
1245 *
1246 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1247 * @param a0 The first extra argument.
1248 * @param a1 The second extra argument.
1249 * @param a2 The third extra argument.
1250 */
1251#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1252 do { \
1253 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1254 } while (0)
1255
1256#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1257 do { \
1258 (a_FpuData).FSW = (a_FSW); \
1259 (a_FpuData).r80Result = *(a_pr80Value); \
1260 } while (0)
1261
1262/** Pushes FPU result onto the stack. */
1263#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1264 iemFpuPushResult(pVCpu, &a_FpuData)
1265/** Pushes FPU result onto the stack and sets the FPUDP. */
1266#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1267 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1268
1269/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1270#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1271 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1272
1273/** Stores FPU result in a stack register. */
1274#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1275 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1276/** Stores FPU result in a stack register and pops the stack. */
1277#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1278 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1279/** Stores FPU result in a stack register and sets the FPUDP. */
1280#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1281 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1282/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1283 * stack. */
1284#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1285 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1286
1287/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1288#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1289 iemFpuUpdateOpcodeAndIp(pVCpu)
1290/** Free a stack register (for FFREE and FFREEP). */
1291#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1292 iemFpuStackFree(pVCpu, a_iStReg)
1293/** Increment the FPU stack pointer. */
1294#define IEM_MC_FPU_STACK_INC_TOP() \
1295 iemFpuStackIncTop(pVCpu)
1296/** Decrement the FPU stack pointer. */
1297#define IEM_MC_FPU_STACK_DEC_TOP() \
1298 iemFpuStackDecTop(pVCpu)
1299
1300/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1301#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1302 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1303/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1304#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1305 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1306/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1307#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1308 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1309/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1310#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1311 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1312/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1313 * stack. */
1314#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1315 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1316/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1317#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1318 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1319
1320/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1321#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1322 iemFpuStackUnderflow(pVCpu, a_iStDst)
1323/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1324 * stack. */
1325#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1326 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1327/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1328 * FPUDS. */
1329#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1330 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1331/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1332 * FPUDS. Pops stack. */
1333#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1334 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1335/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1336 * stack twice. */
1337#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1338 iemFpuStackUnderflowThenPopPop(pVCpu)
1339/** Raises a FPU stack underflow exception for an instruction pushing a result
1340 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1341#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1342 iemFpuStackPushUnderflow(pVCpu)
1343/** Raises a FPU stack underflow exception for an instruction pushing a result
1344 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1345#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1346 iemFpuStackPushUnderflowTwo(pVCpu)
1347
1348/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1349 * FPUIP, FPUCS and FOP. */
1350#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1351 iemFpuStackPushOverflow(pVCpu)
1352/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1353 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1354#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1355 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1356/** Prepares for using the FPU state.
1357 * Ensures that we can use the host FPU in the current context (RC+R0.
1358 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1359#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1360/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1361#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1362/** Actualizes the guest FPU state so it can be accessed and modified. */
1363#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1364
1365/** Stores SSE SIMD result updating MXCSR. */
1366#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1367 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1368/** Updates MXCSR. */
1369#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1370 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1371
1372/** Prepares for using the SSE state.
1373 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1374 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1375#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1376/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1377#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1378/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1379#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1380
1381/** Prepares for using the AVX state.
1382 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1383 * Ensures the guest AVX state in the CPUMCTX is up to date.
1384 * @note This will include the AVX512 state too when support for it is added
1385 * due to the zero extending feature of VEX instruction. */
1386#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1387/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1388#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1389/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1390#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1391
1392/**
1393 * Calls a MMX assembly implementation taking two visible arguments.
1394 *
1395 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1396 * @param a0 The first extra argument.
1397 * @param a1 The second extra argument.
1398 */
1399#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1400 do { \
1401 IEM_MC_PREPARE_FPU_USAGE(); \
1402 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1403 } while (0)
1404
1405/**
1406 * Calls a MMX assembly implementation taking three visible arguments.
1407 *
1408 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1409 * @param a0 The first extra argument.
1410 * @param a1 The second extra argument.
1411 * @param a2 The third extra argument.
1412 */
1413#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1414 do { \
1415 IEM_MC_PREPARE_FPU_USAGE(); \
1416 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1417 } while (0)
1418
1419
1420/**
1421 * Calls a SSE assembly implementation taking two visible arguments.
1422 *
1423 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1424 * @param a0 The first extra argument.
1425 * @param a1 The second extra argument.
1426 */
1427#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1428 do { \
1429 IEM_MC_PREPARE_SSE_USAGE(); \
1430 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1431 } while (0)
1432
1433/**
1434 * Calls a SSE assembly implementation taking three visible arguments.
1435 *
1436 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1437 * @param a0 The first extra argument.
1438 * @param a1 The second extra argument.
1439 * @param a2 The third extra argument.
1440 */
1441#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1442 do { \
1443 IEM_MC_PREPARE_SSE_USAGE(); \
1444 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1445 } while (0)
1446
1447
1448/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1449 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1450#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1451 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1452
1453/**
1454 * Calls a AVX assembly implementation taking two visible arguments.
1455 *
1456 * There is one implicit zero'th argument, a pointer to the extended state.
1457 *
1458 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1459 * @param a1 The first extra argument.
1460 * @param a2 The second extra argument.
1461 */
1462#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1463 do { \
1464 IEM_MC_PREPARE_AVX_USAGE(); \
1465 a_pfnAImpl(pXState, (a1), (a2)); \
1466 } while (0)
1467
1468/**
1469 * Calls a AVX assembly implementation taking three visible arguments.
1470 *
1471 * There is one implicit zero'th argument, a pointer to the extended state.
1472 *
1473 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1474 * @param a1 The first extra argument.
1475 * @param a2 The second extra argument.
1476 * @param a3 The third extra argument.
1477 */
1478#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1479 do { \
1480 IEM_MC_PREPARE_AVX_USAGE(); \
1481 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1482 } while (0)
1483
1484/** @note Not for IOPL or IF testing. */
1485#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1486/** @note Not for IOPL or IF testing. */
1487#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1488/** @note Not for IOPL or IF testing. */
1489#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1490/** @note Not for IOPL or IF testing. */
1491#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1492/** @note Not for IOPL or IF testing. */
1493#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1494 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1495 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1496/** @note Not for IOPL or IF testing. */
1497#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1498 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1499 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1500/** @note Not for IOPL or IF testing. */
1501#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1502 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1503 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1504 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1505/** @note Not for IOPL or IF testing. */
1506#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1507 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1508 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1509 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1510#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1511#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1512#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1513/** @note Not for IOPL or IF testing. */
1514#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1515 if ( pVCpu->cpum.GstCtx.cx != 0 \
1516 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1517/** @note Not for IOPL or IF testing. */
1518#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1519 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1520 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1521/** @note Not for IOPL or IF testing. */
1522#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1523 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1524 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1525/** @note Not for IOPL or IF testing. */
1526#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1527 if ( pVCpu->cpum.GstCtx.cx != 0 \
1528 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1529/** @note Not for IOPL or IF testing. */
1530#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1531 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1532 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1533/** @note Not for IOPL or IF testing. */
1534#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1535 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1536 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1537#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1538#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1539
1540#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1541 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1542#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1543 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1544#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1545 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1546#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1547 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1548#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1549 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1550#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1551 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1552#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1553 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1554#define IEM_MC_IF_FCW_IM() \
1555 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1556#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1557 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1558 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1559
1560#define IEM_MC_ELSE() } else {
1561#define IEM_MC_ENDIF() } do {} while (0)
1562
1563/** @} */
1564
1565#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1566
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