VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 97357

Last change on this file since 97357 was 97357, checked in by vboxsync, 2 years ago

VMM/IEM: IEM_MC_REL_JMP_S* -> IEM_MC_REL_JMP_S*_AND_FINISH and IEM_MC_SET_RIP_U* -> IEM_MC_SET_RIP_U*_AND_FINISH in prep for TF and other #DB stuff. bugref:9898
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File size: 84.2 KB
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1/* $Id: IEMMc.h 97357 2022-10-31 22:47:43Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44
45/** Internal macro. */
46#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
47 do \
48 { \
49 VBOXSTRICTRC rcStrict2 = a_Expr; \
50 if (rcStrict2 != VINF_SUCCESS) \
51 return rcStrict2; \
52 } while (0)
53
54
55/** Advances RIP and finishes the instruction.
56 * This may include raising debug exceptions and such.
57 * @todo Make this be the return point, so we can get unreachable code erros
58 * if not the last MC statement. */
59#define IEM_MC_ADVANCE_RIP_AND_FINISH() iemRegUpdateRipAndClearRF(pVCpu)
60/** Tries to set RIP (may trigger \#GP) and finishes the instruction. */
61#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS8(pVCpu, a_i8))
62/** Tries to set RIP (may trigger \#GP) and finishes the instruction. */
63#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS16(pVCpu, a_i16))
64/** Tries to set RIP (may trigger \#GP) and finishes the instruction. */
65#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS32(pVCpu, a_i32))
66/** Tries to set RIP (may trigger \#GP) and finishes the instruction. */
67#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u16NewIP)))
68/** Tries to set RIP (may trigger \#GP) and finishes the instruction. */
69#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u32NewIP)))
70/** Tries to set RIP (may trigger \#GP) and finishes the instruction. */
71#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u64NewIP)))
72
73#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
74#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
75 do { \
76 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
77 return iemRaiseDeviceNotAvailable(pVCpu); \
78 } while (0)
79#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
80 do { \
81 if ((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)) \
82 return iemRaiseDeviceNotAvailable(pVCpu); \
83 } while (0)
84#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
85 do { \
86 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
87 return iemRaiseMathFault(pVCpu); \
88 } while (0)
89#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
90 do { \
91 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
92 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
93 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx2) \
94 return iemRaiseUndefinedOpcode(pVCpu); \
95 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
96 return iemRaiseDeviceNotAvailable(pVCpu); \
97 } while (0)
98#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
99 do { \
100 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
101 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
102 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) \
103 return iemRaiseUndefinedOpcode(pVCpu); \
104 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
105 return iemRaiseDeviceNotAvailable(pVCpu); \
106 } while (0)
107#define IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT() \
108 do { \
109 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
110 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
111 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAesNi) \
112 return iemRaiseUndefinedOpcode(pVCpu); \
113 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
114 return iemRaiseDeviceNotAvailable(pVCpu); \
115 } while (0)
116#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
117 do { \
118 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
119 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
120 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42) \
121 return iemRaiseUndefinedOpcode(pVCpu); \
122 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
123 return iemRaiseDeviceNotAvailable(pVCpu); \
124 } while (0)
125#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
126 do { \
127 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
128 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
129 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse41) \
130 return iemRaiseUndefinedOpcode(pVCpu); \
131 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
132 return iemRaiseDeviceNotAvailable(pVCpu); \
133 } while (0)
134#define IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT() \
135 do { \
136 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
137 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
138 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3) \
139 return iemRaiseUndefinedOpcode(pVCpu); \
140 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
141 return iemRaiseDeviceNotAvailable(pVCpu); \
142 } while (0)
143#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
144 do { \
145 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
146 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
147 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse3) \
148 return iemRaiseUndefinedOpcode(pVCpu); \
149 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
150 return iemRaiseDeviceNotAvailable(pVCpu); \
151 } while (0)
152#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
153 do { \
154 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
155 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
156 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) \
157 return iemRaiseUndefinedOpcode(pVCpu); \
158 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
159 return iemRaiseDeviceNotAvailable(pVCpu); \
160 } while (0)
161#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
162 do { \
163 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
164 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
165 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) \
166 return iemRaiseUndefinedOpcode(pVCpu); \
167 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
168 return iemRaiseDeviceNotAvailable(pVCpu); \
169 } while (0)
170#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
171 do { \
172 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
173 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMmx) \
174 return iemRaiseUndefinedOpcode(pVCpu); \
175 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
176 return iemRaiseDeviceNotAvailable(pVCpu); \
177 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
178 return iemRaiseMathFault(pVCpu); \
179 } while (0)
180#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(a_fSupported) \
181 do { \
182 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
183 || !(a_fSupported)) \
184 return iemRaiseUndefinedOpcode(pVCpu); \
185 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
186 return iemRaiseDeviceNotAvailable(pVCpu); \
187 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
188 return iemRaiseMathFault(pVCpu); \
189 } while (0)
190#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() \
191 do { \
192 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
193 || ( !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse \
194 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAmdMmxExts) ) \
195 return iemRaiseUndefinedOpcode(pVCpu); \
196 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
197 return iemRaiseDeviceNotAvailable(pVCpu); \
198 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
199 return iemRaiseMathFault(pVCpu); \
200 } while (0)
201#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
202 do { \
203 if (pVCpu->iem.s.uCpl != 0) \
204 return iemRaiseGeneralProtectionFault0(pVCpu); \
205 } while (0)
206#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
207 do { \
208 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
209 else return iemRaiseGeneralProtectionFault0(pVCpu); \
210 } while (0)
211#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
212 do { \
213 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
214 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase \
215 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
216 return iemRaiseUndefinedOpcode(pVCpu); \
217 } while (0)
218#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
219 do { \
220 if (!IEM_IS_CANONICAL(a_u64Addr)) \
221 return iemRaiseGeneralProtectionFault0(pVCpu); \
222 } while (0)
223#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
224 do { \
225 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
226 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) \
227 { \
228 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
229 return iemRaiseSimdFpException(pVCpu); \
230 else \
231 return iemRaiseUndefinedOpcode(pVCpu); \
232 } \
233 } while (0)
234#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
235 do { \
236 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
237 return iemRaiseSimdFpException(pVCpu); \
238 else \
239 return iemRaiseUndefinedOpcode(pVCpu); \
240 } while (0)
241#define IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT() \
242 do { \
243 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
244 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
245 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPclMul) \
246 return iemRaiseUndefinedOpcode(pVCpu); \
247 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
248 return iemRaiseDeviceNotAvailable(pVCpu); \
249 } while (0)
250
251
252#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
253#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
254#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
255#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
256#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
257#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
258#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
259 uint32_t a_Name; \
260 uint32_t *a_pName = &a_Name
261#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
262 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
263
264#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
265#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
266
267#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
268#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
269#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
270#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
271#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
272#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
273#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
274#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
275#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
276#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
277#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
278#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
279#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
280#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
281#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
282#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
283#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
284#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
285 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
286 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
287 } while (0)
288#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
289 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
290 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
291 } while (0)
292#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
293 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
294 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
295 } while (0)
296/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
297#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
298 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
299 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
300 } while (0)
301#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
302 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
303 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
304 } while (0)
305/** @note Not for IOPL or IF testing or modification. */
306#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
307#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
308#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
309#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
310
311#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
312#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
313#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
314#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
315#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
316#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
317#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
318#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
319#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
320#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
321#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
322/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
323#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
324 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
325 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
326 } while (0)
327#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
328 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
329 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
330 } while (0)
331#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
332 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
333
334
335#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
336#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
337/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
338 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
339#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
340#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
341#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
342#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
343#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
344#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
345/** @note Not for IOPL or IF testing or modification.
346 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
347#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
348#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
349
350#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
351#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
352#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
353 do { \
354 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
355 *pu32Reg += (a_u32Value); \
356 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
357 } while (0)
358#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
359
360#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
361#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
362#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
363 do { \
364 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
365 *pu32Reg -= (a_u32Value); \
366 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
367 } while (0)
368#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
369#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
370
371#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
372#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
373#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
374#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
375#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
376#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
377#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
378
379#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
380#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
381#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
382#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
383
384#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
385#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
386#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
387
388#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
389#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
390#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
391
392#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
393#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
394#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
395
396#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
397#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
398#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
399
400#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
401
402#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
403
404#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
405#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
406#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
407 do { \
408 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
409 *pu32Reg &= (a_u32Value); \
410 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
411 } while (0)
412#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
413
414#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
415#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
416#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
417 do { \
418 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
419 *pu32Reg |= (a_u32Value); \
420 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
421 } while (0)
422#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
423
424
425/** @note Not for IOPL or IF modification. */
426#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
427/** @note Not for IOPL or IF modification. */
428#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
429/** @note Not for IOPL or IF modification. */
430#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
431
432#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
433
434/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
435#define IEM_MC_FPU_TO_MMX_MODE() do { \
436 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
437 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
438 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
439 } while (0)
440
441/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
442#define IEM_MC_FPU_FROM_MMX_MODE() do { \
443 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
444 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
445 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
446 } while (0)
447
448#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
449 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
450#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
451 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
452#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
453 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
454 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
455 } while (0)
456#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
457 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
458 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
459 } while (0)
460#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
461 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
462#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
463 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
464#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
465 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
466#define IEM_MC_MODIFIED_MREG(a_iMReg) \
467 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
468#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
469 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
470
471#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
472 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
473 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
474 } while (0)
475#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
476 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
477 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
478 } while (0)
479#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) \
480 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; } while (0)
481#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) \
482 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0]; } while (0)
483#define IEM_MC_FETCH_XREG_HI_U64(a_u64Value, a_iXReg) \
484 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; } while (0)
485#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
486 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
487 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
488 } while (0)
489#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
490 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
491 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
492 } while (0)
493#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
494 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
495#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
496 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
497#define IEM_MC_STORE_XREG_U64(a_iXReg, a_u64Value) \
498 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); } while (0)
499#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
500 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
501 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
502 } while (0)
503#define IEM_MC_STORE_XREG_U32(a_iXReg, a_u32Value) \
504 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = (a_u32Value); } while (0)
505#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
506 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
507#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
508 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
509#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
510 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
511 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
512 } while (0)
513#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
514 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
515#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
516 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
517#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
518 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
519#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
520 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
521#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
522 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
523#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
524 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
525#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
526 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
527#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
528 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
529#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
530 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
531 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
532 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
533 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
534 } while (0)
535
536#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
537 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
538 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
539 } while (0)
540#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
541 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
542 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
543 } while (0)
544#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
545 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
546 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
547 } while (0)
548#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
549 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
550 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
551 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
552 } while (0)
553#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
554 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
555 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
556 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
557 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
558 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
559 } while (0)
560
561#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
562#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
563 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
564 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
565 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
566 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
567 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
568 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
569 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
570 } while (0)
571#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
572 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
573 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
574 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
575 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
576 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
577 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
578 } while (0)
579#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
580 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
581 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
582 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
583 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
584 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
585 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
586 } while (0)
587#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
588 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
589 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
590 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
591 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
592 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
593 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
594 } while (0)
595
596#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
597 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
598#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
599 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
600#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
601 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
602#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
603 do { uintptr_t const iYRegTmp = (a_iYReg); \
604 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
605 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
606 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
607 } while (0)
608
609#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
610 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
611 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
612 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
613 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
614 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
615 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
616 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
617 } while (0)
618#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
619 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
620 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
621 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
622 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
623 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
624 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
625 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
626 } while (0)
627#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
628 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
629 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
630 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
631 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
632 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
633 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
634 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
635 } while (0)
636
637#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
638 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
639 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
640 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
641 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
642 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
643 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
644 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
645 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
646 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
647 } while (0)
648#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
649 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
650 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
651 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
652 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
653 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
654 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
655 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
656 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
657 } while (0)
658#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
659 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
660 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
661 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
662 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
663 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
664 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
665 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
666 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
667 } while (0)
668#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
669 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
670 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
671 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
672 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
673 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
674 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
675 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
676 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
677 } while (0)
678#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
679 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
680 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
681 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
682 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
683 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
684 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
685 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
686 } while (0)
687#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
688 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
689 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
690 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
691 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
692 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
693 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
694 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
695 } while (0)
696
697#ifndef IEM_WITH_SETJMP
698# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
699 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
700# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
701 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
702# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
703 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
704#else
705# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
706 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
707# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
708 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
709# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
710 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
711#endif
712
713#ifndef IEM_WITH_SETJMP
714# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
715 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
716# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
717 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
718# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
719 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
720#else
721# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
722 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
723# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
724 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
725# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
726 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
727#endif
728
729#ifndef IEM_WITH_SETJMP
730# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
731 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
732# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
733 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
734# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
735 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
736#else
737# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
738 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
739# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
740 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
741# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
742 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
743#endif
744
745#ifdef SOME_UNUSED_FUNCTION
746# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
747 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
748#endif
749
750#ifndef IEM_WITH_SETJMP
751# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
752 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
753# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
754 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
755# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
756 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
757# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
758 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
759#else
760# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
761 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
762# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
763 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
764# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
765 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
766# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
767 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
768#endif
769
770#ifndef IEM_WITH_SETJMP
771# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
772 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
773# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
774 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
775# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
776 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
777# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
778 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
779#else
780# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
781 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
782# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
783 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
784# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
785 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
786# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
787 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
788#endif
789
790#ifndef IEM_WITH_SETJMP
791# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
792 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
793# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
794 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
795# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
796 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
797
798# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
799 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
800# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
801 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
802# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
803 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
804# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
805 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
806# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
807 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
808#else
809# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
810 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
811# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
812 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
813# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
814 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
815
816# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
817 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
818# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
819 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
820# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
821 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
822# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
823 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
824# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
825 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
826#endif
827
828#ifndef IEM_WITH_SETJMP
829# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
830 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
831# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
832 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
833# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
834 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
835
836# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
837 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
838# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
839 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
840# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
841 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
842#else
843# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
844 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
845# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
846 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
847# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
848 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
849
850# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
851 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
852# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
853 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
854# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
855 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
856#endif
857
858
859
860#ifndef IEM_WITH_SETJMP
861# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
862 do { \
863 uint8_t u8Tmp; \
864 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
865 (a_u16Dst) = u8Tmp; \
866 } while (0)
867# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
868 do { \
869 uint8_t u8Tmp; \
870 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
871 (a_u32Dst) = u8Tmp; \
872 } while (0)
873# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
874 do { \
875 uint8_t u8Tmp; \
876 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
877 (a_u64Dst) = u8Tmp; \
878 } while (0)
879# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
880 do { \
881 uint16_t u16Tmp; \
882 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
883 (a_u32Dst) = u16Tmp; \
884 } while (0)
885# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
886 do { \
887 uint16_t u16Tmp; \
888 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
889 (a_u64Dst) = u16Tmp; \
890 } while (0)
891# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
892 do { \
893 uint32_t u32Tmp; \
894 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
895 (a_u64Dst) = u32Tmp; \
896 } while (0)
897#else /* IEM_WITH_SETJMP */
898# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
899 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
900# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
901 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
902# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
903 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
904# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
905 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
906# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
907 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
908# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
909 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
910#endif /* IEM_WITH_SETJMP */
911
912#ifndef IEM_WITH_SETJMP
913# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
914 do { \
915 uint8_t u8Tmp; \
916 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
917 (a_u16Dst) = (int8_t)u8Tmp; \
918 } while (0)
919# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
920 do { \
921 uint8_t u8Tmp; \
922 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
923 (a_u32Dst) = (int8_t)u8Tmp; \
924 } while (0)
925# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
926 do { \
927 uint8_t u8Tmp; \
928 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
929 (a_u64Dst) = (int8_t)u8Tmp; \
930 } while (0)
931# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
932 do { \
933 uint16_t u16Tmp; \
934 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
935 (a_u32Dst) = (int16_t)u16Tmp; \
936 } while (0)
937# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
938 do { \
939 uint16_t u16Tmp; \
940 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
941 (a_u64Dst) = (int16_t)u16Tmp; \
942 } while (0)
943# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
944 do { \
945 uint32_t u32Tmp; \
946 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
947 (a_u64Dst) = (int32_t)u32Tmp; \
948 } while (0)
949#else /* IEM_WITH_SETJMP */
950# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
951 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
952# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
953 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
954# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
955 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
956# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
957 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
958# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
959 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
960# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
961 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
962#endif /* IEM_WITH_SETJMP */
963
964#ifndef IEM_WITH_SETJMP
965# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
966 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
967# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
968 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
969# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
970 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
971# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
972 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
973#else
974# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
975 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
976# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
977 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
978# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
979 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
980# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
981 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
982#endif
983
984#ifndef IEM_WITH_SETJMP
985# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
986 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
987# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
988 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
989# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
990 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
991# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
992 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
993#else
994# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
995 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
996# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
997 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
998# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
999 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
1000# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1001 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
1002#endif
1003
1004#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
1005#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
1006#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
1007#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
1008#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
1009#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
1010#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
1011 do { \
1012 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1013 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
1014 } while (0)
1015#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
1016 do { \
1017 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1018 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
1019 } while (0)
1020
1021#ifndef IEM_WITH_SETJMP
1022# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1023 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1024# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1025 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1026#else
1027# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1028 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1029# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1030 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1031#endif
1032
1033#ifndef IEM_WITH_SETJMP
1034# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1035 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1036# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1037 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1038#else
1039# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1040 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1041# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1042 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1043#endif
1044
1045
1046#define IEM_MC_PUSH_U16(a_u16Value) \
1047 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1048#define IEM_MC_PUSH_U32(a_u32Value) \
1049 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1050#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
1051 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
1052#define IEM_MC_PUSH_U64(a_u64Value) \
1053 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1054
1055#define IEM_MC_POP_U16(a_pu16Value) \
1056 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1057#define IEM_MC_POP_U32(a_pu32Value) \
1058 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1059#define IEM_MC_POP_U64(a_pu64Value) \
1060 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1061
1062/** Maps guest memory for direct or bounce buffered access.
1063 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1064 * @remarks May return.
1065 */
1066#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1067 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1068 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1069
1070/** Maps guest memory for direct or bounce buffered access.
1071 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1072 * @remarks May return.
1073 */
1074#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1075 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1076 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1077
1078/** Commits the memory and unmaps the guest memory.
1079 * @remarks May return.
1080 */
1081#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1082 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1083
1084/** Commits the memory and unmaps the guest memory unless the FPU status word
1085 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1086 * that would cause FLD not to store.
1087 *
1088 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1089 * store, while \#P will not.
1090 *
1091 * @remarks May in theory return - for now.
1092 */
1093#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1094 do { \
1095 if ( !(a_u16FSW & X86_FSW_ES) \
1096 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1097 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1098 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1099 } while (0)
1100
1101/** Calculate efficient address from R/M. */
1102#ifndef IEM_WITH_SETJMP
1103# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1104 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1105#else
1106# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1107 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1108#endif
1109
1110#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1111#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1112#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1113#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1114#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1115#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1116#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1117
1118/**
1119 * Defers the rest of the instruction emulation to a C implementation routine
1120 * and returns, only taking the standard parameters.
1121 *
1122 * @param a_pfnCImpl The pointer to the C routine.
1123 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1124 */
1125#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1126
1127/**
1128 * Defers the rest of instruction emulation to a C implementation routine and
1129 * returns, taking one argument in addition to the standard ones.
1130 *
1131 * @param a_pfnCImpl The pointer to the C routine.
1132 * @param a0 The argument.
1133 */
1134#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1135
1136/**
1137 * Defers the rest of the instruction emulation to a C implementation routine
1138 * and returns, taking two arguments in addition to the standard ones.
1139 *
1140 * @param a_pfnCImpl The pointer to the C routine.
1141 * @param a0 The first extra argument.
1142 * @param a1 The second extra argument.
1143 */
1144#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1145
1146/**
1147 * Defers the rest of the instruction emulation to a C implementation routine
1148 * and returns, taking three arguments in addition to the standard ones.
1149 *
1150 * @param a_pfnCImpl The pointer to the C routine.
1151 * @param a0 The first extra argument.
1152 * @param a1 The second extra argument.
1153 * @param a2 The third extra argument.
1154 */
1155#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1156
1157/**
1158 * Defers the rest of the instruction emulation to a C implementation routine
1159 * and returns, taking four arguments in addition to the standard ones.
1160 *
1161 * @param a_pfnCImpl The pointer to the C routine.
1162 * @param a0 The first extra argument.
1163 * @param a1 The second extra argument.
1164 * @param a2 The third extra argument.
1165 * @param a3 The fourth extra argument.
1166 */
1167#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1168
1169/**
1170 * Defers the rest of the instruction emulation to a C implementation routine
1171 * and returns, taking two arguments in addition to the standard ones.
1172 *
1173 * @param a_pfnCImpl The pointer to the C routine.
1174 * @param a0 The first extra argument.
1175 * @param a1 The second extra argument.
1176 * @param a2 The third extra argument.
1177 * @param a3 The fourth extra argument.
1178 * @param a4 The fifth extra argument.
1179 */
1180#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1181
1182/**
1183 * Defers the entire instruction emulation to a C implementation routine and
1184 * returns, only taking the standard parameters.
1185 *
1186 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1187 *
1188 * @param a_pfnCImpl The pointer to the C routine.
1189 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1190 */
1191#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1192
1193/**
1194 * Defers the entire instruction emulation to a C implementation routine and
1195 * returns, taking one argument in addition to the standard ones.
1196 *
1197 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1198 *
1199 * @param a_pfnCImpl The pointer to the C routine.
1200 * @param a0 The argument.
1201 */
1202#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1203
1204/**
1205 * Defers the entire instruction emulation to a C implementation routine and
1206 * returns, taking two arguments in addition to the standard ones.
1207 *
1208 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1209 *
1210 * @param a_pfnCImpl The pointer to the C routine.
1211 * @param a0 The first extra argument.
1212 * @param a1 The second extra argument.
1213 */
1214#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1215
1216/**
1217 * Defers the entire instruction emulation to a C implementation routine and
1218 * returns, taking three arguments in addition to the standard ones.
1219 *
1220 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1221 *
1222 * @param a_pfnCImpl The pointer to the C routine.
1223 * @param a0 The first extra argument.
1224 * @param a1 The second extra argument.
1225 * @param a2 The third extra argument.
1226 */
1227#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1228
1229/**
1230 * Calls a FPU assembly implementation taking one visible argument.
1231 *
1232 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1233 * @param a0 The first extra argument.
1234 */
1235#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1236 do { \
1237 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1238 } while (0)
1239
1240/**
1241 * Calls a FPU assembly implementation taking two visible arguments.
1242 *
1243 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1244 * @param a0 The first extra argument.
1245 * @param a1 The second extra argument.
1246 */
1247#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1248 do { \
1249 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1250 } while (0)
1251
1252/**
1253 * Calls a FPU assembly implementation taking three visible arguments.
1254 *
1255 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1256 * @param a0 The first extra argument.
1257 * @param a1 The second extra argument.
1258 * @param a2 The third extra argument.
1259 */
1260#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1261 do { \
1262 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1263 } while (0)
1264
1265#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1266 do { \
1267 (a_FpuData).FSW = (a_FSW); \
1268 (a_FpuData).r80Result = *(a_pr80Value); \
1269 } while (0)
1270
1271/** Pushes FPU result onto the stack. */
1272#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1273 iemFpuPushResult(pVCpu, &a_FpuData)
1274/** Pushes FPU result onto the stack and sets the FPUDP. */
1275#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1276 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1277
1278/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1279#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1280 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1281
1282/** Stores FPU result in a stack register. */
1283#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1284 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1285/** Stores FPU result in a stack register and pops the stack. */
1286#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1287 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1288/** Stores FPU result in a stack register and sets the FPUDP. */
1289#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1290 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1291/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1292 * stack. */
1293#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1294 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1295
1296/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1297#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1298 iemFpuUpdateOpcodeAndIp(pVCpu)
1299/** Free a stack register (for FFREE and FFREEP). */
1300#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1301 iemFpuStackFree(pVCpu, a_iStReg)
1302/** Increment the FPU stack pointer. */
1303#define IEM_MC_FPU_STACK_INC_TOP() \
1304 iemFpuStackIncTop(pVCpu)
1305/** Decrement the FPU stack pointer. */
1306#define IEM_MC_FPU_STACK_DEC_TOP() \
1307 iemFpuStackDecTop(pVCpu)
1308
1309/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1310#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1311 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1312/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1313#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1314 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1315/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1316#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1317 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1318/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1319#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1320 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1321/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1322 * stack. */
1323#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1324 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1325/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1326#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1327 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1328
1329/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1330#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1331 iemFpuStackUnderflow(pVCpu, a_iStDst)
1332/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1333 * stack. */
1334#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1335 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1336/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1337 * FPUDS. */
1338#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1339 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1340/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1341 * FPUDS. Pops stack. */
1342#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1343 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1344/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1345 * stack twice. */
1346#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1347 iemFpuStackUnderflowThenPopPop(pVCpu)
1348/** Raises a FPU stack underflow exception for an instruction pushing a result
1349 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1350#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1351 iemFpuStackPushUnderflow(pVCpu)
1352/** Raises a FPU stack underflow exception for an instruction pushing a result
1353 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1354#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1355 iemFpuStackPushUnderflowTwo(pVCpu)
1356
1357/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1358 * FPUIP, FPUCS and FOP. */
1359#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1360 iemFpuStackPushOverflow(pVCpu)
1361/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1362 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1363#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1364 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1365/** Prepares for using the FPU state.
1366 * Ensures that we can use the host FPU in the current context (RC+R0.
1367 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1368#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1369/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1370#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1371/** Actualizes the guest FPU state so it can be accessed and modified. */
1372#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1373
1374/** Stores SSE SIMD result updating MXCSR. */
1375#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1376 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1377/** Updates MXCSR. */
1378#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1379 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1380
1381/** Prepares for using the SSE state.
1382 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1383 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1384#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1385/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1386#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1387/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1388#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1389
1390/** Prepares for using the AVX state.
1391 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1392 * Ensures the guest AVX state in the CPUMCTX is up to date.
1393 * @note This will include the AVX512 state too when support for it is added
1394 * due to the zero extending feature of VEX instruction. */
1395#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1396/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1397#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1398/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1399#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1400
1401/**
1402 * Calls a MMX assembly implementation taking two visible arguments.
1403 *
1404 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1405 * @param a0 The first extra argument.
1406 * @param a1 The second extra argument.
1407 */
1408#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1409 do { \
1410 IEM_MC_PREPARE_FPU_USAGE(); \
1411 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1412 } while (0)
1413
1414/**
1415 * Calls a MMX assembly implementation taking three visible arguments.
1416 *
1417 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1418 * @param a0 The first extra argument.
1419 * @param a1 The second extra argument.
1420 * @param a2 The third extra argument.
1421 */
1422#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1423 do { \
1424 IEM_MC_PREPARE_FPU_USAGE(); \
1425 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1426 } while (0)
1427
1428
1429/**
1430 * Calls a SSE assembly implementation taking two visible arguments.
1431 *
1432 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1433 * @param a0 The first extra argument.
1434 * @param a1 The second extra argument.
1435 */
1436#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1437 do { \
1438 IEM_MC_PREPARE_SSE_USAGE(); \
1439 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1440 } while (0)
1441
1442/**
1443 * Calls a SSE assembly implementation taking three visible arguments.
1444 *
1445 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1446 * @param a0 The first extra argument.
1447 * @param a1 The second extra argument.
1448 * @param a2 The third extra argument.
1449 */
1450#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1451 do { \
1452 IEM_MC_PREPARE_SSE_USAGE(); \
1453 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1454 } while (0)
1455
1456
1457/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1458 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1459#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1460 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1461
1462/**
1463 * Calls a AVX assembly implementation taking two visible arguments.
1464 *
1465 * There is one implicit zero'th argument, a pointer to the extended state.
1466 *
1467 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1468 * @param a1 The first extra argument.
1469 * @param a2 The second extra argument.
1470 */
1471#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1472 do { \
1473 IEM_MC_PREPARE_AVX_USAGE(); \
1474 a_pfnAImpl(pXState, (a1), (a2)); \
1475 } while (0)
1476
1477/**
1478 * Calls a AVX assembly implementation taking three visible arguments.
1479 *
1480 * There is one implicit zero'th argument, a pointer to the extended state.
1481 *
1482 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1483 * @param a1 The first extra argument.
1484 * @param a2 The second extra argument.
1485 * @param a3 The third extra argument.
1486 */
1487#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1488 do { \
1489 IEM_MC_PREPARE_AVX_USAGE(); \
1490 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1491 } while (0)
1492
1493/** @note Not for IOPL or IF testing. */
1494#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1495/** @note Not for IOPL or IF testing. */
1496#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1497/** @note Not for IOPL or IF testing. */
1498#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1499/** @note Not for IOPL or IF testing. */
1500#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1501/** @note Not for IOPL or IF testing. */
1502#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1503 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1504 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1505/** @note Not for IOPL or IF testing. */
1506#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1507 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1508 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1509/** @note Not for IOPL or IF testing. */
1510#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1511 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1512 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1513 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1514/** @note Not for IOPL or IF testing. */
1515#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1516 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1517 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1518 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1519#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1520#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1521#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1522/** @note Not for IOPL or IF testing. */
1523#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1524 if ( pVCpu->cpum.GstCtx.cx != 0 \
1525 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1526/** @note Not for IOPL or IF testing. */
1527#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1528 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1529 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1530/** @note Not for IOPL or IF testing. */
1531#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1532 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1533 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1534/** @note Not for IOPL or IF testing. */
1535#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1536 if ( pVCpu->cpum.GstCtx.cx != 0 \
1537 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1538/** @note Not for IOPL or IF testing. */
1539#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1540 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1541 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1542/** @note Not for IOPL or IF testing. */
1543#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1544 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1545 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1546#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1547#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1548
1549#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1550 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1551#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1552 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1553#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1554 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1555#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1556 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1557#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1558 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1559#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1560 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1561#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1562 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1563#define IEM_MC_IF_FCW_IM() \
1564 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1565#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1566 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1567 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1568
1569#define IEM_MC_ELSE() } else {
1570#define IEM_MC_ENDIF() } do {} while (0)
1571
1572/** @} */
1573
1574#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1575
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