VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 97534

Last change on this file since 97534 was 97534, checked in by vboxsync, 2 years ago

IEM: Reworked [V]MOVxDUP to be done directly in microcode. Added MOVBE instruction.
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File size: 84.9 KB
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1/* $Id: IEMMc.h 97534 2022-11-14 16:55:57Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44
45/** Internal macro. */
46#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
47 do \
48 { \
49 VBOXSTRICTRC rcStrict2 = a_Expr; \
50 if (rcStrict2 != VINF_SUCCESS) \
51 return rcStrict2; \
52 } while (0)
53
54
55/** Advances RIP, finishes the instruction and returns.
56 * This may include raising debug exceptions and such. */
57#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
58/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
59#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
60 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
61/** Sets RIP (may trigger \#GP), finishes the instruction and returns.
62 * @note only usable in 16-bit op size mode. */
63#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
64 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
65/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
66#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
67 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
68/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
69#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJumpU16AndFinishClearningRF((pVCpu), (a_u16NewIP))
70/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
71#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJumpU32AndFinishClearningRF((pVCpu), (a_u32NewIP))
72/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
73#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJumpU64AndFinishClearningRF((pVCpu), (a_u64NewIP))
74
75#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
76#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
77 do { \
78 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
79 return iemRaiseDeviceNotAvailable(pVCpu); \
80 } while (0)
81#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
82 do { \
83 if ((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)) \
84 return iemRaiseDeviceNotAvailable(pVCpu); \
85 } while (0)
86#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
87 do { \
88 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
89 return iemRaiseMathFault(pVCpu); \
90 } while (0)
91#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
92 do { \
93 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
94 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
95 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx2) \
96 return iemRaiseUndefinedOpcode(pVCpu); \
97 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
98 return iemRaiseDeviceNotAvailable(pVCpu); \
99 } while (0)
100#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
101 do { \
102 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
103 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
104 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) \
105 return iemRaiseUndefinedOpcode(pVCpu); \
106 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
107 return iemRaiseDeviceNotAvailable(pVCpu); \
108 } while (0)
109#define IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT() \
110 do { \
111 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
112 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
113 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAesNi) \
114 return iemRaiseUndefinedOpcode(pVCpu); \
115 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
116 return iemRaiseDeviceNotAvailable(pVCpu); \
117 } while (0)
118#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
119 do { \
120 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
121 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
122 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42) \
123 return iemRaiseUndefinedOpcode(pVCpu); \
124 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
125 return iemRaiseDeviceNotAvailable(pVCpu); \
126 } while (0)
127#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
128 do { \
129 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
130 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
131 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse41) \
132 return iemRaiseUndefinedOpcode(pVCpu); \
133 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
134 return iemRaiseDeviceNotAvailable(pVCpu); \
135 } while (0)
136#define IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT() \
137 do { \
138 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
139 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
140 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3) \
141 return iemRaiseUndefinedOpcode(pVCpu); \
142 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
143 return iemRaiseDeviceNotAvailable(pVCpu); \
144 } while (0)
145#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
146 do { \
147 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
148 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
149 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse3) \
150 return iemRaiseUndefinedOpcode(pVCpu); \
151 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
152 return iemRaiseDeviceNotAvailable(pVCpu); \
153 } while (0)
154#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
155 do { \
156 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
157 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
158 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) \
159 return iemRaiseUndefinedOpcode(pVCpu); \
160 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
161 return iemRaiseDeviceNotAvailable(pVCpu); \
162 } while (0)
163#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
164 do { \
165 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
166 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
167 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) \
168 return iemRaiseUndefinedOpcode(pVCpu); \
169 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
170 return iemRaiseDeviceNotAvailable(pVCpu); \
171 } while (0)
172#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
173 do { \
174 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
175 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMmx) \
176 return iemRaiseUndefinedOpcode(pVCpu); \
177 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
178 return iemRaiseDeviceNotAvailable(pVCpu); \
179 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
180 return iemRaiseMathFault(pVCpu); \
181 } while (0)
182#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(a_fSupported) \
183 do { \
184 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
185 || !(a_fSupported)) \
186 return iemRaiseUndefinedOpcode(pVCpu); \
187 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
188 return iemRaiseDeviceNotAvailable(pVCpu); \
189 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
190 return iemRaiseMathFault(pVCpu); \
191 } while (0)
192#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() \
193 do { \
194 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
195 || ( !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse \
196 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAmdMmxExts) ) \
197 return iemRaiseUndefinedOpcode(pVCpu); \
198 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
199 return iemRaiseDeviceNotAvailable(pVCpu); \
200 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
201 return iemRaiseMathFault(pVCpu); \
202 } while (0)
203#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
204 do { \
205 if (pVCpu->iem.s.uCpl != 0) \
206 return iemRaiseGeneralProtectionFault0(pVCpu); \
207 } while (0)
208#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
209 do { \
210 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
211 else return iemRaiseGeneralProtectionFault0(pVCpu); \
212 } while (0)
213#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
214 do { \
215 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
216 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase \
217 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
218 return iemRaiseUndefinedOpcode(pVCpu); \
219 } while (0)
220#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
221 do { \
222 if (!IEM_IS_CANONICAL(a_u64Addr)) \
223 return iemRaiseGeneralProtectionFault0(pVCpu); \
224 } while (0)
225#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
226 do { \
227 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
228 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) \
229 { \
230 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
231 return iemRaiseSimdFpException(pVCpu); \
232 else \
233 return iemRaiseUndefinedOpcode(pVCpu); \
234 } \
235 } while (0)
236#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
237 do { \
238 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
239 return iemRaiseSimdFpException(pVCpu); \
240 else \
241 return iemRaiseUndefinedOpcode(pVCpu); \
242 } while (0)
243#define IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT() \
244 do { \
245 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
246 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
247 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPclMul) \
248 return iemRaiseUndefinedOpcode(pVCpu); \
249 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
250 return iemRaiseDeviceNotAvailable(pVCpu); \
251 } while (0)
252
253
254#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
255#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
256#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
257#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
258#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
259#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
260#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
261 uint32_t a_Name; \
262 uint32_t *a_pName = &a_Name
263#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
264 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
265
266#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
267#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
268
269#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
270#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
271#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
272#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
273#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
274#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
275#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
276#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
277#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
278#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
279#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
280#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
281#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
282#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
283#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
284#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
285#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
286#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
287 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
288 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
289 } while (0)
290#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
291 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
292 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
293 } while (0)
294#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
295 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
296 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
297 } while (0)
298/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
299#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
300 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
301 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
302 } while (0)
303#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
304 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
305 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
306 } while (0)
307/** @note Not for IOPL or IF testing or modification. */
308#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
309#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
310#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
311#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
312
313#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
314#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
315#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
316#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
317#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
318#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
319#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
320#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
321#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
322#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
323#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
324/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
325#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
326 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
327 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
328 } while (0)
329#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
330 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
331 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
332 } while (0)
333#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
334 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
335
336
337#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
338#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
339/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
340 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
341#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
342#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
343#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
344#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
345#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
346#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
347/** @note Not for IOPL or IF testing or modification.
348 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
349#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
350#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
351
352#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
353#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
354#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
355 do { \
356 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
357 *pu32Reg += (a_u32Value); \
358 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
359 } while (0)
360#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
361
362#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
363#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
364#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
365 do { \
366 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
367 *pu32Reg -= (a_u32Value); \
368 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
369 } while (0)
370#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
371#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
372
373#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
374#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
375#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
376#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
377#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
378#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
379#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
380
381#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
382#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
383#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
384#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
385
386#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
387#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
388#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
389
390#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
391#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
392#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
393
394#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
395#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
396#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
397
398#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
399#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
400#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
401
402#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
403
404#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
405
406#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
407#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
408#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
409 do { \
410 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
411 *pu32Reg &= (a_u32Value); \
412 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
413 } while (0)
414#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
415
416#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
417#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
418#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
419 do { \
420 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
421 *pu32Reg |= (a_u32Value); \
422 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
423 } while (0)
424#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
425
426#define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) (a_u16Local) = RT_BSWAP_U16((a_u16Local));
427#define IEM_MC_BSWAP_LOCAL_U32(a_u32Local) (a_u32Local) = RT_BSWAP_U32((a_u32Local));
428#define IEM_MC_BSWAP_LOCAL_U64(a_u64Local) (a_u64Local) = RT_BSWAP_U64((a_u64Local));
429
430/** @note Not for IOPL or IF modification. */
431#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
432/** @note Not for IOPL or IF modification. */
433#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
434/** @note Not for IOPL or IF modification. */
435#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
436
437#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
438
439/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
440#define IEM_MC_FPU_TO_MMX_MODE() do { \
441 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
442 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
443 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
444 } while (0)
445
446/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
447#define IEM_MC_FPU_FROM_MMX_MODE() do { \
448 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
449 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
450 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
451 } while (0)
452
453#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
454 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
455#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
456 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
457#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
458 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
459 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
460 } while (0)
461#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
462 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
463 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
464 } while (0)
465#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
466 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
467#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
468 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
469#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
470 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
471#define IEM_MC_MODIFIED_MREG(a_iMReg) \
472 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
473#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
474 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
475
476#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
477 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
478 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
479 } while (0)
480#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
481 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
482 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
483 } while (0)
484#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) \
485 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; } while (0)
486#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) \
487 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0]; } while (0)
488#define IEM_MC_FETCH_XREG_HI_U64(a_u64Value, a_iXReg) \
489 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; } while (0)
490#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
491 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
492 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
493 } while (0)
494#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
495 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
496 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
497 } while (0)
498#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
499 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
500#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
501 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
502#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) \
503 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_u64Value); } while (0)
504#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
505 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
506 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
507 } while (0)
508#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) \
509 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_u32Value); } while (0)
510#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) \
511 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDwDst)] = (a_u128Value).au32[(a_iDwSrc)]; } while (0)
512#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
513 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
514#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
515 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
516#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
517 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
518 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
519 } while (0)
520#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
521 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
522#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
523 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
524#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
525 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
526#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
527 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
528#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
529 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
530#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
531 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
532#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
533 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
534#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
535 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
536#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
537 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
538 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
539 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
540 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
541 } while (0)
542
543#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
544 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
545 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
546 } while (0)
547#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
548 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
549 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
550 } while (0)
551#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
552 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
553 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
554 } while (0)
555#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
556 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
557 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
558 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
559 } while (0)
560#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
561 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
562 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
563 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
564 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
565 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
566 } while (0)
567
568#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
569#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
570 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
571 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
572 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
573 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
574 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
575 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
576 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
577 } while (0)
578#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
579 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
580 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
581 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
582 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
583 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
584 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
585 } while (0)
586#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
587 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
588 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
589 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
590 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
591 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
592 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
593 } while (0)
594#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
595 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
596 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
597 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
598 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
599 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
600 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
601 } while (0)
602
603#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
604 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
605#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
606 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
607#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
608 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
609#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
610 do { uintptr_t const iYRegTmp = (a_iYReg); \
611 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
612 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
613 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
614 } while (0)
615
616#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
617 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
618 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
619 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
620 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
621 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
622 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
623 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
624 } while (0)
625#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
626 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
627 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
628 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
629 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
630 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
631 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
632 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
633 } while (0)
634#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
635 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
636 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
637 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
638 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
639 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
640 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
641 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
642 } while (0)
643
644#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
645 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
646 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
647 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
648 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
649 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
650 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
651 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
652 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
653 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
654 } while (0)
655#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
656 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
657 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
658 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
659 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
660 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
661 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
662 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
663 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
664 } while (0)
665#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
666 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
667 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
668 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
669 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
670 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
671 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
672 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
673 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
674 } while (0)
675#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
676 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
677 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
678 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
679 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
680 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
681 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
682 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
683 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
684 } while (0)
685#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
686 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
687 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
688 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
689 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
690 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
691 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
692 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
693 } while (0)
694#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
695 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
696 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
697 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
698 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
699 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
700 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
701 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
702 } while (0)
703
704#ifndef IEM_WITH_SETJMP
705# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
706 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
707# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
708 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
709# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
710 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
711#else
712# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
713 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
714# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
715 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
716# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
717 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
718#endif
719
720#ifndef IEM_WITH_SETJMP
721# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
722 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
723# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
724 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
725# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
726 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
727#else
728# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
729 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
730# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
731 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
732# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
733 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
734#endif
735
736#ifndef IEM_WITH_SETJMP
737# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
738 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
739# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
740 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
741# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
742 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
743#else
744# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
745 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
746# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
747 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
748# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
749 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
750#endif
751
752#ifdef SOME_UNUSED_FUNCTION
753# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
754 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
755#endif
756
757#ifndef IEM_WITH_SETJMP
758# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
759 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
760# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
761 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
762# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
763 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
764# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
765 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
766#else
767# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
768 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
769# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
770 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
771# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
772 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
773# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
774 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
775#endif
776
777#ifndef IEM_WITH_SETJMP
778# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
779 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
780# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
781 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
782# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
783 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
784# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
785 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
786#else
787# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
788 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
789# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
790 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
791# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
792 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
793# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
794 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
795#endif
796
797#ifndef IEM_WITH_SETJMP
798# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
799 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
800# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
801 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
802# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
803 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
804
805# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
806 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
807# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
808 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
809# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
810 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
811# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
812 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
813# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
814 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
815#else
816# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
817 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
818# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
819 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
820# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
821 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
822
823# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
824 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
825# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
826 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
827# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
828 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
829# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
830 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
831# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
832 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
833#endif
834
835#ifndef IEM_WITH_SETJMP
836# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
837 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
838# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
839 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
840# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
841 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
842
843# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
844 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
845# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
846 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
847# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
848 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
849#else
850# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
851 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
852# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
853 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
854# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
855 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
856
857# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
858 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
859# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
860 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
861# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
862 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
863#endif
864
865
866
867#ifndef IEM_WITH_SETJMP
868# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
869 do { \
870 uint8_t u8Tmp; \
871 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
872 (a_u16Dst) = u8Tmp; \
873 } while (0)
874# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
875 do { \
876 uint8_t u8Tmp; \
877 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
878 (a_u32Dst) = u8Tmp; \
879 } while (0)
880# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
881 do { \
882 uint8_t u8Tmp; \
883 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
884 (a_u64Dst) = u8Tmp; \
885 } while (0)
886# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
887 do { \
888 uint16_t u16Tmp; \
889 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
890 (a_u32Dst) = u16Tmp; \
891 } while (0)
892# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
893 do { \
894 uint16_t u16Tmp; \
895 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
896 (a_u64Dst) = u16Tmp; \
897 } while (0)
898# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
899 do { \
900 uint32_t u32Tmp; \
901 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
902 (a_u64Dst) = u32Tmp; \
903 } while (0)
904#else /* IEM_WITH_SETJMP */
905# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
906 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
907# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
908 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
909# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
910 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
911# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
912 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
913# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
914 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
915# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
916 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
917#endif /* IEM_WITH_SETJMP */
918
919#ifndef IEM_WITH_SETJMP
920# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
921 do { \
922 uint8_t u8Tmp; \
923 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
924 (a_u16Dst) = (int8_t)u8Tmp; \
925 } while (0)
926# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
927 do { \
928 uint8_t u8Tmp; \
929 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
930 (a_u32Dst) = (int8_t)u8Tmp; \
931 } while (0)
932# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
933 do { \
934 uint8_t u8Tmp; \
935 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
936 (a_u64Dst) = (int8_t)u8Tmp; \
937 } while (0)
938# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
939 do { \
940 uint16_t u16Tmp; \
941 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
942 (a_u32Dst) = (int16_t)u16Tmp; \
943 } while (0)
944# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
945 do { \
946 uint16_t u16Tmp; \
947 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
948 (a_u64Dst) = (int16_t)u16Tmp; \
949 } while (0)
950# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
951 do { \
952 uint32_t u32Tmp; \
953 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
954 (a_u64Dst) = (int32_t)u32Tmp; \
955 } while (0)
956#else /* IEM_WITH_SETJMP */
957# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
958 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
959# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
960 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
961# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
962 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
963# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
964 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
965# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
966 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
967# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
968 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
969#endif /* IEM_WITH_SETJMP */
970
971#ifndef IEM_WITH_SETJMP
972# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
973 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
974# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
975 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
976# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
977 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
978# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
979 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
980#else
981# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
982 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
983# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
984 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
985# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
986 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
987# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
988 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
989#endif
990
991#ifndef IEM_WITH_SETJMP
992# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
993 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
994# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
995 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
996# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
997 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
998# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
999 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
1000#else
1001# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
1002 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
1003# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
1004 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
1005# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
1006 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
1007# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1008 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
1009#endif
1010
1011#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
1012#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
1013#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
1014#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
1015#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
1016#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
1017#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
1018 do { \
1019 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1020 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
1021 } while (0)
1022#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
1023 do { \
1024 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1025 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
1026 } while (0)
1027
1028#ifndef IEM_WITH_SETJMP
1029# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1030 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1031# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1032 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1033#else
1034# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1035 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1036# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1037 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1038#endif
1039
1040#ifndef IEM_WITH_SETJMP
1041# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1042 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1043# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1044 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1045#else
1046# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1047 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1048# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1049 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1050#endif
1051
1052
1053#define IEM_MC_PUSH_U16(a_u16Value) \
1054 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1055#define IEM_MC_PUSH_U32(a_u32Value) \
1056 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1057#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
1058 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
1059#define IEM_MC_PUSH_U64(a_u64Value) \
1060 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1061
1062#define IEM_MC_POP_U16(a_pu16Value) \
1063 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1064#define IEM_MC_POP_U32(a_pu32Value) \
1065 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1066#define IEM_MC_POP_U64(a_pu64Value) \
1067 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1068
1069/** Maps guest memory for direct or bounce buffered access.
1070 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1071 * @remarks May return.
1072 */
1073#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1074 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1075 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1076
1077/** Maps guest memory for direct or bounce buffered access.
1078 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1079 * @remarks May return.
1080 */
1081#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1082 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1083 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1084
1085/** Commits the memory and unmaps the guest memory.
1086 * @remarks May return.
1087 */
1088#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1089 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1090
1091/** Commits the memory and unmaps the guest memory unless the FPU status word
1092 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1093 * that would cause FLD not to store.
1094 *
1095 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1096 * store, while \#P will not.
1097 *
1098 * @remarks May in theory return - for now.
1099 */
1100#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1101 do { \
1102 if ( !(a_u16FSW & X86_FSW_ES) \
1103 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1104 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1105 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1106 } while (0)
1107
1108/** Calculate efficient address from R/M. */
1109#ifndef IEM_WITH_SETJMP
1110# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1111 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1112#else
1113# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1114 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1115#endif
1116
1117#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1118#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1119#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1120#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1121#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1122#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1123#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1124
1125/**
1126 * Defers the rest of the instruction emulation to a C implementation routine
1127 * and returns, only taking the standard parameters.
1128 *
1129 * @param a_pfnCImpl The pointer to the C routine.
1130 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1131 */
1132#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1133
1134/**
1135 * Defers the rest of instruction emulation to a C implementation routine and
1136 * returns, taking one argument in addition to the standard ones.
1137 *
1138 * @param a_pfnCImpl The pointer to the C routine.
1139 * @param a0 The argument.
1140 */
1141#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1142
1143/**
1144 * Defers the rest of the instruction emulation to a C implementation routine
1145 * and returns, taking two arguments in addition to the standard ones.
1146 *
1147 * @param a_pfnCImpl The pointer to the C routine.
1148 * @param a0 The first extra argument.
1149 * @param a1 The second extra argument.
1150 */
1151#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1152
1153/**
1154 * Defers the rest of the instruction emulation to a C implementation routine
1155 * and returns, taking three arguments in addition to the standard ones.
1156 *
1157 * @param a_pfnCImpl The pointer to the C routine.
1158 * @param a0 The first extra argument.
1159 * @param a1 The second extra argument.
1160 * @param a2 The third extra argument.
1161 */
1162#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1163
1164/**
1165 * Defers the rest of the instruction emulation to a C implementation routine
1166 * and returns, taking four arguments in addition to the standard ones.
1167 *
1168 * @param a_pfnCImpl The pointer to the C routine.
1169 * @param a0 The first extra argument.
1170 * @param a1 The second extra argument.
1171 * @param a2 The third extra argument.
1172 * @param a3 The fourth extra argument.
1173 */
1174#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1175
1176/**
1177 * Defers the rest of the instruction emulation to a C implementation routine
1178 * and returns, taking two arguments in addition to the standard ones.
1179 *
1180 * @param a_pfnCImpl The pointer to the C routine.
1181 * @param a0 The first extra argument.
1182 * @param a1 The second extra argument.
1183 * @param a2 The third extra argument.
1184 * @param a3 The fourth extra argument.
1185 * @param a4 The fifth extra argument.
1186 */
1187#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1188
1189/**
1190 * Defers the entire instruction emulation to a C implementation routine and
1191 * returns, only taking the standard parameters.
1192 *
1193 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1194 *
1195 * @param a_pfnCImpl The pointer to the C routine.
1196 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1197 */
1198#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1199
1200/**
1201 * Defers the entire instruction emulation to a C implementation routine and
1202 * returns, taking one argument in addition to the standard ones.
1203 *
1204 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1205 *
1206 * @param a_pfnCImpl The pointer to the C routine.
1207 * @param a0 The argument.
1208 */
1209#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1210
1211/**
1212 * Defers the entire instruction emulation to a C implementation routine and
1213 * returns, taking two arguments in addition to the standard ones.
1214 *
1215 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1216 *
1217 * @param a_pfnCImpl The pointer to the C routine.
1218 * @param a0 The first extra argument.
1219 * @param a1 The second extra argument.
1220 */
1221#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1222
1223/**
1224 * Defers the entire instruction emulation to a C implementation routine and
1225 * returns, taking three arguments in addition to the standard ones.
1226 *
1227 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1228 *
1229 * @param a_pfnCImpl The pointer to the C routine.
1230 * @param a0 The first extra argument.
1231 * @param a1 The second extra argument.
1232 * @param a2 The third extra argument.
1233 */
1234#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1235
1236/**
1237 * Calls a FPU assembly implementation taking one visible argument.
1238 *
1239 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1240 * @param a0 The first extra argument.
1241 */
1242#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1243 do { \
1244 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1245 } while (0)
1246
1247/**
1248 * Calls a FPU assembly implementation taking two visible arguments.
1249 *
1250 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1251 * @param a0 The first extra argument.
1252 * @param a1 The second extra argument.
1253 */
1254#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1255 do { \
1256 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1257 } while (0)
1258
1259/**
1260 * Calls a FPU assembly implementation taking three visible arguments.
1261 *
1262 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1263 * @param a0 The first extra argument.
1264 * @param a1 The second extra argument.
1265 * @param a2 The third extra argument.
1266 */
1267#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1268 do { \
1269 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1270 } while (0)
1271
1272#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1273 do { \
1274 (a_FpuData).FSW = (a_FSW); \
1275 (a_FpuData).r80Result = *(a_pr80Value); \
1276 } while (0)
1277
1278/** Pushes FPU result onto the stack. */
1279#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1280 iemFpuPushResult(pVCpu, &a_FpuData)
1281/** Pushes FPU result onto the stack and sets the FPUDP. */
1282#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1283 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1284
1285/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1286#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1287 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1288
1289/** Stores FPU result in a stack register. */
1290#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1291 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1292/** Stores FPU result in a stack register and pops the stack. */
1293#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1294 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1295/** Stores FPU result in a stack register and sets the FPUDP. */
1296#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1297 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1298/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1299 * stack. */
1300#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1301 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1302
1303/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1304#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1305 iemFpuUpdateOpcodeAndIp(pVCpu)
1306/** Free a stack register (for FFREE and FFREEP). */
1307#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1308 iemFpuStackFree(pVCpu, a_iStReg)
1309/** Increment the FPU stack pointer. */
1310#define IEM_MC_FPU_STACK_INC_TOP() \
1311 iemFpuStackIncTop(pVCpu)
1312/** Decrement the FPU stack pointer. */
1313#define IEM_MC_FPU_STACK_DEC_TOP() \
1314 iemFpuStackDecTop(pVCpu)
1315
1316/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1317#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1318 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1319/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1320#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1321 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1322/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1323#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1324 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1325/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1326#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1327 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1328/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1329 * stack. */
1330#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1331 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1332/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1333#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1334 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1335
1336/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1337#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1338 iemFpuStackUnderflow(pVCpu, a_iStDst)
1339/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1340 * stack. */
1341#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1342 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1343/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1344 * FPUDS. */
1345#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1346 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1347/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1348 * FPUDS. Pops stack. */
1349#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1350 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1351/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1352 * stack twice. */
1353#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1354 iemFpuStackUnderflowThenPopPop(pVCpu)
1355/** Raises a FPU stack underflow exception for an instruction pushing a result
1356 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1357#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1358 iemFpuStackPushUnderflow(pVCpu)
1359/** Raises a FPU stack underflow exception for an instruction pushing a result
1360 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1361#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1362 iemFpuStackPushUnderflowTwo(pVCpu)
1363
1364/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1365 * FPUIP, FPUCS and FOP. */
1366#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1367 iemFpuStackPushOverflow(pVCpu)
1368/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1369 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1370#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1371 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1372/** Prepares for using the FPU state.
1373 * Ensures that we can use the host FPU in the current context (RC+R0.
1374 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1375#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1376/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1377#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1378/** Actualizes the guest FPU state so it can be accessed and modified. */
1379#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1380
1381/** Stores SSE SIMD result updating MXCSR. */
1382#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1383 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1384/** Updates MXCSR. */
1385#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1386 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1387
1388/** Prepares for using the SSE state.
1389 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1390 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1391#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1392/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1393#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1394/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1395#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1396
1397/** Prepares for using the AVX state.
1398 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1399 * Ensures the guest AVX state in the CPUMCTX is up to date.
1400 * @note This will include the AVX512 state too when support for it is added
1401 * due to the zero extending feature of VEX instruction. */
1402#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1403/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1404#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1405/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1406#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1407
1408/**
1409 * Calls a MMX assembly implementation taking two visible arguments.
1410 *
1411 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1412 * @param a0 The first extra argument.
1413 * @param a1 The second extra argument.
1414 */
1415#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1416 do { \
1417 IEM_MC_PREPARE_FPU_USAGE(); \
1418 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1419 } while (0)
1420
1421/**
1422 * Calls a MMX assembly implementation taking three visible arguments.
1423 *
1424 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1425 * @param a0 The first extra argument.
1426 * @param a1 The second extra argument.
1427 * @param a2 The third extra argument.
1428 */
1429#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1430 do { \
1431 IEM_MC_PREPARE_FPU_USAGE(); \
1432 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1433 } while (0)
1434
1435
1436/**
1437 * Calls a SSE assembly implementation taking two visible arguments.
1438 *
1439 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1440 * @param a0 The first extra argument.
1441 * @param a1 The second extra argument.
1442 */
1443#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1444 do { \
1445 IEM_MC_PREPARE_SSE_USAGE(); \
1446 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1447 } while (0)
1448
1449/**
1450 * Calls a SSE assembly implementation taking three visible arguments.
1451 *
1452 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1453 * @param a0 The first extra argument.
1454 * @param a1 The second extra argument.
1455 * @param a2 The third extra argument.
1456 */
1457#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1458 do { \
1459 IEM_MC_PREPARE_SSE_USAGE(); \
1460 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1461 } while (0)
1462
1463
1464/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1465 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1466#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1467 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1468
1469/**
1470 * Calls a AVX assembly implementation taking two visible arguments.
1471 *
1472 * There is one implicit zero'th argument, a pointer to the extended state.
1473 *
1474 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1475 * @param a1 The first extra argument.
1476 * @param a2 The second extra argument.
1477 */
1478#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1479 do { \
1480 IEM_MC_PREPARE_AVX_USAGE(); \
1481 a_pfnAImpl(pXState, (a1), (a2)); \
1482 } while (0)
1483
1484/**
1485 * Calls a AVX assembly implementation taking three visible arguments.
1486 *
1487 * There is one implicit zero'th argument, a pointer to the extended state.
1488 *
1489 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1490 * @param a1 The first extra argument.
1491 * @param a2 The second extra argument.
1492 * @param a3 The third extra argument.
1493 */
1494#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1495 do { \
1496 IEM_MC_PREPARE_AVX_USAGE(); \
1497 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1498 } while (0)
1499
1500/** @note Not for IOPL or IF testing. */
1501#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1502/** @note Not for IOPL or IF testing. */
1503#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1504/** @note Not for IOPL or IF testing. */
1505#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1506/** @note Not for IOPL or IF testing. */
1507#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1508/** @note Not for IOPL or IF testing. */
1509#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1510 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1511 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1512/** @note Not for IOPL or IF testing. */
1513#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1514 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1515 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1516/** @note Not for IOPL or IF testing. */
1517#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1518 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1519 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1520 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1521/** @note Not for IOPL or IF testing. */
1522#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1523 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1524 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1525 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1526#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1527#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1528#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1529/** @note Not for IOPL or IF testing. */
1530#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1531 if ( pVCpu->cpum.GstCtx.cx != 0 \
1532 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1533/** @note Not for IOPL or IF testing. */
1534#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1535 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1536 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1537/** @note Not for IOPL or IF testing. */
1538#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1539 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1540 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1541/** @note Not for IOPL or IF testing. */
1542#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1543 if ( pVCpu->cpum.GstCtx.cx != 0 \
1544 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1545/** @note Not for IOPL or IF testing. */
1546#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1547 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1548 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1549/** @note Not for IOPL or IF testing. */
1550#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1551 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1552 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1553#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1554#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1555
1556#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1557 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1558#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1559 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1560#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1561 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1562#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1563 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1564#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1565 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1566#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1567 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1568#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1569 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1570#define IEM_MC_IF_FCW_IM() \
1571 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1572#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1573 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1574 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1575
1576#define IEM_MC_ELSE() } else {
1577#define IEM_MC_ENDIF() } do {} while (0)
1578
1579/** @} */
1580
1581#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1582
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