VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 97607

Last change on this file since 97607 was 97607, checked in by vboxsync, 2 years ago

IEM: Added SSE 4.1 PINSRB, PEXTRB, PEXTRB, PEXTRW, EXTRACTPS.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 85.4 KB
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1/* $Id: IEMMc.h 97607 2022-11-18 10:58:11Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44
45/** Internal macro. */
46#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
47 do \
48 { \
49 VBOXSTRICTRC rcStrict2 = a_Expr; \
50 if (rcStrict2 != VINF_SUCCESS) \
51 return rcStrict2; \
52 } while (0)
53
54
55/** Advances RIP, finishes the instruction and returns.
56 * This may include raising debug exceptions and such. */
57#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
58/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
59#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
60 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
61/** Sets RIP (may trigger \#GP), finishes the instruction and returns.
62 * @note only usable in 16-bit op size mode. */
63#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
64 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
65/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
66#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
67 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
68/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
69#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJumpU16AndFinishClearningRF((pVCpu), (a_u16NewIP))
70/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
71#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJumpU32AndFinishClearningRF((pVCpu), (a_u32NewIP))
72/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
73#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJumpU64AndFinishClearningRF((pVCpu), (a_u64NewIP))
74
75#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
76#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
77 do { \
78 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
79 return iemRaiseDeviceNotAvailable(pVCpu); \
80 } while (0)
81#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
82 do { \
83 if ((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)) \
84 return iemRaiseDeviceNotAvailable(pVCpu); \
85 } while (0)
86#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
87 do { \
88 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
89 return iemRaiseMathFault(pVCpu); \
90 } while (0)
91#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
92 do { \
93 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
94 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
95 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx2) \
96 return iemRaiseUndefinedOpcode(pVCpu); \
97 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
98 return iemRaiseDeviceNotAvailable(pVCpu); \
99 } while (0)
100#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
101 do { \
102 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
103 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
104 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) \
105 return iemRaiseUndefinedOpcode(pVCpu); \
106 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
107 return iemRaiseDeviceNotAvailable(pVCpu); \
108 } while (0)
109#define IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT() \
110 do { \
111 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
112 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
113 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAesNi) \
114 return iemRaiseUndefinedOpcode(pVCpu); \
115 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
116 return iemRaiseDeviceNotAvailable(pVCpu); \
117 } while (0)
118#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
119 do { \
120 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
121 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
122 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42) \
123 return iemRaiseUndefinedOpcode(pVCpu); \
124 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
125 return iemRaiseDeviceNotAvailable(pVCpu); \
126 } while (0)
127#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
128 do { \
129 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
130 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
131 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse41) \
132 return iemRaiseUndefinedOpcode(pVCpu); \
133 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
134 return iemRaiseDeviceNotAvailable(pVCpu); \
135 } while (0)
136#define IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT() \
137 do { \
138 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
139 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
140 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3) \
141 return iemRaiseUndefinedOpcode(pVCpu); \
142 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
143 return iemRaiseDeviceNotAvailable(pVCpu); \
144 } while (0)
145#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
146 do { \
147 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
148 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
149 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse3) \
150 return iemRaiseUndefinedOpcode(pVCpu); \
151 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
152 return iemRaiseDeviceNotAvailable(pVCpu); \
153 } while (0)
154#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
155 do { \
156 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
157 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
158 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) \
159 return iemRaiseUndefinedOpcode(pVCpu); \
160 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
161 return iemRaiseDeviceNotAvailable(pVCpu); \
162 } while (0)
163#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
164 do { \
165 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
166 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
167 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) \
168 return iemRaiseUndefinedOpcode(pVCpu); \
169 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
170 return iemRaiseDeviceNotAvailable(pVCpu); \
171 } while (0)
172#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
173 do { \
174 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
175 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMmx) \
176 return iemRaiseUndefinedOpcode(pVCpu); \
177 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
178 return iemRaiseDeviceNotAvailable(pVCpu); \
179 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
180 return iemRaiseMathFault(pVCpu); \
181 } while (0)
182#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(a_fSupported) \
183 do { \
184 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
185 || !(a_fSupported)) \
186 return iemRaiseUndefinedOpcode(pVCpu); \
187 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
188 return iemRaiseDeviceNotAvailable(pVCpu); \
189 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
190 return iemRaiseMathFault(pVCpu); \
191 } while (0)
192#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() \
193 do { \
194 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
195 || ( !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse \
196 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAmdMmxExts) ) \
197 return iemRaiseUndefinedOpcode(pVCpu); \
198 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
199 return iemRaiseDeviceNotAvailable(pVCpu); \
200 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
201 return iemRaiseMathFault(pVCpu); \
202 } while (0)
203#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
204 do { \
205 if (pVCpu->iem.s.uCpl != 0) \
206 return iemRaiseGeneralProtectionFault0(pVCpu); \
207 } while (0)
208#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
209 do { \
210 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
211 else return iemRaiseGeneralProtectionFault0(pVCpu); \
212 } while (0)
213#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
214 do { \
215 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
216 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase \
217 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
218 return iemRaiseUndefinedOpcode(pVCpu); \
219 } while (0)
220#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
221 do { \
222 if (!IEM_IS_CANONICAL(a_u64Addr)) \
223 return iemRaiseGeneralProtectionFault0(pVCpu); \
224 } while (0)
225#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
226 do { \
227 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
228 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) \
229 { \
230 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
231 return iemRaiseSimdFpException(pVCpu); \
232 else \
233 return iemRaiseUndefinedOpcode(pVCpu); \
234 } \
235 } while (0)
236#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
237 do { \
238 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
239 return iemRaiseSimdFpException(pVCpu); \
240 else \
241 return iemRaiseUndefinedOpcode(pVCpu); \
242 } while (0)
243#define IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT() \
244 do { \
245 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
246 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
247 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPclMul) \
248 return iemRaiseUndefinedOpcode(pVCpu); \
249 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
250 return iemRaiseDeviceNotAvailable(pVCpu); \
251 } while (0)
252
253
254#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
255#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
256#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
257#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
258#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
259#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
260#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
261 uint32_t a_Name; \
262 uint32_t *a_pName = &a_Name
263#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
264 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
265
266#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
267#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
268
269#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
270#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
271#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
272#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
273#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
274#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
275#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
276#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
277#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
278#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
279#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
280#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
281#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
282#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
283#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
284#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
285#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
286#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
287 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
288 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
289 } while (0)
290#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
291 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
292 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
293 } while (0)
294#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
295 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
296 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
297 } while (0)
298/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
299#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
300 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
301 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
302 } while (0)
303#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
304 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
305 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
306 } while (0)
307/** @note Not for IOPL or IF testing or modification. */
308#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
309#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
310#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
311#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
312
313#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
314#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
315#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
316#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
317#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
318#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
319#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
320#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
321#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
322#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
323#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
324/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
325#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
326 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
327 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
328 } while (0)
329#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
330 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
331 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
332 } while (0)
333#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
334 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
335
336
337#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
338#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
339/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
340 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
341#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
342#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
343#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
344#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
345#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
346#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
347/** @note Not for IOPL or IF testing or modification.
348 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
349#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
350#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
351
352#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
353#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
354#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
355 do { \
356 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
357 *pu32Reg += (a_u32Value); \
358 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
359 } while (0)
360#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
361
362#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
363#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
364#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
365 do { \
366 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
367 *pu32Reg -= (a_u32Value); \
368 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
369 } while (0)
370#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
371#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
372
373#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
374#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
375#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
376#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
377#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
378#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
379#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
380
381#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
382#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
383#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
384#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
385
386#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
387#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
388#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
389
390#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
391#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
392#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
393
394#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
395#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
396#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
397
398#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
399#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
400#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
401
402#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
403
404#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
405
406#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
407#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
408#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
409 do { \
410 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
411 *pu32Reg &= (a_u32Value); \
412 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
413 } while (0)
414#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
415
416#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
417#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
418#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
419 do { \
420 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
421 *pu32Reg |= (a_u32Value); \
422 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
423 } while (0)
424#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
425
426#define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) (a_u16Local) = RT_BSWAP_U16((a_u16Local));
427#define IEM_MC_BSWAP_LOCAL_U32(a_u32Local) (a_u32Local) = RT_BSWAP_U32((a_u32Local));
428#define IEM_MC_BSWAP_LOCAL_U64(a_u64Local) (a_u64Local) = RT_BSWAP_U64((a_u64Local));
429
430/** @note Not for IOPL or IF modification. */
431#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
432/** @note Not for IOPL or IF modification. */
433#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
434/** @note Not for IOPL or IF modification. */
435#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
436
437#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
438
439/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
440#define IEM_MC_FPU_TO_MMX_MODE() do { \
441 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
442 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
443 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
444 } while (0)
445
446/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
447#define IEM_MC_FPU_FROM_MMX_MODE() do { \
448 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
449 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
450 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
451 } while (0)
452
453#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
454 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
455#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
456 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
457#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
458 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
459 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
460 } while (0)
461#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
462 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
463 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
464 } while (0)
465#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
466 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
467#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
468 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
469#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
470 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
471#define IEM_MC_MODIFIED_MREG(a_iMReg) \
472 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
473#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
474 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
475
476#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
477 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
478 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
479 } while (0)
480#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
481 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
482 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
483 } while (0)
484#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) \
485 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQWord)]; } while (0)
486#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg, a_iDWord) \
487 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDWord)]; } while (0)
488#define IEM_MC_FETCH_XREG_U16(a_u16Value, a_iXReg, a_iWord) \
489 do { (a_u16Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iWord)]; } while (0)
490#define IEM_MC_FETCH_XREG_U8( a_u8Value, a_iXReg, a_iByte) \
491 do { (a_u8Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iByte)]; } while (0)
492#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
493 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
494 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
495 } while (0)
496#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
497 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
498 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
499 } while (0)
500#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
501 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
502#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
503 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
504#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) \
505 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_u64Value); } while (0)
506#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) \
507 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_u32Value); } while (0)
508#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u16Value) \
509 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iWord)] = (a_u16Value); } while (0)
510#define IEM_MC_STORE_XREG_U8(a_iXReg, a_iByte, a_u8Value) \
511 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iByte)] = (a_u8Value); } while (0)
512
513#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
514 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
515 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
516 } while (0)
517
518#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) \
519 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDwDst)] = (a_u128Value).au32[(a_iDwSrc)]; } while (0)
520#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
521 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
522#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
523 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
524#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
525 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
526 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
527 } while (0)
528#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
529 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
530#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
531 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
532#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
533 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
534#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
535 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
536#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
537 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
538#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
539 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
540#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
541 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
542#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
543 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
544#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
545 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
546 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
547 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
548 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
549 } while (0)
550
551#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
552 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
553 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
554 } while (0)
555#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
556 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
557 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
558 } while (0)
559#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
560 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
561 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
562 } while (0)
563#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
564 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
565 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
566 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
567 } while (0)
568#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
569 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
570 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
571 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
572 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
573 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
574 } while (0)
575
576#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
577#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
578 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
579 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
580 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
581 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
582 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
583 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
584 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
585 } while (0)
586#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
587 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
588 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
589 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
590 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
591 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
592 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
593 } while (0)
594#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
595 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
596 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
597 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
598 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
599 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
600 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
601 } while (0)
602#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
603 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
604 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
605 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
606 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
607 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
608 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
609 } while (0)
610
611#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
612 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
613#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
614 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
615#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
616 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
617#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
618 do { uintptr_t const iYRegTmp = (a_iYReg); \
619 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
620 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
621 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
622 } while (0)
623
624#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
625 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
626 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
627 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
628 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
629 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
630 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
631 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
632 } while (0)
633#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
634 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
635 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
636 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
637 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
638 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
639 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
640 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
641 } while (0)
642#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
643 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
644 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
645 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
646 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
647 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
648 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
649 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
650 } while (0)
651
652#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
653 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
654 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
655 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
656 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
657 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
658 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
659 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
660 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
661 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
662 } while (0)
663#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
664 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
665 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
666 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
667 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
668 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
669 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
670 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
671 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
672 } while (0)
673#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
674 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
675 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
676 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
677 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
678 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
679 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
680 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
681 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
682 } while (0)
683#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
684 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
685 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
686 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
687 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
688 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
689 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
690 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
691 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
692 } while (0)
693#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
694 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
695 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
696 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
697 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
698 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
699 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
700 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
701 } while (0)
702#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
703 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
704 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
705 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
706 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
707 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
708 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
709 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
710 } while (0)
711
712#ifndef IEM_WITH_SETJMP
713# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
714 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
715# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
716 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
717# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
718 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
719#else
720# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
721 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
722# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
723 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
724# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
725 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
726#endif
727
728#ifndef IEM_WITH_SETJMP
729# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
730 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
731# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
732 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
733# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
734 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
735#else
736# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
737 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
738# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
739 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
740# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
741 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
742#endif
743
744#ifndef IEM_WITH_SETJMP
745# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
746 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
747# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
748 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
749# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
750 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
751#else
752# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
753 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
754# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
755 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
756# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
757 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
758#endif
759
760#ifdef SOME_UNUSED_FUNCTION
761# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
762 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
763#endif
764
765#ifndef IEM_WITH_SETJMP
766# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
767 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
768# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
769 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
770# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
771 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
772# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
773 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
774#else
775# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
776 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
777# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
778 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
779# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
780 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
781# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
782 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
783#endif
784
785#ifndef IEM_WITH_SETJMP
786# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
787 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
788# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
789 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
790# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
791 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
792# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
793 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
794#else
795# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
796 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
797# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
798 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
799# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
800 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
801# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
802 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
803#endif
804
805#ifndef IEM_WITH_SETJMP
806# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
807 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
808# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
809 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
810# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
811 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
812
813# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
814 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
815# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
816 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
817# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
818 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
819# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
820 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
821# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
822 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
823#else
824# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
825 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
826# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
827 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
828# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
829 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
830
831# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
832 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
833# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
834 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
835# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
836 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
837# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
838 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
839# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
840 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
841#endif
842
843#ifndef IEM_WITH_SETJMP
844# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
845 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
846# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
847 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
848# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
849 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
850
851# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
852 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
853# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
854 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
855# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
856 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
857#else
858# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
859 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
860# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
861 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
862# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
863 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
864
865# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
866 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
867# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
868 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
869# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
870 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
871#endif
872
873
874
875#ifndef IEM_WITH_SETJMP
876# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
877 do { \
878 uint8_t u8Tmp; \
879 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
880 (a_u16Dst) = u8Tmp; \
881 } while (0)
882# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
883 do { \
884 uint8_t u8Tmp; \
885 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
886 (a_u32Dst) = u8Tmp; \
887 } while (0)
888# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
889 do { \
890 uint8_t u8Tmp; \
891 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
892 (a_u64Dst) = u8Tmp; \
893 } while (0)
894# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
895 do { \
896 uint16_t u16Tmp; \
897 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
898 (a_u32Dst) = u16Tmp; \
899 } while (0)
900# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
901 do { \
902 uint16_t u16Tmp; \
903 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
904 (a_u64Dst) = u16Tmp; \
905 } while (0)
906# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
907 do { \
908 uint32_t u32Tmp; \
909 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
910 (a_u64Dst) = u32Tmp; \
911 } while (0)
912#else /* IEM_WITH_SETJMP */
913# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
914 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
915# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
916 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
917# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
918 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
919# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
920 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
921# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
922 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
923# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
924 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
925#endif /* IEM_WITH_SETJMP */
926
927#ifndef IEM_WITH_SETJMP
928# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
929 do { \
930 uint8_t u8Tmp; \
931 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
932 (a_u16Dst) = (int8_t)u8Tmp; \
933 } while (0)
934# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
935 do { \
936 uint8_t u8Tmp; \
937 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
938 (a_u32Dst) = (int8_t)u8Tmp; \
939 } while (0)
940# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
941 do { \
942 uint8_t u8Tmp; \
943 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
944 (a_u64Dst) = (int8_t)u8Tmp; \
945 } while (0)
946# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
947 do { \
948 uint16_t u16Tmp; \
949 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
950 (a_u32Dst) = (int16_t)u16Tmp; \
951 } while (0)
952# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
953 do { \
954 uint16_t u16Tmp; \
955 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
956 (a_u64Dst) = (int16_t)u16Tmp; \
957 } while (0)
958# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
959 do { \
960 uint32_t u32Tmp; \
961 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
962 (a_u64Dst) = (int32_t)u32Tmp; \
963 } while (0)
964#else /* IEM_WITH_SETJMP */
965# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
966 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
967# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
968 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
969# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
970 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
971# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
972 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
973# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
974 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
975# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
976 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
977#endif /* IEM_WITH_SETJMP */
978
979#ifndef IEM_WITH_SETJMP
980# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
981 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
982# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
983 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
984# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
985 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
986# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
987 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
988#else
989# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
990 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
991# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
992 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
993# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
994 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
995# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
996 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
997#endif
998
999#ifndef IEM_WITH_SETJMP
1000# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
1001 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
1002# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
1003 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
1004# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
1005 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
1006# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1007 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
1008#else
1009# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
1010 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
1011# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
1012 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
1013# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
1014 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
1015# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1016 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
1017#endif
1018
1019#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
1020#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
1021#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
1022#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
1023#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
1024#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
1025#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
1026 do { \
1027 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1028 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
1029 } while (0)
1030#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
1031 do { \
1032 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1033 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
1034 } while (0)
1035
1036#ifndef IEM_WITH_SETJMP
1037# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1038 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1039# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1040 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1041#else
1042# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1043 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1044# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1045 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1046#endif
1047
1048#ifndef IEM_WITH_SETJMP
1049# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1050 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1051# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1052 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1053#else
1054# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1055 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1056# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1057 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1058#endif
1059
1060
1061#define IEM_MC_PUSH_U16(a_u16Value) \
1062 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1063#define IEM_MC_PUSH_U32(a_u32Value) \
1064 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1065#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
1066 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
1067#define IEM_MC_PUSH_U64(a_u64Value) \
1068 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1069
1070#define IEM_MC_POP_U16(a_pu16Value) \
1071 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1072#define IEM_MC_POP_U32(a_pu32Value) \
1073 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1074#define IEM_MC_POP_U64(a_pu64Value) \
1075 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1076
1077/** Maps guest memory for direct or bounce buffered access.
1078 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1079 * @remarks May return.
1080 */
1081#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1082 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1083 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1084
1085/** Maps guest memory for direct or bounce buffered access.
1086 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1087 * @remarks May return.
1088 */
1089#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1090 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1091 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1092
1093/** Commits the memory and unmaps the guest memory.
1094 * @remarks May return.
1095 */
1096#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1097 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1098
1099/** Commits the memory and unmaps the guest memory unless the FPU status word
1100 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1101 * that would cause FLD not to store.
1102 *
1103 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1104 * store, while \#P will not.
1105 *
1106 * @remarks May in theory return - for now.
1107 */
1108#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1109 do { \
1110 if ( !(a_u16FSW & X86_FSW_ES) \
1111 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1112 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1113 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1114 } while (0)
1115
1116/** Calculate efficient address from R/M. */
1117#ifndef IEM_WITH_SETJMP
1118# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1119 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1120#else
1121# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1122 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1123#endif
1124
1125#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1126#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1127#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1128#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1129#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1130#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1131#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1132
1133/**
1134 * Defers the rest of the instruction emulation to a C implementation routine
1135 * and returns, only taking the standard parameters.
1136 *
1137 * @param a_pfnCImpl The pointer to the C routine.
1138 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1139 */
1140#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1141
1142/**
1143 * Defers the rest of instruction emulation to a C implementation routine and
1144 * returns, taking one argument in addition to the standard ones.
1145 *
1146 * @param a_pfnCImpl The pointer to the C routine.
1147 * @param a0 The argument.
1148 */
1149#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1150
1151/**
1152 * Defers the rest of the instruction emulation to a C implementation routine
1153 * and returns, taking two arguments in addition to the standard ones.
1154 *
1155 * @param a_pfnCImpl The pointer to the C routine.
1156 * @param a0 The first extra argument.
1157 * @param a1 The second extra argument.
1158 */
1159#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1160
1161/**
1162 * Defers the rest of the instruction emulation to a C implementation routine
1163 * and returns, taking three arguments in addition to the standard ones.
1164 *
1165 * @param a_pfnCImpl The pointer to the C routine.
1166 * @param a0 The first extra argument.
1167 * @param a1 The second extra argument.
1168 * @param a2 The third extra argument.
1169 */
1170#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1171
1172/**
1173 * Defers the rest of the instruction emulation to a C implementation routine
1174 * and returns, taking four arguments in addition to the standard ones.
1175 *
1176 * @param a_pfnCImpl The pointer to the C routine.
1177 * @param a0 The first extra argument.
1178 * @param a1 The second extra argument.
1179 * @param a2 The third extra argument.
1180 * @param a3 The fourth extra argument.
1181 */
1182#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1183
1184/**
1185 * Defers the rest of the instruction emulation to a C implementation routine
1186 * and returns, taking two arguments in addition to the standard ones.
1187 *
1188 * @param a_pfnCImpl The pointer to the C routine.
1189 * @param a0 The first extra argument.
1190 * @param a1 The second extra argument.
1191 * @param a2 The third extra argument.
1192 * @param a3 The fourth extra argument.
1193 * @param a4 The fifth extra argument.
1194 */
1195#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1196
1197/**
1198 * Defers the entire instruction emulation to a C implementation routine and
1199 * returns, only taking the standard parameters.
1200 *
1201 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1202 *
1203 * @param a_pfnCImpl The pointer to the C routine.
1204 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1205 */
1206#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1207
1208/**
1209 * Defers the entire instruction emulation to a C implementation routine and
1210 * returns, taking one argument in addition to the standard ones.
1211 *
1212 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1213 *
1214 * @param a_pfnCImpl The pointer to the C routine.
1215 * @param a0 The argument.
1216 */
1217#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1218
1219/**
1220 * Defers the entire instruction emulation to a C implementation routine and
1221 * returns, taking two arguments in addition to the standard ones.
1222 *
1223 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1224 *
1225 * @param a_pfnCImpl The pointer to the C routine.
1226 * @param a0 The first extra argument.
1227 * @param a1 The second extra argument.
1228 */
1229#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1230
1231/**
1232 * Defers the entire instruction emulation to a C implementation routine and
1233 * returns, taking three arguments in addition to the standard ones.
1234 *
1235 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1236 *
1237 * @param a_pfnCImpl The pointer to the C routine.
1238 * @param a0 The first extra argument.
1239 * @param a1 The second extra argument.
1240 * @param a2 The third extra argument.
1241 */
1242#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1243
1244/**
1245 * Calls a FPU assembly implementation taking one visible argument.
1246 *
1247 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1248 * @param a0 The first extra argument.
1249 */
1250#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1251 do { \
1252 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1253 } while (0)
1254
1255/**
1256 * Calls a FPU assembly implementation taking two visible arguments.
1257 *
1258 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1259 * @param a0 The first extra argument.
1260 * @param a1 The second extra argument.
1261 */
1262#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1263 do { \
1264 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1265 } while (0)
1266
1267/**
1268 * Calls a FPU assembly implementation taking three visible arguments.
1269 *
1270 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1271 * @param a0 The first extra argument.
1272 * @param a1 The second extra argument.
1273 * @param a2 The third extra argument.
1274 */
1275#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1276 do { \
1277 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1278 } while (0)
1279
1280#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1281 do { \
1282 (a_FpuData).FSW = (a_FSW); \
1283 (a_FpuData).r80Result = *(a_pr80Value); \
1284 } while (0)
1285
1286/** Pushes FPU result onto the stack. */
1287#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1288 iemFpuPushResult(pVCpu, &a_FpuData)
1289/** Pushes FPU result onto the stack and sets the FPUDP. */
1290#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1291 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1292
1293/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1294#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1295 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1296
1297/** Stores FPU result in a stack register. */
1298#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1299 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1300/** Stores FPU result in a stack register and pops the stack. */
1301#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1302 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1303/** Stores FPU result in a stack register and sets the FPUDP. */
1304#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1305 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1306/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1307 * stack. */
1308#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1309 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1310
1311/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1312#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1313 iemFpuUpdateOpcodeAndIp(pVCpu)
1314/** Free a stack register (for FFREE and FFREEP). */
1315#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1316 iemFpuStackFree(pVCpu, a_iStReg)
1317/** Increment the FPU stack pointer. */
1318#define IEM_MC_FPU_STACK_INC_TOP() \
1319 iemFpuStackIncTop(pVCpu)
1320/** Decrement the FPU stack pointer. */
1321#define IEM_MC_FPU_STACK_DEC_TOP() \
1322 iemFpuStackDecTop(pVCpu)
1323
1324/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1325#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1326 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1327/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1328#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1329 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1330/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1331#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1332 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1333/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1334#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1335 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1336/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1337 * stack. */
1338#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1339 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1340/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1341#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1342 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1343
1344/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1345#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1346 iemFpuStackUnderflow(pVCpu, a_iStDst)
1347/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1348 * stack. */
1349#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1350 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1351/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1352 * FPUDS. */
1353#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1354 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1355/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1356 * FPUDS. Pops stack. */
1357#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1358 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1359/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1360 * stack twice. */
1361#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1362 iemFpuStackUnderflowThenPopPop(pVCpu)
1363/** Raises a FPU stack underflow exception for an instruction pushing a result
1364 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1365#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1366 iemFpuStackPushUnderflow(pVCpu)
1367/** Raises a FPU stack underflow exception for an instruction pushing a result
1368 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1369#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1370 iemFpuStackPushUnderflowTwo(pVCpu)
1371
1372/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1373 * FPUIP, FPUCS and FOP. */
1374#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1375 iemFpuStackPushOverflow(pVCpu)
1376/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1377 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1378#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1379 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1380/** Prepares for using the FPU state.
1381 * Ensures that we can use the host FPU in the current context (RC+R0.
1382 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1383#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1384/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1385#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1386/** Actualizes the guest FPU state so it can be accessed and modified. */
1387#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1388
1389/** Stores SSE SIMD result updating MXCSR. */
1390#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1391 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1392/** Updates MXCSR. */
1393#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1394 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1395
1396/** Prepares for using the SSE state.
1397 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1398 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1399#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1400/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1401#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1402/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1403#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1404
1405/** Prepares for using the AVX state.
1406 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1407 * Ensures the guest AVX state in the CPUMCTX is up to date.
1408 * @note This will include the AVX512 state too when support for it is added
1409 * due to the zero extending feature of VEX instruction. */
1410#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1411/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1412#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1413/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1414#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1415
1416/**
1417 * Calls a MMX assembly implementation taking two visible arguments.
1418 *
1419 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1420 * @param a0 The first extra argument.
1421 * @param a1 The second extra argument.
1422 */
1423#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1424 do { \
1425 IEM_MC_PREPARE_FPU_USAGE(); \
1426 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1427 } while (0)
1428
1429/**
1430 * Calls a MMX assembly implementation taking three visible arguments.
1431 *
1432 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1433 * @param a0 The first extra argument.
1434 * @param a1 The second extra argument.
1435 * @param a2 The third extra argument.
1436 */
1437#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1438 do { \
1439 IEM_MC_PREPARE_FPU_USAGE(); \
1440 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1441 } while (0)
1442
1443
1444/**
1445 * Calls a SSE assembly implementation taking two visible arguments.
1446 *
1447 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1448 * @param a0 The first extra argument.
1449 * @param a1 The second extra argument.
1450 */
1451#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1452 do { \
1453 IEM_MC_PREPARE_SSE_USAGE(); \
1454 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1455 } while (0)
1456
1457/**
1458 * Calls a SSE assembly implementation taking three visible arguments.
1459 *
1460 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1461 * @param a0 The first extra argument.
1462 * @param a1 The second extra argument.
1463 * @param a2 The third extra argument.
1464 */
1465#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1466 do { \
1467 IEM_MC_PREPARE_SSE_USAGE(); \
1468 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1469 } while (0)
1470
1471
1472/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1473 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1474#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1475 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1476
1477/**
1478 * Calls a AVX assembly implementation taking two visible arguments.
1479 *
1480 * There is one implicit zero'th argument, a pointer to the extended state.
1481 *
1482 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1483 * @param a1 The first extra argument.
1484 * @param a2 The second extra argument.
1485 */
1486#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1487 do { \
1488 IEM_MC_PREPARE_AVX_USAGE(); \
1489 a_pfnAImpl(pXState, (a1), (a2)); \
1490 } while (0)
1491
1492/**
1493 * Calls a AVX assembly implementation taking three visible arguments.
1494 *
1495 * There is one implicit zero'th argument, a pointer to the extended state.
1496 *
1497 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1498 * @param a1 The first extra argument.
1499 * @param a2 The second extra argument.
1500 * @param a3 The third extra argument.
1501 */
1502#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1503 do { \
1504 IEM_MC_PREPARE_AVX_USAGE(); \
1505 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1506 } while (0)
1507
1508/** @note Not for IOPL or IF testing. */
1509#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1510/** @note Not for IOPL or IF testing. */
1511#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1512/** @note Not for IOPL or IF testing. */
1513#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1514/** @note Not for IOPL or IF testing. */
1515#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1516/** @note Not for IOPL or IF testing. */
1517#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1518 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1519 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1520/** @note Not for IOPL or IF testing. */
1521#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1522 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1523 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1524/** @note Not for IOPL or IF testing. */
1525#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1526 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1527 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1528 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1529/** @note Not for IOPL or IF testing. */
1530#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1531 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1532 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1533 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1534#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1535#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1536#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1537/** @note Not for IOPL or IF testing. */
1538#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1539 if ( pVCpu->cpum.GstCtx.cx != 0 \
1540 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1541/** @note Not for IOPL or IF testing. */
1542#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1543 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1544 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1545/** @note Not for IOPL or IF testing. */
1546#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1547 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1548 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1549/** @note Not for IOPL or IF testing. */
1550#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1551 if ( pVCpu->cpum.GstCtx.cx != 0 \
1552 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1553/** @note Not for IOPL or IF testing. */
1554#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1555 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1556 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1557/** @note Not for IOPL or IF testing. */
1558#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1559 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1560 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1561#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1562#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1563
1564#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1565 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1566#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1567 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1568#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1569 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1570#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1571 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1572#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1573 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1574#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1575 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1576#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1577 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1578#define IEM_MC_IF_FCW_IM() \
1579 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1580#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1581 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1582 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1583
1584#define IEM_MC_ELSE() } else {
1585#define IEM_MC_ENDIF() } do {} while (0)
1586
1587/** @} */
1588
1589#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1590
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