VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 99335

Last change on this file since 99335 was 99335, checked in by vboxsync, 2 years ago

VMM/IEM: IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT -> IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT, since the CPUID check was removed they are identical. bugref:10369
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1/* $Id: IEMMc.h 99335 2023-04-07 12:24:52Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44
45/** Internal macro. */
46#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
47 do \
48 { \
49 VBOXSTRICTRC rcStrict2 = a_Expr; \
50 if (rcStrict2 != VINF_SUCCESS) \
51 return rcStrict2; \
52 } while (0)
53
54
55/** Advances RIP, finishes the instruction and returns.
56 * This may include raising debug exceptions and such. */
57#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
58/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
59#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
60 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
61/** Sets RIP (may trigger \#GP), finishes the instruction and returns.
62 * @note only usable in 16-bit op size mode. */
63#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
64 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
65/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
66#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
67 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
68/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
69#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJumpU16AndFinishClearningRF((pVCpu), (a_u16NewIP))
70/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
71#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJumpU32AndFinishClearningRF((pVCpu), (a_u32NewIP))
72/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
73#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJumpU64AndFinishClearningRF((pVCpu), (a_u64NewIP))
74
75#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
76#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
77 do { \
78 if (!(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))) \
79 { } else return iemRaiseDeviceNotAvailable(pVCpu); \
80 } while (0)
81#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
82 do { \
83 if (!((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS))) \
84 { } else return iemRaiseDeviceNotAvailable(pVCpu); \
85 } while (0)
86#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
87 do { \
88 if (!(pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES)) \
89 { } else return iemRaiseMathFault(pVCpu); \
90 } while (0)
91#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
92 do { \
93 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
94 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)) \
95 return iemRaiseUndefinedOpcode(pVCpu); \
96 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
97 return iemRaiseDeviceNotAvailable(pVCpu); \
98 } while (0)
99#define IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT() \
100 do { \
101 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
102 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
103 return iemRaiseUndefinedOpcode(pVCpu); \
104 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
105 return iemRaiseDeviceNotAvailable(pVCpu); \
106 } while (0)
107#define IEM_MC_MAYBE_RAISE_SHA_RELATED_XCPT() \
108 do { \
109 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
110 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
111 return iemRaiseUndefinedOpcode(pVCpu); \
112 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
113 return iemRaiseDeviceNotAvailable(pVCpu); \
114 } while (0)
115#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
116 do { \
117 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
118 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
119 return iemRaiseUndefinedOpcode(pVCpu); \
120 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
121 return iemRaiseDeviceNotAvailable(pVCpu); \
122 } while (0)
123#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
124 do { \
125 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
126 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
127 return iemRaiseUndefinedOpcode(pVCpu); \
128 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
129 return iemRaiseDeviceNotAvailable(pVCpu); \
130 } while (0)
131#define IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT() \
132 do { \
133 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
134 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
135 return iemRaiseUndefinedOpcode(pVCpu); \
136 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
137 return iemRaiseDeviceNotAvailable(pVCpu); \
138 } while (0)
139#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
140 do { \
141 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
142 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
143 return iemRaiseUndefinedOpcode(pVCpu); \
144 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
145 return iemRaiseDeviceNotAvailable(pVCpu); \
146 } while (0)
147#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
148 do { \
149 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
150 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
151 return iemRaiseUndefinedOpcode(pVCpu); \
152 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
153 return iemRaiseDeviceNotAvailable(pVCpu); \
154 } while (0)
155#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
156 do { \
157 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
158 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
159 return iemRaiseUndefinedOpcode(pVCpu); \
160 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
161 return iemRaiseDeviceNotAvailable(pVCpu); \
162 } while (0)
163#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
164 do { \
165 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
166 return iemRaiseUndefinedOpcode(pVCpu); \
167 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
168 return iemRaiseDeviceNotAvailable(pVCpu); \
169 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
170 return iemRaiseMathFault(pVCpu); \
171 } while (0)
172#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
173 do { \
174 if (pVCpu->iem.s.uCpl != 0) \
175 return iemRaiseGeneralProtectionFault0(pVCpu); \
176 } while (0)
177#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
178 do { \
179 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
180 else return iemRaiseGeneralProtectionFault0(pVCpu); \
181 } while (0)
182#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
183 do { \
184 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
185 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
186 return iemRaiseUndefinedOpcode(pVCpu); \
187 } while (0)
188#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
189 do { \
190 if (!IEM_IS_CANONICAL(a_u64Addr)) \
191 return iemRaiseGeneralProtectionFault0(pVCpu); \
192 } while (0)
193#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
194 do { \
195 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
196 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) \
197 { \
198 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
199 return iemRaiseSimdFpException(pVCpu); \
200 return iemRaiseUndefinedOpcode(pVCpu); \
201 } \
202 } while (0)
203#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
204 do { \
205 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
206 return iemRaiseSimdFpException(pVCpu); \
207 return iemRaiseUndefinedOpcode(pVCpu); \
208 } while (0)
209#define IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT() \
210 do { \
211 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
212 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
213 return iemRaiseUndefinedOpcode(pVCpu); \
214 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
215 return iemRaiseDeviceNotAvailable(pVCpu); \
216 } while (0)
217
218
219#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
220#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
221#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
222#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
223#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
224#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
225#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
226 uint32_t a_Name; \
227 uint32_t *a_pName = &a_Name
228#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
229 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
230
231#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
232#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
233#define IEM_MC_ASSIGN_U8_SX_U64(a_u64VarOrArg, a_u8CVariableOrConst) \
234 (a_u64VarOrArg) = (int8_t)(a_u8CVariableOrConst)
235#define IEM_MC_ASSIGN_U32_SX_U64(a_u64VarOrArg, a_u32CVariableOrConst) \
236 (a_u64VarOrArg) = (int32_t)(a_u32CVariableOrConst)
237
238#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
239#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
240#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
241#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
242#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
243#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
244#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
245#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
246#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
247#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
248#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
249#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
250#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
251#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
252#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
253#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
254#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
255#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
256 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
257 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
258 } while (0)
259#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
260 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
261 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
262 } while (0)
263#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
264 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
265 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
266 } while (0)
267/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
268#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
269 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
270 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
271 } while (0)
272#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
273 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
274 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
275 } while (0)
276/** @note Not for IOPL or IF testing or modification. */
277#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
278#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
279#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
280#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
281
282#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
283#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
284#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
285#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
286#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
287#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
288#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
289#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
290#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
291#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
292#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
293/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
294#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
295 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
296 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
297 } while (0)
298#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
299 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
300 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
301 } while (0)
302#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
303 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
304
305
306#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
307#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
308/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
309 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
310#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
311#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
312#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
313#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
314#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
315#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
316/** @note Not for IOPL or IF testing or modification.
317 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
318#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
319#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
320
321#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
322#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
323#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
324 do { \
325 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
326 *pu32Reg += (a_u32Value); \
327 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
328 } while (0)
329#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
330
331#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
332#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
333#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
334 do { \
335 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
336 *pu32Reg -= (a_u32Value); \
337 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
338 } while (0)
339#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
340#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
341
342#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
343#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
344#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
345#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
346#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
347#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
348#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
349
350#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
351#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
352#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
353#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
354
355#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
356#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
357#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
358
359#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
360#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
361#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
362
363#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
364#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
365#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
366
367#define IEM_MC_SHR_LOCAL_U8(a_u8Local, a_cShift) do { (a_u8Local) >>= (a_cShift); } while (0)
368
369#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
370#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
371#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
372
373#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
374
375#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
376
377#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
378#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
379#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
380 do { \
381 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
382 *pu32Reg &= (a_u32Value); \
383 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
384 } while (0)
385#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
386
387#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
388#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
389#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
390 do { \
391 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
392 *pu32Reg |= (a_u32Value); \
393 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
394 } while (0)
395#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
396
397#define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) (a_u16Local) = RT_BSWAP_U16((a_u16Local));
398#define IEM_MC_BSWAP_LOCAL_U32(a_u32Local) (a_u32Local) = RT_BSWAP_U32((a_u32Local));
399#define IEM_MC_BSWAP_LOCAL_U64(a_u64Local) (a_u64Local) = RT_BSWAP_U64((a_u64Local));
400
401/** @note Not for IOPL or IF modification. */
402#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
403/** @note Not for IOPL or IF modification. */
404#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
405/** @note Not for IOPL or IF modification. */
406#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
407
408#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
409
410/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
411#define IEM_MC_FPU_TO_MMX_MODE() do { \
412 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
413 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
414 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
415 } while (0)
416
417/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
418#define IEM_MC_FPU_FROM_MMX_MODE() do { \
419 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
420 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
421 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
422 } while (0)
423
424#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
425 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
426#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
427 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
428#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
429 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
430 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
431 } while (0)
432#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
433 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
434 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
435 } while (0)
436#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
437 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
438#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
439 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
440#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
441 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
442#define IEM_MC_MODIFIED_MREG(a_iMReg) \
443 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
444#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
445 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
446
447#define IEM_MC_CLEAR_XREG_U32_MASK(a_iXReg, a_bMask) \
448 do { if ((a_bMask) & (1 << 0)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = 0; \
449 if ((a_bMask) & (1 << 1)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[1] = 0; \
450 if ((a_bMask) & (1 << 2)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[2] = 0; \
451 if ((a_bMask) & (1 << 3)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[3] = 0; \
452 } while (0)
453#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
454 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
455 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
456 } while (0)
457#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
458 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
459 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
460 } while (0)
461#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) \
462 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQWord)]; } while (0)
463#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg, a_iDWord) \
464 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDWord)]; } while (0)
465#define IEM_MC_FETCH_XREG_U16(a_u16Value, a_iXReg, a_iWord) \
466 do { (a_u16Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iWord)]; } while (0)
467#define IEM_MC_FETCH_XREG_U8( a_u8Value, a_iXReg, a_iByte) \
468 do { (a_u8Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iByte)]; } while (0)
469#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
470 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
471 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
472 } while (0)
473#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
474 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
475 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
476 } while (0)
477#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
478 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
479#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
480 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
481#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) \
482 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_u64Value); } while (0)
483#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) \
484 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_u32Value); } while (0)
485#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u16Value) \
486 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iWord)] = (a_u16Value); } while (0)
487#define IEM_MC_STORE_XREG_U8(a_iXReg, a_iByte, a_u8Value) \
488 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iByte)] = (a_u8Value); } while (0)
489
490#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
491 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
492 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
493 } while (0)
494
495#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) \
496 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDwDst)] = (a_u128Value).au32[(a_iDwSrc)]; } while (0)
497#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
498 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
499#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
500 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
501#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
502 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
503 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
504 } while (0)
505#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
506 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
507#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
508 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
509#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
510 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
511#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
512 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
513#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
514 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
515#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
516 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
517#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
518 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
519#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
520 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
521#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
522 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
523 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
524 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
525 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
526 } while (0)
527
528#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
529 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
530 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
531 } while (0)
532#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
533 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
534 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
535 } while (0)
536#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
537 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
538 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
539 } while (0)
540#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
541 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
542 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
543 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
544 } while (0)
545#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
546 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
547 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
548 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
549 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
550 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
551 } while (0)
552
553#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
554#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
555 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
556 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
557 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
558 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
559 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
560 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
561 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
562 } while (0)
563#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
564 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
565 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
566 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
567 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
568 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
569 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
570 } while (0)
571#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
572 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
573 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
574 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
575 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
576 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
577 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
578 } while (0)
579#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
580 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
581 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
582 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
583 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
584 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
585 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
586 } while (0)
587
588#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
589 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
590#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
591 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
592#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
593 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
594#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
595 do { uintptr_t const iYRegTmp = (a_iYReg); \
596 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
597 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
598 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
599 } while (0)
600
601#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
602 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
603 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
604 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
605 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
606 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
607 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
608 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
609 } while (0)
610#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
611 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
612 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
613 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
614 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
615 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
616 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
617 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
618 } while (0)
619#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
620 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
621 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
622 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
623 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
624 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
625 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
626 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
627 } while (0)
628
629#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
630 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
631 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
632 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
633 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
634 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
635 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
636 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
637 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
638 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
639 } while (0)
640#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
641 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
642 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
643 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
644 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
645 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
646 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
647 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
648 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
649 } while (0)
650#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
651 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
652 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
653 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
654 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
655 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
656 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
657 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
658 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
659 } while (0)
660#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
661 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
662 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
663 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
664 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
665 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
666 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
667 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
668 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
669 } while (0)
670#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
671 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
672 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
673 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
674 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
675 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
676 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
677 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
678 } while (0)
679#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
680 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
681 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
682 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
683 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
684 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
685 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
686 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
687 } while (0)
688
689#ifndef IEM_WITH_SETJMP
690# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
691 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
692# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
693 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
694# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
695 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
696#else
697# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
698 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
699# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
700 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
701# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
702 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
703#endif
704
705#ifndef IEM_WITH_SETJMP
706# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
707 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
708# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
709 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
710# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
711 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
712#else
713# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
714 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
715# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
716 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
717# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
718 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
719#endif
720
721#ifndef IEM_WITH_SETJMP
722# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
723 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
724# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
725 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
726# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
727 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
728#else
729# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
730 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
731# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
732 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
733# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
734 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
735#endif
736
737#ifdef SOME_UNUSED_FUNCTION
738# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
739 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
740#endif
741
742#ifndef IEM_WITH_SETJMP
743# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
744 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
745# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
746 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
747# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
748 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
749# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
750 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
751#else
752# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
753 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
754# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
755 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
756# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
757 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
758# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
759 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
760#endif
761
762#ifndef IEM_WITH_SETJMP
763# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
764 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
765# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
766 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
767# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
768 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
769# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
770 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
771#else
772# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
773 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
774# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
775 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
776# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
777 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
778# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
779 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
780#endif
781
782#ifndef IEM_WITH_SETJMP
783# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
784 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
785# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
786 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
787# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
788 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
789
790# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
791 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
792# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
793 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
794# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
795 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
796# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
797 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
798# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
799 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
800#else
801# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
802 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
803# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
804 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
805# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
806 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
807
808# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
809 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
810# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
811 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
812# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
813 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
814# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
815 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
816# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
817 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
818#endif
819
820#ifndef IEM_WITH_SETJMP
821# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
822 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
823# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
824 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
825# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
826 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
827
828# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
829 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
830# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
831 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
832# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
833 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
834#else
835# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
836 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
837# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
838 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
839# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
840 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
841
842# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
843 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
844# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
845 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
846# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
847 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
848#endif
849
850
851
852#ifndef IEM_WITH_SETJMP
853# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
854 do { \
855 uint8_t u8Tmp; \
856 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
857 (a_u16Dst) = u8Tmp; \
858 } while (0)
859# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
860 do { \
861 uint8_t u8Tmp; \
862 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
863 (a_u32Dst) = u8Tmp; \
864 } while (0)
865# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
866 do { \
867 uint8_t u8Tmp; \
868 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
869 (a_u64Dst) = u8Tmp; \
870 } while (0)
871# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
872 do { \
873 uint16_t u16Tmp; \
874 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
875 (a_u32Dst) = u16Tmp; \
876 } while (0)
877# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
878 do { \
879 uint16_t u16Tmp; \
880 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
881 (a_u64Dst) = u16Tmp; \
882 } while (0)
883# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
884 do { \
885 uint32_t u32Tmp; \
886 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
887 (a_u64Dst) = u32Tmp; \
888 } while (0)
889#else /* IEM_WITH_SETJMP */
890# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
891 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
892# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
893 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
894# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
895 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
896# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
897 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
898# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
899 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
900# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
901 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
902#endif /* IEM_WITH_SETJMP */
903
904#ifndef IEM_WITH_SETJMP
905# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
906 do { \
907 uint8_t u8Tmp; \
908 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
909 (a_u16Dst) = (int8_t)u8Tmp; \
910 } while (0)
911# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
912 do { \
913 uint8_t u8Tmp; \
914 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
915 (a_u32Dst) = (int8_t)u8Tmp; \
916 } while (0)
917# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
918 do { \
919 uint8_t u8Tmp; \
920 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
921 (a_u64Dst) = (int8_t)u8Tmp; \
922 } while (0)
923# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
924 do { \
925 uint16_t u16Tmp; \
926 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
927 (a_u32Dst) = (int16_t)u16Tmp; \
928 } while (0)
929# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
930 do { \
931 uint16_t u16Tmp; \
932 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
933 (a_u64Dst) = (int16_t)u16Tmp; \
934 } while (0)
935# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
936 do { \
937 uint32_t u32Tmp; \
938 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
939 (a_u64Dst) = (int32_t)u32Tmp; \
940 } while (0)
941#else /* IEM_WITH_SETJMP */
942# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
943 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
944# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
945 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
946# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
947 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
948# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
949 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
950# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
951 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
952# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
953 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
954#endif /* IEM_WITH_SETJMP */
955
956#ifndef IEM_WITH_SETJMP
957# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
958 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
959# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
960 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
961# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
962 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
963# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
964 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
965#else
966# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
967 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
968# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
969 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
970# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
971 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
972# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
973 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
974#endif
975
976#ifndef IEM_WITH_SETJMP
977# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
978 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
979# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
980 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
981# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
982 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
983# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
984 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
985#else
986# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
987 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
988# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
989 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
990# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
991 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
992# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
993 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
994#endif
995
996#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
997#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
998#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
999#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
1000#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
1001#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
1002#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
1003 do { \
1004 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1005 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
1006 } while (0)
1007#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
1008 do { \
1009 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1010 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
1011 } while (0)
1012
1013#ifndef IEM_WITH_SETJMP
1014# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1015 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1016# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1017 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1018#else
1019# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1020 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1021# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1022 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1023#endif
1024
1025#ifndef IEM_WITH_SETJMP
1026# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1027 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1028# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1029 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1030#else
1031# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1032 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1033# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1034 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1035#endif
1036
1037
1038#define IEM_MC_PUSH_U16(a_u16Value) \
1039 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1040#define IEM_MC_PUSH_U32(a_u32Value) \
1041 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1042#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
1043 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
1044#define IEM_MC_PUSH_U64(a_u64Value) \
1045 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1046
1047#define IEM_MC_POP_U16(a_pu16Value) \
1048 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1049#define IEM_MC_POP_U32(a_pu32Value) \
1050 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1051#define IEM_MC_POP_U64(a_pu64Value) \
1052 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1053
1054/** Maps guest memory for direct or bounce buffered access.
1055 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1056 * @remarks May return.
1057 */
1058#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1059 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1060 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1061
1062/** Maps guest memory for direct or bounce buffered access.
1063 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1064 * @remarks May return.
1065 */
1066#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1067 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1068 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1069
1070/** Commits the memory and unmaps the guest memory.
1071 * @remarks May return.
1072 */
1073#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1074 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1075
1076/** Commits the memory and unmaps the guest memory unless the FPU status word
1077 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1078 * that would cause FLD not to store.
1079 *
1080 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1081 * store, while \#P will not.
1082 *
1083 * @remarks May in theory return - for now.
1084 */
1085#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1086 do { \
1087 if ( !(a_u16FSW & X86_FSW_ES) \
1088 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1089 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1090 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1091 } while (0)
1092
1093/** Calculate efficient address from R/M. */
1094#ifndef IEM_WITH_SETJMP
1095# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1096 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1097#else
1098# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1099 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1100#endif
1101
1102#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1103#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1104#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1105#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1106#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1107#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1108#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1109
1110/**
1111 * Defers the rest of the instruction emulation to a C implementation routine
1112 * and returns, only taking the standard parameters.
1113 *
1114 * @param a_pfnCImpl The pointer to the C routine.
1115 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1116 */
1117#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1118
1119/**
1120 * Defers the rest of instruction emulation to a C implementation routine and
1121 * returns, taking one argument in addition to the standard ones.
1122 *
1123 * @param a_pfnCImpl The pointer to the C routine.
1124 * @param a0 The argument.
1125 */
1126#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1127
1128/**
1129 * Defers the rest of the instruction emulation to a C implementation routine
1130 * and returns, taking two arguments in addition to the standard ones.
1131 *
1132 * @param a_pfnCImpl The pointer to the C routine.
1133 * @param a0 The first extra argument.
1134 * @param a1 The second extra argument.
1135 */
1136#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1137
1138/**
1139 * Defers the rest of the instruction emulation to a C implementation routine
1140 * and returns, taking three arguments in addition to the standard ones.
1141 *
1142 * @param a_pfnCImpl The pointer to the C routine.
1143 * @param a0 The first extra argument.
1144 * @param a1 The second extra argument.
1145 * @param a2 The third extra argument.
1146 */
1147#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1148
1149/**
1150 * Defers the rest of the instruction emulation to a C implementation routine
1151 * and returns, taking four arguments in addition to the standard ones.
1152 *
1153 * @param a_pfnCImpl The pointer to the C routine.
1154 * @param a0 The first extra argument.
1155 * @param a1 The second extra argument.
1156 * @param a2 The third extra argument.
1157 * @param a3 The fourth extra argument.
1158 */
1159#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1160
1161/**
1162 * Defers the rest of the instruction emulation to a C implementation routine
1163 * and returns, taking two arguments in addition to the standard ones.
1164 *
1165 * @param a_pfnCImpl The pointer to the C routine.
1166 * @param a0 The first extra argument.
1167 * @param a1 The second extra argument.
1168 * @param a2 The third extra argument.
1169 * @param a3 The fourth extra argument.
1170 * @param a4 The fifth extra argument.
1171 */
1172#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1173
1174/**
1175 * Defers the entire instruction emulation to a C implementation routine and
1176 * returns, only taking the standard parameters.
1177 *
1178 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1179 *
1180 * @param a_pfnCImpl The pointer to the C routine.
1181 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1182 */
1183#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1184
1185/**
1186 * Defers the entire instruction emulation to a C implementation routine and
1187 * returns, taking one argument in addition to the standard ones.
1188 *
1189 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1190 *
1191 * @param a_pfnCImpl The pointer to the C routine.
1192 * @param a0 The argument.
1193 */
1194#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1195
1196/**
1197 * Defers the entire instruction emulation to a C implementation routine and
1198 * returns, taking two arguments in addition to the standard ones.
1199 *
1200 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1201 *
1202 * @param a_pfnCImpl The pointer to the C routine.
1203 * @param a0 The first extra argument.
1204 * @param a1 The second extra argument.
1205 */
1206#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1207
1208/**
1209 * Defers the entire instruction emulation to a C implementation routine and
1210 * returns, taking three arguments in addition to the standard ones.
1211 *
1212 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1213 *
1214 * @param a_pfnCImpl The pointer to the C routine.
1215 * @param a0 The first extra argument.
1216 * @param a1 The second extra argument.
1217 * @param a2 The third extra argument.
1218 */
1219#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1220
1221/**
1222 * Calls a FPU assembly implementation taking one visible argument.
1223 *
1224 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1225 * @param a0 The first extra argument.
1226 */
1227#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1228 do { \
1229 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1230 } while (0)
1231
1232/**
1233 * Calls a FPU assembly implementation taking two visible arguments.
1234 *
1235 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1236 * @param a0 The first extra argument.
1237 * @param a1 The second extra argument.
1238 */
1239#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1240 do { \
1241 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1242 } while (0)
1243
1244/**
1245 * Calls a FPU assembly implementation taking three visible arguments.
1246 *
1247 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1248 * @param a0 The first extra argument.
1249 * @param a1 The second extra argument.
1250 * @param a2 The third extra argument.
1251 */
1252#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1253 do { \
1254 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1255 } while (0)
1256
1257#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1258 do { \
1259 (a_FpuData).FSW = (a_FSW); \
1260 (a_FpuData).r80Result = *(a_pr80Value); \
1261 } while (0)
1262
1263/** Pushes FPU result onto the stack. */
1264#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1265 iemFpuPushResult(pVCpu, &a_FpuData)
1266/** Pushes FPU result onto the stack and sets the FPUDP. */
1267#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1268 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1269
1270/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1271#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1272 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1273
1274/** Stores FPU result in a stack register. */
1275#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1276 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1277/** Stores FPU result in a stack register and pops the stack. */
1278#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1279 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1280/** Stores FPU result in a stack register and sets the FPUDP. */
1281#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1282 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1283/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1284 * stack. */
1285#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1286 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1287
1288/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1289#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1290 iemFpuUpdateOpcodeAndIp(pVCpu)
1291/** Free a stack register (for FFREE and FFREEP). */
1292#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1293 iemFpuStackFree(pVCpu, a_iStReg)
1294/** Increment the FPU stack pointer. */
1295#define IEM_MC_FPU_STACK_INC_TOP() \
1296 iemFpuStackIncTop(pVCpu)
1297/** Decrement the FPU stack pointer. */
1298#define IEM_MC_FPU_STACK_DEC_TOP() \
1299 iemFpuStackDecTop(pVCpu)
1300
1301/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1302#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1303 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1304/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1305#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1306 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1307/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1308#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1309 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1310/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1311#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1312 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1313/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1314 * stack. */
1315#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1316 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1317/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1318#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1319 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1320
1321/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1322#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1323 iemFpuStackUnderflow(pVCpu, a_iStDst)
1324/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1325 * stack. */
1326#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1327 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1328/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1329 * FPUDS. */
1330#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1331 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1332/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1333 * FPUDS. Pops stack. */
1334#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1335 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1336/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1337 * stack twice. */
1338#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1339 iemFpuStackUnderflowThenPopPop(pVCpu)
1340/** Raises a FPU stack underflow exception for an instruction pushing a result
1341 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1342#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1343 iemFpuStackPushUnderflow(pVCpu)
1344/** Raises a FPU stack underflow exception for an instruction pushing a result
1345 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1346#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1347 iemFpuStackPushUnderflowTwo(pVCpu)
1348
1349/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1350 * FPUIP, FPUCS and FOP. */
1351#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1352 iemFpuStackPushOverflow(pVCpu)
1353/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1354 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1355#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1356 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1357/** Prepares for using the FPU state.
1358 * Ensures that we can use the host FPU in the current context (RC+R0.
1359 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1360#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1361/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1362#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1363/** Actualizes the guest FPU state so it can be accessed and modified. */
1364#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1365
1366/** Stores SSE SIMD result updating MXCSR. */
1367#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1368 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1369/** Updates MXCSR. */
1370#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1371 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1372
1373/** Prepares for using the SSE state.
1374 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1375 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1376#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1377/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1378#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1379/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1380#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1381
1382/** Prepares for using the AVX state.
1383 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1384 * Ensures the guest AVX state in the CPUMCTX is up to date.
1385 * @note This will include the AVX512 state too when support for it is added
1386 * due to the zero extending feature of VEX instruction. */
1387#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1388/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1389#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1390/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1391#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1392
1393/**
1394 * Calls a MMX assembly implementation taking two visible arguments.
1395 *
1396 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1397 * @param a0 The first extra argument.
1398 * @param a1 The second extra argument.
1399 */
1400#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1401 do { \
1402 IEM_MC_PREPARE_FPU_USAGE(); \
1403 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1404 } while (0)
1405
1406/**
1407 * Calls a MMX assembly implementation taking three visible arguments.
1408 *
1409 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1410 * @param a0 The first extra argument.
1411 * @param a1 The second extra argument.
1412 * @param a2 The third extra argument.
1413 */
1414#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1415 do { \
1416 IEM_MC_PREPARE_FPU_USAGE(); \
1417 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1418 } while (0)
1419
1420
1421/**
1422 * Calls a SSE assembly implementation taking two visible arguments.
1423 *
1424 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1425 * @param a0 The first extra argument.
1426 * @param a1 The second extra argument.
1427 */
1428#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1429 do { \
1430 IEM_MC_PREPARE_SSE_USAGE(); \
1431 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1432 } while (0)
1433
1434/**
1435 * Calls a SSE assembly implementation taking three visible arguments.
1436 *
1437 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1438 * @param a0 The first extra argument.
1439 * @param a1 The second extra argument.
1440 * @param a2 The third extra argument.
1441 */
1442#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1443 do { \
1444 IEM_MC_PREPARE_SSE_USAGE(); \
1445 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1446 } while (0)
1447
1448
1449/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1450 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1451#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1452 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1453
1454/**
1455 * Calls a AVX assembly implementation taking two visible arguments.
1456 *
1457 * There is one implicit zero'th argument, a pointer to the extended state.
1458 *
1459 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1460 * @param a1 The first extra argument.
1461 * @param a2 The second extra argument.
1462 */
1463#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1464 do { \
1465 IEM_MC_PREPARE_AVX_USAGE(); \
1466 a_pfnAImpl(pXState, (a1), (a2)); \
1467 } while (0)
1468
1469/**
1470 * Calls a AVX assembly implementation taking three visible arguments.
1471 *
1472 * There is one implicit zero'th argument, a pointer to the extended state.
1473 *
1474 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1475 * @param a1 The first extra argument.
1476 * @param a2 The second extra argument.
1477 * @param a3 The third extra argument.
1478 */
1479#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1480 do { \
1481 IEM_MC_PREPARE_AVX_USAGE(); \
1482 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1483 } while (0)
1484
1485/** @note Not for IOPL or IF testing. */
1486#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1487/** @note Not for IOPL or IF testing. */
1488#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1489/** @note Not for IOPL or IF testing. */
1490#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1491/** @note Not for IOPL or IF testing. */
1492#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1493/** @note Not for IOPL or IF testing. */
1494#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1495 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1496 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1497/** @note Not for IOPL or IF testing. */
1498#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1499 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1500 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1501/** @note Not for IOPL or IF testing. */
1502#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1503 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1504 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1505 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1506/** @note Not for IOPL or IF testing. */
1507#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1508 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1509 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1510 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1511#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1512#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1513#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1514/** @note Not for IOPL or IF testing. */
1515#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1516 if ( pVCpu->cpum.GstCtx.cx != 0 \
1517 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1518/** @note Not for IOPL or IF testing. */
1519#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1520 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1521 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1522/** @note Not for IOPL or IF testing. */
1523#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1524 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1525 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1526/** @note Not for IOPL or IF testing. */
1527#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1528 if ( pVCpu->cpum.GstCtx.cx != 0 \
1529 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1530/** @note Not for IOPL or IF testing. */
1531#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1532 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1533 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1534/** @note Not for IOPL or IF testing. */
1535#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1536 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1537 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1538#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1539#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1540
1541#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1542 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1543#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1544 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1545#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1546 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1547#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1548 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1549#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1550 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1551#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1552 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1553#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1554 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1555#define IEM_MC_IF_FCW_IM() \
1556 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1557#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1558 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1559 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1560
1561#define IEM_MC_ELSE() } else {
1562#define IEM_MC_ENDIF() } do {} while (0)
1563
1564/** @} */
1565
1566#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1567
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