VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 99337

Last change on this file since 99337 was 99337, checked in by vboxsync, 21 months ago

VMM/IEM: IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT -> IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT, since the CPUID check was removed they are identical. bugref:10369
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 83.7 KB
Line 
1/* $Id: IEMMc.h 99337 2023-04-07 12:33:48Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44
45/** Internal macro. */
46#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
47 do \
48 { \
49 VBOXSTRICTRC rcStrict2 = a_Expr; \
50 if (rcStrict2 != VINF_SUCCESS) \
51 return rcStrict2; \
52 } while (0)
53
54
55/** Advances RIP, finishes the instruction and returns.
56 * This may include raising debug exceptions and such. */
57#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
58/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
59#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
60 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
61/** Sets RIP (may trigger \#GP), finishes the instruction and returns.
62 * @note only usable in 16-bit op size mode. */
63#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
64 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
65/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
66#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
67 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
68/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
69#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJumpU16AndFinishClearningRF((pVCpu), (a_u16NewIP))
70/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
71#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJumpU32AndFinishClearningRF((pVCpu), (a_u32NewIP))
72/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
73#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJumpU64AndFinishClearningRF((pVCpu), (a_u64NewIP))
74
75#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
76#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
77 do { \
78 if (!(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))) \
79 { } else return iemRaiseDeviceNotAvailable(pVCpu); \
80 } while (0)
81#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
82 do { \
83 if (!((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS))) \
84 { } else return iemRaiseDeviceNotAvailable(pVCpu); \
85 } while (0)
86#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
87 do { \
88 if (!(pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES)) \
89 { } else return iemRaiseMathFault(pVCpu); \
90 } while (0)
91#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
92 do { \
93 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
94 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)) \
95 return iemRaiseUndefinedOpcode(pVCpu); \
96 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
97 return iemRaiseDeviceNotAvailable(pVCpu); \
98 } while (0)
99#define IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT() \
100 do { \
101 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
102 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
103 return iemRaiseUndefinedOpcode(pVCpu); \
104 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
105 return iemRaiseDeviceNotAvailable(pVCpu); \
106 } while (0)
107#define IEM_MC_MAYBE_RAISE_SHA_RELATED_XCPT() \
108 do { \
109 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
110 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
111 return iemRaiseUndefinedOpcode(pVCpu); \
112 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
113 return iemRaiseDeviceNotAvailable(pVCpu); \
114 } while (0)
115#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
116 do { \
117 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
118 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
119 return iemRaiseUndefinedOpcode(pVCpu); \
120 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
121 return iemRaiseDeviceNotAvailable(pVCpu); \
122 } while (0)
123#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
124 do { \
125 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
126 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
127 return iemRaiseUndefinedOpcode(pVCpu); \
128 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
129 return iemRaiseDeviceNotAvailable(pVCpu); \
130 } while (0)
131#define IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT() \
132 do { \
133 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
134 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
135 return iemRaiseUndefinedOpcode(pVCpu); \
136 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
137 return iemRaiseDeviceNotAvailable(pVCpu); \
138 } while (0)
139#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
140 do { \
141 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
142 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
143 return iemRaiseUndefinedOpcode(pVCpu); \
144 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
145 return iemRaiseDeviceNotAvailable(pVCpu); \
146 } while (0)
147#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
148 do { \
149 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
150 return iemRaiseUndefinedOpcode(pVCpu); \
151 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
152 return iemRaiseDeviceNotAvailable(pVCpu); \
153 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
154 return iemRaiseMathFault(pVCpu); \
155 } while (0)
156#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
157 do { \
158 if (pVCpu->iem.s.uCpl != 0) \
159 return iemRaiseGeneralProtectionFault0(pVCpu); \
160 } while (0)
161#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
162 do { \
163 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
164 else return iemRaiseGeneralProtectionFault0(pVCpu); \
165 } while (0)
166#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
167 do { \
168 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
169 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
170 return iemRaiseUndefinedOpcode(pVCpu); \
171 } while (0)
172#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
173 do { \
174 if (!IEM_IS_CANONICAL(a_u64Addr)) \
175 return iemRaiseGeneralProtectionFault0(pVCpu); \
176 } while (0)
177#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
178 do { \
179 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
180 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) \
181 { \
182 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
183 return iemRaiseSimdFpException(pVCpu); \
184 return iemRaiseUndefinedOpcode(pVCpu); \
185 } \
186 } while (0)
187#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
188 do { \
189 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
190 return iemRaiseSimdFpException(pVCpu); \
191 return iemRaiseUndefinedOpcode(pVCpu); \
192 } while (0)
193#define IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT() \
194 do { \
195 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
196 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
197 return iemRaiseUndefinedOpcode(pVCpu); \
198 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
199 return iemRaiseDeviceNotAvailable(pVCpu); \
200 } while (0)
201
202
203#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
204#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
205#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
206#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
207#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
208#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
209#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
210 uint32_t a_Name; \
211 uint32_t *a_pName = &a_Name
212#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
213 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
214
215#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
216#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
217#define IEM_MC_ASSIGN_U8_SX_U64(a_u64VarOrArg, a_u8CVariableOrConst) \
218 (a_u64VarOrArg) = (int8_t)(a_u8CVariableOrConst)
219#define IEM_MC_ASSIGN_U32_SX_U64(a_u64VarOrArg, a_u32CVariableOrConst) \
220 (a_u64VarOrArg) = (int32_t)(a_u32CVariableOrConst)
221
222#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
223#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
224#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
225#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
226#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
227#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
228#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
229#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
230#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
231#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
232#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
233#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
234#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
235#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
236#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
237#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
238#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
239#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
240 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
241 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
242 } while (0)
243#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
244 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
245 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
246 } while (0)
247#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
248 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
249 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
250 } while (0)
251/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
252#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
253 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
254 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
255 } while (0)
256#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
257 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
258 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
259 } while (0)
260/** @note Not for IOPL or IF testing or modification. */
261#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
262#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
263#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
264#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
265
266#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
267#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
268#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
269#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
270#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
271#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
272#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
273#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
274#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
275#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
276#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
277/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
278#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
279 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
280 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
281 } while (0)
282#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
283 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
284 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
285 } while (0)
286#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
287 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
288
289
290#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
291#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
292/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
293 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
294#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
295#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
296#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
297#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
298#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
299#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
300/** @note Not for IOPL or IF testing or modification.
301 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
302#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
303#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
304
305#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
306#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
307#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
308 do { \
309 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
310 *pu32Reg += (a_u32Value); \
311 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
312 } while (0)
313#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
314
315#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
316#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
317#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
318 do { \
319 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
320 *pu32Reg -= (a_u32Value); \
321 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
322 } while (0)
323#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
324#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
325
326#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
327#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
328#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
329#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
330#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
331#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
332#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
333
334#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
335#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
336#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
337#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
338
339#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
340#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
341#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
342
343#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
344#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
345#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
346
347#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
348#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
349#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
350
351#define IEM_MC_SHR_LOCAL_U8(a_u8Local, a_cShift) do { (a_u8Local) >>= (a_cShift); } while (0)
352
353#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
354#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
355#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
356
357#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
358
359#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
360
361#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
362#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
363#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
364 do { \
365 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
366 *pu32Reg &= (a_u32Value); \
367 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
368 } while (0)
369#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
370
371#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
372#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
373#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
374 do { \
375 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
376 *pu32Reg |= (a_u32Value); \
377 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
378 } while (0)
379#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
380
381#define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) (a_u16Local) = RT_BSWAP_U16((a_u16Local));
382#define IEM_MC_BSWAP_LOCAL_U32(a_u32Local) (a_u32Local) = RT_BSWAP_U32((a_u32Local));
383#define IEM_MC_BSWAP_LOCAL_U64(a_u64Local) (a_u64Local) = RT_BSWAP_U64((a_u64Local));
384
385/** @note Not for IOPL or IF modification. */
386#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
387/** @note Not for IOPL or IF modification. */
388#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
389/** @note Not for IOPL or IF modification. */
390#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
391
392#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
393
394/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
395#define IEM_MC_FPU_TO_MMX_MODE() do { \
396 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
397 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
398 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
399 } while (0)
400
401/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
402#define IEM_MC_FPU_FROM_MMX_MODE() do { \
403 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
404 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
405 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
406 } while (0)
407
408#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
409 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
410#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
411 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
412#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
413 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
414 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
415 } while (0)
416#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
417 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
418 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
419 } while (0)
420#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
421 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
422#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
423 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
424#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
425 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
426#define IEM_MC_MODIFIED_MREG(a_iMReg) \
427 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
428#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
429 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
430
431#define IEM_MC_CLEAR_XREG_U32_MASK(a_iXReg, a_bMask) \
432 do { if ((a_bMask) & (1 << 0)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = 0; \
433 if ((a_bMask) & (1 << 1)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[1] = 0; \
434 if ((a_bMask) & (1 << 2)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[2] = 0; \
435 if ((a_bMask) & (1 << 3)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[3] = 0; \
436 } while (0)
437#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
438 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
439 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
440 } while (0)
441#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
442 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
443 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
444 } while (0)
445#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) \
446 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQWord)]; } while (0)
447#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg, a_iDWord) \
448 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDWord)]; } while (0)
449#define IEM_MC_FETCH_XREG_U16(a_u16Value, a_iXReg, a_iWord) \
450 do { (a_u16Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iWord)]; } while (0)
451#define IEM_MC_FETCH_XREG_U8( a_u8Value, a_iXReg, a_iByte) \
452 do { (a_u8Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iByte)]; } while (0)
453#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
454 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
455 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
456 } while (0)
457#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
458 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
459 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
460 } while (0)
461#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
462 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
463#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
464 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
465#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) \
466 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_u64Value); } while (0)
467#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) \
468 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_u32Value); } while (0)
469#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u16Value) \
470 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iWord)] = (a_u16Value); } while (0)
471#define IEM_MC_STORE_XREG_U8(a_iXReg, a_iByte, a_u8Value) \
472 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iByte)] = (a_u8Value); } while (0)
473
474#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
475 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
476 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
477 } while (0)
478
479#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) \
480 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDwDst)] = (a_u128Value).au32[(a_iDwSrc)]; } while (0)
481#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
482 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
483#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
484 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
485#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
486 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
487 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
488 } while (0)
489#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
490 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
491#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
492 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
493#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
494 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
495#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
496 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
497#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
498 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
499#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
500 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
501#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
502 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
503#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
504 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
505#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
506 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
507 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
508 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
509 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
510 } while (0)
511
512#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
513 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
514 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
515 } while (0)
516#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
517 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
518 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
519 } while (0)
520#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
521 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
522 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
523 } while (0)
524#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
525 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
526 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
527 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
528 } while (0)
529#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
530 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
531 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
532 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
533 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
534 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
535 } while (0)
536
537#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
538#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
539 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
540 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
541 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
542 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
543 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
544 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
545 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
546 } while (0)
547#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
548 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
549 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
550 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
551 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
552 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
553 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
554 } while (0)
555#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
556 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
557 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
558 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
559 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
560 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
561 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
562 } while (0)
563#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
564 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
565 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
566 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
567 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
568 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
569 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
570 } while (0)
571
572#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
573 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
574#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
575 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
576#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
577 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
578#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
579 do { uintptr_t const iYRegTmp = (a_iYReg); \
580 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
581 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
582 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
583 } while (0)
584
585#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
586 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
587 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
588 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
589 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
590 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
591 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
592 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
593 } while (0)
594#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
595 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
596 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
597 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
598 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
599 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
600 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
601 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
602 } while (0)
603#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
604 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
605 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
606 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
607 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
608 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
609 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
610 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
611 } while (0)
612
613#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
614 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
615 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
616 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
617 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
618 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
619 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
620 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
621 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
622 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
623 } while (0)
624#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
625 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
626 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
627 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
628 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
629 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
630 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
631 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
632 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
633 } while (0)
634#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
635 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
636 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
637 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
638 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
639 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
640 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
641 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
642 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
643 } while (0)
644#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
645 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
646 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
647 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
648 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
649 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
650 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
651 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
652 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
653 } while (0)
654#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
655 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
656 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
657 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
658 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
659 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
660 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
661 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
662 } while (0)
663#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
664 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
665 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
666 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
667 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
668 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
669 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
670 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
671 } while (0)
672
673#ifndef IEM_WITH_SETJMP
674# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
675 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
676# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
677 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
678# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
679 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
680#else
681# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
682 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
683# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
684 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
685# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
686 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
687#endif
688
689#ifndef IEM_WITH_SETJMP
690# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
691 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
692# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
693 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
694# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
695 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
696#else
697# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
698 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
699# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
700 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
701# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
702 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
703#endif
704
705#ifndef IEM_WITH_SETJMP
706# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
707 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
708# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
709 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
710# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
711 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
712#else
713# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
714 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
715# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
716 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
717# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
718 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
719#endif
720
721#ifdef SOME_UNUSED_FUNCTION
722# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
723 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
724#endif
725
726#ifndef IEM_WITH_SETJMP
727# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
728 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
729# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
730 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
731# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
732 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
733# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
734 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
735#else
736# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
737 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
738# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
739 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
740# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
741 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
742# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
743 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
744#endif
745
746#ifndef IEM_WITH_SETJMP
747# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
748 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
749# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
750 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
751# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
752 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
753# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
754 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
755#else
756# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
757 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
758# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
759 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
760# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
761 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
762# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
763 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
764#endif
765
766#ifndef IEM_WITH_SETJMP
767# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
768 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
769# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
770 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
771# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
772 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
773
774# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
775 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
776# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
777 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
778# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
779 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
780# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
781 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
782# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
783 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
784#else
785# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
786 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
787# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
788 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
789# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
790 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
791
792# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
793 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
794# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
795 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
796# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
797 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
798# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
799 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
800# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
801 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
802#endif
803
804#ifndef IEM_WITH_SETJMP
805# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
806 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
807# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
808 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
809# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
810 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
811
812# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
813 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
814# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
815 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
816# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
817 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
818#else
819# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
820 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
821# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
822 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
823# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
824 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
825
826# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
827 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
828# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
829 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
830# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
831 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
832#endif
833
834
835
836#ifndef IEM_WITH_SETJMP
837# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
838 do { \
839 uint8_t u8Tmp; \
840 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
841 (a_u16Dst) = u8Tmp; \
842 } while (0)
843# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
844 do { \
845 uint8_t u8Tmp; \
846 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
847 (a_u32Dst) = u8Tmp; \
848 } while (0)
849# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
850 do { \
851 uint8_t u8Tmp; \
852 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
853 (a_u64Dst) = u8Tmp; \
854 } while (0)
855# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
856 do { \
857 uint16_t u16Tmp; \
858 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
859 (a_u32Dst) = u16Tmp; \
860 } while (0)
861# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
862 do { \
863 uint16_t u16Tmp; \
864 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
865 (a_u64Dst) = u16Tmp; \
866 } while (0)
867# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
868 do { \
869 uint32_t u32Tmp; \
870 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
871 (a_u64Dst) = u32Tmp; \
872 } while (0)
873#else /* IEM_WITH_SETJMP */
874# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
875 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
876# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
877 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
878# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
879 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
880# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
881 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
882# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
883 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
884# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
885 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
886#endif /* IEM_WITH_SETJMP */
887
888#ifndef IEM_WITH_SETJMP
889# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
890 do { \
891 uint8_t u8Tmp; \
892 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
893 (a_u16Dst) = (int8_t)u8Tmp; \
894 } while (0)
895# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
896 do { \
897 uint8_t u8Tmp; \
898 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
899 (a_u32Dst) = (int8_t)u8Tmp; \
900 } while (0)
901# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
902 do { \
903 uint8_t u8Tmp; \
904 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
905 (a_u64Dst) = (int8_t)u8Tmp; \
906 } while (0)
907# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
908 do { \
909 uint16_t u16Tmp; \
910 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
911 (a_u32Dst) = (int16_t)u16Tmp; \
912 } while (0)
913# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
914 do { \
915 uint16_t u16Tmp; \
916 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
917 (a_u64Dst) = (int16_t)u16Tmp; \
918 } while (0)
919# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
920 do { \
921 uint32_t u32Tmp; \
922 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
923 (a_u64Dst) = (int32_t)u32Tmp; \
924 } while (0)
925#else /* IEM_WITH_SETJMP */
926# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
927 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
928# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
929 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
930# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
931 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
932# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
933 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
934# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
935 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
936# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
937 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
938#endif /* IEM_WITH_SETJMP */
939
940#ifndef IEM_WITH_SETJMP
941# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
942 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
943# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
944 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
945# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
946 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
947# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
948 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
949#else
950# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
951 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
952# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
953 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
954# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
955 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
956# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
957 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
958#endif
959
960#ifndef IEM_WITH_SETJMP
961# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
962 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
963# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
964 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
965# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
966 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
967# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
968 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
969#else
970# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
971 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
972# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
973 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
974# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
975 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
976# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
977 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
978#endif
979
980#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
981#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
982#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
983#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
984#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
985#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
986#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
987 do { \
988 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
989 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
990 } while (0)
991#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
992 do { \
993 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
994 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
995 } while (0)
996
997#ifndef IEM_WITH_SETJMP
998# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
999 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1000# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1001 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1002#else
1003# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1004 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1005# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1006 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1007#endif
1008
1009#ifndef IEM_WITH_SETJMP
1010# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1011 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1012# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1013 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1014#else
1015# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1016 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1017# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1018 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1019#endif
1020
1021
1022#define IEM_MC_PUSH_U16(a_u16Value) \
1023 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1024#define IEM_MC_PUSH_U32(a_u32Value) \
1025 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1026#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
1027 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
1028#define IEM_MC_PUSH_U64(a_u64Value) \
1029 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1030
1031#define IEM_MC_POP_U16(a_pu16Value) \
1032 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1033#define IEM_MC_POP_U32(a_pu32Value) \
1034 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1035#define IEM_MC_POP_U64(a_pu64Value) \
1036 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1037
1038/** Maps guest memory for direct or bounce buffered access.
1039 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1040 * @remarks May return.
1041 */
1042#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1043 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1044 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1045
1046/** Maps guest memory for direct or bounce buffered access.
1047 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1048 * @remarks May return.
1049 */
1050#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1051 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1052 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1053
1054/** Commits the memory and unmaps the guest memory.
1055 * @remarks May return.
1056 */
1057#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1058 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1059
1060/** Commits the memory and unmaps the guest memory unless the FPU status word
1061 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1062 * that would cause FLD not to store.
1063 *
1064 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1065 * store, while \#P will not.
1066 *
1067 * @remarks May in theory return - for now.
1068 */
1069#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1070 do { \
1071 if ( !(a_u16FSW & X86_FSW_ES) \
1072 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1073 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1074 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1075 } while (0)
1076
1077/** Calculate efficient address from R/M. */
1078#ifndef IEM_WITH_SETJMP
1079# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1080 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1081#else
1082# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1083 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1084#endif
1085
1086#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1087#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1088#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1089#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1090#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1091#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1092#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1093
1094/**
1095 * Defers the rest of the instruction emulation to a C implementation routine
1096 * and returns, only taking the standard parameters.
1097 *
1098 * @param a_pfnCImpl The pointer to the C routine.
1099 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1100 */
1101#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1102
1103/**
1104 * Defers the rest of instruction emulation to a C implementation routine and
1105 * returns, taking one argument in addition to the standard ones.
1106 *
1107 * @param a_pfnCImpl The pointer to the C routine.
1108 * @param a0 The argument.
1109 */
1110#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1111
1112/**
1113 * Defers the rest of the instruction emulation to a C implementation routine
1114 * and returns, taking two arguments in addition to the standard ones.
1115 *
1116 * @param a_pfnCImpl The pointer to the C routine.
1117 * @param a0 The first extra argument.
1118 * @param a1 The second extra argument.
1119 */
1120#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1121
1122/**
1123 * Defers the rest of the instruction emulation to a C implementation routine
1124 * and returns, taking three arguments in addition to the standard ones.
1125 *
1126 * @param a_pfnCImpl The pointer to the C routine.
1127 * @param a0 The first extra argument.
1128 * @param a1 The second extra argument.
1129 * @param a2 The third extra argument.
1130 */
1131#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1132
1133/**
1134 * Defers the rest of the instruction emulation to a C implementation routine
1135 * and returns, taking four arguments in addition to the standard ones.
1136 *
1137 * @param a_pfnCImpl The pointer to the C routine.
1138 * @param a0 The first extra argument.
1139 * @param a1 The second extra argument.
1140 * @param a2 The third extra argument.
1141 * @param a3 The fourth extra argument.
1142 */
1143#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1144
1145/**
1146 * Defers the rest of the instruction emulation to a C implementation routine
1147 * and returns, taking two arguments in addition to the standard ones.
1148 *
1149 * @param a_pfnCImpl The pointer to the C routine.
1150 * @param a0 The first extra argument.
1151 * @param a1 The second extra argument.
1152 * @param a2 The third extra argument.
1153 * @param a3 The fourth extra argument.
1154 * @param a4 The fifth extra argument.
1155 */
1156#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1157
1158/**
1159 * Defers the entire instruction emulation to a C implementation routine and
1160 * returns, only taking the standard parameters.
1161 *
1162 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1163 *
1164 * @param a_pfnCImpl The pointer to the C routine.
1165 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1166 */
1167#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1168
1169/**
1170 * Defers the entire instruction emulation to a C implementation routine and
1171 * returns, taking one argument in addition to the standard ones.
1172 *
1173 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1174 *
1175 * @param a_pfnCImpl The pointer to the C routine.
1176 * @param a0 The argument.
1177 */
1178#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1179
1180/**
1181 * Defers the entire instruction emulation to a C implementation routine and
1182 * returns, taking two arguments in addition to the standard ones.
1183 *
1184 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1185 *
1186 * @param a_pfnCImpl The pointer to the C routine.
1187 * @param a0 The first extra argument.
1188 * @param a1 The second extra argument.
1189 */
1190#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1191
1192/**
1193 * Defers the entire instruction emulation to a C implementation routine and
1194 * returns, taking three arguments in addition to the standard ones.
1195 *
1196 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1197 *
1198 * @param a_pfnCImpl The pointer to the C routine.
1199 * @param a0 The first extra argument.
1200 * @param a1 The second extra argument.
1201 * @param a2 The third extra argument.
1202 */
1203#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1204
1205/**
1206 * Calls a FPU assembly implementation taking one visible argument.
1207 *
1208 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1209 * @param a0 The first extra argument.
1210 */
1211#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1212 do { \
1213 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1214 } while (0)
1215
1216/**
1217 * Calls a FPU assembly implementation taking two visible arguments.
1218 *
1219 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1220 * @param a0 The first extra argument.
1221 * @param a1 The second extra argument.
1222 */
1223#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1224 do { \
1225 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1226 } while (0)
1227
1228/**
1229 * Calls a FPU assembly implementation taking three visible arguments.
1230 *
1231 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1232 * @param a0 The first extra argument.
1233 * @param a1 The second extra argument.
1234 * @param a2 The third extra argument.
1235 */
1236#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1237 do { \
1238 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1239 } while (0)
1240
1241#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1242 do { \
1243 (a_FpuData).FSW = (a_FSW); \
1244 (a_FpuData).r80Result = *(a_pr80Value); \
1245 } while (0)
1246
1247/** Pushes FPU result onto the stack. */
1248#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1249 iemFpuPushResult(pVCpu, &a_FpuData)
1250/** Pushes FPU result onto the stack and sets the FPUDP. */
1251#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1252 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1253
1254/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1255#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1256 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1257
1258/** Stores FPU result in a stack register. */
1259#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1260 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1261/** Stores FPU result in a stack register and pops the stack. */
1262#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1263 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1264/** Stores FPU result in a stack register and sets the FPUDP. */
1265#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1266 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1267/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1268 * stack. */
1269#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1270 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1271
1272/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1273#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1274 iemFpuUpdateOpcodeAndIp(pVCpu)
1275/** Free a stack register (for FFREE and FFREEP). */
1276#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1277 iemFpuStackFree(pVCpu, a_iStReg)
1278/** Increment the FPU stack pointer. */
1279#define IEM_MC_FPU_STACK_INC_TOP() \
1280 iemFpuStackIncTop(pVCpu)
1281/** Decrement the FPU stack pointer. */
1282#define IEM_MC_FPU_STACK_DEC_TOP() \
1283 iemFpuStackDecTop(pVCpu)
1284
1285/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1286#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1287 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1288/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1289#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1290 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1291/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1292#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1293 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1294/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1295#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1296 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1297/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1298 * stack. */
1299#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1300 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1301/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1302#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1303 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1304
1305/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1306#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1307 iemFpuStackUnderflow(pVCpu, a_iStDst)
1308/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1309 * stack. */
1310#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1311 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1312/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1313 * FPUDS. */
1314#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1315 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1316/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1317 * FPUDS. Pops stack. */
1318#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1319 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1320/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1321 * stack twice. */
1322#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1323 iemFpuStackUnderflowThenPopPop(pVCpu)
1324/** Raises a FPU stack underflow exception for an instruction pushing a result
1325 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1326#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1327 iemFpuStackPushUnderflow(pVCpu)
1328/** Raises a FPU stack underflow exception for an instruction pushing a result
1329 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1330#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1331 iemFpuStackPushUnderflowTwo(pVCpu)
1332
1333/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1334 * FPUIP, FPUCS and FOP. */
1335#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1336 iemFpuStackPushOverflow(pVCpu)
1337/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1338 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1339#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1340 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1341/** Prepares for using the FPU state.
1342 * Ensures that we can use the host FPU in the current context (RC+R0.
1343 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1344#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1345/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1346#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1347/** Actualizes the guest FPU state so it can be accessed and modified. */
1348#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1349
1350/** Stores SSE SIMD result updating MXCSR. */
1351#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1352 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1353/** Updates MXCSR. */
1354#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1355 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1356
1357/** Prepares for using the SSE state.
1358 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1359 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1360#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1361/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1362#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1363/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1364#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1365
1366/** Prepares for using the AVX state.
1367 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1368 * Ensures the guest AVX state in the CPUMCTX is up to date.
1369 * @note This will include the AVX512 state too when support for it is added
1370 * due to the zero extending feature of VEX instruction. */
1371#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1372/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1373#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1374/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1375#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1376
1377/**
1378 * Calls a MMX assembly implementation taking two visible arguments.
1379 *
1380 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1381 * @param a0 The first extra argument.
1382 * @param a1 The second extra argument.
1383 */
1384#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1385 do { \
1386 IEM_MC_PREPARE_FPU_USAGE(); \
1387 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1388 } while (0)
1389
1390/**
1391 * Calls a MMX assembly implementation taking three visible arguments.
1392 *
1393 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1394 * @param a0 The first extra argument.
1395 * @param a1 The second extra argument.
1396 * @param a2 The third extra argument.
1397 */
1398#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1399 do { \
1400 IEM_MC_PREPARE_FPU_USAGE(); \
1401 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1402 } while (0)
1403
1404
1405/**
1406 * Calls a SSE assembly implementation taking two visible arguments.
1407 *
1408 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1409 * @param a0 The first extra argument.
1410 * @param a1 The second extra argument.
1411 */
1412#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1413 do { \
1414 IEM_MC_PREPARE_SSE_USAGE(); \
1415 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1416 } while (0)
1417
1418/**
1419 * Calls a SSE assembly implementation taking three visible arguments.
1420 *
1421 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1422 * @param a0 The first extra argument.
1423 * @param a1 The second extra argument.
1424 * @param a2 The third extra argument.
1425 */
1426#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1427 do { \
1428 IEM_MC_PREPARE_SSE_USAGE(); \
1429 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1430 } while (0)
1431
1432
1433/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1434 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1435#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1436 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1437
1438/**
1439 * Calls a AVX assembly implementation taking two visible arguments.
1440 *
1441 * There is one implicit zero'th argument, a pointer to the extended state.
1442 *
1443 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1444 * @param a1 The first extra argument.
1445 * @param a2 The second extra argument.
1446 */
1447#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1448 do { \
1449 IEM_MC_PREPARE_AVX_USAGE(); \
1450 a_pfnAImpl(pXState, (a1), (a2)); \
1451 } while (0)
1452
1453/**
1454 * Calls a AVX assembly implementation taking three visible arguments.
1455 *
1456 * There is one implicit zero'th argument, a pointer to the extended state.
1457 *
1458 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1459 * @param a1 The first extra argument.
1460 * @param a2 The second extra argument.
1461 * @param a3 The third extra argument.
1462 */
1463#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1464 do { \
1465 IEM_MC_PREPARE_AVX_USAGE(); \
1466 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1467 } while (0)
1468
1469/** @note Not for IOPL or IF testing. */
1470#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1471/** @note Not for IOPL or IF testing. */
1472#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1473/** @note Not for IOPL or IF testing. */
1474#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1475/** @note Not for IOPL or IF testing. */
1476#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1477/** @note Not for IOPL or IF testing. */
1478#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1479 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1480 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1481/** @note Not for IOPL or IF testing. */
1482#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1483 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1484 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1485/** @note Not for IOPL or IF testing. */
1486#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1487 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1488 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1489 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1490/** @note Not for IOPL or IF testing. */
1491#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1492 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1493 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1494 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1495#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1496#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1497#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1498/** @note Not for IOPL or IF testing. */
1499#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1500 if ( pVCpu->cpum.GstCtx.cx != 0 \
1501 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1502/** @note Not for IOPL or IF testing. */
1503#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1504 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1505 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1506/** @note Not for IOPL or IF testing. */
1507#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1508 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1509 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1510/** @note Not for IOPL or IF testing. */
1511#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1512 if ( pVCpu->cpum.GstCtx.cx != 0 \
1513 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1514/** @note Not for IOPL or IF testing. */
1515#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1516 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1517 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1518/** @note Not for IOPL or IF testing. */
1519#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1520 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1521 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1522#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1523#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1524
1525#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1526 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1527#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1528 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1529#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1530 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1531#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1532 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1533#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1534 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1535#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1536 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1537#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1538 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1539#define IEM_MC_IF_FCW_IM() \
1540 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1541#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1542 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1543 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1544
1545#define IEM_MC_ELSE() } else {
1546#define IEM_MC_ENDIF() } do {} while (0)
1547
1548/** @} */
1549
1550#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1551
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette