VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 99341

Last change on this file since 99341 was 99341, checked in by vboxsync, 2 years ago

VMM/IEM: IEM_MC_MAYBE_RAISE_SHA_RELATED_XCPT -> IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT, since the CPUID check was removed they are identical. bugref:10369
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1/* $Id: IEMMc.h 99341 2023-04-07 12:41:27Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44
45/** Internal macro. */
46#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
47 do \
48 { \
49 VBOXSTRICTRC rcStrict2 = a_Expr; \
50 if (rcStrict2 != VINF_SUCCESS) \
51 return rcStrict2; \
52 } while (0)
53
54
55/** Advances RIP, finishes the instruction and returns.
56 * This may include raising debug exceptions and such. */
57#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
58/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
59#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
60 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
61/** Sets RIP (may trigger \#GP), finishes the instruction and returns.
62 * @note only usable in 16-bit op size mode. */
63#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
64 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
65/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
66#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
67 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
68/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
69#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJumpU16AndFinishClearningRF((pVCpu), (a_u16NewIP))
70/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
71#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJumpU32AndFinishClearningRF((pVCpu), (a_u32NewIP))
72/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
73#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJumpU64AndFinishClearningRF((pVCpu), (a_u64NewIP))
74
75#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
76#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
77 do { \
78 if (!(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))) \
79 { } else return iemRaiseDeviceNotAvailable(pVCpu); \
80 } while (0)
81#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
82 do { \
83 if (!((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS))) \
84 { } else return iemRaiseDeviceNotAvailable(pVCpu); \
85 } while (0)
86#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
87 do { \
88 if (!(pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES)) \
89 { } else return iemRaiseMathFault(pVCpu); \
90 } while (0)
91#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
92 do { \
93 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
94 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)) \
95 return iemRaiseUndefinedOpcode(pVCpu); \
96 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
97 return iemRaiseDeviceNotAvailable(pVCpu); \
98 } while (0)
99#define IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT() \
100 do { \
101 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
102 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
103 return iemRaiseUndefinedOpcode(pVCpu); \
104 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
105 return iemRaiseDeviceNotAvailable(pVCpu); \
106 } while (0)
107#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
108 do { \
109 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
110 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
111 return iemRaiseUndefinedOpcode(pVCpu); \
112 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
113 return iemRaiseDeviceNotAvailable(pVCpu); \
114 } while (0)
115#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
116 do { \
117 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
118 return iemRaiseUndefinedOpcode(pVCpu); \
119 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
120 return iemRaiseDeviceNotAvailable(pVCpu); \
121 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
122 return iemRaiseMathFault(pVCpu); \
123 } while (0)
124#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
125 do { \
126 if (pVCpu->iem.s.uCpl != 0) \
127 return iemRaiseGeneralProtectionFault0(pVCpu); \
128 } while (0)
129#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
130 do { \
131 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
132 else return iemRaiseGeneralProtectionFault0(pVCpu); \
133 } while (0)
134#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
135 do { \
136 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
137 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
138 return iemRaiseUndefinedOpcode(pVCpu); \
139 } while (0)
140#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
141 do { \
142 if (!IEM_IS_CANONICAL(a_u64Addr)) \
143 return iemRaiseGeneralProtectionFault0(pVCpu); \
144 } while (0)
145#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
146 do { \
147 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
148 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) \
149 { \
150 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
151 return iemRaiseSimdFpException(pVCpu); \
152 return iemRaiseUndefinedOpcode(pVCpu); \
153 } \
154 } while (0)
155#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
156 do { \
157 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
158 return iemRaiseSimdFpException(pVCpu); \
159 return iemRaiseUndefinedOpcode(pVCpu); \
160 } while (0)
161#define IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT() \
162 do { \
163 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
164 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
165 return iemRaiseUndefinedOpcode(pVCpu); \
166 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
167 return iemRaiseDeviceNotAvailable(pVCpu); \
168 } while (0)
169
170
171#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
172#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
173#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
174#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
175#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
176#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
177#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
178 uint32_t a_Name; \
179 uint32_t *a_pName = &a_Name
180#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
181 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
182
183#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
184#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
185#define IEM_MC_ASSIGN_U8_SX_U64(a_u64VarOrArg, a_u8CVariableOrConst) \
186 (a_u64VarOrArg) = (int8_t)(a_u8CVariableOrConst)
187#define IEM_MC_ASSIGN_U32_SX_U64(a_u64VarOrArg, a_u32CVariableOrConst) \
188 (a_u64VarOrArg) = (int32_t)(a_u32CVariableOrConst)
189
190#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
191#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
192#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
193#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
194#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
195#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
196#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
197#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
198#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
199#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
200#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
201#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
202#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
203#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
204#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
205#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
206#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
207#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
208 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
209 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
210 } while (0)
211#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
212 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
213 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
214 } while (0)
215#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
216 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
217 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
218 } while (0)
219/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
220#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
221 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
222 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
223 } while (0)
224#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
225 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
226 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
227 } while (0)
228/** @note Not for IOPL or IF testing or modification. */
229#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
230#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
231#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
232#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
233
234#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
235#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
236#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
237#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
238#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
239#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
240#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
241#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
242#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
243#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
244#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
245/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
246#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
247 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
248 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
249 } while (0)
250#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
251 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
252 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
253 } while (0)
254#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
255 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
256
257
258#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
259#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
260/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
261 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
262#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
263#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
264#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
265#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
266#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
267#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
268/** @note Not for IOPL or IF testing or modification.
269 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
270#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
271#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
272
273#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
274#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
275#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
276 do { \
277 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
278 *pu32Reg += (a_u32Value); \
279 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
280 } while (0)
281#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
282
283#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
284#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
285#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
286 do { \
287 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
288 *pu32Reg -= (a_u32Value); \
289 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
290 } while (0)
291#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
292#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
293
294#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
295#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
296#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
297#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
298#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
299#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
300#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
301
302#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
303#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
304#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
305#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
306
307#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
308#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
309#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
310
311#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
312#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
313#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
314
315#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
316#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
317#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
318
319#define IEM_MC_SHR_LOCAL_U8(a_u8Local, a_cShift) do { (a_u8Local) >>= (a_cShift); } while (0)
320
321#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
322#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
323#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
324
325#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
326
327#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
328
329#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
330#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
331#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
332 do { \
333 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
334 *pu32Reg &= (a_u32Value); \
335 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
336 } while (0)
337#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
338
339#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
340#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
341#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
342 do { \
343 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
344 *pu32Reg |= (a_u32Value); \
345 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
346 } while (0)
347#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
348
349#define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) (a_u16Local) = RT_BSWAP_U16((a_u16Local));
350#define IEM_MC_BSWAP_LOCAL_U32(a_u32Local) (a_u32Local) = RT_BSWAP_U32((a_u32Local));
351#define IEM_MC_BSWAP_LOCAL_U64(a_u64Local) (a_u64Local) = RT_BSWAP_U64((a_u64Local));
352
353/** @note Not for IOPL or IF modification. */
354#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
355/** @note Not for IOPL or IF modification. */
356#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
357/** @note Not for IOPL or IF modification. */
358#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
359
360#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
361
362/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
363#define IEM_MC_FPU_TO_MMX_MODE() do { \
364 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
365 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
366 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
367 } while (0)
368
369/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
370#define IEM_MC_FPU_FROM_MMX_MODE() do { \
371 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
372 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
373 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
374 } while (0)
375
376#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
377 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
378#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
379 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
380#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
381 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
382 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
383 } while (0)
384#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
385 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
386 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
387 } while (0)
388#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
389 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
390#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
391 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
392#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
393 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
394#define IEM_MC_MODIFIED_MREG(a_iMReg) \
395 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
396#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
397 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
398
399#define IEM_MC_CLEAR_XREG_U32_MASK(a_iXReg, a_bMask) \
400 do { if ((a_bMask) & (1 << 0)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = 0; \
401 if ((a_bMask) & (1 << 1)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[1] = 0; \
402 if ((a_bMask) & (1 << 2)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[2] = 0; \
403 if ((a_bMask) & (1 << 3)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[3] = 0; \
404 } while (0)
405#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
406 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
407 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
408 } while (0)
409#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
410 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
411 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
412 } while (0)
413#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) \
414 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQWord)]; } while (0)
415#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg, a_iDWord) \
416 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDWord)]; } while (0)
417#define IEM_MC_FETCH_XREG_U16(a_u16Value, a_iXReg, a_iWord) \
418 do { (a_u16Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iWord)]; } while (0)
419#define IEM_MC_FETCH_XREG_U8( a_u8Value, a_iXReg, a_iByte) \
420 do { (a_u8Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iByte)]; } while (0)
421#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
422 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
423 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
424 } while (0)
425#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
426 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
427 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
428 } while (0)
429#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
430 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
431#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
432 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
433#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) \
434 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_u64Value); } while (0)
435#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) \
436 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_u32Value); } while (0)
437#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u16Value) \
438 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iWord)] = (a_u16Value); } while (0)
439#define IEM_MC_STORE_XREG_U8(a_iXReg, a_iByte, a_u8Value) \
440 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iByte)] = (a_u8Value); } while (0)
441
442#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
443 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
444 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
445 } while (0)
446
447#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) \
448 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDwDst)] = (a_u128Value).au32[(a_iDwSrc)]; } while (0)
449#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
450 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
451#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
452 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
453#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
454 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
455 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
456 } while (0)
457#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
458 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
459#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
460 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
461#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
462 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
463#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
464 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
465#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
466 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
467#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
468 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
469#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
470 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
471#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
472 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
473#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
474 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
475 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
476 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
477 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
478 } while (0)
479
480#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
481 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
482 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
483 } while (0)
484#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
485 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
486 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
487 } while (0)
488#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
489 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
490 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
491 } while (0)
492#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
493 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
494 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
495 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
496 } while (0)
497#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
498 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
499 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
500 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
501 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
502 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
503 } while (0)
504
505#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
506#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
507 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
508 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
509 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
510 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
511 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
512 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
513 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
514 } while (0)
515#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
516 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
517 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
518 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
519 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
520 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
521 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
522 } while (0)
523#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
524 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
525 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
526 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
527 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
528 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
529 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
530 } while (0)
531#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
532 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
533 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
534 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
535 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
536 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
537 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
538 } while (0)
539
540#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
541 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
542#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
543 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
544#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
545 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
546#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
547 do { uintptr_t const iYRegTmp = (a_iYReg); \
548 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
549 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
550 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
551 } while (0)
552
553#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
554 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
555 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
556 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
557 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
558 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
559 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
560 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
561 } while (0)
562#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
563 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
564 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
565 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
566 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
567 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
568 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
569 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
570 } while (0)
571#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
572 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
573 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
574 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
575 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
576 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
577 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
578 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
579 } while (0)
580
581#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
582 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
583 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
584 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
585 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
586 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
587 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
588 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
589 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
590 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
591 } while (0)
592#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
593 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
594 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
595 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
596 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
597 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
598 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
599 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
600 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
601 } while (0)
602#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
603 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
604 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
605 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
606 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
607 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
608 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
609 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
610 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
611 } while (0)
612#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
613 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
614 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
615 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
616 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
617 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
618 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
619 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
620 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
621 } while (0)
622#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
623 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
624 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
625 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
626 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
627 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
628 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
629 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
630 } while (0)
631#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
632 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
633 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
634 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
635 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
636 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
637 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
638 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
639 } while (0)
640
641#ifndef IEM_WITH_SETJMP
642# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
643 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
644# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
645 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
646# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
647 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
648#else
649# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
650 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
651# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
652 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
653# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
654 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
655#endif
656
657#ifndef IEM_WITH_SETJMP
658# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
659 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
660# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
661 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
662# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
663 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
664#else
665# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
666 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
667# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
668 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
669# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
670 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
671#endif
672
673#ifndef IEM_WITH_SETJMP
674# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
675 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
676# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
677 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
678# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
679 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
680#else
681# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
682 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
683# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
684 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
685# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
686 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
687#endif
688
689#ifdef SOME_UNUSED_FUNCTION
690# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
691 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
692#endif
693
694#ifndef IEM_WITH_SETJMP
695# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
696 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
697# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
698 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
699# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
700 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
701# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
702 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
703#else
704# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
705 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
706# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
707 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
708# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
709 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
710# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
711 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
712#endif
713
714#ifndef IEM_WITH_SETJMP
715# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
716 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
717# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
718 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
719# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
720 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
721# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
722 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
723#else
724# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
725 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
726# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
727 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
728# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
729 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
730# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
731 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
732#endif
733
734#ifndef IEM_WITH_SETJMP
735# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
736 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
737# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
738 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
739# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
740 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
741
742# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
743 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
744# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
745 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
746# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
747 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
748# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
749 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
750# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
751 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
752#else
753# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
754 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
755# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
756 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
757# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
758 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
759
760# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
761 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
762# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
763 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
764# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
765 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
766# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
767 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
768# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
769 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
770#endif
771
772#ifndef IEM_WITH_SETJMP
773# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
774 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
775# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
776 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
777# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
778 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
779
780# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
781 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
782# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
783 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
784# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
785 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
786#else
787# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
788 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
789# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
790 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
791# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
792 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
793
794# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
795 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
796# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
797 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
798# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
799 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
800#endif
801
802
803
804#ifndef IEM_WITH_SETJMP
805# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
806 do { \
807 uint8_t u8Tmp; \
808 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
809 (a_u16Dst) = u8Tmp; \
810 } while (0)
811# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
812 do { \
813 uint8_t u8Tmp; \
814 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
815 (a_u32Dst) = u8Tmp; \
816 } while (0)
817# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
818 do { \
819 uint8_t u8Tmp; \
820 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
821 (a_u64Dst) = u8Tmp; \
822 } while (0)
823# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
824 do { \
825 uint16_t u16Tmp; \
826 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
827 (a_u32Dst) = u16Tmp; \
828 } while (0)
829# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
830 do { \
831 uint16_t u16Tmp; \
832 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
833 (a_u64Dst) = u16Tmp; \
834 } while (0)
835# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
836 do { \
837 uint32_t u32Tmp; \
838 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
839 (a_u64Dst) = u32Tmp; \
840 } while (0)
841#else /* IEM_WITH_SETJMP */
842# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
843 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
844# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
845 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
846# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
847 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
848# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
849 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
850# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
851 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
852# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
853 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
854#endif /* IEM_WITH_SETJMP */
855
856#ifndef IEM_WITH_SETJMP
857# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
858 do { \
859 uint8_t u8Tmp; \
860 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
861 (a_u16Dst) = (int8_t)u8Tmp; \
862 } while (0)
863# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
864 do { \
865 uint8_t u8Tmp; \
866 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
867 (a_u32Dst) = (int8_t)u8Tmp; \
868 } while (0)
869# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
870 do { \
871 uint8_t u8Tmp; \
872 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
873 (a_u64Dst) = (int8_t)u8Tmp; \
874 } while (0)
875# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
876 do { \
877 uint16_t u16Tmp; \
878 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
879 (a_u32Dst) = (int16_t)u16Tmp; \
880 } while (0)
881# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
882 do { \
883 uint16_t u16Tmp; \
884 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
885 (a_u64Dst) = (int16_t)u16Tmp; \
886 } while (0)
887# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
888 do { \
889 uint32_t u32Tmp; \
890 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
891 (a_u64Dst) = (int32_t)u32Tmp; \
892 } while (0)
893#else /* IEM_WITH_SETJMP */
894# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
895 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
896# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
897 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
898# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
899 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
900# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
901 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
902# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
903 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
904# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
905 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
906#endif /* IEM_WITH_SETJMP */
907
908#ifndef IEM_WITH_SETJMP
909# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
910 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
911# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
912 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
913# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
914 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
915# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
916 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
917#else
918# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
919 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
920# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
921 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
922# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
923 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
924# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
925 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
926#endif
927
928#ifndef IEM_WITH_SETJMP
929# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
930 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
931# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
932 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
933# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
934 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
935# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
936 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
937#else
938# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
939 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
940# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
941 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
942# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
943 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
944# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
945 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
946#endif
947
948#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
949#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
950#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
951#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
952#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
953#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
954#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
955 do { \
956 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
957 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
958 } while (0)
959#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
960 do { \
961 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
962 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
963 } while (0)
964
965#ifndef IEM_WITH_SETJMP
966# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
967 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
968# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
969 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
970#else
971# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
972 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
973# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
974 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
975#endif
976
977#ifndef IEM_WITH_SETJMP
978# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
979 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
980# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
981 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
982#else
983# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
984 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
985# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
986 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
987#endif
988
989
990#define IEM_MC_PUSH_U16(a_u16Value) \
991 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
992#define IEM_MC_PUSH_U32(a_u32Value) \
993 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
994#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
995 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
996#define IEM_MC_PUSH_U64(a_u64Value) \
997 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
998
999#define IEM_MC_POP_U16(a_pu16Value) \
1000 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1001#define IEM_MC_POP_U32(a_pu32Value) \
1002 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1003#define IEM_MC_POP_U64(a_pu64Value) \
1004 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1005
1006/** Maps guest memory for direct or bounce buffered access.
1007 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1008 * @remarks May return.
1009 */
1010#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1011 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1012 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1013
1014/** Maps guest memory for direct or bounce buffered access.
1015 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1016 * @remarks May return.
1017 */
1018#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1019 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1020 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1021
1022/** Commits the memory and unmaps the guest memory.
1023 * @remarks May return.
1024 */
1025#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1026 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1027
1028/** Commits the memory and unmaps the guest memory unless the FPU status word
1029 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1030 * that would cause FLD not to store.
1031 *
1032 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1033 * store, while \#P will not.
1034 *
1035 * @remarks May in theory return - for now.
1036 */
1037#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1038 do { \
1039 if ( !(a_u16FSW & X86_FSW_ES) \
1040 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1041 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1042 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1043 } while (0)
1044
1045/** Calculate efficient address from R/M. */
1046#ifndef IEM_WITH_SETJMP
1047# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1048 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1049#else
1050# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1051 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1052#endif
1053
1054#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1055#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1056#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1057#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1058#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1059#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1060#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1061
1062/**
1063 * Defers the rest of the instruction emulation to a C implementation routine
1064 * and returns, only taking the standard parameters.
1065 *
1066 * @param a_pfnCImpl The pointer to the C routine.
1067 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1068 */
1069#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1070
1071/**
1072 * Defers the rest of instruction emulation to a C implementation routine and
1073 * returns, taking one argument in addition to the standard ones.
1074 *
1075 * @param a_pfnCImpl The pointer to the C routine.
1076 * @param a0 The argument.
1077 */
1078#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1079
1080/**
1081 * Defers the rest of the instruction emulation to a C implementation routine
1082 * and returns, taking two arguments in addition to the standard ones.
1083 *
1084 * @param a_pfnCImpl The pointer to the C routine.
1085 * @param a0 The first extra argument.
1086 * @param a1 The second extra argument.
1087 */
1088#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1089
1090/**
1091 * Defers the rest of the instruction emulation to a C implementation routine
1092 * and returns, taking three arguments in addition to the standard ones.
1093 *
1094 * @param a_pfnCImpl The pointer to the C routine.
1095 * @param a0 The first extra argument.
1096 * @param a1 The second extra argument.
1097 * @param a2 The third extra argument.
1098 */
1099#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1100
1101/**
1102 * Defers the rest of the instruction emulation to a C implementation routine
1103 * and returns, taking four arguments in addition to the standard ones.
1104 *
1105 * @param a_pfnCImpl The pointer to the C routine.
1106 * @param a0 The first extra argument.
1107 * @param a1 The second extra argument.
1108 * @param a2 The third extra argument.
1109 * @param a3 The fourth extra argument.
1110 */
1111#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1112
1113/**
1114 * Defers the rest of the instruction emulation to a C implementation routine
1115 * and returns, taking two arguments in addition to the standard ones.
1116 *
1117 * @param a_pfnCImpl The pointer to the C routine.
1118 * @param a0 The first extra argument.
1119 * @param a1 The second extra argument.
1120 * @param a2 The third extra argument.
1121 * @param a3 The fourth extra argument.
1122 * @param a4 The fifth extra argument.
1123 */
1124#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1125
1126/**
1127 * Defers the entire instruction emulation to a C implementation routine and
1128 * returns, only taking the standard parameters.
1129 *
1130 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1131 *
1132 * @param a_pfnCImpl The pointer to the C routine.
1133 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1134 */
1135#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1136
1137/**
1138 * Defers the entire instruction emulation to a C implementation routine and
1139 * returns, taking one argument in addition to the standard ones.
1140 *
1141 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1142 *
1143 * @param a_pfnCImpl The pointer to the C routine.
1144 * @param a0 The argument.
1145 */
1146#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1147
1148/**
1149 * Defers the entire instruction emulation to a C implementation routine and
1150 * returns, taking two arguments in addition to the standard ones.
1151 *
1152 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1153 *
1154 * @param a_pfnCImpl The pointer to the C routine.
1155 * @param a0 The first extra argument.
1156 * @param a1 The second extra argument.
1157 */
1158#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1159
1160/**
1161 * Defers the entire instruction emulation to a C implementation routine and
1162 * returns, taking three arguments in addition to the standard ones.
1163 *
1164 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1165 *
1166 * @param a_pfnCImpl The pointer to the C routine.
1167 * @param a0 The first extra argument.
1168 * @param a1 The second extra argument.
1169 * @param a2 The third extra argument.
1170 */
1171#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1172
1173/**
1174 * Calls a FPU assembly implementation taking one visible argument.
1175 *
1176 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1177 * @param a0 The first extra argument.
1178 */
1179#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1180 do { \
1181 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1182 } while (0)
1183
1184/**
1185 * Calls a FPU assembly implementation taking two visible arguments.
1186 *
1187 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1188 * @param a0 The first extra argument.
1189 * @param a1 The second extra argument.
1190 */
1191#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1192 do { \
1193 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1194 } while (0)
1195
1196/**
1197 * Calls a FPU assembly implementation taking three visible arguments.
1198 *
1199 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1200 * @param a0 The first extra argument.
1201 * @param a1 The second extra argument.
1202 * @param a2 The third extra argument.
1203 */
1204#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1205 do { \
1206 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1207 } while (0)
1208
1209#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1210 do { \
1211 (a_FpuData).FSW = (a_FSW); \
1212 (a_FpuData).r80Result = *(a_pr80Value); \
1213 } while (0)
1214
1215/** Pushes FPU result onto the stack. */
1216#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1217 iemFpuPushResult(pVCpu, &a_FpuData)
1218/** Pushes FPU result onto the stack and sets the FPUDP. */
1219#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1220 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1221
1222/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1223#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1224 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1225
1226/** Stores FPU result in a stack register. */
1227#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1228 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1229/** Stores FPU result in a stack register and pops the stack. */
1230#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1231 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1232/** Stores FPU result in a stack register and sets the FPUDP. */
1233#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1234 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1235/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1236 * stack. */
1237#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1238 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1239
1240/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1241#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1242 iemFpuUpdateOpcodeAndIp(pVCpu)
1243/** Free a stack register (for FFREE and FFREEP). */
1244#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1245 iemFpuStackFree(pVCpu, a_iStReg)
1246/** Increment the FPU stack pointer. */
1247#define IEM_MC_FPU_STACK_INC_TOP() \
1248 iemFpuStackIncTop(pVCpu)
1249/** Decrement the FPU stack pointer. */
1250#define IEM_MC_FPU_STACK_DEC_TOP() \
1251 iemFpuStackDecTop(pVCpu)
1252
1253/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1254#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1255 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1256/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1257#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1258 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1259/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1260#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1261 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1262/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1263#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1264 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1265/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1266 * stack. */
1267#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1268 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1269/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1270#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1271 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1272
1273/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1274#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1275 iemFpuStackUnderflow(pVCpu, a_iStDst)
1276/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1277 * stack. */
1278#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1279 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1280/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1281 * FPUDS. */
1282#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1283 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1284/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1285 * FPUDS. Pops stack. */
1286#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1287 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1288/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1289 * stack twice. */
1290#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1291 iemFpuStackUnderflowThenPopPop(pVCpu)
1292/** Raises a FPU stack underflow exception for an instruction pushing a result
1293 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1294#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1295 iemFpuStackPushUnderflow(pVCpu)
1296/** Raises a FPU stack underflow exception for an instruction pushing a result
1297 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1298#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1299 iemFpuStackPushUnderflowTwo(pVCpu)
1300
1301/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1302 * FPUIP, FPUCS and FOP. */
1303#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1304 iemFpuStackPushOverflow(pVCpu)
1305/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1306 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1307#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1308 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1309/** Prepares for using the FPU state.
1310 * Ensures that we can use the host FPU in the current context (RC+R0.
1311 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1312#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1313/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1314#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1315/** Actualizes the guest FPU state so it can be accessed and modified. */
1316#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1317
1318/** Stores SSE SIMD result updating MXCSR. */
1319#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1320 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1321/** Updates MXCSR. */
1322#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1323 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1324
1325/** Prepares for using the SSE state.
1326 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1327 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1328#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1329/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1330#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1331/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1332#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1333
1334/** Prepares for using the AVX state.
1335 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1336 * Ensures the guest AVX state in the CPUMCTX is up to date.
1337 * @note This will include the AVX512 state too when support for it is added
1338 * due to the zero extending feature of VEX instruction. */
1339#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1340/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1341#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1342/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1343#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1344
1345/**
1346 * Calls a MMX assembly implementation taking two visible arguments.
1347 *
1348 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1349 * @param a0 The first extra argument.
1350 * @param a1 The second extra argument.
1351 */
1352#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1353 do { \
1354 IEM_MC_PREPARE_FPU_USAGE(); \
1355 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1356 } while (0)
1357
1358/**
1359 * Calls a MMX assembly implementation taking three visible arguments.
1360 *
1361 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1362 * @param a0 The first extra argument.
1363 * @param a1 The second extra argument.
1364 * @param a2 The third extra argument.
1365 */
1366#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1367 do { \
1368 IEM_MC_PREPARE_FPU_USAGE(); \
1369 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1370 } while (0)
1371
1372
1373/**
1374 * Calls a SSE assembly implementation taking two visible arguments.
1375 *
1376 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1377 * @param a0 The first extra argument.
1378 * @param a1 The second extra argument.
1379 */
1380#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1381 do { \
1382 IEM_MC_PREPARE_SSE_USAGE(); \
1383 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1384 } while (0)
1385
1386/**
1387 * Calls a SSE assembly implementation taking three visible arguments.
1388 *
1389 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1390 * @param a0 The first extra argument.
1391 * @param a1 The second extra argument.
1392 * @param a2 The third extra argument.
1393 */
1394#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1395 do { \
1396 IEM_MC_PREPARE_SSE_USAGE(); \
1397 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1398 } while (0)
1399
1400
1401/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1402 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1403#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1404 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1405
1406/**
1407 * Calls a AVX assembly implementation taking two visible arguments.
1408 *
1409 * There is one implicit zero'th argument, a pointer to the extended state.
1410 *
1411 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1412 * @param a1 The first extra argument.
1413 * @param a2 The second extra argument.
1414 */
1415#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1416 do { \
1417 IEM_MC_PREPARE_AVX_USAGE(); \
1418 a_pfnAImpl(pXState, (a1), (a2)); \
1419 } while (0)
1420
1421/**
1422 * Calls a AVX assembly implementation taking three visible arguments.
1423 *
1424 * There is one implicit zero'th argument, a pointer to the extended state.
1425 *
1426 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1427 * @param a1 The first extra argument.
1428 * @param a2 The second extra argument.
1429 * @param a3 The third extra argument.
1430 */
1431#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1432 do { \
1433 IEM_MC_PREPARE_AVX_USAGE(); \
1434 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1435 } while (0)
1436
1437/** @note Not for IOPL or IF testing. */
1438#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1439/** @note Not for IOPL or IF testing. */
1440#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1441/** @note Not for IOPL or IF testing. */
1442#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1443/** @note Not for IOPL or IF testing. */
1444#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1445/** @note Not for IOPL or IF testing. */
1446#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1447 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1448 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1449/** @note Not for IOPL or IF testing. */
1450#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1451 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1452 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1453/** @note Not for IOPL or IF testing. */
1454#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1455 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1456 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1457 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1458/** @note Not for IOPL or IF testing. */
1459#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1460 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1461 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1462 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1463#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1464#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1465#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1466/** @note Not for IOPL or IF testing. */
1467#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1468 if ( pVCpu->cpum.GstCtx.cx != 0 \
1469 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1470/** @note Not for IOPL or IF testing. */
1471#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1472 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1473 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1474/** @note Not for IOPL or IF testing. */
1475#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1476 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1477 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1478/** @note Not for IOPL or IF testing. */
1479#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1480 if ( pVCpu->cpum.GstCtx.cx != 0 \
1481 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1482/** @note Not for IOPL or IF testing. */
1483#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1484 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1485 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1486/** @note Not for IOPL or IF testing. */
1487#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1488 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1489 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1490#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1491#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1492
1493#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1494 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1495#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1496 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1497#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1498 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1499#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1500 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1501#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1502 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1503#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1504 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1505#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1506 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1507#define IEM_MC_IF_FCW_IM() \
1508 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1509#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1510 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1511 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1512
1513#define IEM_MC_ELSE() } else {
1514#define IEM_MC_ENDIF() } do {} while (0)
1515
1516/** @} */
1517
1518#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1519
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