VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 99342

Last change on this file since 99342 was 99342, checked in by vboxsync, 20 months ago

VMM/IEM: IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT -> IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT, since the CPUID check was removed they are identical. bugref:10369
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 82.0 KB
Line 
1/* $Id: IEMMc.h 99342 2023-04-07 12:43:12Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44
45/** Internal macro. */
46#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
47 do \
48 { \
49 VBOXSTRICTRC rcStrict2 = a_Expr; \
50 if (rcStrict2 != VINF_SUCCESS) \
51 return rcStrict2; \
52 } while (0)
53
54
55/** Advances RIP, finishes the instruction and returns.
56 * This may include raising debug exceptions and such. */
57#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
58/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
59#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
60 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
61/** Sets RIP (may trigger \#GP), finishes the instruction and returns.
62 * @note only usable in 16-bit op size mode. */
63#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
64 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
65/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
66#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
67 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
68/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
69#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJumpU16AndFinishClearningRF((pVCpu), (a_u16NewIP))
70/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
71#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJumpU32AndFinishClearningRF((pVCpu), (a_u32NewIP))
72/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
73#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJumpU64AndFinishClearningRF((pVCpu), (a_u64NewIP))
74
75#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
76#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
77 do { \
78 if (!(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))) \
79 { } else return iemRaiseDeviceNotAvailable(pVCpu); \
80 } while (0)
81#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
82 do { \
83 if (!((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS))) \
84 { } else return iemRaiseDeviceNotAvailable(pVCpu); \
85 } while (0)
86#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
87 do { \
88 if (!(pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES)) \
89 { } else return iemRaiseMathFault(pVCpu); \
90 } while (0)
91#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
92 do { \
93 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
94 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)) \
95 return iemRaiseUndefinedOpcode(pVCpu); \
96 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
97 return iemRaiseDeviceNotAvailable(pVCpu); \
98 } while (0)
99#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
100 do { \
101 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
102 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
103 return iemRaiseUndefinedOpcode(pVCpu); \
104 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
105 return iemRaiseDeviceNotAvailable(pVCpu); \
106 } while (0)
107#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
108 do { \
109 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
110 return iemRaiseUndefinedOpcode(pVCpu); \
111 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
112 return iemRaiseDeviceNotAvailable(pVCpu); \
113 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
114 return iemRaiseMathFault(pVCpu); \
115 } while (0)
116#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
117 do { \
118 if (pVCpu->iem.s.uCpl != 0) \
119 return iemRaiseGeneralProtectionFault0(pVCpu); \
120 } while (0)
121#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
122 do { \
123 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
124 else return iemRaiseGeneralProtectionFault0(pVCpu); \
125 } while (0)
126#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
127 do { \
128 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
129 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
130 return iemRaiseUndefinedOpcode(pVCpu); \
131 } while (0)
132#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
133 do { \
134 if (!IEM_IS_CANONICAL(a_u64Addr)) \
135 return iemRaiseGeneralProtectionFault0(pVCpu); \
136 } while (0)
137#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
138 do { \
139 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
140 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) \
141 { \
142 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
143 return iemRaiseSimdFpException(pVCpu); \
144 return iemRaiseUndefinedOpcode(pVCpu); \
145 } \
146 } while (0)
147#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
148 do { \
149 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
150 return iemRaiseSimdFpException(pVCpu); \
151 return iemRaiseUndefinedOpcode(pVCpu); \
152 } while (0)
153#define IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT() \
154 do { \
155 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
156 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
157 return iemRaiseUndefinedOpcode(pVCpu); \
158 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
159 return iemRaiseDeviceNotAvailable(pVCpu); \
160 } while (0)
161
162
163#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
164#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
165#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
166#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
167#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
168#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
169#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
170 uint32_t a_Name; \
171 uint32_t *a_pName = &a_Name
172#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
173 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
174
175#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
176#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
177#define IEM_MC_ASSIGN_U8_SX_U64(a_u64VarOrArg, a_u8CVariableOrConst) \
178 (a_u64VarOrArg) = (int8_t)(a_u8CVariableOrConst)
179#define IEM_MC_ASSIGN_U32_SX_U64(a_u64VarOrArg, a_u32CVariableOrConst) \
180 (a_u64VarOrArg) = (int32_t)(a_u32CVariableOrConst)
181
182#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
183#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
184#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
185#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
186#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
187#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
188#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
189#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
190#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
191#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
192#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
193#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
194#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
195#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
196#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
197#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
198#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
199#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
200 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
201 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
202 } while (0)
203#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
204 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
205 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
206 } while (0)
207#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
208 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
209 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
210 } while (0)
211/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
212#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
213 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
214 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
215 } while (0)
216#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
217 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
218 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
219 } while (0)
220/** @note Not for IOPL or IF testing or modification. */
221#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
222#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
223#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
224#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
225
226#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
227#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
228#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
229#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
230#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
231#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
232#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
233#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
234#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
235#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
236#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
237/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
238#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
239 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
240 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
241 } while (0)
242#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
243 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
244 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
245 } while (0)
246#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
247 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
248
249
250#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
251#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
252/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
253 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
254#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
255#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
256#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
257#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
258#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
259#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
260/** @note Not for IOPL or IF testing or modification.
261 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
262#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
263#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
264
265#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
266#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
267#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
268 do { \
269 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
270 *pu32Reg += (a_u32Value); \
271 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
272 } while (0)
273#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
274
275#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
276#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
277#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
278 do { \
279 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
280 *pu32Reg -= (a_u32Value); \
281 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
282 } while (0)
283#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
284#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
285
286#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
287#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
288#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
289#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
290#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
291#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
292#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
293
294#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
295#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
296#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
297#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
298
299#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
300#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
301#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
302
303#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
304#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
305#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
306
307#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
308#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
309#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
310
311#define IEM_MC_SHR_LOCAL_U8(a_u8Local, a_cShift) do { (a_u8Local) >>= (a_cShift); } while (0)
312
313#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
314#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
315#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
316
317#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
318
319#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
320
321#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
322#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
323#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
324 do { \
325 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
326 *pu32Reg &= (a_u32Value); \
327 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
328 } while (0)
329#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
330
331#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
332#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
333#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
334 do { \
335 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
336 *pu32Reg |= (a_u32Value); \
337 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
338 } while (0)
339#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
340
341#define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) (a_u16Local) = RT_BSWAP_U16((a_u16Local));
342#define IEM_MC_BSWAP_LOCAL_U32(a_u32Local) (a_u32Local) = RT_BSWAP_U32((a_u32Local));
343#define IEM_MC_BSWAP_LOCAL_U64(a_u64Local) (a_u64Local) = RT_BSWAP_U64((a_u64Local));
344
345/** @note Not for IOPL or IF modification. */
346#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
347/** @note Not for IOPL or IF modification. */
348#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
349/** @note Not for IOPL or IF modification. */
350#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
351
352#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
353
354/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
355#define IEM_MC_FPU_TO_MMX_MODE() do { \
356 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
357 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
358 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
359 } while (0)
360
361/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
362#define IEM_MC_FPU_FROM_MMX_MODE() do { \
363 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
364 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
365 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
366 } while (0)
367
368#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
369 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
370#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
371 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
372#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
373 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
374 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
375 } while (0)
376#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
377 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
378 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
379 } while (0)
380#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
381 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
382#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
383 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
384#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
385 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
386#define IEM_MC_MODIFIED_MREG(a_iMReg) \
387 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
388#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
389 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
390
391#define IEM_MC_CLEAR_XREG_U32_MASK(a_iXReg, a_bMask) \
392 do { if ((a_bMask) & (1 << 0)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = 0; \
393 if ((a_bMask) & (1 << 1)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[1] = 0; \
394 if ((a_bMask) & (1 << 2)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[2] = 0; \
395 if ((a_bMask) & (1 << 3)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[3] = 0; \
396 } while (0)
397#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
398 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
399 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
400 } while (0)
401#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
402 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
403 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
404 } while (0)
405#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) \
406 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQWord)]; } while (0)
407#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg, a_iDWord) \
408 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDWord)]; } while (0)
409#define IEM_MC_FETCH_XREG_U16(a_u16Value, a_iXReg, a_iWord) \
410 do { (a_u16Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iWord)]; } while (0)
411#define IEM_MC_FETCH_XREG_U8( a_u8Value, a_iXReg, a_iByte) \
412 do { (a_u8Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iByte)]; } while (0)
413#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
414 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
415 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
416 } while (0)
417#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
418 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
419 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
420 } while (0)
421#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
422 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
423#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
424 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
425#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) \
426 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_u64Value); } while (0)
427#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) \
428 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_u32Value); } while (0)
429#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u16Value) \
430 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iWord)] = (a_u16Value); } while (0)
431#define IEM_MC_STORE_XREG_U8(a_iXReg, a_iByte, a_u8Value) \
432 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iByte)] = (a_u8Value); } while (0)
433
434#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
435 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
436 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
437 } while (0)
438
439#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) \
440 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDwDst)] = (a_u128Value).au32[(a_iDwSrc)]; } while (0)
441#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
442 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
443#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
444 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
445#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
446 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
447 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
448 } while (0)
449#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
450 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
451#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
452 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
453#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
454 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
455#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
456 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
457#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
458 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
459#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
460 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
461#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
462 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
463#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
464 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
465#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
466 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
467 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
468 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
469 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
470 } while (0)
471
472#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
473 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
474 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
475 } while (0)
476#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
477 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
478 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
479 } while (0)
480#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
481 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
482 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
483 } while (0)
484#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
485 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
486 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
487 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
488 } while (0)
489#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
490 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
491 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
492 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
493 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
494 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
495 } while (0)
496
497#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
498#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
499 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
500 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
501 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
502 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
503 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
504 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
505 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
506 } while (0)
507#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
508 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
509 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
510 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
511 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
512 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
513 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
514 } while (0)
515#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
516 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
517 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
518 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
519 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
520 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
521 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
522 } while (0)
523#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
524 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
525 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
526 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
527 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
528 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
529 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
530 } while (0)
531
532#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
533 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
534#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
535 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
536#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
537 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
538#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
539 do { uintptr_t const iYRegTmp = (a_iYReg); \
540 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
541 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
542 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
543 } while (0)
544
545#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
546 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
547 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
548 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
549 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
550 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
551 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
552 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
553 } while (0)
554#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
555 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
556 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
557 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
558 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
559 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
560 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
561 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
562 } while (0)
563#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
564 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
565 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
566 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
567 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
568 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
569 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
570 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
571 } while (0)
572
573#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
574 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
575 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
576 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
577 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
578 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
579 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
580 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
581 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
582 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
583 } while (0)
584#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
585 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
586 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
587 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
588 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
589 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
590 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
591 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
592 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
593 } while (0)
594#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
595 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
596 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
597 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
598 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
599 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
600 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
601 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
602 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
603 } while (0)
604#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
605 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
606 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
607 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
608 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
609 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
610 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
611 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
612 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
613 } while (0)
614#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
615 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
616 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
617 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
618 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
619 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
620 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
621 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
622 } while (0)
623#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
624 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
625 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
626 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
627 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
628 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
629 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
630 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
631 } while (0)
632
633#ifndef IEM_WITH_SETJMP
634# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
635 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
636# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
637 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
638# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
639 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
640#else
641# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
642 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
643# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
644 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
645# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
646 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
647#endif
648
649#ifndef IEM_WITH_SETJMP
650# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
651 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
652# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
653 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
654# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
655 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
656#else
657# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
658 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
659# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
660 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
661# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
662 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
663#endif
664
665#ifndef IEM_WITH_SETJMP
666# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
667 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
668# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
669 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
670# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
671 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
672#else
673# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
674 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
675# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
676 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
677# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
678 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
679#endif
680
681#ifdef SOME_UNUSED_FUNCTION
682# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
683 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
684#endif
685
686#ifndef IEM_WITH_SETJMP
687# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
688 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
689# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
690 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
691# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
692 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
693# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
694 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
695#else
696# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
697 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
698# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
699 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
700# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
701 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
702# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
703 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
704#endif
705
706#ifndef IEM_WITH_SETJMP
707# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
708 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
709# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
710 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
711# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
712 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
713# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
714 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
715#else
716# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
717 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
718# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
719 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
720# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
721 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
722# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
723 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
724#endif
725
726#ifndef IEM_WITH_SETJMP
727# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
728 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
729# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
730 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
731# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
732 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
733
734# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
735 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
736# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
737 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
738# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
739 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
740# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
741 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
742# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
743 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
744#else
745# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
746 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
747# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
748 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
749# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
750 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
751
752# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
753 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
754# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
755 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
756# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
757 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
758# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
759 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
760# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
761 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
762#endif
763
764#ifndef IEM_WITH_SETJMP
765# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
766 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
767# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
768 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
769# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
770 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
771
772# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
773 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
774# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
775 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
776# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
777 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
778#else
779# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
780 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
781# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
782 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
783# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
784 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
785
786# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
787 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
788# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
789 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
790# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
791 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
792#endif
793
794
795
796#ifndef IEM_WITH_SETJMP
797# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
798 do { \
799 uint8_t u8Tmp; \
800 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
801 (a_u16Dst) = u8Tmp; \
802 } while (0)
803# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
804 do { \
805 uint8_t u8Tmp; \
806 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
807 (a_u32Dst) = u8Tmp; \
808 } while (0)
809# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
810 do { \
811 uint8_t u8Tmp; \
812 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
813 (a_u64Dst) = u8Tmp; \
814 } while (0)
815# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
816 do { \
817 uint16_t u16Tmp; \
818 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
819 (a_u32Dst) = u16Tmp; \
820 } while (0)
821# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
822 do { \
823 uint16_t u16Tmp; \
824 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
825 (a_u64Dst) = u16Tmp; \
826 } while (0)
827# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
828 do { \
829 uint32_t u32Tmp; \
830 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
831 (a_u64Dst) = u32Tmp; \
832 } while (0)
833#else /* IEM_WITH_SETJMP */
834# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
835 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
836# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
837 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
838# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
839 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
840# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
841 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
842# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
843 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
844# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
845 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
846#endif /* IEM_WITH_SETJMP */
847
848#ifndef IEM_WITH_SETJMP
849# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
850 do { \
851 uint8_t u8Tmp; \
852 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
853 (a_u16Dst) = (int8_t)u8Tmp; \
854 } while (0)
855# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
856 do { \
857 uint8_t u8Tmp; \
858 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
859 (a_u32Dst) = (int8_t)u8Tmp; \
860 } while (0)
861# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
862 do { \
863 uint8_t u8Tmp; \
864 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
865 (a_u64Dst) = (int8_t)u8Tmp; \
866 } while (0)
867# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
868 do { \
869 uint16_t u16Tmp; \
870 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
871 (a_u32Dst) = (int16_t)u16Tmp; \
872 } while (0)
873# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
874 do { \
875 uint16_t u16Tmp; \
876 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
877 (a_u64Dst) = (int16_t)u16Tmp; \
878 } while (0)
879# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
880 do { \
881 uint32_t u32Tmp; \
882 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
883 (a_u64Dst) = (int32_t)u32Tmp; \
884 } while (0)
885#else /* IEM_WITH_SETJMP */
886# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
887 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
888# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
889 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
890# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
891 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
892# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
893 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
894# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
895 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
896# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
897 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
898#endif /* IEM_WITH_SETJMP */
899
900#ifndef IEM_WITH_SETJMP
901# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
902 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
903# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
904 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
905# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
906 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
907# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
908 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
909#else
910# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
911 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
912# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
913 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
914# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
915 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
916# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
917 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
918#endif
919
920#ifndef IEM_WITH_SETJMP
921# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
922 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
923# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
924 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
925# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
926 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
927# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
928 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
929#else
930# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
931 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
932# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
933 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
934# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
935 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
936# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
937 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
938#endif
939
940#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
941#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
942#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
943#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
944#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
945#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
946#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
947 do { \
948 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
949 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
950 } while (0)
951#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
952 do { \
953 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
954 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
955 } while (0)
956
957#ifndef IEM_WITH_SETJMP
958# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
959 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
960# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
961 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
962#else
963# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
964 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
965# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
966 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
967#endif
968
969#ifndef IEM_WITH_SETJMP
970# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
971 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
972# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
973 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
974#else
975# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
976 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
977# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
978 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
979#endif
980
981
982#define IEM_MC_PUSH_U16(a_u16Value) \
983 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
984#define IEM_MC_PUSH_U32(a_u32Value) \
985 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
986#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
987 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
988#define IEM_MC_PUSH_U64(a_u64Value) \
989 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
990
991#define IEM_MC_POP_U16(a_pu16Value) \
992 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
993#define IEM_MC_POP_U32(a_pu32Value) \
994 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
995#define IEM_MC_POP_U64(a_pu64Value) \
996 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
997
998/** Maps guest memory for direct or bounce buffered access.
999 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1000 * @remarks May return.
1001 */
1002#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1003 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1004 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1005
1006/** Maps guest memory for direct or bounce buffered access.
1007 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1008 * @remarks May return.
1009 */
1010#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1011 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1012 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1013
1014/** Commits the memory and unmaps the guest memory.
1015 * @remarks May return.
1016 */
1017#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1018 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1019
1020/** Commits the memory and unmaps the guest memory unless the FPU status word
1021 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1022 * that would cause FLD not to store.
1023 *
1024 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1025 * store, while \#P will not.
1026 *
1027 * @remarks May in theory return - for now.
1028 */
1029#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1030 do { \
1031 if ( !(a_u16FSW & X86_FSW_ES) \
1032 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1033 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1034 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1035 } while (0)
1036
1037/** Calculate efficient address from R/M. */
1038#ifndef IEM_WITH_SETJMP
1039# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1040 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1041#else
1042# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1043 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1044#endif
1045
1046#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1047#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1048#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1049#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1050#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1051#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1052#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1053
1054/**
1055 * Defers the rest of the instruction emulation to a C implementation routine
1056 * and returns, only taking the standard parameters.
1057 *
1058 * @param a_pfnCImpl The pointer to the C routine.
1059 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1060 */
1061#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1062
1063/**
1064 * Defers the rest of instruction emulation to a C implementation routine and
1065 * returns, taking one argument in addition to the standard ones.
1066 *
1067 * @param a_pfnCImpl The pointer to the C routine.
1068 * @param a0 The argument.
1069 */
1070#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1071
1072/**
1073 * Defers the rest of the instruction emulation to a C implementation routine
1074 * and returns, taking two arguments in addition to the standard ones.
1075 *
1076 * @param a_pfnCImpl The pointer to the C routine.
1077 * @param a0 The first extra argument.
1078 * @param a1 The second extra argument.
1079 */
1080#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1081
1082/**
1083 * Defers the rest of the instruction emulation to a C implementation routine
1084 * and returns, taking three arguments in addition to the standard ones.
1085 *
1086 * @param a_pfnCImpl The pointer to the C routine.
1087 * @param a0 The first extra argument.
1088 * @param a1 The second extra argument.
1089 * @param a2 The third extra argument.
1090 */
1091#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1092
1093/**
1094 * Defers the rest of the instruction emulation to a C implementation routine
1095 * and returns, taking four arguments in addition to the standard ones.
1096 *
1097 * @param a_pfnCImpl The pointer to the C routine.
1098 * @param a0 The first extra argument.
1099 * @param a1 The second extra argument.
1100 * @param a2 The third extra argument.
1101 * @param a3 The fourth extra argument.
1102 */
1103#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1104
1105/**
1106 * Defers the rest of the instruction emulation to a C implementation routine
1107 * and returns, taking two arguments in addition to the standard ones.
1108 *
1109 * @param a_pfnCImpl The pointer to the C routine.
1110 * @param a0 The first extra argument.
1111 * @param a1 The second extra argument.
1112 * @param a2 The third extra argument.
1113 * @param a3 The fourth extra argument.
1114 * @param a4 The fifth extra argument.
1115 */
1116#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1117
1118/**
1119 * Defers the entire instruction emulation to a C implementation routine and
1120 * returns, only taking the standard parameters.
1121 *
1122 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1123 *
1124 * @param a_pfnCImpl The pointer to the C routine.
1125 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1126 */
1127#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1128
1129/**
1130 * Defers the entire instruction emulation to a C implementation routine and
1131 * returns, taking one argument in addition to the standard ones.
1132 *
1133 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1134 *
1135 * @param a_pfnCImpl The pointer to the C routine.
1136 * @param a0 The argument.
1137 */
1138#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1139
1140/**
1141 * Defers the entire instruction emulation to a C implementation routine and
1142 * returns, taking two arguments in addition to the standard ones.
1143 *
1144 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1145 *
1146 * @param a_pfnCImpl The pointer to the C routine.
1147 * @param a0 The first extra argument.
1148 * @param a1 The second extra argument.
1149 */
1150#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1151
1152/**
1153 * Defers the entire instruction emulation to a C implementation routine and
1154 * returns, taking three arguments in addition to the standard ones.
1155 *
1156 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1157 *
1158 * @param a_pfnCImpl The pointer to the C routine.
1159 * @param a0 The first extra argument.
1160 * @param a1 The second extra argument.
1161 * @param a2 The third extra argument.
1162 */
1163#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1164
1165/**
1166 * Calls a FPU assembly implementation taking one visible argument.
1167 *
1168 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1169 * @param a0 The first extra argument.
1170 */
1171#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1172 do { \
1173 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1174 } while (0)
1175
1176/**
1177 * Calls a FPU assembly implementation taking two visible arguments.
1178 *
1179 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1180 * @param a0 The first extra argument.
1181 * @param a1 The second extra argument.
1182 */
1183#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1184 do { \
1185 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1186 } while (0)
1187
1188/**
1189 * Calls a FPU assembly implementation taking three visible arguments.
1190 *
1191 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1192 * @param a0 The first extra argument.
1193 * @param a1 The second extra argument.
1194 * @param a2 The third extra argument.
1195 */
1196#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1197 do { \
1198 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1199 } while (0)
1200
1201#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1202 do { \
1203 (a_FpuData).FSW = (a_FSW); \
1204 (a_FpuData).r80Result = *(a_pr80Value); \
1205 } while (0)
1206
1207/** Pushes FPU result onto the stack. */
1208#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1209 iemFpuPushResult(pVCpu, &a_FpuData)
1210/** Pushes FPU result onto the stack and sets the FPUDP. */
1211#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1212 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1213
1214/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1215#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1216 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1217
1218/** Stores FPU result in a stack register. */
1219#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1220 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1221/** Stores FPU result in a stack register and pops the stack. */
1222#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1223 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1224/** Stores FPU result in a stack register and sets the FPUDP. */
1225#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1226 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1227/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1228 * stack. */
1229#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1230 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1231
1232/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1233#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1234 iemFpuUpdateOpcodeAndIp(pVCpu)
1235/** Free a stack register (for FFREE and FFREEP). */
1236#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1237 iemFpuStackFree(pVCpu, a_iStReg)
1238/** Increment the FPU stack pointer. */
1239#define IEM_MC_FPU_STACK_INC_TOP() \
1240 iemFpuStackIncTop(pVCpu)
1241/** Decrement the FPU stack pointer. */
1242#define IEM_MC_FPU_STACK_DEC_TOP() \
1243 iemFpuStackDecTop(pVCpu)
1244
1245/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1246#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1247 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1248/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1249#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1250 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1251/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1252#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1253 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1254/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1255#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1256 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1257/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1258 * stack. */
1259#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1260 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1261/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1262#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1263 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1264
1265/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1266#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1267 iemFpuStackUnderflow(pVCpu, a_iStDst)
1268/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1269 * stack. */
1270#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1271 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1272/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1273 * FPUDS. */
1274#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1275 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1276/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1277 * FPUDS. Pops stack. */
1278#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1279 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1280/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1281 * stack twice. */
1282#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1283 iemFpuStackUnderflowThenPopPop(pVCpu)
1284/** Raises a FPU stack underflow exception for an instruction pushing a result
1285 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1286#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1287 iemFpuStackPushUnderflow(pVCpu)
1288/** Raises a FPU stack underflow exception for an instruction pushing a result
1289 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1290#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1291 iemFpuStackPushUnderflowTwo(pVCpu)
1292
1293/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1294 * FPUIP, FPUCS and FOP. */
1295#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1296 iemFpuStackPushOverflow(pVCpu)
1297/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1298 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1299#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1300 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1301/** Prepares for using the FPU state.
1302 * Ensures that we can use the host FPU in the current context (RC+R0.
1303 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1304#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1305/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1306#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1307/** Actualizes the guest FPU state so it can be accessed and modified. */
1308#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1309
1310/** Stores SSE SIMD result updating MXCSR. */
1311#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1312 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1313/** Updates MXCSR. */
1314#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1315 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1316
1317/** Prepares for using the SSE state.
1318 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1319 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1320#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1321/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1322#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1323/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1324#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1325
1326/** Prepares for using the AVX state.
1327 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1328 * Ensures the guest AVX state in the CPUMCTX is up to date.
1329 * @note This will include the AVX512 state too when support for it is added
1330 * due to the zero extending feature of VEX instruction. */
1331#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1332/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1333#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1334/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1335#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1336
1337/**
1338 * Calls a MMX assembly implementation taking two visible arguments.
1339 *
1340 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1341 * @param a0 The first extra argument.
1342 * @param a1 The second extra argument.
1343 */
1344#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1345 do { \
1346 IEM_MC_PREPARE_FPU_USAGE(); \
1347 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1348 } while (0)
1349
1350/**
1351 * Calls a MMX assembly implementation taking three visible arguments.
1352 *
1353 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1354 * @param a0 The first extra argument.
1355 * @param a1 The second extra argument.
1356 * @param a2 The third extra argument.
1357 */
1358#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1359 do { \
1360 IEM_MC_PREPARE_FPU_USAGE(); \
1361 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1362 } while (0)
1363
1364
1365/**
1366 * Calls a SSE assembly implementation taking two visible arguments.
1367 *
1368 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1369 * @param a0 The first extra argument.
1370 * @param a1 The second extra argument.
1371 */
1372#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1373 do { \
1374 IEM_MC_PREPARE_SSE_USAGE(); \
1375 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1376 } while (0)
1377
1378/**
1379 * Calls a SSE assembly implementation taking three visible arguments.
1380 *
1381 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1382 * @param a0 The first extra argument.
1383 * @param a1 The second extra argument.
1384 * @param a2 The third extra argument.
1385 */
1386#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1387 do { \
1388 IEM_MC_PREPARE_SSE_USAGE(); \
1389 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1390 } while (0)
1391
1392
1393/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1394 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1395#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1396 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1397
1398/**
1399 * Calls a AVX assembly implementation taking two visible arguments.
1400 *
1401 * There is one implicit zero'th argument, a pointer to the extended state.
1402 *
1403 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1404 * @param a1 The first extra argument.
1405 * @param a2 The second extra argument.
1406 */
1407#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1408 do { \
1409 IEM_MC_PREPARE_AVX_USAGE(); \
1410 a_pfnAImpl(pXState, (a1), (a2)); \
1411 } while (0)
1412
1413/**
1414 * Calls a AVX assembly implementation taking three visible arguments.
1415 *
1416 * There is one implicit zero'th argument, a pointer to the extended state.
1417 *
1418 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1419 * @param a1 The first extra argument.
1420 * @param a2 The second extra argument.
1421 * @param a3 The third extra argument.
1422 */
1423#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1424 do { \
1425 IEM_MC_PREPARE_AVX_USAGE(); \
1426 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1427 } while (0)
1428
1429/** @note Not for IOPL or IF testing. */
1430#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1431/** @note Not for IOPL or IF testing. */
1432#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1433/** @note Not for IOPL or IF testing. */
1434#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1435/** @note Not for IOPL or IF testing. */
1436#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1437/** @note Not for IOPL or IF testing. */
1438#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1439 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1440 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1441/** @note Not for IOPL or IF testing. */
1442#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1443 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1444 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1445/** @note Not for IOPL or IF testing. */
1446#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1447 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1448 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1449 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1450/** @note Not for IOPL or IF testing. */
1451#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1452 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1453 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1454 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1455#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1456#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1457#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1458/** @note Not for IOPL or IF testing. */
1459#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1460 if ( pVCpu->cpum.GstCtx.cx != 0 \
1461 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1462/** @note Not for IOPL or IF testing. */
1463#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1464 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1465 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1466/** @note Not for IOPL or IF testing. */
1467#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1468 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1469 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1470/** @note Not for IOPL or IF testing. */
1471#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1472 if ( pVCpu->cpum.GstCtx.cx != 0 \
1473 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1474/** @note Not for IOPL or IF testing. */
1475#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1476 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1477 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1478/** @note Not for IOPL or IF testing. */
1479#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1480 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1481 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1482#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1483#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1484
1485#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1486 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1487#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1488 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1489#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1490 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1491#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1492 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1493#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1494 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1495#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1496 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1497#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1498 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1499#define IEM_MC_IF_FCW_IM() \
1500 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1501#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1502 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1503 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1504
1505#define IEM_MC_ELSE() } else {
1506#define IEM_MC_ENDIF() } do {} while (0)
1507
1508/** @} */
1509
1510#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1511
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette