VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 99353

Last change on this file since 99353 was 99353, checked in by vboxsync, 20 months ago

VMM/IEM: Mojo improvments for IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT. bugref:10369
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1/* $Id: IEMMc.h 99353 2023-04-08 00:27:03Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44
45/** Internal macro. */
46#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
47 do \
48 { \
49 VBOXSTRICTRC rcStrict2 = a_Expr; \
50 if (rcStrict2 != VINF_SUCCESS) \
51 return rcStrict2; \
52 } while (0)
53
54
55/** Advances RIP, finishes the instruction and returns.
56 * This may include raising debug exceptions and such. */
57#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
58/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
59#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
60 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
61/** Sets RIP (may trigger \#GP), finishes the instruction and returns.
62 * @note only usable in 16-bit op size mode. */
63#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
64 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
65/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
66#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
67 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
68/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
69#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJumpU16AndFinishClearningRF((pVCpu), (a_u16NewIP))
70/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
71#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJumpU32AndFinishClearningRF((pVCpu), (a_u32NewIP))
72/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
73#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJumpU64AndFinishClearningRF((pVCpu), (a_u64NewIP))
74
75#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
76#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
77 do { \
78 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)))) \
79 { /* probable */ } \
80 else return iemRaiseDeviceNotAvailable(pVCpu); \
81 } while (0)
82#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
83 do { \
84 if (RT_LIKELY(!((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)))) \
85 { /* probable */ } \
86 else return iemRaiseDeviceNotAvailable(pVCpu); \
87 } while (0)
88#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
89 do { \
90 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES))) \
91 { /* probable */ } \
92 else return iemRaiseMathFault(pVCpu); \
93 } while (0)
94#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
95 do { \
96 /* Since none of the bits we compare from XCR0, CR4 and CR0 overlap, it can \
97 be reduced to a single compare branch in the more probably code path. */ \
98 if (RT_LIKELY( ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) \
99 | (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
100 | (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)) \
101 == (XSAVE_C_YMM | XSAVE_C_SSE | X86_CR4_OSXSAVE))) \
102 { /* probable */ } \
103 else if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
104 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)) \
105 return iemRaiseUndefinedOpcode(pVCpu); \
106 else \
107 return iemRaiseDeviceNotAvailable(pVCpu); \
108 } while (0)
109AssertCompile(!((XSAVE_C_YMM | XSAVE_C_SSE) & X86_CR4_OSXSAVE));
110AssertCompile(!((XSAVE_C_YMM | XSAVE_C_SSE) & X86_CR0_TS));
111AssertCompile(!(X86_CR4_OSXSAVE & X86_CR0_TS));
112#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
113 do { \
114 /* Since the CR4 and CR0 bits doesn't overlap, it can be reduced to a
115 single compare branch in the more probable code path. */ \
116 if (RT_LIKELY( ( (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
117 | (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
118 == X86_CR4_OSFXSR)) \
119 { /* likely */ } \
120 else if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
121 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
122 return iemRaiseUndefinedOpcode(pVCpu); \
123 else \
124 return iemRaiseDeviceNotAvailable(pVCpu); \
125 } while (0)
126AssertCompile(!((X86_CR0_EM | X86_CR0_TS) & X86_CR4_OSFXSR));
127#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
128 do { \
129 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)))) \
130 { /* probable */ } \
131 else if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
132 return iemRaiseUndefinedOpcode(pVCpu); \
133 else \
134 return iemRaiseDeviceNotAvailable(pVCpu); \
135 \
136 if (!(pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES)) { /* probable */ } \
137 else return iemRaiseMathFault(pVCpu); \
138 } while (0)
139#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
140 do { \
141 if (RT_LIKELY(pVCpu->iem.s.uCpl == 0)) { /* probable */ } \
142 else return iemRaiseGeneralProtectionFault0(pVCpu); \
143 } while (0)
144#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
145 do { \
146 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
147 else return iemRaiseGeneralProtectionFault0(pVCpu); \
148 } while (0)
149#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
150 do { \
151 if (RT_LIKELY( pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT \
152 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE))) \
153 { /* probable */ } \
154 else return iemRaiseUndefinedOpcode(pVCpu); \
155 } while (0)
156#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
157 do { \
158 if (RT_LIKELY(IEM_IS_CANONICAL(a_u64Addr))) { /* likely */ } \
159 else return iemRaiseGeneralProtectionFault0(pVCpu); \
160 } while (0)
161#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
162 do { \
163 if (RT_LIKELY(( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
164 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) == 0)) \
165 { /* probable */ } \
166 else \
167 { \
168 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT) \
169 return iemRaiseSimdFpException(pVCpu); \
170 return iemRaiseUndefinedOpcode(pVCpu); \
171 } \
172 } while (0)
173#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
174 do { \
175 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
176 return iemRaiseSimdFpException(pVCpu); \
177 return iemRaiseUndefinedOpcode(pVCpu); \
178 } while (0)
179
180
181#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
182#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
183#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
184#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
185#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
186#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
187#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
188 uint32_t a_Name; \
189 uint32_t *a_pName = &a_Name
190#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
191 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
192
193#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
194#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
195#define IEM_MC_ASSIGN_U8_SX_U64(a_u64VarOrArg, a_u8CVariableOrConst) \
196 (a_u64VarOrArg) = (int8_t)(a_u8CVariableOrConst)
197#define IEM_MC_ASSIGN_U32_SX_U64(a_u64VarOrArg, a_u32CVariableOrConst) \
198 (a_u64VarOrArg) = (int32_t)(a_u32CVariableOrConst)
199
200#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
201#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
202#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
203#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
204#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
205#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
206#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
207#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
208#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
209#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
210#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
211#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
212#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
213#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
214#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
215#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
216#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
217#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
218 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
219 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
220 } while (0)
221#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
222 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
223 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
224 } while (0)
225#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
226 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
227 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
228 } while (0)
229/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
230#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
231 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
232 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
233 } while (0)
234#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
235 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
236 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
237 } while (0)
238/** @note Not for IOPL or IF testing or modification. */
239#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
240#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
241#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
242#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
243
244#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
245#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
246#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
247#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
248#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
249#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
250#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
251#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
252#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
253#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
254#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
255/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
256#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
257 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
258 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
259 } while (0)
260#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
261 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
262 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
263 } while (0)
264#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
265 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
266
267
268#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
269#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
270/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
271 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
272#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
273#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
274#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
275#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
276#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
277#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
278/** @note Not for IOPL or IF testing or modification.
279 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
280#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
281#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
282
283#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
284#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
285#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
286 do { \
287 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
288 *pu32Reg += (a_u32Value); \
289 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
290 } while (0)
291#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
292
293#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
294#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
295#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
296 do { \
297 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
298 *pu32Reg -= (a_u32Value); \
299 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
300 } while (0)
301#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
302#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
303
304#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
305#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
306#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
307#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
308#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
309#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
310#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
311
312#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
313#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
314#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
315#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
316
317#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
318#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
319#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
320
321#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
322#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
323#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
324
325#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
326#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
327#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
328
329#define IEM_MC_SHR_LOCAL_U8(a_u8Local, a_cShift) do { (a_u8Local) >>= (a_cShift); } while (0)
330
331#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
332#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
333#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
334
335#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
336
337#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
338
339#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
340#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
341#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
342 do { \
343 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
344 *pu32Reg &= (a_u32Value); \
345 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
346 } while (0)
347#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
348
349#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
350#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
351#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
352 do { \
353 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
354 *pu32Reg |= (a_u32Value); \
355 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
356 } while (0)
357#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
358
359#define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) (a_u16Local) = RT_BSWAP_U16((a_u16Local));
360#define IEM_MC_BSWAP_LOCAL_U32(a_u32Local) (a_u32Local) = RT_BSWAP_U32((a_u32Local));
361#define IEM_MC_BSWAP_LOCAL_U64(a_u64Local) (a_u64Local) = RT_BSWAP_U64((a_u64Local));
362
363/** @note Not for IOPL or IF modification. */
364#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
365/** @note Not for IOPL or IF modification. */
366#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
367/** @note Not for IOPL or IF modification. */
368#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
369
370#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
371
372/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
373#define IEM_MC_FPU_TO_MMX_MODE() do { \
374 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
375 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
376 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
377 } while (0)
378
379/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
380#define IEM_MC_FPU_FROM_MMX_MODE() do { \
381 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
382 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
383 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
384 } while (0)
385
386#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
387 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
388#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
389 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
390#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
391 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
392 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
393 } while (0)
394#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
395 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
396 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
397 } while (0)
398#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
399 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
400#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
401 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
402#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
403 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
404#define IEM_MC_MODIFIED_MREG(a_iMReg) \
405 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
406#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
407 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
408
409#define IEM_MC_CLEAR_XREG_U32_MASK(a_iXReg, a_bMask) \
410 do { if ((a_bMask) & (1 << 0)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = 0; \
411 if ((a_bMask) & (1 << 1)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[1] = 0; \
412 if ((a_bMask) & (1 << 2)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[2] = 0; \
413 if ((a_bMask) & (1 << 3)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[3] = 0; \
414 } while (0)
415#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
416 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
417 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
418 } while (0)
419#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
420 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
421 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
422 } while (0)
423#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) \
424 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQWord)]; } while (0)
425#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg, a_iDWord) \
426 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDWord)]; } while (0)
427#define IEM_MC_FETCH_XREG_U16(a_u16Value, a_iXReg, a_iWord) \
428 do { (a_u16Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iWord)]; } while (0)
429#define IEM_MC_FETCH_XREG_U8( a_u8Value, a_iXReg, a_iByte) \
430 do { (a_u8Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iByte)]; } while (0)
431#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
432 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
433 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
434 } while (0)
435#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
436 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
437 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
438 } while (0)
439#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
440 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
441#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
442 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
443#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) \
444 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_u64Value); } while (0)
445#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) \
446 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_u32Value); } while (0)
447#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u16Value) \
448 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iWord)] = (a_u16Value); } while (0)
449#define IEM_MC_STORE_XREG_U8(a_iXReg, a_iByte, a_u8Value) \
450 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iByte)] = (a_u8Value); } while (0)
451
452#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
453 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
454 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
455 } while (0)
456
457#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) \
458 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDwDst)] = (a_u128Value).au32[(a_iDwSrc)]; } while (0)
459#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
460 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
461#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
462 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
463#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
464 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
465 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
466 } while (0)
467#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
468 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
469#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
470 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
471#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
472 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
473#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
474 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
475#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
476 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
477#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
478 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
479#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
480 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
481#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
482 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
483#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
484 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
485 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
486 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
487 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
488 } while (0)
489
490#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
491 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
492 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
493 } while (0)
494#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
495 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
496 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
497 } while (0)
498#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
499 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
500 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
501 } while (0)
502#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
503 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
504 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
505 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
506 } while (0)
507#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
508 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
509 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
510 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
511 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
512 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
513 } while (0)
514
515#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
516#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
517 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
518 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
519 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
520 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
521 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
522 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
523 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
524 } while (0)
525#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
526 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
527 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
528 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
529 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
530 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
531 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
532 } while (0)
533#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
534 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
535 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
536 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
537 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
538 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
539 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
540 } while (0)
541#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
542 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
543 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
544 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
545 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
546 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
547 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
548 } while (0)
549
550#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
551 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
552#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
553 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
554#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
555 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
556#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
557 do { uintptr_t const iYRegTmp = (a_iYReg); \
558 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
559 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
560 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
561 } while (0)
562
563#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
564 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
565 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
566 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
567 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
568 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
569 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
570 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
571 } while (0)
572#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
573 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
574 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
575 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
576 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
577 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
578 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
579 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
580 } while (0)
581#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
582 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
583 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
584 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
585 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
586 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
587 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
588 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
589 } while (0)
590
591#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
592 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
593 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
594 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
595 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
596 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
597 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
598 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
599 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
600 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
601 } while (0)
602#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
603 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
604 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
605 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
606 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
607 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
608 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
609 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
610 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
611 } while (0)
612#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
613 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
614 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
615 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
616 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
617 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
618 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
619 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
620 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
621 } while (0)
622#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
623 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
624 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
625 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
626 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
627 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
628 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
629 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
630 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
631 } while (0)
632#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
633 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
634 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
635 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
636 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
637 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
638 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
639 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
640 } while (0)
641#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
642 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
643 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
644 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
645 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
646 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
647 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
648 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
649 } while (0)
650
651#ifndef IEM_WITH_SETJMP
652# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
653 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
654# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
655 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
656# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
657 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
658#else
659# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
660 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
661# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
662 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
663# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
664 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
665#endif
666
667#ifndef IEM_WITH_SETJMP
668# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
669 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
670# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
671 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
672# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
673 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
674#else
675# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
676 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
677# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
678 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
679# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
680 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
681#endif
682
683#ifndef IEM_WITH_SETJMP
684# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
685 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
686# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
687 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
688# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
689 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
690#else
691# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
692 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
693# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
694 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
695# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
696 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
697#endif
698
699#ifdef SOME_UNUSED_FUNCTION
700# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
701 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
702#endif
703
704#ifndef IEM_WITH_SETJMP
705# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
706 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
707# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
708 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
709# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
710 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
711# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
712 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
713#else
714# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
715 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
716# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
717 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
718# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
719 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
720# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
721 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
722#endif
723
724#ifndef IEM_WITH_SETJMP
725# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
726 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
727# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
728 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
729# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
730 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
731# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
732 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
733#else
734# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
735 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
736# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
737 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
738# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
739 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
740# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
741 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
742#endif
743
744#ifndef IEM_WITH_SETJMP
745# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
746 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
747# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
748 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
749# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
750 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
751
752# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
753 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
754# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
755 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
756# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
757 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
758# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
759 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
760# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
761 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
762#else
763# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
764 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
765# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
766 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
767# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
768 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
769
770# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
771 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
772# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
773 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
774# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
775 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
776# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
777 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
778# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
779 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
780#endif
781
782#ifndef IEM_WITH_SETJMP
783# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
784 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
785# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
786 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
787# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
788 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
789
790# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
791 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
792# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
793 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
794# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
795 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
796#else
797# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
798 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
799# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
800 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
801# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
802 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
803
804# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
805 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
806# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
807 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
808# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
809 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
810#endif
811
812
813
814#ifndef IEM_WITH_SETJMP
815# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
816 do { \
817 uint8_t u8Tmp; \
818 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
819 (a_u16Dst) = u8Tmp; \
820 } while (0)
821# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
822 do { \
823 uint8_t u8Tmp; \
824 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
825 (a_u32Dst) = u8Tmp; \
826 } while (0)
827# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
828 do { \
829 uint8_t u8Tmp; \
830 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
831 (a_u64Dst) = u8Tmp; \
832 } while (0)
833# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
834 do { \
835 uint16_t u16Tmp; \
836 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
837 (a_u32Dst) = u16Tmp; \
838 } while (0)
839# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
840 do { \
841 uint16_t u16Tmp; \
842 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
843 (a_u64Dst) = u16Tmp; \
844 } while (0)
845# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
846 do { \
847 uint32_t u32Tmp; \
848 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
849 (a_u64Dst) = u32Tmp; \
850 } while (0)
851#else /* IEM_WITH_SETJMP */
852# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
853 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
854# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
855 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
856# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
857 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
858# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
859 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
860# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
861 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
862# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
863 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
864#endif /* IEM_WITH_SETJMP */
865
866#ifndef IEM_WITH_SETJMP
867# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
868 do { \
869 uint8_t u8Tmp; \
870 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
871 (a_u16Dst) = (int8_t)u8Tmp; \
872 } while (0)
873# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
874 do { \
875 uint8_t u8Tmp; \
876 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
877 (a_u32Dst) = (int8_t)u8Tmp; \
878 } while (0)
879# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
880 do { \
881 uint8_t u8Tmp; \
882 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
883 (a_u64Dst) = (int8_t)u8Tmp; \
884 } while (0)
885# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
886 do { \
887 uint16_t u16Tmp; \
888 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
889 (a_u32Dst) = (int16_t)u16Tmp; \
890 } while (0)
891# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
892 do { \
893 uint16_t u16Tmp; \
894 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
895 (a_u64Dst) = (int16_t)u16Tmp; \
896 } while (0)
897# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
898 do { \
899 uint32_t u32Tmp; \
900 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
901 (a_u64Dst) = (int32_t)u32Tmp; \
902 } while (0)
903#else /* IEM_WITH_SETJMP */
904# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
905 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
906# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
907 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
908# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
909 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
910# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
911 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
912# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
913 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
914# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
915 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
916#endif /* IEM_WITH_SETJMP */
917
918#ifndef IEM_WITH_SETJMP
919# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
920 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
921# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
922 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
923# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
924 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
925# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
926 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
927#else
928# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
929 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
930# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
931 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
932# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
933 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
934# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
935 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
936#endif
937
938#ifndef IEM_WITH_SETJMP
939# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
940 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
941# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
942 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
943# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
944 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
945# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
946 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
947#else
948# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
949 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
950# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
951 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
952# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
953 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
954# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
955 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
956#endif
957
958#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
959#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
960#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
961#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
962#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
963#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
964#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
965 do { \
966 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
967 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
968 } while (0)
969#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
970 do { \
971 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
972 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
973 } while (0)
974
975#ifndef IEM_WITH_SETJMP
976# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
977 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
978# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
979 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
980#else
981# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
982 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
983# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
984 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
985#endif
986
987#ifndef IEM_WITH_SETJMP
988# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
989 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
990# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
991 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
992#else
993# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
994 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
995# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
996 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
997#endif
998
999
1000#define IEM_MC_PUSH_U16(a_u16Value) \
1001 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1002#define IEM_MC_PUSH_U32(a_u32Value) \
1003 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1004#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
1005 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
1006#define IEM_MC_PUSH_U64(a_u64Value) \
1007 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1008
1009#define IEM_MC_POP_U16(a_pu16Value) \
1010 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1011#define IEM_MC_POP_U32(a_pu32Value) \
1012 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1013#define IEM_MC_POP_U64(a_pu64Value) \
1014 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1015
1016/** Maps guest memory for direct or bounce buffered access.
1017 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1018 * @remarks May return.
1019 */
1020#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1021 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1022 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1023
1024/** Maps guest memory for direct or bounce buffered access.
1025 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1026 * @remarks May return.
1027 */
1028#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1029 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1030 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1031
1032/** Commits the memory and unmaps the guest memory.
1033 * @remarks May return.
1034 */
1035#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1036 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1037
1038/** Commits the memory and unmaps the guest memory unless the FPU status word
1039 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1040 * that would cause FLD not to store.
1041 *
1042 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1043 * store, while \#P will not.
1044 *
1045 * @remarks May in theory return - for now.
1046 */
1047#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1048 do { \
1049 if ( !(a_u16FSW & X86_FSW_ES) \
1050 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1051 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1052 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1053 } while (0)
1054
1055/** Calculate efficient address from R/M. */
1056#ifndef IEM_WITH_SETJMP
1057# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1058 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1059#else
1060# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1061 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1062#endif
1063
1064#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1065#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1066#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1067#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1068#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1069#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1070#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1071
1072/**
1073 * Defers the rest of the instruction emulation to a C implementation routine
1074 * and returns, only taking the standard parameters.
1075 *
1076 * @param a_pfnCImpl The pointer to the C routine.
1077 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1078 */
1079#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1080
1081/**
1082 * Defers the rest of instruction emulation to a C implementation routine and
1083 * returns, taking one argument in addition to the standard ones.
1084 *
1085 * @param a_pfnCImpl The pointer to the C routine.
1086 * @param a0 The argument.
1087 */
1088#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1089
1090/**
1091 * Defers the rest of the instruction emulation to a C implementation routine
1092 * and returns, taking two arguments in addition to the standard ones.
1093 *
1094 * @param a_pfnCImpl The pointer to the C routine.
1095 * @param a0 The first extra argument.
1096 * @param a1 The second extra argument.
1097 */
1098#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1099
1100/**
1101 * Defers the rest of the instruction emulation to a C implementation routine
1102 * and returns, taking three arguments in addition to the standard ones.
1103 *
1104 * @param a_pfnCImpl The pointer to the C routine.
1105 * @param a0 The first extra argument.
1106 * @param a1 The second extra argument.
1107 * @param a2 The third extra argument.
1108 */
1109#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1110
1111/**
1112 * Defers the rest of the instruction emulation to a C implementation routine
1113 * and returns, taking four arguments in addition to the standard ones.
1114 *
1115 * @param a_pfnCImpl The pointer to the C routine.
1116 * @param a0 The first extra argument.
1117 * @param a1 The second extra argument.
1118 * @param a2 The third extra argument.
1119 * @param a3 The fourth extra argument.
1120 */
1121#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1122
1123/**
1124 * Defers the rest of the instruction emulation to a C implementation routine
1125 * and returns, taking two arguments in addition to the standard ones.
1126 *
1127 * @param a_pfnCImpl The pointer to the C routine.
1128 * @param a0 The first extra argument.
1129 * @param a1 The second extra argument.
1130 * @param a2 The third extra argument.
1131 * @param a3 The fourth extra argument.
1132 * @param a4 The fifth extra argument.
1133 */
1134#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1135
1136/**
1137 * Defers the entire instruction emulation to a C implementation routine and
1138 * returns, only taking the standard parameters.
1139 *
1140 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1141 *
1142 * @param a_pfnCImpl The pointer to the C routine.
1143 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1144 */
1145#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1146
1147/**
1148 * Defers the entire instruction emulation to a C implementation routine and
1149 * returns, taking one argument in addition to the standard ones.
1150 *
1151 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1152 *
1153 * @param a_pfnCImpl The pointer to the C routine.
1154 * @param a0 The argument.
1155 */
1156#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1157
1158/**
1159 * Defers the entire instruction emulation to a C implementation routine and
1160 * returns, taking two arguments in addition to the standard ones.
1161 *
1162 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1163 *
1164 * @param a_pfnCImpl The pointer to the C routine.
1165 * @param a0 The first extra argument.
1166 * @param a1 The second extra argument.
1167 */
1168#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1169
1170/**
1171 * Defers the entire instruction emulation to a C implementation routine and
1172 * returns, taking three arguments in addition to the standard ones.
1173 *
1174 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1175 *
1176 * @param a_pfnCImpl The pointer to the C routine.
1177 * @param a0 The first extra argument.
1178 * @param a1 The second extra argument.
1179 * @param a2 The third extra argument.
1180 */
1181#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1182
1183/**
1184 * Calls a FPU assembly implementation taking one visible argument.
1185 *
1186 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1187 * @param a0 The first extra argument.
1188 */
1189#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1190 do { \
1191 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1192 } while (0)
1193
1194/**
1195 * Calls a FPU assembly implementation taking two visible arguments.
1196 *
1197 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1198 * @param a0 The first extra argument.
1199 * @param a1 The second extra argument.
1200 */
1201#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1202 do { \
1203 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1204 } while (0)
1205
1206/**
1207 * Calls a FPU assembly implementation taking three visible arguments.
1208 *
1209 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1210 * @param a0 The first extra argument.
1211 * @param a1 The second extra argument.
1212 * @param a2 The third extra argument.
1213 */
1214#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1215 do { \
1216 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1217 } while (0)
1218
1219#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1220 do { \
1221 (a_FpuData).FSW = (a_FSW); \
1222 (a_FpuData).r80Result = *(a_pr80Value); \
1223 } while (0)
1224
1225/** Pushes FPU result onto the stack. */
1226#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1227 iemFpuPushResult(pVCpu, &a_FpuData)
1228/** Pushes FPU result onto the stack and sets the FPUDP. */
1229#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1230 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1231
1232/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1233#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1234 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1235
1236/** Stores FPU result in a stack register. */
1237#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1238 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1239/** Stores FPU result in a stack register and pops the stack. */
1240#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1241 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1242/** Stores FPU result in a stack register and sets the FPUDP. */
1243#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1244 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1245/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1246 * stack. */
1247#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1248 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1249
1250/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1251#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1252 iemFpuUpdateOpcodeAndIp(pVCpu)
1253/** Free a stack register (for FFREE and FFREEP). */
1254#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1255 iemFpuStackFree(pVCpu, a_iStReg)
1256/** Increment the FPU stack pointer. */
1257#define IEM_MC_FPU_STACK_INC_TOP() \
1258 iemFpuStackIncTop(pVCpu)
1259/** Decrement the FPU stack pointer. */
1260#define IEM_MC_FPU_STACK_DEC_TOP() \
1261 iemFpuStackDecTop(pVCpu)
1262
1263/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1264#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1265 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1266/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1267#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1268 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1269/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1270#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1271 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1272/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1273#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1274 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1275/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1276 * stack. */
1277#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1278 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1279/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1280#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1281 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1282
1283/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1284#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1285 iemFpuStackUnderflow(pVCpu, a_iStDst)
1286/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1287 * stack. */
1288#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1289 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1290/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1291 * FPUDS. */
1292#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1293 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1294/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1295 * FPUDS. Pops stack. */
1296#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1297 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1298/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1299 * stack twice. */
1300#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1301 iemFpuStackUnderflowThenPopPop(pVCpu)
1302/** Raises a FPU stack underflow exception for an instruction pushing a result
1303 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1304#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1305 iemFpuStackPushUnderflow(pVCpu)
1306/** Raises a FPU stack underflow exception for an instruction pushing a result
1307 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1308#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1309 iemFpuStackPushUnderflowTwo(pVCpu)
1310
1311/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1312 * FPUIP, FPUCS and FOP. */
1313#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1314 iemFpuStackPushOverflow(pVCpu)
1315/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1316 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1317#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1318 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1319/** Prepares for using the FPU state.
1320 * Ensures that we can use the host FPU in the current context (RC+R0.
1321 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1322#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1323/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1324#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1325/** Actualizes the guest FPU state so it can be accessed and modified. */
1326#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1327
1328/** Stores SSE SIMD result updating MXCSR. */
1329#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1330 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1331/** Updates MXCSR. */
1332#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1333 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1334
1335/** Prepares for using the SSE state.
1336 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1337 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1338#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1339/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1340#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1341/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1342#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1343
1344/** Prepares for using the AVX state.
1345 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1346 * Ensures the guest AVX state in the CPUMCTX is up to date.
1347 * @note This will include the AVX512 state too when support for it is added
1348 * due to the zero extending feature of VEX instruction. */
1349#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1350/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1351#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1352/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1353#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1354
1355/**
1356 * Calls a MMX assembly implementation taking two visible arguments.
1357 *
1358 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1359 * @param a0 The first extra argument.
1360 * @param a1 The second extra argument.
1361 */
1362#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1363 do { \
1364 IEM_MC_PREPARE_FPU_USAGE(); \
1365 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1366 } while (0)
1367
1368/**
1369 * Calls a MMX assembly implementation taking three visible arguments.
1370 *
1371 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1372 * @param a0 The first extra argument.
1373 * @param a1 The second extra argument.
1374 * @param a2 The third extra argument.
1375 */
1376#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1377 do { \
1378 IEM_MC_PREPARE_FPU_USAGE(); \
1379 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1380 } while (0)
1381
1382
1383/**
1384 * Calls a SSE assembly implementation taking two visible arguments.
1385 *
1386 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1387 * @param a0 The first extra argument.
1388 * @param a1 The second extra argument.
1389 */
1390#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1391 do { \
1392 IEM_MC_PREPARE_SSE_USAGE(); \
1393 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1394 } while (0)
1395
1396/**
1397 * Calls a SSE assembly implementation taking three visible arguments.
1398 *
1399 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1400 * @param a0 The first extra argument.
1401 * @param a1 The second extra argument.
1402 * @param a2 The third extra argument.
1403 */
1404#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1405 do { \
1406 IEM_MC_PREPARE_SSE_USAGE(); \
1407 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1408 } while (0)
1409
1410
1411/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1412 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1413#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1414 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1415
1416/**
1417 * Calls a AVX assembly implementation taking two visible arguments.
1418 *
1419 * There is one implicit zero'th argument, a pointer to the extended state.
1420 *
1421 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1422 * @param a1 The first extra argument.
1423 * @param a2 The second extra argument.
1424 */
1425#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1426 do { \
1427 IEM_MC_PREPARE_AVX_USAGE(); \
1428 a_pfnAImpl(pXState, (a1), (a2)); \
1429 } while (0)
1430
1431/**
1432 * Calls a AVX assembly implementation taking three visible arguments.
1433 *
1434 * There is one implicit zero'th argument, a pointer to the extended state.
1435 *
1436 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1437 * @param a1 The first extra argument.
1438 * @param a2 The second extra argument.
1439 * @param a3 The third extra argument.
1440 */
1441#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1442 do { \
1443 IEM_MC_PREPARE_AVX_USAGE(); \
1444 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1445 } while (0)
1446
1447/** @note Not for IOPL or IF testing. */
1448#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1449/** @note Not for IOPL or IF testing. */
1450#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1451/** @note Not for IOPL or IF testing. */
1452#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1453/** @note Not for IOPL or IF testing. */
1454#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1455/** @note Not for IOPL or IF testing. */
1456#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1457 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1458 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1459/** @note Not for IOPL or IF testing. */
1460#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1461 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1462 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1463/** @note Not for IOPL or IF testing. */
1464#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1465 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1466 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1467 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1468/** @note Not for IOPL or IF testing. */
1469#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1470 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1471 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1472 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1473#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1474#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1475#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1476/** @note Not for IOPL or IF testing. */
1477#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1478 if ( pVCpu->cpum.GstCtx.cx != 0 \
1479 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1480/** @note Not for IOPL or IF testing. */
1481#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1482 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1483 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1484/** @note Not for IOPL or IF testing. */
1485#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1486 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1487 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1488/** @note Not for IOPL or IF testing. */
1489#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1490 if ( pVCpu->cpum.GstCtx.cx != 0 \
1491 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1492/** @note Not for IOPL or IF testing. */
1493#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1494 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1495 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1496/** @note Not for IOPL or IF testing. */
1497#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1498 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1499 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1500#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1501#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1502
1503#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1504 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1505#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1506 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1507#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1508 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1509#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1510 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1511#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1512 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1513#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1514 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1515#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1516 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1517#define IEM_MC_IF_FCW_IM() \
1518 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1519#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1520 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1521 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1522
1523#define IEM_MC_ELSE() } else {
1524#define IEM_MC_ENDIF() } do {} while (0)
1525
1526/** @} */
1527
1528#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1529
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