IEMN8veRecompiler.h@ 102377

Last change on this file since 102377 was 102370, checked in by vboxsync, 15 months ago
VMM/IEM: Some ARM bugfixes. bugref:10371
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1	/* $Id: IEMN8veRecompiler.h 102370 2023-11-28 22:17:45Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager - Native Recompiler Internals.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h
29	#define VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34
35	/** @defgroup grp_iem_n8ve_re Native Recompiler Internals.
36	* @ingroup grp_iem_int
37	* @{
38	*/
39
40	/** @def IEMNATIVE_WITH_TB_DEBUG_INFO
41	* Enables generating internal debug info for better TB disassembly dumping. */
42	#if defined(DEBUG) \|\| defined(DOXYGEN_RUNNING)
43	# define IEMNATIVE_WITH_TB_DEBUG_INFO
44	#endif
45
46
47	/** @name Stack Frame Layout
48	*
49	* @{ */
50	/** The size of the area for stack variables and spills and stuff.
51	* @note This limit is duplicated in the python script(s). We add 0x40 for
52	* alignment padding. */
53	#define IEMNATIVE_FRAME_VAR_SIZE (0xc0 + 0x40)
54	/** Number of 64-bit variable slots (0x100 / 8 = 32. */
55	#define IEMNATIVE_FRAME_VAR_SLOTS (IEMNATIVE_FRAME_VAR_SIZE / 8)
56	AssertCompile(IEMNATIVE_FRAME_VAR_SLOTS == 32);
57
58	#ifdef RT_ARCH_AMD64
59	/** An stack alignment adjustment (between non-volatile register pushes and
60	* the stack variable area, so the latter better aligned). */
61	# define IEMNATIVE_FRAME_ALIGN_SIZE 8
62
63	/** Number of stack arguments slots for calls made from the frame. */
64	# ifdef RT_OS_WINDOWS
65	# define IEMNATIVE_FRAME_STACK_ARG_COUNT 4
66	# else
67	# define IEMNATIVE_FRAME_STACK_ARG_COUNT 2
68	# endif
69	/** Number of any shadow arguments (spill area) for calls we make. */
70	# ifdef RT_OS_WINDOWS
71	# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 4
72	# else
73	# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 0
74	# endif
75
76	/** Frame pointer (RBP) relative offset of the last push. */
77	# ifdef RT_OS_WINDOWS
78	# define IEMNATIVE_FP_OFF_LAST_PUSH (7 * -8)
79	# else
80	# define IEMNATIVE_FP_OFF_LAST_PUSH (5 * -8)
81	# endif
82	/** Frame pointer (RBP) relative offset of the stack variable area (the lowest
83	* address for it). */
84	# define IEMNATIVE_FP_OFF_STACK_VARS (IEMNATIVE_FP_OFF_LAST_PUSH - IEMNATIVE_FRAME_ALIGN_SIZE - IEMNATIVE_FRAME_VAR_SIZE)
85	/** Frame pointer (RBP) relative offset of the first stack argument for calls. */
86	# define IEMNATIVE_FP_OFF_STACK_ARG0 (IEMNATIVE_FP_OFF_STACK_VARS - IEMNATIVE_FRAME_STACK_ARG_COUNT * 8)
87	/** Frame pointer (RBP) relative offset of the second stack argument for calls. */
88	# define IEMNATIVE_FP_OFF_STACK_ARG1 (IEMNATIVE_FP_OFF_STACK_ARG0 + 8)
89	# ifdef RT_OS_WINDOWS
90	/** Frame pointer (RBP) relative offset of the third stack argument for calls. */
91	# define IEMNATIVE_FP_OFF_STACK_ARG2 (IEMNATIVE_FP_OFF_STACK_ARG0 + 16)
92	/** Frame pointer (RBP) relative offset of the fourth stack argument for calls. */
93	# define IEMNATIVE_FP_OFF_STACK_ARG3 (IEMNATIVE_FP_OFF_STACK_ARG0 + 24)
94	# endif
95
96	# ifdef RT_OS_WINDOWS
97	/** Frame pointer (RBP) relative offset of the first incoming shadow argument. */
98	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG0 (16)
99	/** Frame pointer (RBP) relative offset of the second incoming shadow argument. */
100	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG1 (24)
101	/** Frame pointer (RBP) relative offset of the third incoming shadow argument. */
102	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG2 (32)
103	/** Frame pointer (RBP) relative offset of the fourth incoming shadow argument. */
104	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG3 (40)
105	# endif
106
107	#elif RT_ARCH_ARM64
108	/** No alignment padding needed for arm64. */
109	# define IEMNATIVE_FRAME_ALIGN_SIZE 0
110	/** No stack argument slots, got 8 registers for arguments will suffice. */
111	# define IEMNATIVE_FRAME_STACK_ARG_COUNT 0
112	/** There are no argument spill area. */
113	# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 0
114
115	/** Number of saved registers at the top of our stack frame.
116	* This includes the return address and old frame pointer, so x19 thru x30. */
117	# define IEMNATIVE_FRAME_SAVE_REG_COUNT (12)
118	/** The size of the save registered (IEMNATIVE_FRAME_SAVE_REG_COUNT). */
119	# define IEMNATIVE_FRAME_SAVE_REG_SIZE (IEMNATIVE_FRAME_SAVE_REG_COUNT * 8)
120
121	/** Frame pointer (BP) relative offset of the last push. */
122	# define IEMNATIVE_FP_OFF_LAST_PUSH (7 * -8)
123
124	/** Frame pointer (BP) relative offset of the stack variable area (the lowest
125	* address for it). */
126	# define IEMNATIVE_FP_OFF_STACK_VARS (IEMNATIVE_FP_OFF_LAST_PUSH - IEMNATIVE_FRAME_ALIGN_SIZE - IEMNATIVE_FRAME_VAR_SIZE)
127
128	#else
129	# error "port me"
130	#endif
131	/** @} */
132
133
134	/** @name Fixed Register Allocation(s)
135	* @{ */
136	/** @def IEMNATIVE_REG_FIXED_PVMCPU
137	* The number of the register holding the pVCpu pointer. */
138	/** @def IEMNATIVE_REG_FIXED_PCPUMCTX
139	* The number of the register holding the &pVCpu->cpum.GstCtx pointer.
140	* @note This not available on AMD64, only ARM64. */
141	/** @def IEMNATIVE_REG_FIXED_TMP0
142	* Dedicated temporary register.
143	* @todo replace this by a register allocator and content tracker. */
144	/** @def IEMNATIVE_REG_FIXED_MASK
145	* Mask GPRs with fixes assignments, either by us or dictated by the CPU/OS
146	* architecture. */
147	#if defined(RT_ARCH_AMD64) && !defined(DOXYGEN_RUNNING)
148	# define IEMNATIVE_REG_FIXED_PVMCPU X86_GREG_xBX
149	# define IEMNATIVE_REG_FIXED_TMP0 X86_GREG_x11
150	# define IEMNATIVE_REG_FIXED_MASK ( RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU) \
151	\| RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0) \
152	\| RT_BIT_32(X86_GREG_xSP) \
153	\| RT_BIT_32(X86_GREG_xBP) )
154
155	#elif defined(RT_ARCH_ARM64) \|\| defined(DOXYGEN_RUNNING)
156	# define IEMNATIVE_REG_FIXED_PVMCPU ARMV8_A64_REG_X28
157	# define IEMNATIVE_REG_FIXED_PCPUMCTX ARMV8_A64_REG_X27
158	# define IEMNATIVE_REG_FIXED_TMP0 ARMV8_A64_REG_X15
159	# define IEMNATIVE_REG_FIXED_MASK ( RT_BIT_32(ARMV8_A64_REG_SP) \
160	\| RT_BIT_32(ARMV8_A64_REG_LR) \
161	\| RT_BIT_32(ARMV8_A64_REG_BP) \
162	\| RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU) \
163	\| RT_BIT_32(IEMNATIVE_REG_FIXED_PCPUMCTX) \
164	\| RT_BIT_32(ARMV8_A64_REG_X18) \
165	\| RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0) )
166
167	#else
168	# error "port me"
169	#endif
170	/** @} */
171
172	/** @name Call related registers.
173	* @{ */
174	/** @def IEMNATIVE_CALL_RET_GREG
175	* The return value register. */
176	/** @def IEMNATIVE_CALL_ARG_GREG_COUNT
177	* Number of arguments in registers. */
178	/** @def IEMNATIVE_CALL_ARG0_GREG
179	* The general purpose register carrying argument \#0. */
180	/** @def IEMNATIVE_CALL_ARG1_GREG
181	* The general purpose register carrying argument \#1. */
182	/** @def IEMNATIVE_CALL_ARG2_GREG
183	* The general purpose register carrying argument \#2. */
184	/** @def IEMNATIVE_CALL_ARG3_GREG
185	* The general purpose register carrying argument \#3. */
186	/** @def IEMNATIVE_CALL_VOLATILE_GREG_MASK
187	* Mask of registers the callee will not save and may trash. */
188	#ifdef RT_ARCH_AMD64
189	# define IEMNATIVE_CALL_RET_GREG X86_GREG_xAX
190
191	# ifdef RT_OS_WINDOWS
192	# define IEMNATIVE_CALL_ARG_GREG_COUNT 4
193	# define IEMNATIVE_CALL_ARG0_GREG X86_GREG_xCX
194	# define IEMNATIVE_CALL_ARG1_GREG X86_GREG_xDX
195	# define IEMNATIVE_CALL_ARG2_GREG X86_GREG_x8
196	# define IEMNATIVE_CALL_ARG3_GREG X86_GREG_x9
197	# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \
198	\| RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \
199	\| RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG) \
200	\| RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) \
201	\| RT_BIT_32(IEMNATIVE_CALL_ARG4_GREG) )
202	# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(X86_GREG_xAX) \
203	\| RT_BIT_32(X86_GREG_xCX) \
204	\| RT_BIT_32(X86_GREG_xDX) \
205	\| RT_BIT_32(X86_GREG_x8) \
206	\| RT_BIT_32(X86_GREG_x9) \
207	\| RT_BIT_32(X86_GREG_x10) \
208	\| RT_BIT_32(X86_GREG_x11) )
209	# else
210	# define IEMNATIVE_CALL_ARG_GREG_COUNT 6
211	# define IEMNATIVE_CALL_ARG0_GREG X86_GREG_xDI
212	# define IEMNATIVE_CALL_ARG1_GREG X86_GREG_xSI
213	# define IEMNATIVE_CALL_ARG2_GREG X86_GREG_xDX
214	# define IEMNATIVE_CALL_ARG3_GREG X86_GREG_xCX
215	# define IEMNATIVE_CALL_ARG4_GREG X86_GREG_x8
216	# define IEMNATIVE_CALL_ARG5_GREG X86_GREG_x9
217	# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \
218	\| RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \
219	\| RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG) \
220	\| RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) \
221	\| RT_BIT_32(IEMNATIVE_CALL_ARG4_GREG) \
222	\| RT_BIT_32(IEMNATIVE_CALL_ARG5_GREG) )
223	# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(X86_GREG_xAX) \
224	\| RT_BIT_32(X86_GREG_xCX) \
225	\| RT_BIT_32(X86_GREG_xDX) \
226	\| RT_BIT_32(X86_GREG_xDI) \
227	\| RT_BIT_32(X86_GREG_xSI) \
228	\| RT_BIT_32(X86_GREG_x8) \
229	\| RT_BIT_32(X86_GREG_x9) \
230	\| RT_BIT_32(X86_GREG_x10) \
231	\| RT_BIT_32(X86_GREG_x11) )
232	# endif
233
234	#elif defined(RT_ARCH_ARM64)
235	# define IEMNATIVE_CALL_RET_GREG ARMV8_A64_REG_X0
236	# define IEMNATIVE_CALL_ARG_GREG_COUNT 8
237	# define IEMNATIVE_CALL_ARG0_GREG ARMV8_A64_REG_X0
238	# define IEMNATIVE_CALL_ARG1_GREG ARMV8_A64_REG_X1
239	# define IEMNATIVE_CALL_ARG2_GREG ARMV8_A64_REG_X2
240	# define IEMNATIVE_CALL_ARG3_GREG ARMV8_A64_REG_X3
241	# define IEMNATIVE_CALL_ARG4_GREG ARMV8_A64_REG_X4
242	# define IEMNATIVE_CALL_ARG5_GREG ARMV8_A64_REG_X5
243	# define IEMNATIVE_CALL_ARG6_GREG ARMV8_A64_REG_X6
244	# define IEMNATIVE_CALL_ARG7_GREG ARMV8_A64_REG_X7
245	# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(ARMV8_A64_REG_X0) \
246	\| RT_BIT_32(ARMV8_A64_REG_X1) \
247	\| RT_BIT_32(ARMV8_A64_REG_X2) \
248	\| RT_BIT_32(ARMV8_A64_REG_X3) \
249	\| RT_BIT_32(ARMV8_A64_REG_X4) \
250	\| RT_BIT_32(ARMV8_A64_REG_X5) \
251	\| RT_BIT_32(ARMV8_A64_REG_X6) \
252	\| RT_BIT_32(ARMV8_A64_REG_X7) )
253	# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(ARMV8_A64_REG_X0) \
254	\| RT_BIT_32(ARMV8_A64_REG_X1) \
255	\| RT_BIT_32(ARMV8_A64_REG_X2) \
256	\| RT_BIT_32(ARMV8_A64_REG_X3) \
257	\| RT_BIT_32(ARMV8_A64_REG_X4) \
258	\| RT_BIT_32(ARMV8_A64_REG_X5) \
259	\| RT_BIT_32(ARMV8_A64_REG_X6) \
260	\| RT_BIT_32(ARMV8_A64_REG_X7) \
261	\| RT_BIT_32(ARMV8_A64_REG_X8) \
262	\| RT_BIT_32(ARMV8_A64_REG_X9) \
263	\| RT_BIT_32(ARMV8_A64_REG_X10) \
264	\| RT_BIT_32(ARMV8_A64_REG_X11) \
265	\| RT_BIT_32(ARMV8_A64_REG_X12) \
266	\| RT_BIT_32(ARMV8_A64_REG_X13) \
267	\| RT_BIT_32(ARMV8_A64_REG_X14) \
268	\| RT_BIT_32(ARMV8_A64_REG_X15) \
269	\| RT_BIT_32(ARMV8_A64_REG_X16) \
270	\| RT_BIT_32(ARMV8_A64_REG_X17) )
271
272	#endif
273
274	/** This is the maximum argument count we'll ever be needing. */
275	#if defined(RT_OS_WINDOWS) && defined(VBOXSTRICTRC_STRICT_ENABLED)
276	# define IEMNATIVE_CALL_MAX_ARG_COUNT 8
277	#else
278	# define IEMNATIVE_CALL_MAX_ARG_COUNT 7
279	#endif
280	/** @} */
281
282
283	/** @def IEMNATIVE_HST_GREG_COUNT
284	* Number of host general purpose registers we tracker. */
285	/** @def IEMNATIVE_HST_GREG_MASK
286	* Mask corresponding to IEMNATIVE_HST_GREG_COUNT that can be applied to
287	* inverted register masks and such to get down to a correct set of regs. */
288	#ifdef RT_ARCH_AMD64
289	# define IEMNATIVE_HST_GREG_COUNT 16
290	# define IEMNATIVE_HST_GREG_MASK UINT32_C(0xffff)
291
292	#elif defined(RT_ARCH_ARM64)
293	# define IEMNATIVE_HST_GREG_COUNT 32
294	# define IEMNATIVE_HST_GREG_MASK UINT32_MAX
295	#else
296	# error "Port me!"
297	#endif
298
299
300	/** Native code generator label types. */
301	typedef enum
302	{
303	kIemNativeLabelType_Invalid = 0,
304	/* Labels w/o data, only once instance per TB: */
305	kIemNativeLabelType_Return,
306	kIemNativeLabelType_ReturnBreak,
307	kIemNativeLabelType_ReturnWithFlags,
308	kIemNativeLabelType_NonZeroRetOrPassUp,
309	kIemNativeLabelType_RaiseGp0,
310	/* Labels with data, potentially multiple instances per TB: */
311	kIemNativeLabelType_FirstWithMultipleInstances,
312	kIemNativeLabelType_If = kIemNativeLabelType_FirstWithMultipleInstances,
313	kIemNativeLabelType_Else,
314	kIemNativeLabelType_Endif,
315	kIemNativeLabelType_CheckIrq,
316	kIemNativeLabelType_TlbMiss,
317	kIemNativeLabelType_TlbDone,
318	kIemNativeLabelType_End
319	} IEMNATIVELABELTYPE;
320
321	/** Native code generator label definition. */
322	typedef struct IEMNATIVELABEL
323	{
324	/** Code offset if defined, UINT32_MAX if it needs to be generated after/in
325	* the epilog. */
326	uint32_t off;
327	/** The type of label (IEMNATIVELABELTYPE). */
328	uint16_t enmType;
329	/** Additional label data, type specific. */
330	uint16_t uData;
331	} IEMNATIVELABEL;
332	/** Pointer to a label. */
333	typedef IEMNATIVELABEL *PIEMNATIVELABEL;
334
335
336	/** Native code generator fixup types. */
337	typedef enum
338	{
339	kIemNativeFixupType_Invalid = 0,
340	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
341	/** AMD64 fixup: PC relative 32-bit with addend in bData. */
342	kIemNativeFixupType_Rel32,
343	#elif defined(RT_ARCH_ARM64)
344	/** ARM64 fixup: PC relative offset at bits 25:0 (B, BL). */
345	kIemNativeFixupType_RelImm26At0,
346	/** ARM64 fixup: PC relative offset at bits 23:5 (CBZ, CBNZ, B.CC). */
347	kIemNativeFixupType_RelImm19At5,
348	/** ARM64 fixup: PC relative offset at bits 18:5 (TBZ, TBNZ). */
349	kIemNativeFixupType_RelImm14At5,
350	#endif
351	kIemNativeFixupType_End
352	} IEMNATIVEFIXUPTYPE;
353
354	/** Native code generator fixup. */
355	typedef struct IEMNATIVEFIXUP
356	{
357	/** Code offset of the fixup location. */
358	uint32_t off;
359	/** The IEMNATIVELABEL this is a fixup for. */
360	uint16_t idxLabel;
361	/** The fixup type (IEMNATIVEFIXUPTYPE). */
362	uint8_t enmType;
363	/** Addend or other data. */
364	int8_t offAddend;
365	} IEMNATIVEFIXUP;
366	/** Pointer to a native code generator fixup. */
367	typedef IEMNATIVEFIXUP *PIEMNATIVEFIXUP;
368
369
370	/**
371	* Guest registers that can be shadowed in GPRs.
372	*/
373	typedef enum IEMNATIVEGSTREG : uint8_t
374	{
375	kIemNativeGstReg_GprFirst = 0,
376	kIemNativeGstReg_GprLast = kIemNativeGstReg_GprFirst + 15,
377	kIemNativeGstReg_Pc,
378	kIemNativeGstReg_EFlags, /*< 32-bit, includes internal flags. /
379	kIemNativeGstReg_SegSelFirst,
380	kIemNativeGstReg_SegSelLast = kIemNativeGstReg_SegSelFirst + 5,
381	kIemNativeGstReg_SegBaseFirst,
382	kIemNativeGstReg_SegBaseLast = kIemNativeGstReg_SegBaseFirst + 5,
383	kIemNativeGstReg_SegLimitFirst,
384	kIemNativeGstReg_SegLimitLast = kIemNativeGstReg_SegLimitFirst + 5,
385	kIemNativeGstReg_End
386	} IEMNATIVEGSTREG;
387
388	/** @name Helpers for converting register numbers to IEMNATIVEGSTREG values.
389	* @{ */
390	#define IEMNATIVEGSTREG_GPR(a_iGpr) ((IEMNATIVEGSTREG)(kIemNativeGstReg_GprFirst + (a_iGpr) ))
391	#define IEMNATIVEGSTREG_SEG_SEL(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegSelFirst + (a_iSegReg) ))
392	#define IEMNATIVEGSTREG_SEG_BASE(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegBaseFirst + (a_iSegReg) ))
393	#define IEMNATIVEGSTREG_SEG_LIMIT(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegLimitFirst + (a_iSegReg) ))
394	/** @} */
395
396	/**
397	* Intended use statement for iemNativeRegAllocTmpForGuestReg().
398	*/
399	typedef enum IEMNATIVEGSTREGUSE
400	{
401	/** The usage is read-only, the register holding the guest register
402	* shadow copy will not be modified by the caller. */
403	kIemNativeGstRegUse_ReadOnly = 0,
404	/** The caller will update the guest register (think: PC += cbInstr).
405	* The guest shadow copy will follow the returned register. */
406	kIemNativeGstRegUse_ForUpdate,
407	/** The call will put an entirely new value in the guest register, so
408	* if new register is allocate it will be returned uninitialized. */
409	kIemNativeGstRegUse_ForFullWrite,
410	/** The caller will use the guest register value as input in a calculation
411	* and the host register will be modified.
412	* This means that the returned host register will not be marked as a shadow
413	* copy of the guest register. */
414	kIemNativeGstRegUse_Calculation
415	} IEMNATIVEGSTREGUSE;
416
417	/**
418	* Guest registers (classes) that can be referenced.
419	*/
420	typedef enum IEMNATIVEGSTREGREF : uint8_t
421	{
422	kIemNativeGstRegRef_Invalid = 0,
423	kIemNativeGstRegRef_Gpr,
424	kIemNativeGstRegRef_GprHighByte, /*< AH, CH, DH, BH/
425	kIemNativeGstRegRef_EFlags,
426	kIemNativeGstRegRef_MxCsr,
427	kIemNativeGstRegRef_FpuReg,
428	kIemNativeGstRegRef_MReg,
429	kIemNativeGstRegRef_XReg,
430	//kIemNativeGstRegRef_YReg, - doesn't work.
431	kIemNativeGstRegRef_End
432	} IEMNATIVEGSTREGREF;
433
434
435	/** Variable kinds. */
436	typedef enum IEMNATIVEVARKIND : uint8_t
437	{
438	/** Customary invalid zero value. */
439	kIemNativeVarKind_Invalid = 0,
440	/** This is either in a register or on the stack. */
441	kIemNativeVarKind_Stack,
442	/** Immediate value - loaded into register when needed, or can live on the
443	* stack if referenced (in theory). */
444	kIemNativeVarKind_Immediate,
445	/** Variable reference - loaded into register when needed, never stack. */
446	kIemNativeVarKind_VarRef,
447	/** Guest register reference - loaded into register when needed, never stack. */
448	kIemNativeVarKind_GstRegRef,
449	/** End of valid values. */
450	kIemNativeVarKind_End
451	} IEMNATIVEVARKIND;
452
453
454	/** Variable or argument. */
455	typedef struct IEMNATIVEVAR
456	{
457	/** The kind of variable. */
458	IEMNATIVEVARKIND enmKind;
459	/** The variable size in bytes. */
460	uint8_t cbVar;
461	/** The first stack slot (uint64_t), except for immediate and references
462	* where it usually is UINT8_MAX. */
463	uint8_t idxStackSlot;
464	/** The host register allocated for the variable, UINT8_MAX if not. */
465	uint8_t idxReg;
466	/** The argument number if argument, UINT8_MAX if regular variable. */
467	uint8_t uArgNo;
468	/** If referenced, the index of the variable referencing this one, otherwise
469	* UINT8_MAX. A referenced variable must only be placed on the stack and
470	* must be either kIemNativeVarKind_Stack or kIemNativeVarKind_Immediate. */
471	uint8_t idxReferrerVar;
472	/** Guest register being shadowed here, kIemNativeGstReg_End(/UINT8_MAX) if not.
473	* @todo not sure what this really is for... */
474	IEMNATIVEGSTREG enmGstReg;
475	uint8_t bAlign;
476
477	union
478	{
479	/** kIemNativeVarKind_Immediate: The immediate value. */
480	uint64_t uValue;
481	/** kIemNativeVarKind_VarRef: The index of the variable being referenced. */
482	uint8_t idxRefVar;
483	/** kIemNativeVarKind_GstRegRef: The guest register being referrenced. */
484	struct
485	{
486	/** The class of register. */
487	IEMNATIVEGSTREGREF enmClass;
488	/** Index within the class. */
489	uint8_t idx;
490	} GstRegRef;
491	} u;
492	} IEMNATIVEVAR;
493
494	/** What is being kept in a host register. */
495	typedef enum IEMNATIVEWHAT : uint8_t
496	{
497	/** The traditional invalid zero value. */
498	kIemNativeWhat_Invalid = 0,
499	/** Mapping a variable (IEMNATIVEHSTREG::idxVar). */
500	kIemNativeWhat_Var,
501	/** Temporary register, this is typically freed when a MC completes. */
502	kIemNativeWhat_Tmp,
503	/** Call argument w/o a variable mapping. This is free (via
504	* IEMNATIVE_CALL_VOLATILE_GREG_MASK) after the call is emitted. */
505	kIemNativeWhat_Arg,
506	/** Return status code.
507	* @todo not sure if we need this... */
508	kIemNativeWhat_rc,
509	/** The fixed pVCpu (PVMCPUCC) register.
510	* @todo consider offsetting this on amd64 to use negative offsets to access
511	* more members using 8-byte disp. */
512	kIemNativeWhat_pVCpuFixed,
513	/** The fixed pCtx (PCPUMCTX) register.
514	* @todo consider offsetting this on amd64 to use negative offsets to access
515	* more members using 8-byte disp. */
516	kIemNativeWhat_pCtxFixed,
517	/** Fixed temporary register. */
518	kIemNativeWhat_FixedTmp,
519	/** Register reserved by the CPU or OS architecture. */
520	kIemNativeWhat_FixedReserved,
521	/** End of valid values. */
522	kIemNativeWhat_End
523	} IEMNATIVEWHAT;
524
525	/**
526	* Host general register entry.
527	*
528	* The actual allocation status is kept in IEMRECOMPILERSTATE::bmHstRegs.
529	*
530	* @todo Track immediate values in host registers similarlly to how we track the
531	* guest register shadow copies. For it to be real helpful, though,
532	* we probably need to know which will be reused and put them into
533	* non-volatile registers, otherwise it's going to be more or less
534	* restricted to an instruction or two.
535	*/
536	typedef struct IEMNATIVEHSTREG
537	{
538	/** Set of guest registers this one shadows.
539	*
540	* Using a bitmap here so we can designate the same host register as a copy
541	* for more than one guest register. This is expected to be useful in
542	* situations where one value is copied to several registers in a sequence.
543	* If the mapping is 1:1, then we'd have to pick which side of a 'MOV SRC,DST'
544	* sequence we'd want to let this register follow to be a copy of and there
545	* will always be places where we'd be picking the wrong one.
546	*/
547	uint64_t fGstRegShadows;
548	/** What is being kept in this register. */
549	IEMNATIVEWHAT enmWhat;
550	/** Variable index if holding a variable, otherwise UINT8_MAX. */
551	uint8_t idxVar;
552	/** Alignment padding. */
553	uint8_t abAlign[6];
554	} IEMNATIVEHSTREG;
555
556
557	/**
558	* Core state for the native recompiler, that is, things that needs careful
559	* handling when dealing with branches.
560	*/
561	typedef struct IEMNATIVECORESTATE
562	{
563	/** Allocation bitmap for aHstRegs. */
564	uint32_t bmHstRegs;
565
566	/** Bitmap marking which host register contains guest register shadow copies.
567	* This is used during register allocation to try preserve copies. */
568	uint32_t bmHstRegsWithGstShadow;
569	/** Bitmap marking valid entries in aidxGstRegShadows. */
570	uint64_t bmGstRegShadows;
571
572	union
573	{
574	/** Index of variable arguments, UINT8_MAX if not valid. */
575	uint8_t aidxArgVars[8];
576	/** For more efficient resetting. */
577	uint64_t u64ArgVars;
578	};
579
580	/** Allocation bitmap for the stack. */
581	uint32_t bmStack;
582	/** Allocation bitmap for aVars. */
583	uint32_t bmVars;
584
585	/** Maps a guest register to a host GPR (index by IEMNATIVEGSTREG).
586	* Entries are only valid if the corresponding bit in bmGstRegShadows is set.
587	* (A shadow copy of a guest register can only be held in a one host register,
588	* there are no duplicate copies or ambiguities like that). */
589	uint8_t aidxGstRegShadows[kIemNativeGstReg_End];
590
591	/** Host register allocation tracking. */
592	IEMNATIVEHSTREG aHstRegs[IEMNATIVE_HST_GREG_COUNT];
593
594	/** Variables and arguments. */
595	IEMNATIVEVAR aVars[9];
596	} IEMNATIVECORESTATE;
597	/** Pointer to core state. */
598	typedef IEMNATIVECORESTATE *PIEMNATIVECORESTATE;
599	/** Pointer to const core state. */
600	typedef IEMNATIVECORESTATE const *PCIEMNATIVECORESTATE;
601
602
603	/**
604	* Conditional stack entry.
605	*/
606	typedef struct IEMNATIVECOND
607	{
608	/** Set if we're in the "else" part, clear if we're in the "if" before it. */
609	bool fInElse;
610	/** The label for the IEM_MC_ELSE. */
611	uint32_t idxLabelElse;
612	/** The label for the IEM_MC_ENDIF. */
613	uint32_t idxLabelEndIf;
614	/** The initial state snapshot as the if-block starts executing. */
615	IEMNATIVECORESTATE InitialState;
616	/** The state snapshot at the end of the if-block. */
617	IEMNATIVECORESTATE IfFinalState;
618	} IEMNATIVECOND;
619	/** Pointer to a condition stack entry. */
620	typedef IEMNATIVECOND *PIEMNATIVECOND;
621
622
623	/**
624	* Native recompiler state.
625	*/
626	typedef struct IEMRECOMPILERSTATE
627	{
628	/** Size of the buffer that pbNativeRecompileBufR3 points to in
629	* IEMNATIVEINSTR units. */
630	uint32_t cInstrBufAlloc;
631	#ifdef VBOX_STRICT
632	/** Strict: How far the last iemNativeInstrBufEnsure() checked. */
633	uint32_t offInstrBufChecked;
634	#else
635	uint32_t uPadding1; /* We don't keep track of the size here... */
636	#endif
637	/** Fixed temporary code buffer for native recompilation. */
638	PIEMNATIVEINSTR pInstrBuf;
639
640	/** Bitmaps with the label types used. */
641	uint64_t bmLabelTypes;
642	/** Actual number of labels in paLabels. */
643	uint32_t cLabels;
644	/** Max number of entries allowed in paLabels before reallocating it. */
645	uint32_t cLabelsAlloc;
646	/** Labels defined while recompiling (referenced by fixups). */
647	PIEMNATIVELABEL paLabels;
648	/** Array with indexes of unique labels (uData always 0). */
649	uint32_t aidxUniqueLabels[kIemNativeLabelType_FirstWithMultipleInstances];
650
651	/** Actual number of fixups paFixups. */
652	uint32_t cFixups;
653	/** Max number of entries allowed in paFixups before reallocating it. */
654	uint32_t cFixupsAlloc;
655	/** Buffer used by the recompiler for recording fixups when generating code. */
656	PIEMNATIVEFIXUP paFixups;
657
658	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
659	/** Number of debug info entries allocated for pDbgInfo. */
660	uint32_t cDbgInfoAlloc;
661	uint32_t uPadding;
662	/** Debug info. */
663	PIEMTBDBG pDbgInfo;
664	#endif
665
666	/** The translation block being recompiled. */
667	PCIEMTB pTbOrg;
668
669	/** Condition sequence number (for generating unique labels). */
670	uint16_t uCondSeqNo;
671	/** Check IRQ seqeunce number (for generating unique labels). */
672	uint16_t uCheckIrqSeqNo;
673	/** TLB load sequence number (for generating unique labels). */
674	uint16_t uTlbSeqNo;
675	/** The current condition stack depth (aCondStack). */
676	uint8_t cCondDepth;
677
678	/** The argument count + hidden regs from the IEM_MC_BEGIN statement. */
679	uint8_t cArgs;
680	/** The IEM_CIMPL_F_XXX flags from the IEM_MC_BEGIN statement. */
681	uint32_t fCImpl;
682	/** The IEM_MC_F_XXX flags from the IEM_MC_BEGIN statement. */
683	uint32_t fMc;
684	/** The expected IEMCPU::fExec value for the current call/instruction. */
685	uint32_t fExec;
686
687	/** Core state requiring care with branches. */
688	IEMNATIVECORESTATE Core;
689
690	/** The condition nesting stack. */
691	IEMNATIVECOND aCondStack[2];
692
693	#ifndef IEM_WITH_THROW_CATCH
694	/** Pointer to the setjmp/longjmp buffer if we're not using C++ exceptions
695	* for recompilation error handling. */
696	jmp_buf JmpBuf;
697	#endif
698	} IEMRECOMPILERSTATE;
699	/** Pointer to a native recompiler state. */
700	typedef IEMRECOMPILERSTATE *PIEMRECOMPILERSTATE;
701
702
703	/** @def IEMNATIVE_TRY_SETJMP
704	* Wrapper around setjmp / try, hiding all the ugly differences.
705	*
706	* @note Use with extreme care as this is a fragile macro.
707	* @param a_pReNative The native recompile state.
708	* @param a_rcTarget The variable that should receive the status code in case
709	* of a longjmp/throw.
710	*/
711	/** @def IEMNATIVE_CATCH_LONGJMP_BEGIN
712	* Start wrapper for catch / setjmp-else.
713	*
714	* This will set up a scope.
715	*
716	* @note Use with extreme care as this is a fragile macro.
717	* @param a_pReNative The native recompile state.
718	* @param a_rcTarget The variable that should receive the status code in case
719	* of a longjmp/throw.
720	*/
721	/** @def IEMNATIVE_CATCH_LONGJMP_END
722	* End wrapper for catch / setjmp-else.
723	*
724	* This will close the scope set up by IEMNATIVE_CATCH_LONGJMP_BEGIN and clean
725	* up the state.
726	*
727	* @note Use with extreme care as this is a fragile macro.
728	* @param a_pReNative The native recompile state.
729	*/
730	/** @def IEMNATIVE_DO_LONGJMP
731	*
732	* Wrapper around longjmp / throw.
733	*
734	* @param a_pReNative The native recompile state.
735	* @param a_rc The status code jump back with / throw.
736	*/
737	#ifdef IEM_WITH_THROW_CATCH
738	# define IEMNATIVE_TRY_SETJMP(a_pReNative, a_rcTarget) \
739	a_rcTarget = VINF_SUCCESS; \
740	try
741	# define IEMNATIVE_CATCH_LONGJMP_BEGIN(a_pReNative, a_rcTarget) \
742	catch (int rcThrown) \
743	{ \
744	a_rcTarget = rcThrown
745	# define IEMNATIVE_CATCH_LONGJMP_END(a_pReNative) \
746	} \
747	((void)0)
748	# define IEMNATIVE_DO_LONGJMP(a_pReNative, a_rc) throw int(a_rc)
749	#else /* !IEM_WITH_THROW_CATCH */
750	# define IEMNATIVE_TRY_SETJMP(a_pReNative, a_rcTarget) \
751	if ((a_rcTarget = setjmp((a_pReNative)->JmpBuf)) == 0)
752	# define IEMNATIVE_CATCH_LONGJMP_BEGIN(a_pReNative, a_rcTarget) \
753	else \
754	{ \
755	((void)0)
756	# define IEMNATIVE_CATCH_LONGJMP_END(a_pReNative) \
757	}
758	# define IEMNATIVE_DO_LONGJMP(a_pReNative, a_rc) longjmp((a_pReNative)->JmpBuf, (a_rc))
759	#endif /* !IEM_WITH_THROW_CATCH */
760
761
762	/**
763	* Native recompiler worker for a threaded function.
764	*
765	* @returns New code buffer offset; throws VBox status code in case of a failure.
766	* @param pReNative The native recompiler state.
767	* @param off The current code buffer offset.
768	* @param pCallEntry The threaded call entry.
769	*
770	* @note This may throw/longjmp VBox status codes (int) to abort compilation, so no RT_NOEXCEPT!
771	*/
772	typedef uint32_t (VBOXCALL FNIEMNATIVERECOMPFUNC)(PIEMRECOMPILERSTATE pReNative, uint32_t off, PCIEMTHRDEDCALLENTRY pCallEntry);
773	/** Pointer to a native recompiler worker for a threaded function. */
774	typedef FNIEMNATIVERECOMPFUNC *PFNIEMNATIVERECOMPFUNC;
775
776	/** Defines a native recompiler worker for a threaded function.
777	* @see FNIEMNATIVERECOMPFUNC */
778	#define IEM_DECL_IEMNATIVERECOMPFUNC_DEF(a_Name) \
779	uint32_t VBOXCALL a_Name(PIEMRECOMPILERSTATE pReNative, uint32_t off, PCIEMTHRDEDCALLENTRY pCallEntry)
780
781	/** Prototypes a native recompiler function for a threaded function.
782	* @see FNIEMNATIVERECOMPFUNC */
783	#define IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(a_Name) FNIEMNATIVERECOMPFUNC a_Name
784
785
786	/** Define a native recompiler helper function, safe to call from the TB code. */
787	#define IEM_DECL_NATIVE_HLP_DEF(a_RetType, a_Name, a_ArgList) \
788	DECL_HIDDEN_THROW(a_RetType) VBOXCALL a_Name a_ArgList
789	/** Prototype a native recompiler helper function, safe to call from the TB code. */
790	#define IEM_DECL_NATIVE_HLP_PROTO(a_RetType, a_Name, a_ArgList) \
791	DECL_HIDDEN_THROW(a_RetType) VBOXCALL a_Name a_ArgList
792
793
794	DECL_HIDDEN_THROW(uint32_t) iemNativeLabelCreate(PIEMRECOMPILERSTATE pReNative, IEMNATIVELABELTYPE enmType,
795	uint32_t offWhere = UINT32_MAX, uint16_t uData = 0);
796	DECL_HIDDEN_THROW(void) iemNativeLabelDefine(PIEMRECOMPILERSTATE pReNative, uint32_t idxLabel, uint32_t offWhere);
797	DECL_HIDDEN_THROW(void) iemNativeAddFixup(PIEMRECOMPILERSTATE pReNative, uint32_t offWhere, uint32_t idxLabel,
798	IEMNATIVEFIXUPTYPE enmType, int8_t offAddend = 0);
799	DECL_HIDDEN_THROW(PIEMNATIVEINSTR) iemNativeInstrBufEnsureSlow(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t cInstrReq);
800
801	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmp(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, bool fPreferVolatile = true);
802	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpImm(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint64_t uImm,
803	bool fPreferVolatile = true);
804	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpForGuestReg(PIEMRECOMPILERSTATE pReNative, uint32_t *poff,
805	IEMNATIVEGSTREG enmGstReg, IEMNATIVEGSTREGUSE enmIntendedUse);
806	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpForGuestRegIfAlreadyPresent(PIEMRECOMPILERSTATE pReNative, uint32_t *poff,
807	IEMNATIVEGSTREG enmGstReg);
808
809	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocVar(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint8_t idxVar);
810	DECL_HIDDEN_THROW(uint32_t) iemNativeRegAllocArgs(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs);
811	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAssignRc(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg);
812	DECLHIDDEN(void) iemNativeRegFree(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
813	DECLHIDDEN(void) iemNativeRegFreeTmp(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
814	DECLHIDDEN(void) iemNativeRegFreeTmpImm(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
815	DECLHIDDEN(void) iemNativeRegFreeAndFlushMask(PIEMRECOMPILERSTATE pReNative, uint32_t fHstRegMask) RT_NOEXCEPT;
816	DECL_HIDDEN_THROW(uint32_t) iemNativeRegFlushPendingWrites(PIEMRECOMPILERSTATE pReNative, uint32_t off);
817
818	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitLoadGprWithGstShadowReg(PIEMRECOMPILERSTATE pReNative, uint32_t off,
819	uint8_t idxHstReg, IEMNATIVEGSTREG enmGstReg);
820	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitCheckCallRetAndPassUp(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr);
821
822	extern DECL_HIDDEN_DATA(const char * const) g_apszIemNativeHstRegNames[];
823
824
825	/**
826	* Ensures that there is sufficient space in the instruction output buffer.
827	*
828	* This will reallocate the buffer if needed and allowed.
829	*
830	* @note Always use IEMNATIVE_ASSERT_INSTR_BUF_ENSURE when done to check the
831	* allocation size.
832	*
833	* @returns Pointer to the instruction output buffer on success; throws VBox
834	* status code on failure, so no need to check it.
835	* @param pReNative The native recompile state.
836	* @param off Current instruction offset. Works safely for UINT32_MAX
837	* as well.
838	* @param cInstrReq Number of instruction about to be added. It's okay to
839	* overestimate this a bit.
840	*/
841	DECL_FORCE_INLINE_THROW(PIEMNATIVEINSTR)
842	iemNativeInstrBufEnsure(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t cInstrReq)
843	{
844	uint64_t const offChecked = off + (uint64_t)cInstrReq; /** @todo may reconsider the need for UINT32_MAX safety... */
845	if (RT_LIKELY(offChecked <= pReNative->cInstrBufAlloc))
846	{
847	#ifdef VBOX_STRICT
848	pReNative->offInstrBufChecked = offChecked;
849	#endif
850	return pReNative->pInstrBuf;
851	}
852	return iemNativeInstrBufEnsureSlow(pReNative, off, cInstrReq);
853	}
854
855	/**
856	* Checks that we didn't exceed the space requested in the last
857	* iemNativeInstrBufEnsure() call.
858	*/
859	#define IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(a_pReNative, a_off) \
860	AssertMsg((a_off) <= (a_pReNative)->offInstrBufChecked, \
861	("off=%#x offInstrBufChecked=%#x\n", (a_off), (a_pReNative)->offInstrBufChecked))
862
863	/**
864	* Checks that a variable index is valid.
865	*/
866	#define IEMNATIVE_ASSERT_VAR_IDX(a_pReNative, a_idxVar) \
867	AssertMsg( (unsigned)(a_idxVar) < RT_ELEMENTS((a_pReNative)->Core.aVars) \
868	&& ((a_pReNative)->Core.bmVars & RT_BIT_32(a_idxVar)), ("%s=%d\n", #a_idxVar, a_idxVar))
869
870	/**
871	* Checks that a variable index is valid and that the variable is assigned the
872	* correct argument number.
873	* This also adds a RT_NOREF of a_idxVar.
874	*/
875	#define IEMNATIVE_ASSERT_ARG_VAR_IDX(a_pReNative, a_idxVar, a_uArgNo) do { \
876	RT_NOREF_PV(a_idxVar); \
877	AssertMsg( (unsigned)(a_idxVar) < RT_ELEMENTS((a_pReNative)->Core.aVars) \
878	&& ((a_pReNative)->Core.bmVars & RT_BIT_32(a_idxVar))\
879	&& (a_pReNative)->Core.aVars[a_idxVar].uArgNo == (a_uArgNo) \
880	, ("%s=%d; uArgNo=%d, expected %u\n", #a_idxVar, a_idxVar, \
881	(a_pReNative)->Core.aVars[RT_MAX(a_idxVar, RT_ELEMENTS((a_pReNative)->Core.aVars)) - 1].uArgNo, a_uArgNo)); \
882	} while (0)
883
884	/**
885	* Calculates the stack address of a variable as a [r]BP displacement value.
886	*/
887	DECL_FORCE_INLINE(int32_t)
888	iemNativeStackCalcBpDisp(uint8_t idxStackSlot)
889	{
890	Assert(idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS);
891	return idxStackSlot * sizeof(uint64_t) + IEMNATIVE_FP_OFF_STACK_VARS;
892	}
893
894	/**
895	* Calculates the stack address of a variable as a [r]BP displacement value.
896	*/
897	DECL_FORCE_INLINE(int32_t)
898	iemNativeVarCalcBpDisp(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar)
899	{
900	return iemNativeStackCalcBpDisp(pReNative->Core.aVars[idxVar].idxStackSlot);
901	}
902
903	/** @} */
904
905	#endif /* !VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h */
906

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