IEMN8veRecompiler.h@ 102734

Last change on this file since 102734 was 102733, checked in by vboxsync, 11 months ago
VMM/IEM: Implemented making the TLB-missed call w/o trashing/flushing stuff in volatile registers. bugref:10371
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1	/* $Id: IEMN8veRecompiler.h 102733 2023-12-29 19:40:03Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager - Native Recompiler Internals.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h
29	#define VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34
35	/** @defgroup grp_iem_n8ve_re Native Recompiler Internals.
36	* @ingroup grp_iem_int
37	* @{
38	*/
39
40	/** @def IEMNATIVE_WITH_TB_DEBUG_INFO
41	* Enables generating internal debug info for better TB disassembly dumping. */
42	#if defined(DEBUG) \|\| defined(DOXYGEN_RUNNING)
43	# define IEMNATIVE_WITH_TB_DEBUG_INFO
44	#endif
45
46	/** Always count instructions for now. */
47	#define IEMNATIVE_WITH_INSTRUCTION_COUNTING
48
49
50	/** @name Stack Frame Layout
51	*
52	* @{ */
53	/** The size of the area for stack variables and spills and stuff.
54	* @note This limit is duplicated in the python script(s). We add 0x40 for
55	* alignment padding. */
56	#define IEMNATIVE_FRAME_VAR_SIZE (0xc0 + 0x40)
57	/** Number of 64-bit variable slots (0x100 / 8 = 32. */
58	#define IEMNATIVE_FRAME_VAR_SLOTS (IEMNATIVE_FRAME_VAR_SIZE / 8)
59	AssertCompile(IEMNATIVE_FRAME_VAR_SLOTS == 32);
60
61	#ifdef RT_ARCH_AMD64
62	/** An stack alignment adjustment (between non-volatile register pushes and
63	* the stack variable area, so the latter better aligned). */
64	# define IEMNATIVE_FRAME_ALIGN_SIZE 8
65
66	/** Number of stack arguments slots for calls made from the frame. */
67	# ifdef RT_OS_WINDOWS
68	# define IEMNATIVE_FRAME_STACK_ARG_COUNT 4
69	# else
70	# define IEMNATIVE_FRAME_STACK_ARG_COUNT 2
71	# endif
72	/** Number of any shadow arguments (spill area) for calls we make. */
73	# ifdef RT_OS_WINDOWS
74	# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 4
75	# else
76	# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 0
77	# endif
78
79	/** Frame pointer (RBP) relative offset of the last push. */
80	# ifdef RT_OS_WINDOWS
81	# define IEMNATIVE_FP_OFF_LAST_PUSH (7 * -8)
82	# else
83	# define IEMNATIVE_FP_OFF_LAST_PUSH (5 * -8)
84	# endif
85	/** Frame pointer (RBP) relative offset of the stack variable area (the lowest
86	* address for it). */
87	# define IEMNATIVE_FP_OFF_STACK_VARS (IEMNATIVE_FP_OFF_LAST_PUSH - IEMNATIVE_FRAME_ALIGN_SIZE - IEMNATIVE_FRAME_VAR_SIZE)
88	/** Frame pointer (RBP) relative offset of the first stack argument for calls. */
89	# define IEMNATIVE_FP_OFF_STACK_ARG0 (IEMNATIVE_FP_OFF_STACK_VARS - IEMNATIVE_FRAME_STACK_ARG_COUNT * 8)
90	/** Frame pointer (RBP) relative offset of the second stack argument for calls. */
91	# define IEMNATIVE_FP_OFF_STACK_ARG1 (IEMNATIVE_FP_OFF_STACK_ARG0 + 8)
92	# ifdef RT_OS_WINDOWS
93	/** Frame pointer (RBP) relative offset of the third stack argument for calls. */
94	# define IEMNATIVE_FP_OFF_STACK_ARG2 (IEMNATIVE_FP_OFF_STACK_ARG0 + 16)
95	/** Frame pointer (RBP) relative offset of the fourth stack argument for calls. */
96	# define IEMNATIVE_FP_OFF_STACK_ARG3 (IEMNATIVE_FP_OFF_STACK_ARG0 + 24)
97	# endif
98
99	# ifdef RT_OS_WINDOWS
100	/** Frame pointer (RBP) relative offset of the first incoming shadow argument. */
101	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG0 (16)
102	/** Frame pointer (RBP) relative offset of the second incoming shadow argument. */
103	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG1 (24)
104	/** Frame pointer (RBP) relative offset of the third incoming shadow argument. */
105	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG2 (32)
106	/** Frame pointer (RBP) relative offset of the fourth incoming shadow argument. */
107	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG3 (40)
108	# endif
109
110	#elif RT_ARCH_ARM64
111	/** No alignment padding needed for arm64. */
112	# define IEMNATIVE_FRAME_ALIGN_SIZE 0
113	/** No stack argument slots, got 8 registers for arguments will suffice. */
114	# define IEMNATIVE_FRAME_STACK_ARG_COUNT 0
115	/** There are no argument spill area. */
116	# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 0
117
118	/** Number of saved registers at the top of our stack frame.
119	* This includes the return address and old frame pointer, so x19 thru x30. */
120	# define IEMNATIVE_FRAME_SAVE_REG_COUNT (12)
121	/** The size of the save registered (IEMNATIVE_FRAME_SAVE_REG_COUNT). */
122	# define IEMNATIVE_FRAME_SAVE_REG_SIZE (IEMNATIVE_FRAME_SAVE_REG_COUNT * 8)
123
124	/** Frame pointer (BP) relative offset of the last push. */
125	# define IEMNATIVE_FP_OFF_LAST_PUSH (10 * -8)
126
127	/** Frame pointer (BP) relative offset of the stack variable area (the lowest
128	* address for it). */
129	# define IEMNATIVE_FP_OFF_STACK_VARS (IEMNATIVE_FP_OFF_LAST_PUSH - IEMNATIVE_FRAME_ALIGN_SIZE - IEMNATIVE_FRAME_VAR_SIZE)
130
131	#else
132	# error "port me"
133	#endif
134	/** @} */
135
136
137	/** @name Fixed Register Allocation(s)
138	* @{ */
139	/** @def IEMNATIVE_REG_FIXED_PVMCPU
140	* The number of the register holding the pVCpu pointer. */
141	/** @def IEMNATIVE_REG_FIXED_PCPUMCTX
142	* The number of the register holding the &pVCpu->cpum.GstCtx pointer.
143	* @note This not available on AMD64, only ARM64. */
144	/** @def IEMNATIVE_REG_FIXED_TMP0
145	* Dedicated temporary register.
146	* @todo replace this by a register allocator and content tracker. */
147	/** @def IEMNATIVE_REG_FIXED_MASK
148	* Mask GPRs with fixes assignments, either by us or dictated by the CPU/OS
149	* architecture. */
150	#if defined(RT_ARCH_AMD64) && !defined(DOXYGEN_RUNNING)
151	# define IEMNATIVE_REG_FIXED_PVMCPU X86_GREG_xBX
152	# define IEMNATIVE_REG_FIXED_TMP0 X86_GREG_x11
153	# define IEMNATIVE_REG_FIXED_MASK ( RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU) \
154	\| RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0) \
155	\| RT_BIT_32(X86_GREG_xSP) \
156	\| RT_BIT_32(X86_GREG_xBP) )
157
158	#elif defined(RT_ARCH_ARM64) \|\| defined(DOXYGEN_RUNNING)
159	# define IEMNATIVE_REG_FIXED_PVMCPU ARMV8_A64_REG_X28
160	# define IEMNATIVE_REG_FIXED_PCPUMCTX ARMV8_A64_REG_X27
161	# define IEMNATIVE_REG_FIXED_TMP0 ARMV8_A64_REG_X15
162	# define IEMNATIVE_REG_FIXED_MASK ( RT_BIT_32(ARMV8_A64_REG_SP) \
163	\| RT_BIT_32(ARMV8_A64_REG_LR) \
164	\| RT_BIT_32(ARMV8_A64_REG_BP) \
165	\| RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU) \
166	\| RT_BIT_32(IEMNATIVE_REG_FIXED_PCPUMCTX) \
167	\| RT_BIT_32(ARMV8_A64_REG_X18) \
168	\| RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0) )
169
170	#else
171	# error "port me"
172	#endif
173	/** @} */
174
175	/** @name Call related registers.
176	* @{ */
177	/** @def IEMNATIVE_CALL_RET_GREG
178	* The return value register. */
179	/** @def IEMNATIVE_CALL_ARG_GREG_COUNT
180	* Number of arguments in registers. */
181	/** @def IEMNATIVE_CALL_ARG0_GREG
182	* The general purpose register carrying argument \#0. */
183	/** @def IEMNATIVE_CALL_ARG1_GREG
184	* The general purpose register carrying argument \#1. */
185	/** @def IEMNATIVE_CALL_ARG2_GREG
186	* The general purpose register carrying argument \#2. */
187	/** @def IEMNATIVE_CALL_ARG3_GREG
188	* The general purpose register carrying argument \#3. */
189	/** @def IEMNATIVE_CALL_VOLATILE_GREG_MASK
190	* Mask of registers the callee will not save and may trash. */
191	#ifdef RT_ARCH_AMD64
192	# define IEMNATIVE_CALL_RET_GREG X86_GREG_xAX
193
194	# ifdef RT_OS_WINDOWS
195	# define IEMNATIVE_CALL_ARG_GREG_COUNT 4
196	# define IEMNATIVE_CALL_ARG0_GREG X86_GREG_xCX
197	# define IEMNATIVE_CALL_ARG1_GREG X86_GREG_xDX
198	# define IEMNATIVE_CALL_ARG2_GREG X86_GREG_x8
199	# define IEMNATIVE_CALL_ARG3_GREG X86_GREG_x9
200	# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \
201	\| RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \
202	\| RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG) \
203	\| RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) )
204	# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(X86_GREG_xAX) \
205	\| RT_BIT_32(X86_GREG_xCX) \
206	\| RT_BIT_32(X86_GREG_xDX) \
207	\| RT_BIT_32(X86_GREG_x8) \
208	\| RT_BIT_32(X86_GREG_x9) \
209	\| RT_BIT_32(X86_GREG_x10) \
210	\| RT_BIT_32(X86_GREG_x11) )
211	# else
212	# define IEMNATIVE_CALL_ARG_GREG_COUNT 6
213	# define IEMNATIVE_CALL_ARG0_GREG X86_GREG_xDI
214	# define IEMNATIVE_CALL_ARG1_GREG X86_GREG_xSI
215	# define IEMNATIVE_CALL_ARG2_GREG X86_GREG_xDX
216	# define IEMNATIVE_CALL_ARG3_GREG X86_GREG_xCX
217	# define IEMNATIVE_CALL_ARG4_GREG X86_GREG_x8
218	# define IEMNATIVE_CALL_ARG5_GREG X86_GREG_x9
219	# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \
220	\| RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \
221	\| RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG) \
222	\| RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) \
223	\| RT_BIT_32(IEMNATIVE_CALL_ARG4_GREG) \
224	\| RT_BIT_32(IEMNATIVE_CALL_ARG5_GREG) )
225	# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(X86_GREG_xAX) \
226	\| RT_BIT_32(X86_GREG_xCX) \
227	\| RT_BIT_32(X86_GREG_xDX) \
228	\| RT_BIT_32(X86_GREG_xDI) \
229	\| RT_BIT_32(X86_GREG_xSI) \
230	\| RT_BIT_32(X86_GREG_x8) \
231	\| RT_BIT_32(X86_GREG_x9) \
232	\| RT_BIT_32(X86_GREG_x10) \
233	\| RT_BIT_32(X86_GREG_x11) )
234	# endif
235
236	#elif defined(RT_ARCH_ARM64)
237	# define IEMNATIVE_CALL_RET_GREG ARMV8_A64_REG_X0
238	# define IEMNATIVE_CALL_ARG_GREG_COUNT 8
239	# define IEMNATIVE_CALL_ARG0_GREG ARMV8_A64_REG_X0
240	# define IEMNATIVE_CALL_ARG1_GREG ARMV8_A64_REG_X1
241	# define IEMNATIVE_CALL_ARG2_GREG ARMV8_A64_REG_X2
242	# define IEMNATIVE_CALL_ARG3_GREG ARMV8_A64_REG_X3
243	# define IEMNATIVE_CALL_ARG4_GREG ARMV8_A64_REG_X4
244	# define IEMNATIVE_CALL_ARG5_GREG ARMV8_A64_REG_X5
245	# define IEMNATIVE_CALL_ARG6_GREG ARMV8_A64_REG_X6
246	# define IEMNATIVE_CALL_ARG7_GREG ARMV8_A64_REG_X7
247	# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(ARMV8_A64_REG_X0) \
248	\| RT_BIT_32(ARMV8_A64_REG_X1) \
249	\| RT_BIT_32(ARMV8_A64_REG_X2) \
250	\| RT_BIT_32(ARMV8_A64_REG_X3) \
251	\| RT_BIT_32(ARMV8_A64_REG_X4) \
252	\| RT_BIT_32(ARMV8_A64_REG_X5) \
253	\| RT_BIT_32(ARMV8_A64_REG_X6) \
254	\| RT_BIT_32(ARMV8_A64_REG_X7) )
255	# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(ARMV8_A64_REG_X0) \
256	\| RT_BIT_32(ARMV8_A64_REG_X1) \
257	\| RT_BIT_32(ARMV8_A64_REG_X2) \
258	\| RT_BIT_32(ARMV8_A64_REG_X3) \
259	\| RT_BIT_32(ARMV8_A64_REG_X4) \
260	\| RT_BIT_32(ARMV8_A64_REG_X5) \
261	\| RT_BIT_32(ARMV8_A64_REG_X6) \
262	\| RT_BIT_32(ARMV8_A64_REG_X7) \
263	\| RT_BIT_32(ARMV8_A64_REG_X8) \
264	\| RT_BIT_32(ARMV8_A64_REG_X9) \
265	\| RT_BIT_32(ARMV8_A64_REG_X10) \
266	\| RT_BIT_32(ARMV8_A64_REG_X11) \
267	\| RT_BIT_32(ARMV8_A64_REG_X12) \
268	\| RT_BIT_32(ARMV8_A64_REG_X13) \
269	\| RT_BIT_32(ARMV8_A64_REG_X14) \
270	\| RT_BIT_32(ARMV8_A64_REG_X15) \
271	\| RT_BIT_32(ARMV8_A64_REG_X16) \
272	\| RT_BIT_32(ARMV8_A64_REG_X17) )
273
274	#endif
275
276	/** This is the maximum argument count we'll ever be needing. */
277	#if defined(RT_OS_WINDOWS) && defined(VBOXSTRICTRC_STRICT_ENABLED)
278	# define IEMNATIVE_CALL_MAX_ARG_COUNT 8
279	#else
280	# define IEMNATIVE_CALL_MAX_ARG_COUNT 7
281	#endif
282	/** @} */
283
284
285	/** @def IEMNATIVE_HST_GREG_COUNT
286	* Number of host general purpose registers we tracker. */
287	/** @def IEMNATIVE_HST_GREG_MASK
288	* Mask corresponding to IEMNATIVE_HST_GREG_COUNT that can be applied to
289	* inverted register masks and such to get down to a correct set of regs. */
290	#ifdef RT_ARCH_AMD64
291	# define IEMNATIVE_HST_GREG_COUNT 16
292	# define IEMNATIVE_HST_GREG_MASK UINT32_C(0xffff)
293
294	#elif defined(RT_ARCH_ARM64)
295	# define IEMNATIVE_HST_GREG_COUNT 32
296	# define IEMNATIVE_HST_GREG_MASK UINT32_MAX
297	#else
298	# error "Port me!"
299	#endif
300
301
302	/** Native code generator label types. */
303	typedef enum
304	{
305	kIemNativeLabelType_Invalid = 0,
306	/* Labels w/o data, only once instance per TB: */
307	kIemNativeLabelType_Return,
308	kIemNativeLabelType_ReturnBreak,
309	kIemNativeLabelType_ReturnWithFlags,
310	kIemNativeLabelType_NonZeroRetOrPassUp,
311	kIemNativeLabelType_RaiseGp0,
312	kIemNativeLabelType_ObsoleteTb,
313	kIemNativeLabelType_NeedCsLimChecking,
314	kIemNativeLabelType_CheckBranchMiss,
315	/* Labels with data, potentially multiple instances per TB: */
316	kIemNativeLabelType_FirstWithMultipleInstances,
317	kIemNativeLabelType_If = kIemNativeLabelType_FirstWithMultipleInstances,
318	kIemNativeLabelType_Else,
319	kIemNativeLabelType_Endif,
320	kIemNativeLabelType_CheckIrq,
321	kIemNativeLabelType_TlbLookup,
322	kIemNativeLabelType_TlbMiss,
323	kIemNativeLabelType_TlbDone,
324	kIemNativeLabelType_End
325	} IEMNATIVELABELTYPE;
326
327	/** Native code generator label definition. */
328	typedef struct IEMNATIVELABEL
329	{
330	/** Code offset if defined, UINT32_MAX if it needs to be generated after/in
331	* the epilog. */
332	uint32_t off;
333	/** The type of label (IEMNATIVELABELTYPE). */
334	uint16_t enmType;
335	/** Additional label data, type specific. */
336	uint16_t uData;
337	} IEMNATIVELABEL;
338	/** Pointer to a label. */
339	typedef IEMNATIVELABEL *PIEMNATIVELABEL;
340
341
342	/** Native code generator fixup types. */
343	typedef enum
344	{
345	kIemNativeFixupType_Invalid = 0,
346	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
347	/** AMD64 fixup: PC relative 32-bit with addend in bData. */
348	kIemNativeFixupType_Rel32,
349	#elif defined(RT_ARCH_ARM64)
350	/** ARM64 fixup: PC relative offset at bits 25:0 (B, BL). */
351	kIemNativeFixupType_RelImm26At0,
352	/** ARM64 fixup: PC relative offset at bits 23:5 (CBZ, CBNZ, B.CC). */
353	kIemNativeFixupType_RelImm19At5,
354	/** ARM64 fixup: PC relative offset at bits 18:5 (TBZ, TBNZ). */
355	kIemNativeFixupType_RelImm14At5,
356	#endif
357	kIemNativeFixupType_End
358	} IEMNATIVEFIXUPTYPE;
359
360	/** Native code generator fixup. */
361	typedef struct IEMNATIVEFIXUP
362	{
363	/** Code offset of the fixup location. */
364	uint32_t off;
365	/** The IEMNATIVELABEL this is a fixup for. */
366	uint16_t idxLabel;
367	/** The fixup type (IEMNATIVEFIXUPTYPE). */
368	uint8_t enmType;
369	/** Addend or other data. */
370	int8_t offAddend;
371	} IEMNATIVEFIXUP;
372	/** Pointer to a native code generator fixup. */
373	typedef IEMNATIVEFIXUP *PIEMNATIVEFIXUP;
374
375
376	/**
377	* Guest registers that can be shadowed in GPRs.
378	*/
379	typedef enum IEMNATIVEGSTREG : uint8_t
380	{
381	kIemNativeGstReg_GprFirst = 0,
382	kIemNativeGstReg_GprLast = kIemNativeGstReg_GprFirst + 15,
383	kIemNativeGstReg_Pc,
384	kIemNativeGstReg_EFlags, /*< 32-bit, includes internal flags. /
385	kIemNativeGstReg_SegSelFirst,
386	kIemNativeGstReg_SegSelLast = kIemNativeGstReg_SegSelFirst + 5,
387	kIemNativeGstReg_SegBaseFirst,
388	kIemNativeGstReg_SegBaseLast = kIemNativeGstReg_SegBaseFirst + 5,
389	kIemNativeGstReg_SegLimitFirst,
390	kIemNativeGstReg_SegLimitLast = kIemNativeGstReg_SegLimitFirst + 5,
391	kIemNativeGstReg_SegAttribFirst,
392	kIemNativeGstReg_SegAttribLast = kIemNativeGstReg_SegAttribFirst + 5,
393	kIemNativeGstReg_End
394	} IEMNATIVEGSTREG;
395
396	/** @name Helpers for converting register numbers to IEMNATIVEGSTREG values.
397	* @{ */
398	#define IEMNATIVEGSTREG_GPR(a_iGpr) ((IEMNATIVEGSTREG)(kIemNativeGstReg_GprFirst + (a_iGpr) ))
399	#define IEMNATIVEGSTREG_SEG_SEL(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegSelFirst + (a_iSegReg) ))
400	#define IEMNATIVEGSTREG_SEG_BASE(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegBaseFirst + (a_iSegReg) ))
401	#define IEMNATIVEGSTREG_SEG_LIMIT(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegLimitFirst + (a_iSegReg) ))
402	#define IEMNATIVEGSTREG_SEG_ATTRIB(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegAttribFirst + (a_iSegReg) ))
403	/** @} */
404
405	/**
406	* Intended use statement for iemNativeRegAllocTmpForGuestReg().
407	*/
408	typedef enum IEMNATIVEGSTREGUSE
409	{
410	/** The usage is read-only, the register holding the guest register
411	* shadow copy will not be modified by the caller. */
412	kIemNativeGstRegUse_ReadOnly = 0,
413	/** The caller will update the guest register (think: PC += cbInstr).
414	* The guest shadow copy will follow the returned register. */
415	kIemNativeGstRegUse_ForUpdate,
416	/** The call will put an entirely new value in the guest register, so
417	* if new register is allocate it will be returned uninitialized. */
418	kIemNativeGstRegUse_ForFullWrite,
419	/** The caller will use the guest register value as input in a calculation
420	* and the host register will be modified.
421	* This means that the returned host register will not be marked as a shadow
422	* copy of the guest register. */
423	kIemNativeGstRegUse_Calculation
424	} IEMNATIVEGSTREGUSE;
425
426	/**
427	* Guest registers (classes) that can be referenced.
428	*/
429	typedef enum IEMNATIVEGSTREGREF : uint8_t
430	{
431	kIemNativeGstRegRef_Invalid = 0,
432	kIemNativeGstRegRef_Gpr,
433	kIemNativeGstRegRef_GprHighByte, /*< AH, CH, DH, BH/
434	kIemNativeGstRegRef_EFlags,
435	kIemNativeGstRegRef_MxCsr,
436	kIemNativeGstRegRef_FpuReg,
437	kIemNativeGstRegRef_MReg,
438	kIemNativeGstRegRef_XReg,
439	//kIemNativeGstRegRef_YReg, - doesn't work.
440	kIemNativeGstRegRef_End
441	} IEMNATIVEGSTREGREF;
442
443
444	/** Variable kinds. */
445	typedef enum IEMNATIVEVARKIND : uint8_t
446	{
447	/** Customary invalid zero value. */
448	kIemNativeVarKind_Invalid = 0,
449	/** This is either in a register or on the stack. */
450	kIemNativeVarKind_Stack,
451	/** Immediate value - loaded into register when needed, or can live on the
452	* stack if referenced (in theory). */
453	kIemNativeVarKind_Immediate,
454	/** Variable reference - loaded into register when needed, never stack. */
455	kIemNativeVarKind_VarRef,
456	/** Guest register reference - loaded into register when needed, never stack. */
457	kIemNativeVarKind_GstRegRef,
458	/** End of valid values. */
459	kIemNativeVarKind_End
460	} IEMNATIVEVARKIND;
461
462
463	/** Variable or argument. */
464	typedef struct IEMNATIVEVAR
465	{
466	/** The kind of variable. */
467	IEMNATIVEVARKIND enmKind;
468	/** The variable size in bytes. */
469	uint8_t cbVar;
470	/** The first stack slot (uint64_t), except for immediate and references
471	* where it usually is UINT8_MAX. This is allocated lazily, so if a variable
472	* has a stack slot it has been initialized and has a value. Unused variables
473	* has neither a stack slot nor a host register assignment. */
474	uint8_t idxStackSlot;
475	/** The host register allocated for the variable, UINT8_MAX if not. */
476	uint8_t idxReg;
477	/** The argument number if argument, UINT8_MAX if regular variable. */
478	uint8_t uArgNo;
479	/** If referenced, the index of the variable referencing this one, otherwise
480	* UINT8_MAX. A referenced variable must only be placed on the stack and
481	* must be either kIemNativeVarKind_Stack or kIemNativeVarKind_Immediate. */
482	uint8_t idxReferrerVar;
483	/** Guest register being shadowed here, kIemNativeGstReg_End(/UINT8_MAX) if not.
484	* @todo not sure what this really is for... */
485	IEMNATIVEGSTREG enmGstReg;
486	/** Set if the registered is currently used exclusively, false if the
487	* variable is idle and the register can be grabbed. */
488	bool fRegAcquired;
489
490	union
491	{
492	/** kIemNativeVarKind_Immediate: The immediate value. */
493	uint64_t uValue;
494	/** kIemNativeVarKind_VarRef: The index of the variable being referenced. */
495	uint8_t idxRefVar;
496	/** kIemNativeVarKind_GstRegRef: The guest register being referrenced. */
497	struct
498	{
499	/** The class of register. */
500	IEMNATIVEGSTREGREF enmClass;
501	/** Index within the class. */
502	uint8_t idx;
503	} GstRegRef;
504	} u;
505	} IEMNATIVEVAR;
506
507	/** What is being kept in a host register. */
508	typedef enum IEMNATIVEWHAT : uint8_t
509	{
510	/** The traditional invalid zero value. */
511	kIemNativeWhat_Invalid = 0,
512	/** Mapping a variable (IEMNATIVEHSTREG::idxVar). */
513	kIemNativeWhat_Var,
514	/** Temporary register, this is typically freed when a MC completes. */
515	kIemNativeWhat_Tmp,
516	/** Call argument w/o a variable mapping. This is free (via
517	* IEMNATIVE_CALL_VOLATILE_GREG_MASK) after the call is emitted. */
518	kIemNativeWhat_Arg,
519	/** Return status code.
520	* @todo not sure if we need this... */
521	kIemNativeWhat_rc,
522	/** The fixed pVCpu (PVMCPUCC) register.
523	* @todo consider offsetting this on amd64 to use negative offsets to access
524	* more members using 8-byte disp. */
525	kIemNativeWhat_pVCpuFixed,
526	/** The fixed pCtx (PCPUMCTX) register.
527	* @todo consider offsetting this on amd64 to use negative offsets to access
528	* more members using 8-byte disp. */
529	kIemNativeWhat_pCtxFixed,
530	/** Fixed temporary register. */
531	kIemNativeWhat_FixedTmp,
532	/** Register reserved by the CPU or OS architecture. */
533	kIemNativeWhat_FixedReserved,
534	/** End of valid values. */
535	kIemNativeWhat_End
536	} IEMNATIVEWHAT;
537
538	/**
539	* Host general register entry.
540	*
541	* The actual allocation status is kept in IEMRECOMPILERSTATE::bmHstRegs.
542	*
543	* @todo Track immediate values in host registers similarlly to how we track the
544	* guest register shadow copies. For it to be real helpful, though,
545	* we probably need to know which will be reused and put them into
546	* non-volatile registers, otherwise it's going to be more or less
547	* restricted to an instruction or two.
548	*/
549	typedef struct IEMNATIVEHSTREG
550	{
551	/** Set of guest registers this one shadows.
552	*
553	* Using a bitmap here so we can designate the same host register as a copy
554	* for more than one guest register. This is expected to be useful in
555	* situations where one value is copied to several registers in a sequence.
556	* If the mapping is 1:1, then we'd have to pick which side of a 'MOV SRC,DST'
557	* sequence we'd want to let this register follow to be a copy of and there
558	* will always be places where we'd be picking the wrong one.
559	*/
560	uint64_t fGstRegShadows;
561	/** What is being kept in this register. */
562	IEMNATIVEWHAT enmWhat;
563	/** Variable index if holding a variable, otherwise UINT8_MAX. */
564	uint8_t idxVar;
565	/** Alignment padding. */
566	uint8_t abAlign[6];
567	} IEMNATIVEHSTREG;
568
569
570	/**
571	* Core state for the native recompiler, that is, things that needs careful
572	* handling when dealing with branches.
573	*/
574	typedef struct IEMNATIVECORESTATE
575	{
576	/** Allocation bitmap for aHstRegs. */
577	uint32_t bmHstRegs;
578
579	/** Bitmap marking which host register contains guest register shadow copies.
580	* This is used during register allocation to try preserve copies. */
581	uint32_t bmHstRegsWithGstShadow;
582	/** Bitmap marking valid entries in aidxGstRegShadows. */
583	uint64_t bmGstRegShadows;
584
585	union
586	{
587	/** Index of variable arguments, UINT8_MAX if not valid. */
588	uint8_t aidxArgVars[8];
589	/** For more efficient resetting. */
590	uint64_t u64ArgVars;
591	};
592
593	/** Allocation bitmap for the stack. */
594	uint32_t bmStack;
595	/** Allocation bitmap for aVars. */
596	uint32_t bmVars;
597
598	/** Maps a guest register to a host GPR (index by IEMNATIVEGSTREG).
599	* Entries are only valid if the corresponding bit in bmGstRegShadows is set.
600	* (A shadow copy of a guest register can only be held in a one host register,
601	* there are no duplicate copies or ambiguities like that). */
602	uint8_t aidxGstRegShadows[kIemNativeGstReg_End];
603
604	/** Host register allocation tracking. */
605	IEMNATIVEHSTREG aHstRegs[IEMNATIVE_HST_GREG_COUNT];
606
607	/** Variables and arguments. */
608	IEMNATIVEVAR aVars[9];
609	} IEMNATIVECORESTATE;
610	/** Pointer to core state. */
611	typedef IEMNATIVECORESTATE *PIEMNATIVECORESTATE;
612	/** Pointer to const core state. */
613	typedef IEMNATIVECORESTATE const *PCIEMNATIVECORESTATE;
614
615
616	/**
617	* Conditional stack entry.
618	*/
619	typedef struct IEMNATIVECOND
620	{
621	/** Set if we're in the "else" part, clear if we're in the "if" before it. */
622	bool fInElse;
623	/** The label for the IEM_MC_ELSE. */
624	uint32_t idxLabelElse;
625	/** The label for the IEM_MC_ENDIF. */
626	uint32_t idxLabelEndIf;
627	/** The initial state snapshot as the if-block starts executing. */
628	IEMNATIVECORESTATE InitialState;
629	/** The state snapshot at the end of the if-block. */
630	IEMNATIVECORESTATE IfFinalState;
631	} IEMNATIVECOND;
632	/** Pointer to a condition stack entry. */
633	typedef IEMNATIVECOND *PIEMNATIVECOND;
634
635
636	/**
637	* Native recompiler state.
638	*/
639	typedef struct IEMRECOMPILERSTATE
640	{
641	/** Size of the buffer that pbNativeRecompileBufR3 points to in
642	* IEMNATIVEINSTR units. */
643	uint32_t cInstrBufAlloc;
644	#ifdef VBOX_STRICT
645	/** Strict: How far the last iemNativeInstrBufEnsure() checked. */
646	uint32_t offInstrBufChecked;
647	#else
648	uint32_t uPadding1; /* We don't keep track of the size here... */
649	#endif
650	/** Fixed temporary code buffer for native recompilation. */
651	PIEMNATIVEINSTR pInstrBuf;
652
653	/** Bitmaps with the label types used. */
654	uint64_t bmLabelTypes;
655	/** Actual number of labels in paLabels. */
656	uint32_t cLabels;
657	/** Max number of entries allowed in paLabels before reallocating it. */
658	uint32_t cLabelsAlloc;
659	/** Labels defined while recompiling (referenced by fixups). */
660	PIEMNATIVELABEL paLabels;
661	/** Array with indexes of unique labels (uData always 0). */
662	uint32_t aidxUniqueLabels[kIemNativeLabelType_FirstWithMultipleInstances];
663
664	/** Actual number of fixups paFixups. */
665	uint32_t cFixups;
666	/** Max number of entries allowed in paFixups before reallocating it. */
667	uint32_t cFixupsAlloc;
668	/** Buffer used by the recompiler for recording fixups when generating code. */
669	PIEMNATIVEFIXUP paFixups;
670
671	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
672	/** Number of debug info entries allocated for pDbgInfo. */
673	uint32_t cDbgInfoAlloc;
674	uint32_t uPadding;
675	/** Debug info. */
676	PIEMTBDBG pDbgInfo;
677	#endif
678
679	/** The translation block being recompiled. */
680	PCIEMTB pTbOrg;
681
682	/** Condition sequence number (for generating unique labels). */
683	uint16_t uCondSeqNo;
684	/** Check IRQ seqeunce number (for generating unique labels). */
685	uint16_t uCheckIrqSeqNo;
686	/** TLB load sequence number (for generating unique labels). */
687	uint16_t uTlbSeqNo;
688	/** The current condition stack depth (aCondStack). */
689	uint8_t cCondDepth;
690
691	/** The argument count + hidden regs from the IEM_MC_BEGIN statement. */
692	uint8_t cArgs;
693	/** The IEM_CIMPL_F_XXX flags from the IEM_MC_BEGIN statement. */
694	uint32_t fCImpl;
695	/** The IEM_MC_F_XXX flags from the IEM_MC_BEGIN statement. */
696	uint32_t fMc;
697	/** The expected IEMCPU::fExec value for the current call/instruction. */
698	uint32_t fExec;
699
700	/** Core state requiring care with branches. */
701	IEMNATIVECORESTATE Core;
702
703	/** The condition nesting stack. */
704	IEMNATIVECOND aCondStack[2];
705
706	#ifndef IEM_WITH_THROW_CATCH
707	/** Pointer to the setjmp/longjmp buffer if we're not using C++ exceptions
708	* for recompilation error handling. */
709	jmp_buf JmpBuf;
710	#endif
711	} IEMRECOMPILERSTATE;
712	/** Pointer to a native recompiler state. */
713	typedef IEMRECOMPILERSTATE *PIEMRECOMPILERSTATE;
714
715
716	/** @def IEMNATIVE_TRY_SETJMP
717	* Wrapper around setjmp / try, hiding all the ugly differences.
718	*
719	* @note Use with extreme care as this is a fragile macro.
720	* @param a_pReNative The native recompile state.
721	* @param a_rcTarget The variable that should receive the status code in case
722	* of a longjmp/throw.
723	*/
724	/** @def IEMNATIVE_CATCH_LONGJMP_BEGIN
725	* Start wrapper for catch / setjmp-else.
726	*
727	* This will set up a scope.
728	*
729	* @note Use with extreme care as this is a fragile macro.
730	* @param a_pReNative The native recompile state.
731	* @param a_rcTarget The variable that should receive the status code in case
732	* of a longjmp/throw.
733	*/
734	/** @def IEMNATIVE_CATCH_LONGJMP_END
735	* End wrapper for catch / setjmp-else.
736	*
737	* This will close the scope set up by IEMNATIVE_CATCH_LONGJMP_BEGIN and clean
738	* up the state.
739	*
740	* @note Use with extreme care as this is a fragile macro.
741	* @param a_pReNative The native recompile state.
742	*/
743	/** @def IEMNATIVE_DO_LONGJMP
744	*
745	* Wrapper around longjmp / throw.
746	*
747	* @param a_pReNative The native recompile state.
748	* @param a_rc The status code jump back with / throw.
749	*/
750	#ifdef IEM_WITH_THROW_CATCH
751	# define IEMNATIVE_TRY_SETJMP(a_pReNative, a_rcTarget) \
752	a_rcTarget = VINF_SUCCESS; \
753	try
754	# define IEMNATIVE_CATCH_LONGJMP_BEGIN(a_pReNative, a_rcTarget) \
755	catch (int rcThrown) \
756	{ \
757	a_rcTarget = rcThrown
758	# define IEMNATIVE_CATCH_LONGJMP_END(a_pReNative) \
759	} \
760	((void)0)
761	# define IEMNATIVE_DO_LONGJMP(a_pReNative, a_rc) throw int(a_rc)
762	#else /* !IEM_WITH_THROW_CATCH */
763	# define IEMNATIVE_TRY_SETJMP(a_pReNative, a_rcTarget) \
764	if ((a_rcTarget = setjmp((a_pReNative)->JmpBuf)) == 0)
765	# define IEMNATIVE_CATCH_LONGJMP_BEGIN(a_pReNative, a_rcTarget) \
766	else \
767	{ \
768	((void)0)
769	# define IEMNATIVE_CATCH_LONGJMP_END(a_pReNative) \
770	}
771	# define IEMNATIVE_DO_LONGJMP(a_pReNative, a_rc) longjmp((a_pReNative)->JmpBuf, (a_rc))
772	#endif /* !IEM_WITH_THROW_CATCH */
773
774
775	/**
776	* Native recompiler worker for a threaded function.
777	*
778	* @returns New code buffer offset; throws VBox status code in case of a failure.
779	* @param pReNative The native recompiler state.
780	* @param off The current code buffer offset.
781	* @param pCallEntry The threaded call entry.
782	*
783	* @note This may throw/longjmp VBox status codes (int) to abort compilation, so no RT_NOEXCEPT!
784	*/
785	typedef uint32_t (VBOXCALL FNIEMNATIVERECOMPFUNC)(PIEMRECOMPILERSTATE pReNative, uint32_t off, PCIEMTHRDEDCALLENTRY pCallEntry);
786	/** Pointer to a native recompiler worker for a threaded function. */
787	typedef FNIEMNATIVERECOMPFUNC *PFNIEMNATIVERECOMPFUNC;
788
789	/** Defines a native recompiler worker for a threaded function.
790	* @see FNIEMNATIVERECOMPFUNC */
791	#define IEM_DECL_IEMNATIVERECOMPFUNC_DEF(a_Name) \
792	uint32_t VBOXCALL a_Name(PIEMRECOMPILERSTATE pReNative, uint32_t off, PCIEMTHRDEDCALLENTRY pCallEntry)
793
794	/** Prototypes a native recompiler function for a threaded function.
795	* @see FNIEMNATIVERECOMPFUNC */
796	#define IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(a_Name) FNIEMNATIVERECOMPFUNC a_Name
797
798
799	/** Define a native recompiler helper function, safe to call from the TB code. */
800	#define IEM_DECL_NATIVE_HLP_DEF(a_RetType, a_Name, a_ArgList) \
801	DECL_HIDDEN_THROW(a_RetType) VBOXCALL a_Name a_ArgList
802	/** Prototype a native recompiler helper function, safe to call from the TB code. */
803	#define IEM_DECL_NATIVE_HLP_PROTO(a_RetType, a_Name, a_ArgList) \
804	DECL_HIDDEN_THROW(a_RetType) VBOXCALL a_Name a_ArgList
805
806
807	DECL_HIDDEN_THROW(uint32_t) iemNativeLabelCreate(PIEMRECOMPILERSTATE pReNative, IEMNATIVELABELTYPE enmType,
808	uint32_t offWhere = UINT32_MAX, uint16_t uData = 0);
809	DECL_HIDDEN_THROW(void) iemNativeLabelDefine(PIEMRECOMPILERSTATE pReNative, uint32_t idxLabel, uint32_t offWhere);
810	DECL_HIDDEN_THROW(void) iemNativeAddFixup(PIEMRECOMPILERSTATE pReNative, uint32_t offWhere, uint32_t idxLabel,
811	IEMNATIVEFIXUPTYPE enmType, int8_t offAddend = 0);
812	DECL_HIDDEN_THROW(PIEMNATIVEINSTR) iemNativeInstrBufEnsureSlow(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t cInstrReq);
813
814	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmp(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, bool fPreferVolatile = true);
815	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpEx(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint32_t fRegMask,
816	bool fPreferVolatile = true);
817	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpImm(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint64_t uImm,
818	bool fPreferVolatile = true);
819	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpForGuestReg(PIEMRECOMPILERSTATE pReNative, uint32_t *poff,
820	IEMNATIVEGSTREG enmGstReg,
821	IEMNATIVEGSTREGUSE enmIntendedUse = kIemNativeGstRegUse_ReadOnly,
822	bool fNoVoltileRegs = false);
823	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpForGuestRegIfAlreadyPresent(PIEMRECOMPILERSTATE pReNative, uint32_t *poff,
824	IEMNATIVEGSTREG enmGstReg);
825
826	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocVar(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint8_t idxVar);
827	DECL_HIDDEN_THROW(uint32_t) iemNativeRegAllocArgs(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs);
828	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAssignRc(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg);
829	DECLHIDDEN(void) iemNativeRegFree(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
830	DECLHIDDEN(void) iemNativeRegFreeTmp(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
831	DECLHIDDEN(void) iemNativeRegFreeTmpImm(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
832	DECLHIDDEN(void) iemNativeRegFreeVar(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg, bool fFlushShadows) RT_NOEXCEPT;
833	DECLHIDDEN(void) iemNativeRegFreeAndFlushMask(PIEMRECOMPILERSTATE pReNative, uint32_t fHstRegMask) RT_NOEXCEPT;
834	DECL_HIDDEN_THROW(uint32_t) iemNativeRegFlushPendingWrites(PIEMRECOMPILERSTATE pReNative, uint32_t off);
835	DECL_HIDDEN_THROW(uint32_t) iemNativeRegMoveAndFreeAndFlushAtCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs,
836	uint32_t fKeepVars = 0);
837	DECLHIDDEN(void) iemNativeRegFlushGuestShadows(PIEMRECOMPILERSTATE pReNative, uint64_t fGstRegs) RT_NOEXCEPT;
838	DECLHIDDEN(void) iemNativeRegFlushGuestShadowsByHostMask(PIEMRECOMPILERSTATE pReNative, uint32_t fHstRegs) RT_NOEXCEPT;
839
840	DECL_HIDDEN_THROW(uint8_t) iemNativeVarGetStackSlot(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar);
841	DECL_HIDDEN_THROW(uint8_t) iemNativeVarRegisterAcquireForGuestReg(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar,
842	IEMNATIVEGSTREG enmGstReg, uint32_t *poff);
843
844
845	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitLoadGprWithGstShadowReg(PIEMRECOMPILERSTATE pReNative, uint32_t off,
846	uint8_t idxHstReg, IEMNATIVEGSTREG enmGstReg);
847	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitCheckCallRetAndPassUp(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr);
848	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitCImplCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr,
849	uint64_t fGstShwFlush, uintptr_t pfnCImpl, uint8_t cbInstr, uint8_t cAddParams,
850	uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
851	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitThreadedCall(PIEMRECOMPILERSTATE pReNative, uint32_t off,
852	PCIEMTHRDEDCALLENTRY pCallEntry);
853
854	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_Nop);
855	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_LogCpuState);
856	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_DeferToCImpl0);
857	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckIrq);
858	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckMode);
859	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckCsLim);
860	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckCsLimAndOpcodes);
861	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckOpcodes);
862	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckOpcodesConsiderCsLim);
863	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckCsLimAndPcAndOpcodes);
864	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckPcAndOpcodes);
865	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckPcAndOpcodesConsiderCsLim);
866	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckCsLimAndOpcodesLoadingTlb);
867	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckOpcodesLoadingTlb);
868	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckOpcodesLoadingTlbConsiderCsLim);
869	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckCsLimAndOpcodesAcrossPageLoadingTlb);
870	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckOpcodesAcrossPageLoadingTlb);
871	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckOpcodesAcrossPageLoadingTlbConsiderCsLim);
872	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckCsLimAndOpcodesOnNextPageLoadingTlb);
873	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckOpcodesOnNextPageLoadingTlb);
874	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckOpcodesOnNextPageLoadingTlbConsiderCsLim);
875	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckCsLimAndOpcodesOnNewPageLoadingTlb);
876	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckOpcodesOnNewPageLoadingTlb);
877	IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(iemNativeRecompFunc_BltIn_CheckOpcodesOnNewPageLoadingTlbConsiderCsLim);
878
879	extern DECL_HIDDEN_DATA(const char * const) g_apszIemNativeHstRegNames[];
880
881
882	/**
883	* Ensures that there is sufficient space in the instruction output buffer.
884	*
885	* This will reallocate the buffer if needed and allowed.
886	*
887	* @note Always use IEMNATIVE_ASSERT_INSTR_BUF_ENSURE when done to check the
888	* allocation size.
889	*
890	* @returns Pointer to the instruction output buffer on success; throws VBox
891	* status code on failure, so no need to check it.
892	* @param pReNative The native recompile state.
893	* @param off Current instruction offset. Works safely for UINT32_MAX
894	* as well.
895	* @param cInstrReq Number of instruction about to be added. It's okay to
896	* overestimate this a bit.
897	*/
898	DECL_FORCE_INLINE_THROW(PIEMNATIVEINSTR)
899	iemNativeInstrBufEnsure(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t cInstrReq)
900	{
901	uint64_t const offChecked = off + (uint64_t)cInstrReq; /** @todo may reconsider the need for UINT32_MAX safety... */
902	if (RT_LIKELY(offChecked <= pReNative->cInstrBufAlloc))
903	{
904	#ifdef VBOX_STRICT
905	pReNative->offInstrBufChecked = offChecked;
906	#endif
907	return pReNative->pInstrBuf;
908	}
909	return iemNativeInstrBufEnsureSlow(pReNative, off, cInstrReq);
910	}
911
912	/**
913	* Checks that we didn't exceed the space requested in the last
914	* iemNativeInstrBufEnsure() call.
915	*/
916	#define IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(a_pReNative, a_off) \
917	AssertMsg((a_off) <= (a_pReNative)->offInstrBufChecked, \
918	("off=%#x offInstrBufChecked=%#x\n", (a_off), (a_pReNative)->offInstrBufChecked))
919
920	/**
921	* Checks that a variable index is valid.
922	*/
923	#define IEMNATIVE_ASSERT_VAR_IDX(a_pReNative, a_idxVar) \
924	AssertMsg( (unsigned)(a_idxVar) < RT_ELEMENTS((a_pReNative)->Core.aVars) \
925	&& ((a_pReNative)->Core.bmVars & RT_BIT_32(a_idxVar)), ("%s=%d\n", #a_idxVar, a_idxVar))
926
927	/**
928	* Checks that a variable index is valid and that the variable is assigned the
929	* correct argument number.
930	* This also adds a RT_NOREF of a_idxVar.
931	*/
932	#define IEMNATIVE_ASSERT_ARG_VAR_IDX(a_pReNative, a_idxVar, a_uArgNo) do { \
933	RT_NOREF_PV(a_idxVar); \
934	AssertMsg( (unsigned)(a_idxVar) < RT_ELEMENTS((a_pReNative)->Core.aVars) \
935	&& ((a_pReNative)->Core.bmVars & RT_BIT_32(a_idxVar))\
936	&& (a_pReNative)->Core.aVars[a_idxVar].uArgNo == (a_uArgNo) \
937	, ("%s=%d; uArgNo=%d, expected %u\n", #a_idxVar, a_idxVar, \
938	(a_pReNative)->Core.aVars[RT_MAX(a_idxVar, RT_ELEMENTS((a_pReNative)->Core.aVars)) - 1].uArgNo, a_uArgNo)); \
939	} while (0)
940
941	/**
942	* Calculates the stack address of a variable as a [r]BP displacement value.
943	*/
944	DECL_FORCE_INLINE(int32_t)
945	iemNativeStackCalcBpDisp(uint8_t idxStackSlot)
946	{
947	Assert(idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS);
948	return idxStackSlot * sizeof(uint64_t) + IEMNATIVE_FP_OFF_STACK_VARS;
949	}
950
951	/** @} */
952
953	#endif /* !VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h */
954

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source: vbox/trunk/src/VBox/VMM/include/IEMN8veRecompiler.h@ 102734

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