IEMN8veRecompiler.h@ 103589

Last change on this file since 103589 was 103589, checked in by vboxsync, 14 months ago
VMM/IEM: Native translation of IEM_MC_FETCH_FCW() body, bugref:10371
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1	/* $Id: IEMN8veRecompiler.h 103589 2024-02-27 16:14:12Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager - Native Recompiler Internals.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h
29	#define VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34
35	/** @defgroup grp_iem_n8ve_re Native Recompiler Internals.
36	* @ingroup grp_iem_int
37	* @{
38	*/
39
40	/** @def IEMNATIVE_WITH_TB_DEBUG_INFO
41	* Enables generating internal debug info for better TB disassembly dumping. */
42	#if defined(DEBUG) \|\| defined(DOXYGEN_RUNNING)
43	# define IEMNATIVE_WITH_TB_DEBUG_INFO
44	#endif
45
46	/** @def IEMNATIVE_WITH_LIVENESS_ANALYSIS
47	* Enables liveness analysis. */
48	#if 1 \|\| defined(DOXYGEN_RUNNING)
49	# define IEMNATIVE_WITH_LIVENESS_ANALYSIS
50	/# define IEMLIVENESS_EXTENDED_LAYOUT/
51	#endif
52
53	#ifdef VBOX_WITH_STATISTICS
54	/** Always count instructions for now. */
55	# define IEMNATIVE_WITH_INSTRUCTION_COUNTING
56	#endif
57
58
59	/** @name Stack Frame Layout
60	*
61	* @{ */
62	/** The size of the area for stack variables and spills and stuff.
63	* @note This limit is duplicated in the python script(s). We add 0x40 for
64	* alignment padding. */
65	#define IEMNATIVE_FRAME_VAR_SIZE (0xc0 + 0x40)
66	/** Number of 64-bit variable slots (0x100 / 8 = 32. */
67	#define IEMNATIVE_FRAME_VAR_SLOTS (IEMNATIVE_FRAME_VAR_SIZE / 8)
68	AssertCompile(IEMNATIVE_FRAME_VAR_SLOTS == 32);
69
70	#ifdef RT_ARCH_AMD64
71	/** An stack alignment adjustment (between non-volatile register pushes and
72	* the stack variable area, so the latter better aligned). */
73	# define IEMNATIVE_FRAME_ALIGN_SIZE 8
74
75	/** Number of stack arguments slots for calls made from the frame. */
76	# ifdef RT_OS_WINDOWS
77	# define IEMNATIVE_FRAME_STACK_ARG_COUNT 4
78	# else
79	# define IEMNATIVE_FRAME_STACK_ARG_COUNT 2
80	# endif
81	/** Number of any shadow arguments (spill area) for calls we make. */
82	# ifdef RT_OS_WINDOWS
83	# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 4
84	# else
85	# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 0
86	# endif
87
88	/** Frame pointer (RBP) relative offset of the last push. */
89	# ifdef RT_OS_WINDOWS
90	# define IEMNATIVE_FP_OFF_LAST_PUSH (7 * -8)
91	# else
92	# define IEMNATIVE_FP_OFF_LAST_PUSH (5 * -8)
93	# endif
94	/** Frame pointer (RBP) relative offset of the stack variable area (the lowest
95	* address for it). */
96	# define IEMNATIVE_FP_OFF_STACK_VARS (IEMNATIVE_FP_OFF_LAST_PUSH - IEMNATIVE_FRAME_ALIGN_SIZE - IEMNATIVE_FRAME_VAR_SIZE)
97	/** Frame pointer (RBP) relative offset of the first stack argument for calls. */
98	# define IEMNATIVE_FP_OFF_STACK_ARG0 (IEMNATIVE_FP_OFF_STACK_VARS - IEMNATIVE_FRAME_STACK_ARG_COUNT * 8)
99	/** Frame pointer (RBP) relative offset of the second stack argument for calls. */
100	# define IEMNATIVE_FP_OFF_STACK_ARG1 (IEMNATIVE_FP_OFF_STACK_ARG0 + 8)
101	# ifdef RT_OS_WINDOWS
102	/** Frame pointer (RBP) relative offset of the third stack argument for calls. */
103	# define IEMNATIVE_FP_OFF_STACK_ARG2 (IEMNATIVE_FP_OFF_STACK_ARG0 + 16)
104	/** Frame pointer (RBP) relative offset of the fourth stack argument for calls. */
105	# define IEMNATIVE_FP_OFF_STACK_ARG3 (IEMNATIVE_FP_OFF_STACK_ARG0 + 24)
106	# endif
107
108	# ifdef RT_OS_WINDOWS
109	/** Frame pointer (RBP) relative offset of the first incoming shadow argument. */
110	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG0 (16)
111	/** Frame pointer (RBP) relative offset of the second incoming shadow argument. */
112	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG1 (24)
113	/** Frame pointer (RBP) relative offset of the third incoming shadow argument. */
114	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG2 (32)
115	/** Frame pointer (RBP) relative offset of the fourth incoming shadow argument. */
116	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG3 (40)
117	# endif
118
119	#elif RT_ARCH_ARM64
120	/** No alignment padding needed for arm64. */
121	# define IEMNATIVE_FRAME_ALIGN_SIZE 0
122	/** No stack argument slots, got 8 registers for arguments will suffice. */
123	# define IEMNATIVE_FRAME_STACK_ARG_COUNT 0
124	/** There are no argument spill area. */
125	# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 0
126
127	/** Number of saved registers at the top of our stack frame.
128	* This includes the return address and old frame pointer, so x19 thru x30. */
129	# define IEMNATIVE_FRAME_SAVE_REG_COUNT (12)
130	/** The size of the save registered (IEMNATIVE_FRAME_SAVE_REG_COUNT). */
131	# define IEMNATIVE_FRAME_SAVE_REG_SIZE (IEMNATIVE_FRAME_SAVE_REG_COUNT * 8)
132
133	/** Frame pointer (BP) relative offset of the last push. */
134	# define IEMNATIVE_FP_OFF_LAST_PUSH (10 * -8)
135
136	/** Frame pointer (BP) relative offset of the stack variable area (the lowest
137	* address for it). */
138	# define IEMNATIVE_FP_OFF_STACK_VARS (IEMNATIVE_FP_OFF_LAST_PUSH - IEMNATIVE_FRAME_ALIGN_SIZE - IEMNATIVE_FRAME_VAR_SIZE)
139
140	#else
141	# error "port me"
142	#endif
143	/** @} */
144
145
146	/** @name Fixed Register Allocation(s)
147	* @{ */
148	/** @def IEMNATIVE_REG_FIXED_PVMCPU
149	* The number of the register holding the pVCpu pointer. */
150	/** @def IEMNATIVE_REG_FIXED_PCPUMCTX
151	* The number of the register holding the &pVCpu->cpum.GstCtx pointer.
152	* @note This not available on AMD64, only ARM64. */
153	/** @def IEMNATIVE_REG_FIXED_TMP0
154	* Dedicated temporary register.
155	* @todo replace this by a register allocator and content tracker. */
156	/** @def IEMNATIVE_REG_FIXED_MASK
157	* Mask GPRs with fixes assignments, either by us or dictated by the CPU/OS
158	* architecture. */
159	#if defined(RT_ARCH_AMD64) && !defined(DOXYGEN_RUNNING)
160	# define IEMNATIVE_REG_FIXED_PVMCPU X86_GREG_xBX
161	# define IEMNATIVE_REG_FIXED_TMP0 X86_GREG_x11
162	# define IEMNATIVE_REG_FIXED_MASK ( RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU) \
163	\| RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0) \
164	\| RT_BIT_32(X86_GREG_xSP) \
165	\| RT_BIT_32(X86_GREG_xBP) )
166
167	#elif defined(RT_ARCH_ARM64) \|\| defined(DOXYGEN_RUNNING)
168	# define IEMNATIVE_REG_FIXED_PVMCPU ARMV8_A64_REG_X28
169	# define IEMNATIVE_REG_FIXED_PCPUMCTX ARMV8_A64_REG_X27
170	# define IEMNATIVE_REG_FIXED_TMP0 ARMV8_A64_REG_X15
171	# define IEMNATIVE_REG_FIXED_MASK ( RT_BIT_32(ARMV8_A64_REG_SP) \
172	\| RT_BIT_32(ARMV8_A64_REG_LR) \
173	\| RT_BIT_32(ARMV8_A64_REG_BP) \
174	\| RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU) \
175	\| RT_BIT_32(IEMNATIVE_REG_FIXED_PCPUMCTX) \
176	\| RT_BIT_32(ARMV8_A64_REG_X18) \
177	\| RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0) )
178
179	#else
180	# error "port me"
181	#endif
182	/** @} */
183
184	/** @name Call related registers.
185	* @{ */
186	/** @def IEMNATIVE_CALL_RET_GREG
187	* The return value register. */
188	/** @def IEMNATIVE_CALL_ARG_GREG_COUNT
189	* Number of arguments in registers. */
190	/** @def IEMNATIVE_CALL_ARG0_GREG
191	* The general purpose register carrying argument \#0. */
192	/** @def IEMNATIVE_CALL_ARG1_GREG
193	* The general purpose register carrying argument \#1. */
194	/** @def IEMNATIVE_CALL_ARG2_GREG
195	* The general purpose register carrying argument \#2. */
196	/** @def IEMNATIVE_CALL_ARG3_GREG
197	* The general purpose register carrying argument \#3. */
198	/** @def IEMNATIVE_CALL_VOLATILE_GREG_MASK
199	* Mask of registers the callee will not save and may trash. */
200	#ifdef RT_ARCH_AMD64
201	# define IEMNATIVE_CALL_RET_GREG X86_GREG_xAX
202
203	# ifdef RT_OS_WINDOWS
204	# define IEMNATIVE_CALL_ARG_GREG_COUNT 4
205	# define IEMNATIVE_CALL_ARG0_GREG X86_GREG_xCX
206	# define IEMNATIVE_CALL_ARG1_GREG X86_GREG_xDX
207	# define IEMNATIVE_CALL_ARG2_GREG X86_GREG_x8
208	# define IEMNATIVE_CALL_ARG3_GREG X86_GREG_x9
209	# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \
210	\| RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \
211	\| RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG) \
212	\| RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) )
213	# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(X86_GREG_xAX) \
214	\| RT_BIT_32(X86_GREG_xCX) \
215	\| RT_BIT_32(X86_GREG_xDX) \
216	\| RT_BIT_32(X86_GREG_x8) \
217	\| RT_BIT_32(X86_GREG_x9) \
218	\| RT_BIT_32(X86_GREG_x10) \
219	\| RT_BIT_32(X86_GREG_x11) )
220	# else
221	# define IEMNATIVE_CALL_ARG_GREG_COUNT 6
222	# define IEMNATIVE_CALL_ARG0_GREG X86_GREG_xDI
223	# define IEMNATIVE_CALL_ARG1_GREG X86_GREG_xSI
224	# define IEMNATIVE_CALL_ARG2_GREG X86_GREG_xDX
225	# define IEMNATIVE_CALL_ARG3_GREG X86_GREG_xCX
226	# define IEMNATIVE_CALL_ARG4_GREG X86_GREG_x8
227	# define IEMNATIVE_CALL_ARG5_GREG X86_GREG_x9
228	# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \
229	\| RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \
230	\| RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG) \
231	\| RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) \
232	\| RT_BIT_32(IEMNATIVE_CALL_ARG4_GREG) \
233	\| RT_BIT_32(IEMNATIVE_CALL_ARG5_GREG) )
234	# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(X86_GREG_xAX) \
235	\| RT_BIT_32(X86_GREG_xCX) \
236	\| RT_BIT_32(X86_GREG_xDX) \
237	\| RT_BIT_32(X86_GREG_xDI) \
238	\| RT_BIT_32(X86_GREG_xSI) \
239	\| RT_BIT_32(X86_GREG_x8) \
240	\| RT_BIT_32(X86_GREG_x9) \
241	\| RT_BIT_32(X86_GREG_x10) \
242	\| RT_BIT_32(X86_GREG_x11) )
243	# endif
244
245	#elif defined(RT_ARCH_ARM64)
246	# define IEMNATIVE_CALL_RET_GREG ARMV8_A64_REG_X0
247	# define IEMNATIVE_CALL_ARG_GREG_COUNT 8
248	# define IEMNATIVE_CALL_ARG0_GREG ARMV8_A64_REG_X0
249	# define IEMNATIVE_CALL_ARG1_GREG ARMV8_A64_REG_X1
250	# define IEMNATIVE_CALL_ARG2_GREG ARMV8_A64_REG_X2
251	# define IEMNATIVE_CALL_ARG3_GREG ARMV8_A64_REG_X3
252	# define IEMNATIVE_CALL_ARG4_GREG ARMV8_A64_REG_X4
253	# define IEMNATIVE_CALL_ARG5_GREG ARMV8_A64_REG_X5
254	# define IEMNATIVE_CALL_ARG6_GREG ARMV8_A64_REG_X6
255	# define IEMNATIVE_CALL_ARG7_GREG ARMV8_A64_REG_X7
256	# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(ARMV8_A64_REG_X0) \
257	\| RT_BIT_32(ARMV8_A64_REG_X1) \
258	\| RT_BIT_32(ARMV8_A64_REG_X2) \
259	\| RT_BIT_32(ARMV8_A64_REG_X3) \
260	\| RT_BIT_32(ARMV8_A64_REG_X4) \
261	\| RT_BIT_32(ARMV8_A64_REG_X5) \
262	\| RT_BIT_32(ARMV8_A64_REG_X6) \
263	\| RT_BIT_32(ARMV8_A64_REG_X7) )
264	# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(ARMV8_A64_REG_X0) \
265	\| RT_BIT_32(ARMV8_A64_REG_X1) \
266	\| RT_BIT_32(ARMV8_A64_REG_X2) \
267	\| RT_BIT_32(ARMV8_A64_REG_X3) \
268	\| RT_BIT_32(ARMV8_A64_REG_X4) \
269	\| RT_BIT_32(ARMV8_A64_REG_X5) \
270	\| RT_BIT_32(ARMV8_A64_REG_X6) \
271	\| RT_BIT_32(ARMV8_A64_REG_X7) \
272	\| RT_BIT_32(ARMV8_A64_REG_X8) \
273	\| RT_BIT_32(ARMV8_A64_REG_X9) \
274	\| RT_BIT_32(ARMV8_A64_REG_X10) \
275	\| RT_BIT_32(ARMV8_A64_REG_X11) \
276	\| RT_BIT_32(ARMV8_A64_REG_X12) \
277	\| RT_BIT_32(ARMV8_A64_REG_X13) \
278	\| RT_BIT_32(ARMV8_A64_REG_X14) \
279	\| RT_BIT_32(ARMV8_A64_REG_X15) \
280	\| RT_BIT_32(ARMV8_A64_REG_X16) \
281	\| RT_BIT_32(ARMV8_A64_REG_X17) )
282
283	#endif
284
285	/** This is the maximum argument count we'll ever be needing. */
286	#if defined(RT_OS_WINDOWS) && defined(VBOXSTRICTRC_STRICT_ENABLED)
287	# define IEMNATIVE_CALL_MAX_ARG_COUNT 8
288	#else
289	# define IEMNATIVE_CALL_MAX_ARG_COUNT 7
290	#endif
291	/** @} */
292
293
294	/** @def IEMNATIVE_HST_GREG_COUNT
295	* Number of host general purpose registers we tracker. */
296	/** @def IEMNATIVE_HST_GREG_MASK
297	* Mask corresponding to IEMNATIVE_HST_GREG_COUNT that can be applied to
298	* inverted register masks and such to get down to a correct set of regs. */
299	#ifdef RT_ARCH_AMD64
300	# define IEMNATIVE_HST_GREG_COUNT 16
301	# define IEMNATIVE_HST_GREG_MASK UINT32_C(0xffff)
302
303	#elif defined(RT_ARCH_ARM64)
304	# define IEMNATIVE_HST_GREG_COUNT 32
305	# define IEMNATIVE_HST_GREG_MASK UINT32_MAX
306	#else
307	# error "Port me!"
308	#endif
309
310
311	/** Native code generator label types. */
312	typedef enum
313	{
314	kIemNativeLabelType_Invalid = 0,
315	/* Labels w/o data, only once instance per TB: */
316	kIemNativeLabelType_Return,
317	kIemNativeLabelType_ReturnBreak,
318	kIemNativeLabelType_ReturnWithFlags,
319	kIemNativeLabelType_NonZeroRetOrPassUp,
320	kIemNativeLabelType_RaiseGp0,
321	kIemNativeLabelType_RaiseNm,
322	kIemNativeLabelType_ObsoleteTb,
323	kIemNativeLabelType_NeedCsLimChecking,
324	kIemNativeLabelType_CheckBranchMiss,
325	/* Labels with data, potentially multiple instances per TB: */
326	kIemNativeLabelType_FirstWithMultipleInstances,
327	kIemNativeLabelType_If = kIemNativeLabelType_FirstWithMultipleInstances,
328	kIemNativeLabelType_Else,
329	kIemNativeLabelType_Endif,
330	kIemNativeLabelType_CheckIrq,
331	kIemNativeLabelType_TlbLookup,
332	kIemNativeLabelType_TlbMiss,
333	kIemNativeLabelType_TlbDone,
334	kIemNativeLabelType_End
335	} IEMNATIVELABELTYPE;
336
337	/** Native code generator label definition. */
338	typedef struct IEMNATIVELABEL
339	{
340	/** Code offset if defined, UINT32_MAX if it needs to be generated after/in
341	* the epilog. */
342	uint32_t off;
343	/** The type of label (IEMNATIVELABELTYPE). */
344	uint16_t enmType;
345	/** Additional label data, type specific. */
346	uint16_t uData;
347	} IEMNATIVELABEL;
348	/** Pointer to a label. */
349	typedef IEMNATIVELABEL *PIEMNATIVELABEL;
350
351
352	/** Native code generator fixup types. */
353	typedef enum
354	{
355	kIemNativeFixupType_Invalid = 0,
356	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
357	/** AMD64 fixup: PC relative 32-bit with addend in bData. */
358	kIemNativeFixupType_Rel32,
359	#elif defined(RT_ARCH_ARM64)
360	/** ARM64 fixup: PC relative offset at bits 25:0 (B, BL). */
361	kIemNativeFixupType_RelImm26At0,
362	/** ARM64 fixup: PC relative offset at bits 23:5 (CBZ, CBNZ, B.CC). */
363	kIemNativeFixupType_RelImm19At5,
364	/** ARM64 fixup: PC relative offset at bits 18:5 (TBZ, TBNZ). */
365	kIemNativeFixupType_RelImm14At5,
366	#endif
367	kIemNativeFixupType_End
368	} IEMNATIVEFIXUPTYPE;
369
370	/** Native code generator fixup. */
371	typedef struct IEMNATIVEFIXUP
372	{
373	/** Code offset of the fixup location. */
374	uint32_t off;
375	/** The IEMNATIVELABEL this is a fixup for. */
376	uint16_t idxLabel;
377	/** The fixup type (IEMNATIVEFIXUPTYPE). */
378	uint8_t enmType;
379	/** Addend or other data. */
380	int8_t offAddend;
381	} IEMNATIVEFIXUP;
382	/** Pointer to a native code generator fixup. */
383	typedef IEMNATIVEFIXUP *PIEMNATIVEFIXUP;
384
385
386	/**
387	* One bit of the state.
388	*
389	* Each register state takes up two bits. We keep the two bits in two separate
390	* 64-bit words to simplify applying them to the guest shadow register mask in
391	* the register allocator.
392	*/
393	typedef union IEMLIVENESSBIT
394	{
395	uint64_t bm64;
396	RT_GCC_EXTENSION struct
397	{ /* bit no */
398	uint64_t bmGprs : 16; /*< 0x00 / 0: The 16 general purpose registers. /
399	uint64_t fUnusedPc : 1; /*< 0x10 / 16: (PC in ) /
400	uint64_t uPadding1 : 3; /*< 0x11 / 17: /
401	uint64_t bmSegBase : 6; /*< 0x14 / 20: /
402	uint64_t bmSegAttrib : 6; /*< 0x1a / 26: /
403	uint64_t bmSegLimit : 6; /*< 0x20 / 32: /
404	uint64_t bmSegSel : 6; /*< 0x26 / 38: /
405	uint64_t fEflOther : 1; /*< 0x2c / 44: Other EFLAGS bits (~X86_EFL_STATUS_BITS & X86_EFL_LIVE_MASK). First! /
406	uint64_t fEflCf : 1; /*< 0x2d / 45: Carry flag (X86_EFL_CF / 0). /
407	uint64_t fEflPf : 1; /*< 0x2e / 46: Parity flag (X86_EFL_PF / 2). /
408	uint64_t fEflAf : 1; /*< 0x2f / 47: Auxilary carry flag (X86_EFL_AF / 4). /
409	uint64_t fEflZf : 1; /*< 0x30 / 48: Zero flag (X86_EFL_ZF / 6). /
410	uint64_t fEflSf : 1; /*< 0x31 / 49: Signed flag (X86_EFL_SF / 7). /
411	uint64_t fEflOf : 1; /*< 0x32 / 50: Overflow flag (X86_EFL_OF / 12). /
412	uint64_t uUnused : 13; /* 0x33 / 51 -> 0x40/64 */
413	};
414	} IEMLIVENESSBIT;
415	AssertCompileSize(IEMLIVENESSBIT, 8);
416
417	#define IEMLIVENESSBIT_IDX_EFL_OTHER ((unsigned)kIemNativeGstReg_EFlags + 0)
418	#define IEMLIVENESSBIT_IDX_EFL_CF ((unsigned)kIemNativeGstReg_EFlags + 1)
419	#define IEMLIVENESSBIT_IDX_EFL_PF ((unsigned)kIemNativeGstReg_EFlags + 2)
420	#define IEMLIVENESSBIT_IDX_EFL_AF ((unsigned)kIemNativeGstReg_EFlags + 3)
421	#define IEMLIVENESSBIT_IDX_EFL_ZF ((unsigned)kIemNativeGstReg_EFlags + 4)
422	#define IEMLIVENESSBIT_IDX_EFL_SF ((unsigned)kIemNativeGstReg_EFlags + 5)
423	#define IEMLIVENESSBIT_IDX_EFL_OF ((unsigned)kIemNativeGstReg_EFlags + 6)
424
425
426	/**
427	* A liveness state entry.
428	*
429	* The first 128 bits runs parallel to kIemNativeGstReg_xxx for the most part.
430	* Once we add a SSE register shadowing, we'll add another 64-bit element for
431	* that.
432	*/
433	typedef union IEMLIVENESSENTRY
434	{
435	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
436	uint64_t bm64[16 / 8];
437	uint16_t bm32[16 / 4];
438	uint16_t bm16[16 / 2];
439	uint8_t bm8[ 16 / 1];
440	IEMLIVENESSBIT aBits[2];
441	#else
442	uint64_t bm64[32 / 8];
443	uint16_t bm32[32 / 4];
444	uint16_t bm16[32 / 2];
445	uint8_t bm8[ 32 / 1];
446	IEMLIVENESSBIT aBits[4];
447	#endif
448	RT_GCC_EXTENSION struct
449	{
450	/** Bit \#0 of the register states. */
451	IEMLIVENESSBIT Bit0;
452	/** Bit \#1 of the register states. */
453	IEMLIVENESSBIT Bit1;
454	#ifdef IEMLIVENESS_EXTENDED_LAYOUT
455	/** Bit \#2 of the register states. */
456	IEMLIVENESSBIT Bit2;
457	/** Bit \#3 of the register states. */
458	IEMLIVENESSBIT Bit3;
459	#endif
460	};
461	} IEMLIVENESSENTRY;
462	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
463	AssertCompileSize(IEMLIVENESSENTRY, 16);
464	#else
465	AssertCompileSize(IEMLIVENESSENTRY, 32);
466	#endif
467	/** Pointer to a liveness state entry. */
468	typedef IEMLIVENESSENTRY *PIEMLIVENESSENTRY;
469	/** Pointer to a const liveness state entry. */
470	typedef IEMLIVENESSENTRY const *PCIEMLIVENESSENTRY;
471
472	/** @name 64-bit value masks for IEMLIVENESSENTRY.
473	* @{ / / 0xzzzzyyyyxxxxwwww */
474	#define IEMLIVENESSBIT_MASK UINT64_C(0x0007fffffff0ffff)
475
476	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
477	# define IEMLIVENESSBIT0_XCPT_OR_CALL UINT64_C(0x0000000000000000)
478	# define IEMLIVENESSBIT1_XCPT_OR_CALL IEMLIVENESSBIT_MASK
479
480	# define IEMLIVENESSBIT0_ALL_UNUSED IEMLIVENESSBIT_MASK
481	# define IEMLIVENESSBIT1_ALL_UNUSED UINT64_C(0x0000000000000000)
482	#endif
483
484	#define IEMLIVENESSBIT_ALL_EFL_MASK UINT64_C(0x0007f00000000000)
485
486	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
487	# define IEMLIVENESSBIT0_ALL_EFL_INPUT IEMLIVENESSBIT_ALL_EFL_MASK
488	# define IEMLIVENESSBIT1_ALL_EFL_INPUT IEMLIVENESSBIT_ALL_EFL_MASK
489	#endif
490	/** @} */
491
492
493	/** @name The liveness state for a register.
494	*
495	* The state values have been picked to with state accumulation in mind (what
496	* the iemNativeLivenessFunc_xxxx functions does), as that is the most
497	* performance critical work done with the values.
498	*
499	* This is a compressed state that only requires 2 bits per register.
500	* When accumulating state, we'll be using three IEMLIVENESSENTRY copies:
501	* 1. the incoming state from the following call,
502	* 2. the outgoing state for this call,
503	* 3. mask of the entries set in the 2nd.
504	*
505	* The mask entry (3rd one above) will be used both when updating the outgoing
506	* state and when merging in incoming state for registers not touched by the
507	* current call.
508	*
509	* @{ */
510	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
511	/** The register will be clobbered and the current value thrown away.
512	*
513	* When this is applied to the state (2) we'll simply be AND'ing it with the
514	* (old) mask (3) and adding the register to the mask. This way we'll
515	* preserve the high priority IEMLIVENESS_STATE_XCPT_OR_CALL and
516	* IEMLIVENESS_STATE_INPUT states. */
517	# define IEMLIVENESS_STATE_CLOBBERED 0
518	/** The register is unused in the remainder of the TB.
519	*
520	* This is an initial state and can not be set by any of the
521	* iemNativeLivenessFunc_xxxx callbacks. */
522	# define IEMLIVENESS_STATE_UNUSED 1
523	/** The register value is required in a potential call or exception.
524	*
525	* This means that the register value must be calculated and is best written to
526	* the state, but that any shadowing registers can be flushed thereafter as it's
527	* not used again. This state has lower priority than IEMLIVENESS_STATE_INPUT.
528	*
529	* It is typically applied across the board, but we preserve incoming
530	* IEMLIVENESS_STATE_INPUT values. This latter means we have to do some extra
531	* trickery to filter out IEMLIVENESS_STATE_UNUSED:
532	* 1. r0 = old & ~mask;
533	* 2. r0 = t1 & (t1 >> 1)'
534	* 3. state \|= r0 \| 0b10;
535	* 4. mask = ~0;
536	*/
537	# define IEMLIVENESS_STATE_XCPT_OR_CALL 2
538	/** The register value is used as input.
539	*
540	* This means that the register value must be calculated and it is best to keep
541	* it in a register. It does not need to be writtent out as such. This is the
542	* highest priority state.
543	*
544	* Whether the call modifies the register or not isn't relevant to earlier
545	* calls, so that's not recorded.
546	*
547	* When applying this state we just or in the value in the outgoing state and
548	* mask. */
549	# define IEMLIVENESS_STATE_INPUT 3
550	/** Mask of the state bits. */
551	# define IEMLIVENESS_STATE_MASK 3
552	/** The number of bits per state. */
553	# define IEMLIVENESS_STATE_BIT_COUNT 2
554	/** Check if we're expecting read & write accesses to a register with the given (previous) liveness state. */
555	# define IEMLIVENESS_STATE_IS_MODIFY_EXPECTED(a_uState) ((uint32_t)((a_uState) - 1U) >= (uint32_t)(IEMLIVENESS_STATE_INPUT - 1U))
556	/** Check if we're expecting read accesses to a register with the given (previous) liveness state. */
557	# define IEMLIVENESS_STATE_IS_INPUT_EXPECTED(a_uState) IEMLIVENESS_STATE_IS_MODIFY_EXPECTED(a_uState)
558	/** Check if a register clobbering is expected given the (previous) liveness state.
559	* The state must be either CLOBBERED or XCPT_OR_CALL, but it may also
560	* include INPUT if the register is used in more than one place. */
561	# define IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(a_uState) ((uint32_t)(a_uState) != IEMLIVENESS_STATE_UNUSED)
562
563	#else /* IEMLIVENESS_EXTENDED_LAYOUT */
564	/** The register is not used any more. */
565	# define IEMLIVENESS_STATE_UNUSED 0
566	/** Flag: The register is required in a potential exception or call. */
567	# define IEMLIVENESS_STATE_POT_XCPT_OR_CALL 1
568	# define IEMLIVENESS_BIT_POT_XCPT_OR_CALL 0
569	/** Flag: The register is read. */
570	# define IEMLIVENESS_STATE_READ 2
571	# define IEMLIVENESS_BIT_READ 1
572	/** Flag: The register is written. */
573	# define IEMLIVENESS_STATE_WRITE 4
574	# define IEMLIVENESS_BIT_WRITE 2
575	/** Flag: Unconditional call (not needed, can be redefined for research). */
576	# define IEMLIVENESS_STATE_CALL 8
577	# define IEMLIVENESS_BIT_CALL 3
578	# define IEMLIVENESS_BIT_OTHER 3 /*< More convenient name for this one. /
579	# define IEMLIVENESS_STATE_IS_MODIFY_EXPECTED(a_uState) \
580	( ((a_uState) & (IEMLIVENESS_STATE_WRITE \| IEMLIVENESS_STATE_READ)) == (IEMLIVENESS_STATE_WRITE \| IEMLIVENESS_STATE_READ) )
581	# define IEMLIVENESS_STATE_IS_INPUT_EXPECTED(a_uState) RT_BOOL((a_uState) & IEMLIVENESS_STATE_READ)
582	# define IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(a_uState) RT_BOOL((a_uState) & IEMLIVENESS_STATE_WRITE)
583	#endif /* IEMLIVENESS_EXTENDED_LAYOUT */
584	/** @} */
585
586	/** @name Liveness helpers for builtin functions and similar.
587	*
588	* These are not used by IEM_MC_BEGIN/END blocks, IEMAllN8veLiveness.cpp has its
589	* own set of manimulator macros for those.
590	*
591	* @{ */
592	/** Initializing the state as all unused. */
593	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
594	# define IEM_LIVENESS_RAW_INIT_AS_UNUSED(a_pOutgoing) \
595	do { \
596	(a_pOutgoing)->Bit0.bm64 = IEMLIVENESSBIT0_ALL_UNUSED; \
597	(a_pOutgoing)->Bit1.bm64 = IEMLIVENESSBIT1_ALL_UNUSED; \
598	} while (0)
599	#else
600	# define IEM_LIVENESS_RAW_INIT_AS_UNUSED(a_pOutgoing) \
601	do { \
602	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64 = 0; \
603	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ ].bm64 = 0; \
604	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_WRITE ].bm64 = 0; \
605	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_OTHER ].bm64 = 0; \
606	} while (0)
607	#endif
608
609	/** Initializing the outgoing state with a potential xcpt or call state.
610	* This only works when all later changes will be IEMLIVENESS_STATE_INPUT. */
611	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
612	# define IEM_LIVENESS_RAW_INIT_WITH_XCPT_OR_CALL(a_pOutgoing, a_pIncoming) \
613	do { \
614	(a_pOutgoing)->Bit0.bm64 = (a_pIncoming)->Bit0.bm64 & (a_pIncoming)->Bit1.bm64; \
615	(a_pOutgoing)->Bit1.bm64 = IEMLIVENESSBIT1_XCPT_OR_CALL; \
616	} while (0)
617	#else
618	# define IEM_LIVENESS_RAW_INIT_WITH_XCPT_OR_CALL(a_pOutgoing, a_pIncoming) \
619	do { \
620	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64 = IEMLIVENESSBIT_MASK; \
621	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ ].bm64 = (a_pIncoming)->aBits[IEMLIVENESS_BIT_READ].bm64; \
622	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_WRITE ].bm64 = 0; \
623	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_OTHER ].bm64 = 0; \
624	} while (0)
625	#endif
626
627	/** Adds a segment base register as input to the outgoing state. */
628	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
629	# define IEM_LIVENESS_RAW_SEG_BASE_INPUT(a_pOutgoing, a_iSReg) do { \
630	(a_pOutgoing)->Bit0.bmSegBase \|= RT_BIT_64(a_iSReg); \
631	(a_pOutgoing)->Bit1.bmSegBase \|= RT_BIT_64(a_iSReg); \
632	} while (0)
633	#else
634	# define IEM_LIVENESS_RAW_SEG_BASE_INPUT(a_pOutgoing, a_iSReg) do { \
635	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].bmSegBase \|= RT_BIT_64(a_iSReg); \
636	} while (0)
637	#endif
638
639	/** Adds a segment attribute register as input to the outgoing state. */
640	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
641	# define IEM_LIVENESS_RAW_SEG_ATTRIB_INPUT(a_pOutgoing, a_iSReg) do { \
642	(a_pOutgoing)->Bit0.bmSegAttrib \|= RT_BIT_64(a_iSReg); \
643	(a_pOutgoing)->Bit1.bmSegAttrib \|= RT_BIT_64(a_iSReg); \
644	} while (0)
645	#else
646	# define IEM_LIVENESS_RAW_SEG_ATTRIB_INPUT(a_pOutgoing, a_iSReg) do { \
647	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].bmSegAttrib \|= RT_BIT_64(a_iSReg); \
648	} while (0)
649	#endif
650
651	/** Adds a segment limit register as input to the outgoing state. */
652	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
653	# define IEM_LIVENESS_RAW_SEG_LIMIT_INPUT(a_pOutgoing, a_iSReg) do { \
654	(a_pOutgoing)->Bit0.bmSegLimit \|= RT_BIT_64(a_iSReg); \
655	(a_pOutgoing)->Bit1.bmSegLimit \|= RT_BIT_64(a_iSReg); \
656	} while (0)
657	#else
658	# define IEM_LIVENESS_RAW_SEG_LIMIT_INPUT(a_pOutgoing, a_iSReg) do { \
659	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].bmSegLimit \|= RT_BIT_64(a_iSReg); \
660	} while (0)
661	#endif
662
663	/** Adds a segment limit register as input to the outgoing state. */
664	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
665	# define IEM_LIVENESS_RAW_EFLAGS_ONE_INPUT(a_pOutgoing, a_fEflMember) do { \
666	(a_pOutgoing)->Bit0.a_fEflMember \|= 1; \
667	(a_pOutgoing)->Bit1.a_fEflMember \|= 1; \
668	} while (0)
669	#else
670	# define IEM_LIVENESS_RAW_EFLAGS_ONE_INPUT(a_pOutgoing, a_fEflMember) do { \
671	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].a_fEflMember \|= 1; \
672	} while (0)
673	#endif
674	/** @} */
675
676	/**
677	* Guest registers that can be shadowed in GPRs.
678	*
679	* This runs parallel to the first 128-bits of liveness state. To avoid having
680	* the SegLimitXxxx range cross from the 1st 64-bit word to the 2nd,
681	* we've inserted some padding. The EFlags must be placed last, as the liveness
682	* state tracks it as 7 subcomponents and we don't want to waste space here.
683	*/
684	typedef enum IEMNATIVEGSTREG : uint8_t
685	{
686	kIemNativeGstReg_GprFirst = 0,
687	kIemNativeGstReg_GprLast = kIemNativeGstReg_GprFirst + 15,
688	kIemNativeGstReg_Pc,
689	kIemNativeGstReg_Cr0,
690	kIemNativeGstReg_FpuFcw,
691	kIemNativeGstReg_LivenessPadding19,
692	kIemNativeGstReg_SegBaseFirst,
693	kIemNativeGstReg_SegBaseLast = kIemNativeGstReg_SegBaseFirst + 5,
694	kIemNativeGstReg_SegAttribFirst,
695	kIemNativeGstReg_SegAttribLast = kIemNativeGstReg_SegAttribFirst + 5,
696	kIemNativeGstReg_SegLimitFirst,
697	kIemNativeGstReg_SegLimitLast = kIemNativeGstReg_SegLimitFirst + 5,
698	kIemNativeGstReg_SegSelFirst,
699	kIemNativeGstReg_SegSelLast = kIemNativeGstReg_SegSelFirst + 5,
700	kIemNativeGstReg_EFlags, /*< 32-bit, includes internal flags - last! /
701	kIemNativeGstReg_End
702	} IEMNATIVEGSTREG;
703	AssertCompile((int)kIemNativeGstReg_SegLimitFirst == 32);
704
705	/** @name Helpers for converting register numbers to IEMNATIVEGSTREG values.
706	* @{ */
707	#define IEMNATIVEGSTREG_GPR(a_iGpr) ((IEMNATIVEGSTREG)(kIemNativeGstReg_GprFirst + (a_iGpr) ))
708	#define IEMNATIVEGSTREG_SEG_SEL(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegSelFirst + (a_iSegReg) ))
709	#define IEMNATIVEGSTREG_SEG_BASE(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegBaseFirst + (a_iSegReg) ))
710	#define IEMNATIVEGSTREG_SEG_LIMIT(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegLimitFirst + (a_iSegReg) ))
711	#define IEMNATIVEGSTREG_SEG_ATTRIB(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegAttribFirst + (a_iSegReg) ))
712	/** @} */
713
714	/**
715	* Intended use statement for iemNativeRegAllocTmpForGuestReg().
716	*/
717	typedef enum IEMNATIVEGSTREGUSE
718	{
719	/** The usage is read-only, the register holding the guest register
720	* shadow copy will not be modified by the caller. */
721	kIemNativeGstRegUse_ReadOnly = 0,
722	/** The caller will update the guest register (think: PC += cbInstr).
723	* The guest shadow copy will follow the returned register. */
724	kIemNativeGstRegUse_ForUpdate,
725	/** The call will put an entirely new value in the guest register, so
726	* if new register is allocate it will be returned uninitialized. */
727	kIemNativeGstRegUse_ForFullWrite,
728	/** The caller will use the guest register value as input in a calculation
729	* and the host register will be modified.
730	* This means that the returned host register will not be marked as a shadow
731	* copy of the guest register. */
732	kIemNativeGstRegUse_Calculation
733	} IEMNATIVEGSTREGUSE;
734
735	/**
736	* Guest registers (classes) that can be referenced.
737	*/
738	typedef enum IEMNATIVEGSTREGREF : uint8_t
739	{
740	kIemNativeGstRegRef_Invalid = 0,
741	kIemNativeGstRegRef_Gpr,
742	kIemNativeGstRegRef_GprHighByte, /*< AH, CH, DH, BH/
743	kIemNativeGstRegRef_EFlags,
744	kIemNativeGstRegRef_MxCsr,
745	kIemNativeGstRegRef_FpuReg,
746	kIemNativeGstRegRef_MReg,
747	kIemNativeGstRegRef_XReg,
748	//kIemNativeGstRegRef_YReg, - doesn't work.
749	kIemNativeGstRegRef_End
750	} IEMNATIVEGSTREGREF;
751
752
753	/** Variable kinds. */
754	typedef enum IEMNATIVEVARKIND : uint8_t
755	{
756	/** Customary invalid zero value. */
757	kIemNativeVarKind_Invalid = 0,
758	/** This is either in a register or on the stack. */
759	kIemNativeVarKind_Stack,
760	/** Immediate value - loaded into register when needed, or can live on the
761	* stack if referenced (in theory). */
762	kIemNativeVarKind_Immediate,
763	/** Variable reference - loaded into register when needed, never stack. */
764	kIemNativeVarKind_VarRef,
765	/** Guest register reference - loaded into register when needed, never stack. */
766	kIemNativeVarKind_GstRegRef,
767	/** End of valid values. */
768	kIemNativeVarKind_End
769	} IEMNATIVEVARKIND;
770
771
772	/** Variable or argument. */
773	typedef struct IEMNATIVEVAR
774	{
775	/** The kind of variable. */
776	IEMNATIVEVARKIND enmKind;
777	/** The variable size in bytes. */
778	uint8_t cbVar;
779	/** The first stack slot (uint64_t), except for immediate and references
780	* where it usually is UINT8_MAX. This is allocated lazily, so if a variable
781	* has a stack slot it has been initialized and has a value. Unused variables
782	* has neither a stack slot nor a host register assignment. */
783	uint8_t idxStackSlot;
784	/** The host register allocated for the variable, UINT8_MAX if not. */
785	uint8_t idxReg;
786	/** The argument number if argument, UINT8_MAX if regular variable. */
787	uint8_t uArgNo;
788	/** If referenced, the index of the variable referencing this one, otherwise
789	* UINT8_MAX. A referenced variable must only be placed on the stack and
790	* must be either kIemNativeVarKind_Stack or kIemNativeVarKind_Immediate. */
791	uint8_t idxReferrerVar;
792	/** Guest register being shadowed here, kIemNativeGstReg_End(/UINT8_MAX) if not.
793	* @todo not sure what this really is for... */
794	IEMNATIVEGSTREG enmGstReg;
795	/** Set if the registered is currently used exclusively, false if the
796	* variable is idle and the register can be grabbed. */
797	bool fRegAcquired;
798
799	union
800	{
801	/** kIemNativeVarKind_Immediate: The immediate value. */
802	uint64_t uValue;
803	/** kIemNativeVarKind_VarRef: The index of the variable being referenced. */
804	uint8_t idxRefVar;
805	/** kIemNativeVarKind_GstRegRef: The guest register being referrenced. */
806	struct
807	{
808	/** The class of register. */
809	IEMNATIVEGSTREGREF enmClass;
810	/** Index within the class. */
811	uint8_t idx;
812	} GstRegRef;
813	} u;
814	} IEMNATIVEVAR;
815
816	/** What is being kept in a host register. */
817	typedef enum IEMNATIVEWHAT : uint8_t
818	{
819	/** The traditional invalid zero value. */
820	kIemNativeWhat_Invalid = 0,
821	/** Mapping a variable (IEMNATIVEHSTREG::idxVar). */
822	kIemNativeWhat_Var,
823	/** Temporary register, this is typically freed when a MC completes. */
824	kIemNativeWhat_Tmp,
825	/** Call argument w/o a variable mapping. This is free (via
826	* IEMNATIVE_CALL_VOLATILE_GREG_MASK) after the call is emitted. */
827	kIemNativeWhat_Arg,
828	/** Return status code.
829	* @todo not sure if we need this... */
830	kIemNativeWhat_rc,
831	/** The fixed pVCpu (PVMCPUCC) register.
832	* @todo consider offsetting this on amd64 to use negative offsets to access
833	* more members using 8-byte disp. */
834	kIemNativeWhat_pVCpuFixed,
835	/** The fixed pCtx (PCPUMCTX) register.
836	* @todo consider offsetting this on amd64 to use negative offsets to access
837	* more members using 8-byte disp. */
838	kIemNativeWhat_pCtxFixed,
839	/** Fixed temporary register. */
840	kIemNativeWhat_FixedTmp,
841	/** Register reserved by the CPU or OS architecture. */
842	kIemNativeWhat_FixedReserved,
843	/** End of valid values. */
844	kIemNativeWhat_End
845	} IEMNATIVEWHAT;
846
847	/**
848	* Host general register entry.
849	*
850	* The actual allocation status is kept in IEMRECOMPILERSTATE::bmHstRegs.
851	*
852	* @todo Track immediate values in host registers similarlly to how we track the
853	* guest register shadow copies. For it to be real helpful, though,
854	* we probably need to know which will be reused and put them into
855	* non-volatile registers, otherwise it's going to be more or less
856	* restricted to an instruction or two.
857	*/
858	typedef struct IEMNATIVEHSTREG
859	{
860	/** Set of guest registers this one shadows.
861	*
862	* Using a bitmap here so we can designate the same host register as a copy
863	* for more than one guest register. This is expected to be useful in
864	* situations where one value is copied to several registers in a sequence.
865	* If the mapping is 1:1, then we'd have to pick which side of a 'MOV SRC,DST'
866	* sequence we'd want to let this register follow to be a copy of and there
867	* will always be places where we'd be picking the wrong one.
868	*/
869	uint64_t fGstRegShadows;
870	/** What is being kept in this register. */
871	IEMNATIVEWHAT enmWhat;
872	/** Variable index if holding a variable, otherwise UINT8_MAX. */
873	uint8_t idxVar;
874	/** Stack slot assigned by iemNativeVarSaveVolatileRegsPreHlpCall and freed
875	* by iemNativeVarRestoreVolatileRegsPostHlpCall. This is not valid outside
876	* that scope. */
877	uint8_t idxStackSlot;
878	/** Alignment padding. */
879	uint8_t abAlign[5];
880	} IEMNATIVEHSTREG;
881
882
883	/**
884	* Core state for the native recompiler, that is, things that needs careful
885	* handling when dealing with branches.
886	*/
887	typedef struct IEMNATIVECORESTATE
888	{
889	/** Allocation bitmap for aHstRegs. */
890	uint32_t bmHstRegs;
891
892	/** Bitmap marking which host register contains guest register shadow copies.
893	* This is used during register allocation to try preserve copies. */
894	uint32_t bmHstRegsWithGstShadow;
895	/** Bitmap marking valid entries in aidxGstRegShadows. */
896	uint64_t bmGstRegShadows;
897
898	union
899	{
900	/** Index of variable arguments, UINT8_MAX if not valid. */
901	uint8_t aidxArgVars[8];
902	/** For more efficient resetting. */
903	uint64_t u64ArgVars;
904	};
905
906	/** Allocation bitmap for the stack. */
907	uint32_t bmStack;
908	/** Allocation bitmap for aVars. */
909	uint32_t bmVars;
910
911	/** Maps a guest register to a host GPR (index by IEMNATIVEGSTREG).
912	* Entries are only valid if the corresponding bit in bmGstRegShadows is set.
913	* (A shadow copy of a guest register can only be held in a one host register,
914	* there are no duplicate copies or ambiguities like that). */
915	uint8_t aidxGstRegShadows[kIemNativeGstReg_End];
916
917	/** Host register allocation tracking. */
918	IEMNATIVEHSTREG aHstRegs[IEMNATIVE_HST_GREG_COUNT];
919
920	/** Variables and arguments. */
921	IEMNATIVEVAR aVars[9];
922	} IEMNATIVECORESTATE;
923	/** Pointer to core state. */
924	typedef IEMNATIVECORESTATE *PIEMNATIVECORESTATE;
925	/** Pointer to const core state. */
926	typedef IEMNATIVECORESTATE const *PCIEMNATIVECORESTATE;
927
928
929	/**
930	* Conditional stack entry.
931	*/
932	typedef struct IEMNATIVECOND
933	{
934	/** Set if we're in the "else" part, clear if we're in the "if" before it. */
935	bool fInElse;
936	/** The label for the IEM_MC_ELSE. */
937	uint32_t idxLabelElse;
938	/** The label for the IEM_MC_ENDIF. */
939	uint32_t idxLabelEndIf;
940	/** The initial state snapshot as the if-block starts executing. */
941	IEMNATIVECORESTATE InitialState;
942	/** The state snapshot at the end of the if-block. */
943	IEMNATIVECORESTATE IfFinalState;
944	} IEMNATIVECOND;
945	/** Pointer to a condition stack entry. */
946	typedef IEMNATIVECOND *PIEMNATIVECOND;
947
948
949	/**
950	* Native recompiler state.
951	*/
952	typedef struct IEMRECOMPILERSTATE
953	{
954	/** Size of the buffer that pbNativeRecompileBufR3 points to in
955	* IEMNATIVEINSTR units. */
956	uint32_t cInstrBufAlloc;
957	#ifdef VBOX_STRICT
958	/** Strict: How far the last iemNativeInstrBufEnsure() checked. */
959	uint32_t offInstrBufChecked;
960	#else
961	uint32_t uPadding1; /* We don't keep track of the size here... */
962	#endif
963	/** Fixed temporary code buffer for native recompilation. */
964	PIEMNATIVEINSTR pInstrBuf;
965
966	/** Bitmaps with the label types used. */
967	uint64_t bmLabelTypes;
968	/** Actual number of labels in paLabels. */
969	uint32_t cLabels;
970	/** Max number of entries allowed in paLabels before reallocating it. */
971	uint32_t cLabelsAlloc;
972	/** Labels defined while recompiling (referenced by fixups). */
973	PIEMNATIVELABEL paLabels;
974	/** Array with indexes of unique labels (uData always 0). */
975	uint32_t aidxUniqueLabels[kIemNativeLabelType_FirstWithMultipleInstances];
976
977	/** Actual number of fixups paFixups. */
978	uint32_t cFixups;
979	/** Max number of entries allowed in paFixups before reallocating it. */
980	uint32_t cFixupsAlloc;
981	/** Buffer used by the recompiler for recording fixups when generating code. */
982	PIEMNATIVEFIXUP paFixups;
983
984	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
985	/** Number of debug info entries allocated for pDbgInfo. */
986	uint32_t cDbgInfoAlloc;
987	uint32_t uPadding;
988	/** Debug info. */
989	PIEMTBDBG pDbgInfo;
990	#endif
991
992	#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
993	/** The current call index (liveness array and threaded calls in TB). */
994	uint32_t idxCurCall;
995	/** Number of liveness entries allocated. */
996	uint32_t cLivenessEntriesAlloc;
997	/** Liveness entries for all the calls in the TB begin recompiled.
998	* The entry for idxCurCall contains the info for what the next call will
999	* require wrt registers. (Which means the last entry is the initial liveness
1000	* state.) */
1001	PIEMLIVENESSENTRY paLivenessEntries;
1002	#endif
1003
1004	/** The translation block being recompiled. */
1005	PCIEMTB pTbOrg;
1006	/** The VMCPU structure of the EMT. */
1007	PVMCPUCC pVCpu;
1008
1009	/** Condition sequence number (for generating unique labels). */
1010	uint16_t uCondSeqNo;
1011	/** Check IRQ seqeunce number (for generating unique labels). */
1012	uint16_t uCheckIrqSeqNo;
1013	/** TLB load sequence number (for generating unique labels). */
1014	uint16_t uTlbSeqNo;
1015	/** The current condition stack depth (aCondStack). */
1016	uint8_t cCondDepth;
1017
1018	/** The argument count + hidden regs from the IEM_MC_BEGIN statement. */
1019	uint8_t cArgs;
1020	/** The IEM_CIMPL_F_XXX flags from the IEM_MC_BEGIN statement. */
1021	uint32_t fCImpl;
1022	/** The IEM_MC_F_XXX flags from the IEM_MC_BEGIN statement. */
1023	uint32_t fMc;
1024	/** The expected IEMCPU::fExec value for the current call/instruction. */
1025	uint32_t fExec;
1026
1027	/** Core state requiring care with branches. */
1028	IEMNATIVECORESTATE Core;
1029
1030	/** The condition nesting stack. */
1031	IEMNATIVECOND aCondStack[2];
1032
1033	#ifndef IEM_WITH_THROW_CATCH
1034	/** Pointer to the setjmp/longjmp buffer if we're not using C++ exceptions
1035	* for recompilation error handling. */
1036	jmp_buf JmpBuf;
1037	#endif
1038	} IEMRECOMPILERSTATE;
1039	/** Pointer to a native recompiler state. */
1040	typedef IEMRECOMPILERSTATE *PIEMRECOMPILERSTATE;
1041
1042
1043	/** @def IEMNATIVE_TRY_SETJMP
1044	* Wrapper around setjmp / try, hiding all the ugly differences.
1045	*
1046	* @note Use with extreme care as this is a fragile macro.
1047	* @param a_pReNative The native recompile state.
1048	* @param a_rcTarget The variable that should receive the status code in case
1049	* of a longjmp/throw.
1050	*/
1051	/** @def IEMNATIVE_CATCH_LONGJMP_BEGIN
1052	* Start wrapper for catch / setjmp-else.
1053	*
1054	* This will set up a scope.
1055	*
1056	* @note Use with extreme care as this is a fragile macro.
1057	* @param a_pReNative The native recompile state.
1058	* @param a_rcTarget The variable that should receive the status code in case
1059	* of a longjmp/throw.
1060	*/
1061	/** @def IEMNATIVE_CATCH_LONGJMP_END
1062	* End wrapper for catch / setjmp-else.
1063	*
1064	* This will close the scope set up by IEMNATIVE_CATCH_LONGJMP_BEGIN and clean
1065	* up the state.
1066	*
1067	* @note Use with extreme care as this is a fragile macro.
1068	* @param a_pReNative The native recompile state.
1069	*/
1070	/** @def IEMNATIVE_DO_LONGJMP
1071	*
1072	* Wrapper around longjmp / throw.
1073	*
1074	* @param a_pReNative The native recompile state.
1075	* @param a_rc The status code jump back with / throw.
1076	*/
1077	#ifdef IEM_WITH_THROW_CATCH
1078	# define IEMNATIVE_TRY_SETJMP(a_pReNative, a_rcTarget) \
1079	a_rcTarget = VINF_SUCCESS; \
1080	try
1081	# define IEMNATIVE_CATCH_LONGJMP_BEGIN(a_pReNative, a_rcTarget) \
1082	catch (int rcThrown) \
1083	{ \
1084	a_rcTarget = rcThrown
1085	# define IEMNATIVE_CATCH_LONGJMP_END(a_pReNative) \
1086	} \
1087	((void)0)
1088	# define IEMNATIVE_DO_LONGJMP(a_pReNative, a_rc) throw int(a_rc)
1089	#else /* !IEM_WITH_THROW_CATCH */
1090	# define IEMNATIVE_TRY_SETJMP(a_pReNative, a_rcTarget) \
1091	if ((a_rcTarget = setjmp((a_pReNative)->JmpBuf)) == 0)
1092	# define IEMNATIVE_CATCH_LONGJMP_BEGIN(a_pReNative, a_rcTarget) \
1093	else \
1094	{ \
1095	((void)0)
1096	# define IEMNATIVE_CATCH_LONGJMP_END(a_pReNative) \
1097	}
1098	# define IEMNATIVE_DO_LONGJMP(a_pReNative, a_rc) longjmp((a_pReNative)->JmpBuf, (a_rc))
1099	#endif /* !IEM_WITH_THROW_CATCH */
1100
1101
1102	/**
1103	* Native recompiler worker for a threaded function.
1104	*
1105	* @returns New code buffer offset; throws VBox status code in case of a failure.
1106	* @param pReNative The native recompiler state.
1107	* @param off The current code buffer offset.
1108	* @param pCallEntry The threaded call entry.
1109	*
1110	* @note This may throw/longjmp VBox status codes (int) to abort compilation, so no RT_NOEXCEPT!
1111	*/
1112	typedef uint32_t (VBOXCALL FNIEMNATIVERECOMPFUNC)(PIEMRECOMPILERSTATE pReNative, uint32_t off, PCIEMTHRDEDCALLENTRY pCallEntry);
1113	/** Pointer to a native recompiler worker for a threaded function. */
1114	typedef FNIEMNATIVERECOMPFUNC *PFNIEMNATIVERECOMPFUNC;
1115
1116	/** Defines a native recompiler worker for a threaded function.
1117	* @see FNIEMNATIVERECOMPFUNC */
1118	#define IEM_DECL_IEMNATIVERECOMPFUNC_DEF(a_Name) \
1119	uint32_t VBOXCALL a_Name(PIEMRECOMPILERSTATE pReNative, uint32_t off, PCIEMTHRDEDCALLENTRY pCallEntry)
1120
1121	/** Prototypes a native recompiler function for a threaded function.
1122	* @see FNIEMNATIVERECOMPFUNC */
1123	#define IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(a_Name) FNIEMNATIVERECOMPFUNC a_Name
1124
1125
1126	/**
1127	* Native recompiler liveness analysis worker for a threaded function.
1128	*
1129	* @param pCallEntry The threaded call entry.
1130	* @param pIncoming The incoming liveness state entry.
1131	* @param pOutgoing The outgoing liveness state entry.
1132	*/
1133	typedef DECLCALLBACKTYPE(void, FNIEMNATIVELIVENESSFUNC, (PCIEMTHRDEDCALLENTRY pCallEntry,
1134	PCIEMLIVENESSENTRY pIncoming, PIEMLIVENESSENTRY pOutgoing));
1135	/** Pointer to a native recompiler liveness analysis worker for a threaded function. */
1136	typedef FNIEMNATIVELIVENESSFUNC *PFNIEMNATIVELIVENESSFUNC;
1137
1138	/** Defines a native recompiler liveness analysis worker for a threaded function.
1139	* @see FNIEMNATIVELIVENESSFUNC */
1140	#define IEM_DECL_IEMNATIVELIVENESSFUNC_DEF(a_Name) \
1141	DECLCALLBACK(void) a_Name(PCIEMTHRDEDCALLENTRY pCallEntry, PCIEMLIVENESSENTRY pIncoming, PIEMLIVENESSENTRY pOutgoing)
1142
1143	/** Prototypes a native recompiler liveness analysis function for a threaded function.
1144	* @see FNIEMNATIVELIVENESSFUNC */
1145	#define IEM_DECL_IEMNATIVELIVENESSFUNC_PROTO(a_Name) FNIEMNATIVELIVENESSFUNC a_Name
1146
1147
1148	/** Define a native recompiler helper function, safe to call from the TB code. */
1149	#define IEM_DECL_NATIVE_HLP_DEF(a_RetType, a_Name, a_ArgList) \
1150	DECL_HIDDEN_THROW(a_RetType) VBOXCALL a_Name a_ArgList
1151	/** Prototype a native recompiler helper function, safe to call from the TB code. */
1152	#define IEM_DECL_NATIVE_HLP_PROTO(a_RetType, a_Name, a_ArgList) \
1153	DECL_HIDDEN_THROW(a_RetType) VBOXCALL a_Name a_ArgList
1154
1155
1156	DECL_HIDDEN_THROW(uint32_t) iemNativeLabelCreate(PIEMRECOMPILERSTATE pReNative, IEMNATIVELABELTYPE enmType,
1157	uint32_t offWhere = UINT32_MAX, uint16_t uData = 0);
1158	DECL_HIDDEN_THROW(void) iemNativeLabelDefine(PIEMRECOMPILERSTATE pReNative, uint32_t idxLabel, uint32_t offWhere);
1159	DECL_HIDDEN_THROW(void) iemNativeAddFixup(PIEMRECOMPILERSTATE pReNative, uint32_t offWhere, uint32_t idxLabel,
1160	IEMNATIVEFIXUPTYPE enmType, int8_t offAddend = 0);
1161	DECL_HIDDEN_THROW(PIEMNATIVEINSTR) iemNativeInstrBufEnsureSlow(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t cInstrReq);
1162
1163	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmp(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, bool fPreferVolatile = true);
1164	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpEx(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint32_t fRegMask,
1165	bool fPreferVolatile = true);
1166	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpImm(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint64_t uImm,
1167	bool fPreferVolatile = true);
1168	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpForGuestReg(PIEMRECOMPILERSTATE pReNative, uint32_t *poff,
1169	IEMNATIVEGSTREG enmGstReg,
1170	IEMNATIVEGSTREGUSE enmIntendedUse = kIemNativeGstRegUse_ReadOnly,
1171	bool fNoVolatileRegs = false, bool fSkipLivenessAssert = false);
1172	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpForGuestRegIfAlreadyPresent(PIEMRECOMPILERSTATE pReNative, uint32_t *poff,
1173	IEMNATIVEGSTREG enmGstReg);
1174
1175	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocVar(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint8_t idxVar);
1176	DECL_HIDDEN_THROW(uint32_t) iemNativeRegAllocArgs(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs);
1177	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAssignRc(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg);
1178	DECLHIDDEN(void) iemNativeRegFree(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
1179	DECLHIDDEN(void) iemNativeRegFreeTmp(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
1180	DECLHIDDEN(void) iemNativeRegFreeTmpImm(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
1181	DECLHIDDEN(void) iemNativeRegFreeVar(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg, bool fFlushShadows) RT_NOEXCEPT;
1182	DECLHIDDEN(void) iemNativeRegFreeAndFlushMask(PIEMRECOMPILERSTATE pReNative, uint32_t fHstRegMask) RT_NOEXCEPT;
1183	DECL_HIDDEN_THROW(uint32_t) iemNativeRegFlushPendingWrites(PIEMRECOMPILERSTATE pReNative, uint32_t off);
1184	DECL_HIDDEN_THROW(uint32_t) iemNativeRegMoveAndFreeAndFlushAtCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs,
1185	uint32_t fKeepVars = 0);
1186	DECLHIDDEN(void) iemNativeRegFlushGuestShadows(PIEMRECOMPILERSTATE pReNative, uint64_t fGstRegs) RT_NOEXCEPT;
1187	DECLHIDDEN(void) iemNativeRegFlushGuestShadowsByHostMask(PIEMRECOMPILERSTATE pReNative, uint32_t fHstRegs) RT_NOEXCEPT;
1188	DECL_HIDDEN_THROW(uint32_t) iemNativeRegRestoreGuestShadowsInVolatileRegs(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1189	uint32_t fHstRegsActiveShadows);
1190
1191	DECL_HIDDEN_THROW(uint8_t) iemNativeVarGetStackSlot(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar);
1192	DECL_HIDDEN_THROW(uint8_t) iemNativeVarRegisterAcquire(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, uint32_t *poff,
1193	bool fInitialized = false, uint8_t idxRegPref = UINT8_MAX);
1194	DECL_HIDDEN_THROW(uint8_t) iemNativeVarRegisterAcquireForGuestReg(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar,
1195	IEMNATIVEGSTREG enmGstReg, uint32_t *poff);
1196	DECL_HIDDEN_THROW(uint32_t) iemNativeVarSaveVolatileRegsPreHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1197	uint32_t fHstRegsNotToSave);
1198	DECL_HIDDEN_THROW(uint32_t) iemNativeVarRestoreVolatileRegsPostHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1199	uint32_t fHstRegsNotToSave);
1200
1201	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitLoadGprWithGstShadowReg(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1202	uint8_t idxHstReg, IEMNATIVEGSTREG enmGstReg);
1203	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitCheckCallRetAndPassUp(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr);
1204	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitCImplCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr,
1205	uint64_t fGstShwFlush, uintptr_t pfnCImpl, uint8_t cbInstr, uint8_t cAddParams,
1206	uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
1207	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitThreadedCall(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1208	PCIEMTHRDEDCALLENTRY pCallEntry);
1209
1210	extern DECL_HIDDEN_DATA(const char * const) g_apszIemNativeHstRegNames[];
1211
1212
1213	/**
1214	* Ensures that there is sufficient space in the instruction output buffer.
1215	*
1216	* This will reallocate the buffer if needed and allowed.
1217	*
1218	* @note Always use IEMNATIVE_ASSERT_INSTR_BUF_ENSURE when done to check the
1219	* allocation size.
1220	*
1221	* @returns Pointer to the instruction output buffer on success; throws VBox
1222	* status code on failure, so no need to check it.
1223	* @param pReNative The native recompile state.
1224	* @param off Current instruction offset. Works safely for UINT32_MAX
1225	* as well.
1226	* @param cInstrReq Number of instruction about to be added. It's okay to
1227	* overestimate this a bit.
1228	*/
1229	DECL_FORCE_INLINE_THROW(PIEMNATIVEINSTR)
1230	iemNativeInstrBufEnsure(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t cInstrReq)
1231	{
1232	uint64_t const offChecked = off + (uint64_t)cInstrReq; /** @todo may reconsider the need for UINT32_MAX safety... */
1233	if (RT_LIKELY(offChecked <= pReNative->cInstrBufAlloc))
1234	{
1235	#ifdef VBOX_STRICT
1236	pReNative->offInstrBufChecked = offChecked;
1237	#endif
1238	return pReNative->pInstrBuf;
1239	}
1240	return iemNativeInstrBufEnsureSlow(pReNative, off, cInstrReq);
1241	}
1242
1243	/**
1244	* Checks that we didn't exceed the space requested in the last
1245	* iemNativeInstrBufEnsure() call.
1246	*/
1247	#define IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(a_pReNative, a_off) \
1248	AssertMsg((a_off) <= (a_pReNative)->offInstrBufChecked, \
1249	("off=%#x offInstrBufChecked=%#x\n", (a_off), (a_pReNative)->offInstrBufChecked))
1250
1251	/**
1252	* Checks that a variable index is valid.
1253	*/
1254	#define IEMNATIVE_ASSERT_VAR_IDX(a_pReNative, a_idxVar) \
1255	AssertMsg( (unsigned)(a_idxVar) < RT_ELEMENTS((a_pReNative)->Core.aVars) \
1256	&& ((a_pReNative)->Core.bmVars & RT_BIT_32(a_idxVar)), ("%s=%d\n", #a_idxVar, a_idxVar))
1257
1258	/**
1259	* Checks that a variable index is valid and that the variable is assigned the
1260	* correct argument number.
1261	* This also adds a RT_NOREF of a_idxVar.
1262	*/
1263	#define IEMNATIVE_ASSERT_ARG_VAR_IDX(a_pReNative, a_idxVar, a_uArgNo) do { \
1264	RT_NOREF_PV(a_idxVar); \
1265	AssertMsg( (unsigned)(a_idxVar) < RT_ELEMENTS((a_pReNative)->Core.aVars) \
1266	&& ((a_pReNative)->Core.bmVars & RT_BIT_32(a_idxVar))\
1267	&& (a_pReNative)->Core.aVars[a_idxVar].uArgNo == (a_uArgNo) \
1268	, ("%s=%d; uArgNo=%d, expected %u\n", #a_idxVar, a_idxVar, \
1269	(a_pReNative)->Core.aVars[RT_MAX(a_idxVar, RT_ELEMENTS((a_pReNative)->Core.aVars)) - 1].uArgNo, a_uArgNo)); \
1270	} while (0)
1271
1272	/**
1273	* Calculates the stack address of a variable as a [r]BP displacement value.
1274	*/
1275	DECL_FORCE_INLINE(int32_t)
1276	iemNativeStackCalcBpDisp(uint8_t idxStackSlot)
1277	{
1278	Assert(idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS);
1279	return idxStackSlot * sizeof(uint64_t) + IEMNATIVE_FP_OFF_STACK_VARS;
1280	}
1281
1282
1283	/**
1284	* Releases the variable's register.
1285	*
1286	* The register must have been previously acquired calling
1287	* iemNativeVarRegisterAcquire(), iemNativeVarRegisterAcquireForGuestReg() or
1288	* iemNativeVarRegisterSetAndAcquire().
1289	*/
1290	DECL_INLINE_THROW(void) iemNativeVarRegisterRelease(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar)
1291	{
1292	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
1293	Assert(pReNative->Core.aVars[idxVar].fRegAcquired);
1294	pReNative->Core.aVars[idxVar].fRegAcquired = false;
1295	}
1296
1297	/** @} */
1298
1299	#endif /* !VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h */
1300

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