IEMN8veRecompiler.h@ 103599

Last change on this file since 103599 was 103592, checked in by vboxsync, 12 months ago
VMM/IEM: Native translation of IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() body (untested due to no instruction still being re-compilable), bugref:10371
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 57.1 KB

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1	/* $Id: IEMN8veRecompiler.h 103592 2024-02-27 17:19:48Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager - Native Recompiler Internals.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h
29	#define VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34
35	/** @defgroup grp_iem_n8ve_re Native Recompiler Internals.
36	* @ingroup grp_iem_int
37	* @{
38	*/
39
40	/** @def IEMNATIVE_WITH_TB_DEBUG_INFO
41	* Enables generating internal debug info for better TB disassembly dumping. */
42	#if defined(DEBUG) \|\| defined(DOXYGEN_RUNNING)
43	# define IEMNATIVE_WITH_TB_DEBUG_INFO
44	#endif
45
46	/** @def IEMNATIVE_WITH_LIVENESS_ANALYSIS
47	* Enables liveness analysis. */
48	#if 1 \|\| defined(DOXYGEN_RUNNING)
49	# define IEMNATIVE_WITH_LIVENESS_ANALYSIS
50	/# define IEMLIVENESS_EXTENDED_LAYOUT/
51	#endif
52
53	#ifdef VBOX_WITH_STATISTICS
54	/** Always count instructions for now. */
55	# define IEMNATIVE_WITH_INSTRUCTION_COUNTING
56	#endif
57
58
59	/** @name Stack Frame Layout
60	*
61	* @{ */
62	/** The size of the area for stack variables and spills and stuff.
63	* @note This limit is duplicated in the python script(s). We add 0x40 for
64	* alignment padding. */
65	#define IEMNATIVE_FRAME_VAR_SIZE (0xc0 + 0x40)
66	/** Number of 64-bit variable slots (0x100 / 8 = 32. */
67	#define IEMNATIVE_FRAME_VAR_SLOTS (IEMNATIVE_FRAME_VAR_SIZE / 8)
68	AssertCompile(IEMNATIVE_FRAME_VAR_SLOTS == 32);
69
70	#ifdef RT_ARCH_AMD64
71	/** An stack alignment adjustment (between non-volatile register pushes and
72	* the stack variable area, so the latter better aligned). */
73	# define IEMNATIVE_FRAME_ALIGN_SIZE 8
74
75	/** Number of stack arguments slots for calls made from the frame. */
76	# ifdef RT_OS_WINDOWS
77	# define IEMNATIVE_FRAME_STACK_ARG_COUNT 4
78	# else
79	# define IEMNATIVE_FRAME_STACK_ARG_COUNT 2
80	# endif
81	/** Number of any shadow arguments (spill area) for calls we make. */
82	# ifdef RT_OS_WINDOWS
83	# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 4
84	# else
85	# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 0
86	# endif
87
88	/** Frame pointer (RBP) relative offset of the last push. */
89	# ifdef RT_OS_WINDOWS
90	# define IEMNATIVE_FP_OFF_LAST_PUSH (7 * -8)
91	# else
92	# define IEMNATIVE_FP_OFF_LAST_PUSH (5 * -8)
93	# endif
94	/** Frame pointer (RBP) relative offset of the stack variable area (the lowest
95	* address for it). */
96	# define IEMNATIVE_FP_OFF_STACK_VARS (IEMNATIVE_FP_OFF_LAST_PUSH - IEMNATIVE_FRAME_ALIGN_SIZE - IEMNATIVE_FRAME_VAR_SIZE)
97	/** Frame pointer (RBP) relative offset of the first stack argument for calls. */
98	# define IEMNATIVE_FP_OFF_STACK_ARG0 (IEMNATIVE_FP_OFF_STACK_VARS - IEMNATIVE_FRAME_STACK_ARG_COUNT * 8)
99	/** Frame pointer (RBP) relative offset of the second stack argument for calls. */
100	# define IEMNATIVE_FP_OFF_STACK_ARG1 (IEMNATIVE_FP_OFF_STACK_ARG0 + 8)
101	# ifdef RT_OS_WINDOWS
102	/** Frame pointer (RBP) relative offset of the third stack argument for calls. */
103	# define IEMNATIVE_FP_OFF_STACK_ARG2 (IEMNATIVE_FP_OFF_STACK_ARG0 + 16)
104	/** Frame pointer (RBP) relative offset of the fourth stack argument for calls. */
105	# define IEMNATIVE_FP_OFF_STACK_ARG3 (IEMNATIVE_FP_OFF_STACK_ARG0 + 24)
106	# endif
107
108	# ifdef RT_OS_WINDOWS
109	/** Frame pointer (RBP) relative offset of the first incoming shadow argument. */
110	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG0 (16)
111	/** Frame pointer (RBP) relative offset of the second incoming shadow argument. */
112	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG1 (24)
113	/** Frame pointer (RBP) relative offset of the third incoming shadow argument. */
114	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG2 (32)
115	/** Frame pointer (RBP) relative offset of the fourth incoming shadow argument. */
116	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG3 (40)
117	# endif
118
119	#elif RT_ARCH_ARM64
120	/** No alignment padding needed for arm64. */
121	# define IEMNATIVE_FRAME_ALIGN_SIZE 0
122	/** No stack argument slots, got 8 registers for arguments will suffice. */
123	# define IEMNATIVE_FRAME_STACK_ARG_COUNT 0
124	/** There are no argument spill area. */
125	# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 0
126
127	/** Number of saved registers at the top of our stack frame.
128	* This includes the return address and old frame pointer, so x19 thru x30. */
129	# define IEMNATIVE_FRAME_SAVE_REG_COUNT (12)
130	/** The size of the save registered (IEMNATIVE_FRAME_SAVE_REG_COUNT). */
131	# define IEMNATIVE_FRAME_SAVE_REG_SIZE (IEMNATIVE_FRAME_SAVE_REG_COUNT * 8)
132
133	/** Frame pointer (BP) relative offset of the last push. */
134	# define IEMNATIVE_FP_OFF_LAST_PUSH (10 * -8)
135
136	/** Frame pointer (BP) relative offset of the stack variable area (the lowest
137	* address for it). */
138	# define IEMNATIVE_FP_OFF_STACK_VARS (IEMNATIVE_FP_OFF_LAST_PUSH - IEMNATIVE_FRAME_ALIGN_SIZE - IEMNATIVE_FRAME_VAR_SIZE)
139
140	#else
141	# error "port me"
142	#endif
143	/** @} */
144
145
146	/** @name Fixed Register Allocation(s)
147	* @{ */
148	/** @def IEMNATIVE_REG_FIXED_PVMCPU
149	* The number of the register holding the pVCpu pointer. */
150	/** @def IEMNATIVE_REG_FIXED_PCPUMCTX
151	* The number of the register holding the &pVCpu->cpum.GstCtx pointer.
152	* @note This not available on AMD64, only ARM64. */
153	/** @def IEMNATIVE_REG_FIXED_TMP0
154	* Dedicated temporary register.
155	* @todo replace this by a register allocator and content tracker. */
156	/** @def IEMNATIVE_REG_FIXED_MASK
157	* Mask GPRs with fixes assignments, either by us or dictated by the CPU/OS
158	* architecture. */
159	#if defined(RT_ARCH_AMD64) && !defined(DOXYGEN_RUNNING)
160	# define IEMNATIVE_REG_FIXED_PVMCPU X86_GREG_xBX
161	# define IEMNATIVE_REG_FIXED_TMP0 X86_GREG_x11
162	# define IEMNATIVE_REG_FIXED_MASK ( RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU) \
163	\| RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0) \
164	\| RT_BIT_32(X86_GREG_xSP) \
165	\| RT_BIT_32(X86_GREG_xBP) )
166
167	#elif defined(RT_ARCH_ARM64) \|\| defined(DOXYGEN_RUNNING)
168	# define IEMNATIVE_REG_FIXED_PVMCPU ARMV8_A64_REG_X28
169	# define IEMNATIVE_REG_FIXED_PCPUMCTX ARMV8_A64_REG_X27
170	# define IEMNATIVE_REG_FIXED_TMP0 ARMV8_A64_REG_X15
171	# define IEMNATIVE_REG_FIXED_MASK ( RT_BIT_32(ARMV8_A64_REG_SP) \
172	\| RT_BIT_32(ARMV8_A64_REG_LR) \
173	\| RT_BIT_32(ARMV8_A64_REG_BP) \
174	\| RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU) \
175	\| RT_BIT_32(IEMNATIVE_REG_FIXED_PCPUMCTX) \
176	\| RT_BIT_32(ARMV8_A64_REG_X18) \
177	\| RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0) )
178
179	#else
180	# error "port me"
181	#endif
182	/** @} */
183
184	/** @name Call related registers.
185	* @{ */
186	/** @def IEMNATIVE_CALL_RET_GREG
187	* The return value register. */
188	/** @def IEMNATIVE_CALL_ARG_GREG_COUNT
189	* Number of arguments in registers. */
190	/** @def IEMNATIVE_CALL_ARG0_GREG
191	* The general purpose register carrying argument \#0. */
192	/** @def IEMNATIVE_CALL_ARG1_GREG
193	* The general purpose register carrying argument \#1. */
194	/** @def IEMNATIVE_CALL_ARG2_GREG
195	* The general purpose register carrying argument \#2. */
196	/** @def IEMNATIVE_CALL_ARG3_GREG
197	* The general purpose register carrying argument \#3. */
198	/** @def IEMNATIVE_CALL_VOLATILE_GREG_MASK
199	* Mask of registers the callee will not save and may trash. */
200	#ifdef RT_ARCH_AMD64
201	# define IEMNATIVE_CALL_RET_GREG X86_GREG_xAX
202
203	# ifdef RT_OS_WINDOWS
204	# define IEMNATIVE_CALL_ARG_GREG_COUNT 4
205	# define IEMNATIVE_CALL_ARG0_GREG X86_GREG_xCX
206	# define IEMNATIVE_CALL_ARG1_GREG X86_GREG_xDX
207	# define IEMNATIVE_CALL_ARG2_GREG X86_GREG_x8
208	# define IEMNATIVE_CALL_ARG3_GREG X86_GREG_x9
209	# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \
210	\| RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \
211	\| RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG) \
212	\| RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) )
213	# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(X86_GREG_xAX) \
214	\| RT_BIT_32(X86_GREG_xCX) \
215	\| RT_BIT_32(X86_GREG_xDX) \
216	\| RT_BIT_32(X86_GREG_x8) \
217	\| RT_BIT_32(X86_GREG_x9) \
218	\| RT_BIT_32(X86_GREG_x10) \
219	\| RT_BIT_32(X86_GREG_x11) )
220	# else
221	# define IEMNATIVE_CALL_ARG_GREG_COUNT 6
222	# define IEMNATIVE_CALL_ARG0_GREG X86_GREG_xDI
223	# define IEMNATIVE_CALL_ARG1_GREG X86_GREG_xSI
224	# define IEMNATIVE_CALL_ARG2_GREG X86_GREG_xDX
225	# define IEMNATIVE_CALL_ARG3_GREG X86_GREG_xCX
226	# define IEMNATIVE_CALL_ARG4_GREG X86_GREG_x8
227	# define IEMNATIVE_CALL_ARG5_GREG X86_GREG_x9
228	# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \
229	\| RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \
230	\| RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG) \
231	\| RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) \
232	\| RT_BIT_32(IEMNATIVE_CALL_ARG4_GREG) \
233	\| RT_BIT_32(IEMNATIVE_CALL_ARG5_GREG) )
234	# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(X86_GREG_xAX) \
235	\| RT_BIT_32(X86_GREG_xCX) \
236	\| RT_BIT_32(X86_GREG_xDX) \
237	\| RT_BIT_32(X86_GREG_xDI) \
238	\| RT_BIT_32(X86_GREG_xSI) \
239	\| RT_BIT_32(X86_GREG_x8) \
240	\| RT_BIT_32(X86_GREG_x9) \
241	\| RT_BIT_32(X86_GREG_x10) \
242	\| RT_BIT_32(X86_GREG_x11) )
243	# endif
244
245	#elif defined(RT_ARCH_ARM64)
246	# define IEMNATIVE_CALL_RET_GREG ARMV8_A64_REG_X0
247	# define IEMNATIVE_CALL_ARG_GREG_COUNT 8
248	# define IEMNATIVE_CALL_ARG0_GREG ARMV8_A64_REG_X0
249	# define IEMNATIVE_CALL_ARG1_GREG ARMV8_A64_REG_X1
250	# define IEMNATIVE_CALL_ARG2_GREG ARMV8_A64_REG_X2
251	# define IEMNATIVE_CALL_ARG3_GREG ARMV8_A64_REG_X3
252	# define IEMNATIVE_CALL_ARG4_GREG ARMV8_A64_REG_X4
253	# define IEMNATIVE_CALL_ARG5_GREG ARMV8_A64_REG_X5
254	# define IEMNATIVE_CALL_ARG6_GREG ARMV8_A64_REG_X6
255	# define IEMNATIVE_CALL_ARG7_GREG ARMV8_A64_REG_X7
256	# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(ARMV8_A64_REG_X0) \
257	\| RT_BIT_32(ARMV8_A64_REG_X1) \
258	\| RT_BIT_32(ARMV8_A64_REG_X2) \
259	\| RT_BIT_32(ARMV8_A64_REG_X3) \
260	\| RT_BIT_32(ARMV8_A64_REG_X4) \
261	\| RT_BIT_32(ARMV8_A64_REG_X5) \
262	\| RT_BIT_32(ARMV8_A64_REG_X6) \
263	\| RT_BIT_32(ARMV8_A64_REG_X7) )
264	# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(ARMV8_A64_REG_X0) \
265	\| RT_BIT_32(ARMV8_A64_REG_X1) \
266	\| RT_BIT_32(ARMV8_A64_REG_X2) \
267	\| RT_BIT_32(ARMV8_A64_REG_X3) \
268	\| RT_BIT_32(ARMV8_A64_REG_X4) \
269	\| RT_BIT_32(ARMV8_A64_REG_X5) \
270	\| RT_BIT_32(ARMV8_A64_REG_X6) \
271	\| RT_BIT_32(ARMV8_A64_REG_X7) \
272	\| RT_BIT_32(ARMV8_A64_REG_X8) \
273	\| RT_BIT_32(ARMV8_A64_REG_X9) \
274	\| RT_BIT_32(ARMV8_A64_REG_X10) \
275	\| RT_BIT_32(ARMV8_A64_REG_X11) \
276	\| RT_BIT_32(ARMV8_A64_REG_X12) \
277	\| RT_BIT_32(ARMV8_A64_REG_X13) \
278	\| RT_BIT_32(ARMV8_A64_REG_X14) \
279	\| RT_BIT_32(ARMV8_A64_REG_X15) \
280	\| RT_BIT_32(ARMV8_A64_REG_X16) \
281	\| RT_BIT_32(ARMV8_A64_REG_X17) )
282
283	#endif
284
285	/** This is the maximum argument count we'll ever be needing. */
286	#if defined(RT_OS_WINDOWS) && defined(VBOXSTRICTRC_STRICT_ENABLED)
287	# define IEMNATIVE_CALL_MAX_ARG_COUNT 8
288	#else
289	# define IEMNATIVE_CALL_MAX_ARG_COUNT 7
290	#endif
291	/** @} */
292
293
294	/** @def IEMNATIVE_HST_GREG_COUNT
295	* Number of host general purpose registers we tracker. */
296	/** @def IEMNATIVE_HST_GREG_MASK
297	* Mask corresponding to IEMNATIVE_HST_GREG_COUNT that can be applied to
298	* inverted register masks and such to get down to a correct set of regs. */
299	#ifdef RT_ARCH_AMD64
300	# define IEMNATIVE_HST_GREG_COUNT 16
301	# define IEMNATIVE_HST_GREG_MASK UINT32_C(0xffff)
302
303	#elif defined(RT_ARCH_ARM64)
304	# define IEMNATIVE_HST_GREG_COUNT 32
305	# define IEMNATIVE_HST_GREG_MASK UINT32_MAX
306	#else
307	# error "Port me!"
308	#endif
309
310
311	/** Native code generator label types. */
312	typedef enum
313	{
314	kIemNativeLabelType_Invalid = 0,
315	/* Labels w/o data, only once instance per TB: */
316	kIemNativeLabelType_Return,
317	kIemNativeLabelType_ReturnBreak,
318	kIemNativeLabelType_ReturnWithFlags,
319	kIemNativeLabelType_NonZeroRetOrPassUp,
320	kIemNativeLabelType_RaiseGp0,
321	kIemNativeLabelType_RaiseNm,
322	kIemNativeLabelType_RaiseUd,
323	kIemNativeLabelType_ObsoleteTb,
324	kIemNativeLabelType_NeedCsLimChecking,
325	kIemNativeLabelType_CheckBranchMiss,
326	/* Labels with data, potentially multiple instances per TB: */
327	kIemNativeLabelType_FirstWithMultipleInstances,
328	kIemNativeLabelType_If = kIemNativeLabelType_FirstWithMultipleInstances,
329	kIemNativeLabelType_Else,
330	kIemNativeLabelType_Endif,
331	kIemNativeLabelType_CheckIrq,
332	kIemNativeLabelType_TlbLookup,
333	kIemNativeLabelType_TlbMiss,
334	kIemNativeLabelType_TlbDone,
335	kIemNativeLabelType_End
336	} IEMNATIVELABELTYPE;
337
338	/** Native code generator label definition. */
339	typedef struct IEMNATIVELABEL
340	{
341	/** Code offset if defined, UINT32_MAX if it needs to be generated after/in
342	* the epilog. */
343	uint32_t off;
344	/** The type of label (IEMNATIVELABELTYPE). */
345	uint16_t enmType;
346	/** Additional label data, type specific. */
347	uint16_t uData;
348	} IEMNATIVELABEL;
349	/** Pointer to a label. */
350	typedef IEMNATIVELABEL *PIEMNATIVELABEL;
351
352
353	/** Native code generator fixup types. */
354	typedef enum
355	{
356	kIemNativeFixupType_Invalid = 0,
357	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
358	/** AMD64 fixup: PC relative 32-bit with addend in bData. */
359	kIemNativeFixupType_Rel32,
360	#elif defined(RT_ARCH_ARM64)
361	/** ARM64 fixup: PC relative offset at bits 25:0 (B, BL). */
362	kIemNativeFixupType_RelImm26At0,
363	/** ARM64 fixup: PC relative offset at bits 23:5 (CBZ, CBNZ, B.CC). */
364	kIemNativeFixupType_RelImm19At5,
365	/** ARM64 fixup: PC relative offset at bits 18:5 (TBZ, TBNZ). */
366	kIemNativeFixupType_RelImm14At5,
367	#endif
368	kIemNativeFixupType_End
369	} IEMNATIVEFIXUPTYPE;
370
371	/** Native code generator fixup. */
372	typedef struct IEMNATIVEFIXUP
373	{
374	/** Code offset of the fixup location. */
375	uint32_t off;
376	/** The IEMNATIVELABEL this is a fixup for. */
377	uint16_t idxLabel;
378	/** The fixup type (IEMNATIVEFIXUPTYPE). */
379	uint8_t enmType;
380	/** Addend or other data. */
381	int8_t offAddend;
382	} IEMNATIVEFIXUP;
383	/** Pointer to a native code generator fixup. */
384	typedef IEMNATIVEFIXUP *PIEMNATIVEFIXUP;
385
386
387	/**
388	* One bit of the state.
389	*
390	* Each register state takes up two bits. We keep the two bits in two separate
391	* 64-bit words to simplify applying them to the guest shadow register mask in
392	* the register allocator.
393	*/
394	typedef union IEMLIVENESSBIT
395	{
396	uint64_t bm64;
397	RT_GCC_EXTENSION struct
398	{ /* bit no */
399	uint64_t bmGprs : 16; /*< 0x00 / 0: The 16 general purpose registers. /
400	uint64_t fUnusedPc : 1; /*< 0x10 / 16: (PC in ) /
401	uint64_t uPadding1 : 3; /*< 0x11 / 17: /
402	uint64_t bmSegBase : 6; /*< 0x14 / 20: /
403	uint64_t bmSegAttrib : 6; /*< 0x1a / 26: /
404	uint64_t bmSegLimit : 6; /*< 0x20 / 32: /
405	uint64_t bmSegSel : 6; /*< 0x26 / 38: /
406	uint64_t fEflOther : 1; /*< 0x2c / 44: Other EFLAGS bits (~X86_EFL_STATUS_BITS & X86_EFL_LIVE_MASK). First! /
407	uint64_t fEflCf : 1; /*< 0x2d / 45: Carry flag (X86_EFL_CF / 0). /
408	uint64_t fEflPf : 1; /*< 0x2e / 46: Parity flag (X86_EFL_PF / 2). /
409	uint64_t fEflAf : 1; /*< 0x2f / 47: Auxilary carry flag (X86_EFL_AF / 4). /
410	uint64_t fEflZf : 1; /*< 0x30 / 48: Zero flag (X86_EFL_ZF / 6). /
411	uint64_t fEflSf : 1; /*< 0x31 / 49: Signed flag (X86_EFL_SF / 7). /
412	uint64_t fEflOf : 1; /*< 0x32 / 50: Overflow flag (X86_EFL_OF / 12). /
413	uint64_t uUnused : 13; /* 0x33 / 51 -> 0x40/64 */
414	};
415	} IEMLIVENESSBIT;
416	AssertCompileSize(IEMLIVENESSBIT, 8);
417
418	#define IEMLIVENESSBIT_IDX_EFL_OTHER ((unsigned)kIemNativeGstReg_EFlags + 0)
419	#define IEMLIVENESSBIT_IDX_EFL_CF ((unsigned)kIemNativeGstReg_EFlags + 1)
420	#define IEMLIVENESSBIT_IDX_EFL_PF ((unsigned)kIemNativeGstReg_EFlags + 2)
421	#define IEMLIVENESSBIT_IDX_EFL_AF ((unsigned)kIemNativeGstReg_EFlags + 3)
422	#define IEMLIVENESSBIT_IDX_EFL_ZF ((unsigned)kIemNativeGstReg_EFlags + 4)
423	#define IEMLIVENESSBIT_IDX_EFL_SF ((unsigned)kIemNativeGstReg_EFlags + 5)
424	#define IEMLIVENESSBIT_IDX_EFL_OF ((unsigned)kIemNativeGstReg_EFlags + 6)
425
426
427	/**
428	* A liveness state entry.
429	*
430	* The first 128 bits runs parallel to kIemNativeGstReg_xxx for the most part.
431	* Once we add a SSE register shadowing, we'll add another 64-bit element for
432	* that.
433	*/
434	typedef union IEMLIVENESSENTRY
435	{
436	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
437	uint64_t bm64[16 / 8];
438	uint16_t bm32[16 / 4];
439	uint16_t bm16[16 / 2];
440	uint8_t bm8[ 16 / 1];
441	IEMLIVENESSBIT aBits[2];
442	#else
443	uint64_t bm64[32 / 8];
444	uint16_t bm32[32 / 4];
445	uint16_t bm16[32 / 2];
446	uint8_t bm8[ 32 / 1];
447	IEMLIVENESSBIT aBits[4];
448	#endif
449	RT_GCC_EXTENSION struct
450	{
451	/** Bit \#0 of the register states. */
452	IEMLIVENESSBIT Bit0;
453	/** Bit \#1 of the register states. */
454	IEMLIVENESSBIT Bit1;
455	#ifdef IEMLIVENESS_EXTENDED_LAYOUT
456	/** Bit \#2 of the register states. */
457	IEMLIVENESSBIT Bit2;
458	/** Bit \#3 of the register states. */
459	IEMLIVENESSBIT Bit3;
460	#endif
461	};
462	} IEMLIVENESSENTRY;
463	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
464	AssertCompileSize(IEMLIVENESSENTRY, 16);
465	#else
466	AssertCompileSize(IEMLIVENESSENTRY, 32);
467	#endif
468	/** Pointer to a liveness state entry. */
469	typedef IEMLIVENESSENTRY *PIEMLIVENESSENTRY;
470	/** Pointer to a const liveness state entry. */
471	typedef IEMLIVENESSENTRY const *PCIEMLIVENESSENTRY;
472
473	/** @name 64-bit value masks for IEMLIVENESSENTRY.
474	* @{ / / 0xzzzzyyyyxxxxwwww */
475	#define IEMLIVENESSBIT_MASK UINT64_C(0x0007fffffff0ffff)
476
477	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
478	# define IEMLIVENESSBIT0_XCPT_OR_CALL UINT64_C(0x0000000000000000)
479	# define IEMLIVENESSBIT1_XCPT_OR_CALL IEMLIVENESSBIT_MASK
480
481	# define IEMLIVENESSBIT0_ALL_UNUSED IEMLIVENESSBIT_MASK
482	# define IEMLIVENESSBIT1_ALL_UNUSED UINT64_C(0x0000000000000000)
483	#endif
484
485	#define IEMLIVENESSBIT_ALL_EFL_MASK UINT64_C(0x0007f00000000000)
486
487	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
488	# define IEMLIVENESSBIT0_ALL_EFL_INPUT IEMLIVENESSBIT_ALL_EFL_MASK
489	# define IEMLIVENESSBIT1_ALL_EFL_INPUT IEMLIVENESSBIT_ALL_EFL_MASK
490	#endif
491	/** @} */
492
493
494	/** @name The liveness state for a register.
495	*
496	* The state values have been picked to with state accumulation in mind (what
497	* the iemNativeLivenessFunc_xxxx functions does), as that is the most
498	* performance critical work done with the values.
499	*
500	* This is a compressed state that only requires 2 bits per register.
501	* When accumulating state, we'll be using three IEMLIVENESSENTRY copies:
502	* 1. the incoming state from the following call,
503	* 2. the outgoing state for this call,
504	* 3. mask of the entries set in the 2nd.
505	*
506	* The mask entry (3rd one above) will be used both when updating the outgoing
507	* state and when merging in incoming state for registers not touched by the
508	* current call.
509	*
510	* @{ */
511	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
512	/** The register will be clobbered and the current value thrown away.
513	*
514	* When this is applied to the state (2) we'll simply be AND'ing it with the
515	* (old) mask (3) and adding the register to the mask. This way we'll
516	* preserve the high priority IEMLIVENESS_STATE_XCPT_OR_CALL and
517	* IEMLIVENESS_STATE_INPUT states. */
518	# define IEMLIVENESS_STATE_CLOBBERED 0
519	/** The register is unused in the remainder of the TB.
520	*
521	* This is an initial state and can not be set by any of the
522	* iemNativeLivenessFunc_xxxx callbacks. */
523	# define IEMLIVENESS_STATE_UNUSED 1
524	/** The register value is required in a potential call or exception.
525	*
526	* This means that the register value must be calculated and is best written to
527	* the state, but that any shadowing registers can be flushed thereafter as it's
528	* not used again. This state has lower priority than IEMLIVENESS_STATE_INPUT.
529	*
530	* It is typically applied across the board, but we preserve incoming
531	* IEMLIVENESS_STATE_INPUT values. This latter means we have to do some extra
532	* trickery to filter out IEMLIVENESS_STATE_UNUSED:
533	* 1. r0 = old & ~mask;
534	* 2. r0 = t1 & (t1 >> 1)'
535	* 3. state \|= r0 \| 0b10;
536	* 4. mask = ~0;
537	*/
538	# define IEMLIVENESS_STATE_XCPT_OR_CALL 2
539	/** The register value is used as input.
540	*
541	* This means that the register value must be calculated and it is best to keep
542	* it in a register. It does not need to be writtent out as such. This is the
543	* highest priority state.
544	*
545	* Whether the call modifies the register or not isn't relevant to earlier
546	* calls, so that's not recorded.
547	*
548	* When applying this state we just or in the value in the outgoing state and
549	* mask. */
550	# define IEMLIVENESS_STATE_INPUT 3
551	/** Mask of the state bits. */
552	# define IEMLIVENESS_STATE_MASK 3
553	/** The number of bits per state. */
554	# define IEMLIVENESS_STATE_BIT_COUNT 2
555	/** Check if we're expecting read & write accesses to a register with the given (previous) liveness state. */
556	# define IEMLIVENESS_STATE_IS_MODIFY_EXPECTED(a_uState) ((uint32_t)((a_uState) - 1U) >= (uint32_t)(IEMLIVENESS_STATE_INPUT - 1U))
557	/** Check if we're expecting read accesses to a register with the given (previous) liveness state. */
558	# define IEMLIVENESS_STATE_IS_INPUT_EXPECTED(a_uState) IEMLIVENESS_STATE_IS_MODIFY_EXPECTED(a_uState)
559	/** Check if a register clobbering is expected given the (previous) liveness state.
560	* The state must be either CLOBBERED or XCPT_OR_CALL, but it may also
561	* include INPUT if the register is used in more than one place. */
562	# define IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(a_uState) ((uint32_t)(a_uState) != IEMLIVENESS_STATE_UNUSED)
563
564	#else /* IEMLIVENESS_EXTENDED_LAYOUT */
565	/** The register is not used any more. */
566	# define IEMLIVENESS_STATE_UNUSED 0
567	/** Flag: The register is required in a potential exception or call. */
568	# define IEMLIVENESS_STATE_POT_XCPT_OR_CALL 1
569	# define IEMLIVENESS_BIT_POT_XCPT_OR_CALL 0
570	/** Flag: The register is read. */
571	# define IEMLIVENESS_STATE_READ 2
572	# define IEMLIVENESS_BIT_READ 1
573	/** Flag: The register is written. */
574	# define IEMLIVENESS_STATE_WRITE 4
575	# define IEMLIVENESS_BIT_WRITE 2
576	/** Flag: Unconditional call (not needed, can be redefined for research). */
577	# define IEMLIVENESS_STATE_CALL 8
578	# define IEMLIVENESS_BIT_CALL 3
579	# define IEMLIVENESS_BIT_OTHER 3 /*< More convenient name for this one. /
580	# define IEMLIVENESS_STATE_IS_MODIFY_EXPECTED(a_uState) \
581	( ((a_uState) & (IEMLIVENESS_STATE_WRITE \| IEMLIVENESS_STATE_READ)) == (IEMLIVENESS_STATE_WRITE \| IEMLIVENESS_STATE_READ) )
582	# define IEMLIVENESS_STATE_IS_INPUT_EXPECTED(a_uState) RT_BOOL((a_uState) & IEMLIVENESS_STATE_READ)
583	# define IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(a_uState) RT_BOOL((a_uState) & IEMLIVENESS_STATE_WRITE)
584	#endif /* IEMLIVENESS_EXTENDED_LAYOUT */
585	/** @} */
586
587	/** @name Liveness helpers for builtin functions and similar.
588	*
589	* These are not used by IEM_MC_BEGIN/END blocks, IEMAllN8veLiveness.cpp has its
590	* own set of manimulator macros for those.
591	*
592	* @{ */
593	/** Initializing the state as all unused. */
594	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
595	# define IEM_LIVENESS_RAW_INIT_AS_UNUSED(a_pOutgoing) \
596	do { \
597	(a_pOutgoing)->Bit0.bm64 = IEMLIVENESSBIT0_ALL_UNUSED; \
598	(a_pOutgoing)->Bit1.bm64 = IEMLIVENESSBIT1_ALL_UNUSED; \
599	} while (0)
600	#else
601	# define IEM_LIVENESS_RAW_INIT_AS_UNUSED(a_pOutgoing) \
602	do { \
603	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64 = 0; \
604	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ ].bm64 = 0; \
605	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_WRITE ].bm64 = 0; \
606	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_OTHER ].bm64 = 0; \
607	} while (0)
608	#endif
609
610	/** Initializing the outgoing state with a potential xcpt or call state.
611	* This only works when all later changes will be IEMLIVENESS_STATE_INPUT. */
612	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
613	# define IEM_LIVENESS_RAW_INIT_WITH_XCPT_OR_CALL(a_pOutgoing, a_pIncoming) \
614	do { \
615	(a_pOutgoing)->Bit0.bm64 = (a_pIncoming)->Bit0.bm64 & (a_pIncoming)->Bit1.bm64; \
616	(a_pOutgoing)->Bit1.bm64 = IEMLIVENESSBIT1_XCPT_OR_CALL; \
617	} while (0)
618	#else
619	# define IEM_LIVENESS_RAW_INIT_WITH_XCPT_OR_CALL(a_pOutgoing, a_pIncoming) \
620	do { \
621	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64 = IEMLIVENESSBIT_MASK; \
622	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ ].bm64 = (a_pIncoming)->aBits[IEMLIVENESS_BIT_READ].bm64; \
623	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_WRITE ].bm64 = 0; \
624	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_OTHER ].bm64 = 0; \
625	} while (0)
626	#endif
627
628	/** Adds a segment base register as input to the outgoing state. */
629	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
630	# define IEM_LIVENESS_RAW_SEG_BASE_INPUT(a_pOutgoing, a_iSReg) do { \
631	(a_pOutgoing)->Bit0.bmSegBase \|= RT_BIT_64(a_iSReg); \
632	(a_pOutgoing)->Bit1.bmSegBase \|= RT_BIT_64(a_iSReg); \
633	} while (0)
634	#else
635	# define IEM_LIVENESS_RAW_SEG_BASE_INPUT(a_pOutgoing, a_iSReg) do { \
636	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].bmSegBase \|= RT_BIT_64(a_iSReg); \
637	} while (0)
638	#endif
639
640	/** Adds a segment attribute register as input to the outgoing state. */
641	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
642	# define IEM_LIVENESS_RAW_SEG_ATTRIB_INPUT(a_pOutgoing, a_iSReg) do { \
643	(a_pOutgoing)->Bit0.bmSegAttrib \|= RT_BIT_64(a_iSReg); \
644	(a_pOutgoing)->Bit1.bmSegAttrib \|= RT_BIT_64(a_iSReg); \
645	} while (0)
646	#else
647	# define IEM_LIVENESS_RAW_SEG_ATTRIB_INPUT(a_pOutgoing, a_iSReg) do { \
648	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].bmSegAttrib \|= RT_BIT_64(a_iSReg); \
649	} while (0)
650	#endif
651
652	/** Adds a segment limit register as input to the outgoing state. */
653	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
654	# define IEM_LIVENESS_RAW_SEG_LIMIT_INPUT(a_pOutgoing, a_iSReg) do { \
655	(a_pOutgoing)->Bit0.bmSegLimit \|= RT_BIT_64(a_iSReg); \
656	(a_pOutgoing)->Bit1.bmSegLimit \|= RT_BIT_64(a_iSReg); \
657	} while (0)
658	#else
659	# define IEM_LIVENESS_RAW_SEG_LIMIT_INPUT(a_pOutgoing, a_iSReg) do { \
660	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].bmSegLimit \|= RT_BIT_64(a_iSReg); \
661	} while (0)
662	#endif
663
664	/** Adds a segment limit register as input to the outgoing state. */
665	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
666	# define IEM_LIVENESS_RAW_EFLAGS_ONE_INPUT(a_pOutgoing, a_fEflMember) do { \
667	(a_pOutgoing)->Bit0.a_fEflMember \|= 1; \
668	(a_pOutgoing)->Bit1.a_fEflMember \|= 1; \
669	} while (0)
670	#else
671	# define IEM_LIVENESS_RAW_EFLAGS_ONE_INPUT(a_pOutgoing, a_fEflMember) do { \
672	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].a_fEflMember \|= 1; \
673	} while (0)
674	#endif
675	/** @} */
676
677	/**
678	* Guest registers that can be shadowed in GPRs.
679	*
680	* This runs parallel to the first 128-bits of liveness state. To avoid having
681	* the SegLimitXxxx range cross from the 1st 64-bit word to the 2nd,
682	* we've inserted some padding. The EFlags must be placed last, as the liveness
683	* state tracks it as 7 subcomponents and we don't want to waste space here.
684	*/
685	typedef enum IEMNATIVEGSTREG : uint8_t
686	{
687	kIemNativeGstReg_GprFirst = 0,
688	kIemNativeGstReg_GprLast = kIemNativeGstReg_GprFirst + 15,
689	kIemNativeGstReg_Pc,
690	kIemNativeGstReg_Cr0,
691	kIemNativeGstReg_FpuFcw,
692	kIemNativeGstReg_FpuFsw,
693	kIemNativeGstReg_SegBaseFirst,
694	kIemNativeGstReg_SegBaseLast = kIemNativeGstReg_SegBaseFirst + 5,
695	kIemNativeGstReg_SegAttribFirst,
696	kIemNativeGstReg_SegAttribLast = kIemNativeGstReg_SegAttribFirst + 5,
697	kIemNativeGstReg_SegLimitFirst,
698	kIemNativeGstReg_SegLimitLast = kIemNativeGstReg_SegLimitFirst + 5,
699	kIemNativeGstReg_SegSelFirst,
700	kIemNativeGstReg_SegSelLast = kIemNativeGstReg_SegSelFirst + 5,
701	kIemNativeGstReg_Cr4,
702	kIemNativeGstReg_EFlags, /*< 32-bit, includes internal flags - last! /
703	kIemNativeGstReg_End
704	} IEMNATIVEGSTREG;
705	AssertCompile((int)kIemNativeGstReg_SegLimitFirst == 32);
706
707	/** @name Helpers for converting register numbers to IEMNATIVEGSTREG values.
708	* @{ */
709	#define IEMNATIVEGSTREG_GPR(a_iGpr) ((IEMNATIVEGSTREG)(kIemNativeGstReg_GprFirst + (a_iGpr) ))
710	#define IEMNATIVEGSTREG_SEG_SEL(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegSelFirst + (a_iSegReg) ))
711	#define IEMNATIVEGSTREG_SEG_BASE(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegBaseFirst + (a_iSegReg) ))
712	#define IEMNATIVEGSTREG_SEG_LIMIT(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegLimitFirst + (a_iSegReg) ))
713	#define IEMNATIVEGSTREG_SEG_ATTRIB(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegAttribFirst + (a_iSegReg) ))
714	/** @} */
715
716	/**
717	* Intended use statement for iemNativeRegAllocTmpForGuestReg().
718	*/
719	typedef enum IEMNATIVEGSTREGUSE
720	{
721	/** The usage is read-only, the register holding the guest register
722	* shadow copy will not be modified by the caller. */
723	kIemNativeGstRegUse_ReadOnly = 0,
724	/** The caller will update the guest register (think: PC += cbInstr).
725	* The guest shadow copy will follow the returned register. */
726	kIemNativeGstRegUse_ForUpdate,
727	/** The call will put an entirely new value in the guest register, so
728	* if new register is allocate it will be returned uninitialized. */
729	kIemNativeGstRegUse_ForFullWrite,
730	/** The caller will use the guest register value as input in a calculation
731	* and the host register will be modified.
732	* This means that the returned host register will not be marked as a shadow
733	* copy of the guest register. */
734	kIemNativeGstRegUse_Calculation
735	} IEMNATIVEGSTREGUSE;
736
737	/**
738	* Guest registers (classes) that can be referenced.
739	*/
740	typedef enum IEMNATIVEGSTREGREF : uint8_t
741	{
742	kIemNativeGstRegRef_Invalid = 0,
743	kIemNativeGstRegRef_Gpr,
744	kIemNativeGstRegRef_GprHighByte, /*< AH, CH, DH, BH/
745	kIemNativeGstRegRef_EFlags,
746	kIemNativeGstRegRef_MxCsr,
747	kIemNativeGstRegRef_FpuReg,
748	kIemNativeGstRegRef_MReg,
749	kIemNativeGstRegRef_XReg,
750	//kIemNativeGstRegRef_YReg, - doesn't work.
751	kIemNativeGstRegRef_End
752	} IEMNATIVEGSTREGREF;
753
754
755	/** Variable kinds. */
756	typedef enum IEMNATIVEVARKIND : uint8_t
757	{
758	/** Customary invalid zero value. */
759	kIemNativeVarKind_Invalid = 0,
760	/** This is either in a register or on the stack. */
761	kIemNativeVarKind_Stack,
762	/** Immediate value - loaded into register when needed, or can live on the
763	* stack if referenced (in theory). */
764	kIemNativeVarKind_Immediate,
765	/** Variable reference - loaded into register when needed, never stack. */
766	kIemNativeVarKind_VarRef,
767	/** Guest register reference - loaded into register when needed, never stack. */
768	kIemNativeVarKind_GstRegRef,
769	/** End of valid values. */
770	kIemNativeVarKind_End
771	} IEMNATIVEVARKIND;
772
773
774	/** Variable or argument. */
775	typedef struct IEMNATIVEVAR
776	{
777	/** The kind of variable. */
778	IEMNATIVEVARKIND enmKind;
779	/** The variable size in bytes. */
780	uint8_t cbVar;
781	/** The first stack slot (uint64_t), except for immediate and references
782	* where it usually is UINT8_MAX. This is allocated lazily, so if a variable
783	* has a stack slot it has been initialized and has a value. Unused variables
784	* has neither a stack slot nor a host register assignment. */
785	uint8_t idxStackSlot;
786	/** The host register allocated for the variable, UINT8_MAX if not. */
787	uint8_t idxReg;
788	/** The argument number if argument, UINT8_MAX if regular variable. */
789	uint8_t uArgNo;
790	/** If referenced, the index of the variable referencing this one, otherwise
791	* UINT8_MAX. A referenced variable must only be placed on the stack and
792	* must be either kIemNativeVarKind_Stack or kIemNativeVarKind_Immediate. */
793	uint8_t idxReferrerVar;
794	/** Guest register being shadowed here, kIemNativeGstReg_End(/UINT8_MAX) if not.
795	* @todo not sure what this really is for... */
796	IEMNATIVEGSTREG enmGstReg;
797	/** Set if the registered is currently used exclusively, false if the
798	* variable is idle and the register can be grabbed. */
799	bool fRegAcquired;
800
801	union
802	{
803	/** kIemNativeVarKind_Immediate: The immediate value. */
804	uint64_t uValue;
805	/** kIemNativeVarKind_VarRef: The index of the variable being referenced. */
806	uint8_t idxRefVar;
807	/** kIemNativeVarKind_GstRegRef: The guest register being referrenced. */
808	struct
809	{
810	/** The class of register. */
811	IEMNATIVEGSTREGREF enmClass;
812	/** Index within the class. */
813	uint8_t idx;
814	} GstRegRef;
815	} u;
816	} IEMNATIVEVAR;
817
818	/** What is being kept in a host register. */
819	typedef enum IEMNATIVEWHAT : uint8_t
820	{
821	/** The traditional invalid zero value. */
822	kIemNativeWhat_Invalid = 0,
823	/** Mapping a variable (IEMNATIVEHSTREG::idxVar). */
824	kIemNativeWhat_Var,
825	/** Temporary register, this is typically freed when a MC completes. */
826	kIemNativeWhat_Tmp,
827	/** Call argument w/o a variable mapping. This is free (via
828	* IEMNATIVE_CALL_VOLATILE_GREG_MASK) after the call is emitted. */
829	kIemNativeWhat_Arg,
830	/** Return status code.
831	* @todo not sure if we need this... */
832	kIemNativeWhat_rc,
833	/** The fixed pVCpu (PVMCPUCC) register.
834	* @todo consider offsetting this on amd64 to use negative offsets to access
835	* more members using 8-byte disp. */
836	kIemNativeWhat_pVCpuFixed,
837	/** The fixed pCtx (PCPUMCTX) register.
838	* @todo consider offsetting this on amd64 to use negative offsets to access
839	* more members using 8-byte disp. */
840	kIemNativeWhat_pCtxFixed,
841	/** Fixed temporary register. */
842	kIemNativeWhat_FixedTmp,
843	/** Register reserved by the CPU or OS architecture. */
844	kIemNativeWhat_FixedReserved,
845	/** End of valid values. */
846	kIemNativeWhat_End
847	} IEMNATIVEWHAT;
848
849	/**
850	* Host general register entry.
851	*
852	* The actual allocation status is kept in IEMRECOMPILERSTATE::bmHstRegs.
853	*
854	* @todo Track immediate values in host registers similarlly to how we track the
855	* guest register shadow copies. For it to be real helpful, though,
856	* we probably need to know which will be reused and put them into
857	* non-volatile registers, otherwise it's going to be more or less
858	* restricted to an instruction or two.
859	*/
860	typedef struct IEMNATIVEHSTREG
861	{
862	/** Set of guest registers this one shadows.
863	*
864	* Using a bitmap here so we can designate the same host register as a copy
865	* for more than one guest register. This is expected to be useful in
866	* situations where one value is copied to several registers in a sequence.
867	* If the mapping is 1:1, then we'd have to pick which side of a 'MOV SRC,DST'
868	* sequence we'd want to let this register follow to be a copy of and there
869	* will always be places where we'd be picking the wrong one.
870	*/
871	uint64_t fGstRegShadows;
872	/** What is being kept in this register. */
873	IEMNATIVEWHAT enmWhat;
874	/** Variable index if holding a variable, otherwise UINT8_MAX. */
875	uint8_t idxVar;
876	/** Stack slot assigned by iemNativeVarSaveVolatileRegsPreHlpCall and freed
877	* by iemNativeVarRestoreVolatileRegsPostHlpCall. This is not valid outside
878	* that scope. */
879	uint8_t idxStackSlot;
880	/** Alignment padding. */
881	uint8_t abAlign[5];
882	} IEMNATIVEHSTREG;
883
884
885	/**
886	* Core state for the native recompiler, that is, things that needs careful
887	* handling when dealing with branches.
888	*/
889	typedef struct IEMNATIVECORESTATE
890	{
891	/** Allocation bitmap for aHstRegs. */
892	uint32_t bmHstRegs;
893
894	/** Bitmap marking which host register contains guest register shadow copies.
895	* This is used during register allocation to try preserve copies. */
896	uint32_t bmHstRegsWithGstShadow;
897	/** Bitmap marking valid entries in aidxGstRegShadows. */
898	uint64_t bmGstRegShadows;
899
900	union
901	{
902	/** Index of variable arguments, UINT8_MAX if not valid. */
903	uint8_t aidxArgVars[8];
904	/** For more efficient resetting. */
905	uint64_t u64ArgVars;
906	};
907
908	/** Allocation bitmap for the stack. */
909	uint32_t bmStack;
910	/** Allocation bitmap for aVars. */
911	uint32_t bmVars;
912
913	/** Maps a guest register to a host GPR (index by IEMNATIVEGSTREG).
914	* Entries are only valid if the corresponding bit in bmGstRegShadows is set.
915	* (A shadow copy of a guest register can only be held in a one host register,
916	* there are no duplicate copies or ambiguities like that). */
917	uint8_t aidxGstRegShadows[kIemNativeGstReg_End];
918
919	/** Host register allocation tracking. */
920	IEMNATIVEHSTREG aHstRegs[IEMNATIVE_HST_GREG_COUNT];
921
922	/** Variables and arguments. */
923	IEMNATIVEVAR aVars[9];
924	} IEMNATIVECORESTATE;
925	/** Pointer to core state. */
926	typedef IEMNATIVECORESTATE *PIEMNATIVECORESTATE;
927	/** Pointer to const core state. */
928	typedef IEMNATIVECORESTATE const *PCIEMNATIVECORESTATE;
929
930
931	/**
932	* Conditional stack entry.
933	*/
934	typedef struct IEMNATIVECOND
935	{
936	/** Set if we're in the "else" part, clear if we're in the "if" before it. */
937	bool fInElse;
938	/** The label for the IEM_MC_ELSE. */
939	uint32_t idxLabelElse;
940	/** The label for the IEM_MC_ENDIF. */
941	uint32_t idxLabelEndIf;
942	/** The initial state snapshot as the if-block starts executing. */
943	IEMNATIVECORESTATE InitialState;
944	/** The state snapshot at the end of the if-block. */
945	IEMNATIVECORESTATE IfFinalState;
946	} IEMNATIVECOND;
947	/** Pointer to a condition stack entry. */
948	typedef IEMNATIVECOND *PIEMNATIVECOND;
949
950
951	/**
952	* Native recompiler state.
953	*/
954	typedef struct IEMRECOMPILERSTATE
955	{
956	/** Size of the buffer that pbNativeRecompileBufR3 points to in
957	* IEMNATIVEINSTR units. */
958	uint32_t cInstrBufAlloc;
959	#ifdef VBOX_STRICT
960	/** Strict: How far the last iemNativeInstrBufEnsure() checked. */
961	uint32_t offInstrBufChecked;
962	#else
963	uint32_t uPadding1; /* We don't keep track of the size here... */
964	#endif
965	/** Fixed temporary code buffer for native recompilation. */
966	PIEMNATIVEINSTR pInstrBuf;
967
968	/** Bitmaps with the label types used. */
969	uint64_t bmLabelTypes;
970	/** Actual number of labels in paLabels. */
971	uint32_t cLabels;
972	/** Max number of entries allowed in paLabels before reallocating it. */
973	uint32_t cLabelsAlloc;
974	/** Labels defined while recompiling (referenced by fixups). */
975	PIEMNATIVELABEL paLabels;
976	/** Array with indexes of unique labels (uData always 0). */
977	uint32_t aidxUniqueLabels[kIemNativeLabelType_FirstWithMultipleInstances];
978
979	/** Actual number of fixups paFixups. */
980	uint32_t cFixups;
981	/** Max number of entries allowed in paFixups before reallocating it. */
982	uint32_t cFixupsAlloc;
983	/** Buffer used by the recompiler for recording fixups when generating code. */
984	PIEMNATIVEFIXUP paFixups;
985
986	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
987	/** Number of debug info entries allocated for pDbgInfo. */
988	uint32_t cDbgInfoAlloc;
989	uint32_t uPadding;
990	/** Debug info. */
991	PIEMTBDBG pDbgInfo;
992	#endif
993
994	#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
995	/** The current call index (liveness array and threaded calls in TB). */
996	uint32_t idxCurCall;
997	/** Number of liveness entries allocated. */
998	uint32_t cLivenessEntriesAlloc;
999	/** Liveness entries for all the calls in the TB begin recompiled.
1000	* The entry for idxCurCall contains the info for what the next call will
1001	* require wrt registers. (Which means the last entry is the initial liveness
1002	* state.) */
1003	PIEMLIVENESSENTRY paLivenessEntries;
1004	#endif
1005
1006	/** The translation block being recompiled. */
1007	PCIEMTB pTbOrg;
1008	/** The VMCPU structure of the EMT. */
1009	PVMCPUCC pVCpu;
1010
1011	/** Condition sequence number (for generating unique labels). */
1012	uint16_t uCondSeqNo;
1013	/** Check IRQ seqeunce number (for generating unique labels). */
1014	uint16_t uCheckIrqSeqNo;
1015	/** TLB load sequence number (for generating unique labels). */
1016	uint16_t uTlbSeqNo;
1017	/** The current condition stack depth (aCondStack). */
1018	uint8_t cCondDepth;
1019
1020	/** The argument count + hidden regs from the IEM_MC_BEGIN statement. */
1021	uint8_t cArgs;
1022	/** The IEM_CIMPL_F_XXX flags from the IEM_MC_BEGIN statement. */
1023	uint32_t fCImpl;
1024	/** The IEM_MC_F_XXX flags from the IEM_MC_BEGIN statement. */
1025	uint32_t fMc;
1026	/** The expected IEMCPU::fExec value for the current call/instruction. */
1027	uint32_t fExec;
1028
1029	/** Core state requiring care with branches. */
1030	IEMNATIVECORESTATE Core;
1031
1032	/** The condition nesting stack. */
1033	IEMNATIVECOND aCondStack[2];
1034
1035	#ifndef IEM_WITH_THROW_CATCH
1036	/** Pointer to the setjmp/longjmp buffer if we're not using C++ exceptions
1037	* for recompilation error handling. */
1038	jmp_buf JmpBuf;
1039	#endif
1040	} IEMRECOMPILERSTATE;
1041	/** Pointer to a native recompiler state. */
1042	typedef IEMRECOMPILERSTATE *PIEMRECOMPILERSTATE;
1043
1044
1045	/** @def IEMNATIVE_TRY_SETJMP
1046	* Wrapper around setjmp / try, hiding all the ugly differences.
1047	*
1048	* @note Use with extreme care as this is a fragile macro.
1049	* @param a_pReNative The native recompile state.
1050	* @param a_rcTarget The variable that should receive the status code in case
1051	* of a longjmp/throw.
1052	*/
1053	/** @def IEMNATIVE_CATCH_LONGJMP_BEGIN
1054	* Start wrapper for catch / setjmp-else.
1055	*
1056	* This will set up a scope.
1057	*
1058	* @note Use with extreme care as this is a fragile macro.
1059	* @param a_pReNative The native recompile state.
1060	* @param a_rcTarget The variable that should receive the status code in case
1061	* of a longjmp/throw.
1062	*/
1063	/** @def IEMNATIVE_CATCH_LONGJMP_END
1064	* End wrapper for catch / setjmp-else.
1065	*
1066	* This will close the scope set up by IEMNATIVE_CATCH_LONGJMP_BEGIN and clean
1067	* up the state.
1068	*
1069	* @note Use with extreme care as this is a fragile macro.
1070	* @param a_pReNative The native recompile state.
1071	*/
1072	/** @def IEMNATIVE_DO_LONGJMP
1073	*
1074	* Wrapper around longjmp / throw.
1075	*
1076	* @param a_pReNative The native recompile state.
1077	* @param a_rc The status code jump back with / throw.
1078	*/
1079	#ifdef IEM_WITH_THROW_CATCH
1080	# define IEMNATIVE_TRY_SETJMP(a_pReNative, a_rcTarget) \
1081	a_rcTarget = VINF_SUCCESS; \
1082	try
1083	# define IEMNATIVE_CATCH_LONGJMP_BEGIN(a_pReNative, a_rcTarget) \
1084	catch (int rcThrown) \
1085	{ \
1086	a_rcTarget = rcThrown
1087	# define IEMNATIVE_CATCH_LONGJMP_END(a_pReNative) \
1088	} \
1089	((void)0)
1090	# define IEMNATIVE_DO_LONGJMP(a_pReNative, a_rc) throw int(a_rc)
1091	#else /* !IEM_WITH_THROW_CATCH */
1092	# define IEMNATIVE_TRY_SETJMP(a_pReNative, a_rcTarget) \
1093	if ((a_rcTarget = setjmp((a_pReNative)->JmpBuf)) == 0)
1094	# define IEMNATIVE_CATCH_LONGJMP_BEGIN(a_pReNative, a_rcTarget) \
1095	else \
1096	{ \
1097	((void)0)
1098	# define IEMNATIVE_CATCH_LONGJMP_END(a_pReNative) \
1099	}
1100	# define IEMNATIVE_DO_LONGJMP(a_pReNative, a_rc) longjmp((a_pReNative)->JmpBuf, (a_rc))
1101	#endif /* !IEM_WITH_THROW_CATCH */
1102
1103
1104	/**
1105	* Native recompiler worker for a threaded function.
1106	*
1107	* @returns New code buffer offset; throws VBox status code in case of a failure.
1108	* @param pReNative The native recompiler state.
1109	* @param off The current code buffer offset.
1110	* @param pCallEntry The threaded call entry.
1111	*
1112	* @note This may throw/longjmp VBox status codes (int) to abort compilation, so no RT_NOEXCEPT!
1113	*/
1114	typedef uint32_t (VBOXCALL FNIEMNATIVERECOMPFUNC)(PIEMRECOMPILERSTATE pReNative, uint32_t off, PCIEMTHRDEDCALLENTRY pCallEntry);
1115	/** Pointer to a native recompiler worker for a threaded function. */
1116	typedef FNIEMNATIVERECOMPFUNC *PFNIEMNATIVERECOMPFUNC;
1117
1118	/** Defines a native recompiler worker for a threaded function.
1119	* @see FNIEMNATIVERECOMPFUNC */
1120	#define IEM_DECL_IEMNATIVERECOMPFUNC_DEF(a_Name) \
1121	uint32_t VBOXCALL a_Name(PIEMRECOMPILERSTATE pReNative, uint32_t off, PCIEMTHRDEDCALLENTRY pCallEntry)
1122
1123	/** Prototypes a native recompiler function for a threaded function.
1124	* @see FNIEMNATIVERECOMPFUNC */
1125	#define IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(a_Name) FNIEMNATIVERECOMPFUNC a_Name
1126
1127
1128	/**
1129	* Native recompiler liveness analysis worker for a threaded function.
1130	*
1131	* @param pCallEntry The threaded call entry.
1132	* @param pIncoming The incoming liveness state entry.
1133	* @param pOutgoing The outgoing liveness state entry.
1134	*/
1135	typedef DECLCALLBACKTYPE(void, FNIEMNATIVELIVENESSFUNC, (PCIEMTHRDEDCALLENTRY pCallEntry,
1136	PCIEMLIVENESSENTRY pIncoming, PIEMLIVENESSENTRY pOutgoing));
1137	/** Pointer to a native recompiler liveness analysis worker for a threaded function. */
1138	typedef FNIEMNATIVELIVENESSFUNC *PFNIEMNATIVELIVENESSFUNC;
1139
1140	/** Defines a native recompiler liveness analysis worker for a threaded function.
1141	* @see FNIEMNATIVELIVENESSFUNC */
1142	#define IEM_DECL_IEMNATIVELIVENESSFUNC_DEF(a_Name) \
1143	DECLCALLBACK(void) a_Name(PCIEMTHRDEDCALLENTRY pCallEntry, PCIEMLIVENESSENTRY pIncoming, PIEMLIVENESSENTRY pOutgoing)
1144
1145	/** Prototypes a native recompiler liveness analysis function for a threaded function.
1146	* @see FNIEMNATIVELIVENESSFUNC */
1147	#define IEM_DECL_IEMNATIVELIVENESSFUNC_PROTO(a_Name) FNIEMNATIVELIVENESSFUNC a_Name
1148
1149
1150	/** Define a native recompiler helper function, safe to call from the TB code. */
1151	#define IEM_DECL_NATIVE_HLP_DEF(a_RetType, a_Name, a_ArgList) \
1152	DECL_HIDDEN_THROW(a_RetType) VBOXCALL a_Name a_ArgList
1153	/** Prototype a native recompiler helper function, safe to call from the TB code. */
1154	#define IEM_DECL_NATIVE_HLP_PROTO(a_RetType, a_Name, a_ArgList) \
1155	DECL_HIDDEN_THROW(a_RetType) VBOXCALL a_Name a_ArgList
1156
1157
1158	DECL_HIDDEN_THROW(uint32_t) iemNativeLabelCreate(PIEMRECOMPILERSTATE pReNative, IEMNATIVELABELTYPE enmType,
1159	uint32_t offWhere = UINT32_MAX, uint16_t uData = 0);
1160	DECL_HIDDEN_THROW(void) iemNativeLabelDefine(PIEMRECOMPILERSTATE pReNative, uint32_t idxLabel, uint32_t offWhere);
1161	DECL_HIDDEN_THROW(void) iemNativeAddFixup(PIEMRECOMPILERSTATE pReNative, uint32_t offWhere, uint32_t idxLabel,
1162	IEMNATIVEFIXUPTYPE enmType, int8_t offAddend = 0);
1163	DECL_HIDDEN_THROW(PIEMNATIVEINSTR) iemNativeInstrBufEnsureSlow(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t cInstrReq);
1164
1165	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmp(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, bool fPreferVolatile = true);
1166	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpEx(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint32_t fRegMask,
1167	bool fPreferVolatile = true);
1168	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpImm(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint64_t uImm,
1169	bool fPreferVolatile = true);
1170	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpForGuestReg(PIEMRECOMPILERSTATE pReNative, uint32_t *poff,
1171	IEMNATIVEGSTREG enmGstReg,
1172	IEMNATIVEGSTREGUSE enmIntendedUse = kIemNativeGstRegUse_ReadOnly,
1173	bool fNoVolatileRegs = false, bool fSkipLivenessAssert = false);
1174	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpForGuestRegIfAlreadyPresent(PIEMRECOMPILERSTATE pReNative, uint32_t *poff,
1175	IEMNATIVEGSTREG enmGstReg);
1176
1177	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocVar(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint8_t idxVar);
1178	DECL_HIDDEN_THROW(uint32_t) iemNativeRegAllocArgs(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs);
1179	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAssignRc(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg);
1180	DECLHIDDEN(void) iemNativeRegFree(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
1181	DECLHIDDEN(void) iemNativeRegFreeTmp(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
1182	DECLHIDDEN(void) iemNativeRegFreeTmpImm(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
1183	DECLHIDDEN(void) iemNativeRegFreeVar(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg, bool fFlushShadows) RT_NOEXCEPT;
1184	DECLHIDDEN(void) iemNativeRegFreeAndFlushMask(PIEMRECOMPILERSTATE pReNative, uint32_t fHstRegMask) RT_NOEXCEPT;
1185	DECL_HIDDEN_THROW(uint32_t) iemNativeRegFlushPendingWrites(PIEMRECOMPILERSTATE pReNative, uint32_t off);
1186	DECL_HIDDEN_THROW(uint32_t) iemNativeRegMoveAndFreeAndFlushAtCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs,
1187	uint32_t fKeepVars = 0);
1188	DECLHIDDEN(void) iemNativeRegFlushGuestShadows(PIEMRECOMPILERSTATE pReNative, uint64_t fGstRegs) RT_NOEXCEPT;
1189	DECLHIDDEN(void) iemNativeRegFlushGuestShadowsByHostMask(PIEMRECOMPILERSTATE pReNative, uint32_t fHstRegs) RT_NOEXCEPT;
1190	DECL_HIDDEN_THROW(uint32_t) iemNativeRegRestoreGuestShadowsInVolatileRegs(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1191	uint32_t fHstRegsActiveShadows);
1192
1193	DECL_HIDDEN_THROW(uint8_t) iemNativeVarGetStackSlot(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar);
1194	DECL_HIDDEN_THROW(uint8_t) iemNativeVarRegisterAcquire(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, uint32_t *poff,
1195	bool fInitialized = false, uint8_t idxRegPref = UINT8_MAX);
1196	DECL_HIDDEN_THROW(uint8_t) iemNativeVarRegisterAcquireForGuestReg(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar,
1197	IEMNATIVEGSTREG enmGstReg, uint32_t *poff);
1198	DECL_HIDDEN_THROW(uint32_t) iemNativeVarSaveVolatileRegsPreHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1199	uint32_t fHstRegsNotToSave);
1200	DECL_HIDDEN_THROW(uint32_t) iemNativeVarRestoreVolatileRegsPostHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1201	uint32_t fHstRegsNotToSave);
1202
1203	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitLoadGprWithGstShadowReg(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1204	uint8_t idxHstReg, IEMNATIVEGSTREG enmGstReg);
1205	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitCheckCallRetAndPassUp(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr);
1206	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitCImplCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr,
1207	uint64_t fGstShwFlush, uintptr_t pfnCImpl, uint8_t cbInstr, uint8_t cAddParams,
1208	uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
1209	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitThreadedCall(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1210	PCIEMTHRDEDCALLENTRY pCallEntry);
1211
1212	extern DECL_HIDDEN_DATA(const char * const) g_apszIemNativeHstRegNames[];
1213
1214
1215	/**
1216	* Ensures that there is sufficient space in the instruction output buffer.
1217	*
1218	* This will reallocate the buffer if needed and allowed.
1219	*
1220	* @note Always use IEMNATIVE_ASSERT_INSTR_BUF_ENSURE when done to check the
1221	* allocation size.
1222	*
1223	* @returns Pointer to the instruction output buffer on success; throws VBox
1224	* status code on failure, so no need to check it.
1225	* @param pReNative The native recompile state.
1226	* @param off Current instruction offset. Works safely for UINT32_MAX
1227	* as well.
1228	* @param cInstrReq Number of instruction about to be added. It's okay to
1229	* overestimate this a bit.
1230	*/
1231	DECL_FORCE_INLINE_THROW(PIEMNATIVEINSTR)
1232	iemNativeInstrBufEnsure(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t cInstrReq)
1233	{
1234	uint64_t const offChecked = off + (uint64_t)cInstrReq; /** @todo may reconsider the need for UINT32_MAX safety... */
1235	if (RT_LIKELY(offChecked <= pReNative->cInstrBufAlloc))
1236	{
1237	#ifdef VBOX_STRICT
1238	pReNative->offInstrBufChecked = offChecked;
1239	#endif
1240	return pReNative->pInstrBuf;
1241	}
1242	return iemNativeInstrBufEnsureSlow(pReNative, off, cInstrReq);
1243	}
1244
1245	/**
1246	* Checks that we didn't exceed the space requested in the last
1247	* iemNativeInstrBufEnsure() call.
1248	*/
1249	#define IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(a_pReNative, a_off) \
1250	AssertMsg((a_off) <= (a_pReNative)->offInstrBufChecked, \
1251	("off=%#x offInstrBufChecked=%#x\n", (a_off), (a_pReNative)->offInstrBufChecked))
1252
1253	/**
1254	* Checks that a variable index is valid.
1255	*/
1256	#define IEMNATIVE_ASSERT_VAR_IDX(a_pReNative, a_idxVar) \
1257	AssertMsg( (unsigned)(a_idxVar) < RT_ELEMENTS((a_pReNative)->Core.aVars) \
1258	&& ((a_pReNative)->Core.bmVars & RT_BIT_32(a_idxVar)), ("%s=%d\n", #a_idxVar, a_idxVar))
1259
1260	/**
1261	* Checks that a variable index is valid and that the variable is assigned the
1262	* correct argument number.
1263	* This also adds a RT_NOREF of a_idxVar.
1264	*/
1265	#define IEMNATIVE_ASSERT_ARG_VAR_IDX(a_pReNative, a_idxVar, a_uArgNo) do { \
1266	RT_NOREF_PV(a_idxVar); \
1267	AssertMsg( (unsigned)(a_idxVar) < RT_ELEMENTS((a_pReNative)->Core.aVars) \
1268	&& ((a_pReNative)->Core.bmVars & RT_BIT_32(a_idxVar))\
1269	&& (a_pReNative)->Core.aVars[a_idxVar].uArgNo == (a_uArgNo) \
1270	, ("%s=%d; uArgNo=%d, expected %u\n", #a_idxVar, a_idxVar, \
1271	(a_pReNative)->Core.aVars[RT_MAX(a_idxVar, RT_ELEMENTS((a_pReNative)->Core.aVars)) - 1].uArgNo, a_uArgNo)); \
1272	} while (0)
1273
1274	/**
1275	* Calculates the stack address of a variable as a [r]BP displacement value.
1276	*/
1277	DECL_FORCE_INLINE(int32_t)
1278	iemNativeStackCalcBpDisp(uint8_t idxStackSlot)
1279	{
1280	Assert(idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS);
1281	return idxStackSlot * sizeof(uint64_t) + IEMNATIVE_FP_OFF_STACK_VARS;
1282	}
1283
1284
1285	/**
1286	* Releases the variable's register.
1287	*
1288	* The register must have been previously acquired calling
1289	* iemNativeVarRegisterAcquire(), iemNativeVarRegisterAcquireForGuestReg() or
1290	* iemNativeVarRegisterSetAndAcquire().
1291	*/
1292	DECL_INLINE_THROW(void) iemNativeVarRegisterRelease(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar)
1293	{
1294	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
1295	Assert(pReNative->Core.aVars[idxVar].fRegAcquired);
1296	pReNative->Core.aVars[idxVar].fRegAcquired = false;
1297	}
1298
1299	/** @} */
1300
1301	#endif /* !VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h */
1302

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