IEMN8veRecompiler.h@ 104386

Last change on this file since 104386 was 104383, checked in by vboxsync, 8 months ago
VMM/IEM: Automtically convert IEMInternal.h & IEMN8veRecompiler.h into nasm/yasm include files so IEMAllN8veHlpA.asm can make use of some of the constants define in them for the prolog code. [doxygen] bugref:10653 bugref:10370
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1	/* $Id: IEMN8veRecompiler.h 104383 2024-04-19 20:00:51Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager - Native Recompiler Internals.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h
29	#define VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34
35	/** @defgroup grp_iem_n8ve_re Native Recompiler Internals.
36	* @ingroup grp_iem_int
37	* @{
38	*/
39
40	#include <iprt/assertcompile.h> /* for RT_IN_ASSEMBLER mode */
41
42	/** @def IEMNATIVE_WITH_TB_DEBUG_INFO
43	* Enables generating internal debug info for better TB disassembly dumping. */
44	#if defined(DEBUG) \|\| defined(DOXYGEN_RUNNING)
45	# define IEMNATIVE_WITH_TB_DEBUG_INFO
46	#endif
47
48	/** @def IEMNATIVE_WITH_LIVENESS_ANALYSIS
49	* Enables liveness analysis. */
50	#if 1 \|\| defined(DOXYGEN_RUNNING)
51	# define IEMNATIVE_WITH_LIVENESS_ANALYSIS
52	/# define IEMLIVENESS_EXTENDED_LAYOUT/
53	#endif
54
55	/** @def IEMNATIVE_WITH_EFLAGS_SKIPPING
56	* Enables skipping EFLAGS calculations/updating based on liveness info. */
57	#if defined(IEMNATIVE_WITH_LIVENESS_ANALYSIS) \|\| defined(DOXYGEN_RUNNING)
58	# define IEMNATIVE_WITH_EFLAGS_SKIPPING
59	#endif
60
61
62	/** @def IEMNATIVE_STRICT_EFLAGS_SKIPPING
63	* Enables strict consistency checks around EFLAGS skipping.
64	* @note Only defined when IEMNATIVE_WITH_EFLAGS_SKIPPING is also defined. */
65	#ifdef IEMNATIVE_WITH_EFLAGS_SKIPPING
66	# ifdef VBOX_STRICT
67	# define IEMNATIVE_STRICT_EFLAGS_SKIPPING
68	# endif
69	#elif defined(DOXYGEN_RUNNING)
70	# define IEMNATIVE_STRICT_EFLAGS_SKIPPING
71	#endif
72
73	#ifdef VBOX_WITH_STATISTICS
74	/** Always count instructions for now. */
75	# define IEMNATIVE_WITH_INSTRUCTION_COUNTING
76	#endif
77
78	/** @def IEMNATIVE_WITH_RECOMPILER_PROLOGUE_SINGLETON
79	* Enables having only a single prologue for native TBs. */
80	#if 1 \|\| defined(DOXYGEN_RUNNING)
81	# define IEMNATIVE_WITH_RECOMPILER_PROLOGUE_SINGLETON
82	#endif
83
84
85	/** @name Stack Frame Layout
86	*
87	* @{ */
88	/** The size of the area for stack variables and spills and stuff.
89	* @note This limit is duplicated in the python script(s). We add 0x40 for
90	* alignment padding. */
91	#define IEMNATIVE_FRAME_VAR_SIZE (0xc0 + 0x40)
92	/** Number of 64-bit variable slots (0x100 / 8 = 32. */
93	#define IEMNATIVE_FRAME_VAR_SLOTS (IEMNATIVE_FRAME_VAR_SIZE / 8)
94	AssertCompile(IEMNATIVE_FRAME_VAR_SLOTS == 32);
95
96	#ifdef RT_ARCH_AMD64
97	/** An stack alignment adjustment (between non-volatile register pushes and
98	* the stack variable area, so the latter better aligned). */
99	# define IEMNATIVE_FRAME_ALIGN_SIZE 8
100
101	/** Number of stack arguments slots for calls made from the frame. */
102	# ifdef RT_OS_WINDOWS
103	# define IEMNATIVE_FRAME_STACK_ARG_COUNT 4
104	# else
105	# define IEMNATIVE_FRAME_STACK_ARG_COUNT 2
106	# endif
107	/** Number of any shadow arguments (spill area) for calls we make. */
108	# ifdef RT_OS_WINDOWS
109	# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 4
110	# else
111	# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 0
112	# endif
113
114	/** Frame pointer (RBP) relative offset of the last push. */
115	# ifdef RT_OS_WINDOWS
116	# define IEMNATIVE_FP_OFF_LAST_PUSH (7 * -8)
117	# else
118	# define IEMNATIVE_FP_OFF_LAST_PUSH (5 * -8)
119	# endif
120	/** Frame pointer (RBP) relative offset of the stack variable area (the lowest
121	* address for it). */
122	# define IEMNATIVE_FP_OFF_STACK_VARS (IEMNATIVE_FP_OFF_LAST_PUSH - IEMNATIVE_FRAME_ALIGN_SIZE - IEMNATIVE_FRAME_VAR_SIZE)
123	/** Frame pointer (RBP) relative offset of the first stack argument for calls. */
124	# define IEMNATIVE_FP_OFF_STACK_ARG0 (IEMNATIVE_FP_OFF_STACK_VARS - IEMNATIVE_FRAME_STACK_ARG_COUNT * 8)
125	/** Frame pointer (RBP) relative offset of the second stack argument for calls. */
126	# define IEMNATIVE_FP_OFF_STACK_ARG1 (IEMNATIVE_FP_OFF_STACK_ARG0 + 8)
127	# ifdef RT_OS_WINDOWS
128	/** Frame pointer (RBP) relative offset of the third stack argument for calls. */
129	# define IEMNATIVE_FP_OFF_STACK_ARG2 (IEMNATIVE_FP_OFF_STACK_ARG0 + 16)
130	/** Frame pointer (RBP) relative offset of the fourth stack argument for calls. */
131	# define IEMNATIVE_FP_OFF_STACK_ARG3 (IEMNATIVE_FP_OFF_STACK_ARG0 + 24)
132	# endif
133
134	# ifdef RT_OS_WINDOWS
135	/** Frame pointer (RBP) relative offset of the first incoming shadow argument. */
136	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG0 (16)
137	/** Frame pointer (RBP) relative offset of the second incoming shadow argument. */
138	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG1 (24)
139	/** Frame pointer (RBP) relative offset of the third incoming shadow argument. */
140	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG2 (32)
141	/** Frame pointer (RBP) relative offset of the fourth incoming shadow argument. */
142	# define IEMNATIVE_FP_OFF_IN_SHADOW_ARG3 (40)
143	# endif
144
145	#elif RT_ARCH_ARM64
146	/** No alignment padding needed for arm64. */
147	# define IEMNATIVE_FRAME_ALIGN_SIZE 0
148	/** No stack argument slots, got 8 registers for arguments will suffice. */
149	# define IEMNATIVE_FRAME_STACK_ARG_COUNT 0
150	/** There are no argument spill area. */
151	# define IEMNATIVE_FRAME_SHADOW_ARG_COUNT 0
152
153	/** Number of saved registers at the top of our stack frame.
154	* This includes the return address and old frame pointer, so x19 thru x30. */
155	# define IEMNATIVE_FRAME_SAVE_REG_COUNT (12)
156	/** The size of the save registered (IEMNATIVE_FRAME_SAVE_REG_COUNT). */
157	# define IEMNATIVE_FRAME_SAVE_REG_SIZE (IEMNATIVE_FRAME_SAVE_REG_COUNT * 8)
158
159	/** Frame pointer (BP) relative offset of the last push. */
160	# define IEMNATIVE_FP_OFF_LAST_PUSH (10 * -8)
161
162	/** Frame pointer (BP) relative offset of the stack variable area (the lowest
163	* address for it). */
164	# define IEMNATIVE_FP_OFF_STACK_VARS (IEMNATIVE_FP_OFF_LAST_PUSH - IEMNATIVE_FRAME_ALIGN_SIZE - IEMNATIVE_FRAME_VAR_SIZE)
165
166	#else
167	# error "port me"
168	#endif
169	/** @} */
170
171
172	/** @name Fixed Register Allocation(s)
173	* @{ */
174	/** @def IEMNATIVE_REG_FIXED_PVMCPU
175	* The number of the register holding the pVCpu pointer. */
176	/** @def IEMNATIVE_REG_FIXED_PCPUMCTX
177	* The number of the register holding the &pVCpu->cpum.GstCtx pointer.
178	* @note This not available on AMD64, only ARM64. */
179	/** @def IEMNATIVE_REG_FIXED_TMP0
180	* Dedicated temporary register.
181	* @todo replace this by a register allocator and content tracker. */
182	/** @def IEMNATIVE_REG_FIXED_MASK
183	* Mask GPRs with fixes assignments, either by us or dictated by the CPU/OS
184	* architecture. */
185	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
186	/** @def IEMNATIVE_SIMD_REG_FIXED_TMP0
187	* Mask SIMD registers with fixes assignments, either by us or dictated by the CPU/OS
188	* architecture. */
189	/** @def IEMNATIVE_SIMD_REG_FIXED_TMP0
190	* Dedicated temporary SIMD register. */
191	#endif
192	#if defined(RT_ARCH_ARM64) \|\| defined(DOXYGEN_RUNNING) /* arm64 goes first because of doxygen */
193	# define IEMNATIVE_REG_FIXED_PVMCPU ARMV8_A64_REG_X28
194	# define IEMNATIVE_REG_FIXED_PVMCPU_ASM RT_CONCAT(x,IEMNATIVE_REG_FIXED_PVMCPU)
195	# define IEMNATIVE_REG_FIXED_PCPUMCTX ARMV8_A64_REG_X27
196	# define IEMNATIVE_REG_FIXED_PCPUMCTX_ASM RT_CONCAT(x,IEMNATIVE_REG_FIXED_PCPUMCTX)
197	# define IEMNATIVE_REG_FIXED_TMP0 ARMV8_A64_REG_X15
198	# if defined(IEMNATIVE_WITH_DELAYED_PC_UPDATING) && 0 /* debug the updating with a shadow RIP. */
199	# define IEMNATIVE_REG_FIXED_TMP1 ARMV8_A64_REG_X16
200	# define IEMNATIVE_REG_FIXED_PC_DBG ARMV8_A64_REG_X26
201	# define IEMNATIVE_REG_FIXED_MASK_ADD ( RT_BIT_32(IEMNATIVE_REG_FIXED_TMP1) \
202	\| RT_BIT_32(IEMNATIVE_REG_FIXED_PC_DBG))
203	# else
204	# define IEMNATIVE_REG_FIXED_MASK_ADD 0
205	# endif
206	# define IEMNATIVE_REG_FIXED_MASK ( RT_BIT_32(ARMV8_A64_REG_SP) \
207	\| RT_BIT_32(ARMV8_A64_REG_LR) \
208	\| RT_BIT_32(ARMV8_A64_REG_BP) \
209	\| RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU) \
210	\| RT_BIT_32(IEMNATIVE_REG_FIXED_PCPUMCTX) \
211	\| RT_BIT_32(ARMV8_A64_REG_X18) \
212	\| RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0) \
213	\| IEMNATIVE_REG_FIXED_MASK_ADD)
214
215	# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
216	# define IEMNATIVE_SIMD_REG_FIXED_TMP0 ARMV8_A64_REG_Q30
217	# if defined(IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS)
218	# define IEMNATIVE_SIMD_REG_FIXED_MASK RT_BIT_32(ARMV8_A64_REG_Q30)
219	# else
220	/** @note
221	* ARM64 has 32 registers, but they are only 128-bit wide. So, in order to
222	* support emulating 256-bit registers we pair two real registers statically to
223	* one virtual for now, leaving us with only 16 256-bit registers. We always
224	* pair v0 with v1, v2 with v3, etc. so we mark the higher register as fixed and
225	* the register allocator assumes that it will be always free when the lower is
226	* picked.
227	*
228	* Also ARM64 declares the low 64-bit of v8-v15 as callee saved, so we don't
229	* touch them in order to avoid having to save and restore them in the
230	* prologue/epilogue.
231	*/
232	# define IEMNATIVE_SIMD_REG_FIXED_MASK ( UINT32_C(0xff00) \
233	\| RT_BIT_32(ARMV8_A64_REG_Q31) \
234	\| RT_BIT_32(ARMV8_A64_REG_Q30) \
235	\| RT_BIT_32(ARMV8_A64_REG_Q29) \
236	\| RT_BIT_32(ARMV8_A64_REG_Q27) \
237	\| RT_BIT_32(ARMV8_A64_REG_Q25) \
238	\| RT_BIT_32(ARMV8_A64_REG_Q23) \
239	\| RT_BIT_32(ARMV8_A64_REG_Q21) \
240	\| RT_BIT_32(ARMV8_A64_REG_Q19) \
241	\| RT_BIT_32(ARMV8_A64_REG_Q17) \
242	\| RT_BIT_32(ARMV8_A64_REG_Q15) \
243	\| RT_BIT_32(ARMV8_A64_REG_Q13) \
244	\| RT_BIT_32(ARMV8_A64_REG_Q11) \
245	\| RT_BIT_32(ARMV8_A64_REG_Q9) \
246	\| RT_BIT_32(ARMV8_A64_REG_Q7) \
247	\| RT_BIT_32(ARMV8_A64_REG_Q5) \
248	\| RT_BIT_32(ARMV8_A64_REG_Q3) \
249	\| RT_BIT_32(ARMV8_A64_REG_Q1))
250	# endif
251	# endif
252
253	#elif defined(RT_ARCH_AMD64)
254	# define IEMNATIVE_REG_FIXED_PVMCPU X86_GREG_xBX
255	# define IEMNATIVE_REG_FIXED_PVMCPU_ASM xBX
256	# define IEMNATIVE_REG_FIXED_TMP0 X86_GREG_x11
257	# define IEMNATIVE_REG_FIXED_MASK ( RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU) \
258	\| RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0) \
259	\| RT_BIT_32(X86_GREG_xSP) \
260	\| RT_BIT_32(X86_GREG_xBP) )
261
262	# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
263	# define IEMNATIVE_SIMD_REG_FIXED_TMP0 5 /* xmm5/ymm5 */
264	# ifndef IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
265	# ifndef _MSC_VER
266	# define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
267	# endif
268	# endif
269	# ifdef IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS
270	# define IEMNATIVE_SIMD_REG_FIXED_MASK (RT_BIT_32(IEMNATIVE_SIMD_REG_FIXED_TMP0))
271	# else
272	/** @note On Windows/AMD64 xmm6 through xmm15 are marked as callee saved. */
273	# define IEMNATIVE_SIMD_REG_FIXED_MASK ( UINT32_C(0xffc0) \
274	\| RT_BIT_32(IEMNATIVE_SIMD_REG_FIXED_TMP0))
275	# endif
276	# endif
277
278	#else
279	# error "port me"
280	#endif
281	/** @} */
282
283	/** @name Call related registers.
284	* @{ */
285	/** @def IEMNATIVE_CALL_RET_GREG
286	* The return value register. */
287	/** @def IEMNATIVE_CALL_ARG_GREG_COUNT
288	* Number of arguments in registers. */
289	/** @def IEMNATIVE_CALL_ARG0_GREG
290	* The general purpose register carrying argument \#0. */
291	/** @def IEMNATIVE_CALL_ARG1_GREG
292	* The general purpose register carrying argument \#1. */
293	/** @def IEMNATIVE_CALL_ARG2_GREG
294	* The general purpose register carrying argument \#2. */
295	/** @def IEMNATIVE_CALL_ARG3_GREG
296	* The general purpose register carrying argument \#3. */
297	/** @def IEMNATIVE_CALL_VOLATILE_GREG_MASK
298	* Mask of registers the callee will not save and may trash. */
299	#ifdef RT_ARCH_AMD64
300	# define IEMNATIVE_CALL_RET_GREG X86_GREG_xAX
301
302	# ifdef RT_OS_WINDOWS
303	# define IEMNATIVE_CALL_ARG_GREG_COUNT 4
304	# define IEMNATIVE_CALL_ARG0_GREG X86_GREG_xCX
305	# define IEMNATIVE_CALL_ARG1_GREG X86_GREG_xDX
306	# define IEMNATIVE_CALL_ARG2_GREG X86_GREG_x8
307	# define IEMNATIVE_CALL_ARG3_GREG X86_GREG_x9
308	# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \
309	\| RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \
310	\| RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG) \
311	\| RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) )
312	# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(X86_GREG_xAX) \
313	\| RT_BIT_32(X86_GREG_xCX) \
314	\| RT_BIT_32(X86_GREG_xDX) \
315	\| RT_BIT_32(X86_GREG_x8) \
316	\| RT_BIT_32(X86_GREG_x9) \
317	\| RT_BIT_32(X86_GREG_x10) \
318	\| RT_BIT_32(X86_GREG_x11) )
319	# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
320	/* xmm0 - xmm5 are marked as volatile. */
321	# define IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK (UINT32_C(0x3f))
322	# endif
323
324	# else /* !RT_OS_WINDOWS */
325	# define IEMNATIVE_CALL_ARG_GREG_COUNT 6
326	# define IEMNATIVE_CALL_ARG0_GREG X86_GREG_xDI
327	# define IEMNATIVE_CALL_ARG1_GREG X86_GREG_xSI
328	# define IEMNATIVE_CALL_ARG2_GREG X86_GREG_xDX
329	# define IEMNATIVE_CALL_ARG3_GREG X86_GREG_xCX
330	# define IEMNATIVE_CALL_ARG4_GREG X86_GREG_x8
331	# define IEMNATIVE_CALL_ARG5_GREG X86_GREG_x9
332	# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(IEMNATIVE_CALL_ARG0_GREG) \
333	\| RT_BIT_32(IEMNATIVE_CALL_ARG1_GREG) \
334	\| RT_BIT_32(IEMNATIVE_CALL_ARG2_GREG) \
335	\| RT_BIT_32(IEMNATIVE_CALL_ARG3_GREG) \
336	\| RT_BIT_32(IEMNATIVE_CALL_ARG4_GREG) \
337	\| RT_BIT_32(IEMNATIVE_CALL_ARG5_GREG) )
338	# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(X86_GREG_xAX) \
339	\| RT_BIT_32(X86_GREG_xCX) \
340	\| RT_BIT_32(X86_GREG_xDX) \
341	\| RT_BIT_32(X86_GREG_xDI) \
342	\| RT_BIT_32(X86_GREG_xSI) \
343	\| RT_BIT_32(X86_GREG_x8) \
344	\| RT_BIT_32(X86_GREG_x9) \
345	\| RT_BIT_32(X86_GREG_x10) \
346	\| RT_BIT_32(X86_GREG_x11) )
347	# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
348	/* xmm0 - xmm15 are marked as volatile. */
349	# define IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK (UINT32_C(0xffff))
350	# endif
351	# endif /* !RT_OS_WINDOWS */
352
353	#elif defined(RT_ARCH_ARM64)
354	# define IEMNATIVE_CALL_RET_GREG ARMV8_A64_REG_X0
355	# define IEMNATIVE_CALL_ARG_GREG_COUNT 8
356	# define IEMNATIVE_CALL_ARG0_GREG ARMV8_A64_REG_X0
357	# define IEMNATIVE_CALL_ARG1_GREG ARMV8_A64_REG_X1
358	# define IEMNATIVE_CALL_ARG2_GREG ARMV8_A64_REG_X2
359	# define IEMNATIVE_CALL_ARG3_GREG ARMV8_A64_REG_X3
360	# define IEMNATIVE_CALL_ARG4_GREG ARMV8_A64_REG_X4
361	# define IEMNATIVE_CALL_ARG5_GREG ARMV8_A64_REG_X5
362	# define IEMNATIVE_CALL_ARG6_GREG ARMV8_A64_REG_X6
363	# define IEMNATIVE_CALL_ARG7_GREG ARMV8_A64_REG_X7
364	# define IEMNATIVE_CALL_ARGS_GREG_MASK ( RT_BIT_32(ARMV8_A64_REG_X0) \
365	\| RT_BIT_32(ARMV8_A64_REG_X1) \
366	\| RT_BIT_32(ARMV8_A64_REG_X2) \
367	\| RT_BIT_32(ARMV8_A64_REG_X3) \
368	\| RT_BIT_32(ARMV8_A64_REG_X4) \
369	\| RT_BIT_32(ARMV8_A64_REG_X5) \
370	\| RT_BIT_32(ARMV8_A64_REG_X6) \
371	\| RT_BIT_32(ARMV8_A64_REG_X7) )
372	# define IEMNATIVE_CALL_VOLATILE_GREG_MASK ( RT_BIT_32(ARMV8_A64_REG_X0) \
373	\| RT_BIT_32(ARMV8_A64_REG_X1) \
374	\| RT_BIT_32(ARMV8_A64_REG_X2) \
375	\| RT_BIT_32(ARMV8_A64_REG_X3) \
376	\| RT_BIT_32(ARMV8_A64_REG_X4) \
377	\| RT_BIT_32(ARMV8_A64_REG_X5) \
378	\| RT_BIT_32(ARMV8_A64_REG_X6) \
379	\| RT_BIT_32(ARMV8_A64_REG_X7) \
380	\| RT_BIT_32(ARMV8_A64_REG_X8) \
381	\| RT_BIT_32(ARMV8_A64_REG_X9) \
382	\| RT_BIT_32(ARMV8_A64_REG_X10) \
383	\| RT_BIT_32(ARMV8_A64_REG_X11) \
384	\| RT_BIT_32(ARMV8_A64_REG_X12) \
385	\| RT_BIT_32(ARMV8_A64_REG_X13) \
386	\| RT_BIT_32(ARMV8_A64_REG_X14) \
387	\| RT_BIT_32(ARMV8_A64_REG_X15) \
388	\| RT_BIT_32(ARMV8_A64_REG_X16) \
389	\| RT_BIT_32(ARMV8_A64_REG_X17) )
390	# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
391	/* The low 64 bits of v8 - v15 marked as callee saved but the rest is volatile,
392	* so to simplify our life a bit we just mark everything as volatile. */
393	# define IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK (UINT32_C(0xffffffff))
394	# endif
395
396	#endif
397
398	/** This is the maximum argument count we'll ever be needing. */
399	#define IEMNATIVE_CALL_MAX_ARG_COUNT 7
400	#ifdef RT_OS_WINDOWS
401	# ifdef VBOXSTRICTRC_STRICT_ENABLED
402	# undef IEMNATIVE_CALL_MAX_ARG_COUNT
403	# define IEMNATIVE_CALL_MAX_ARG_COUNT 8
404	# endif
405	#endif
406	/** @} */
407
408
409	/** @def IEMNATIVE_HST_GREG_COUNT
410	* Number of host general purpose registers we tracker. */
411	/** @def IEMNATIVE_HST_GREG_MASK
412	* Mask corresponding to IEMNATIVE_HST_GREG_COUNT that can be applied to
413	* inverted register masks and such to get down to a correct set of regs. */
414	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
415	/** @def IEMNATIVE_HST_SIMD_REG_COUNT
416	* Number of host SIMD registers we track. */
417	/** @def IEMNATIVE_HST_SIMD_REG_MASK
418	* Mask corresponding to IEMNATIVE_HST_SIMD_REG_COUNT that can be applied to
419	* inverted register masks and such to get down to a correct set of regs. */
420	#endif
421	#ifdef RT_ARCH_AMD64
422	# define IEMNATIVE_HST_GREG_COUNT 16
423	# define IEMNATIVE_HST_GREG_MASK UINT32_C(0xffff)
424
425	# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
426	# define IEMNATIVE_HST_SIMD_REG_COUNT 16
427	# define IEMNATIVE_HST_SIMD_REG_MASK UINT32_C(0xffff)
428	# endif
429
430	#elif defined(RT_ARCH_ARM64)
431	# define IEMNATIVE_HST_GREG_COUNT 32
432	# define IEMNATIVE_HST_GREG_MASK UINT32_MAX
433
434	# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
435	# define IEMNATIVE_HST_SIMD_REG_COUNT 32
436	# define IEMNATIVE_HST_SIMD_REG_MASK UINT32_MAX
437	# endif
438
439	#else
440	# error "Port me!"
441	#endif
442
443
444	#ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */
445
446
447	/** Native code generator label types. */
448	typedef enum
449	{
450	kIemNativeLabelType_Invalid = 0,
451	/*
452	* Labels w/o data, only once instance per TB.
453	*
454	* Note! Jumps to these requires instructions that are capable of spanning
455	* the max TB length.
456	*/
457	/* Simple labels comes first for indexing reasons. RaiseXx is order by the exception's numerical value(s). */
458	kIemNativeLabelType_RaiseDe, /*< Raise (throw) X86_XCPT_DE (00h). /
459	kIemNativeLabelType_RaiseUd, /*< Raise (throw) X86_XCPT_UD (06h). /
460	kIemNativeLabelType_RaiseSseRelated, /*< Raise (throw) X86_XCPT_UD or X86_XCPT_NM according to cr0 & cr4. /
461	kIemNativeLabelType_RaiseAvxRelated, /*< Raise (throw) X86_XCPT_UD or X86_XCPT_NM according to xcr0, cr0 & cr4. /
462	kIemNativeLabelType_RaiseSseAvxFpRelated, /*< Raise (throw) X86_XCPT_UD or X86_XCPT_XF according to c4. /
463	kIemNativeLabelType_RaiseNm, /*< Raise (throw) X86_XCPT_NM (07h). /
464	kIemNativeLabelType_RaiseGp0, /*< Raise (throw) X86_XCPT_GP (0dh) w/ errcd=0. /
465	kIemNativeLabelType_RaiseMf, /*< Raise (throw) X86_XCPT_MF (10h). /
466	kIemNativeLabelType_RaiseXf, /*< Raise (throw) X86_XCPT_XF (13h). /
467	kIemNativeLabelType_ObsoleteTb,
468	kIemNativeLabelType_NeedCsLimChecking,
469	kIemNativeLabelType_CheckBranchMiss,
470	kIemNativeLabelType_LastSimple = kIemNativeLabelType_CheckBranchMiss,
471	/* Manually defined labels. */
472	kIemNativeLabelType_Return,
473	kIemNativeLabelType_ReturnBreak,
474	kIemNativeLabelType_ReturnWithFlags,
475	kIemNativeLabelType_NonZeroRetOrPassUp,
476	/** The last fixup for branches that can span almost the whole TB length. */
477	kIemNativeLabelType_LastWholeTbBranch = kIemNativeLabelType_NonZeroRetOrPassUp,
478
479	/*
480	* Labels with data, potentially multiple instances per TB:
481	*
482	* These are localized labels, so no fixed jump type restrictions here.
483	*/
484	kIemNativeLabelType_FirstWithMultipleInstances,
485	kIemNativeLabelType_If = kIemNativeLabelType_FirstWithMultipleInstances,
486	kIemNativeLabelType_Else,
487	kIemNativeLabelType_Endif,
488	kIemNativeLabelType_CheckIrq,
489	kIemNativeLabelType_TlbLookup,
490	kIemNativeLabelType_TlbMiss,
491	kIemNativeLabelType_TlbDone,
492	kIemNativeLabelType_End
493	} IEMNATIVELABELTYPE;
494
495	/** Native code generator label definition. */
496	typedef struct IEMNATIVELABEL
497	{
498	/** Code offset if defined, UINT32_MAX if it needs to be generated after/in
499	* the epilog. */
500	uint32_t off;
501	/** The type of label (IEMNATIVELABELTYPE). */
502	uint16_t enmType;
503	/** Additional label data, type specific. */
504	uint16_t uData;
505	} IEMNATIVELABEL;
506	/** Pointer to a label. */
507	typedef IEMNATIVELABEL *PIEMNATIVELABEL;
508
509
510	/** Native code generator fixup types. */
511	typedef enum
512	{
513	kIemNativeFixupType_Invalid = 0,
514	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
515	/** AMD64 fixup: PC relative 32-bit with addend in bData. */
516	kIemNativeFixupType_Rel32,
517	#elif defined(RT_ARCH_ARM64)
518	/** ARM64 fixup: PC relative offset at bits 25:0 (B, BL). */
519	kIemNativeFixupType_RelImm26At0,
520	/** ARM64 fixup: PC relative offset at bits 23:5 (CBZ, CBNZ, B.CC). */
521	kIemNativeFixupType_RelImm19At5,
522	/** ARM64 fixup: PC relative offset at bits 18:5 (TBZ, TBNZ). */
523	kIemNativeFixupType_RelImm14At5,
524	#endif
525	kIemNativeFixupType_End
526	} IEMNATIVEFIXUPTYPE;
527
528	/** Native code generator fixup. */
529	typedef struct IEMNATIVEFIXUP
530	{
531	/** Code offset of the fixup location. */
532	uint32_t off;
533	/** The IEMNATIVELABEL this is a fixup for. */
534	uint16_t idxLabel;
535	/** The fixup type (IEMNATIVEFIXUPTYPE). */
536	uint8_t enmType;
537	/** Addend or other data. */
538	int8_t offAddend;
539	} IEMNATIVEFIXUP;
540	/** Pointer to a native code generator fixup. */
541	typedef IEMNATIVEFIXUP *PIEMNATIVEFIXUP;
542
543
544	/**
545	* One bit of the state.
546	*
547	* Each register state takes up two bits. We keep the two bits in two separate
548	* 64-bit words to simplify applying them to the guest shadow register mask in
549	* the register allocator.
550	*/
551	typedef union IEMLIVENESSBIT
552	{
553	uint64_t bm64;
554	RT_GCC_EXTENSION struct
555	{ /* bit no */
556	uint64_t bmGprs : 16; /*< 0x00 / 0: The 16 general purpose registers. /
557	uint64_t fUnusedPc : 1; /*< 0x10 / 16: (PC in ) /
558	uint64_t fCr0 : 1; /*< 0x11 / 17: /
559	uint64_t fFcw : 1; /*< 0x12 / 18: /
560	uint64_t fFsw : 1; /*< 0x13 / 19: /
561	uint64_t bmSegBase : 6; /*< 0x14 / 20: /
562	uint64_t bmSegAttrib : 6; /*< 0x1a / 26: /
563	uint64_t bmSegLimit : 6; /*< 0x20 / 32: /
564	uint64_t bmSegSel : 6; /*< 0x26 / 38: /
565	uint64_t fCr4 : 1; /*< 0x2c / 44: /
566	uint64_t fXcr0 : 1; /*< 0x2d / 45: /
567	uint64_t fMxCsr : 1; /*< 0x2e / 46: /
568	uint64_t fEflOther : 1; /*< 0x2f / 47: Other EFLAGS bits (~X86_EFL_STATUS_BITS & X86_EFL_LIVE_MASK). First! /
569	uint64_t fEflCf : 1; /*< 0x30 / 48: Carry flag (X86_EFL_CF / 0). /
570	uint64_t fEflPf : 1; /*< 0x31 / 49: Parity flag (X86_EFL_PF / 2). /
571	uint64_t fEflAf : 1; /*< 0x32 / 50: Auxilary carry flag (X86_EFL_AF / 4). /
572	uint64_t fEflZf : 1; /*< 0x33 / 51: Zero flag (X86_EFL_ZF / 6). /
573	uint64_t fEflSf : 1; /*< 0x34 / 52: Signed flag (X86_EFL_SF / 7). /
574	uint64_t fEflOf : 1; /*< 0x35 / 53: Overflow flag (X86_EFL_OF / 12). /
575	uint64_t uUnused : 10; /* 0x36 / 54 -> 0x40/64 */
576	};
577	} IEMLIVENESSBIT;
578	AssertCompileSize(IEMLIVENESSBIT, 8);
579
580	#define IEMLIVENESSBIT_IDX_EFL_OTHER ((unsigned)kIemNativeGstReg_EFlags + 0)
581	#define IEMLIVENESSBIT_IDX_EFL_CF ((unsigned)kIemNativeGstReg_EFlags + 1)
582	#define IEMLIVENESSBIT_IDX_EFL_PF ((unsigned)kIemNativeGstReg_EFlags + 2)
583	#define IEMLIVENESSBIT_IDX_EFL_AF ((unsigned)kIemNativeGstReg_EFlags + 3)
584	#define IEMLIVENESSBIT_IDX_EFL_ZF ((unsigned)kIemNativeGstReg_EFlags + 4)
585	#define IEMLIVENESSBIT_IDX_EFL_SF ((unsigned)kIemNativeGstReg_EFlags + 5)
586	#define IEMLIVENESSBIT_IDX_EFL_OF ((unsigned)kIemNativeGstReg_EFlags + 6)
587
588
589	/**
590	* A liveness state entry.
591	*
592	* The first 128 bits runs parallel to kIemNativeGstReg_xxx for the most part.
593	* Once we add a SSE register shadowing, we'll add another 64-bit element for
594	* that.
595	*/
596	typedef union IEMLIVENESSENTRY
597	{
598	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
599	uint64_t bm64[16 / 8];
600	uint16_t bm32[16 / 4];
601	uint16_t bm16[16 / 2];
602	uint8_t bm8[ 16 / 1];
603	IEMLIVENESSBIT aBits[2];
604	#else
605	uint64_t bm64[32 / 8];
606	uint16_t bm32[32 / 4];
607	uint16_t bm16[32 / 2];
608	uint8_t bm8[ 32 / 1];
609	IEMLIVENESSBIT aBits[4];
610	#endif
611	RT_GCC_EXTENSION struct
612	{
613	/** Bit \#0 of the register states. */
614	IEMLIVENESSBIT Bit0;
615	/** Bit \#1 of the register states. */
616	IEMLIVENESSBIT Bit1;
617	#ifdef IEMLIVENESS_EXTENDED_LAYOUT
618	/** Bit \#2 of the register states. */
619	IEMLIVENESSBIT Bit2;
620	/** Bit \#3 of the register states. */
621	IEMLIVENESSBIT Bit3;
622	#endif
623	};
624	} IEMLIVENESSENTRY;
625	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
626	AssertCompileSize(IEMLIVENESSENTRY, 16);
627	#else
628	AssertCompileSize(IEMLIVENESSENTRY, 32);
629	#endif
630	/** Pointer to a liveness state entry. */
631	typedef IEMLIVENESSENTRY *PIEMLIVENESSENTRY;
632	/** Pointer to a const liveness state entry. */
633	typedef IEMLIVENESSENTRY const *PCIEMLIVENESSENTRY;
634
635	/** @name 64-bit value masks for IEMLIVENESSENTRY.
636	* @{ / / 0xzzzzyyyyxxxxwwww */
637	#define IEMLIVENESSBIT_MASK UINT64_C(0x003ffffffffeffff)
638
639	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
640	# define IEMLIVENESSBIT0_XCPT_OR_CALL UINT64_C(0x0000000000000000)
641	# define IEMLIVENESSBIT1_XCPT_OR_CALL IEMLIVENESSBIT_MASK
642
643	# define IEMLIVENESSBIT0_ALL_UNUSED IEMLIVENESSBIT_MASK
644	# define IEMLIVENESSBIT1_ALL_UNUSED UINT64_C(0x0000000000000000)
645	#endif
646
647	#define IEMLIVENESSBIT_ALL_EFL_MASK UINT64_C(0x003f800000000000)
648	#define IEMLIVENESSBIT_STATUS_EFL_MASK UINT64_C(0x003f000000000000)
649
650	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
651	# define IEMLIVENESSBIT0_ALL_EFL_INPUT IEMLIVENESSBIT_ALL_EFL_MASK
652	# define IEMLIVENESSBIT1_ALL_EFL_INPUT IEMLIVENESSBIT_ALL_EFL_MASK
653	#endif
654	/** @} */
655
656
657	/** @name The liveness state for a register.
658	*
659	* The state values have been picked to with state accumulation in mind (what
660	* the iemNativeLivenessFunc_xxxx functions does), as that is the most
661	* performance critical work done with the values.
662	*
663	* This is a compressed state that only requires 2 bits per register.
664	* When accumulating state, we'll be using three IEMLIVENESSENTRY copies:
665	* 1. the incoming state from the following call,
666	* 2. the outgoing state for this call,
667	* 3. mask of the entries set in the 2nd.
668	*
669	* The mask entry (3rd one above) will be used both when updating the outgoing
670	* state and when merging in incoming state for registers not touched by the
671	* current call.
672	*
673	* @{ */
674	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
675	/** The register will be clobbered and the current value thrown away.
676	*
677	* When this is applied to the state (2) we'll simply be AND'ing it with the
678	* (old) mask (3) and adding the register to the mask. This way we'll
679	* preserve the high priority IEMLIVENESS_STATE_XCPT_OR_CALL and
680	* IEMLIVENESS_STATE_INPUT states. */
681	# define IEMLIVENESS_STATE_CLOBBERED 0
682	/** The register is unused in the remainder of the TB.
683	*
684	* This is an initial state and can not be set by any of the
685	* iemNativeLivenessFunc_xxxx callbacks. */
686	# define IEMLIVENESS_STATE_UNUSED 1
687	/** The register value is required in a potential call or exception.
688	*
689	* This means that the register value must be calculated and is best written to
690	* the state, but that any shadowing registers can be flushed thereafter as it's
691	* not used again. This state has lower priority than IEMLIVENESS_STATE_INPUT.
692	*
693	* It is typically applied across the board, but we preserve incoming
694	* IEMLIVENESS_STATE_INPUT values. This latter means we have to do some extra
695	* trickery to filter out IEMLIVENESS_STATE_UNUSED:
696	* 1. r0 = old & ~mask;
697	* 2. r0 = t1 & (t1 >> 1)'
698	* 3. state \|= r0 \| 0b10;
699	* 4. mask = ~0;
700	*/
701	# define IEMLIVENESS_STATE_XCPT_OR_CALL 2
702	/** The register value is used as input.
703	*
704	* This means that the register value must be calculated and it is best to keep
705	* it in a register. It does not need to be writtent out as such. This is the
706	* highest priority state.
707	*
708	* Whether the call modifies the register or not isn't relevant to earlier
709	* calls, so that's not recorded.
710	*
711	* When applying this state we just or in the value in the outgoing state and
712	* mask. */
713	# define IEMLIVENESS_STATE_INPUT 3
714	/** Mask of the state bits. */
715	# define IEMLIVENESS_STATE_MASK 3
716	/** The number of bits per state. */
717	# define IEMLIVENESS_STATE_BIT_COUNT 2
718	/** Check if we're expecting read & write accesses to a register with the given (previous) liveness state. */
719	# define IEMLIVENESS_STATE_IS_MODIFY_EXPECTED(a_uState) ((uint32_t)((a_uState) - 1U) >= (uint32_t)(IEMLIVENESS_STATE_INPUT - 1U))
720	/** Check if we're expecting read accesses to a register with the given (previous) liveness state. */
721	# define IEMLIVENESS_STATE_IS_INPUT_EXPECTED(a_uState) IEMLIVENESS_STATE_IS_MODIFY_EXPECTED(a_uState)
722	/** Check if a register clobbering is expected given the (previous) liveness state.
723	* The state must be either CLOBBERED or XCPT_OR_CALL, but it may also
724	* include INPUT if the register is used in more than one place. */
725	# define IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(a_uState) ((uint32_t)(a_uState) != IEMLIVENESS_STATE_UNUSED)
726
727	/** Check if all status flags are going to be clobbered and doesn't need
728	* calculating in the current step.
729	* @param a_pCurEntry The current liveness entry. */
730	# define IEMLIVENESS_STATE_ARE_STATUS_EFL_TO_BE_CLOBBERED(a_pCurEntry) \
731	( (((a_pCurEntry)->Bit0.bm64 \| (a_pCurEntry)->Bit1.bm64) & IEMLIVENESSBIT_STATUS_EFL_MASK) == 0 )
732
733	#else /* IEMLIVENESS_EXTENDED_LAYOUT */
734	/** The register is not used any more. */
735	# define IEMLIVENESS_STATE_UNUSED 0
736	/** Flag: The register is required in a potential exception or call. */
737	# define IEMLIVENESS_STATE_POT_XCPT_OR_CALL 1
738	# define IEMLIVENESS_BIT_POT_XCPT_OR_CALL 0
739	/** Flag: The register is read. */
740	# define IEMLIVENESS_STATE_READ 2
741	# define IEMLIVENESS_BIT_READ 1
742	/** Flag: The register is written. */
743	# define IEMLIVENESS_STATE_WRITE 4
744	# define IEMLIVENESS_BIT_WRITE 2
745	/** Flag: Unconditional call (not needed, can be redefined for research). */
746	# define IEMLIVENESS_STATE_CALL 8
747	# define IEMLIVENESS_BIT_CALL 3
748	# define IEMLIVENESS_BIT_OTHER 3 /*< More convenient name for this one. /
749	# define IEMLIVENESS_STATE_IS_MODIFY_EXPECTED(a_uState) \
750	( ((a_uState) & (IEMLIVENESS_STATE_WRITE \| IEMLIVENESS_STATE_READ)) == (IEMLIVENESS_STATE_WRITE \| IEMLIVENESS_STATE_READ) )
751	# define IEMLIVENESS_STATE_IS_INPUT_EXPECTED(a_uState) RT_BOOL((a_uState) & IEMLIVENESS_STATE_READ)
752	# define IEMLIVENESS_STATE_IS_CLOBBER_EXPECTED(a_uState) RT_BOOL((a_uState) & IEMLIVENESS_STATE_WRITE)
753
754	# define IEMLIVENESS_STATE_ARE_STATUS_EFL_TO_BE_CLOBBERED(a_pCurEntry) \
755	( ((a_pCurEntry)->aBits[IEMLIVENESS_BIT_WRITE].bm64 & IEMLIVENESSBIT_STATUS_EFL_MASK) == IEMLIVENESSBIT_STATUS_EFL_MASK \
756	&& !( ((a_pCurEntry)->aBits[IEMLIVENESS_BIT_READ].bm64 \| (a_pCurEntry)->aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64) \
757	& IEMLIVENESSBIT_STATUS_EFL_MASK) )
758
759	#endif /* IEMLIVENESS_EXTENDED_LAYOUT */
760	/** @} */
761
762	/** @name Liveness helpers for builtin functions and similar.
763	*
764	* These are not used by IEM_MC_BEGIN/END blocks, IEMAllN8veLiveness.cpp has its
765	* own set of manimulator macros for those.
766	*
767	* @{ */
768	/** Initializing the state as all unused. */
769	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
770	# define IEM_LIVENESS_RAW_INIT_AS_UNUSED(a_pOutgoing) \
771	do { \
772	(a_pOutgoing)->Bit0.bm64 = IEMLIVENESSBIT0_ALL_UNUSED; \
773	(a_pOutgoing)->Bit1.bm64 = IEMLIVENESSBIT1_ALL_UNUSED; \
774	} while (0)
775	#else
776	# define IEM_LIVENESS_RAW_INIT_AS_UNUSED(a_pOutgoing) \
777	do { \
778	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64 = 0; \
779	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ ].bm64 = 0; \
780	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_WRITE ].bm64 = 0; \
781	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_OTHER ].bm64 = 0; \
782	} while (0)
783	#endif
784
785	/** Initializing the outgoing state with a potential xcpt or call state.
786	* This only works when all later changes will be IEMLIVENESS_STATE_INPUT. */
787	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
788	# define IEM_LIVENESS_RAW_INIT_WITH_XCPT_OR_CALL(a_pOutgoing, a_pIncoming) \
789	do { \
790	(a_pOutgoing)->Bit0.bm64 = (a_pIncoming)->Bit0.bm64 & (a_pIncoming)->Bit1.bm64; \
791	(a_pOutgoing)->Bit1.bm64 = IEMLIVENESSBIT1_XCPT_OR_CALL; \
792	} while (0)
793	#else
794	# define IEM_LIVENESS_RAW_INIT_WITH_XCPT_OR_CALL(a_pOutgoing, a_pIncoming) \
795	do { \
796	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_POT_XCPT_OR_CALL].bm64 = IEMLIVENESSBIT_MASK; \
797	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ ].bm64 = (a_pIncoming)->aBits[IEMLIVENESS_BIT_READ].bm64; \
798	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_WRITE ].bm64 = 0; \
799	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_OTHER ].bm64 = 0; \
800	} while (0)
801	#endif
802
803	/** Adds a segment base register as input to the outgoing state. */
804	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
805	# define IEM_LIVENESS_RAW_SEG_BASE_INPUT(a_pOutgoing, a_iSReg) do { \
806	(a_pOutgoing)->Bit0.bmSegBase \|= RT_BIT_64(a_iSReg); \
807	(a_pOutgoing)->Bit1.bmSegBase \|= RT_BIT_64(a_iSReg); \
808	} while (0)
809	#else
810	# define IEM_LIVENESS_RAW_SEG_BASE_INPUT(a_pOutgoing, a_iSReg) do { \
811	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].bmSegBase \|= RT_BIT_64(a_iSReg); \
812	} while (0)
813	#endif
814
815	/** Adds a segment attribute register as input to the outgoing state. */
816	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
817	# define IEM_LIVENESS_RAW_SEG_ATTRIB_INPUT(a_pOutgoing, a_iSReg) do { \
818	(a_pOutgoing)->Bit0.bmSegAttrib \|= RT_BIT_64(a_iSReg); \
819	(a_pOutgoing)->Bit1.bmSegAttrib \|= RT_BIT_64(a_iSReg); \
820	} while (0)
821	#else
822	# define IEM_LIVENESS_RAW_SEG_ATTRIB_INPUT(a_pOutgoing, a_iSReg) do { \
823	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].bmSegAttrib \|= RT_BIT_64(a_iSReg); \
824	} while (0)
825	#endif
826
827	/** Adds a segment limit register as input to the outgoing state. */
828	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
829	# define IEM_LIVENESS_RAW_SEG_LIMIT_INPUT(a_pOutgoing, a_iSReg) do { \
830	(a_pOutgoing)->Bit0.bmSegLimit \|= RT_BIT_64(a_iSReg); \
831	(a_pOutgoing)->Bit1.bmSegLimit \|= RT_BIT_64(a_iSReg); \
832	} while (0)
833	#else
834	# define IEM_LIVENESS_RAW_SEG_LIMIT_INPUT(a_pOutgoing, a_iSReg) do { \
835	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].bmSegLimit \|= RT_BIT_64(a_iSReg); \
836	} while (0)
837	#endif
838
839	/** Adds a segment limit register as input to the outgoing state. */
840	#ifndef IEMLIVENESS_EXTENDED_LAYOUT
841	# define IEM_LIVENESS_RAW_EFLAGS_ONE_INPUT(a_pOutgoing, a_fEflMember) do { \
842	(a_pOutgoing)->Bit0.a_fEflMember \|= 1; \
843	(a_pOutgoing)->Bit1.a_fEflMember \|= 1; \
844	} while (0)
845	#else
846	# define IEM_LIVENESS_RAW_EFLAGS_ONE_INPUT(a_pOutgoing, a_fEflMember) do { \
847	(a_pOutgoing)->aBits[IEMLIVENESS_BIT_READ].a_fEflMember \|= 1; \
848	} while (0)
849	#endif
850	/** @} */
851
852	/** @def IEMNATIVE_STRICT_EFLAGS_SKIPPING_EMIT_CHECK
853	* Checks that the EFLAGS bits specified by @a a_fEflNeeded are actually
854	* calculated and up to date. This is to double check that we haven't skipped
855	* EFLAGS calculations when we actually need them. NOP in non-strict builds.
856	* @note has to be placed in
857	*/
858	#ifdef IEMNATIVE_STRICT_EFLAGS_SKIPPING
859	# define IEMNATIVE_STRICT_EFLAGS_SKIPPING_EMIT_CHECK(a_pReNative, a_off, a_fEflNeeded) \
860	do { (a_off) = iemNativeEmitEFlagsSkippingCheck(a_pReNative, a_off, a_fEflNeeded); } while (0)
861	#else
862	# define IEMNATIVE_STRICT_EFLAGS_SKIPPING_EMIT_CHECK(a_pReNative, a_off, a_fEflNeeded) do { } while (0)
863	#endif
864
865
866	/**
867	* Guest registers that can be shadowed in GPRs.
868	*
869	* This runs parallel to the liveness state (IEMLIVENESSBIT, ++). The EFlags
870	* must be placed last, as the liveness state tracks it as 7 subcomponents and
871	* we don't want to waste space here.
872	*
873	* @note Make sure to update IEMLIVENESSBIT, IEMLIVENESSBIT_ALL_EFL_MASK and
874	* friends as well as IEMAllN8veLiveness.cpp.
875	*/
876	typedef enum IEMNATIVEGSTREG : uint8_t
877	{
878	kIemNativeGstReg_GprFirst = 0,
879	kIemNativeGstReg_GprLast = kIemNativeGstReg_GprFirst + 15,
880	kIemNativeGstReg_Pc,
881	kIemNativeGstReg_Cr0,
882	kIemNativeGstReg_FpuFcw,
883	kIemNativeGstReg_FpuFsw,
884	kIemNativeGstReg_SegBaseFirst,
885	kIemNativeGstReg_SegBaseLast = kIemNativeGstReg_SegBaseFirst + 5,
886	kIemNativeGstReg_SegAttribFirst,
887	kIemNativeGstReg_SegAttribLast = kIemNativeGstReg_SegAttribFirst + 5,
888	kIemNativeGstReg_SegLimitFirst,
889	kIemNativeGstReg_SegLimitLast = kIemNativeGstReg_SegLimitFirst + 5,
890	kIemNativeGstReg_SegSelFirst,
891	kIemNativeGstReg_SegSelLast = kIemNativeGstReg_SegSelFirst + 5,
892	kIemNativeGstReg_Cr4,
893	kIemNativeGstReg_Xcr0,
894	kIemNativeGstReg_MxCsr,
895	kIemNativeGstReg_EFlags, /*< 32-bit, includes internal flags - last! /
896	kIemNativeGstReg_End
897	} IEMNATIVEGSTREG;
898	AssertCompile((int)kIemNativeGstReg_SegLimitFirst == 32);
899	AssertCompile((UINT64_C(0x7f) << kIemNativeGstReg_EFlags) == IEMLIVENESSBIT_ALL_EFL_MASK);
900
901	/** @name Helpers for converting register numbers to IEMNATIVEGSTREG values.
902	* @{ */
903	#define IEMNATIVEGSTREG_GPR(a_iGpr) ((IEMNATIVEGSTREG)(kIemNativeGstReg_GprFirst + (a_iGpr) ))
904	#define IEMNATIVEGSTREG_SEG_SEL(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegSelFirst + (a_iSegReg) ))
905	#define IEMNATIVEGSTREG_SEG_BASE(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegBaseFirst + (a_iSegReg) ))
906	#define IEMNATIVEGSTREG_SEG_LIMIT(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegLimitFirst + (a_iSegReg) ))
907	#define IEMNATIVEGSTREG_SEG_ATTRIB(a_iSegReg) ((IEMNATIVEGSTREG)(kIemNativeGstReg_SegAttribFirst + (a_iSegReg) ))
908	/** @} */
909
910	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
911
912	/**
913	* Guest registers that can be shadowed in host SIMD registers.
914	*
915	* @todo r=aeichner Liveness tracking
916	* @todo r=aeichner Given that we can only track xmm/ymm here does this actually make sense?
917	*/
918	typedef enum IEMNATIVEGSTSIMDREG : uint8_t
919	{
920	kIemNativeGstSimdReg_SimdRegFirst = 0,
921	kIemNativeGstSimdReg_SimdRegLast = kIemNativeGstSimdReg_SimdRegFirst + 15,
922	kIemNativeGstSimdReg_End
923	} IEMNATIVEGSTSIMDREG;
924
925	/** @name Helpers for converting register numbers to IEMNATIVEGSTSIMDREG values.
926	* @{ */
927	#define IEMNATIVEGSTSIMDREG_SIMD(a_iSimdReg) ((IEMNATIVEGSTSIMDREG)(kIemNativeGstSimdReg_SimdRegFirst + (a_iSimdReg)))
928	/** @} */
929
930	/**
931	* The Load/store size for a SIMD guest register.
932	*/
933	typedef enum IEMNATIVEGSTSIMDREGLDSTSZ : uint8_t
934	{
935	/** Invalid size. */
936	kIemNativeGstSimdRegLdStSz_Invalid = 0,
937	/** Loads the low 128-bit of a guest SIMD register. */
938	kIemNativeGstSimdRegLdStSz_Low128,
939	/** Loads the high 128-bit of a guest SIMD register. */
940	kIemNativeGstSimdRegLdStSz_High128,
941	/** Loads the whole 256-bits of a guest SIMD register. */
942	kIemNativeGstSimdRegLdStSz_256,
943	/** End value. */
944	kIemNativeGstSimdRegLdStSz_End
945	} IEMNATIVEGSTSIMDREGLDSTSZ;
946
947	#endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */
948
949	/**
950	* Intended use statement for iemNativeRegAllocTmpForGuestReg().
951	*/
952	typedef enum IEMNATIVEGSTREGUSE
953	{
954	/** The usage is read-only, the register holding the guest register
955	* shadow copy will not be modified by the caller. */
956	kIemNativeGstRegUse_ReadOnly = 0,
957	/** The caller will update the guest register (think: PC += cbInstr).
958	* The guest shadow copy will follow the returned register. */
959	kIemNativeGstRegUse_ForUpdate,
960	/** The call will put an entirely new value in the guest register, so
961	* if new register is allocate it will be returned uninitialized. */
962	kIemNativeGstRegUse_ForFullWrite,
963	/** The caller will use the guest register value as input in a calculation
964	* and the host register will be modified.
965	* This means that the returned host register will not be marked as a shadow
966	* copy of the guest register. */
967	kIemNativeGstRegUse_Calculation
968	} IEMNATIVEGSTREGUSE;
969
970	/**
971	* Guest registers (classes) that can be referenced.
972	*/
973	typedef enum IEMNATIVEGSTREGREF : uint8_t
974	{
975	kIemNativeGstRegRef_Invalid = 0,
976	kIemNativeGstRegRef_Gpr,
977	kIemNativeGstRegRef_GprHighByte, /*< AH, CH, DH, BH/
978	kIemNativeGstRegRef_EFlags,
979	kIemNativeGstRegRef_MxCsr,
980	kIemNativeGstRegRef_FpuReg,
981	kIemNativeGstRegRef_MReg,
982	kIemNativeGstRegRef_XReg,
983	kIemNativeGstRegRef_X87,
984	kIemNativeGstRegRef_XState,
985	//kIemNativeGstRegRef_YReg, - doesn't work.
986	kIemNativeGstRegRef_End
987	} IEMNATIVEGSTREGREF;
988
989
990	/** Variable kinds. */
991	typedef enum IEMNATIVEVARKIND : uint8_t
992	{
993	/** Customary invalid zero value. */
994	kIemNativeVarKind_Invalid = 0,
995	/** This is either in a register or on the stack. */
996	kIemNativeVarKind_Stack,
997	/** Immediate value - loaded into register when needed, or can live on the
998	* stack if referenced (in theory). */
999	kIemNativeVarKind_Immediate,
1000	/** Variable reference - loaded into register when needed, never stack. */
1001	kIemNativeVarKind_VarRef,
1002	/** Guest register reference - loaded into register when needed, never stack. */
1003	kIemNativeVarKind_GstRegRef,
1004	/** End of valid values. */
1005	kIemNativeVarKind_End
1006	} IEMNATIVEVARKIND;
1007
1008
1009	/** Variable or argument. */
1010	typedef struct IEMNATIVEVAR
1011	{
1012	/** The kind of variable. */
1013	IEMNATIVEVARKIND enmKind;
1014	/** The variable size in bytes. */
1015	uint8_t cbVar;
1016	/** The first stack slot (uint64_t), except for immediate and references
1017	* where it usually is UINT8_MAX. This is allocated lazily, so if a variable
1018	* has a stack slot it has been initialized and has a value. Unused variables
1019	* has neither a stack slot nor a host register assignment. */
1020	uint8_t idxStackSlot;
1021	/** The host register allocated for the variable, UINT8_MAX if not. */
1022	uint8_t idxReg;
1023	/** The argument number if argument, UINT8_MAX if regular variable. */
1024	uint8_t uArgNo;
1025	/** If referenced, the index (unpacked) of the variable referencing this one,
1026	* otherwise UINT8_MAX. A referenced variable must only be placed on the stack
1027	* and must be either kIemNativeVarKind_Stack or kIemNativeVarKind_Immediate. */
1028	uint8_t idxReferrerVar;
1029	/** Guest register being shadowed here, kIemNativeGstReg_End(/UINT8_MAX) if not.
1030	* @todo not sure what this really is for... */
1031	IEMNATIVEGSTREG enmGstReg;
1032	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1033	/** Flag whether this variable is held in a SIMD register (only supported for 128-bit and 256-bit variables),
1034	* only valid when idxReg is not UINT8_MAX. */
1035	bool fSimdReg : 1;
1036	/** Set if the registered is currently used exclusively, false if the
1037	* variable is idle and the register can be grabbed. */
1038	bool fRegAcquired : 1;
1039	#else
1040	/** Set if the registered is currently used exclusively, false if the
1041	* variable is idle and the register can be grabbed. */
1042	bool fRegAcquired;
1043	#endif
1044
1045	union
1046	{
1047	/** kIemNativeVarKind_Immediate: The immediate value. */
1048	uint64_t uValue;
1049	/** kIemNativeVarKind_VarRef: The index (unpacked) of the variable being referenced. */
1050	uint8_t idxRefVar;
1051	/** kIemNativeVarKind_GstRegRef: The guest register being referrenced. */
1052	struct
1053	{
1054	/** The class of register. */
1055	IEMNATIVEGSTREGREF enmClass;
1056	/** Index within the class. */
1057	uint8_t idx;
1058	} GstRegRef;
1059	} u;
1060	} IEMNATIVEVAR;
1061	/** Pointer to a variable or argument. */
1062	typedef IEMNATIVEVAR *PIEMNATIVEVAR;
1063	/** Pointer to a const variable or argument. */
1064	typedef IEMNATIVEVAR const *PCIEMNATIVEVAR;
1065
1066	/** What is being kept in a host register. */
1067	typedef enum IEMNATIVEWHAT : uint8_t
1068	{
1069	/** The traditional invalid zero value. */
1070	kIemNativeWhat_Invalid = 0,
1071	/** Mapping a variable (IEMNATIVEHSTREG::idxVar). */
1072	kIemNativeWhat_Var,
1073	/** Temporary register, this is typically freed when a MC completes. */
1074	kIemNativeWhat_Tmp,
1075	/** Call argument w/o a variable mapping. This is free (via
1076	* IEMNATIVE_CALL_VOLATILE_GREG_MASK) after the call is emitted. */
1077	kIemNativeWhat_Arg,
1078	/** Return status code.
1079	* @todo not sure if we need this... */
1080	kIemNativeWhat_rc,
1081	/** The fixed pVCpu (PVMCPUCC) register.
1082	* @todo consider offsetting this on amd64 to use negative offsets to access
1083	* more members using 8-byte disp. */
1084	kIemNativeWhat_pVCpuFixed,
1085	/** The fixed pCtx (PCPUMCTX) register.
1086	* @todo consider offsetting this on amd64 to use negative offsets to access
1087	* more members using 8-byte disp. */
1088	kIemNativeWhat_pCtxFixed,
1089	/** Fixed temporary register. */
1090	kIemNativeWhat_FixedTmp,
1091	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1092	/** Shadow RIP for the delayed RIP updating debugging. */
1093	kIemNativeWhat_PcShadow,
1094	#endif
1095	/** Register reserved by the CPU or OS architecture. */
1096	kIemNativeWhat_FixedReserved,
1097	/** End of valid values. */
1098	kIemNativeWhat_End
1099	} IEMNATIVEWHAT;
1100
1101	/**
1102	* Host general register entry.
1103	*
1104	* The actual allocation status is kept in IEMRECOMPILERSTATE::bmHstRegs.
1105	*
1106	* @todo Track immediate values in host registers similarlly to how we track the
1107	* guest register shadow copies. For it to be real helpful, though,
1108	* we probably need to know which will be reused and put them into
1109	* non-volatile registers, otherwise it's going to be more or less
1110	* restricted to an instruction or two.
1111	*/
1112	typedef struct IEMNATIVEHSTREG
1113	{
1114	/** Set of guest registers this one shadows.
1115	*
1116	* Using a bitmap here so we can designate the same host register as a copy
1117	* for more than one guest register. This is expected to be useful in
1118	* situations where one value is copied to several registers in a sequence.
1119	* If the mapping is 1:1, then we'd have to pick which side of a 'MOV SRC,DST'
1120	* sequence we'd want to let this register follow to be a copy of and there
1121	* will always be places where we'd be picking the wrong one.
1122	*/
1123	uint64_t fGstRegShadows;
1124	/** What is being kept in this register. */
1125	IEMNATIVEWHAT enmWhat;
1126	/** Variable index (packed) if holding a variable, otherwise UINT8_MAX. */
1127	uint8_t idxVar;
1128	/** Stack slot assigned by iemNativeVarSaveVolatileRegsPreHlpCall and freed
1129	* by iemNativeVarRestoreVolatileRegsPostHlpCall. This is not valid outside
1130	* that scope. */
1131	uint8_t idxStackSlot;
1132	/** Alignment padding. */
1133	uint8_t abAlign[5];
1134	} IEMNATIVEHSTREG;
1135
1136
1137	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1138	/**
1139	* Host SIMD register entry - this tracks a virtual 256-bit register split into two 128-bit
1140	* halves, on architectures where there is no 256-bit register available this entry will track
1141	* two adjacent 128-bit host registers.
1142	*
1143	* The actual allocation status is kept in IEMRECOMPILERSTATE::bmHstSimdRegs.
1144	*/
1145	typedef struct IEMNATIVEHSTSIMDREG
1146	{
1147	/** Set of guest registers this one shadows.
1148	*
1149	* Using a bitmap here so we can designate the same host register as a copy
1150	* for more than one guest register. This is expected to be useful in
1151	* situations where one value is copied to several registers in a sequence.
1152	* If the mapping is 1:1, then we'd have to pick which side of a 'MOV SRC,DST'
1153	* sequence we'd want to let this register follow to be a copy of and there
1154	* will always be places where we'd be picking the wrong one.
1155	*/
1156	uint64_t fGstRegShadows;
1157	/** What is being kept in this register. */
1158	IEMNATIVEWHAT enmWhat;
1159	/** Variable index (packed) if holding a variable, otherwise UINT8_MAX. */
1160	uint8_t idxVar;
1161	/** Flag what is currently loaded, low 128-bits, high 128-bits or complete 256-bits. */
1162	IEMNATIVEGSTSIMDREGLDSTSZ enmLoaded;
1163	/** Alignment padding. */
1164	uint8_t abAlign[5];
1165	} IEMNATIVEHSTSIMDREG;
1166	#endif
1167
1168
1169	/**
1170	* Core state for the native recompiler, that is, things that needs careful
1171	* handling when dealing with branches.
1172	*/
1173	typedef struct IEMNATIVECORESTATE
1174	{
1175	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1176	/** The current instruction offset in bytes from when the guest program counter
1177	* was updated last. Used for delaying the write to the guest context program counter
1178	* as long as possible. */
1179	uint32_t offPc;
1180	/** Number of instructions where we could skip the updating. */
1181	uint32_t cInstrPcUpdateSkipped;
1182	#endif
1183	/** Allocation bitmap for aHstRegs. */
1184	uint32_t bmHstRegs;
1185
1186	/** Bitmap marking which host register contains guest register shadow copies.
1187	* This is used during register allocation to try preserve copies. */
1188	uint32_t bmHstRegsWithGstShadow;
1189	/** Bitmap marking valid entries in aidxGstRegShadows. */
1190	uint64_t bmGstRegShadows;
1191	#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
1192	/** Bitmap marking the shadowed guest register as dirty and needing writeback when flushing. */
1193	uint64_t bmGstRegShadowDirty;
1194	#endif
1195
1196	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1197	/** Allocation bitmap for aHstSimdRegs. */
1198	uint32_t bmHstSimdRegs;
1199
1200	/** Bitmap marking which host SIMD register contains guest SIMD register shadow copies.
1201	* This is used during register allocation to try preserve copies. */
1202	uint32_t bmHstSimdRegsWithGstShadow;
1203	/** Bitmap marking valid entries in aidxSimdGstRegShadows. */
1204	uint64_t bmGstSimdRegShadows;
1205	/** Bitmap marking whether the low 128-bit of the shadowed guest register are dirty and need writeback. */
1206	uint64_t bmGstSimdRegShadowDirtyLo128;
1207	/** Bitmap marking whether the high 128-bit of the shadowed guest register are dirty and need writeback. */
1208	uint64_t bmGstSimdRegShadowDirtyHi128;
1209	#endif
1210
1211	union
1212	{
1213	/** Index of variable (unpacked) arguments, UINT8_MAX if not valid. */
1214	uint8_t aidxArgVars[8];
1215	/** For more efficient resetting. */
1216	uint64_t u64ArgVars;
1217	};
1218
1219	/** Allocation bitmap for the stack. */
1220	uint32_t bmStack;
1221	/** Allocation bitmap for aVars. */
1222	uint32_t bmVars;
1223
1224	/** Maps a guest register to a host GPR (index by IEMNATIVEGSTREG).
1225	* Entries are only valid if the corresponding bit in bmGstRegShadows is set.
1226	* (A shadow copy of a guest register can only be held in a one host register,
1227	* there are no duplicate copies or ambiguities like that). */
1228	uint8_t aidxGstRegShadows[kIemNativeGstReg_End];
1229	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1230	/** Maps a guest SIMD register to a host SIMD register (index by IEMNATIVEGSTSIMDREG).
1231	* Entries are only valid if the corresponding bit in bmGstSimdRegShadows is set.
1232	* (A shadow copy of a guest register can only be held in a one host register,
1233	* there are no duplicate copies or ambiguities like that). */
1234	uint8_t aidxGstSimdRegShadows[kIemNativeGstSimdReg_End];
1235	#endif
1236
1237	/** Host register allocation tracking. */
1238	IEMNATIVEHSTREG aHstRegs[IEMNATIVE_HST_GREG_COUNT];
1239	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1240	/** Host SIMD register allocation tracking. */
1241	IEMNATIVEHSTSIMDREG aHstSimdRegs[IEMNATIVE_HST_SIMD_REG_COUNT];
1242	#endif
1243
1244	/** Variables and arguments. */
1245	IEMNATIVEVAR aVars[9];
1246	} IEMNATIVECORESTATE;
1247	/** Pointer to core state. */
1248	typedef IEMNATIVECORESTATE *PIEMNATIVECORESTATE;
1249	/** Pointer to const core state. */
1250	typedef IEMNATIVECORESTATE const *PCIEMNATIVECORESTATE;
1251
1252	/** @def IEMNATIVE_VAR_IDX_UNPACK
1253	* @returns Index into IEMNATIVECORESTATE::aVars.
1254	* @param a_idxVar Variable index w/ magic (in strict builds).
1255	*/
1256	/** @def IEMNATIVE_VAR_IDX_PACK
1257	* @returns Variable index w/ magic (in strict builds).
1258	* @param a_idxVar Index into IEMNATIVECORESTATE::aVars.
1259	*/
1260	#ifdef VBOX_STRICT
1261	# define IEMNATIVE_VAR_IDX_UNPACK(a_idxVar) ((a_idxVar) & IEMNATIVE_VAR_IDX_MASK)
1262	# define IEMNATIVE_VAR_IDX_PACK(a_idxVar) ((a_idxVar) \| IEMNATIVE_VAR_IDX_MAGIC)
1263	# define IEMNATIVE_VAR_IDX_MAGIC UINT8_C(0xd0)
1264	# define IEMNATIVE_VAR_IDX_MAGIC_MASK UINT8_C(0xf0)
1265	# define IEMNATIVE_VAR_IDX_MASK UINT8_C(0x0f)
1266	#else
1267	# define IEMNATIVE_VAR_IDX_UNPACK(a_idxVar) (a_idxVar)
1268	# define IEMNATIVE_VAR_IDX_PACK(a_idxVar) (a_idxVar)
1269	#endif
1270
1271
1272	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1273	/** Clear the dirty state of the given guest SIMD register. */
1274	# define IEMNATIVE_SIMD_REG_STATE_CLR_DIRTY(a_pReNative, a_iSimdReg) \
1275	do { \
1276	(a_pReNative)->Core.bmGstSimdRegShadowDirtyLo128 &= ~RT_BIT_64(a_iSimdReg); \
1277	(a_pReNative)->Core.bmGstSimdRegShadowDirtyHi128 &= ~RT_BIT_64(a_iSimdReg); \
1278	} while (0)
1279
1280	/** Returns whether the low 128-bits of the given guest SIMD register are dirty. */
1281	# define IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_LO_U128(a_pReNative, a_iSimdReg) \
1282	RT_BOOL((a_pReNative)->Core.bmGstSimdRegShadowDirtyLo128 & RT_BIT_64(a_iSimdReg))
1283	/** Returns whether the high 128-bits of the given guest SIMD register are dirty. */
1284	# define IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_HI_U128(a_pReNative, a_iSimdReg) \
1285	RT_BOOL((a_pReNative)->Core.bmGstSimdRegShadowDirtyHi128 & RT_BIT_64(a_iSimdReg))
1286	/** Returns whether the given guest SIMD register is dirty. */
1287	# define IEMNATIVE_SIMD_REG_STATE_IS_DIRTY_U256(a_pReNative, a_iSimdReg) \
1288	RT_BOOL(((a_pReNative)->Core.bmGstSimdRegShadowDirtyLo128 \| (a_pReNative)->Core.bmGstSimdRegShadowDirtyHi128) & RT_BIT_64(a_iSimdReg))
1289
1290	/** Set the low 128-bits of the given guest SIMD register to the dirty state. */
1291	# define IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_LO_U128(a_pReNative, a_iSimdReg) \
1292	((a_pReNative)->Core.bmGstSimdRegShadowDirtyLo128 \|= RT_BIT_64(a_iSimdReg))
1293	/** Set the high 128-bits of the given guest SIMD register to the dirty state. */
1294	# define IEMNATIVE_SIMD_REG_STATE_SET_DIRTY_HI_U128(a_pReNative, a_iSimdReg) \
1295	((a_pReNative)->Core.bmGstSimdRegShadowDirtyHi128 \|= RT_BIT_64(a_iSimdReg))
1296
1297	/** Flag for indicating that IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() has emitted code in the current TB. */
1298	# define IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_DEVICE_NOT_AVAILABLE RT_BIT_32(0)
1299	/** Flag for indicating that IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() has emitted code in the current TB. */
1300	# define IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_WAIT_DEVICE_NOT_AVAILABLE RT_BIT_32(1)
1301	/** Flag for indicating that IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() has emitted code in the current TB. */
1302	# define IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_SSE RT_BIT_32(2)
1303	/** Flag for indicating that IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() has emitted code in the current TB. */
1304	# define IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_MAYBE_AVX RT_BIT_32(3)
1305	#endif
1306
1307
1308	/**
1309	* Conditional stack entry.
1310	*/
1311	typedef struct IEMNATIVECOND
1312	{
1313	/** Set if we're in the "else" part, clear if we're in the "if" before it. */
1314	bool fInElse;
1315	/** The label for the IEM_MC_ELSE. */
1316	uint32_t idxLabelElse;
1317	/** The label for the IEM_MC_ENDIF. */
1318	uint32_t idxLabelEndIf;
1319	/** The initial state snapshot as the if-block starts executing. */
1320	IEMNATIVECORESTATE InitialState;
1321	/** The state snapshot at the end of the if-block. */
1322	IEMNATIVECORESTATE IfFinalState;
1323	} IEMNATIVECOND;
1324	/** Pointer to a condition stack entry. */
1325	typedef IEMNATIVECOND *PIEMNATIVECOND;
1326
1327
1328	/**
1329	* Native recompiler state.
1330	*/
1331	typedef struct IEMRECOMPILERSTATE
1332	{
1333	/** Size of the buffer that pbNativeRecompileBufR3 points to in
1334	* IEMNATIVEINSTR units. */
1335	uint32_t cInstrBufAlloc;
1336	#ifdef VBOX_STRICT
1337	/** Strict: How far the last iemNativeInstrBufEnsure() checked. */
1338	uint32_t offInstrBufChecked;
1339	#else
1340	uint32_t uPadding1; /* We don't keep track of the size here... */
1341	#endif
1342	/** Fixed temporary code buffer for native recompilation. */
1343	PIEMNATIVEINSTR pInstrBuf;
1344
1345	/** Bitmaps with the label types used. */
1346	uint64_t bmLabelTypes;
1347	/** Actual number of labels in paLabels. */
1348	uint32_t cLabels;
1349	/** Max number of entries allowed in paLabels before reallocating it. */
1350	uint32_t cLabelsAlloc;
1351	/** Labels defined while recompiling (referenced by fixups). */
1352	PIEMNATIVELABEL paLabels;
1353	/** Array with indexes of unique labels (uData always 0). */
1354	uint32_t aidxUniqueLabels[kIemNativeLabelType_FirstWithMultipleInstances];
1355
1356	/** Actual number of fixups paFixups. */
1357	uint32_t cFixups;
1358	/** Max number of entries allowed in paFixups before reallocating it. */
1359	uint32_t cFixupsAlloc;
1360	/** Buffer used by the recompiler for recording fixups when generating code. */
1361	PIEMNATIVEFIXUP paFixups;
1362
1363	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
1364	/** Number of debug info entries allocated for pDbgInfo. */
1365	uint32_t cDbgInfoAlloc;
1366	uint32_t uPadding;
1367	/** Debug info. */
1368	PIEMTBDBG pDbgInfo;
1369	#endif
1370
1371	#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
1372	/** The current call index (liveness array and threaded calls in TB). */
1373	uint32_t idxCurCall;
1374	/** Number of liveness entries allocated. */
1375	uint32_t cLivenessEntriesAlloc;
1376	/** Liveness entries for all the calls in the TB begin recompiled.
1377	* The entry for idxCurCall contains the info for what the next call will
1378	* require wrt registers. (Which means the last entry is the initial liveness
1379	* state.) */
1380	PIEMLIVENESSENTRY paLivenessEntries;
1381	#endif
1382
1383	/** The translation block being recompiled. */
1384	PCIEMTB pTbOrg;
1385	/** The VMCPU structure of the EMT. */
1386	PVMCPUCC pVCpu;
1387
1388	/** Condition sequence number (for generating unique labels). */
1389	uint16_t uCondSeqNo;
1390	/** Check IRQ seqeunce number (for generating unique labels). */
1391	uint16_t uCheckIrqSeqNo;
1392	/** TLB load sequence number (for generating unique labels). */
1393	uint16_t uTlbSeqNo;
1394	/** The current condition stack depth (aCondStack). */
1395	uint8_t cCondDepth;
1396
1397	/** The argument count + hidden regs from the IEM_MC_BEGIN_EX statement. */
1398	uint8_t cArgsX;
1399	/** The IEM_CIMPL_F_XXX flags from the IEM_MC_BEGIN statement. */
1400	uint32_t fCImpl;
1401	/** The IEM_MC_F_XXX flags from the IEM_MC_BEGIN statement. */
1402	uint32_t fMc;
1403	/** The expected IEMCPU::fExec value for the current call/instruction. */
1404	uint32_t fExec;
1405	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1406	/** IEMNATIVE_SIMD_RAISE_XCPT_CHECKS_EMITTED_XXX flags for exception flags
1407	* we only emit once per TB (or when the cr0/cr4/xcr0 register changes).
1408	*
1409	* This is an optimization because these control registers can only be changed from
1410	* by calling a C helper we can catch. Should reduce the number of instructions in a TB
1411	* consisting of multiple SIMD instructions.
1412	*/
1413	uint32_t fSimdRaiseXcptChecksEmitted;
1414	#endif
1415
1416	/** Core state requiring care with branches. */
1417	IEMNATIVECORESTATE Core;
1418
1419	/** The condition nesting stack. */
1420	IEMNATIVECOND aCondStack[2];
1421
1422	#ifndef IEM_WITH_THROW_CATCH
1423	/** Pointer to the setjmp/longjmp buffer if we're not using C++ exceptions
1424	* for recompilation error handling. */
1425	jmp_buf JmpBuf;
1426	#endif
1427	} IEMRECOMPILERSTATE;
1428	/** Pointer to a native recompiler state. */
1429	typedef IEMRECOMPILERSTATE *PIEMRECOMPILERSTATE;
1430
1431
1432	/** @def IEMNATIVE_TRY_SETJMP
1433	* Wrapper around setjmp / try, hiding all the ugly differences.
1434	*
1435	* @note Use with extreme care as this is a fragile macro.
1436	* @param a_pReNative The native recompile state.
1437	* @param a_rcTarget The variable that should receive the status code in case
1438	* of a longjmp/throw.
1439	*/
1440	/** @def IEMNATIVE_CATCH_LONGJMP_BEGIN
1441	* Start wrapper for catch / setjmp-else.
1442	*
1443	* This will set up a scope.
1444	*
1445	* @note Use with extreme care as this is a fragile macro.
1446	* @param a_pReNative The native recompile state.
1447	* @param a_rcTarget The variable that should receive the status code in case
1448	* of a longjmp/throw.
1449	*/
1450	/** @def IEMNATIVE_CATCH_LONGJMP_END
1451	* End wrapper for catch / setjmp-else.
1452	*
1453	* This will close the scope set up by IEMNATIVE_CATCH_LONGJMP_BEGIN and clean
1454	* up the state.
1455	*
1456	* @note Use with extreme care as this is a fragile macro.
1457	* @param a_pReNative The native recompile state.
1458	*/
1459	/** @def IEMNATIVE_DO_LONGJMP
1460	*
1461	* Wrapper around longjmp / throw.
1462	*
1463	* @param a_pReNative The native recompile state.
1464	* @param a_rc The status code jump back with / throw.
1465	*/
1466	#ifdef IEM_WITH_THROW_CATCH
1467	# define IEMNATIVE_TRY_SETJMP(a_pReNative, a_rcTarget) \
1468	a_rcTarget = VINF_SUCCESS; \
1469	try
1470	# define IEMNATIVE_CATCH_LONGJMP_BEGIN(a_pReNative, a_rcTarget) \
1471	catch (int rcThrown) \
1472	{ \
1473	a_rcTarget = rcThrown
1474	# define IEMNATIVE_CATCH_LONGJMP_END(a_pReNative) \
1475	} \
1476	((void)0)
1477	# define IEMNATIVE_DO_LONGJMP(a_pReNative, a_rc) throw int(a_rc)
1478	#else /* !IEM_WITH_THROW_CATCH */
1479	# define IEMNATIVE_TRY_SETJMP(a_pReNative, a_rcTarget) \
1480	if ((a_rcTarget = setjmp((a_pReNative)->JmpBuf)) == 0)
1481	# define IEMNATIVE_CATCH_LONGJMP_BEGIN(a_pReNative, a_rcTarget) \
1482	else \
1483	{ \
1484	((void)0)
1485	# define IEMNATIVE_CATCH_LONGJMP_END(a_pReNative) \
1486	}
1487	# define IEMNATIVE_DO_LONGJMP(a_pReNative, a_rc) longjmp((a_pReNative)->JmpBuf, (a_rc))
1488	#endif /* !IEM_WITH_THROW_CATCH */
1489
1490
1491	/**
1492	* Native recompiler worker for a threaded function.
1493	*
1494	* @returns New code buffer offset; throws VBox status code in case of a failure.
1495	* @param pReNative The native recompiler state.
1496	* @param off The current code buffer offset.
1497	* @param pCallEntry The threaded call entry.
1498	*
1499	* @note This may throw/longjmp VBox status codes (int) to abort compilation, so no RT_NOEXCEPT!
1500	*/
1501	typedef uint32_t (VBOXCALL FNIEMNATIVERECOMPFUNC)(PIEMRECOMPILERSTATE pReNative, uint32_t off, PCIEMTHRDEDCALLENTRY pCallEntry);
1502	/** Pointer to a native recompiler worker for a threaded function. */
1503	typedef FNIEMNATIVERECOMPFUNC *PFNIEMNATIVERECOMPFUNC;
1504
1505	/** Defines a native recompiler worker for a threaded function.
1506	* @see FNIEMNATIVERECOMPFUNC */
1507	#define IEM_DECL_IEMNATIVERECOMPFUNC_DEF(a_Name) \
1508	uint32_t VBOXCALL a_Name(PIEMRECOMPILERSTATE pReNative, uint32_t off, PCIEMTHRDEDCALLENTRY pCallEntry)
1509
1510	/** Prototypes a native recompiler function for a threaded function.
1511	* @see FNIEMNATIVERECOMPFUNC */
1512	#define IEM_DECL_IEMNATIVERECOMPFUNC_PROTO(a_Name) FNIEMNATIVERECOMPFUNC a_Name
1513
1514
1515	/**
1516	* Native recompiler liveness analysis worker for a threaded function.
1517	*
1518	* @param pCallEntry The threaded call entry.
1519	* @param pIncoming The incoming liveness state entry.
1520	* @param pOutgoing The outgoing liveness state entry.
1521	*/
1522	typedef DECLCALLBACKTYPE(void, FNIEMNATIVELIVENESSFUNC, (PCIEMTHRDEDCALLENTRY pCallEntry,
1523	PCIEMLIVENESSENTRY pIncoming, PIEMLIVENESSENTRY pOutgoing));
1524	/** Pointer to a native recompiler liveness analysis worker for a threaded function. */
1525	typedef FNIEMNATIVELIVENESSFUNC *PFNIEMNATIVELIVENESSFUNC;
1526
1527	/** Defines a native recompiler liveness analysis worker for a threaded function.
1528	* @see FNIEMNATIVELIVENESSFUNC */
1529	#define IEM_DECL_IEMNATIVELIVENESSFUNC_DEF(a_Name) \
1530	DECLCALLBACK(void) a_Name(PCIEMTHRDEDCALLENTRY pCallEntry, PCIEMLIVENESSENTRY pIncoming, PIEMLIVENESSENTRY pOutgoing)
1531
1532	/** Prototypes a native recompiler liveness analysis function for a threaded function.
1533	* @see FNIEMNATIVELIVENESSFUNC */
1534	#define IEM_DECL_IEMNATIVELIVENESSFUNC_PROTO(a_Name) FNIEMNATIVELIVENESSFUNC a_Name
1535
1536
1537	/** Define a native recompiler helper function, safe to call from the TB code. */
1538	#define IEM_DECL_NATIVE_HLP_DEF(a_RetType, a_Name, a_ArgList) \
1539	DECL_HIDDEN_THROW(a_RetType) VBOXCALL a_Name a_ArgList
1540	/** Prototype a native recompiler helper function, safe to call from the TB code. */
1541	#define IEM_DECL_NATIVE_HLP_PROTO(a_RetType, a_Name, a_ArgList) \
1542	DECL_HIDDEN_THROW(a_RetType) VBOXCALL a_Name a_ArgList
1543	/** Pointer typedef a native recompiler helper function, safe to call from the TB code. */
1544	#define IEM_DECL_NATIVE_HLP_PTR(a_RetType, a_Name, a_ArgList) \
1545	a_RetType (VBOXCALL *a_Name) a_ArgList
1546
1547
1548	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
1549	DECL_HIDDEN_THROW(void) iemNativeDbgInfoAddNativeOffset(PIEMRECOMPILERSTATE pReNative, uint32_t off);
1550	DECL_HIDDEN_THROW(void) iemNativeDbgInfoAddGuestRegShadowing(PIEMRECOMPILERSTATE pReNative, IEMNATIVEGSTREG enmGstReg,
1551	uint8_t idxHstReg = UINT8_MAX, uint8_t idxHstRegPrev = UINT8_MAX);
1552	# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1553	DECL_HIDDEN_THROW(void) iemNativeDbgInfoAddGuestSimdRegShadowing(PIEMRECOMPILERSTATE pReNative,
1554	IEMNATIVEGSTSIMDREG enmGstSimdReg,
1555	uint8_t idxHstSimdReg = UINT8_MAX,
1556	uint8_t idxHstSimdRegPrev = UINT8_MAX);
1557	# endif
1558	# if defined(IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK) \|\| defined(IEMNATIVE_WITH_SIMD_REG_ALLOCATOR)
1559	DECL_HIDDEN_THROW(void) iemNativeDbgInfoAddGuestRegDirty(PIEMRECOMPILERSTATE pReNative, bool fSimdReg,
1560	uint8_t idxGstReg, uint8_t idxHstReg);
1561	DECL_HIDDEN_THROW(void) iemNativeDbgInfoAddGuestRegWriteback(PIEMRECOMPILERSTATE pReNative, bool fSimdReg,
1562	uint64_t fGstReg);
1563	# endif
1564	DECL_HIDDEN_THROW(void) iemNativeDbgInfoAddDelayedPcUpdate(PIEMRECOMPILERSTATE pReNative,
1565	uint32_t offPc, uint32_t cInstrSkipped);
1566	#endif /* IEMNATIVE_WITH_TB_DEBUG_INFO */
1567
1568	DECL_HIDDEN_THROW(uint32_t) iemNativeLabelCreate(PIEMRECOMPILERSTATE pReNative, IEMNATIVELABELTYPE enmType,
1569	uint32_t offWhere = UINT32_MAX, uint16_t uData = 0);
1570	DECL_HIDDEN_THROW(void) iemNativeLabelDefine(PIEMRECOMPILERSTATE pReNative, uint32_t idxLabel, uint32_t offWhere);
1571	DECL_HIDDEN_THROW(void) iemNativeAddFixup(PIEMRECOMPILERSTATE pReNative, uint32_t offWhere, uint32_t idxLabel,
1572	IEMNATIVEFIXUPTYPE enmType, int8_t offAddend = 0);
1573	DECL_HIDDEN_THROW(PIEMNATIVEINSTR) iemNativeInstrBufEnsureSlow(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t cInstrReq);
1574
1575	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmp(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, bool fPreferVolatile = true);
1576	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpEx(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint32_t fRegMask,
1577	bool fPreferVolatile = true);
1578	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpImm(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint64_t uImm,
1579	bool fPreferVolatile = true);
1580	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpForGuestReg(PIEMRECOMPILERSTATE pReNative, uint32_t *poff,
1581	IEMNATIVEGSTREG enmGstReg,
1582	IEMNATIVEGSTREGUSE enmIntendedUse = kIemNativeGstRegUse_ReadOnly,
1583	bool fNoVolatileRegs = false, bool fSkipLivenessAssert = false);
1584	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAllocTmpForGuestRegIfAlreadyPresent(PIEMRECOMPILERSTATE pReNative, uint32_t *poff,
1585	IEMNATIVEGSTREG enmGstReg);
1586
1587	DECL_HIDDEN_THROW(uint32_t) iemNativeRegAllocArgs(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs);
1588	DECL_HIDDEN_THROW(uint8_t) iemNativeRegAssignRc(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg);
1589	#if (defined(IPRT_INCLUDED_x86_h) && defined(RT_ARCH_AMD64)) \|\| (defined(IPRT_INCLUDED_armv8_h) && defined(RT_ARCH_ARM64))
1590	DECL_HIDDEN_THROW(uint32_t) iemNativeRegMoveOrSpillStackVar(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVar,
1591	uint32_t fForbiddenRegs = IEMNATIVE_CALL_VOLATILE_GREG_MASK);
1592	# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1593	DECL_HIDDEN_THROW(uint32_t) iemNativeSimdRegMoveOrSpillStackVar(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxVar,
1594	uint32_t fForbiddenRegs = IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK);
1595	# endif
1596	#endif
1597	DECLHIDDEN(void) iemNativeRegFree(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
1598	DECLHIDDEN(void) iemNativeRegFreeTmp(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
1599	DECLHIDDEN(void) iemNativeRegFreeTmpImm(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg) RT_NOEXCEPT;
1600	DECLHIDDEN(void) iemNativeRegFreeVar(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg, bool fFlushShadows) RT_NOEXCEPT;
1601	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1602	DECLHIDDEN(void) iemNativeSimdRegFreeVar(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstSimdReg, bool fFlushShadows) RT_NOEXCEPT;
1603	# ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
1604	DECL_HIDDEN_THROW(uint32_t) iemNativeSimdRegFlushDirtyGuestByHostSimdRegShadow(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxHstReg);
1605	# endif
1606	#endif
1607	DECLHIDDEN(void) iemNativeRegFreeAndFlushMask(PIEMRECOMPILERSTATE pReNative, uint32_t fHstRegMask) RT_NOEXCEPT;
1608	DECL_HIDDEN_THROW(uint32_t) iemNativeRegMoveAndFreeAndFlushAtCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs,
1609	uint32_t fKeepVars = 0);
1610	DECLHIDDEN(void) iemNativeRegFlushGuestShadows(PIEMRECOMPILERSTATE pReNative, uint64_t fGstRegs) RT_NOEXCEPT;
1611	DECLHIDDEN(void) iemNativeRegFlushGuestShadowsByHostMask(PIEMRECOMPILERSTATE pReNative, uint32_t fHstRegs) RT_NOEXCEPT;
1612	DECL_HIDDEN_THROW(uint32_t) iemNativeRegRestoreGuestShadowsInVolatileRegs(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1613	uint32_t fHstRegsActiveShadows);
1614	#ifdef VBOX_STRICT
1615	DECLHIDDEN(void) iemNativeRegAssertSanity(PIEMRECOMPILERSTATE pReNative);
1616	#endif
1617	DECL_HIDDEN_THROW(uint32_t) iemNativeRegFlushPendingWritesSlow(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint64_t fGstShwExcept,
1618	uint64_t fGstSimdShwExcept);
1619	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
1620	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitPcWritebackSlow(PIEMRECOMPILERSTATE pReNative, uint32_t off);
1621	#endif
1622	#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
1623	DECL_HIDDEN_THROW(uint32_t) iemNativeRegFlushPendingWrite(PIEMRECOMPILERSTATE pReNative, uint32_t off, IEMNATIVEGSTREG enmGstReg);
1624	DECL_HIDDEN_THROW(uint32_t) iemNativeRegFlushDirtyGuest(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint64_t fFlushGstReg = UINT64_MAX);
1625	DECL_HIDDEN_THROW(uint32_t) iemNativeRegFlushDirtyGuestByHostRegShadow(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxHstReg);
1626	#endif
1627
1628
1629	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1630	DECL_HIDDEN_THROW(uint8_t) iemNativeSimdRegAllocTmp(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, bool fPreferVolatile = true);
1631	DECL_HIDDEN_THROW(uint8_t) iemNativeSimdRegAllocTmpEx(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint32_t fRegMask,
1632	bool fPreferVolatile = true);
1633	DECL_HIDDEN_THROW(uint8_t) iemNativeSimdRegAllocTmpForGuestSimdReg(PIEMRECOMPILERSTATE pReNative, uint32_t *poff,
1634	IEMNATIVEGSTSIMDREG enmGstSimdReg,
1635	IEMNATIVEGSTSIMDREGLDSTSZ enmLoadSz,
1636	IEMNATIVEGSTREGUSE enmIntendedUse = kIemNativeGstRegUse_ReadOnly,
1637	bool fNoVolatileRegs = false);
1638	DECLHIDDEN(void) iemNativeSimdRegFreeTmp(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstSimdReg) RT_NOEXCEPT;
1639	DECLHIDDEN(void) iemNativeSimdRegFlushGuestShadows(PIEMRECOMPILERSTATE pReNative, uint64_t fGstSimdRegs) RT_NOEXCEPT;
1640	DECL_HIDDEN_THROW(uint32_t) iemNativeSimdRegFlushPendingWrite(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1641	IEMNATIVEGSTSIMDREG enmGstSimdReg);
1642	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitLoadSimdRegWithGstShadowSimdReg(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1643	uint8_t idxHstSimdReg, IEMNATIVEGSTSIMDREG enmGstSimdReg,
1644	IEMNATIVEGSTSIMDREGLDSTSZ enmLoadSz);
1645	#endif
1646
1647	DECL_HIDDEN_THROW(uint8_t) iemNativeArgAlloc(PIEMRECOMPILERSTATE pReNative, uint8_t iArgNo, uint8_t cbType);
1648	DECL_HIDDEN_THROW(uint8_t) iemNativeArgAllocConst(PIEMRECOMPILERSTATE pReNative, uint8_t iArgNo, uint8_t cbType, uint64_t uValue);
1649	DECL_HIDDEN_THROW(uint8_t) iemNativeArgAllocLocalRef(PIEMRECOMPILERSTATE pReNative, uint8_t iArgNo, uint8_t idxOtherVar);
1650	DECL_HIDDEN_THROW(uint8_t) iemNativeVarAlloc(PIEMRECOMPILERSTATE pReNative, uint8_t cbType);
1651	DECL_HIDDEN_THROW(uint8_t) iemNativeVarAllocConst(PIEMRECOMPILERSTATE pReNative, uint8_t cbType, uint64_t uValue);
1652	DECL_HIDDEN_THROW(uint8_t) iemNativeVarAllocAssign(PIEMRECOMPILERSTATE pReNative, uint32_t *poff, uint8_t cbType, uint8_t idxVarOther);
1653	DECL_HIDDEN_THROW(void) iemNativeVarSetKindToStack(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar);
1654	DECL_HIDDEN_THROW(void) iemNativeVarSetKindToConst(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, uint64_t uValue);
1655	DECL_HIDDEN_THROW(void) iemNativeVarSetKindToGstRegRef(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar,
1656	IEMNATIVEGSTREGREF enmRegClass, uint8_t idxReg);
1657	DECL_HIDDEN_THROW(uint8_t) iemNativeVarGetStackSlot(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar);
1658	DECL_HIDDEN_THROW(uint8_t) iemNativeVarRegisterAcquire(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, uint32_t *poff,
1659	bool fInitialized = false, uint8_t idxRegPref = UINT8_MAX);
1660	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1661	DECL_HIDDEN_THROW(uint8_t) iemNativeVarSimdRegisterAcquire(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar, uint32_t *poff,
1662	bool fInitialized = false, uint8_t idxRegPref = UINT8_MAX);
1663	#endif
1664	DECL_HIDDEN_THROW(uint8_t) iemNativeVarRegisterAcquireForGuestReg(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar,
1665	IEMNATIVEGSTREG enmGstReg, uint32_t *poff);
1666	DECL_HIDDEN_THROW(uint32_t) iemNativeVarSaveVolatileRegsPreHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1667	uint32_t fHstRegsNotToSave);
1668	DECL_HIDDEN_THROW(uint32_t) iemNativeVarRestoreVolatileRegsPostHlpCall(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1669	uint32_t fHstRegsNotToSave);
1670	DECLHIDDEN(void) iemNativeVarFreeOneWorker(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar);
1671	DECLHIDDEN(void) iemNativeVarFreeAllSlow(PIEMRECOMPILERSTATE pReNative, uint32_t bmVars);
1672
1673	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitLoadGprWithGstShadowReg(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1674	uint8_t idxHstReg, IEMNATIVEGSTREG enmGstReg);
1675	#ifdef VBOX_STRICT
1676	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitTop32BitsClearCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxReg);
1677	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitGuestRegValueCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxReg,
1678	IEMNATIVEGSTREG enmGstReg);
1679	# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1680	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitGuestSimdRegValueCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxSimdReg,
1681	IEMNATIVEGSTSIMDREG enmGstSimdReg,
1682	IEMNATIVEGSTSIMDREGLDSTSZ enmLoadSz);
1683	# endif
1684	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitExecFlagsCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fExec);
1685	#endif
1686	#ifdef IEMNATIVE_STRICT_EFLAGS_SKIPPING
1687	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitEFlagsSkippingCheck(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t fEflNeeded);
1688	#endif
1689	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitCheckCallRetAndPassUp(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr);
1690	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitCallCommon(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t cArgs, uint8_t cHiddenArgs, bool fFlushPendingWrites = true);
1691	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitCImplCall(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxInstr,
1692	uint64_t fGstShwFlush, uintptr_t pfnCImpl, uint8_t cbInstr, uint8_t cAddParams,
1693	uint64_t uParam0, uint64_t uParam1, uint64_t uParam2);
1694	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitThreadedCall(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1695	PCIEMTHRDEDCALLENTRY pCallEntry);
1696	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitCheckGprCanonicalMaybeRaiseGp0(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1697	uint8_t idxAddrReg, uint8_t idxInstr);
1698	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitCheckGpr32AgainstCsSegLimitMaybeRaiseGp0(PIEMRECOMPILERSTATE pReNative, uint32_t off,
1699	uint8_t idxAddrReg, uint8_t idxInstr);
1700	DECL_HIDDEN_THROW(uint32_t) iemNativeEmitLeaGprByGstRegRef(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint8_t idxGprDst,
1701	IEMNATIVEGSTREGREF enmClass, uint8_t idxRegInClass);
1702
1703
1704	IEM_DECL_NATIVE_HLP_PROTO(int, iemNativeHlpExecStatusCodeFiddling,(PVMCPUCC pVCpu, int rc, uint8_t idxInstr));
1705	IEM_DECL_NATIVE_HLP_PROTO(int, iemNativeHlpExecRaiseGp0,(PVMCPUCC pVCpu));
1706	IEM_DECL_NATIVE_HLP_PROTO(int, iemNativeHlpExecRaiseNm,(PVMCPUCC pVCpu));
1707	IEM_DECL_NATIVE_HLP_PROTO(int, iemNativeHlpExecRaiseUd,(PVMCPUCC pVCpu));
1708	IEM_DECL_NATIVE_HLP_PROTO(int, iemNativeHlpExecRaiseMf,(PVMCPUCC pVCpu));
1709	IEM_DECL_NATIVE_HLP_PROTO(int, iemNativeHlpExecRaiseXf,(PVMCPUCC pVCpu));
1710	IEM_DECL_NATIVE_HLP_PROTO(int, iemNativeHlpExecRaiseDe,(PVMCPUCC pVCpu));
1711	IEM_DECL_NATIVE_HLP_PROTO(int, iemNativeHlpObsoleteTb,(PVMCPUCC pVCpu));
1712	IEM_DECL_NATIVE_HLP_PROTO(int, iemNativeHlpNeedCsLimChecking,(PVMCPUCC pVCpu));
1713	IEM_DECL_NATIVE_HLP_PROTO(int, iemNativeHlpCheckBranchMiss,(PVMCPUCC pVCpu));
1714
1715	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFetchDataU8,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg));
1716	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFetchDataU8_Sx_U16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg));
1717	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFetchDataU8_Sx_U32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg));
1718	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFetchDataU8_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg));
1719	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFetchDataU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg));
1720	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFetchDataU16_Sx_U32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg));
1721	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFetchDataU16_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg));
1722	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFetchDataU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg));
1723	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFetchDataU32_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg));
1724	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFetchDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg));
1725	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1726	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFetchDataU128,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PRTUINT128U pu128Dst));
1727	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFetchDataU128AlignedSse,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PRTUINT128U pu128Dst));
1728	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFetchDataU128NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PRTUINT128U pu128Dst));
1729	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFetchDataU256NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PRTUINT256U pu256Dst));
1730	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFetchDataU256AlignedAvx,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PRTUINT256U pu256Dst));
1731	#endif
1732	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemStoreDataU8,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint8_t u8Value));
1733	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemStoreDataU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint16_t u16Value));
1734	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemStoreDataU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint32_t u32Value));
1735	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemStoreDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, uint64_t u64Value));
1736	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1737	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemStoreDataU128AlignedSse,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PCRTUINT128U pu128Src));
1738	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemStoreDataU128NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PCRTUINT128U pu128Src));
1739	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemStoreDataU256NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PCRTUINT256U pu256Src));
1740	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemStoreDataU256AlignedAvx,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t iSegReg, PCRTUINT256U pu256Src));
1741	#endif
1742	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpStackStoreU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t u16Value));
1743	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpStackStoreU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value));
1744	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpStackStoreU32SReg,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value));
1745	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpStackStoreU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t u64Value));
1746	IEM_DECL_NATIVE_HLP_PROTO(uint16_t, iemNativeHlpStackFetchU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
1747	IEM_DECL_NATIVE_HLP_PROTO(uint32_t, iemNativeHlpStackFetchU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
1748	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpStackFetchU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
1749
1750	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFlatFetchDataU8,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
1751	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFlatFetchDataU8_Sx_U16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
1752	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFlatFetchDataU8_Sx_U32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
1753	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFlatFetchDataU8_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
1754	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFlatFetchDataU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
1755	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFlatFetchDataU16_Sx_U32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
1756	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFlatFetchDataU16_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
1757	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFlatFetchDataU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
1758	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFlatFetchDataU32_Sx_U64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
1759	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpMemFlatFetchDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
1760	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1761	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFlatFetchDataU128,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PRTUINT128U pu128Dst));
1762	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFlatFetchDataU128AlignedSse,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PRTUINT128U pu128Dst));
1763	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFlatFetchDataU128NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PRTUINT128U pu128Dst));
1764	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFlatFetchDataU256NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PRTUINT256U pu256Dst));
1765	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFlatFetchDataU256AlignedAvx,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PRTUINT256U pu256Dst));
1766	#endif
1767	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFlatStoreDataU8,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint8_t u8Value));
1768	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFlatStoreDataU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t u16Value));
1769	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFlatStoreDataU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value));
1770	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFlatStoreDataU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t u64Value));
1771	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1772	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFlatStoreDataU128AlignedSse,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PCRTUINT128U pu128Src));
1773	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFlatStoreDataU128NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PCRTUINT128U pu128Src));
1774	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFlatStoreDataU256NoAc,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PCRTUINT256U pu256Src));
1775	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemFlatStoreDataU256AlignedAvx,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, PCRTUINT256U pu256Src));
1776	#endif
1777	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpStackFlatStoreU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint16_t u16Value));
1778	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpStackFlatStoreU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value));
1779	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpStackFlatStoreU32SReg,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t u32Value));
1780	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpStackFlatStoreU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint64_t u64Value));
1781	IEM_DECL_NATIVE_HLP_PROTO(uint16_t, iemNativeHlpStackFlatFetchU16,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
1782	IEM_DECL_NATIVE_HLP_PROTO(uint32_t, iemNativeHlpStackFlatFetchU32,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
1783	IEM_DECL_NATIVE_HLP_PROTO(uint64_t, iemNativeHlpStackFlatFetchU64,(PVMCPUCC pVCpu, RTGCPTR GCPtrMem));
1784
1785	IEM_DECL_NATIVE_HLP_PROTO(uint8_t , iemNativeHlpMemMapDataU8Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1786	IEM_DECL_NATIVE_HLP_PROTO(uint8_t , iemNativeHlpMemMapDataU8Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1787	IEM_DECL_NATIVE_HLP_PROTO(uint8_t , iemNativeHlpMemMapDataU8Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1788	IEM_DECL_NATIVE_HLP_PROTO(uint8_t const , iemNativeHlpMemMapDataU8Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1789	IEM_DECL_NATIVE_HLP_PROTO(uint16_t , iemNativeHlpMemMapDataU16Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1790	IEM_DECL_NATIVE_HLP_PROTO(uint16_t , iemNativeHlpMemMapDataU16Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1791	IEM_DECL_NATIVE_HLP_PROTO(uint16_t , iemNativeHlpMemMapDataU16Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1792	IEM_DECL_NATIVE_HLP_PROTO(uint16_t const , iemNativeHlpMemMapDataU16Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1793	IEM_DECL_NATIVE_HLP_PROTO(uint32_t , iemNativeHlpMemMapDataU32Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1794	IEM_DECL_NATIVE_HLP_PROTO(uint32_t , iemNativeHlpMemMapDataU32Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1795	IEM_DECL_NATIVE_HLP_PROTO(uint32_t , iemNativeHlpMemMapDataU32Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1796	IEM_DECL_NATIVE_HLP_PROTO(uint32_t const , iemNativeHlpMemMapDataU32Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1797	IEM_DECL_NATIVE_HLP_PROTO(uint64_t , iemNativeHlpMemMapDataU64Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1798	IEM_DECL_NATIVE_HLP_PROTO(uint64_t , iemNativeHlpMemMapDataU64Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1799	IEM_DECL_NATIVE_HLP_PROTO(uint64_t , iemNativeHlpMemMapDataU64Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1800	IEM_DECL_NATIVE_HLP_PROTO(uint64_t const , iemNativeHlpMemMapDataU64Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1801	IEM_DECL_NATIVE_HLP_PROTO(RTFLOAT80U , iemNativeHlpMemMapDataR80Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1802	IEM_DECL_NATIVE_HLP_PROTO(RTPBCD80U , iemNativeHlpMemMapDataD80Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1803	IEM_DECL_NATIVE_HLP_PROTO(RTUINT128U , iemNativeHlpMemMapDataU128Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1804	IEM_DECL_NATIVE_HLP_PROTO(RTUINT128U , iemNativeHlpMemMapDataU128Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1805	IEM_DECL_NATIVE_HLP_PROTO(RTUINT128U , iemNativeHlpMemMapDataU128Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1806	IEM_DECL_NATIVE_HLP_PROTO(RTUINT128U const , iemNativeHlpMemMapDataU128Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem, uint8_t iSegReg));
1807
1808	IEM_DECL_NATIVE_HLP_PROTO(uint8_t , iemNativeHlpMemFlatMapDataU8Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1809	IEM_DECL_NATIVE_HLP_PROTO(uint8_t , iemNativeHlpMemFlatMapDataU8Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1810	IEM_DECL_NATIVE_HLP_PROTO(uint8_t , iemNativeHlpMemFlatMapDataU8Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1811	IEM_DECL_NATIVE_HLP_PROTO(uint8_t const , iemNativeHlpMemFlatMapDataU8Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1812	IEM_DECL_NATIVE_HLP_PROTO(uint16_t , iemNativeHlpMemFlatMapDataU16Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1813	IEM_DECL_NATIVE_HLP_PROTO(uint16_t , iemNativeHlpMemFlatMapDataU16Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1814	IEM_DECL_NATIVE_HLP_PROTO(uint16_t , iemNativeHlpMemFlatMapDataU16Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1815	IEM_DECL_NATIVE_HLP_PROTO(uint16_t const , iemNativeHlpMemFlatMapDataU16Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1816	IEM_DECL_NATIVE_HLP_PROTO(uint32_t , iemNativeHlpMemFlatMapDataU32Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1817	IEM_DECL_NATIVE_HLP_PROTO(uint32_t , iemNativeHlpMemFlatMapDataU32Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1818	IEM_DECL_NATIVE_HLP_PROTO(uint32_t , iemNativeHlpMemFlatMapDataU32Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1819	IEM_DECL_NATIVE_HLP_PROTO(uint32_t const , iemNativeHlpMemFlatMapDataU32Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1820	IEM_DECL_NATIVE_HLP_PROTO(uint64_t , iemNativeHlpMemFlatMapDataU64Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1821	IEM_DECL_NATIVE_HLP_PROTO(uint64_t , iemNativeHlpMemFlatMapDataU64Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1822	IEM_DECL_NATIVE_HLP_PROTO(uint64_t , iemNativeHlpMemFlatMapDataU64Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1823	IEM_DECL_NATIVE_HLP_PROTO(uint64_t const , iemNativeHlpMemFlatMapDataU64Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1824	IEM_DECL_NATIVE_HLP_PROTO(RTFLOAT80U , iemNativeHlpMemFlatMapDataR80Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1825	IEM_DECL_NATIVE_HLP_PROTO(RTPBCD80U , iemNativeHlpMemFlatMapDataD80Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1826	IEM_DECL_NATIVE_HLP_PROTO(RTUINT128U , iemNativeHlpMemFlatMapDataU128Atomic,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1827	IEM_DECL_NATIVE_HLP_PROTO(RTUINT128U , iemNativeHlpMemFlatMapDataU128Rw,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1828	IEM_DECL_NATIVE_HLP_PROTO(RTUINT128U , iemNativeHlpMemFlatMapDataU128Wo,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1829	IEM_DECL_NATIVE_HLP_PROTO(RTUINT128U const , iemNativeHlpMemFlatMapDataU128Ro,(PVMCPUCC pVCpu, uint8_t pbUnmapInfo, RTGCPTR GCPtrMem));
1830
1831	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemCommitAndUnmapAtomic,(PVMCPUCC pVCpu, uint8_t bUnmapInfo));
1832	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemCommitAndUnmapRw,(PVMCPUCC pVCpu, uint8_t bUnmapInfo));
1833	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemCommitAndUnmapWo,(PVMCPUCC pVCpu, uint8_t bUnmapInfo));
1834	IEM_DECL_NATIVE_HLP_PROTO(void, iemNativeHlpMemCommitAndUnmapRo,(PVMCPUCC pVCpu, uint8_t bUnmapInfo));
1835
1836
1837	/**
1838	* Info about shadowed guest register values.
1839	* @see IEMNATIVEGSTREG
1840	*/
1841	typedef struct IEMANTIVEGSTREGINFO
1842	{
1843	/** Offset in VMCPU. */
1844	uint32_t off;
1845	/** The field size. */
1846	uint8_t cb;
1847	/** Name (for logging). */
1848	const char *pszName;
1849	} IEMANTIVEGSTREGINFO;
1850	extern DECL_HIDDEN_DATA(IEMANTIVEGSTREGINFO const) g_aGstShadowInfo[];
1851	extern DECL_HIDDEN_DATA(const char * const) g_apszIemNativeHstRegNames[];
1852	extern DECL_HIDDEN_DATA(int32_t const) g_aoffIemNativeCallStackArgBpDisp[];
1853	extern DECL_HIDDEN_DATA(uint32_t const) g_afIemNativeCallRegs[];
1854	extern DECL_HIDDEN_DATA(uint8_t const) g_aidxIemNativeCallRegs[];
1855
1856
1857
1858	/**
1859	* Ensures that there is sufficient space in the instruction output buffer.
1860	*
1861	* This will reallocate the buffer if needed and allowed.
1862	*
1863	* @note Always use IEMNATIVE_ASSERT_INSTR_BUF_ENSURE when done to check the
1864	* allocation size.
1865	*
1866	* @returns Pointer to the instruction output buffer on success; throws VBox
1867	* status code on failure, so no need to check it.
1868	* @param pReNative The native recompile state.
1869	* @param off Current instruction offset. Works safely for UINT32_MAX
1870	* as well.
1871	* @param cInstrReq Number of instruction about to be added. It's okay to
1872	* overestimate this a bit.
1873	*/
1874	DECL_FORCE_INLINE_THROW(PIEMNATIVEINSTR)
1875	iemNativeInstrBufEnsure(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint32_t cInstrReq)
1876	{
1877	uint64_t const offChecked = off + (uint64_t)cInstrReq; /** @todo may reconsider the need for UINT32_MAX safety... */
1878	if (RT_LIKELY(offChecked <= pReNative->cInstrBufAlloc))
1879	{
1880	#ifdef VBOX_STRICT
1881	pReNative->offInstrBufChecked = offChecked;
1882	#endif
1883	return pReNative->pInstrBuf;
1884	}
1885	return iemNativeInstrBufEnsureSlow(pReNative, off, cInstrReq);
1886	}
1887
1888	/**
1889	* Checks that we didn't exceed the space requested in the last
1890	* iemNativeInstrBufEnsure() call.
1891	*/
1892	#define IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(a_pReNative, a_off) \
1893	AssertMsg((a_off) <= (a_pReNative)->offInstrBufChecked, \
1894	("off=%#x offInstrBufChecked=%#x\n", (a_off), (a_pReNative)->offInstrBufChecked))
1895
1896	/**
1897	* Checks that a variable index is valid.
1898	*/
1899	#ifdef IEMNATIVE_VAR_IDX_MAGIC
1900	# define IEMNATIVE_ASSERT_VAR_IDX(a_pReNative, a_idxVar) \
1901	AssertMsg( ((a_idxVar) & IEMNATIVE_VAR_IDX_MAGIC_MASK) == IEMNATIVE_VAR_IDX_MAGIC \
1902	&& (unsigned)IEMNATIVE_VAR_IDX_UNPACK(a_idxVar) < RT_ELEMENTS((a_pReNative)->Core.aVars) \
1903	&& ((a_pReNative)->Core.bmVars & RT_BIT_32(IEMNATIVE_VAR_IDX_UNPACK(a_idxVar))), \
1904	("%s=%#x\n", #a_idxVar, a_idxVar))
1905	#else
1906	# define IEMNATIVE_ASSERT_VAR_IDX(a_pReNative, a_idxVar) \
1907	AssertMsg( (unsigned)(a_idxVar) < RT_ELEMENTS((a_pReNative)->Core.aVars) \
1908	&& ((a_pReNative)->Core.bmVars & RT_BIT_32(a_idxVar)), ("%s=%d\n", #a_idxVar, a_idxVar))
1909	#endif
1910
1911	/**
1912	* Checks that a variable index is valid and that the variable is assigned the
1913	* correct argument number.
1914	* This also adds a RT_NOREF of a_idxVar.
1915	*/
1916	#ifdef IEMNATIVE_VAR_IDX_MAGIC
1917	# define IEMNATIVE_ASSERT_ARG_VAR_IDX(a_pReNative, a_idxVar, a_uArgNo) do { \
1918	RT_NOREF_PV(a_idxVar); \
1919	AssertMsg( ((a_idxVar) & IEMNATIVE_VAR_IDX_MAGIC_MASK) == IEMNATIVE_VAR_IDX_MAGIC \
1920	&& (unsigned)IEMNATIVE_VAR_IDX_UNPACK(a_idxVar) < RT_ELEMENTS((a_pReNative)->Core.aVars) \
1921	&& ((a_pReNative)->Core.bmVars & RT_BIT_32(IEMNATIVE_VAR_IDX_UNPACK(a_idxVar))) \
1922	&& (a_pReNative)->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVar)].uArgNo == (a_uArgNo), \
1923	("%s=%d; uArgNo=%d, expected %u\n", #a_idxVar, a_idxVar, \
1924	(a_pReNative)->Core.aVars[RT_MIN(IEMNATIVE_VAR_IDX_UNPACK(a_idxVar), \
1925	RT_ELEMENTS((a_pReNative)->Core.aVars)) - 1].uArgNo, \
1926	a_uArgNo)); \
1927	} while (0)
1928	#else
1929	# define IEMNATIVE_ASSERT_ARG_VAR_IDX(a_pReNative, a_idxVar, a_uArgNo) do { \
1930	RT_NOREF_PV(a_idxVar); \
1931	AssertMsg( (unsigned)(a_idxVar) < RT_ELEMENTS((a_pReNative)->Core.aVars) \
1932	&& ((a_pReNative)->Core.bmVars & RT_BIT_32(a_idxVar))\
1933	&& (a_pReNative)->Core.aVars[a_idxVar].uArgNo == (a_uArgNo) \
1934	, ("%s=%d; uArgNo=%d, expected %u\n", #a_idxVar, a_idxVar, \
1935	(a_pReNative)->Core.aVars[RT_MIN(a_idxVar, RT_ELEMENTS((a_pReNative)->Core.aVars)) - 1].uArgNo, a_uArgNo)); \
1936	} while (0)
1937	#endif
1938
1939
1940	/**
1941	* Checks that a variable has the expected size.
1942	*/
1943	#define IEMNATIVE_ASSERT_VAR_SIZE(a_pReNative, a_idxVar, a_cbVar) \
1944	AssertMsg((a_pReNative)->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVar)].cbVar == (a_cbVar), \
1945	("%s=%#x: cbVar=%#x, expected %#x!\n", #a_idxVar, a_idxVar, \
1946	(a_pReNative)->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVar)].cbVar == (a_cbVar)))
1947
1948
1949	/**
1950	* Calculates the stack address of a variable as a [r]BP displacement value.
1951	*/
1952	DECL_FORCE_INLINE(int32_t)
1953	iemNativeStackCalcBpDisp(uint8_t idxStackSlot)
1954	{
1955	Assert(idxStackSlot < IEMNATIVE_FRAME_VAR_SLOTS);
1956	return idxStackSlot * sizeof(uint64_t) + IEMNATIVE_FP_OFF_STACK_VARS;
1957	}
1958
1959
1960	/**
1961	* Releases the variable's register.
1962	*
1963	* The register must have been previously acquired calling
1964	* iemNativeVarRegisterAcquire(), iemNativeVarRegisterAcquireForGuestReg() or
1965	* iemNativeVarRegisterSetAndAcquire().
1966	*/
1967	DECL_INLINE_THROW(void) iemNativeVarRegisterRelease(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar)
1968	{
1969	IEMNATIVE_ASSERT_VAR_IDX(pReNative, idxVar);
1970	Assert(pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].fRegAcquired);
1971	pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].fRegAcquired = false;
1972	}
1973
1974
1975	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
1976	DECL_INLINE_THROW(void) iemNativeVarSimdRegisterRelease(PIEMRECOMPILERSTATE pReNative, uint8_t idxVar)
1977	{
1978	Assert(pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(idxVar)].fSimdReg);
1979	iemNativeVarRegisterRelease(pReNative, idxVar);
1980	}
1981	#endif
1982
1983
1984	/**
1985	* Converts IEM_CIMPL_F_XXX flags into a guest register shadow copy flush mask.
1986	*
1987	* @returns The flush mask.
1988	* @param fCImpl The IEM_CIMPL_F_XXX flags.
1989	* @param fGstShwFlush The starting flush mask.
1990	*/
1991	DECL_FORCE_INLINE(uint64_t) iemNativeCImplFlagsToGuestShadowFlushMask(uint32_t fCImpl, uint64_t fGstShwFlush)
1992	{
1993	if (fCImpl & IEM_CIMPL_F_BRANCH_FAR)
1994	fGstShwFlush \|= RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_CS)
1995	\| RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_CS)
1996	\| RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_CS);
1997	if (fCImpl & IEM_CIMPL_F_BRANCH_STACK_FAR)
1998	fGstShwFlush \|= RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP)
1999	\| RT_BIT_64(kIemNativeGstReg_SegSelFirst + X86_SREG_SS)
2000	\| RT_BIT_64(kIemNativeGstReg_SegBaseFirst + X86_SREG_SS)
2001	\| RT_BIT_64(kIemNativeGstReg_SegLimitFirst + X86_SREG_SS);
2002	else if (fCImpl & IEM_CIMPL_F_BRANCH_STACK)
2003	fGstShwFlush \|= RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xSP);
2004	if (fCImpl & (IEM_CIMPL_F_RFLAGS \| IEM_CIMPL_F_STATUS_FLAGS \| IEM_CIMPL_F_INHIBIT_SHADOW))
2005	fGstShwFlush \|= RT_BIT_64(kIemNativeGstReg_EFlags);
2006	return fGstShwFlush;
2007	}
2008
2009
2010	/** Number of hidden arguments for CIMPL calls.
2011	* @note We're sufferning from the usual VBOXSTRICTRC fun on Windows. */
2012	#if defined(VBOXSTRICTRC_STRICT_ENABLED) && defined(RT_OS_WINDOWS) && defined(RT_ARCH_AMD64)
2013	# define IEM_CIMPL_HIDDEN_ARGS 3
2014	#else
2015	# define IEM_CIMPL_HIDDEN_ARGS 2
2016	#endif
2017
2018
2019	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2020	/** Number of hidden arguments for SSE_AIMPL calls. */
2021	# define IEM_SSE_AIMPL_HIDDEN_ARGS 1
2022	/** Number of hidden arguments for AVX_AIMPL calls. */
2023	# define IEM_AVX_AIMPL_HIDDEN_ARGS 1
2024	#endif
2025
2026
2027	#ifdef IEMNATIVE_WITH_LIVENESS_ANALYSIS
2028
2029	# ifndef IEMLIVENESS_EXTENDED_LAYOUT
2030	/**
2031	* Helper for iemNativeLivenessGetStateByGstReg.
2032	*
2033	* @returns IEMLIVENESS_STATE_XXX
2034	* @param fMergedStateExp2 This is the RT_BIT_32() of each sub-state
2035	* ORed together.
2036	*/
2037	DECL_FORCE_INLINE(uint32_t)
2038	iemNativeLivenessMergeExpandedEFlagsState(uint32_t fMergedStateExp2)
2039	{
2040	/* INPUT trumps anything else. */
2041	if (fMergedStateExp2 & RT_BIT_32(IEMLIVENESS_STATE_INPUT))
2042	return IEMLIVENESS_STATE_INPUT;
2043
2044	/* CLOBBERED trumps XCPT_OR_CALL and UNUSED. */
2045	if (fMergedStateExp2 & RT_BIT_32(IEMLIVENESS_STATE_CLOBBERED))
2046	{
2047	/* If not all sub-fields are clobbered they must be considered INPUT. */
2048	if (fMergedStateExp2 & (RT_BIT_32(IEMLIVENESS_STATE_UNUSED) \| RT_BIT_32(IEMLIVENESS_STATE_XCPT_OR_CALL)))
2049	return IEMLIVENESS_STATE_INPUT;
2050	return IEMLIVENESS_STATE_CLOBBERED;
2051	}
2052
2053	/* XCPT_OR_CALL trumps UNUSED. */
2054	if (fMergedStateExp2 & RT_BIT_32(IEMLIVENESS_STATE_XCPT_OR_CALL))
2055	return IEMLIVENESS_STATE_XCPT_OR_CALL;
2056
2057	return IEMLIVENESS_STATE_UNUSED;
2058	}
2059	# endif /* !IEMLIVENESS_EXTENDED_LAYOUT */
2060
2061
2062	DECL_FORCE_INLINE(uint32_t)
2063	iemNativeLivenessGetStateByGstRegEx(PCIEMLIVENESSENTRY pLivenessEntry, unsigned enmGstRegEx)
2064	{
2065	# ifndef IEMLIVENESS_EXTENDED_LAYOUT
2066	return ((pLivenessEntry->Bit0.bm64 >> enmGstRegEx) & 1)
2067	\| (((pLivenessEntry->Bit1.bm64 >> enmGstRegEx) << 1) & 2);
2068	# else
2069	return ( (pLivenessEntry->Bit0.bm64 >> enmGstRegEx) & 1)
2070	\| (((pLivenessEntry->Bit1.bm64 >> enmGstRegEx) << 1) & 2)
2071	\| (((pLivenessEntry->Bit2.bm64 >> enmGstRegEx) << 2) & 4)
2072	\| (((pLivenessEntry->Bit3.bm64 >> enmGstRegEx) << 2) & 8);
2073	# endif
2074	}
2075
2076
2077	DECL_FORCE_INLINE(uint32_t)
2078	iemNativeLivenessGetStateByGstReg(PCIEMLIVENESSENTRY pLivenessEntry, IEMNATIVEGSTREG enmGstReg)
2079	{
2080	uint32_t uRet = iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, (unsigned)enmGstReg);
2081	if (enmGstReg == kIemNativeGstReg_EFlags)
2082	{
2083	/* Merge the eflags states to one. */
2084	# ifndef IEMLIVENESS_EXTENDED_LAYOUT
2085	uRet = RT_BIT_32(uRet);
2086	uRet \|= RT_BIT_32(pLivenessEntry->Bit0.fEflCf \| (pLivenessEntry->Bit1.fEflCf << 1));
2087	uRet \|= RT_BIT_32(pLivenessEntry->Bit0.fEflPf \| (pLivenessEntry->Bit1.fEflPf << 1));
2088	uRet \|= RT_BIT_32(pLivenessEntry->Bit0.fEflAf \| (pLivenessEntry->Bit1.fEflAf << 1));
2089	uRet \|= RT_BIT_32(pLivenessEntry->Bit0.fEflZf \| (pLivenessEntry->Bit1.fEflZf << 1));
2090	uRet \|= RT_BIT_32(pLivenessEntry->Bit0.fEflSf \| (pLivenessEntry->Bit1.fEflSf << 1));
2091	uRet \|= RT_BIT_32(pLivenessEntry->Bit0.fEflOf \| (pLivenessEntry->Bit1.fEflOf << 1));
2092	uRet = iemNativeLivenessMergeExpandedEFlagsState(uRet);
2093	# else
2094	AssertCompile(IEMLIVENESSBIT_IDX_EFL_OTHER == (unsigned)kIemNativeGstReg_EFlags);
2095	uRet \|= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_CF);
2096	uRet \|= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_PF);
2097	uRet \|= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_AF);
2098	uRet \|= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_ZF);
2099	uRet \|= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_SF);
2100	uRet \|= iemNativeLivenessGetStateByGstRegEx(pLivenessEntry, IEMLIVENESSBIT_IDX_EFL_OF);
2101	# endif
2102	}
2103	return uRet;
2104	}
2105
2106
2107	# ifdef VBOX_STRICT
2108	/** For assertions only, user checks that idxCurCall isn't zerow. */
2109	DECL_FORCE_INLINE(uint32_t)
2110	iemNativeLivenessGetPrevStateByGstReg(PIEMRECOMPILERSTATE pReNative, IEMNATIVEGSTREG enmGstReg)
2111	{
2112	return iemNativeLivenessGetStateByGstReg(&pReNative->paLivenessEntries[pReNative->idxCurCall - 1], enmGstReg);
2113	}
2114	# endif /* VBOX_STRICT */
2115
2116	#endif /* IEMNATIVE_WITH_LIVENESS_ANALYSIS */
2117
2118
2119	/**
2120	* Gets the number of hidden arguments for an expected IEM_MC_CALL statement.
2121	*/
2122	DECL_FORCE_INLINE(uint8_t) iemNativeArgGetHiddenArgCount(PIEMRECOMPILERSTATE pReNative)
2123	{
2124	if (pReNative->fCImpl & IEM_CIMPL_F_CALLS_CIMPL)
2125	return IEM_CIMPL_HIDDEN_ARGS;
2126	if (pReNative->fCImpl & (IEM_CIMPL_F_CALLS_AIMPL_WITH_FXSTATE \| IEM_CIMPL_F_CALLS_AIMPL_WITH_XSTATE))
2127	return 1;
2128	return 0;
2129	}
2130
2131
2132	DECL_FORCE_INLINE(uint8_t) iemNativeRegMarkAllocated(PIEMRECOMPILERSTATE pReNative, unsigned idxReg,
2133	IEMNATIVEWHAT enmWhat, uint8_t idxVar = UINT8_MAX) RT_NOEXCEPT
2134	{
2135	pReNative->Core.bmHstRegs \|= RT_BIT_32(idxReg);
2136
2137	pReNative->Core.aHstRegs[idxReg].enmWhat = enmWhat;
2138	pReNative->Core.aHstRegs[idxReg].fGstRegShadows = 0;
2139	pReNative->Core.aHstRegs[idxReg].idxVar = idxVar;
2140	return (uint8_t)idxReg;
2141	}
2142
2143
2144
2145	/*********************************************************************************************************************************
2146	* Register Allocator (GPR) *
2147	*********************************************************************************************************************************/
2148
2149	/**
2150	* Marks host register @a idxHstReg as containing a shadow copy of guest
2151	* register @a enmGstReg.
2152	*
2153	* ASSUMES that caller has made sure @a enmGstReg is not associated with any
2154	* host register before calling.
2155	*/
2156	DECL_FORCE_INLINE(void)
2157	iemNativeRegMarkAsGstRegShadow(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg, IEMNATIVEGSTREG enmGstReg, uint32_t off)
2158	{
2159	Assert(!(pReNative->Core.bmGstRegShadows & RT_BIT_64(enmGstReg)));
2160	Assert(!pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows);
2161	Assert((unsigned)enmGstReg < (unsigned)kIemNativeGstReg_End);
2162
2163	pReNative->Core.aidxGstRegShadows[enmGstReg] = idxHstReg;
2164	pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = RT_BIT_64(enmGstReg); /** @todo why? not OR? */
2165	pReNative->Core.bmGstRegShadows \|= RT_BIT_64(enmGstReg);
2166	pReNative->Core.bmHstRegsWithGstShadow \|= RT_BIT_32(idxHstReg);
2167	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2168	iemNativeDbgInfoAddNativeOffset(pReNative, off);
2169	iemNativeDbgInfoAddGuestRegShadowing(pReNative, enmGstReg, idxHstReg);
2170	#else
2171	RT_NOREF(off);
2172	#endif
2173	}
2174
2175
2176	/**
2177	* Clear any guest register shadow claims from @a idxHstReg.
2178	*
2179	* The register does not need to be shadowing any guest registers.
2180	*/
2181	DECL_FORCE_INLINE(void)
2182	iemNativeRegClearGstRegShadowing(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg, uint32_t off)
2183	{
2184	Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows)
2185	== pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows
2186	&& pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
2187	Assert( RT_BOOL(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxHstReg))
2188	== RT_BOOL(pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows));
2189	#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
2190	Assert(!(pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows & pReNative->Core.bmGstRegShadowDirty));
2191	#endif
2192
2193	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2194	uint64_t fGstRegs = pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows;
2195	if (fGstRegs)
2196	{
2197	Assert(fGstRegs < RT_BIT_64(kIemNativeGstReg_End));
2198	iemNativeDbgInfoAddNativeOffset(pReNative, off);
2199	while (fGstRegs)
2200	{
2201	unsigned const iGstReg = ASMBitFirstSetU64(fGstRegs) - 1;
2202	fGstRegs &= ~RT_BIT_64(iGstReg);
2203	iemNativeDbgInfoAddGuestRegShadowing(pReNative, (IEMNATIVEGSTREG)iGstReg, UINT8_MAX, idxHstReg);
2204	}
2205	}
2206	#else
2207	RT_NOREF(off);
2208	#endif
2209
2210	pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxHstReg);
2211	pReNative->Core.bmGstRegShadows &= ~pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows;
2212	pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = 0;
2213	}
2214
2215
2216	/**
2217	* Clear guest register shadow claim regarding @a enmGstReg from @a idxHstReg
2218	* and global overview flags.
2219	*/
2220	DECL_FORCE_INLINE(void)
2221	iemNativeRegClearGstRegShadowingOne(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstReg, IEMNATIVEGSTREG enmGstReg, uint32_t off)
2222	{
2223	Assert(pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
2224	Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows)
2225	== pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows
2226	&& pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
2227	Assert(pReNative->Core.bmGstRegShadows & RT_BIT_64(enmGstReg));
2228	Assert(pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows & RT_BIT_64(enmGstReg));
2229	Assert(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxHstReg));
2230	#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
2231	Assert(!(pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows & pReNative->Core.bmGstRegShadowDirty));
2232	#endif
2233
2234	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2235	iemNativeDbgInfoAddNativeOffset(pReNative, off);
2236	iemNativeDbgInfoAddGuestRegShadowing(pReNative, enmGstReg, UINT8_MAX, idxHstReg);
2237	#else
2238	RT_NOREF(off);
2239	#endif
2240
2241	uint64_t const fGstRegShadowsNew = pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows & ~RT_BIT_64(enmGstReg);
2242	pReNative->Core.aHstRegs[idxHstReg].fGstRegShadows = fGstRegShadowsNew;
2243	if (!fGstRegShadowsNew)
2244	pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxHstReg);
2245	pReNative->Core.bmGstRegShadows &= ~RT_BIT_64(enmGstReg);
2246	}
2247
2248
2249	#if 0 /* unused */
2250	/**
2251	* Clear any guest register shadow claim for @a enmGstReg.
2252	*/
2253	DECL_FORCE_INLINE(void)
2254	iemNativeRegClearGstRegShadowingByGstReg(PIEMRECOMPILERSTATE pReNative, IEMNATIVEGSTREG enmGstReg, uint32_t off)
2255	{
2256	Assert(pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
2257	if (pReNative->Core.bmGstRegShadows & RT_BIT_64(enmGstReg))
2258	{
2259	Assert(pReNative->Core.aidxGstRegShadows[enmGstReg] < RT_ELEMENTS(pReNative->Core.aHstRegs));
2260	iemNativeRegClearGstRegShadowingOne(pReNative, pReNative->Core.aidxGstRegShadows[enmGstReg], enmGstReg, off);
2261	}
2262	}
2263	#endif
2264
2265
2266	/**
2267	* Clear any guest register shadow claim for @a enmGstReg and mark @a idxHstRegNew
2268	* as the new shadow of it.
2269	*
2270	* Unlike the other guest reg shadow helpers, this does the logging for you.
2271	* However, it is the liveness state is not asserted here, the caller must do
2272	* that.
2273	*/
2274	DECL_FORCE_INLINE(void)
2275	iemNativeRegClearAndMarkAsGstRegShadow(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstRegNew,
2276	IEMNATIVEGSTREG enmGstReg, uint32_t off)
2277	{
2278	Assert(pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
2279	if (pReNative->Core.bmGstRegShadows & RT_BIT_64(enmGstReg))
2280	{
2281	uint8_t const idxHstRegOld = pReNative->Core.aidxGstRegShadows[enmGstReg];
2282	Assert(idxHstRegOld < RT_ELEMENTS(pReNative->Core.aHstRegs));
2283	if (idxHstRegOld == idxHstRegNew)
2284	return;
2285	Log12(("iemNativeRegClearAndMarkAsGstRegShadow: %s for guest %s (from %s)\n", g_apszIemNativeHstRegNames[idxHstRegNew],
2286	g_aGstShadowInfo[enmGstReg].pszName, g_apszIemNativeHstRegNames[idxHstRegOld]));
2287	iemNativeRegClearGstRegShadowingOne(pReNative, pReNative->Core.aidxGstRegShadows[enmGstReg], enmGstReg, off);
2288	}
2289	else
2290	Log12(("iemNativeRegClearAndMarkAsGstRegShadow: %s for guest %s\n", g_apszIemNativeHstRegNames[idxHstRegNew],
2291	g_aGstShadowInfo[enmGstReg].pszName));
2292	iemNativeRegMarkAsGstRegShadow(pReNative, idxHstRegNew, enmGstReg, off);
2293	}
2294
2295
2296	/**
2297	* Transfers the guest register shadow claims of @a enmGstReg from @a idxRegFrom
2298	* to @a idxRegTo.
2299	*/
2300	DECL_FORCE_INLINE(void)
2301	iemNativeRegTransferGstRegShadowing(PIEMRECOMPILERSTATE pReNative, uint8_t idxRegFrom, uint8_t idxRegTo,
2302	IEMNATIVEGSTREG enmGstReg, uint32_t off)
2303	{
2304	Assert(pReNative->Core.aHstRegs[idxRegFrom].fGstRegShadows & RT_BIT_64(enmGstReg));
2305	Assert(pReNative->Core.aidxGstRegShadows[enmGstReg] == idxRegFrom);
2306	Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxRegFrom].fGstRegShadows)
2307	== pReNative->Core.aHstRegs[idxRegFrom].fGstRegShadows
2308	&& pReNative->Core.bmGstRegShadows < RT_BIT_64(kIemNativeGstReg_End));
2309	Assert( (pReNative->Core.bmGstRegShadows & pReNative->Core.aHstRegs[idxRegTo].fGstRegShadows)
2310	== pReNative->Core.aHstRegs[idxRegTo].fGstRegShadows);
2311	Assert( RT_BOOL(pReNative->Core.bmHstRegsWithGstShadow & RT_BIT_32(idxRegFrom))
2312	== RT_BOOL(pReNative->Core.aHstRegs[idxRegFrom].fGstRegShadows));
2313
2314	uint64_t const fGstRegShadowsFrom = pReNative->Core.aHstRegs[idxRegFrom].fGstRegShadows & ~RT_BIT_64(enmGstReg);
2315	pReNative->Core.aHstRegs[idxRegFrom].fGstRegShadows = fGstRegShadowsFrom;
2316	if (!fGstRegShadowsFrom)
2317	pReNative->Core.bmHstRegsWithGstShadow &= ~RT_BIT_32(idxRegFrom);
2318	pReNative->Core.bmHstRegsWithGstShadow \|= RT_BIT_32(idxRegTo);
2319	pReNative->Core.aHstRegs[idxRegTo].fGstRegShadows \|= RT_BIT_64(enmGstReg);
2320	pReNative->Core.aidxGstRegShadows[enmGstReg] = idxRegTo;
2321	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2322	iemNativeDbgInfoAddNativeOffset(pReNative, off);
2323	iemNativeDbgInfoAddGuestRegShadowing(pReNative, enmGstReg, idxRegTo, idxRegFrom);
2324	#else
2325	RT_NOREF(off);
2326	#endif
2327	}
2328
2329
2330	/**
2331	* Flushes any delayed guest register writes.
2332	*
2333	* This must be called prior to calling CImpl functions and any helpers that use
2334	* the guest state (like raising exceptions) and such.
2335	*
2336	* This optimization has not yet been implemented. The first target would be
2337	* RIP updates, since these are the most common ones.
2338	*
2339	* @note This function does not flush any shadowing information for guest registers. This needs to be done by
2340	* the caller if it wishes to do so.
2341	*/
2342	DECL_INLINE_THROW(uint32_t)
2343	iemNativeRegFlushPendingWrites(PIEMRECOMPILERSTATE pReNative, uint32_t off, uint64_t fGstShwExcept = 0, uint64_t fGstSimdShwExcept = 0)
2344	{
2345	#ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
2346	uint64_t const bmGstRegShadowDirty = pReNative->Core.bmGstRegShadowDirty & ~fGstShwExcept;
2347	#else
2348	uint64_t const bmGstRegShadowDirty = 0;
2349	#endif
2350	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2351	uint64_t const bmGstSimdRegShadowDirty = (pReNative->Core.bmGstSimdRegShadowDirtyLo128 \| pReNative->Core.bmGstSimdRegShadowDirtyHi128)
2352	& ~fGstSimdShwExcept;
2353	#else
2354	uint64_t const bmGstSimdRegShadowDirty = 0;
2355	#endif
2356	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
2357	uint64_t const fWritebackPc = ~(fGstShwExcept & kIemNativeGstReg_Pc);
2358	#else
2359	uint64_t const fWritebackPc = 0;
2360	#endif
2361	if (bmGstRegShadowDirty \| bmGstSimdRegShadowDirty \| fWritebackPc)
2362	return iemNativeRegFlushPendingWritesSlow(pReNative, off, fGstShwExcept, fGstSimdShwExcept);
2363
2364	return off;
2365	}
2366
2367
2368
2369	/*********************************************************************************************************************************
2370	* SIMD register allocator (largely code duplication of the GPR allocator for now but might diverge) *
2371	*********************************************************************************************************************************/
2372
2373	#ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
2374
2375	DECL_FORCE_INLINE(uint8_t)
2376	iemNativeSimdRegMarkAllocated(PIEMRECOMPILERSTATE pReNative, uint8_t idxSimdReg,
2377	IEMNATIVEWHAT enmWhat, uint8_t idxVar = UINT8_MAX) RT_NOEXCEPT
2378	{
2379	pReNative->Core.bmHstSimdRegs \|= RT_BIT_32(idxSimdReg);
2380
2381	pReNative->Core.aHstSimdRegs[idxSimdReg].enmWhat = enmWhat;
2382	pReNative->Core.aHstSimdRegs[idxSimdReg].idxVar = idxVar;
2383	pReNative->Core.aHstSimdRegs[idxSimdReg].fGstRegShadows = 0;
2384	return idxSimdReg;
2385	}
2386
2387
2388	/**
2389	* Marks host SIMD register @a idxHstSimdReg as containing a shadow copy of guest
2390	* SIMD register @a enmGstSimdReg.
2391	*
2392	* ASSUMES that caller has made sure @a enmGstSimdReg is not associated with any
2393	* host register before calling.
2394	*/
2395	DECL_FORCE_INLINE(void)
2396	iemNativeSimdRegMarkAsGstSimdRegShadow(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstSimdReg,
2397	IEMNATIVEGSTSIMDREG enmGstSimdReg, uint32_t off)
2398	{
2399	Assert(!(pReNative->Core.bmGstSimdRegShadows & RT_BIT_64(enmGstSimdReg)));
2400	Assert(!pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows);
2401	Assert((unsigned)enmGstSimdReg < (unsigned)kIemNativeGstSimdReg_End);
2402
2403	pReNative->Core.aidxGstSimdRegShadows[enmGstSimdReg] = idxHstSimdReg;
2404	pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows \|= RT_BIT_64(enmGstSimdReg);
2405	pReNative->Core.bmGstSimdRegShadows \|= RT_BIT_64(enmGstSimdReg);
2406	pReNative->Core.bmHstSimdRegsWithGstShadow \|= RT_BIT_32(idxHstSimdReg);
2407	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2408	iemNativeDbgInfoAddNativeOffset(pReNative, off);
2409	iemNativeDbgInfoAddGuestSimdRegShadowing(pReNative, enmGstSimdReg, idxHstSimdReg);
2410	#else
2411	RT_NOREF(off);
2412	#endif
2413	}
2414
2415
2416	/**
2417	* Transfers the guest SIMD register shadow claims of @a enmGstSimdReg from @a idxSimdRegFrom
2418	* to @a idxSimdRegTo.
2419	*/
2420	DECL_FORCE_INLINE(void)
2421	iemNativeSimdRegTransferGstSimdRegShadowing(PIEMRECOMPILERSTATE pReNative, uint8_t idxSimdRegFrom, uint8_t idxSimdRegTo,
2422	IEMNATIVEGSTSIMDREG enmGstSimdReg, uint32_t off)
2423	{
2424	Assert(pReNative->Core.aHstSimdRegs[idxSimdRegFrom].fGstRegShadows & RT_BIT_64(enmGstSimdReg));
2425	Assert(pReNative->Core.aidxGstSimdRegShadows[enmGstSimdReg] == idxSimdRegFrom);
2426	Assert( (pReNative->Core.bmGstSimdRegShadows & pReNative->Core.aHstSimdRegs[idxSimdRegFrom].fGstRegShadows)
2427	== pReNative->Core.aHstSimdRegs[idxSimdRegFrom].fGstRegShadows
2428	&& pReNative->Core.bmGstSimdRegShadows < RT_BIT_64(kIemNativeGstReg_End));
2429	Assert( (pReNative->Core.bmGstSimdRegShadows & pReNative->Core.aHstSimdRegs[idxSimdRegTo].fGstRegShadows)
2430	== pReNative->Core.aHstSimdRegs[idxSimdRegTo].fGstRegShadows);
2431	Assert( RT_BOOL(pReNative->Core.bmHstSimdRegsWithGstShadow & RT_BIT_32(idxSimdRegFrom))
2432	== RT_BOOL(pReNative->Core.aHstSimdRegs[idxSimdRegFrom].fGstRegShadows));
2433	Assert( pReNative->Core.aHstSimdRegs[idxSimdRegFrom].enmLoaded
2434	== pReNative->Core.aHstSimdRegs[idxSimdRegTo].enmLoaded);
2435
2436	uint64_t const fGstRegShadowsFrom = pReNative->Core.aHstSimdRegs[idxSimdRegFrom].fGstRegShadows & ~RT_BIT_64(enmGstSimdReg);
2437	pReNative->Core.aHstSimdRegs[idxSimdRegFrom].fGstRegShadows = fGstRegShadowsFrom;
2438	if (!fGstRegShadowsFrom)
2439	{
2440	pReNative->Core.bmHstSimdRegsWithGstShadow &= ~RT_BIT_32(idxSimdRegFrom);
2441	pReNative->Core.aHstSimdRegs[idxSimdRegFrom].enmLoaded = kIemNativeGstSimdRegLdStSz_Invalid;
2442	}
2443	pReNative->Core.bmHstSimdRegsWithGstShadow \|= RT_BIT_32(idxSimdRegTo);
2444	pReNative->Core.aHstSimdRegs[idxSimdRegTo].fGstRegShadows \|= RT_BIT_64(enmGstSimdReg);
2445	pReNative->Core.aidxGstSimdRegShadows[enmGstSimdReg] = idxSimdRegTo;
2446	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2447	iemNativeDbgInfoAddNativeOffset(pReNative, off);
2448	iemNativeDbgInfoAddGuestSimdRegShadowing(pReNative, enmGstSimdReg, idxSimdRegTo, idxSimdRegFrom);
2449	#else
2450	RT_NOREF(off);
2451	#endif
2452	}
2453
2454
2455	/**
2456	* Clear any guest register shadow claims from @a idxHstSimdReg.
2457	*
2458	* The register does not need to be shadowing any guest registers.
2459	*/
2460	DECL_FORCE_INLINE(void)
2461	iemNativeSimdRegClearGstSimdRegShadowing(PIEMRECOMPILERSTATE pReNative, uint8_t idxHstSimdReg, uint32_t off)
2462	{
2463	Assert( (pReNative->Core.bmGstSimdRegShadows & pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows)
2464	== pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows
2465	&& pReNative->Core.bmGstSimdRegShadows < RT_BIT_64(kIemNativeGstSimdReg_End));
2466	Assert( RT_BOOL(pReNative->Core.bmHstSimdRegsWithGstShadow & RT_BIT_32(idxHstSimdReg))
2467	== RT_BOOL(pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows));
2468	Assert( !(pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows & pReNative->Core.bmGstSimdRegShadowDirtyLo128)
2469	&& !(pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows & pReNative->Core.bmGstSimdRegShadowDirtyHi128));
2470
2471	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
2472	uint64_t fGstRegs = pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows;
2473	if (fGstRegs)
2474	{
2475	Assert(fGstRegs < RT_BIT_64(kIemNativeGstSimdReg_End));
2476	iemNativeDbgInfoAddNativeOffset(pReNative, off);
2477	while (fGstRegs)
2478	{
2479	unsigned const iGstReg = ASMBitFirstSetU64(fGstRegs) - 1;
2480	fGstRegs &= ~RT_BIT_64(iGstReg);
2481	iemNativeDbgInfoAddGuestSimdRegShadowing(pReNative, (IEMNATIVEGSTSIMDREG)iGstReg, UINT8_MAX, idxHstSimdReg);
2482	}
2483	}
2484	#else
2485	RT_NOREF(off);
2486	#endif
2487
2488	pReNative->Core.bmHstSimdRegsWithGstShadow &= ~RT_BIT_32(idxHstSimdReg);
2489	pReNative->Core.bmGstSimdRegShadows &= ~pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows;
2490	pReNative->Core.aHstSimdRegs[idxHstSimdReg].fGstRegShadows = 0;
2491	pReNative->Core.aHstSimdRegs[idxHstSimdReg].enmLoaded = kIemNativeGstSimdRegLdStSz_Invalid;
2492	}
2493
2494	#endif /* IEMNATIVE_WITH_SIMD_REG_ALLOCATOR */
2495
2496
2497	#ifdef IEMNATIVE_WITH_DELAYED_PC_UPDATING
2498	/**
2499	* Emits code to update the guest RIP value by adding the current offset since the start of the last RIP update.
2500	*/
2501	DECL_INLINE_THROW(uint32_t) iemNativeEmitPcWriteback(PIEMRECOMPILERSTATE pReNative, uint32_t off)
2502	{
2503	if (pReNative->Core.offPc)
2504	return iemNativeEmitPcWritebackSlow(pReNative, off);
2505	return off;
2506	}
2507	#endif /* IEMNATIVE_WITH_DELAYED_PC_UPDATING */
2508
2509
2510	#ifdef IEMNATIVE_WITH_RECOMPILER_PROLOGUE_SINGLETON
2511	/** @note iemNativeTbEntry returns VBOXSTRICTRC, but we don't declare it as
2512	* it saves us the trouble of a hidden parameter on MSC/amd64. */
2513	# ifdef RT_ARCH_AMD64
2514	extern "C" IEM_DECL_NATIVE_HLP_DEF(int, iemNativeTbEntry, (PVMCPUCC pVCpu, uintptr_t pfnTbBody));
2515	# elif defined(RT_ARCH_ARM64)
2516	extern "C" IEM_DECL_NATIVE_HLP_DEF(int, iemNativeTbEntry, (PVMCPUCC pVCpu, PCPUMCTX pCpumCtx, uintptr_t pfnTbBody));
2517	# endif
2518	#endif
2519
2520	#endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */
2521
2522	/** @} */
2523
2524	#endif /* !VMM_INCLUDED_SRC_include_IEMN8veRecompiler_h */
2525

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source: vbox/trunk/src/VBox/VMM/include/IEMN8veRecompiler.h@ 104386

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