IEMN8veRecompilerTlbLookup.h@ 102850

Last change on this file since 102850 was 102850, checked in by vboxsync, 11 months ago
VMM/IEM: Implemented the first of two code TLB lookups. bugref:10371
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1	/* $Id: IEMN8veRecompilerTlbLookup.h 102850 2024-01-12 00:47:47Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager - Native Recompiler TLB Lookup Code Emitter.
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMN8veRecompilerTlbLookup_h
29	#define VMM_INCLUDED_SRC_include_IEMN8veRecompilerTlbLookup_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include "IEMN8veRecompiler.h"
35	#include "IEMN8veRecompilerEmit.h"
36
37
38	/** @defgroup grp_iem_n8ve_re_tlblookup Native Recompiler TLB Lookup Code Emitter
39	* @ingroup grp_iem_n8ve_re
40	* @{
41	*/
42
43	/*
44	* TLB Lookup config.
45	*/
46	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_ARM64)
47	# define IEMNATIVE_WITH_TLB_LOOKUP
48	#endif
49	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
50	# define IEMNATIVE_WITH_TLB_LOOKUP_FETCH
51	#endif
52	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
53	# define IEMNATIVE_WITH_TLB_LOOKUP_STORE
54	#endif
55	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
56	# define IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
57	#endif
58	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
59	# define IEMNATIVE_WITH_TLB_LOOKUP_PUSH
60	#endif
61	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
62	# define IEMNATIVE_WITH_TLB_LOOKUP_POP
63	#endif
64
65
66	/**
67	* This must be instantiate before branching off to the lookup code,
68	* so that register spilling and whatnot happens for everyone.
69	*/
70	typedef struct IEMNATIVEEMITTLBSTATE
71	{
72	bool const fSkip;
73	uint8_t const idxRegPtrHlp; /*< We don't support immediate variables with register assignment, so this a tmp reg alloc. /
74	uint8_t const idxRegPtr;
75	uint8_t const idxRegSegBase;
76	uint8_t const idxRegSegLimit;
77	uint8_t const idxRegSegAttrib;
78	uint8_t const idxReg1;
79	uint8_t const idxReg2;
80	#if defined(RT_ARCH_ARM64)
81	uint8_t const idxReg3;
82	#endif
83	uint64_t const uAbsPtr;
84
85	IEMNATIVEEMITTLBSTATE(PIEMRECOMPILERSTATE a_pReNative, uint32_t *a_poff, uint8_t a_idxVarGCPtrMem,
86	uint8_t a_iSegReg, uint8_t a_cbMem, uint8_t a_offDisp = 0)
87	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
88	/* 32-bit and 64-bit wraparound will require special handling, so skip these for absolute addresses. */
89	: fSkip( a_pReNative->Core.aVars[a_idxVarGCPtrMem].enmKind == kIemNativeVarKind_Immediate
90	&& ( (a_pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) != IEMMODE_64BIT
91	? (uint64_t)(UINT32_MAX - a_cbMem - a_offDisp)
92	: (uint64_t)(UINT64_MAX - a_cbMem - a_offDisp))
93	< a_pReNative->Core.aVars[a_idxVarGCPtrMem].u.uValue)
94	#else
95	: fSkip(true)
96	#endif
97	#if defined(RT_ARCH_AMD64) /* got good immediate encoding, otherwise we just load the address in a reg immediately. */
98	, idxRegPtrHlp(UINT8_MAX)
99	#else
100	, idxRegPtrHlp( a_pReNative->Core.aVars[a_idxVarGCPtrMem].enmKind != kIemNativeVarKind_Immediate
101	\|\| fSkip
102	? UINT8_MAX
103	: iemNativeRegAllocTmpImm(a_pReNative, a_poff, a_pReNative->Core.aVars[a_idxVarGCPtrMem].u.uValue) )
104	#endif
105	, idxRegPtr(a_pReNative->Core.aVars[a_idxVarGCPtrMem].enmKind != kIemNativeVarKind_Immediate && !fSkip
106	? iemNativeVarRegisterAcquire(a_pReNative, a_idxVarGCPtrMem, a_poff,
107	true /fInitialized/, IEMNATIVE_CALL_ARG2_GREG)
108	: idxRegPtrHlp)
109	, idxRegSegBase(a_iSegReg == UINT8_MAX \|\| fSkip
110	? UINT8_MAX
111	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_BASE(a_iSegReg)))
112	, idxRegSegLimit((a_iSegReg == UINT8_MAX \|\| (a_pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT) \|\| fSkip
113	? UINT8_MAX
114	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_LIMIT(a_iSegReg)))
115	, idxRegSegAttrib((a_iSegReg == UINT8_MAX \|\| (a_pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT) \|\| fSkip
116	? UINT8_MAX
117	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_ATTRIB(a_iSegReg)))
118	, idxReg1(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
119	, idxReg2(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
120	#if defined(RT_ARCH_ARM64)
121	, idxReg3(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
122	#endif
123	, uAbsPtr( a_pReNative->Core.aVars[a_idxVarGCPtrMem].enmKind != kIemNativeVarKind_Immediate \|\| fSkip
124	? UINT64_MAX
125	: a_pReNative->Core.aVars[a_idxVarGCPtrMem].u.uValue)
126
127	{
128	RT_NOREF(a_cbMem, a_offDisp);
129	}
130
131	/* Alternative constructor for PUSH and POP where we don't have a GCPtrMem
132	variable, only a register derived from the guest RSP. */
133	IEMNATIVEEMITTLBSTATE(PIEMRECOMPILERSTATE a_pReNative, uint8_t a_idxRegPtr, uint32_t *a_poff,
134	uint8_t a_iSegReg, uint8_t a_cbMem)
135	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
136	: fSkip(false)
137	#else
138	: fSkip(true)
139	#endif
140	, idxRegPtrHlp(UINT8_MAX)
141	, idxRegPtr(a_idxRegPtr)
142	, idxRegSegBase(a_iSegReg == UINT8_MAX \|\| fSkip
143	? UINT8_MAX
144	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_BASE(a_iSegReg)))
145	, idxRegSegLimit((a_iSegReg == UINT8_MAX \|\| (a_pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT) \|\| fSkip
146	? UINT8_MAX
147	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_LIMIT(a_iSegReg)))
148	, idxRegSegAttrib((a_iSegReg == UINT8_MAX \|\| (a_pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT) \|\| fSkip
149	? UINT8_MAX
150	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_ATTRIB(a_iSegReg)))
151	, idxReg1(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
152	, idxReg2(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
153	#if defined(RT_ARCH_ARM64)
154	, idxReg3(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
155	#endif
156	, uAbsPtr(UINT64_MAX)
157
158	{
159	RT_NOREF_PV(a_cbMem);
160	}
161
162	/* Alternative constructor for the code TLB lookups where we implictly use RIP
163	variable, only a register derived from the guest RSP. */
164	IEMNATIVEEMITTLBSTATE(PIEMRECOMPILERSTATE a_pReNative, bool a_fFlat, uint32_t *a_poff)
165	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
166	: fSkip(false)
167	#else
168	: fSkip(true)
169	#endif
170	, idxRegPtrHlp(UINT8_MAX)
171	, idxRegPtr(iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, kIemNativeGstReg_Pc))
172	, idxRegSegBase(a_fFlat \|\| fSkip
173	? UINT8_MAX
174	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_BASE(X86_SREG_CS)))
175	, idxRegSegLimit(/*a_fFlat \|\| fSkip
176	? UINT8_MAX
177	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_LIMIT(X86_SREG_CS))*/
178	UINT8_MAX)
179	, idxRegSegAttrib(UINT8_MAX)
180	, idxReg1(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
181	, idxReg2(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
182	#if defined(RT_ARCH_ARM64)
183	, idxReg3(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
184	#endif
185	, uAbsPtr(UINT64_MAX)
186
187	{
188	}
189
190	void freeRegsAndReleaseVars(PIEMRECOMPILERSTATE a_pReNative, uint8_t idxVarGCPtrMem = UINT8_MAX, bool fIsCode = false) const
191	{
192	if (!fIsCode)
193	{
194	if (idxRegPtr != UINT8_MAX)
195	{
196	if (idxRegPtrHlp == UINT8_MAX)
197	{
198	if (idxVarGCPtrMem != UINT8_MAX)
199	iemNativeVarRegisterRelease(a_pReNative, idxVarGCPtrMem);
200	}
201	else
202	{
203	Assert(idxRegPtrHlp == idxRegPtr);
204	iemNativeRegFreeTmpImm(a_pReNative, idxRegPtrHlp);
205	}
206	}
207	else
208	Assert(idxRegPtrHlp == UINT8_MAX);
209	}
210	else
211	{
212	Assert(idxVarGCPtrMem == UINT8_MAX);
213	Assert(idxRegPtrHlp == UINT8_MAX);
214	iemNativeRegFreeTmp(a_pReNative, idxRegPtr); /* RIP */
215	}
216	if (idxRegSegBase != UINT8_MAX)
217	iemNativeRegFreeTmp(a_pReNative, idxRegSegBase);
218	if (idxRegSegLimit != UINT8_MAX)
219	iemNativeRegFreeTmp(a_pReNative, idxRegSegLimit);
220	if (idxRegSegAttrib != UINT8_MAX)
221	iemNativeRegFreeTmp(a_pReNative, idxRegSegAttrib);
222	#if defined(RT_ARCH_ARM64)
223	iemNativeRegFreeTmp(a_pReNative, idxReg3);
224	#endif
225	iemNativeRegFreeTmp(a_pReNative, idxReg2);
226	iemNativeRegFreeTmp(a_pReNative, idxReg1);
227
228	}
229
230	uint32_t getRegsNotToSave() const
231	{
232	if (!fSkip)
233	return RT_BIT_32(idxReg1)
234	\| RT_BIT_32(idxReg2)
235	#if defined(RT_ARCH_ARM64)
236	\| RT_BIT_32(idxReg3)
237	#endif
238	;
239	return 0;
240	}
241
242	/** This is only for avoid assertions. */
243	uint32_t getActiveRegsWithShadows(bool fCode = false) const
244	{
245	#ifdef VBOX_STRICT
246	if (!fSkip)
247	return (idxRegSegBase != UINT8_MAX ? RT_BIT_32(idxRegSegBase) : 0)
248	\| (idxRegSegLimit != UINT8_MAX ? RT_BIT_32(idxRegSegLimit) : 0)
249	\| (idxRegSegAttrib != UINT8_MAX ? RT_BIT_32(idxRegSegAttrib) : 0)
250	\| (fCode ? RT_BIT_32(idxRegPtr) : 0);
251	#endif
252	return 0;
253	}
254	} IEMNATIVEEMITTLBSTATE;
255
256	DECLASM(void) iemNativeHlpAsmSafeWrapCheckTlbLookup(void);
257
258
259	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
260	template<bool const a_fDataTlb>
261	DECL_INLINE_THROW(uint32_t)
262	iemNativeEmitTlbLookup(PIEMRECOMPILERSTATE pReNative, uint32_t off, IEMNATIVEEMITTLBSTATE const * const pTlbState,
263	uint8_t iSegReg, uint8_t cbMem, uint8_t fAlignMask, uint32_t fAccess,
264	uint32_t idxLabelTlbLookup, uint32_t idxLabelTlbMiss, uint8_t idxRegMemResult,
265	uint8_t offDisp = 0)
266	{
267	Assert(!pTlbState->fSkip);
268	uint32_t const offVCpuTlb = a_fDataTlb ? RT_UOFFSETOF(VMCPUCC, iem.s.DataTlb) : RT_UOFFSETOF(VMCPUCC, iem.s.CodeTlb);
269	# if defined(RT_ARCH_AMD64)
270	uint8_t * const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 512);
271	# elif defined(RT_ARCH_ARM64)
272	uint32_t * const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 64);
273	# endif
274
275	/*
276	* The expand down check isn't use all that much, so we emit here to keep
277	* the lookup straighter.
278	*/
279	/* check_expand_down: ; complicted! */
280	uint32_t const offCheckExpandDown = off;
281	uint32_t offFixupLimitDone = 0;
282	if (a_fDataTlb && iSegReg != UINT8_MAX && (pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) != IEMMODE_64BIT)
283	{
284	off = iemNativeEmitBrkEx(pCodeBuf, off, 1); /** @todo this needs testing */
285	/* cmp seglim, regptr */
286	if (pTlbState->idxRegPtr != UINT8_MAX && offDisp == 0)
287	off = iemNativeEmitCmpGpr32WithGprEx(pCodeBuf, off, pTlbState->idxRegSegLimit, pTlbState->idxRegPtr);
288	else if (pTlbState->idxRegPtr == UINT8_MAX)
289	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxRegSegLimit,
290	(uint32_t)(pTlbState->uAbsPtr + offDisp));
291	else if (cbMem == 1)
292	off = iemNativeEmitCmpGpr32WithGprEx(pCodeBuf, off, pTlbState->idxRegSegLimit, pTlbState->idxReg2);
293	else
294	{ /* use idxRegMemResult to calc the displaced address. */
295	off = iemNativeEmitGpr32EqGprPlusImmEx(pCodeBuf, off, idxRegMemResult, pTlbState->idxRegPtr, offDisp);
296	off = iemNativeEmitCmpGpr32WithGprEx(pCodeBuf, off, pTlbState->idxRegSegLimit, idxRegMemResult);
297	}
298	/* ja tlbmiss */
299	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_nbe);
300
301	/* reg1 = segattr & X86DESCATTR_D (0x4000) */
302	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxRegSegAttrib, X86DESCATTR_D);
303	/* xor reg1, X86DESCATTR_D */
304	off = iemNativeEmitXorGpr32ByImmEx(pCodeBuf, off, pTlbState->idxReg1, X86DESCATTR_D);
305	/* shl reg1, 2 (16 - 14) */
306	AssertCompile((X86DESCATTR_D << 2) == UINT32_C(0x10000));
307	off = iemNativeEmitShiftGpr32LeftEx(pCodeBuf, off, pTlbState->idxReg1, 2);
308	/* dec reg1 (=> 0xffff if D=0; 0xffffffff if D=1) */
309	off = iemNativeEmitSubGpr32ImmEx(pCodeBuf, off, pTlbState->idxReg1, 1);
310	/* cmp reg1, reg2 (64-bit) / imm (32-bit) */
311	if (pTlbState->idxRegPtr != UINT8_MAX)
312	off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, pTlbState->idxReg1,
313	cbMem > 1 \|\| offDisp != 0 ? pTlbState->idxReg2 : pTlbState->idxRegPtr);
314	else
315	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxReg1,
316	(uint32_t)(pTlbState->uAbsPtr + offDisp + cbMem - 1)); /* fSkip=true on overflow. */
317	/* jbe tlbmiss */
318	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_be);
319	/* jmp limitdone */
320	offFixupLimitDone = off;
321	off = iemNativeEmitJmpToFixedEx(pCodeBuf, off, off /* ASSUME short jump suffices */);
322	}
323
324	/*
325	* tlblookup:
326	*/
327	iemNativeLabelDefine(pReNative, idxLabelTlbLookup, off);
328	# if defined(RT_ARCH_ARM64) && 0
329	off = iemNativeEmitBrkEx(pCodeBuf, off, 0);
330	# endif
331
332	/*
333	* 1. Segmentation.
334	*
335	* 1a. Check segment limit and attributes if non-flat 32-bit code. This is complicated.
336	*
337	* This can be skipped for code TLB lookups because limit is checked by jmp, call,
338	* ret, and iret prior to making it. It is also checked by the helpers prior to
339	* doing TLB loading.
340	*/
341	if (a_fDataTlb && iSegReg != UINT8_MAX && (pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) != IEMMODE_64BIT)
342	{
343	/* Check that we've got a segment loaded and that it allows the access.
344	For write access this means a writable data segment.
345	For read-only accesses this means a readable code segment or any data segment. */
346	if (fAccess & IEM_ACCESS_TYPE_WRITE)
347	{
348	uint32_t const fMustBe1 = X86DESCATTR_P \| X86DESCATTR_DT \| X86_SEL_TYPE_WRITE;
349	uint32_t const fMustBe0 = X86DESCATTR_UNUSABLE \| X86_SEL_TYPE_CODE;
350	/* reg1 = segattrs & (must1\|must0) */
351	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1,
352	pTlbState->idxRegSegAttrib, fMustBe1 \| fMustBe0);
353	/* cmp reg1, must1 */
354	AssertCompile(fMustBe1 <= UINT16_MAX);
355	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxReg1, fMustBe1);
356	/* jne tlbmiss */
357	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_ne);
358	}
359	else
360	{
361	/* U \| !P \|!DT \|!CD \| RW \|
362	16 \| 8 \| 4 \| 3 \| 1 \|
363	-------------------------------
364	0 \| 0 \| 0 \| 0 \| 0 \| execute-only code segment. - must be excluded
365	0 \| 0 \| 0 \| 0 \| 1 \| execute-read code segment.
366	0 \| 0 \| 0 \| 1 \| 0 \| read-only data segment.
367	0 \| 0 \| 0 \| 1 \| 1 \| read-write data segment. - last valid combination
368	*/
369	/* reg1 = segattrs & (relevant attributes) */
370	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxRegSegAttrib,
371	X86DESCATTR_UNUSABLE \| X86DESCATTR_P \| X86DESCATTR_DT
372	\| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_WRITE);
373	/* xor reg1, X86DESCATTR_P \| X86DESCATTR_DT \| X86_SEL_TYPE_CODE ; place C=1 RW=0 at the bottom & limit the range.
374	; EO-code=0, ER-code=2, RO-data=8, RW-data=10 */
375	#ifdef RT_ARCH_ARM64
376	off = iemNativeEmitXorGpr32ByImmEx(pCodeBuf, off, pTlbState->idxReg1, X86DESCATTR_DT \| X86_SEL_TYPE_CODE);
377	off = iemNativeEmitXorGpr32ByImmEx(pCodeBuf, off, pTlbState->idxReg1, X86DESCATTR_P);
378	#else
379	off = iemNativeEmitXorGpr32ByImmEx(pCodeBuf, off, pTlbState->idxReg1,
380	X86DESCATTR_P \| X86DESCATTR_DT \| X86_SEL_TYPE_CODE);
381	#endif
382	/* sub reg1, X86_SEL_TYPE_WRITE ; EO-code=-2, ER-code=0, RO-data=6, RW-data=8 */
383	off = iemNativeEmitSubGpr32ImmEx(pCodeBuf, off, pTlbState->idxReg1, X86_SEL_TYPE_WRITE /* ER-code */);
384	/* cmp reg1, X86_SEL_TYPE_CODE \| X86_SEL_TYPE_WRITE */
385	AssertCompile(X86_SEL_TYPE_CODE == 8);
386	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxReg1, X86_SEL_TYPE_CODE);
387	/* ja tlbmiss */
388	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_nbe);
389	}
390
391	/* If we're accessing more than one byte or if we're working with a non-zero offDisp,
392	put the last address we'll be accessing in idxReg2 (64-bit). */
393	if ((cbMem > 1 \|\| offDisp != 0) && pTlbState->idxRegPtr != UINT8_MAX)
394	{
395	if (!offDisp)
396	/* reg2 = regptr + cbMem - 1; 64-bit result so we can fend of wraparounds/overflows. */
397	off = iemNativeEmitGprEqGprPlusImmEx(pCodeBuf, off, pTlbState->idxReg2,/=/ pTlbState->idxRegPtr,/+/ cbMem - 1);
398	else
399	{
400	/* reg2 = (uint32_t)(regptr + offDisp) + cbMem - 1;. */
401	off = iemNativeEmitGpr32EqGprPlusImmEx(pCodeBuf, off,
402	pTlbState->idxReg2,/=/ pTlbState->idxRegPtr,/+/ + offDisp);
403	off = iemNativeEmitAddGprImmEx(pCodeBuf, off, pTlbState->idxReg2, cbMem - 1);
404	}
405	}
406
407	/*
408	* Check the limit. If this is a write access, we know that it's a
409	* data segment and includes the expand_down bit. For read-only accesses
410	* we need to check that code/data=0 and expanddown=1 before continuing.
411	*/
412	if (fAccess & IEM_ACCESS_TYPE_WRITE)
413	{
414	/* test segattrs, X86_SEL_TYPE_DOWN */
415	AssertCompile(X86_SEL_TYPE_DOWN < 128);
416	off = iemNativeEmitTestAnyBitsInGpr8Ex(pCodeBuf, off, pTlbState->idxRegSegAttrib, X86_SEL_TYPE_DOWN);
417	/* jnz check_expand_down */
418	off = iemNativeEmitJccToFixedEx(pCodeBuf, off, offCheckExpandDown, kIemNativeInstrCond_ne);
419	}
420	else
421	{
422	/* reg1 = segattr & (code \| down) */
423	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1,
424	pTlbState->idxRegSegAttrib, X86_SEL_TYPE_CODE \| X86_SEL_TYPE_DOWN);
425	/* cmp reg1, down */
426	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxReg1, X86_SEL_TYPE_DOWN);
427	/* je check_expand_down */
428	off = iemNativeEmitJccToFixedEx(pCodeBuf, off, offCheckExpandDown, kIemNativeInstrCond_e);
429	}
430
431	/* expand_up:
432	cmp seglim, regptr/reg2/imm */
433	if (pTlbState->idxRegPtr != UINT8_MAX)
434	off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, pTlbState->idxRegSegLimit,
435	cbMem > 1 \|\| offDisp != 0 ? pTlbState->idxReg2 : pTlbState->idxRegPtr);
436	else
437	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxRegSegLimit,
438	(uint32_t)pTlbState->uAbsPtr + offDisp + cbMem - 1U); /* fSkip=true on overflow. */
439	/* jbe tlbmiss */
440	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_be);
441
442	/* limitdone: */
443	iemNativeFixupFixedJump(pReNative, offFixupLimitDone, off);
444	}
445
446	/* 1b. Add the segment base. We use idxRegMemResult for the ptr register if
447	this step is required or if the address is a constant (simplicity) or
448	if offDisp is non-zero. */
449	uint8_t const idxRegFlatPtr = iSegReg != UINT8_MAX \|\| pTlbState->idxRegPtr == UINT8_MAX \|\| offDisp != 0
450	? idxRegMemResult : pTlbState->idxRegPtr;
451	if (iSegReg != UINT8_MAX)
452	{
453	Assert(idxRegFlatPtr != pTlbState->idxRegPtr);
454	/* regflat = segbase + regptr/imm */
455	if ((pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT)
456	{
457	Assert(iSegReg >= X86_SREG_FS);
458	if (pTlbState->idxRegPtr != UINT8_MAX)
459	{
460	off = iemNativeEmitGprEqGprPlusGprEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->idxRegSegBase, pTlbState->idxRegPtr);
461	if (offDisp != 0)
462	off = iemNativeEmitAddGprImmEx(pCodeBuf, off, idxRegFlatPtr, offDisp);
463	}
464	else
465	off = iemNativeEmitGprEqGprPlusImmEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->idxRegSegBase,
466	pTlbState->uAbsPtr + offDisp);
467	}
468	else if (pTlbState->idxRegPtr != UINT8_MAX)
469	{
470	off = iemNativeEmitGpr32EqGprPlusGprEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->idxRegSegBase, pTlbState->idxRegPtr);
471	if (offDisp != 0)
472	off = iemNativeEmitAddGpr32ImmEx(pCodeBuf, off, idxRegFlatPtr, offDisp);
473	}
474	else
475	off = iemNativeEmitGpr32EqGprPlusImmEx(pCodeBuf, off, idxRegFlatPtr,
476	pTlbState->idxRegSegBase, (uint32_t)pTlbState->uAbsPtr + offDisp);
477	}
478	else if (pTlbState->idxRegPtr == UINT8_MAX)
479	{
480	if ((pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT)
481	off = iemNativeEmitLoadGprImmEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->uAbsPtr + offDisp);
482	else
483	off = iemNativeEmitLoadGpr32ImmEx(pCodeBuf, off, idxRegFlatPtr, (uint32_t)pTlbState->uAbsPtr + offDisp);
484	}
485	else if (offDisp != 0)
486	{
487	Assert(idxRegFlatPtr != pTlbState->idxRegPtr);
488	if ((pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT)
489	off = iemNativeEmitGprEqGprPlusImmEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->idxRegPtr, offDisp);
490	else
491	off = iemNativeEmitGpr32EqGprPlusImmEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->idxRegPtr, offDisp);
492	}
493	else
494	Assert(idxRegFlatPtr == pTlbState->idxRegPtr);
495
496	/*
497	* 2. Check that the address doesn't cross a page boundrary and doesn't have alignment issues.
498	*
499	* 2a. Alignment check using fAlignMask.
500	*/
501	if (fAlignMask)
502	{
503	Assert(RT_IS_POWER_OF_TWO(fAlignMask + 1));
504	Assert(fAlignMask < 128);
505	/* test regflat, fAlignMask */
506	off = iemNativeEmitTestAnyBitsInGpr8Ex(pCodeBuf, off, idxRegFlatPtr, fAlignMask);
507	/* jnz tlbmiss */
508	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_ne);
509	}
510
511	/*
512	* 2b. Check that it's not crossing page a boundrary. This is implicit in
513	* the previous test if the alignment is same or larger than the type.
514	*/
515	if (cbMem > fAlignMask + 1)
516	{
517	/* reg1 = regflat & 0xfff */
518	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1,/=/ idxRegFlatPtr,/&/ GUEST_PAGE_OFFSET_MASK);
519	/* cmp reg1, GUEST_PAGE_SIZE - cbMem */
520	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxReg1, GUEST_PAGE_SIZE);
521	/* ja tlbmiss */
522	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_nbe);
523	}
524
525	/*
526	* 3. TLB lookup.
527	*
528	* 3a. Calculate the TLB tag value (IEMTLB_CALC_TAG).
529	* In 64-bit mode we will also check for non-canonical addresses here.
530	*/
531	if ((pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT)
532	{
533	# if defined(RT_ARCH_AMD64)
534	/* mov reg1, regflat */
535	off = iemNativeEmitLoadGprFromGprEx(pCodeBuf, off, pTlbState->idxReg1, idxRegFlatPtr);
536	/* rol reg1, 16 */
537	off = iemNativeEmitRotateGprLeftEx(pCodeBuf, off, pTlbState->idxReg1, 16);
538	/** @todo Would 'movsx reg2, word reg1' and working on reg2 in dwords be faster? */
539	/* inc word reg1 */
540	pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
541	if (pTlbState->idxReg1 >= 8)
542	pCodeBuf[off++] = X86_OP_REX_B;
543	pCodeBuf[off++] = 0xff;
544	pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, pTlbState->idxReg1 & 7);
545	/* cmp word reg1, 1 */
546	pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
547	if (pTlbState->idxReg1 >= 8)
548	pCodeBuf[off++] = X86_OP_REX_B;
549	pCodeBuf[off++] = 0x83;
550	pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 7, pTlbState->idxReg1 & 7);
551	pCodeBuf[off++] = 1;
552	/* ja tlbmiss */
553	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_nbe);
554	/* shr reg1, 16 + GUEST_PAGE_SHIFT */
555	off = iemNativeEmitShiftGprRightEx(pCodeBuf, off, pTlbState->idxReg1, 16 + GUEST_PAGE_SHIFT);
556
557	# elif defined(RT_ARCH_ARM64)
558	/* lsr reg1, regflat, #48 */
559	pCodeBuf[off++] = Armv8A64MkInstrLslImm(pTlbState->idxReg1, idxRegFlatPtr, 4);
560	/* add reg1, reg1, #1 */
561	pCodeBuf[off++] = Armv8A64MkInstrAddUImm12(pTlbState->idxReg1, pTlbState->idxReg1, 1, false /f64Bit/);
562	/* tst reg1, #0xfffe */
563	Assert(Armv8A64ConvertImmRImmS2Mask32(14, 31) == 0xfffe);
564	pCodeBuf[off++] = Armv8A64MkInstrTstImm(pTlbState->idxReg1, 14, 31, false /f64Bit/);
565	/* b.nq tlbmiss */
566	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_ne);
567
568	/* ubfx reg1, regflat, #12, #36 */
569	pCodeBuf[off++] = Armv8A64MkInstrUbfx(pTlbState->idxReg1, idxRegFlatPtr, GUEST_PAGE_SHIFT, 48 - GUEST_PAGE_SHIFT);
570	# else
571	# error "Port me"
572	# endif
573	}
574	else
575	{
576	/* reg1 = (uint32_t)(regflat >> 12) */
577	off = iemNativeEmitGpr32EqGprShiftRightImmEx(pCodeBuf, off, pTlbState->idxReg1, idxRegFlatPtr, GUEST_PAGE_SHIFT);
578	}
579	/* or reg1, [qword pVCpu->iem.s.DataTlb.uTlbRevision] */
580	# if defined(RT_ARCH_AMD64)
581	pCodeBuf[off++] = pTlbState->idxReg1 < 8 ? X86_OP_REX_W : X86_OP_REX_W \| X86_OP_REX_R;
582	pCodeBuf[off++] = 0x0b; /* OR r64,r/m64 */
583	off = iemNativeEmitGprByVCpuDisp(pCodeBuf, off, pTlbState->idxReg1, offVCpuTlb + RT_UOFFSETOF(IEMTLB, uTlbRevision));
584	# else
585	off = iemNativeEmitLoadGprFromVCpuU64Ex(pCodeBuf, off, pTlbState->idxReg3, offVCpuTlb + RT_UOFFSETOF(IEMTLB, uTlbRevision));
586	off = iemNativeEmitOrGprByGprEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg3);
587	# endif
588
589	/*
590	* 3b. Calc pTlbe.
591	*/
592	uint32_t const offTlbEntries = offVCpuTlb + RT_UOFFSETOF(IEMTLB, aEntries);
593	# if defined(RT_ARCH_AMD64)
594	/* movzx reg2, byte reg1 */
595	off = iemNativeEmitLoadGprFromGpr8Ex(pCodeBuf, off, pTlbState->idxReg2, pTlbState->idxReg1);
596	/* shl reg2, 5 ; reg2 = sizeof(IEMTLBENTRY) /
597	AssertCompileSize(IEMTLBENTRY, 32);
598	off = iemNativeEmitShiftGprLeftEx(pCodeBuf, off, pTlbState->idxReg2, 5);
599	/* lea reg2, [pVCpu->iem.s.DataTlb.aEntries + reg2] */
600	AssertCompile(IEMNATIVE_REG_FIXED_PVMCPU < 8);
601	pCodeBuf[off++] = pTlbState->idxReg2 < 8 ? X86_OP_REX_W : X86_OP_REX_W \| X86_OP_REX_X \| X86_OP_REX_R;
602	pCodeBuf[off++] = 0x8d;
603	pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_MEM4, pTlbState->idxReg2 & 7, 4 /SIB/);
604	pCodeBuf[off++] = X86_SIB_MAKE(IEMNATIVE_REG_FIXED_PVMCPU & 7, pTlbState->idxReg2 & 7, 0);
605	pCodeBuf[off++] = RT_BYTE1(offTlbEntries);
606	pCodeBuf[off++] = RT_BYTE2(offTlbEntries);
607	pCodeBuf[off++] = RT_BYTE3(offTlbEntries);
608	pCodeBuf[off++] = RT_BYTE4(offTlbEntries);
609
610	# elif defined(RT_ARCH_ARM64)
611	/* reg2 = (reg1 & 0xff) << 5 */
612	pCodeBuf[off++] = Armv8A64MkInstrUbfiz(pTlbState->idxReg2, pTlbState->idxReg1, 5, 8);
613	/* reg2 += offsetof(VMCPUCC, iem.s.DataTlb.aEntries) */
614	off = iemNativeEmitAddGprImmEx(pCodeBuf, off, pTlbState->idxReg2, offTlbEntries, pTlbState->idxReg3 /iGprTmp/);
615	/* reg2 += pVCpu */
616	off = iemNativeEmitAddTwoGprsEx(pCodeBuf, off, pTlbState->idxReg2, IEMNATIVE_REG_FIXED_PVMCPU);
617	# else
618	# error "Port me"
619	# endif
620
621	/*
622	* 3c. Compare the TLBE.uTag with the one from 2a (reg1).
623	*/
624	# if defined(RT_ARCH_AMD64)
625	/* cmp reg1, [reg2] */
626	pCodeBuf[off++] = X86_OP_REX_W \| (pTlbState->idxReg1 < 8 ? 0 : X86_OP_REX_R) \| (pTlbState->idxReg2 < 8 ? 0 : X86_OP_REX_B);
627	pCodeBuf[off++] = 0x3b;
628	off = iemNativeEmitGprByGprDisp(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, uTag));
629	# elif defined(RT_ARCH_ARM64)
630	off = iemNativeEmitLoadGprByGprU64Ex(pCodeBuf, off, pTlbState->idxReg3, pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, uTag));
631	off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg3);
632	# else
633	# error "Port me"
634	# endif
635	/* jne tlbmiss */
636	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_ne);
637
638	/*
639	* 4. Check TLB page table level access flags and physical page revision #.
640	*/
641	/* mov reg1, mask */
642	AssertCompile(IEMTLBE_F_PT_NO_USER == 4);
643	uint64_t const fNoUser = (((pReNative->fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK) + 1) & IEMTLBE_F_PT_NO_USER;
644	uint64_t fTlbe = IEMTLBE_F_PHYS_REV \| IEMTLBE_F_NO_MAPPINGR3 \| IEMTLBE_F_PG_UNASSIGNED \| IEMTLBE_F_PT_NO_ACCESSED
645	\| fNoUser;
646	if (fAccess & IEM_ACCESS_TYPE_EXEC)
647	fTlbe \|= IEMTLBE_F_PT_NO_EXEC /\| IEMTLBE_F_PG_NO_READ?/;
648	if (fAccess & IEM_ACCESS_TYPE_READ)
649	fTlbe \|= IEMTLBE_F_PG_NO_READ;
650	if (fAccess & IEM_ACCESS_TYPE_WRITE)
651	fTlbe \|= IEMTLBE_F_PT_NO_WRITE \| IEMTLBE_F_PG_NO_WRITE \| IEMTLBE_F_PT_NO_DIRTY;
652	off = iemNativeEmitLoadGprImmEx(pCodeBuf, off, pTlbState->idxReg1, fTlbe);
653	# if defined(RT_ARCH_AMD64)
654	/* and reg1, [reg2->fFlagsAndPhysRev] */
655	pCodeBuf[off++] = X86_OP_REX_W \| (pTlbState->idxReg1 < 8 ? 0 : X86_OP_REX_R) \| (pTlbState->idxReg2 < 8 ? 0 : X86_OP_REX_B);
656	pCodeBuf[off++] = 0x23;
657	off = iemNativeEmitGprByGprDisp(pCodeBuf, off, pTlbState->idxReg1,
658	pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, fFlagsAndPhysRev));
659
660	/* cmp reg1, [pVCpu->iem.s.DataTlb.uTlbPhysRev] */
661	pCodeBuf[off++] = X86_OP_REX_W \| (pTlbState->idxReg1 < 8 ? 0 : X86_OP_REX_R);
662	pCodeBuf[off++] = 0x3b;
663	off = iemNativeEmitGprByGprDisp(pCodeBuf, off, pTlbState->idxReg1, IEMNATIVE_REG_FIXED_PVMCPU,
664	offVCpuTlb + RT_UOFFSETOF(IEMTLB, uTlbPhysRev));
665	# elif defined(RT_ARCH_ARM64)
666	off = iemNativeEmitLoadGprByGprU64Ex(pCodeBuf, off, pTlbState->idxReg3, pTlbState->idxReg2,
667	RT_UOFFSETOF(IEMTLBENTRY, fFlagsAndPhysRev));
668	pCodeBuf[off++] = Armv8A64MkInstrAnd(pTlbState->idxReg1, pTlbState->idxReg1, pTlbState->idxReg3);
669	off = iemNativeEmitLoadGprFromVCpuU64Ex(pCodeBuf, off, pTlbState->idxReg3, offVCpuTlb + RT_UOFFSETOF(IEMTLB, uTlbPhysRev));
670	off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg3);
671	# else
672	# error "Port me"
673	# endif
674	/* jne tlbmiss */
675	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_ne);
676
677	/*
678	* 5. Check that pbMappingR3 isn't NULL (paranoia) and calculate the
679	* resulting pointer.
680	*
681	* For code TLB lookups we have some more work to do here to set various
682	* IEMCPU members and we return a GCPhys address rather than a host pointer.
683	*/
684	/* mov reg1, [reg2->pbMappingR3] */
685	off = iemNativeEmitLoadGprByGprU64Ex(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg2,
686	RT_UOFFSETOF(IEMTLBENTRY, pbMappingR3));
687	/* if (!reg1) goto tlbmiss; */
688	/** @todo eliminate the need for this test? */
689	off = iemNativeEmitTestIfGprIsZeroAndJmpToLabelEx(pReNative, pCodeBuf, off, pTlbState->idxReg1,
690	true /f64Bit/, idxLabelTlbMiss);
691
692	if (a_fDataTlb)
693	{
694	if (idxRegFlatPtr == idxRegMemResult) /* See step 1b. */
695	{
696	/* and result, 0xfff */
697	off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, idxRegMemResult, GUEST_PAGE_OFFSET_MASK);
698	}
699	else
700	{
701	Assert(idxRegFlatPtr == pTlbState->idxRegPtr);
702	/* result = regflat & 0xfff */
703	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, idxRegMemResult, idxRegFlatPtr, GUEST_PAGE_OFFSET_MASK);
704	}
705
706	/* add result, reg1 */
707	off = iemNativeEmitAddTwoGprsEx(pCodeBuf, off, idxRegMemResult, pTlbState->idxReg1);
708	}
709	else
710	{
711	/*
712	* Code TLB use a la iemOpcodeFetchBytesJmp - keep reg2 pointing to the TLBE.
713	*
714	* Note. We do not need to set offCurInstrStart or offInstrNextByte.
715	*/
716	# ifdef RT_ARCH_AMD64
717	uint8_t const idxReg3 = UINT8_MAX;
718	# else
719	uint8_t const idxReg3 = pTlbState->idxReg3;
720	# endif
721	/* Set pbInstrBuf first since we've got it loaded already. */
722	off = iemNativeEmitStoreGprToVCpuU64Ex(pCodeBuf, off, pTlbState->idxReg1,
723	RT_UOFFSETOF(VMCPUCC, iem.s.pbInstrBuf), idxReg3);
724	/* Set uInstrBufPc to (FlatPC & ~GUEST_PAGE_OFFSET_MASK). */
725	off = iemNativeEmitGprEqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1, idxRegFlatPtr, ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK);
726	off = iemNativeEmitStoreGprToVCpuU64Ex(pCodeBuf, off, pTlbState->idxReg1,
727	RT_UOFFSETOF(VMCPUCC, iem.s.uInstrBufPc), idxReg3);
728	/* Set cbInstrBufTotal to GUEST_PAGE_SIZE. / /* @todo this is a simplifications. Calc right size using CS.LIM and EIP? */
729	off = iemNativeEmitStoreImmToVCpuU16Ex(pCodeBuf, off, GUEST_PAGE_SIZE, RT_UOFFSETOF(VMCPUCC, iem.s.cbInstrBufTotal),
730	pTlbState->idxReg1, idxReg3);
731	/* Now set GCPhysInstrBuf last as we'll be returning it in idxRegMemResult. */
732	off = iemNativeEmitLoadGprByGprU64Ex(pCodeBuf, off, pTlbState->idxReg1,
733	pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, GCPhys));
734	off = iemNativeEmitStoreGprToVCpuU64Ex(pCodeBuf, off, pTlbState->idxReg1,
735	RT_UOFFSETOF(VMCPUCC, iem.s.GCPhysInstrBuf), idxReg3);
736	/* Set idxRegMemResult. */
737	if (idxRegFlatPtr == idxRegMemResult) /* See step 1b. */
738	off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, idxRegMemResult, GUEST_PAGE_OFFSET_MASK);
739	else
740	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, idxRegMemResult, idxRegFlatPtr, GUEST_PAGE_OFFSET_MASK);
741	off = iemNativeEmitAddTwoGprsEx(pCodeBuf, off, idxRegMemResult, pTlbState->idxReg1);
742	}
743
744	# if 0
745	/*
746	* To verify the result we call a helper function.
747	*
748	* It's like the state logging, so parameters are passed on the stack.
749	* iemNativeHlpAsmSafeWrapCheckTlbLookup(pVCpu, result, addr, seg \| (cbMem << 8) \| (fAccess << 16))
750	*/
751	# ifdef RT_ARCH_AMD64
752	if (a_fDataTlb)
753	{
754	/* push seg \| (cbMem << 8) \| (fAccess << 16) */
755	pCodeBuf[off++] = 0x68;
756	pCodeBuf[off++] = iSegReg;
757	pCodeBuf[off++] = cbMem;
758	pCodeBuf[off++] = RT_BYTE1(fAccess);
759	pCodeBuf[off++] = RT_BYTE2(fAccess);
760	/* push pTlbState->idxRegPtr / immediate address. */
761	if (pTlbState->idxRegPtr != UINT8_MAX)
762	{
763	if (pTlbState->idxRegPtr >= 8)
764	pCodeBuf[off++] = X86_OP_REX_B;
765	pCodeBuf[off++] = 0x50 + (pTlbState->idxRegPtr & 7);
766	}
767	else
768	{
769	off = iemNativeEmitLoadGprImmEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->uAbsPtr);
770	if (pTlbState->idxReg1 >= 8)
771	pCodeBuf[off++] = X86_OP_REX_B;
772	pCodeBuf[off++] = 0x50 + (pTlbState->idxReg1 & 7);
773	}
774	/* push idxRegMemResult */
775	if (idxRegMemResult >= 8)
776	pCodeBuf[off++] = X86_OP_REX_B;
777	pCodeBuf[off++] = 0x50 + (idxRegMemResult & 7);
778	/* push pVCpu */
779	pCodeBuf[off++] = 0x50 + IEMNATIVE_REG_FIXED_PVMCPU;
780	/* mov reg1, helper */
781	off = iemNativeEmitLoadGprImmEx(pCodeBuf, off, pTlbState->idxReg1, (uintptr_t)iemNativeHlpAsmSafeWrapCheckTlbLookup);
782	/* call [reg1] */
783	pCodeBuf[off++] = X86_OP_REX_W \| (pTlbState->idxReg1 < 8 ? 0 : X86_OP_REX_B);
784	pCodeBuf[off++] = 0xff;
785	pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 2, pTlbState->idxReg1 & 7);
786	/* The stack is cleaned up by helper function. */
787	}
788
789	# else
790	# error "Port me"
791	# endif
792	# endif
793
794	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
795
796	return off;
797	}
798	#endif /* IEMNATIVE_WITH_TLB_LOOKUP */
799
800
801	/** @} */
802
803	#endif /* !VMM_INCLUDED_SRC_include_IEMN8veRecompilerTlbLookup_h */
804

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source: vbox/trunk/src/VBox/VMM/include/IEMN8veRecompilerTlbLookup.h@ 102850

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