IEMN8veRecompilerTlbLookup.h@ 104984

Last change on this file since 104984 was 104984, checked in by vboxsync, 8 months ago
VMM/IEM: Relax alignment restrictions in native code TLB lookup, avoid the fallback/tlbmiss code path for most accesses as long as they're within the same page. bugref:10687
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File size: 51.7 KB

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1	/* $Id: IEMN8veRecompilerTlbLookup.h 104984 2024-06-20 14:07:04Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager - Native Recompiler TLB Lookup Code Emitter.
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_IEMN8veRecompilerTlbLookup_h
29	#define VMM_INCLUDED_SRC_include_IEMN8veRecompilerTlbLookup_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include "IEMN8veRecompiler.h"
35	#include "IEMN8veRecompilerEmit.h"
36
37
38	/** @defgroup grp_iem_n8ve_re_tlblookup Native Recompiler TLB Lookup Code Emitter
39	* @ingroup grp_iem_n8ve_re
40	* @{
41	*/
42
43	/*
44	* TLB Lookup config.
45	*/
46	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_ARM64)
47	# define IEMNATIVE_WITH_TLB_LOOKUP
48	#endif
49	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
50	# define IEMNATIVE_WITH_TLB_LOOKUP_FETCH
51	#endif
52	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
53	# define IEMNATIVE_WITH_TLB_LOOKUP_STORE
54	#endif
55	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
56	# define IEMNATIVE_WITH_TLB_LOOKUP_MAPPED
57	#endif
58	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
59	# define IEMNATIVE_WITH_TLB_LOOKUP_PUSH
60	#endif
61	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
62	# define IEMNATIVE_WITH_TLB_LOOKUP_POP
63	#endif
64
65
66	/**
67	* This must be instantiate before branching off to the lookup code,
68	* so that register spilling and whatnot happens for everyone.
69	*/
70	typedef struct IEMNATIVEEMITTLBSTATE
71	{
72	bool const fSkip;
73	uint8_t const idxRegPtrHlp; /*< We don't support immediate variables with register assignment, so this a tmp reg alloc. /
74	uint8_t const idxRegPtr;
75	uint8_t const idxRegSegBase;
76	uint8_t const idxRegSegLimit;
77	uint8_t const idxRegSegAttrib;
78	uint8_t const idxReg1;
79	uint8_t const idxReg2;
80	#if defined(RT_ARCH_ARM64)
81	uint8_t const idxReg3;
82	/** @def IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
83	* Use LDP and STDP to reduce number of instructions accessing memory at the
84	* cost of using more registers. This will typically reduce the number of
85	* instructions emitted as well.
86	* @todo Profile this and ensure that it performs the same or better.
87	*/
88	# define IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
89	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
90	uint8_t const idxReg4;
91	uint8_t const idxReg5;
92	# endif
93	#endif
94	uint64_t const uAbsPtr;
95
96	IEMNATIVEEMITTLBSTATE(PIEMRECOMPILERSTATE a_pReNative, uint32_t *a_poff, uint8_t a_idxVarGCPtrMem,
97	uint8_t a_iSegReg, uint8_t a_cbMem, uint8_t a_offDisp = 0)
98	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
99	/* 32-bit and 64-bit wraparound will require special handling, so skip these for absolute addresses. */
100	: fSkip( a_pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVarGCPtrMem)].enmKind
101	== kIemNativeVarKind_Immediate
102	&& ( (a_pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) != IEMMODE_64BIT
103	? (uint64_t)(UINT32_MAX - a_cbMem - a_offDisp)
104	: (uint64_t)(UINT64_MAX - a_cbMem - a_offDisp))
105	< a_pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVarGCPtrMem)].u.uValue)
106	#else
107	: fSkip(true)
108	#endif
109	#if defined(RT_ARCH_AMD64) /* got good immediate encoding, otherwise we just load the address in a reg immediately. */
110	, idxRegPtrHlp(UINT8_MAX)
111	#else
112	, idxRegPtrHlp( a_pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVarGCPtrMem)].enmKind
113	!= kIemNativeVarKind_Immediate
114	\|\| fSkip
115	? UINT8_MAX
116	: iemNativeRegAllocTmpImm(a_pReNative, a_poff,
117	a_pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVarGCPtrMem)].u.uValue))
118	#endif
119	, idxRegPtr( a_pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVarGCPtrMem)].enmKind
120	!= kIemNativeVarKind_Immediate
121	&& !fSkip
122	? iemNativeVarRegisterAcquire(a_pReNative, a_idxVarGCPtrMem, a_poff,
123	true /fInitialized/, IEMNATIVE_CALL_ARG2_GREG)
124	: idxRegPtrHlp)
125	, idxRegSegBase(a_iSegReg == UINT8_MAX \|\| fSkip
126	? UINT8_MAX
127	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_BASE(a_iSegReg)))
128	, idxRegSegLimit((a_iSegReg == UINT8_MAX \|\| (a_pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT) \|\| fSkip
129	? UINT8_MAX
130	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_LIMIT(a_iSegReg)))
131	, idxRegSegAttrib((a_iSegReg == UINT8_MAX \|\| (a_pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT) \|\| fSkip
132	? UINT8_MAX
133	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_ATTRIB(a_iSegReg)))
134	, idxReg1(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
135	, idxReg2(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
136	#if defined(RT_ARCH_ARM64)
137	, idxReg3(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
138	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
139	, idxReg4(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
140	, idxReg5(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
141	# endif
142	#endif
143	, uAbsPtr( a_pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVarGCPtrMem)].enmKind
144	!= kIemNativeVarKind_Immediate
145	\|\| fSkip
146	? UINT64_MAX
147	: a_pReNative->Core.aVars[IEMNATIVE_VAR_IDX_UNPACK(a_idxVarGCPtrMem)].u.uValue)
148
149	{
150	RT_NOREF(a_cbMem, a_offDisp);
151	}
152
153	/* Alternative constructor for PUSH and POP where we don't have a GCPtrMem
154	variable, only a register derived from the guest RSP. */
155	IEMNATIVEEMITTLBSTATE(PIEMRECOMPILERSTATE a_pReNative, uint8_t a_idxRegPtr, uint32_t *a_poff,
156	uint8_t a_iSegReg, uint8_t a_cbMem)
157	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
158	: fSkip(false)
159	#else
160	: fSkip(true)
161	#endif
162	, idxRegPtrHlp(UINT8_MAX)
163	, idxRegPtr(a_idxRegPtr)
164	, idxRegSegBase(a_iSegReg == UINT8_MAX \|\| fSkip
165	? UINT8_MAX
166	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_BASE(a_iSegReg)))
167	, idxRegSegLimit((a_iSegReg == UINT8_MAX \|\| (a_pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT) \|\| fSkip
168	? UINT8_MAX
169	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_LIMIT(a_iSegReg)))
170	, idxRegSegAttrib((a_iSegReg == UINT8_MAX \|\| (a_pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) == IEMMODE_64BIT) \|\| fSkip
171	? UINT8_MAX
172	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_ATTRIB(a_iSegReg)))
173	, idxReg1(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
174	, idxReg2(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
175	#if defined(RT_ARCH_ARM64)
176	, idxReg3(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
177	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
178	, idxReg4(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
179	, idxReg5(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
180	# endif
181	#endif
182	, uAbsPtr(UINT64_MAX)
183
184	{
185	RT_NOREF_PV(a_cbMem);
186	}
187
188	/* Alternative constructor for the code TLB lookups where we implictly use RIP
189	variable, only a register derived from the guest RSP. */
190	IEMNATIVEEMITTLBSTATE(PIEMRECOMPILERSTATE a_pReNative, bool a_fFlat, uint32_t *a_poff)
191	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
192	: fSkip(false)
193	#else
194	: fSkip(true)
195	#endif
196	, idxRegPtrHlp(UINT8_MAX)
197	, idxRegPtr(iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, kIemNativeGstReg_Pc))
198	, idxRegSegBase(a_fFlat \|\| fSkip
199	? UINT8_MAX
200	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_BASE(X86_SREG_CS)))
201	, idxRegSegLimit(/*a_fFlat \|\| fSkip
202	? UINT8_MAX
203	: iemNativeRegAllocTmpForGuestReg(a_pReNative, a_poff, IEMNATIVEGSTREG_SEG_LIMIT(X86_SREG_CS))*/
204	UINT8_MAX)
205	, idxRegSegAttrib(UINT8_MAX)
206	, idxReg1(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
207	, idxReg2(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
208	#if defined(RT_ARCH_ARM64)
209	, idxReg3(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
210	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
211	, idxReg4(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
212	, idxReg5(!fSkip ? iemNativeRegAllocTmp(a_pReNative, a_poff) : UINT8_MAX)
213	# endif
214	#endif
215	, uAbsPtr(UINT64_MAX)
216
217	{
218	}
219
220	void freeRegsAndReleaseVars(PIEMRECOMPILERSTATE a_pReNative, uint8_t idxVarGCPtrMem = UINT8_MAX, bool fIsCode = false) const
221	{
222	if (!fIsCode)
223	{
224	if (idxRegPtr != UINT8_MAX)
225	{
226	if (idxRegPtrHlp == UINT8_MAX)
227	{
228	if (idxVarGCPtrMem != UINT8_MAX)
229	iemNativeVarRegisterRelease(a_pReNative, idxVarGCPtrMem);
230	}
231	else
232	{
233	Assert(idxRegPtrHlp == idxRegPtr);
234	iemNativeRegFreeTmpImm(a_pReNative, idxRegPtrHlp);
235	}
236	}
237	else
238	Assert(idxRegPtrHlp == UINT8_MAX);
239	}
240	else
241	{
242	Assert(idxVarGCPtrMem == UINT8_MAX);
243	Assert(idxRegPtrHlp == UINT8_MAX);
244	iemNativeRegFreeTmp(a_pReNative, idxRegPtr); /* RIP */
245	}
246	if (idxRegSegBase != UINT8_MAX)
247	iemNativeRegFreeTmp(a_pReNative, idxRegSegBase);
248	if (idxRegSegLimit != UINT8_MAX)
249	iemNativeRegFreeTmp(a_pReNative, idxRegSegLimit);
250	if (idxRegSegAttrib != UINT8_MAX)
251	iemNativeRegFreeTmp(a_pReNative, idxRegSegAttrib);
252	#if defined(RT_ARCH_ARM64)
253	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
254	iemNativeRegFreeTmp(a_pReNative, idxReg5);
255	iemNativeRegFreeTmp(a_pReNative, idxReg4);
256	# endif
257	iemNativeRegFreeTmp(a_pReNative, idxReg3);
258	#endif
259	iemNativeRegFreeTmp(a_pReNative, idxReg2);
260	iemNativeRegFreeTmp(a_pReNative, idxReg1);
261
262	}
263
264	uint32_t getRegsNotToSave() const
265	{
266	if (!fSkip)
267	return RT_BIT_32(idxReg1)
268	\| RT_BIT_32(idxReg2)
269	#if defined(RT_ARCH_ARM64)
270	\| RT_BIT_32(idxReg3)
271	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
272	\| RT_BIT_32(idxReg4)
273	\| RT_BIT_32(idxReg5)
274	# endif
275	#endif
276	;
277	return 0;
278	}
279
280	/** This is only for avoid assertions. */
281	uint32_t getActiveRegsWithShadows(bool fCode = false) const
282	{
283	#ifdef VBOX_STRICT
284	if (!fSkip)
285	return (idxRegSegBase != UINT8_MAX ? RT_BIT_32(idxRegSegBase) : 0)
286	\| (idxRegSegLimit != UINT8_MAX ? RT_BIT_32(idxRegSegLimit) : 0)
287	\| (idxRegSegAttrib != UINT8_MAX ? RT_BIT_32(idxRegSegAttrib) : 0)
288	\| (fCode ? RT_BIT_32(idxRegPtr) : 0);
289	#else
290	RT_NOREF_PV(fCode);
291	#endif
292	return 0;
293	}
294	} IEMNATIVEEMITTLBSTATE;
295
296	DECLASM(void) iemNativeHlpAsmSafeWrapCheckTlbLookup(void);
297
298
299	#ifdef IEMNATIVE_WITH_TLB_LOOKUP
300	/**
301	*
302	* @returns New @a off value.
303	* @param pReNative .
304	* @param off .
305	* @param pTlbState .
306	* @param iSegReg .
307	* @param cbMem .
308	* @param fAlignMaskAndCtl The low 8-bit is the alignment mask, ie. a
309	* 128-bit aligned access passes 15. This is only
310	* applied to ring-3 code, when dictated by the
311	* control bits and for atomic accesses.
312	*
313	* The other bits are used for alignment control:
314	* - IEM_MEMMAP_F_ALIGN_GP
315	* - IEM_MEMMAP_F_ALIGN_SSE
316	* - IEM_MEMMAP_F_ALIGN_GP_OR_AC
317	* Any non-zero upper bits means we will go to
318	* tlbmiss on anything out of alignment according
319	* to the mask in the low 8 bits.
320	* @param fAccess .
321	* @param idxLabelTlbLookup .
322	* @param idxLabelTlbMiss .
323	* @param idxRegMemResult .
324	* @param offDisp .
325	* @tparam a_fDataTlb .
326	* @tparam a_fNoReturn .
327	*/
328	template<bool const a_fDataTlb, bool const a_fNoReturn = false>
329	DECL_INLINE_THROW(uint32_t)
330	iemNativeEmitTlbLookup(PIEMRECOMPILERSTATE pReNative, uint32_t off, IEMNATIVEEMITTLBSTATE const * const pTlbState,
331	uint8_t iSegReg, uint8_t cbMem, uint8_t fAlignMaskAndCtl, uint32_t fAccess,
332	uint32_t idxLabelTlbLookup, uint32_t idxLabelTlbMiss, uint8_t idxRegMemResult,
333	uint8_t offDisp = 0)
334	{
335	Assert(!pTlbState->fSkip);
336	uint32_t const offVCpuTlb = a_fDataTlb ? RT_UOFFSETOF(VMCPUCC, iem.s.DataTlb) : RT_UOFFSETOF(VMCPUCC, iem.s.CodeTlb);
337	# if defined(RT_ARCH_AMD64)
338	uint8_t * const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 512);
339	# elif defined(RT_ARCH_ARM64)
340	uint32_t * const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 64);
341	# endif
342
343	/*
344	* The expand down check isn't use all that much, so we emit here to keep
345	* the lookup straighter.
346	*/
347	/* check_expand_down: ; complicted! */
348	uint32_t const offCheckExpandDown = off;
349	uint32_t offFixupLimitDone = 0;
350	if (a_fDataTlb && iSegReg != UINT8_MAX && (pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) != IEMMODE_64BIT)
351	{
352	off = iemNativeEmitBrkEx(pCodeBuf, off, 1); /** @todo this needs testing */
353	/* cmp seglim, regptr */
354	if (pTlbState->idxRegPtr != UINT8_MAX && offDisp == 0)
355	off = iemNativeEmitCmpGpr32WithGprEx(pCodeBuf, off, pTlbState->idxRegSegLimit, pTlbState->idxRegPtr);
356	else if (pTlbState->idxRegPtr == UINT8_MAX)
357	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxRegSegLimit,
358	(uint32_t)(pTlbState->uAbsPtr + offDisp));
359	else if (cbMem == 1)
360	off = iemNativeEmitCmpGpr32WithGprEx(pCodeBuf, off, pTlbState->idxRegSegLimit, pTlbState->idxReg2);
361	else
362	{ /* use idxRegMemResult to calc the displaced address. */
363	off = iemNativeEmitGpr32EqGprPlusImmEx(pCodeBuf, off, idxRegMemResult, pTlbState->idxRegPtr, offDisp);
364	off = iemNativeEmitCmpGpr32WithGprEx(pCodeBuf, off, pTlbState->idxRegSegLimit, idxRegMemResult);
365	}
366	/* ja tlbmiss */
367	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_nbe);
368
369	/* reg1 = segattr & X86DESCATTR_D (0x4000) */
370	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxRegSegAttrib, X86DESCATTR_D);
371	/* xor reg1, X86DESCATTR_D */
372	off = iemNativeEmitXorGpr32ByImmEx(pCodeBuf, off, pTlbState->idxReg1, X86DESCATTR_D);
373	/* shl reg1, 2 (16 - 14) */
374	AssertCompile((X86DESCATTR_D << 2) == UINT32_C(0x10000));
375	off = iemNativeEmitShiftGpr32LeftEx(pCodeBuf, off, pTlbState->idxReg1, 2);
376	/* dec reg1 (=> 0xffff if D=0; 0xffffffff if D=1) */
377	off = iemNativeEmitSubGpr32ImmEx(pCodeBuf, off, pTlbState->idxReg1, 1);
378	/* cmp reg1, reg2 (64-bit) / imm (32-bit) */
379	if (pTlbState->idxRegPtr != UINT8_MAX)
380	off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, pTlbState->idxReg1,
381	cbMem > 1 \|\| offDisp != 0 ? pTlbState->idxReg2 : pTlbState->idxRegPtr);
382	else
383	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxReg1,
384	(uint32_t)(pTlbState->uAbsPtr + offDisp + cbMem - 1)); /* fSkip=true on overflow. */
385	/* jbe tlbmiss */
386	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_be);
387	/* jmp limitdone */
388	offFixupLimitDone = off;
389	off = iemNativeEmitJmpToFixedEx(pCodeBuf, off, off /* ASSUME short jump suffices */);
390	}
391
392	/*
393	* tlblookup:
394	*/
395	iemNativeLabelDefine(pReNative, idxLabelTlbLookup, off);
396	# if defined(RT_ARCH_ARM64) && 0
397	off = iemNativeEmitBrkEx(pCodeBuf, off, 0);
398	# endif
399
400	/*
401	* 1. Segmentation.
402	*
403	* 1a. Check segment limit and attributes if non-flat 32-bit code. This is complicated.
404	*
405	* This can be skipped for code TLB lookups because limit is checked by jmp, call,
406	* ret, and iret prior to making it. It is also checked by the helpers prior to
407	* doing TLB loading.
408	*/
409	if (a_fDataTlb && iSegReg != UINT8_MAX && (pReNative->fExec & IEM_F_MODE_CPUMODE_MASK) != IEMMODE_64BIT)
410	{
411	/* Check that we've got a segment loaded and that it allows the access.
412	For write access this means a writable data segment.
413	For read-only accesses this means a readable code segment or any data segment. */
414	if (fAccess & IEM_ACCESS_TYPE_WRITE)
415	{
416	uint32_t const fMustBe1 = X86DESCATTR_P \| X86DESCATTR_DT \| X86_SEL_TYPE_WRITE;
417	uint32_t const fMustBe0 = X86DESCATTR_UNUSABLE \| X86_SEL_TYPE_CODE;
418	/* reg1 = segattrs & (must1\|must0) */
419	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1,
420	pTlbState->idxRegSegAttrib, fMustBe1 \| fMustBe0);
421	/* cmp reg1, must1 */
422	AssertCompile(fMustBe1 <= UINT16_MAX);
423	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxReg1, fMustBe1);
424	/* jne tlbmiss */
425	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_ne);
426	}
427	else
428	{
429	/* U \| !P \|!DT \|!CD \| RW \|
430	16 \| 8 \| 4 \| 3 \| 1 \|
431	-------------------------------
432	0 \| 0 \| 0 \| 0 \| 0 \| execute-only code segment. - must be excluded
433	0 \| 0 \| 0 \| 0 \| 1 \| execute-read code segment.
434	0 \| 0 \| 0 \| 1 \| 0 \| read-only data segment.
435	0 \| 0 \| 0 \| 1 \| 1 \| read-write data segment. - last valid combination
436	*/
437	/* reg1 = segattrs & (relevant attributes) */
438	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxRegSegAttrib,
439	X86DESCATTR_UNUSABLE \| X86DESCATTR_P \| X86DESCATTR_DT
440	\| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_WRITE);
441	/* xor reg1, X86DESCATTR_P \| X86DESCATTR_DT \| X86_SEL_TYPE_CODE ; place C=1 RW=0 at the bottom & limit the range.
442	; EO-code=0, ER-code=2, RO-data=8, RW-data=10 */
443	#ifdef RT_ARCH_ARM64
444	off = iemNativeEmitXorGpr32ByImmEx(pCodeBuf, off, pTlbState->idxReg1, X86DESCATTR_DT \| X86_SEL_TYPE_CODE);
445	off = iemNativeEmitXorGpr32ByImmEx(pCodeBuf, off, pTlbState->idxReg1, X86DESCATTR_P);
446	#else
447	off = iemNativeEmitXorGpr32ByImmEx(pCodeBuf, off, pTlbState->idxReg1,
448	X86DESCATTR_P \| X86DESCATTR_DT \| X86_SEL_TYPE_CODE);
449	#endif
450	/* sub reg1, X86_SEL_TYPE_WRITE ; EO-code=-2, ER-code=0, RO-data=6, RW-data=8 */
451	off = iemNativeEmitSubGpr32ImmEx(pCodeBuf, off, pTlbState->idxReg1, X86_SEL_TYPE_WRITE /* ER-code */);
452	/* cmp reg1, X86_SEL_TYPE_CODE \| X86_SEL_TYPE_WRITE */
453	AssertCompile(X86_SEL_TYPE_CODE == 8);
454	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxReg1, X86_SEL_TYPE_CODE);
455	/* ja tlbmiss */
456	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_nbe);
457	}
458
459	/* If we're accessing more than one byte or if we're working with a non-zero offDisp,
460	put the last address we'll be accessing in idxReg2 (64-bit). */
461	if ((cbMem > 1 \|\| offDisp != 0) && pTlbState->idxRegPtr != UINT8_MAX)
462	{
463	if (!offDisp)
464	/* reg2 = regptr + cbMem - 1; 64-bit result so we can fend of wraparounds/overflows. */
465	off = iemNativeEmitGprEqGprPlusImmEx(pCodeBuf, off, pTlbState->idxReg2,/=/ pTlbState->idxRegPtr,/+/ cbMem - 1);
466	else
467	{
468	/* reg2 = (uint32_t)(regptr + offDisp) + cbMem - 1;. */
469	off = iemNativeEmitGpr32EqGprPlusImmEx(pCodeBuf, off,
470	pTlbState->idxReg2,/=/ pTlbState->idxRegPtr,/+/ + offDisp);
471	off = iemNativeEmitAddGprImmEx(pCodeBuf, off, pTlbState->idxReg2, cbMem - 1);
472	}
473	}
474
475	/*
476	* Check the limit. If this is a write access, we know that it's a
477	* data segment and includes the expand_down bit. For read-only accesses
478	* we need to check that code/data=0 and expanddown=1 before continuing.
479	*/
480	if (fAccess & IEM_ACCESS_TYPE_WRITE)
481	{
482	/* test segattrs, X86_SEL_TYPE_DOWN */
483	AssertCompile(X86_SEL_TYPE_DOWN < 128);
484	off = iemNativeEmitTestAnyBitsInGpr8Ex(pCodeBuf, off, pTlbState->idxRegSegAttrib, X86_SEL_TYPE_DOWN);
485	/* jnz check_expand_down */
486	off = iemNativeEmitJccToFixedEx(pCodeBuf, off, offCheckExpandDown, kIemNativeInstrCond_ne);
487	}
488	else
489	{
490	/* reg1 = segattr & (code \| down) */
491	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1,
492	pTlbState->idxRegSegAttrib, X86_SEL_TYPE_CODE \| X86_SEL_TYPE_DOWN);
493	/* cmp reg1, down */
494	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxReg1, X86_SEL_TYPE_DOWN);
495	/* je check_expand_down */
496	off = iemNativeEmitJccToFixedEx(pCodeBuf, off, offCheckExpandDown, kIemNativeInstrCond_e);
497	}
498
499	/* expand_up:
500	cmp seglim, regptr/reg2/imm */
501	if (pTlbState->idxRegPtr != UINT8_MAX)
502	off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, pTlbState->idxRegSegLimit,
503	cbMem > 1 \|\| offDisp != 0 ? pTlbState->idxReg2 : pTlbState->idxRegPtr);
504	else
505	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxRegSegLimit,
506	(uint32_t)pTlbState->uAbsPtr + offDisp + cbMem - 1U); /* fSkip=true on overflow. */
507	/* jbe tlbmiss */
508	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_be);
509
510	/* limitdone: */
511	iemNativeFixupFixedJump(pReNative, offFixupLimitDone, off);
512	}
513
514	/* 1b. Add the segment base. We use idxRegMemResult for the ptr register if
515	this step is required or if the address is a constant (simplicity) or
516	if offDisp is non-zero. */
517	uint8_t const idxRegFlatPtr = iSegReg != UINT8_MAX \|\| pTlbState->idxRegPtr == UINT8_MAX \|\| offDisp != 0
518	? idxRegMemResult : pTlbState->idxRegPtr;
519	if (iSegReg != UINT8_MAX)
520	{
521	Assert(idxRegFlatPtr != pTlbState->idxRegPtr);
522	/* regflat = segbase + regptr/imm */
523	if ((pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT)
524	{
525	Assert(iSegReg >= X86_SREG_FS);
526	if (pTlbState->idxRegPtr != UINT8_MAX)
527	{
528	off = iemNativeEmitGprEqGprPlusGprEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->idxRegSegBase, pTlbState->idxRegPtr);
529	if (offDisp != 0)
530	off = iemNativeEmitAddGprImmEx(pCodeBuf, off, idxRegFlatPtr, offDisp);
531	}
532	else
533	off = iemNativeEmitGprEqGprPlusImmEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->idxRegSegBase,
534	pTlbState->uAbsPtr + offDisp);
535	}
536	else if (pTlbState->idxRegPtr != UINT8_MAX)
537	{
538	off = iemNativeEmitGpr32EqGprPlusGprEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->idxRegSegBase, pTlbState->idxRegPtr);
539	if (offDisp != 0)
540	off = iemNativeEmitAddGpr32ImmEx(pCodeBuf, off, idxRegFlatPtr, offDisp);
541	}
542	else
543	off = iemNativeEmitGpr32EqGprPlusImmEx(pCodeBuf, off, idxRegFlatPtr,
544	pTlbState->idxRegSegBase, (uint32_t)pTlbState->uAbsPtr + offDisp);
545	}
546	else if (pTlbState->idxRegPtr == UINT8_MAX)
547	{
548	if ((pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT)
549	off = iemNativeEmitLoadGprImmEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->uAbsPtr + offDisp);
550	else
551	off = iemNativeEmitLoadGpr32ImmEx(pCodeBuf, off, idxRegFlatPtr, (uint32_t)pTlbState->uAbsPtr + offDisp);
552	}
553	else if (offDisp != 0)
554	{
555	Assert(idxRegFlatPtr != pTlbState->idxRegPtr);
556	if ((pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT)
557	off = iemNativeEmitGprEqGprPlusImmEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->idxRegPtr, offDisp);
558	else
559	off = iemNativeEmitGpr32EqGprPlusImmEx(pCodeBuf, off, idxRegFlatPtr, pTlbState->idxRegPtr, offDisp);
560	}
561	else
562	Assert(idxRegFlatPtr == pTlbState->idxRegPtr);
563
564	/*
565	* 2. Check that the address doesn't cross a page boundrary and doesn't
566	* have alignment issues (not applicable to code).
567	*
568	* For regular accesses (non-SSE/AVX & atomic stuff) we only need to
569	* check for #AC in ring-3 code. To simplify this, the need for AC
570	* checking is indicated by IEM_F_X86_AC in IEMCPU::fExec.
571	*
572	* The caller informs us about about SSE/AVX aligned accesses via the
573	* upper bits of fAlignMaskAndCtl and atomic accesses via fAccess.
574	*/
575	if (a_fDataTlb)
576	{
577	uint8_t const fAlignMask = (uint8_t)fAlignMaskAndCtl;
578	Assert(!(fAlignMaskAndCtl & ~(UINT32_C(0xff) \| IEM_MEMMAP_F_ALIGN_SSE \| IEM_MEMMAP_F_ALIGN_GP \| IEM_MEMMAP_F_ALIGN_GP_OR_AC)));
579	Assert(RT_IS_POWER_OF_TWO(fAlignMask + 1U));
580	Assert(cbMem == fAlignMask + 1U \|\| !(fAccess & IEM_ACCESS_ATOMIC));
581	Assert(cbMem < 128); /* alignment test assumptions */
582
583	/*
584	* 2a. Strict alignment check using fAlignMask for atomic, strictly
585	* aligned stuff (SSE & AVX) and AC=1 (ring-3).
586	*/
587	bool const fStrictAlignmentCheck = fAlignMask
588	&& ( (fAlignMaskAndCtl & ~UINT32_C(0xff))
589	\|\| (fAccess & IEM_ACCESS_ATOMIC)
590	\|\| (pReNative->fExec & IEM_F_X86_AC) );
591	if (fStrictAlignmentCheck)
592	{
593	/* test regflat, fAlignMask */
594	off = iemNativeEmitTestAnyBitsInGpr8Ex(pCodeBuf, off, idxRegFlatPtr, fAlignMask);
595
596	#ifndef IEM_WITH_TLB_STATISTICS
597	/* jnz tlbmiss */
598	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_ne);
599	#else
600	/* jz 1F; inc stat; jmp tlbmiss */
601	uint32_t const offFixup1 = off;
602	off = iemNativeEmitJccToFixedEx(pCodeBuf, off, off + 16, kIemNativeInstrCond_e);
603	off = iemNativeEmitIncStamCounterInVCpuEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg2,
604	offVCpuTlb + RT_UOFFSETOF(IEMTLB, cTlbNativeMissAlignment));
605	off = iemNativeEmitJmpToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss);
606	iemNativeFixupFixedJump(pReNative, offFixup1, off);
607	#endif
608	}
609
610	/*
611	* 2b. Check that it's not crossing page a boundrary if the access is
612	* larger than the aligment mask or if we didn't do the strict
613	* alignment check above.
614	*/
615	if ( cbMem > 1
616	&& ( !fStrictAlignmentCheck
617	\|\| cbMem > fAlignMask + 1U))
618	{
619	/* reg1 = regflat & 0xfff */
620	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1,/=/ idxRegFlatPtr,/&/ GUEST_PAGE_OFFSET_MASK);
621	/* cmp reg1, GUEST_PAGE_SIZE - cbMem */
622	off = iemNativeEmitCmpGpr32WithImmEx(pCodeBuf, off, pTlbState->idxReg1, GUEST_PAGE_SIZE - cbMem);
623	#ifndef IEM_WITH_TLB_STATISTICS
624	/* ja tlbmiss */
625	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_nbe);
626	#else
627	/* jbe 1F; inc stat; jmp tlbmiss */
628	uint32_t const offFixup1 = off;
629	off = iemNativeEmitJccToFixedEx(pCodeBuf, off, off + 16, kIemNativeInstrCond_be);
630	off = iemNativeEmitIncU32CounterInVCpuEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg2,
631	offVCpuTlb + RT_UOFFSETOF(IEMTLB, cTlbNativeMissCrossPage));
632	off = iemNativeEmitJmpToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss);
633	iemNativeFixupFixedJump(pReNative, offFixup1, off);
634	#endif
635	}
636	}
637	else
638	Assert(fAlignMaskAndCtl == 0);
639
640	/*
641	* 3. TLB lookup.
642	*
643	* 3a. Calculate the TLB tag value (IEMTLB_CALC_TAG).
644	* In 64-bit mode we will also check for non-canonical addresses here.
645	*/
646	if ((pReNative->fExec & IEM_F_MODE_MASK) == IEM_F_MODE_X86_64BIT)
647	{
648	# if defined(RT_ARCH_AMD64)
649	/* mov reg1, regflat */
650	off = iemNativeEmitLoadGprFromGprEx(pCodeBuf, off, pTlbState->idxReg1, idxRegFlatPtr);
651	/* rol reg1, 16 */
652	off = iemNativeEmitRotateGprLeftEx(pCodeBuf, off, pTlbState->idxReg1, 16);
653	/** @todo Would 'movsx reg2, word reg1' and working on reg2 in dwords be faster? */
654	/* inc word reg1 */
655	pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
656	if (pTlbState->idxReg1 >= 8)
657	pCodeBuf[off++] = X86_OP_REX_B;
658	pCodeBuf[off++] = 0xff;
659	pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 0, pTlbState->idxReg1 & 7);
660	/* cmp word reg1, 1 */
661	pCodeBuf[off++] = X86_OP_PRF_SIZE_OP;
662	if (pTlbState->idxReg1 >= 8)
663	pCodeBuf[off++] = X86_OP_REX_B;
664	pCodeBuf[off++] = 0x83;
665	pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 7, pTlbState->idxReg1 & 7);
666	pCodeBuf[off++] = 1;
667	# ifndef IEM_WITH_TLB_STATISTICS
668	/* ja tlbmiss */
669	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_nbe);
670	# else
671	/* jbe 1F; inc stat; jmp tlbmiss */
672	uint32_t const offFixup1 = off;
673	off = iemNativeEmitJccToFixedEx(pCodeBuf, off, off + 16, kIemNativeInstrCond_be);
674	off = iemNativeEmitIncU32CounterInVCpuEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg2,
675	offVCpuTlb + RT_UOFFSETOF(IEMTLB, cTlbNativeMissNonCanonical));
676	off = iemNativeEmitJmpToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss);
677	iemNativeFixupFixedJump(pReNative, offFixup1, off);
678	# endif
679	/* shr reg1, 16 + GUEST_PAGE_SHIFT */
680	off = iemNativeEmitShiftGprRightEx(pCodeBuf, off, pTlbState->idxReg1, 16 + GUEST_PAGE_SHIFT);
681
682	# elif defined(RT_ARCH_ARM64)
683	/* lsr reg1, regflat, #48 */
684	pCodeBuf[off++] = Armv8A64MkInstrLsrImm(pTlbState->idxReg1, idxRegFlatPtr, 48);
685	/* add reg1, reg1, #1 */
686	pCodeBuf[off++] = Armv8A64MkInstrAddUImm12(pTlbState->idxReg1, pTlbState->idxReg1, 1, false /f64Bit/);
687	/* tst reg1, #0xfffe */
688	Assert(Armv8A64ConvertImmRImmS2Mask32(14, 31) == 0xfffe);
689	pCodeBuf[off++] = Armv8A64MkInstrTstImm(pTlbState->idxReg1, 14, 31, false /f64Bit/);
690	# ifndef IEM_WITH_TLB_STATISTICS
691	/* b.ne tlbmiss */
692	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_ne);
693	# else
694	/* b.eq 1F; inc stat; jmp tlbmiss */
695	uint32_t const offFixup1 = off;
696	off = iemNativeEmitJccToFixedEx(pCodeBuf, off, off + 16, kIemNativeInstrCond_e);
697	off = iemNativeEmitIncU32CounterInVCpuEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg2,
698	offVCpuTlb + RT_UOFFSETOF(IEMTLB, cTlbNativeMissNonCanonical));
699	off = iemNativeEmitJmpToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss);
700	iemNativeFixupFixedJump(pReNative, offFixup1, off);
701	# endif
702
703	/* ubfx reg1, regflat, #12, #36 */
704	pCodeBuf[off++] = Armv8A64MkInstrUbfx(pTlbState->idxReg1, idxRegFlatPtr, GUEST_PAGE_SHIFT, 48 - GUEST_PAGE_SHIFT);
705	# else
706	# error "Port me"
707	# endif
708	}
709	else
710	{
711	/* reg1 = (uint32_t)(regflat >> 12) */
712	off = iemNativeEmitGpr32EqGprShiftRightImmEx(pCodeBuf, off, pTlbState->idxReg1, idxRegFlatPtr, GUEST_PAGE_SHIFT);
713	}
714	/* or reg1, [qword pVCpu->iem.s.DataTlb.uTlbRevision] */
715	# if defined(RT_ARCH_AMD64)
716	pCodeBuf[off++] = pTlbState->idxReg1 < 8 ? X86_OP_REX_W : X86_OP_REX_W \| X86_OP_REX_R;
717	pCodeBuf[off++] = 0x0b; /* OR r64,r/m64 */
718	off = iemNativeEmitGprByVCpuDisp(pCodeBuf, off, pTlbState->idxReg1, offVCpuTlb + RT_UOFFSETOF(IEMTLB, uTlbRevision));
719	# else
720	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
721	/* Load uTlbRevision into reg3 and uTlbPhysRev into reg5.
722	We load the offVCpuTlb + aEntries into reg4 and use it for addressing here
723	and later when calculating pTble (save an instruction). */
724	AssertCompileMemberAlignment(IEMTLB, uTlbRevision, 16); /* It is said that misaligned pair loads doesn't perform well. */
725	AssertCompileAdjacentMembers(IEMTLB, uTlbRevision, uTlbPhysRev);
726	AssertCompile(RTASSERT_OFFSET_OF(IEMTLB, uTlbPhysRev) < RTASSERT_OFFSET_OF(IEMTLB, aEntries));
727	AssertCompile(RTASSERT_OFFSET_OF(VMCPUCC, iem.s.DataTlb.aEntries) < _64K);
728	if (offVCpuTlb + RT_UOFFSETOF(IEMTLB, aEntries) < _64K)
729	{
730	pCodeBuf[off++] = Armv8A64MkInstrMovZ(pTlbState->idxReg4, offVCpuTlb + RT_UOFFSETOF(IEMTLB, aEntries));
731	pCodeBuf[off++] = Armv8A64MkInstrAddReg(pTlbState->idxReg4, IEMNATIVE_REG_FIXED_PVMCPU, pTlbState->idxReg4);
732	}
733	else
734	{
735	AssertCompileMemberAlignment(VMCPUCC, iem.s.CodeTlb.aEntries, 64);
736	AssertCompileMemberAlignment(IEMTLB, aEntries, 64);
737	AssertCompile(RTASSERT_OFFSET_OF(VMCPUCC, iem.s.CodeTlb.aEntries) < _64K*64U);
738	pCodeBuf[off++] = Armv8A64MkInstrMovZ(pTlbState->idxReg4, (offVCpuTlb + RT_UOFFSETOF(IEMTLB, aEntries)) >> 6);
739	pCodeBuf[off++] = Armv8A64MkInstrAddReg(pTlbState->idxReg4, IEMNATIVE_REG_FIXED_PVMCPU, pTlbState->idxReg4,
740	true /64Bit/, false /fSetFlags/, 6 /cShift/, kArmv8A64InstrShift_Lsl);
741	}
742	pCodeBuf[off++] = Armv8A64MkInstrLdPairGpr(pTlbState->idxReg3, pTlbState->idxReg5, pTlbState->idxReg4,
743	(RT_OFFSETOF(IEMTLB, uTlbRevision) - RT_OFFSETOF(IEMTLB, aEntries)) / 8);
744	# else
745	off = iemNativeEmitLoadGprFromVCpuU64Ex(pCodeBuf, off, pTlbState->idxReg3, offVCpuTlb + RT_UOFFSETOF(IEMTLB, uTlbRevision));
746	# endif
747	off = iemNativeEmitOrGprByGprEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg3);
748	# endif
749
750	/*
751	* 3b. Calc pTlbe.
752	*/
753	# if !defined(RT_ARCH_ARM64) \|\| !defined(IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR)
754	uint32_t const offTlbEntries = offVCpuTlb + RT_UOFFSETOF(IEMTLB, aEntries);
755	# endif
756	# if defined(RT_ARCH_AMD64)
757	# if IEMTLB_ENTRY_COUNT == 256
758	/* movzx reg2, byte reg1 */
759	off = iemNativeEmitLoadGprFromGpr8Ex(pCodeBuf, off, pTlbState->idxReg2, pTlbState->idxReg1);
760	# else
761	/* mov reg2, reg1 */
762	off = iemNativeEmitLoadGprFromGpr32Ex(pCodeBuf, off, pTlbState->idxReg2, pTlbState->idxReg1);
763	/* and reg2, IEMTLB_ENTRY_COUNT - 1U */
764	off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, pTlbState->idxReg2, IEMTLB_ENTRY_COUNT - 1U);
765	# endif
766	/* shl reg2, 5 ; reg2 = sizeof(IEMTLBENTRY) /
767	AssertCompileSize(IEMTLBENTRY, 32);
768	off = iemNativeEmitShiftGprLeftEx(pCodeBuf, off, pTlbState->idxReg2, 5);
769	/* lea reg2, [pVCpu->iem.s.DataTlb.aEntries + reg2] */
770	AssertCompile(IEMNATIVE_REG_FIXED_PVMCPU < 8);
771	pCodeBuf[off++] = pTlbState->idxReg2 < 8 ? X86_OP_REX_W : X86_OP_REX_W \| X86_OP_REX_X \| X86_OP_REX_R;
772	pCodeBuf[off++] = 0x8d;
773	pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_MEM4, pTlbState->idxReg2 & 7, 4 /SIB/);
774	pCodeBuf[off++] = X86_SIB_MAKE(IEMNATIVE_REG_FIXED_PVMCPU & 7, pTlbState->idxReg2 & 7, 0);
775	pCodeBuf[off++] = RT_BYTE1(offTlbEntries);
776	pCodeBuf[off++] = RT_BYTE2(offTlbEntries);
777	pCodeBuf[off++] = RT_BYTE3(offTlbEntries);
778	pCodeBuf[off++] = RT_BYTE4(offTlbEntries);
779
780	# elif defined(RT_ARCH_ARM64)
781	/* reg2 = (reg1 & tlbmask) << 5 */
782	pCodeBuf[off++] = Armv8A64MkInstrUbfiz(pTlbState->idxReg2, pTlbState->idxReg1, 5, IEMTLB_ENTRY_COUNT_AS_POWER_OF_TWO);
783	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
784	/* reg2 += &pVCpu->iem.s.DataTlb.aEntries / CodeTlb.aEntries */
785	pCodeBuf[off++] = Armv8A64MkInstrAddReg(pTlbState->idxReg2, pTlbState->idxReg2, pTlbState->idxReg4);
786	# else
787	/* reg2 += offsetof(VMCPUCC, iem.s.DataTlb.aEntries) */
788	off = iemNativeEmitAddGprImmEx(pCodeBuf, off, pTlbState->idxReg2, offTlbEntries, pTlbState->idxReg3 /iGprTmp/);
789	/* reg2 += pVCpu */
790	off = iemNativeEmitAddTwoGprsEx(pCodeBuf, off, pTlbState->idxReg2, IEMNATIVE_REG_FIXED_PVMCPU);
791	# endif
792	# else
793	# error "Port me"
794	# endif
795
796	/*
797	* 3c. Compare the TLBE.uTag with the one from 2a (reg1).
798	*/
799	# if defined(RT_ARCH_AMD64)
800	/* cmp reg1, [reg2] */
801	pCodeBuf[off++] = X86_OP_REX_W \| (pTlbState->idxReg1 < 8 ? 0 : X86_OP_REX_R) \| (pTlbState->idxReg2 < 8 ? 0 : X86_OP_REX_B);
802	pCodeBuf[off++] = 0x3b;
803	off = iemNativeEmitGprByGprDisp(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, uTag));
804	# elif defined(RT_ARCH_ARM64)
805	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
806	AssertCompileMemberAlignment(IEMTLBENTRY, uTag, 16); /* It is said that misaligned pair loads doesn't perform well. */
807	AssertCompile(RT_UOFFSETOF(IEMTLBENTRY, uTag) + sizeof(uint64_t) == RT_UOFFSETOF(IEMTLBENTRY, fFlagsAndPhysRev));
808	pCodeBuf[off++] = Armv8A64MkInstrLdPairGpr(pTlbState->idxReg3, pTlbState->idxReg4,
809	pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, uTag) / 8);
810	# else
811	off = iemNativeEmitLoadGprByGprU64Ex(pCodeBuf, off, pTlbState->idxReg3, pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, uTag));
812	# endif
813	off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg3);
814	# else
815	# error "Port me"
816	# endif
817	# ifndef IEM_WITH_TLB_STATISTICS
818	/* jne tlbmiss */
819	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_ne);
820	# else
821	/* je 1F; inc stat; jmp tlbmiss */
822	uint32_t const offFixup1 = off;
823	off = iemNativeEmitJccToFixedEx(pCodeBuf, off, off + 16, kIemNativeInstrCond_e);
824	off = iemNativeEmitIncStamCounterInVCpuEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg2,
825	offVCpuTlb + RT_UOFFSETOF(IEMTLB, cTlbNativeMissTag));
826	off = iemNativeEmitJmpToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss);
827	iemNativeFixupFixedJump(pReNative, offFixup1, off);
828	# endif
829
830	/*
831	* 4. Check TLB page table level access flags and physical page revision #.
832	*/
833	/* mov reg1, mask */
834	AssertCompile(IEMTLBE_F_PT_NO_USER == 4);
835	uint64_t const fNoUser = (((pReNative->fExec >> IEM_F_X86_CPL_SHIFT) & IEM_F_X86_CPL_SMASK) + 1) & IEMTLBE_F_PT_NO_USER;
836	uint64_t fTlbe = IEMTLBE_F_PHYS_REV \| IEMTLBE_F_NO_MAPPINGR3 \| IEMTLBE_F_PG_UNASSIGNED \| IEMTLBE_F_PT_NO_ACCESSED
837	\| fNoUser;
838	if (fAccess & IEM_ACCESS_TYPE_EXEC)
839	fTlbe \|= IEMTLBE_F_PT_NO_EXEC /\| IEMTLBE_F_PG_NO_READ?/;
840	if (fAccess & IEM_ACCESS_TYPE_READ)
841	fTlbe \|= IEMTLBE_F_PG_NO_READ;
842	if (fAccess & IEM_ACCESS_TYPE_WRITE)
843	fTlbe \|= IEMTLBE_F_PT_NO_WRITE \| IEMTLBE_F_PG_NO_WRITE \| IEMTLBE_F_PT_NO_DIRTY;
844	off = iemNativeEmitLoadGprImmEx(pCodeBuf, off, pTlbState->idxReg1, fTlbe);
845	# if defined(RT_ARCH_AMD64)
846	/* and reg1, [reg2->fFlagsAndPhysRev] */
847	pCodeBuf[off++] = X86_OP_REX_W \| (pTlbState->idxReg1 < 8 ? 0 : X86_OP_REX_R) \| (pTlbState->idxReg2 < 8 ? 0 : X86_OP_REX_B);
848	pCodeBuf[off++] = 0x23;
849	off = iemNativeEmitGprByGprDisp(pCodeBuf, off, pTlbState->idxReg1,
850	pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, fFlagsAndPhysRev));
851
852	/* cmp reg1, [pVCpu->iem.s.DataTlb.uTlbPhysRev] */
853	pCodeBuf[off++] = X86_OP_REX_W \| (pTlbState->idxReg1 < 8 ? 0 : X86_OP_REX_R);
854	pCodeBuf[off++] = 0x3b;
855	off = iemNativeEmitGprByGprDisp(pCodeBuf, off, pTlbState->idxReg1, IEMNATIVE_REG_FIXED_PVMCPU,
856	offVCpuTlb + RT_UOFFSETOF(IEMTLB, uTlbPhysRev));
857	# elif defined(RT_ARCH_ARM64)
858	# ifdef IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR
859	pCodeBuf[off++] = Armv8A64MkInstrAnd(pTlbState->idxReg1, pTlbState->idxReg1, pTlbState->idxReg4);
860	off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg5);
861	# else
862	off = iemNativeEmitLoadGprByGprU64Ex(pCodeBuf, off, pTlbState->idxReg3,
863	pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, fFlagsAndPhysRev));
864	pCodeBuf[off++] = Armv8A64MkInstrAnd(pTlbState->idxReg1, pTlbState->idxReg1, pTlbState->idxReg3);
865	off = iemNativeEmitLoadGprFromVCpuU64Ex(pCodeBuf, off, pTlbState->idxReg3, offVCpuTlb + RT_UOFFSETOF(IEMTLB, uTlbPhysRev));
866	off = iemNativeEmitCmpGprWithGprEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg3);
867	# endif
868	# else
869	# error "Port me"
870	# endif
871	# ifndef IEM_WITH_TLB_STATISTICS
872	/* jne tlbmiss */
873	off = iemNativeEmitJccToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss, kIemNativeInstrCond_ne);
874	# else
875	/* je 2F; inc stat; jmp tlbmiss */
876	uint32_t const offFixup2 = off;
877	off = iemNativeEmitJccToFixedEx(pCodeBuf, off, off + 16, kIemNativeInstrCond_e);
878	off = iemNativeEmitIncStamCounterInVCpuEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg2,
879	offVCpuTlb + RT_UOFFSETOF(IEMTLB, cTlbNativeMissFlagsAndPhysRev));
880	off = iemNativeEmitJmpToLabelEx(pReNative, pCodeBuf, off, idxLabelTlbMiss);
881	iemNativeFixupFixedJump(pReNative, offFixup2, off);
882	# endif
883
884	/*
885	* 5. Check that pbMappingR3 isn't NULL (paranoia) and calculate the
886	* resulting pointer.
887	*
888	* For code TLB lookups we have some more work to do here to set various
889	* IEMCPU members and we return a GCPhys address rather than a host pointer.
890	*/
891	# if defined(RT_ARCH_ARM64) && defined(IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR)
892	if (!a_fDataTlb)
893	{
894	/* ldp reg4, reg1, [reg2->GCPhys+pbMappingR3] */
895	AssertCompileMemberAlignment(IEMTLBENTRY, GCPhys, 16);
896	AssertCompileAdjacentMembers(IEMTLBENTRY, GCPhys, pbMappingR3);
897	pCodeBuf[off++] = Armv8A64MkInstrLdPairGpr(pTlbState->idxReg4, pTlbState->idxReg1,
898	pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, GCPhys) / 8);
899	}
900	else
901	# endif
902	{
903	/* mov reg1, [reg2->pbMappingR3] */
904	off = iemNativeEmitLoadGprByGprU64Ex(pCodeBuf, off, pTlbState->idxReg1, pTlbState->idxReg2,
905	RT_UOFFSETOF(IEMTLBENTRY, pbMappingR3));
906	}
907	/* if (!reg1) goto tlbmiss; */
908	/** @todo eliminate the need for this test? */
909	off = iemNativeEmitTestIfGprIsZeroAndJmpToLabelEx(pReNative, pCodeBuf, off, pTlbState->idxReg1,
910	true /f64Bit/, idxLabelTlbMiss);
911
912	if (a_fDataTlb)
913	{
914	if (idxRegFlatPtr == idxRegMemResult) /* See step 1b. */
915	{
916	/* and result, 0xfff */
917	off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, idxRegMemResult, GUEST_PAGE_OFFSET_MASK);
918	}
919	else
920	{
921	Assert(idxRegFlatPtr == pTlbState->idxRegPtr);
922	/* result = regflat & 0xfff */
923	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, idxRegMemResult, idxRegFlatPtr, GUEST_PAGE_OFFSET_MASK);
924	}
925
926	/* add result, reg1 */
927	off = iemNativeEmitAddTwoGprsEx(pCodeBuf, off, idxRegMemResult, pTlbState->idxReg1);
928	}
929	else
930	{
931	/*
932	* Code TLB use a la iemOpcodeFetchBytesJmp - keep reg2 pointing to the TLBE.
933	*
934	* Note. We do not need to set offCurInstrStart or offInstrNextByte.
935	*/
936	# if !defined(RT_ARCH_ARM64) \|\| !defined(IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR)
937	# ifdef RT_ARCH_AMD64
938	uint8_t const idxReg3 = UINT8_MAX;
939	# else
940	uint8_t const idxReg3 = pTlbState->idxReg3;
941	# endif
942	/* Set pbInstrBuf first since we've got it loaded already. */
943	off = iemNativeEmitStoreGprToVCpuU64Ex(pCodeBuf, off, pTlbState->idxReg1,
944	RT_UOFFSETOF(VMCPUCC, iem.s.pbInstrBuf), idxReg3);
945	/* Set uInstrBufPc to (FlatPC & ~GUEST_PAGE_OFFSET_MASK). */
946	off = iemNativeEmitGprEqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg1, idxRegFlatPtr, ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK);
947	off = iemNativeEmitStoreGprToVCpuU64Ex(pCodeBuf, off, pTlbState->idxReg1,
948	RT_UOFFSETOF(VMCPUCC, iem.s.uInstrBufPc), idxReg3);
949	/* Set cbInstrBufTotal to GUEST_PAGE_SIZE. / /* @todo this is a simplifications. Calc right size using CS.LIM and EIP? */
950	off = iemNativeEmitStoreImmToVCpuU16Ex(pCodeBuf, off, GUEST_PAGE_SIZE, RT_UOFFSETOF(VMCPUCC, iem.s.cbInstrBufTotal),
951	pTlbState->idxReg1, idxReg3);
952	/* Now set GCPhysInstrBuf last as we'll be returning it in idxRegMemResult. */
953	# if defined(RT_ARCH_ARM64) && defined(IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR)
954	off = iemNativeEmitStoreGprToVCpuU64Ex(pCodeBuf, off, pTlbState->idxReg4,
955	RT_UOFFSETOF(VMCPUCC, iem.s.GCPhysInstrBuf), idxReg3);
956	# else
957	off = iemNativeEmitLoadGprByGprU64Ex(pCodeBuf, off, pTlbState->idxReg1,
958	pTlbState->idxReg2, RT_UOFFSETOF(IEMTLBENTRY, GCPhys));
959	off = iemNativeEmitStoreGprToVCpuU64Ex(pCodeBuf, off, pTlbState->idxReg1,
960	RT_UOFFSETOF(VMCPUCC, iem.s.GCPhysInstrBuf), idxReg3);
961	# endif
962	# else
963	/* ARM64: Same as above but using STP. This ASSUMES that we can trash
964	the 6 bytes following iem.s.cbInstrBufTotal! */
965	AssertCompileMemberAlignment(VMCPUCC, iem.s.pbInstrBuf, 16);
966	AssertCompileAdjacentMembers(VMCPUCC, iem.s.pbInstrBuf, iem.s.uInstrBufPc);
967	AssertCompile(RT_UOFFSETOF(VMCPUCC, iem.s.GCPhysInstrBuf) < 512);
968	/* idxReg1 = reg2->pbMappingR3 (see previous LDP) */
969	/* idxReg3 = FlatPC & ~GUEST_PAGE_OFFSET_MASK. */
970	off = iemNativeEmitGprEqGprAndImmEx(pCodeBuf, off, pTlbState->idxReg3, idxRegFlatPtr, ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK);
971	pCodeBuf[off++] = Armv8A64MkInstrStPairGpr(pTlbState->idxReg1, pTlbState->idxReg3,
972	IEMNATIVE_REG_FIXED_PVMCPU, RT_UOFFSETOF(VMCPUCC, iem.s.pbInstrBuf) / 8);
973
974	AssertCompileMemberAlignment(VMCPUCC, iem.s.GCPhysInstrBuf, 16);
975	AssertCompileAdjacentMembers(VMCPUCC, iem.s.GCPhysInstrBuf, iem.s.cbInstrBufTotal);
976	AssertCompile(RT_UOFFSETOF(VMCPUCC, iem.s.GCPhysInstrBuf) < 512);
977	# ifndef IEM_WITH_OPAQUE_DECODER_STATE
978	AssertCompileAdjacentMembers(VMCPUCC, iem.s.cbInstrBufTotal, iem.s.offCurInstrStart);
979	AssertCompileAdjacentMembers(VMCPUCC, iem.s.offCurInstrStart, iem.s.fPrefixes); /* these two will be set to ~0. */
980	# endif
981	/* idxReg4 = reg2->GCPhys (see previous LDP) */
982	/* idxReg3 = GUEST_PAGE_SIZE \| UINT64_C(0xffffffffffff0000) */
983	pCodeBuf[off++] = Armv8A64MkInstrMovN(pTlbState->idxReg3, ~GUEST_PAGE_SIZE & 0xffff);
984	pCodeBuf[off++] = Armv8A64MkInstrStPairGpr(pTlbState->idxReg4, pTlbState->idxReg3,
985	IEMNATIVE_REG_FIXED_PVMCPU, RT_UOFFSETOF(VMCPUCC, iem.s.GCPhysInstrBuf) / 8);
986	# endif
987	if (!a_fNoReturn) /* (We skip this for iemNativeEmitBltLoadTlbAfterBranch.) */
988	{
989	/* Set idxRegMemResult. */
990	if (idxRegFlatPtr == idxRegMemResult) /* See step 1b. */
991	off = iemNativeEmitAndGpr32ByImmEx(pCodeBuf, off, idxRegMemResult, GUEST_PAGE_OFFSET_MASK);
992	else
993	off = iemNativeEmitGpr32EqGprAndImmEx(pCodeBuf, off, idxRegMemResult, idxRegFlatPtr, GUEST_PAGE_OFFSET_MASK);
994	# if defined(RT_ARCH_ARM64) && defined(IEMNATIVE_WITH_TLB_LOOKUP_LOAD_STORE_PAIR)
995	off = iemNativeEmitAddTwoGprsEx(pCodeBuf, off, idxRegMemResult, pTlbState->idxReg4);
996	# else
997	off = iemNativeEmitAddTwoGprsEx(pCodeBuf, off, idxRegMemResult, pTlbState->idxReg1);
998	# endif
999	}
1000	}
1001
1002	# if 0
1003	/*
1004	* To verify the result we call a helper function.
1005	*
1006	* It's like the state logging, so parameters are passed on the stack.
1007	* iemNativeHlpAsmSafeWrapCheckTlbLookup(pVCpu, result, addr, seg \| (cbMem << 8) \| (fAccess << 16))
1008	*/
1009	# ifdef RT_ARCH_AMD64
1010	if (a_fDataTlb)
1011	{
1012	/* push seg \| (cbMem << 8) \| (fAccess << 16) */
1013	pCodeBuf[off++] = 0x68;
1014	pCodeBuf[off++] = iSegReg;
1015	pCodeBuf[off++] = cbMem;
1016	pCodeBuf[off++] = RT_BYTE1(fAccess);
1017	pCodeBuf[off++] = RT_BYTE2(fAccess);
1018	/* push pTlbState->idxRegPtr / immediate address. */
1019	if (pTlbState->idxRegPtr != UINT8_MAX)
1020	{
1021	if (pTlbState->idxRegPtr >= 8)
1022	pCodeBuf[off++] = X86_OP_REX_B;
1023	pCodeBuf[off++] = 0x50 + (pTlbState->idxRegPtr & 7);
1024	}
1025	else
1026	{
1027	off = iemNativeEmitLoadGprImmEx(pCodeBuf, off, pTlbState->idxReg1, pTlbState->uAbsPtr);
1028	if (pTlbState->idxReg1 >= 8)
1029	pCodeBuf[off++] = X86_OP_REX_B;
1030	pCodeBuf[off++] = 0x50 + (pTlbState->idxReg1 & 7);
1031	}
1032	/* push idxRegMemResult */
1033	if (idxRegMemResult >= 8)
1034	pCodeBuf[off++] = X86_OP_REX_B;
1035	pCodeBuf[off++] = 0x50 + (idxRegMemResult & 7);
1036	/* push pVCpu */
1037	pCodeBuf[off++] = 0x50 + IEMNATIVE_REG_FIXED_PVMCPU;
1038	/* mov reg1, helper */
1039	off = iemNativeEmitLoadGprImmEx(pCodeBuf, off, pTlbState->idxReg1, (uintptr_t)iemNativeHlpAsmSafeWrapCheckTlbLookup);
1040	/* call [reg1] */
1041	pCodeBuf[off++] = X86_OP_REX_W \| (pTlbState->idxReg1 < 8 ? 0 : X86_OP_REX_B);
1042	pCodeBuf[off++] = 0xff;
1043	pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, 2, pTlbState->idxReg1 & 7);
1044	/* The stack is cleaned up by helper function. */
1045	}
1046
1047	# else
1048	# error "Port me"
1049	# endif
1050	# endif
1051
1052	IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off);
1053
1054	return off;
1055	}
1056	#endif /* IEMNATIVE_WITH_TLB_LOOKUP */
1057
1058
1059	/** @} */
1060
1061	#endif /* !VMM_INCLUDED_SRC_include_IEMN8veRecompilerTlbLookup_h */
1062

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source: vbox/trunk/src/VBox/VMM/include/IEMN8veRecompilerTlbLookup.h@ 104984

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