VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PDMInternal.h@ 107623

Last change on this file since 107623 was 107308, checked in by vboxsync, 2 months ago

VMM: bugref:10759 Refactor GIC for use with different backends.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 79.7 KB
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1/* $Id: PDMInternal.h 107308 2024-12-13 08:09:39Z vboxsync $ */
2/** @file
3 * PDM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_PDMInternal_h
29#define VMM_INCLUDED_SRC_include_PDMInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/types.h>
35#include <VBox/param.h>
36#include <VBox/vmm/cfgm.h>
37#include <VBox/vmm/stam.h>
38#include <VBox/vusb.h>
39#include <VBox/vmm/iom.h>
40#include <VBox/vmm/pdmasynccompletion.h>
41#ifdef VBOX_WITH_NETSHAPER
42# include <VBox/vmm/pdmnetshaper.h>
43#endif
44#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
45# include <VBox/vmm/pdmasynccompletion.h>
46#endif
47#include <VBox/vmm/pdmblkcache.h>
48#include <VBox/vmm/pdmcommon.h>
49#include <VBox/vmm/pdmtask.h>
50#ifdef VBOX_VMM_TARGET_ARMV8
51# include <VBox/vmm/pdmgic.h>
52#else
53# include <VBox/vmm/pdmapic.h>
54#endif
55#include <VBox/sup.h>
56#include <VBox/msi.h>
57#include <iprt/assert.h>
58#include <iprt/critsect.h>
59#ifdef IN_RING3
60# include <iprt/thread.h>
61#endif
62
63RT_C_DECLS_BEGIN
64
65
66/** @defgroup grp_pdm_int Internal
67 * @ingroup grp_pdm
68 * @internal
69 * @{
70 */
71
72/** @def PDM_WITH_R3R0_CRIT_SECT
73 * Enables or disabled ring-3/ring-0 critical sections. */
74#if defined(DOXYGEN_RUNNING) || 1
75# define PDM_WITH_R3R0_CRIT_SECT
76#endif
77
78/** @def PDMCRITSECT_STRICT
79 * Enables/disables PDM critsect strictness like deadlock detection. */
80#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECT_STRICT)) \
81 || defined(DOXYGEN_RUNNING)
82# define PDMCRITSECT_STRICT
83#endif
84
85/** @def PDMCRITSECT_STRICT
86 * Enables/disables PDM read/write critsect strictness like deadlock
87 * detection. */
88#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECTRW_STRICT)) \
89 || defined(DOXYGEN_RUNNING)
90# define PDMCRITSECTRW_STRICT
91#endif
92
93/** The maximum device instance (total) size, ring-0/raw-mode capable devices. */
94#define PDM_MAX_DEVICE_INSTANCE_SIZE _4M
95/** The maximum device instance (total) size, ring-3 only devices. */
96#define PDM_MAX_DEVICE_INSTANCE_SIZE_R3 _8M
97/** The maximum size for the DBGF tracing tracking structure allocated for each device. */
98#define PDM_MAX_DEVICE_DBGF_TRACING_TRACK HOST_PAGE_SIZE
99
100
101
102/*******************************************************************************
103* Structures and Typedefs *
104*******************************************************************************/
105
106/** Pointer to a PDM Device. */
107typedef struct PDMDEV *PPDMDEV;
108/** Pointer to a pointer to a PDM Device. */
109typedef PPDMDEV *PPPDMDEV;
110
111/** Pointer to a PDM USB Device. */
112typedef struct PDMUSB *PPDMUSB;
113/** Pointer to a pointer to a PDM USB Device. */
114typedef PPDMUSB *PPPDMUSB;
115
116/** Pointer to a PDM Driver. */
117typedef struct PDMDRV *PPDMDRV;
118/** Pointer to a pointer to a PDM Driver. */
119typedef PPDMDRV *PPPDMDRV;
120
121/** Pointer to a PDM Logical Unit. */
122typedef struct PDMLUN *PPDMLUN;
123/** Pointer to a pointer to a PDM Logical Unit. */
124typedef PPDMLUN *PPPDMLUN;
125
126/** Pointer to a DMAC instance. */
127typedef struct PDMDMAC *PPDMDMAC;
128/** Pointer to a RTC instance. */
129typedef struct PDMRTC *PPDMRTC;
130
131/** Pointer to an USB HUB registration record. */
132typedef struct PDMUSBHUB *PPDMUSBHUB;
133
134/**
135 * Supported asynchronous completion endpoint classes.
136 */
137typedef enum PDMASYNCCOMPLETIONEPCLASSTYPE
138{
139 /** File class. */
140 PDMASYNCCOMPLETIONEPCLASSTYPE_FILE = 0,
141 /** Number of supported classes. */
142 PDMASYNCCOMPLETIONEPCLASSTYPE_MAX,
143 /** 32bit hack. */
144 PDMASYNCCOMPLETIONEPCLASSTYPE_32BIT_HACK = 0x7fffffff
145} PDMASYNCCOMPLETIONEPCLASSTYPE;
146
147
148/**
149 * MMIO/IO port registration tracking structure for DBGF tracing.
150 */
151typedef struct PDMDEVINSDBGFTRACK
152{
153 /** Flag whether this tracks a IO port or MMIO registration. */
154 bool fMmio;
155 /** Opaque user data passed during registration. */
156 void *pvUser;
157 /** Type dependent data. */
158 union
159 {
160 /** I/O port registration. */
161 struct
162 {
163 /** IOM I/O port handle. */
164 IOMIOPORTHANDLE hIoPorts;
165 /** Original OUT handler of the device. */
166 PFNIOMIOPORTNEWOUT pfnOut;
167 /** Original IN handler of the device. */
168 PFNIOMIOPORTNEWIN pfnIn;
169 /** Original string OUT handler of the device. */
170 PFNIOMIOPORTNEWOUTSTRING pfnOutStr;
171 /** Original string IN handler of the device. */
172 PFNIOMIOPORTNEWINSTRING pfnInStr;
173 } IoPort;
174 /** MMIO registration. */
175 struct
176 {
177 /** IOM MMIO region handle. */
178 IOMMMIOHANDLE hMmioRegion;
179 /** Original MMIO write handler of the device. */
180 PFNIOMMMIONEWWRITE pfnWrite;
181 /** Original MMIO read handler of the device. */
182 PFNIOMMMIONEWREAD pfnRead;
183 /** Original MMIO fill handler of the device. */
184 PFNIOMMMIONEWFILL pfnFill;
185 } Mmio;
186 } u;
187} PDMDEVINSDBGFTRACK;
188/** Pointer to a MMIO/IO port registration tracking structure. */
189typedef PDMDEVINSDBGFTRACK *PPDMDEVINSDBGFTRACK;
190/** Pointer to a const MMIO/IO port registration tracking structure. */
191typedef const PDMDEVINSDBGFTRACK *PCPDMDEVINSDBGFTRACK;
192
193
194/**
195 * Private device instance data, ring-3.
196 */
197typedef struct PDMDEVINSINTR3
198{
199 /** Pointer to the next instance.
200 * (Head is pointed to by PDM::pDevInstances.) */
201 R3PTRTYPE(PPDMDEVINS) pNextR3;
202 /** Pointer to the next per device instance.
203 * (Head is pointed to by PDMDEV::pInstances.) */
204 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
205 /** Pointer to device structure. */
206 R3PTRTYPE(PPDMDEV) pDevR3;
207 /** Pointer to the list of logical units associated with the device. (FIFO) */
208 R3PTRTYPE(PPDMLUN) pLunsR3;
209 /** Pointer to the asynchronous notification callback set while in
210 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
211 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
212 /** Configuration handle to the instance node. */
213 R3PTRTYPE(PCFGMNODE) pCfgHandle;
214
215 /** R3 pointer to the VM this instance was created for. */
216 PVMR3 pVMR3;
217 /** DBGF trace event source handle if tracing is configured. */
218 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
219 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
220 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
221 /** Index of the next entry to use for tracking. */
222 uint32_t idxDbgfTraceTrackNext;
223 /** Maximum number of records fitting into the single page. */
224 uint32_t cDbgfTraceTrackMax;
225
226 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
227 uint32_t fIntFlags;
228 /** The last IRQ tag (for tracing it thru clearing). */
229 uint32_t uLastIrqTag;
230 /** The ring-0 device index (for making ring-0 calls). */
231 uint32_t idxR0Device;
232} PDMDEVINSINTR3;
233
234
235/**
236 * Private device instance data, ring-0.
237 */
238typedef struct PDMDEVINSINTR0
239{
240 /** Pointer to the VM this instance was created for. */
241 R0PTRTYPE(PGVM) pGVM;
242 /** Pointer to device structure. */
243 R0PTRTYPE(struct PDMDEVREGR0 const *) pRegR0;
244 /** The ring-0 module reference. */
245 RTR0PTR hMod;
246 /** Pointer to the ring-0 mapping of the ring-3 internal data (for uLastIrqTag). */
247 R0PTRTYPE(PDMDEVINSINTR3 *) pIntR3R0;
248 /** Pointer to the ring-0 mapping of the ring-3 instance (for idTracing). */
249 R0PTRTYPE(struct PDMDEVINSR3 *) pInsR3R0;
250 /** DBGF trace event source handle if tracing is configured. */
251 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
252 /** The device instance memory. */
253 RTR0MEMOBJ hMemObj;
254 /** The ring-3 mapping object. */
255 RTR0MEMOBJ hMapObj;
256 /** The page memory object for tracking MMIO and I/O port registrations when tracing is configured. */
257 RTR0MEMOBJ hDbgfTraceObj;
258 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
259 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
260 /** Index of the next entry to use for tracking. */
261 uint32_t idxDbgfTraceTrackNext;
262 /** Maximum number of records fitting into the single page. */
263 uint32_t cDbgfTraceTrackMax;
264 /** Index into PDMR0PERVM::apDevInstances. */
265 uint32_t idxR0Device;
266} PDMDEVINSINTR0;
267
268
269/**
270 * Private device instance data, raw-mode
271 */
272typedef struct PDMDEVINSINTRC
273{
274 /** Pointer to the VM this instance was created for. */
275 RGPTRTYPE(PVM) pVMRC;
276} PDMDEVINSINTRC;
277
278
279/**
280 * Private device instance data.
281 */
282typedef struct PDMDEVINSINT
283{
284 /** Pointer to the next instance (HC Ptr).
285 * (Head is pointed to by PDM::pDevInstances.) */
286 R3PTRTYPE(PPDMDEVINS) pNextR3;
287 /** Pointer to the next per device instance (HC Ptr).
288 * (Head is pointed to by PDMDEV::pInstances.) */
289 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
290 /** Pointer to device structure - HC Ptr. */
291 R3PTRTYPE(PPDMDEV) pDevR3;
292 /** Pointer to the list of logical units associated with the device. (FIFO) */
293 R3PTRTYPE(PPDMLUN) pLunsR3;
294 /** Pointer to the asynchronous notification callback set while in
295 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
296 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
297 /** Configuration handle to the instance node. */
298 R3PTRTYPE(PCFGMNODE) pCfgHandle;
299
300 /** R3 pointer to the VM this instance was created for. */
301 PVMR3 pVMR3;
302
303 /** R0 pointer to the VM this instance was created for. */
304 R0PTRTYPE(PVMCC) pVMR0;
305
306 /** RC pointer to the VM this instance was created for. */
307 PVMRC pVMRC;
308
309 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
310 uint32_t fIntFlags;
311 /** The last IRQ tag (for tracing it thru clearing). */
312 uint32_t uLastIrqTag;
313} PDMDEVINSINT;
314
315/** @name PDMDEVINSINT::fIntFlags
316 * @{ */
317/** Used by pdmR3Load to mark device instances it found in the saved state. */
318#define PDMDEVINSINT_FLAGS_FOUND RT_BIT_32(0)
319/** Indicates that the device hasn't been powered on or resumed.
320 * This is used by PDMR3PowerOn, PDMR3Resume, PDMR3Suspend and PDMR3PowerOff
321 * to make sure each device gets exactly one notification for each of those
322 * events. PDMR3Resume and PDMR3PowerOn also makes use of it to bail out on
323 * a failure (already resumed/powered-on devices are suspended).
324 * PDMR3PowerOff resets this flag once before going through the devices to make sure
325 * every device gets the power off notification even if it was suspended before with
326 * PDMR3Suspend.
327 */
328#define PDMDEVINSINT_FLAGS_SUSPENDED RT_BIT_32(1)
329/** Indicates that the device has been reset already. Used by PDMR3Reset. */
330#define PDMDEVINSINT_FLAGS_RESET RT_BIT_32(2)
331#define PDMDEVINSINT_FLAGS_R0_ENABLED RT_BIT_32(3)
332#define PDMDEVINSINT_FLAGS_RC_ENABLED RT_BIT_32(4)
333/** Set if we've called the ring-0 constructor. */
334#define PDMDEVINSINT_FLAGS_R0_CONTRUCT RT_BIT_32(5)
335/** Set if using non-default critical section. */
336#define PDMDEVINSINT_FLAGS_CHANGED_CRITSECT RT_BIT_32(6)
337/** @} */
338
339
340/**
341 * Private USB device instance data.
342 */
343typedef struct PDMUSBINSINT
344{
345 /** The UUID of this instance. */
346 RTUUID Uuid;
347 /** Pointer to the next instance.
348 * (Head is pointed to by PDM::pUsbInstances.) */
349 R3PTRTYPE(PPDMUSBINS) pNext;
350 /** Pointer to the next per USB device instance.
351 * (Head is pointed to by PDMUSB::pInstances.) */
352 R3PTRTYPE(PPDMUSBINS) pPerDeviceNext;
353
354 /** Pointer to device structure. */
355 R3PTRTYPE(PPDMUSB) pUsbDev;
356
357 /** Pointer to the VM this instance was created for. */
358 PVMR3 pVM;
359 /** Pointer to the list of logical units associated with the device. (FIFO) */
360 R3PTRTYPE(PPDMLUN) pLuns;
361 /** The per instance device configuration. */
362 R3PTRTYPE(PCFGMNODE) pCfg;
363 /** Same as pCfg if the configuration should be deleted when detaching the device. */
364 R3PTRTYPE(PCFGMNODE) pCfgDelete;
365 /** The global device configuration. */
366 R3PTRTYPE(PCFGMNODE) pCfgGlobal;
367
368 /** Pointer to the USB hub this device is attached to.
369 * This is NULL if the device isn't connected to any HUB. */
370 R3PTRTYPE(PPDMUSBHUB) pHub;
371 /** The port number that we're connected to. */
372 uint32_t iPort;
373 /** Indicates that the USB device hasn't been powered on or resumed.
374 * See PDMDEVINSINT_FLAGS_SUSPENDED.
375 * @note Runtime attached USB devices gets a pfnHotPlugged callback rather than
376 * a pfnVMResume one. */
377 bool fVMSuspended;
378 /** Indicates that the USB device has been reset. */
379 bool fVMReset;
380 /** Pointer to the asynchronous notification callback set while in
381 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
382 R3PTRTYPE(PFNPDMUSBASYNCNOTIFY) pfnAsyncNotify;
383} PDMUSBINSINT;
384
385
386/**
387 * Private driver instance data.
388 */
389typedef struct PDMDRVINSINT
390{
391 /** Pointer to the driver instance above.
392 * This is NULL for the topmost drive. */
393 R3PTRTYPE(PPDMDRVINS) pUp;
394 /** Pointer to the driver instance below.
395 * This is NULL for the bottommost driver. */
396 R3PTRTYPE(PPDMDRVINS) pDown;
397 /** Pointer to the logical unit this driver chained on. */
398 R3PTRTYPE(PPDMLUN) pLun;
399 /** Pointer to driver structure from which this was instantiated. */
400 R3PTRTYPE(PPDMDRV) pDrv;
401 /** Pointer to the VM this instance was created for, ring-3 context. */
402 PVMR3 pVMR3;
403 /** Pointer to the VM this instance was created for, ring-0 context. */
404 R0PTRTYPE(PVMCC) pVMR0;
405 /** Pointer to the VM this instance was created for, raw-mode context. */
406 PVMRC pVMRC;
407 /** Flag indicating that the driver is being detached and destroyed.
408 * (Helps detect potential recursive detaching.) */
409 bool fDetaching;
410 /** Indicates that the driver hasn't been powered on or resumed.
411 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
412 bool fVMSuspended;
413 /** Indicates that the driver has been reset already. */
414 bool fVMReset;
415 /** Set if allocated on the hyper heap, false if on the ring-3 heap. */
416 bool fHyperHeap;
417 /** Pointer to the asynchronous notification callback set while in
418 * PDMUSBREG::pfnVMSuspend or PDMUSBREG::pfnVMPowerOff. */
419 R3PTRTYPE(PFNPDMDRVASYNCNOTIFY) pfnAsyncNotify;
420 /** Configuration handle to the instance node. */
421 R3PTRTYPE(PCFGMNODE) pCfgHandle;
422 /** Pointer to the ring-0 request handler function. */
423 PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
424 /** Pointer to the next instance (starts at PDMDRV::pInstances). */
425 R3PTRTYPE(PPDMDRVINS) pNext;
426} PDMDRVINSINT;
427
428
429/**
430 * Private critical section data.
431 */
432typedef struct PDMCRITSECTINT
433{
434 /** The critical section core which is shared with IPRT.
435 * @note The semaphore is a SUPSEMEVENT. */
436 RTCRITSECT Core;
437 /** Pointer to the next critical section.
438 * This chain is used for device cleanup and the dbgf info item. */
439 R3PTRTYPE(struct PDMCRITSECTINT *) pNext;
440 /** Owner identifier.
441 * This is pDevIns if the owner is a device. Similarly for a driver or service.
442 * PDMR3CritSectInit() sets this to point to the critsect itself. */
443 RTR3PTR pvKey;
444 /** Set if this critical section is the automatically created default
445 * section of a device. */
446 bool fAutomaticDefaultCritsect;
447 /** Set if the critical section is used by a timer or similar.
448 * See PDMR3DevGetCritSect. */
449 bool fUsedByTimerOrSimilar;
450 /** Alignment padding. */
451 bool afPadding[2+4];
452 /** Support driver event semaphore that is scheduled to be signaled upon leaving
453 * the critical section. This is only for Ring-3 and Ring-0. */
454 SUPSEMEVENT volatile hEventToSignal;
455 /** The lock name. */
456 R3PTRTYPE(const char *) pszName;
457 /** The ring-3 pointer to this critical section, for leave queueing. */
458 R3PTRTYPE(PPDMCRITSECT) pSelfR3;
459 /** R0/RC lock contention. */
460 STAMCOUNTER StatContentionRZLock;
461 /** R0/RC lock contention: returning rcBusy or VERR_SEM_BUSY (try). */
462 STAMCOUNTER StatContentionRZLockBusy;
463 /** R0/RC lock contention: Profiling waiting time. */
464 STAMPROFILE StatContentionRZWait;
465 /** R0/RC unlock contention. */
466 STAMCOUNTER StatContentionRZUnlock;
467 /** R3 lock contention. */
468 STAMCOUNTER StatContentionR3;
469 /** R3 lock contention: Profiling waiting time. */
470 STAMPROFILE StatContentionR3Wait;
471 /** Profiling the time the section is locked. */
472 STAMPROFILEADV StatLocked;
473} PDMCRITSECTINT;
474AssertCompileMemberAlignment(PDMCRITSECTINT, StatContentionRZLock, 8);
475/** Pointer to private critical section data. */
476typedef PDMCRITSECTINT *PPDMCRITSECTINT;
477
478/** Special magic value set when we failed to abort entering in ring-0 due to a
479 * timeout, interruption or pending thread termination. */
480#define PDMCRITSECT_MAGIC_FAILED_ABORT UINT32_C(0x0bad0326)
481/** Special magic value set if we detected data/state corruption. */
482#define PDMCRITSECT_MAGIC_CORRUPTED UINT32_C(0x0bad2603)
483
484/** Indicates that the critical section is queued for unlock.
485 * PDMCritSectIsOwner and PDMCritSectIsOwned optimizations. */
486#define PDMCRITSECT_FLAGS_PENDING_UNLOCK RT_BIT_32(17)
487
488
489/**
490 * Private critical section data.
491 */
492typedef struct PDMCRITSECTRWINT
493{
494 /** The read/write critical section core which is shared with IPRT.
495 * @note The semaphores are SUPSEMEVENT and SUPSEMEVENTMULTI. */
496 RTCRITSECTRW Core;
497
498 /** Pointer to the next critical section.
499 * This chain is used for device cleanup and the dbgf info item. */
500 R3PTRTYPE(struct PDMCRITSECTRWINT *) pNext;
501 /** Self pointer. */
502 R3PTRTYPE(PPDMCRITSECTRW) pSelfR3;
503 /** Owner identifier.
504 * This is pDevIns if the owner is a device. Similarly for a driver or service.
505 * PDMR3CritSectRwInit() sets this to point to the critsect itself. */
506 RTR3PTR pvKey;
507 /** The lock name. */
508 R3PTRTYPE(const char *) pszName;
509
510 /** R0/RC write lock contention. */
511 STAMCOUNTER StatContentionRZEnterExcl;
512 /** R0/RC write unlock contention. */
513 STAMCOUNTER StatContentionRZLeaveExcl;
514 /** R0/RC read lock contention. */
515 STAMCOUNTER StatContentionRZEnterShared;
516 /** R0/RC read unlock contention. */
517 STAMCOUNTER StatContentionRZLeaveShared;
518 /** R0/RC writes. */
519 STAMCOUNTER StatRZEnterExcl;
520 /** R0/RC reads. */
521 STAMCOUNTER StatRZEnterShared;
522 /** R3 write lock contention. */
523 STAMCOUNTER StatContentionR3EnterExcl;
524 /** R3 write unlock contention. */
525 STAMCOUNTER StatContentionR3LeaveExcl;
526 /** R3 read lock contention. */
527 STAMCOUNTER StatContentionR3EnterShared;
528 /** R3 writes. */
529 STAMCOUNTER StatR3EnterExcl;
530 /** R3 reads. */
531 STAMCOUNTER StatR3EnterShared;
532 /** Profiling the time the section is write locked. */
533 STAMPROFILEADV StatWriteLocked;
534} PDMCRITSECTRWINT;
535AssertCompileMemberAlignment(PDMCRITSECTRWINT, StatContentionRZEnterExcl, 8);
536AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u, 16);
537AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u.s.u64State, 8);
538/** Pointer to private critical section data. */
539typedef PDMCRITSECTRWINT *PPDMCRITSECTRWINT;
540
541/** Special magic value we set the structure has become corrupted. */
542#define PDMCRITSECTRW_MAGIC_CORRUPT UINT32_C(0x0bad0620)
543
544
545/**
546 * The usual device/driver/internal/external stuff.
547 */
548typedef enum
549{
550 /** The usual invalid entry. */
551 PDMTHREADTYPE_INVALID = 0,
552 /** Device type. */
553 PDMTHREADTYPE_DEVICE,
554 /** USB Device type. */
555 PDMTHREADTYPE_USB,
556 /** Driver type. */
557 PDMTHREADTYPE_DRIVER,
558 /** Internal type. */
559 PDMTHREADTYPE_INTERNAL,
560 /** External type. */
561 PDMTHREADTYPE_EXTERNAL,
562 /** The usual 32-bit hack. */
563 PDMTHREADTYPE_32BIT_HACK = 0x7fffffff
564} PDMTHREADTYPE;
565
566
567/**
568 * The internal structure for the thread.
569 */
570typedef struct PDMTHREADINT
571{
572 /** The VM pointer. */
573 PVMR3 pVM;
574 /** The event semaphore the thread blocks on when not running. */
575 RTSEMEVENTMULTI BlockEvent;
576 /** The event semaphore the thread sleeps on while running. */
577 RTSEMEVENTMULTI SleepEvent;
578 /** Pointer to the next thread. */
579 R3PTRTYPE(struct PDMTHREAD *) pNext;
580 /** The thread type. */
581 PDMTHREADTYPE enmType;
582} PDMTHREADINT;
583
584
585
586/* Must be included after PDMDEVINSINT is defined. */
587#define PDMDEVINSINT_DECLARED
588#define PDMUSBINSINT_DECLARED
589#define PDMDRVINSINT_DECLARED
590#define PDMCRITSECTINT_DECLARED
591#define PDMCRITSECTRWINT_DECLARED
592#define PDMTHREADINT_DECLARED
593#ifdef ___VBox_pdm_h
594# error "Invalid header PDM order. Include PDMInternal.h before VBox/vmm/pdm.h!"
595#endif
596RT_C_DECLS_END
597#include <VBox/vmm/pdm.h>
598RT_C_DECLS_BEGIN
599
600/**
601 * PDM Logical Unit.
602 *
603 * This typically the representation of a physical port on a
604 * device, like for instance the PS/2 keyboard port on the
605 * keyboard controller device. The LUNs are chained on the
606 * device they belong to (PDMDEVINSINT::pLunsR3).
607 */
608typedef struct PDMLUN
609{
610 /** The LUN - The Logical Unit Number. */
611 RTUINT iLun;
612 /** Pointer to the next LUN. */
613 PPDMLUN pNext;
614 /** Pointer to the top driver in the driver chain. */
615 PPDMDRVINS pTop;
616 /** Pointer to the bottom driver in the driver chain. */
617 PPDMDRVINS pBottom;
618 /** Pointer to the device instance which the LUN belongs to.
619 * Either this is set or pUsbIns is set. Both are never set at the same time. */
620 PPDMDEVINS pDevIns;
621 /** Pointer to the USB device instance which the LUN belongs to. */
622 PPDMUSBINS pUsbIns;
623 /** Pointer to the device base interface. */
624 PPDMIBASE pBase;
625 /** Description of this LUN. */
626 const char *pszDesc;
627} PDMLUN;
628
629
630/**
631 * PDM Device, ring-3.
632 */
633typedef struct PDMDEV
634{
635 /** Pointer to the next device (R3 Ptr). */
636 R3PTRTYPE(PPDMDEV) pNext;
637 /** Device name length. (search optimization) */
638 uint32_t cchName;
639 /** Registration structure. */
640 R3PTRTYPE(const struct PDMDEVREGR3 *) pReg;
641 /** Number of instances. */
642 uint32_t cInstances;
643 /** Pointer to chain of instances (R3 Ptr). */
644 PPDMDEVINSR3 pInstances;
645 /** The search path for raw-mode context modules (';' as separator). */
646 char *pszRCSearchPath;
647 /** The search path for ring-0 context modules (';' as separator). */
648 char *pszR0SearchPath;
649} PDMDEV;
650
651
652#if 0
653/**
654 * PDM Device, ring-0.
655 */
656typedef struct PDMDEVR0
657{
658 /** Pointer to the next device. */
659 R0PTRTYPE(PPDMDEVR0) pNext;
660 /** Device name length. (search optimization) */
661 uint32_t cchName;
662 /** Registration structure. */
663 R3PTRTYPE(const struct PDMDEVREGR0 *) pReg;
664 /** Number of instances. */
665 uint32_t cInstances;
666 /** Pointer to chain of instances. */
667 PPDMDEVINSR0 pInstances;
668} PDMDEVR0;
669#endif
670
671
672/**
673 * PDM USB Device.
674 */
675typedef struct PDMUSB
676{
677 /** Pointer to the next device (R3 Ptr). */
678 R3PTRTYPE(PPDMUSB) pNext;
679 /** Device name length. (search optimization) */
680 RTUINT cchName;
681 /** Registration structure. */
682 R3PTRTYPE(const struct PDMUSBREG *) pReg;
683 /** Next instance number. */
684 uint32_t iNextInstance;
685 /** Pointer to chain of instances (R3 Ptr). */
686 R3PTRTYPE(PPDMUSBINS) pInstances;
687} PDMUSB;
688
689
690/**
691 * PDM Driver.
692 */
693typedef struct PDMDRV
694{
695 /** Pointer to the next device. */
696 PPDMDRV pNext;
697 /** Registration structure. */
698 const struct PDMDRVREG * pReg;
699 /** Current number of instances. */
700 uint32_t cInstances;
701 /** The next instance number. */
702 uint32_t iNextInstance;
703 /** The search path for raw-mode context modules (';' as separator). */
704 char *pszRCSearchPath;
705 /** The search path for ring-0 context modules (';' as separator). */
706 char *pszR0SearchPath;
707 /** Pointer to chain of instances. */
708 PPDMDRVINSR3 pInstances;
709} PDMDRV;
710
711
712/**
713 * PDM IOMMU, shared ring-3.
714 */
715typedef struct PDMIOMMUR3
716{
717 /** IOMMU index. */
718 uint32_t idxIommu;
719 uint32_t uPadding0; /**< Alignment padding.*/
720
721 /** Pointer to the IOMMU device instance - R3. */
722 PPDMDEVINSR3 pDevInsR3;
723 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
724 DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
725 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
726 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
727 DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
728 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
729 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
730 DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
731} PDMIOMMUR3;
732/** Pointer to a PDM IOMMU instance. */
733typedef PDMIOMMUR3 *PPDMIOMMUR3;
734/** Pointer to a const PDM IOMMU instance. */
735typedef const PDMIOMMUR3 *PCPDMIOMMUR3;
736
737
738/**
739 * PDM IOMMU, ring-0.
740 */
741typedef struct PDMIOMMUR0
742{
743 /** IOMMU index. */
744 uint32_t idxIommu;
745 uint32_t uPadding0; /**< Alignment padding.*/
746
747 /** Pointer to IOMMU device instance. */
748 PPDMDEVINSR0 pDevInsR0;
749 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
750 DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
751 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
752 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
753 DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
754 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
755 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
756 DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
757} PDMIOMMUR0;
758/** Pointer to a ring-0 IOMMU data. */
759typedef PDMIOMMUR0 *PPDMIOMMUR0;
760/** Pointer to a const ring-0 IOMMU data. */
761typedef const PDMIOMMUR0 *PCPDMIOMMUR0;
762
763/** Pointer to a PDM IOMMU for the current context. */
764#ifdef IN_RING3
765typedef PPDMIOMMUR3 PPDMIOMMU;
766#else
767typedef PPDMIOMMUR0 PPDMIOMMU;
768#endif
769
770
771/**
772 * PDM registered PIC device.
773 */
774typedef struct PDMPIC
775{
776 /** Pointer to the PIC device instance - R3. */
777 PPDMDEVINSR3 pDevInsR3;
778 /** @copydoc PDMPICREG::pfnSetIrq */
779 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
780 /** @copydoc PDMPICREG::pfnGetInterrupt */
781 DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
782
783 /** Pointer to the PIC device instance - R0. */
784 PPDMDEVINSR0 pDevInsR0;
785 /** @copydoc PDMPICREG::pfnSetIrq */
786 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
787 /** @copydoc PDMPICREG::pfnGetInterrupt */
788 DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
789
790 /** Pointer to the PIC device instance - RC. */
791 PPDMDEVINSRC pDevInsRC;
792 /** @copydoc PDMPICREG::pfnSetIrq */
793 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
794 /** @copydoc PDMPICREG::pfnGetInterrupt */
795 DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
796 /** Alignment padding. */
797 RTRCPTR RCPtrPadding;
798} PDMPIC;
799
800
801/**
802 * PDM IC (Interrupt Controller), shared ring-3.
803 */
804typedef struct PDMICR3
805{
806 /** Pointer to the interrupt controller instance - R3 Ptr. */
807 PPDMDEVINSR3 pDevInsR3;
808 union
809 {
810#if defined(VBOX_VMM_TARGET_X86) || defined(VBOX_VMM_TARGET_AGNOSTIC)
811 struct
812 {
813 /** The type of APIC backend. */
814 PDMAPICBACKENDTYPE enmKind;
815 uint32_t uPadding;
816 /** The APIC backend. */
817 PDMAPICBACKENDR3 ApicBackend;
818 } x86;
819#endif
820#ifdef VBOX_VMM_TARGET_ARMV8
821 struct
822 {
823 /** The type of GIC backend. */
824 PDMGICBACKENDTYPE enmKind;
825 uint32_t uPadding;
826 /** The APIC backend. */
827 PDMGICBACKENDR3 GicBackend;
828 } armv8;
829#endif
830 uint8_t abPadding[256-8];
831 } u;
832} PDMICR3;
833AssertCompileSizeAlignment(PDMICR3, 8);
834
835/**
836 * PDM IC (Interrupt Controller), ring-0.
837 */
838typedef struct PDMICR0
839{
840 /** Pointer to the interrupt controller instance - R0 Ptr. */
841 PPDMDEVINSR0 pDevInsR0;
842 union
843 {
844#if defined(VBOX_VMM_TARGET_X86) || defined(VBOX_VMM_TARGET_AGNOSTIC)
845 struct
846 {
847 /** The APIC backend. */
848 PDMAPICBACKENDR0 ApicBackend;
849 } x86;
850#endif
851 /** Padding to keep alignment common between x86 and arm (there's no ring-0
852 * armv8 code. */
853 uint8_t abPadding[256-8];
854 } u;
855} PDMICR0;
856AssertCompileSizeAlignment(PDMICR0, 8);
857
858/**
859 * PDM IC (Interrupt Controller), raw-mode context.
860 */
861typedef struct PDMICRC
862{
863 /** Pointer to the interrupt controller instance - RC Ptr. */
864 PPDMDEVINSRC pDevInsR0;
865 RTRCPTR avPadding;
866 union
867 {
868#if defined(VBOX_VMM_TARGET_X86) || defined(VBOX_VMM_TARGET_AGNOSTIC)
869 struct
870 {
871 /** The APIC backend. */
872 PDMAPICBACKENDRC ApicBackend;
873 } x86;
874#endif
875 /** Padding to keep alignment common between x86 and arm (there's no ring-context
876 * armv8 code. */
877 uint8_t abPadding[256-4-4];
878 } u;
879} PDMICRC;
880AssertCompileSizeAlignment(PDMICRC, 8);
881
882/**
883 * PDM registered I/O APIC device.
884 */
885typedef struct PDMIOAPIC
886{
887 /** Pointer to the I/O APIC device instance - R3 Ptr. */
888 PPDMDEVINSR3 pDevInsR3;
889 /** @copydoc PDMIOAPICREG::pfnSetIrq */
890 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
891 /** @copydoc PDMIOAPICREG::pfnSendMsi */
892 DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
893 /** @copydoc PDMIOAPICREG::pfnSetEoi */
894 DECLR3CALLBACKMEMBER(void, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
895
896 /** Pointer to the I/O APIC device instance - R0. */
897 PPDMDEVINSR0 pDevInsR0;
898 /** @copydoc PDMIOAPICREG::pfnSetIrq */
899 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
900 /** @copydoc PDMIOAPICREG::pfnSendMsi */
901 DECLR0CALLBACKMEMBER(void, pfnSendMsiR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
902 /** @copydoc PDMIOAPICREG::pfnSetEoi */
903 DECLR0CALLBACKMEMBER(void, pfnSetEoiR0,(PPDMDEVINS pDevIns, uint8_t u8Vector));
904
905 /** Pointer to the I/O APIC device instance - RC Ptr. */
906 PPDMDEVINSRC pDevInsRC;
907 /** @copydoc PDMIOAPICREG::pfnSetIrq */
908 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
909 /** @copydoc PDMIOAPICREG::pfnSendMsi */
910 DECLRCCALLBACKMEMBER(void, pfnSendMsiRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
911 /** @copydoc PDMIOAPICREG::pfnSendMsi */
912 DECLRCCALLBACKMEMBER(void, pfnSetEoiRC,(PPDMDEVINS pDevIns, uint8_t u8Vector));
913} PDMIOAPIC;
914/** Pointer to a PDM IOAPIC instance. */
915typedef PDMIOAPIC *PPDMIOAPIC;
916/** Pointer to a const PDM IOAPIC instance. */
917typedef PDMIOAPIC const *PCPDMIOAPIC;
918
919/** Maximum number of PCI busses for a VM. */
920#define PDM_PCI_BUSSES_MAX 8
921/** Maximum number of IOMMUs (at most one per PCI bus). */
922#define PDM_IOMMUS_MAX PDM_PCI_BUSSES_MAX
923
924
925#ifdef IN_RING3
926/**
927 * PDM registered firmware device.
928 */
929typedef struct PDMFW
930{
931 /** Pointer to the firmware device instance. */
932 PPDMDEVINSR3 pDevIns;
933 /** Copy of the registration structure. */
934 PDMFWREG Reg;
935} PDMFW;
936/** Pointer to a firmware instance. */
937typedef PDMFW *PPDMFW;
938#endif
939
940
941/**
942 * PDM PCI bus instance.
943 */
944typedef struct PDMPCIBUS
945{
946 /** PCI bus number. */
947 uint32_t iBus;
948 uint32_t uPadding0; /**< Alignment padding.*/
949
950 /** Pointer to PCI bus device instance. */
951 PPDMDEVINSR3 pDevInsR3;
952 /** @copydoc PDMPCIBUSREGR3::pfnSetIrqR3 */
953 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
954
955 /** @copydoc PDMPCIBUSREGR3::pfnRegisterR3 */
956 DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
957 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
958 /** @copydoc PDMPCIBUSREGR3::pfnRegisterMsiR3 */
959 DECLR3CALLBACKMEMBER(int, pfnRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
960 /** @copydoc PDMPCIBUSREGR3::pfnIORegionRegisterR3 */
961 DECLR3CALLBACKMEMBER(int, pfnIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
962 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
963 uint64_t hHandle, PFNPCIIOREGIONMAP pfnCallback));
964 /** @copydoc PDMPCIBUSREGR3::pfnInterceptConfigAccesses */
965 DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
966 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
967 /** @copydoc PDMPCIBUSREGR3::pfnConfigWrite */
968 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
969 uint32_t uAddress, unsigned cb, uint32_t u32Value));
970 /** @copydoc PDMPCIBUSREGR3::pfnConfigRead */
971 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
972 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
973} PDMPCIBUS;
974/** Pointer to a PDM PCI Bus instance. */
975typedef PDMPCIBUS *PPDMPCIBUS;
976/** Pointer to a const PDM PCI Bus instance. */
977typedef const PDMPCIBUS *PCPDMPCIBUS;
978
979
980/**
981 * Ring-0 PDM PCI bus instance data.
982 */
983typedef struct PDMPCIBUSR0
984{
985 /** PCI bus number. */
986 uint32_t iBus;
987 uint32_t uPadding0; /**< Alignment padding.*/
988 /** Pointer to PCI bus device instance. */
989 PPDMDEVINSR0 pDevInsR0;
990 /** @copydoc PDMPCIBUSREGR0::pfnSetIrq */
991 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
992} PDMPCIBUSR0;
993/** Pointer to the ring-0 PCI bus data. */
994typedef PDMPCIBUSR0 *PPDMPCIBUSR0;
995/** Pointer to the const ring-0 PCI bus data. */
996typedef const PDMPCIBUSR0 *PCPDMPCIBUSR0;
997
998
999#ifdef IN_RING3
1000/**
1001 * PDM registered DMAC (DMA Controller) device.
1002 */
1003typedef struct PDMDMAC
1004{
1005 /** Pointer to the DMAC device instance. */
1006 PPDMDEVINSR3 pDevIns;
1007 /** Copy of the registration structure. */
1008 PDMDMACREG Reg;
1009} PDMDMAC;
1010
1011
1012/**
1013 * PDM registered RTC (Real Time Clock) device.
1014 */
1015typedef struct PDMRTC
1016{
1017 /** Pointer to the RTC device instance. */
1018 PPDMDEVINSR3 pDevIns;
1019 /** Copy of the registration structure. */
1020 PDMRTCREG Reg;
1021} PDMRTC;
1022
1023#endif /* IN_RING3 */
1024
1025/**
1026 * Module type.
1027 */
1028typedef enum PDMMODTYPE
1029{
1030 /** Raw-mode (RC) context module. */
1031 PDMMOD_TYPE_RC,
1032 /** Ring-0 (host) context module. */
1033 PDMMOD_TYPE_R0,
1034 /** Ring-3 (host) context module. */
1035 PDMMOD_TYPE_R3
1036} PDMMODTYPE;
1037
1038
1039/** The module name length including the terminator. */
1040#define PDMMOD_NAME_LEN 32
1041
1042/**
1043 * Loaded module instance.
1044 */
1045typedef struct PDMMOD
1046{
1047 /** Module name. This is used for referring to
1048 * the module internally, sort of like a handle. */
1049 char szName[PDMMOD_NAME_LEN];
1050 /** Module type. */
1051 PDMMODTYPE eType;
1052 /** Loader module handle. Not used for R0 modules. */
1053 RTLDRMOD hLdrMod;
1054 /** Loaded address.
1055 * This is the 'handle' for R0 modules. */
1056 RTUINTPTR ImageBase;
1057 /** Old loaded address.
1058 * This is used during relocation of GC modules. Not used for R0 modules. */
1059 RTUINTPTR OldImageBase;
1060 /** Where the R3 HC bits are stored.
1061 * This can be equal to ImageBase but doesn't have to. Not used for R0 modules. */
1062 void *pvBits;
1063
1064 /** Pointer to next module. */
1065 struct PDMMOD *pNext;
1066 /** Module filename. */
1067 char szFilename[1];
1068} PDMMOD;
1069/** Pointer to loaded module instance. */
1070typedef PDMMOD *PPDMMOD;
1071
1072
1073
1074/** Max number of items in a queue. */
1075#define PDMQUEUE_MAX_ITEMS _16K
1076/** Max item size. */
1077#define PDMQUEUE_MAX_ITEM_SIZE _1M
1078/** Max total queue item size for ring-0 capable queues. */
1079#define PDMQUEUE_MAX_TOTAL_SIZE_R0 _8M
1080/** Max total queue item size for ring-3 only queues. */
1081#define PDMQUEUE_MAX_TOTAL_SIZE_R3 _32M
1082
1083/**
1084 * Queue type.
1085 */
1086typedef enum PDMQUEUETYPE
1087{
1088 /** Device consumer. */
1089 PDMQUEUETYPE_DEV = 1,
1090 /** Driver consumer. */
1091 PDMQUEUETYPE_DRV,
1092 /** Internal consumer. */
1093 PDMQUEUETYPE_INTERNAL,
1094 /** External consumer. */
1095 PDMQUEUETYPE_EXTERNAL
1096} PDMQUEUETYPE;
1097
1098/**
1099 * PDM Queue.
1100 */
1101typedef struct PDMQUEUE
1102{
1103 /** Magic value (PDMQUEUE_MAGIC). */
1104 uint32_t u32Magic;
1105 /** Item size (bytes). */
1106 uint32_t cbItem;
1107 /** Number of items in the queue. */
1108 uint32_t cItems;
1109 /** Offset of the the queue items relative to the PDMQUEUE structure. */
1110 uint32_t offItems;
1111
1112 /** Interval timer. Only used if cMilliesInterval is non-zero. */
1113 TMTIMERHANDLE hTimer;
1114 /** The interval between checking the queue for events.
1115 * The realtime timer below is used to do the waiting.
1116 * If 0, the queue will use the VM_FF_PDM_QUEUE forced action. */
1117 uint32_t cMilliesInterval;
1118
1119 /** This is VINF_SUCCESS if the queue is okay, error status if not. */
1120 int32_t rcOkay;
1121 uint32_t u32Padding;
1122
1123 /** Queue type. */
1124 PDMQUEUETYPE enmType;
1125 /** Type specific data. */
1126 union
1127 {
1128 /** PDMQUEUETYPE_DEV */
1129 struct
1130 {
1131 /** Pointer to consumer function. */
1132 R3PTRTYPE(PFNPDMQUEUEDEV) pfnCallback;
1133 /** Pointer to the device instance owning the queue. */
1134 R3PTRTYPE(PPDMDEVINS) pDevIns;
1135 } Dev;
1136 /** PDMQUEUETYPE_DRV */
1137 struct
1138 {
1139 /** Pointer to consumer function. */
1140 R3PTRTYPE(PFNPDMQUEUEDRV) pfnCallback;
1141 /** Pointer to the driver instance owning the queue. */
1142 R3PTRTYPE(PPDMDRVINS) pDrvIns;
1143 } Drv;
1144 /** PDMQUEUETYPE_INTERNAL */
1145 struct
1146 {
1147 /** Pointer to consumer function. */
1148 R3PTRTYPE(PFNPDMQUEUEINT) pfnCallback;
1149 } Int;
1150 /** PDMQUEUETYPE_EXTERNAL */
1151 struct
1152 {
1153 /** Pointer to consumer function. */
1154 R3PTRTYPE(PFNPDMQUEUEEXT) pfnCallback;
1155 /** Pointer to user argument. */
1156 R3PTRTYPE(void *) pvUser;
1157 } Ext;
1158 struct
1159 {
1160 /** Generic callback pointer. */
1161 RTR3PTR pfnCallback;
1162 /** Generic owner pointer. */
1163 RTR3PTR pvOwner;
1164 } Gen;
1165 } u;
1166
1167 /** Unique queue name. */
1168 char szName[40];
1169
1170 /** LIFO of pending items (item index), UINT32_MAX if empty. */
1171 uint32_t volatile iPending;
1172
1173 /** State: Pending items. */
1174 uint32_t volatile cStatPending;
1175 /** Stat: Times PDMQueueAlloc fails. */
1176 STAMCOUNTER StatAllocFailures;
1177 /** Stat: PDMQueueInsert calls. */
1178 STAMCOUNTER StatInsert;
1179 /** Stat: Queue flushes. */
1180 STAMCOUNTER StatFlush;
1181 /** Stat: Queue flushes with pending items left over. */
1182 STAMCOUNTER StatFlushLeftovers;
1183 /** State: Profiling the flushing. */
1184 STAMPROFILE StatFlushPrf;
1185 uint64_t au64Padding[3];
1186
1187 /** Allocation bitmap: Set bits means free, clear means allocated. */
1188 RT_FLEXIBLE_ARRAY_EXTENSION
1189 uint64_t bmAlloc[RT_FLEXIBLE_ARRAY];
1190 /* The items follows after the end of the bitmap */
1191} PDMQUEUE;
1192AssertCompileMemberAlignment(PDMQUEUE, bmAlloc, 64);
1193/** Pointer to a PDM Queue. */
1194typedef struct PDMQUEUE *PPDMQUEUE;
1195
1196/** Magic value PDMQUEUE::u32Magic (Bud Powell). */
1197#define PDMQUEUE_MAGIC UINT32_C(0x19240927)
1198/** Magic value PDMQUEUE::u32Magic after destroy. */
1199#define PDMQUEUE_MAGIC_DEAD UINT32_C(0x19660731)
1200
1201/** @name PDM::fQueueFlushing
1202 * @{ */
1203/** Used to make sure only one EMT will flush the queues.
1204 * Set when an EMT is flushing queues, clear otherwise. */
1205#define PDM_QUEUE_FLUSH_FLAG_ACTIVE_BIT 0
1206/** Indicating there are queues with items pending.
1207 * This is make sure we don't miss inserts happening during flushing. The FF
1208 * cannot be used for this since it has to be cleared immediately to prevent
1209 * other EMTs from spinning. */
1210#define PDM_QUEUE_FLUSH_FLAG_PENDING_BIT 1
1211/** @} */
1212
1213/**
1214 * Ring-0 queue
1215 *
1216 * @author bird (2022-02-04)
1217 */
1218typedef struct PDMQUEUER0
1219{
1220 /** Pointer to the shared queue data. */
1221 R0PTRTYPE(PPDMQUEUE) pQueue;
1222 /** The memory allocation. */
1223 RTR0MEMOBJ hMemObj;
1224 /** The ring-3 mapping object. */
1225 RTR0MEMOBJ hMapObj;
1226 /** The owner pointer. This is NULL if not allocated. */
1227 RTR0PTR pvOwner;
1228 /** Queue item size. */
1229 uint32_t cbItem;
1230 /** Number of queue items. */
1231 uint32_t cItems;
1232 /** Offset of the the queue items relative to the PDMQUEUE structure. */
1233 uint32_t offItems;
1234 uint32_t u32Reserved;
1235} PDMQUEUER0;
1236
1237
1238/** @name PDM task structures.
1239 * @{ */
1240
1241/**
1242 * A asynchronous user mode task.
1243 */
1244typedef struct PDMTASK
1245{
1246 /** Task owner type. */
1247 PDMTASKTYPE volatile enmType;
1248 /** Queue flags. */
1249 uint32_t volatile fFlags;
1250 /** User argument for the callback. */
1251 R3PTRTYPE(void *) volatile pvUser;
1252 /** The callback (will be cast according to enmType before callout). */
1253 R3PTRTYPE(PFNRT) volatile pfnCallback;
1254 /** The owner identifier. */
1255 R3PTRTYPE(void *) volatile pvOwner;
1256 /** Task name. */
1257 R3PTRTYPE(const char *) pszName;
1258 /** Number of times already triggered when PDMTaskTrigger was called. */
1259 uint32_t volatile cAlreadyTrigged;
1260 /** Number of runs. */
1261 uint32_t cRuns;
1262} PDMTASK;
1263/** Pointer to a PDM task. */
1264typedef PDMTASK *PPDMTASK;
1265
1266/**
1267 * A task set.
1268 *
1269 * This is served by one task executor thread.
1270 */
1271typedef struct PDMTASKSET
1272{
1273 /** Magic value (PDMTASKSET_MAGIC). */
1274 uint32_t u32Magic;
1275 /** Set if this task set works for ring-0 and raw-mode. */
1276 bool fRZEnabled;
1277 /** Number of allocated taks. */
1278 uint8_t volatile cAllocated;
1279 /** Base handle value for this set. */
1280 uint16_t uHandleBase;
1281 /** The task executor thread. */
1282 R3PTRTYPE(RTTHREAD) hThread;
1283 /** Event semaphore for waking up the thread when fRZEnabled is set. */
1284 SUPSEMEVENT hEventR0;
1285 /** Event semaphore for waking up the thread when fRZEnabled is clear. */
1286 R3PTRTYPE(RTSEMEVENT) hEventR3;
1287 /** The VM pointer. */
1288 PVM pVM;
1289 /** Padding so fTriggered is in its own cacheline. */
1290 uint64_t au64Padding2[3];
1291
1292 /** Bitmask of triggered tasks. */
1293 uint64_t volatile fTriggered;
1294 /** Shutdown thread indicator. */
1295 bool volatile fShutdown;
1296 /** Padding. */
1297 bool volatile afPadding3[3];
1298 /** Task currently running, UINT32_MAX if idle. */
1299 uint32_t volatile idxRunning;
1300 /** Padding so fTriggered and fShutdown are in their own cacheline. */
1301 uint64_t volatile au64Padding3[6];
1302
1303 /** The individual tasks. (Unallocated tasks have NULL pvOwner.) */
1304 PDMTASK aTasks[64];
1305} PDMTASKSET;
1306AssertCompileMemberAlignment(PDMTASKSET, fTriggered, 64);
1307AssertCompileMemberAlignment(PDMTASKSET, aTasks, 64);
1308/** Magic value for PDMTASKSET::u32Magic (Quincy Delight Jones Jr.). */
1309#define PDMTASKSET_MAGIC UINT32_C(0x19330314)
1310/** Pointer to a task set. */
1311typedef PDMTASKSET *PPDMTASKSET;
1312
1313/** @} */
1314
1315
1316/** @name PDM Network Shaper
1317 * @{ */
1318
1319/**
1320 * Bandwidth group.
1321 */
1322typedef struct PDMNSBWGROUP
1323{
1324 /** Critical section protecting all members below. */
1325 PDMCRITSECT Lock;
1326 /** List of filters in this group (PDMNSFILTER). */
1327 RTLISTANCHORR3 FilterList;
1328 /** Reference counter - How many filters are associated with this group. */
1329 volatile uint32_t cRefs;
1330 uint32_t uPadding1;
1331 /** The group name. */
1332 char szName[PDM_NET_SHAPER_MAX_NAME_LEN + 1];
1333 /** Maximum number of bytes filters are allowed to transfer. */
1334 volatile uint64_t cbPerSecMax;
1335 /** Number of bytes we are allowed to transfer in one burst. */
1336 volatile uint32_t cbBucket;
1337 /** Number of bytes we were allowed to transfer at the last update. */
1338 volatile uint32_t cbTokensLast;
1339 /** Timestamp of the last update */
1340 volatile uint64_t tsUpdatedLast;
1341 /** Number of times a filter was choked. */
1342 volatile uint64_t cTotalChokings;
1343 /** Pad the structure to a multiple of 64 bytes. */
1344 uint64_t au64Padding[1];
1345} PDMNSBWGROUP;
1346AssertCompileSizeAlignment(PDMNSBWGROUP, 64);
1347/** Pointer to a bandwidth group. */
1348typedef PDMNSBWGROUP *PPDMNSBWGROUP;
1349
1350/** @} */
1351
1352
1353/**
1354 * Queue device helper task operation.
1355 */
1356typedef enum PDMDEVHLPTASKOP
1357{
1358 /** The usual invalid 0 entry. */
1359 PDMDEVHLPTASKOP_INVALID = 0,
1360 /** IsaSetIrq, IoApicSetIrq */
1361 PDMDEVHLPTASKOP_ISA_SET_IRQ,
1362 /** PciSetIrq */
1363 PDMDEVHLPTASKOP_PCI_SET_IRQ,
1364 /** PciSetIrq */
1365 PDMDEVHLPTASKOP_IOAPIC_SET_IRQ,
1366 /** IoApicSendMsi */
1367 PDMDEVHLPTASKOP_IOAPIC_SEND_MSI,
1368 /** IoApicSettEoi */
1369 PDMDEVHLPTASKOP_IOAPIC_SET_EOI,
1370 /** The usual 32-bit hack. */
1371 PDMDEVHLPTASKOP_32BIT_HACK = 0x7fffffff
1372} PDMDEVHLPTASKOP;
1373
1374/**
1375 * Queued Device Helper Task.
1376 */
1377typedef struct PDMDEVHLPTASK
1378{
1379 /** The queue item core (don't touch). */
1380 PDMQUEUEITEMCORE Core;
1381 /** Pointer to the device instance (R3 Ptr). */
1382 PPDMDEVINSR3 pDevInsR3;
1383 /** This operation to perform. */
1384 PDMDEVHLPTASKOP enmOp;
1385#if HC_ARCH_BITS == 64
1386 uint32_t Alignment0;
1387#endif
1388 /** Parameters to the operation. */
1389 union PDMDEVHLPTASKPARAMS
1390 {
1391 /**
1392 * PDMDEVHLPTASKOP_ISA_SET_IRQ and PDMDEVHLPTASKOP_IOAPIC_SET_IRQ.
1393 */
1394 struct PDMDEVHLPTASKISASETIRQ
1395 {
1396 /** The bus:device:function of the device initiating the IRQ. Can be NIL_PCIBDF. */
1397 PCIBDF uBusDevFn;
1398 /** The IRQ */
1399 int iIrq;
1400 /** The new level. */
1401 int iLevel;
1402 /** The IRQ tag and source. */
1403 uint32_t uTagSrc;
1404 } IsaSetIrq, IoApicSetIrq;
1405
1406 /**
1407 * PDMDEVHLPTASKOP_PCI_SET_IRQ
1408 */
1409 struct PDMDEVHLPTASKPCISETIRQ
1410 {
1411 /** Index of the PCI device (into PDMDEVINSR3::apPciDevs). */
1412 uint32_t idxPciDev;
1413 /** The IRQ */
1414 int32_t iIrq;
1415 /** The new level. */
1416 int32_t iLevel;
1417 /** The IRQ tag and source. */
1418 uint32_t uTagSrc;
1419 } PciSetIrq;
1420
1421 /**
1422 * PDMDEVHLPTASKOP_IOAPIC_SEND_MSI
1423 */
1424 struct PDMDEVHLPTASKIOAPICSENDMSI
1425 {
1426 /** The bus:device:function of the device sending the MSI. */
1427 PCIBDF uBusDevFn;
1428 /** The MSI. */
1429 MSIMSG Msi;
1430 /** The IRQ tag and source. */
1431 uint32_t uTagSrc;
1432 } IoApicSendMsi;
1433
1434 /**
1435 * PDMDEVHLPTASKOP_IOAPIC_SET_EOI
1436 */
1437 struct PDMDEVHLPTASKIOAPICSETEOI
1438 {
1439 /** The vector corresponding to the EOI. */
1440 uint8_t uVector;
1441 } IoApicSetEoi;
1442
1443 /** Expanding the structure. */
1444 uint64_t au64[3];
1445 } u;
1446} PDMDEVHLPTASK;
1447/** Pointer to a queued Device Helper Task. */
1448typedef PDMDEVHLPTASK *PPDMDEVHLPTASK;
1449/** Pointer to a const queued Device Helper Task. */
1450typedef const PDMDEVHLPTASK *PCPDMDEVHLPTASK;
1451
1452
1453
1454/**
1455 * An USB hub registration record.
1456 */
1457typedef struct PDMUSBHUB
1458{
1459 /** The USB versions this hub support.
1460 * Note that 1.1 hubs can take on 2.0 devices. */
1461 uint32_t fVersions;
1462 /** The number of ports on the hub. */
1463 uint32_t cPorts;
1464 /** The number of available ports (0..cPorts). */
1465 uint32_t cAvailablePorts;
1466 /** The driver instance of the hub. */
1467 PPDMDRVINS pDrvIns;
1468 /** Copy of the to the registration structure. */
1469 PDMUSBHUBREG Reg;
1470
1471 /** Pointer to the next hub in the list. */
1472 struct PDMUSBHUB *pNext;
1473} PDMUSBHUB;
1474
1475/** Pointer to a const USB HUB registration record. */
1476typedef const PDMUSBHUB *PCPDMUSBHUB;
1477
1478/** Pointer to a PDM Async I/O template. */
1479typedef struct PDMASYNCCOMPLETIONTEMPLATE *PPDMASYNCCOMPLETIONTEMPLATE;
1480
1481/** Pointer to the main PDM Async completion endpoint class. */
1482typedef struct PDMASYNCCOMPLETIONEPCLASS *PPDMASYNCCOMPLETIONEPCLASS;
1483
1484/** Pointer to the global block cache structure. */
1485typedef struct PDMBLKCACHEGLOBAL *PPDMBLKCACHEGLOBAL;
1486
1487/**
1488 * PDM VMCPU Instance data.
1489 * Changes to this must checked against the padding of the pdm union in VMCPU!
1490 */
1491typedef struct PDMCPU
1492{
1493 /** The number of entries in the apQueuedCritSectsLeaves table that's currently
1494 * in use. */
1495 uint32_t cQueuedCritSectLeaves;
1496 uint32_t uPadding0; /**< Alignment padding.*/
1497 /** Critical sections queued in RC/R0 because of contention preventing leave to
1498 * complete. (R3 Ptrs)
1499 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1500 R3PTRTYPE(PPDMCRITSECT) apQueuedCritSectLeaves[8];
1501
1502 /** The number of entries in the apQueuedCritSectRwExclLeaves table that's
1503 * currently in use. */
1504 uint32_t cQueuedCritSectRwExclLeaves;
1505 uint32_t uPadding1; /**< Alignment padding.*/
1506 /** Read/write critical sections queued in RC/R0 because of contention
1507 * preventing exclusive leave to complete. (R3 Ptrs)
1508 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1509 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwExclLeaves[8];
1510
1511 /** The number of entries in the apQueuedCritSectsRwShrdLeaves table that's
1512 * currently in use. */
1513 uint32_t cQueuedCritSectRwShrdLeaves;
1514 uint32_t uPadding2; /**< Alignment padding.*/
1515 /** Read/write critical sections queued in RC/R0 because of contention
1516 * preventing shared leave to complete. (R3 Ptrs)
1517 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1518 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwShrdLeaves[8];
1519} PDMCPU;
1520
1521
1522/** Max number of ring-0 device instances. */
1523#define PDM_MAX_RING0_DEVICE_INSTANCES 190
1524
1525
1526/**
1527 * PDM VM Instance data.
1528 * Changes to this must checked against the padding of the cfgm union in VM!
1529 */
1530typedef struct PDM
1531{
1532 /** The PDM lock.
1533 * This is used to protect everything that deals with interrupts, i.e.
1534 * the PIC, APIC, IOAPIC and PCI devices plus some PDM functions. */
1535 PDMCRITSECT CritSect;
1536 /** The NOP critical section.
1537 * This is a dummy critical section that will not do any thread
1538 * serialization but instead let all threads enter immediately and
1539 * concurrently. */
1540 PDMCRITSECT NopCritSect;
1541 /** Critical read/write section protecting the core list: devices,
1542 * usb devices, drivers.
1543 * @note The PDMUSERPERVM::ListCritSect lock covers queues and the stuff in
1544 * PDMUSERPERVM. */
1545 RTCRITSECTRW CoreListCritSectRw;
1546
1547 /** The ring-0 capable task sets (max 128). */
1548 PDMTASKSET aTaskSets[2];
1549 /** Pointer to task sets (max 512). */
1550 R3PTRTYPE(PPDMTASKSET) apTaskSets[8];
1551
1552 /** PCI Buses. */
1553 PDMPCIBUS aPciBuses[PDM_PCI_BUSSES_MAX];
1554 /** IOMMU devices. */
1555 PDMIOMMUR3 aIommus[PDM_IOMMUS_MAX];
1556 /** The register PIC device. */
1557 PDMPIC Pic;
1558 /** The registered IC device. */
1559 PDMICR3 Ic;
1560 /** The registered I/O APIC device. */
1561 PDMIOAPIC IoApic;
1562 /** The registered HPET device. */
1563 PPDMDEVINSR3 pHpet;
1564
1565 /** List of registered devices. (FIFO) */
1566 R3PTRTYPE(PPDMDEV) pDevs;
1567 /** List of devices instances. (FIFO) */
1568 PPDMDEVINSR3 pDevInstances;
1569 /** This runs parallel to PDMR0PERVM::apDevInstances and is used with
1570 * physical access handlers to get the ring-3 device instance for passing down
1571 * as uUser. */
1572 PPDMDEVINSR3 apDevRing0Instances[PDM_MAX_RING0_DEVICE_INSTANCES];
1573
1574 /** List of registered USB devices. (FIFO) */
1575 R3PTRTYPE(PPDMUSB) pUsbDevs;
1576 /** List of USB devices instances. (FIFO) */
1577 R3PTRTYPE(PPDMUSBINS) pUsbInstances;
1578 /** List of registered drivers. (FIFO) */
1579 R3PTRTYPE(PPDMDRV) pDrvs;
1580 /** The registered firmware device (can be NULL). */
1581 R3PTRTYPE(PPDMFW) pFirmware;
1582 /** The registered DMAC device. */
1583 R3PTRTYPE(PPDMDMAC) pDmac;
1584 /** The registered RTC device. */
1585 R3PTRTYPE(PPDMRTC) pRtc;
1586 /** The registered USB HUBs. (FIFO)
1587 * @note Protected by CoreListCritSectRw. */
1588 R3PTRTYPE(PPDMUSBHUB) pUsbHubs;
1589
1590 /** @name Queues
1591 * @note Protected by PDMUSERPERVM::ListCritSect.
1592 * @{ */
1593 /** Number of ring-0 capable queues in apQueues. */
1594 uint32_t cRing0Queues;
1595 uint32_t u32Padding1;
1596 /** Array of ring-0 capable queues running in parallel to PDMR0PERVM::aQueues. */
1597 R3PTRTYPE(PPDMQUEUE) apRing0Queues[16];
1598
1599 /** Number of ring-3 only queues.
1600 * PDMUSERPERVM::ListCritSect protects this and the next two members. */
1601 uint32_t cRing3Queues;
1602 /** The allocation size of the ring-3 queue handle table. */
1603 uint32_t cRing3QueuesAlloc;
1604 /** Handle table for the ring-3 only queues. */
1605 R3PTRTYPE(PPDMQUEUE *) papRing3Queues;
1606
1607 /** Queue in which devhlp tasks are queued for R3 execution. */
1608 PDMQUEUEHANDLE hDevHlpQueue;
1609 /** Bitmask controlling the queue flushing.
1610 * See PDM_QUEUE_FLUSH_FLAG_ACTIVE and PDM_QUEUE_FLUSH_FLAG_PENDING. */
1611 uint32_t volatile fQueueFlushing;
1612 /** @} */
1613
1614 /** The current IRQ tag (tracing purposes). */
1615 uint32_t volatile uIrqTag;
1616
1617 /** Pending reset flags (PDMVMRESET_F_XXX). */
1618 uint32_t volatile fResetFlags;
1619
1620 /** Set by pdmR3LoadExec for use in assertions. */
1621 bool fStateLoaded;
1622 /** Alignment padding. */
1623 bool afPadding1[3];
1624
1625 /** The tracing ID of the next device instance.
1626 *
1627 * @remarks We keep the device tracing ID seperate from the rest as these are
1628 * then more likely to end up with the same ID from one run to
1629 * another, making analysis somewhat easier. Drivers and USB devices
1630 * are more volatile and can be changed at runtime, thus these are much
1631 * less likely to remain stable, so just heap them all together. */
1632 uint32_t idTracingDev;
1633 /** The tracing ID of the next driver instance, USB device instance or other
1634 * PDM entity requiring an ID. */
1635 uint32_t idTracingOther;
1636
1637 /** @name VMM device heap
1638 * @{ */
1639 /** The heap size. */
1640 uint32_t cbVMMDevHeap;
1641 /** Free space. */
1642 uint32_t cbVMMDevHeapLeft;
1643 /** Pointer to the heap base (MMIO2 ring-3 mapping). NULL if not registered. */
1644 RTR3PTR pvVMMDevHeap;
1645 /** Ring-3 mapping/unmapping notification callback for the user. */
1646 PFNPDMVMMDEVHEAPNOTIFY pfnVMMDevHeapNotify;
1647 /** The current mapping. NIL_RTGCPHYS if not mapped or registered. */
1648 RTGCPHYS GCPhysVMMDevHeap;
1649 /** @} */
1650
1651 /** @name Network Shaper
1652 * @{ */
1653 /** Thread that processes choked filter drivers after
1654 * the a PDM_NETSHAPER_MAX_LATENCY period has elapsed. */
1655 PPDMTHREAD pNsUnchokeThread;
1656 /** Semaphore that the TX thread waits on. */
1657 RTSEMEVENT hNsUnchokeEvt;
1658 /** Timer handle for waking up pNsUnchokeThread. */
1659 TMTIMERHANDLE hNsUnchokeTimer;
1660 /** Indicates whether the unchoke timer has been armed already or not. */
1661 bool volatile fNsUnchokeTimerArmed;
1662 /** Align aNsGroups on a cacheline. */
1663 bool afPadding2[19+16+17];
1664 /** Number of network shaper groups.
1665 * @note Marked volatile to prevent re-reading after validation. */
1666 uint32_t volatile cNsGroups;
1667 /** The network shaper groups. */
1668 PDMNSBWGROUP aNsGroups[PDM_NET_SHAPER_MAX_GROUPS];
1669 /** Critical section protecting attaching, detaching and unchoking.
1670 * This helps making sure pNsTxThread can do unchoking w/o needing to lock the
1671 * individual groups and cause unnecessary contention. */
1672 RTCRITSECT NsLock;
1673 /** @} */
1674
1675 /** Number of times a critical section leave request needed to be queued for ring-3 execution. */
1676 STAMCOUNTER StatQueuedCritSectLeaves;
1677 /** Number of times we've successfully aborted a wait in ring-0. */
1678 STAMCOUNTER StatAbortedCritSectEnters;
1679 /** Number of times we've got the critical section ownership while trying to
1680 * abort a wait due to VERR_INTERRUPTED. */
1681 STAMCOUNTER StatCritSectEntersWhileAborting;
1682 STAMCOUNTER StatCritSectVerrTimeout;
1683 STAMCOUNTER StatCritSectVerrInterrupted;
1684 STAMCOUNTER StatCritSectNonInterruptibleWaits;
1685
1686 STAMCOUNTER StatCritSectRwExclVerrTimeout;
1687 STAMCOUNTER StatCritSectRwExclVerrInterrupted;
1688 STAMCOUNTER StatCritSectRwExclNonInterruptibleWaits;
1689
1690 STAMCOUNTER StatCritSectRwEnterSharedWhileAborting;
1691 STAMCOUNTER StatCritSectRwSharedVerrTimeout;
1692 STAMCOUNTER StatCritSectRwSharedVerrInterrupted;
1693 STAMCOUNTER StatCritSectRwSharedNonInterruptibleWaits;
1694} PDM;
1695AssertCompileMemberAlignment(PDM, CritSect, 8);
1696AssertCompileMemberAlignment(PDM, aTaskSets, 64);
1697AssertCompileMemberAlignment(PDM, aNsGroups, 8);
1698AssertCompileMemberAlignment(PDM, aNsGroups, 16);
1699AssertCompileMemberAlignment(PDM, aNsGroups, 32);
1700AssertCompileMemberAlignment(PDM, aNsGroups, 64);
1701AssertCompileMemberAlignment(PDM, StatQueuedCritSectLeaves, 8);
1702AssertCompileMemberAlignment(PDM, GCPhysVMMDevHeap, sizeof(RTGCPHYS));
1703/** Pointer to PDM VM instance data. */
1704typedef PDM *PPDM;
1705
1706
1707/**
1708 * PDM data kept in the ring-0 GVM.
1709 */
1710typedef struct PDMR0PERVM
1711{
1712 /** PCI Buses, ring-0 data. */
1713 PDMPCIBUSR0 aPciBuses[PDM_PCI_BUSSES_MAX];
1714 /** IOMMUs, ring-0 data. */
1715 PDMIOMMUR0 aIommus[PDM_IOMMUS_MAX];
1716 /** Number of valid ring-0 device instances (apDevInstances). */
1717 uint32_t cDevInstances;
1718 uint32_t u32Padding1;
1719 /** Pointer to ring-0 device instances. */
1720 R0PTRTYPE(struct PDMDEVINSR0 *) apDevInstances[PDM_MAX_RING0_DEVICE_INSTANCES];
1721 /** Number of valid ring-0 queue instances (aQueues). */
1722 uint32_t cQueues;
1723 uint32_t u32Padding2;
1724 /** Array of ring-0 queues. */
1725 PDMQUEUER0 aQueues[16];
1726 /** The interrupt-controller, ring-0 data. */
1727 PDMICR0 Ic;
1728} PDMR0PERVM;
1729
1730
1731/**
1732 * PDM data kept in the UVM.
1733 */
1734typedef struct PDMUSERPERVM
1735{
1736 /** @todo move more stuff over here. */
1737
1738 /** Lock protecting the lists below it and the queue list (in PDM). */
1739 RTCRITSECT ListCritSect;
1740 /** Pointer to list of loaded modules. */
1741 PPDMMOD pModules;
1742 /** List of initialized critical sections. (LIFO) */
1743 R3PTRTYPE(PPDMCRITSECTINT) pCritSects;
1744 /** List of initialized read/write critical sections. (LIFO) */
1745 R3PTRTYPE(PPDMCRITSECTRWINT) pRwCritSects;
1746 /** Head of the PDM Thread list. (singly linked) */
1747 R3PTRTYPE(PPDMTHREAD) pThreads;
1748 /** Tail of the PDM Thread list. (singly linked) */
1749 R3PTRTYPE(PPDMTHREAD) pThreadsTail;
1750
1751 /** @name PDM Async Completion
1752 * @{ */
1753 /** Pointer to the array of supported endpoint classes. */
1754 PPDMASYNCCOMPLETIONEPCLASS apAsyncCompletionEndpointClass[PDMASYNCCOMPLETIONEPCLASSTYPE_MAX];
1755 /** Head of the templates. Singly linked, protected by ListCritSect. */
1756 R3PTRTYPE(PPDMASYNCCOMPLETIONTEMPLATE) pAsyncCompletionTemplates;
1757 /** @} */
1758
1759 /** Global block cache data. */
1760 R3PTRTYPE(PPDMBLKCACHEGLOBAL) pBlkCacheGlobal;
1761} PDMUSERPERVM;
1762/** Pointer to the PDM data kept in the UVM. */
1763typedef PDMUSERPERVM *PPDMUSERPERVM;
1764
1765
1766
1767/*******************************************************************************
1768* Global Variables *
1769*******************************************************************************/
1770#ifdef IN_RING3
1771extern const PDMDRVHLPR3 g_pdmR3DrvHlp;
1772extern const PDMDEVHLPR3 g_pdmR3DevHlpTrusted;
1773# ifdef VBOX_WITH_DBGF_TRACING
1774extern const PDMDEVHLPR3 g_pdmR3DevHlpTracing;
1775# endif
1776extern const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted;
1777extern const PDMPICHLP g_pdmR3DevPicHlp;
1778extern const PDMIOAPICHLP g_pdmR3DevIoApicHlp;
1779extern const PDMFWHLPR3 g_pdmR3DevFirmwareHlp;
1780extern const PDMPCIHLPR3 g_pdmR3DevPciHlp;
1781extern const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp;
1782extern const PDMDMACHLP g_pdmR3DevDmacHlp;
1783extern const PDMRTCHLP g_pdmR3DevRtcHlp;
1784extern const PDMHPETHLPR3 g_pdmR3DevHpetHlp;
1785extern const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp;
1786#endif
1787
1788
1789/*******************************************************************************
1790* Defined Constants And Macros *
1791*******************************************************************************/
1792/** @def PDMDEV_ASSERT_DEVINS
1793 * Asserts the validity of the device instance.
1794 */
1795#ifdef VBOX_STRICT
1796# define PDMDEV_ASSERT_DEVINS(pDevIns) \
1797 do { \
1798 AssertPtr(pDevIns); \
1799 Assert(pDevIns->u32Version == PDM_DEVINS_VERSION); \
1800 Assert(pDevIns->CTX_SUFF(pvInstanceDataFor) == (void *)&pDevIns->achInstanceData[0]); \
1801 } while (0)
1802#else
1803# define PDMDEV_ASSERT_DEVINS(pDevIns) do { } while (0)
1804#endif
1805
1806/** @def PDMDRV_ASSERT_DRVINS
1807 * Asserts the validity of the driver instance.
1808 */
1809#ifdef VBOX_STRICT
1810# define PDMDRV_ASSERT_DRVINS(pDrvIns) \
1811 do { \
1812 AssertPtr(pDrvIns); \
1813 Assert(pDrvIns->u32Version == PDM_DRVINS_VERSION); \
1814 Assert(pDrvIns->CTX_SUFF(pvInstanceData) == (void *)&pDrvIns->achInstanceData[0]); \
1815 } while (0)
1816#else
1817# define PDMDRV_ASSERT_DRVINS(pDrvIns) do { } while (0)
1818#endif
1819
1820#ifndef VBOX_VMM_TARGET_ARMV8
1821/** @def PDM_TO_APICBACKEND
1822 * Gets the APIC backend given the VM cross-context structure.
1823 */
1824/** @def PDMCPU_TO_APICBACKEND
1825 * Gets the APIC backend given VMCPU cross-context structure.
1826 */
1827# ifdef IN_RING3
1828# define PDM_TO_APICBACKEND(a_pVM) (&((a_pVM)->pdm.s.Ic.u.x86.ApicBackend))
1829# define PDMCPU_TO_APICBACKEND(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->pdm.s.Ic.u.x86.ApicBackend))
1830#else
1831# define PDM_TO_APICBACKEND(a_pVM) (&((a_pVM)->pdmr0.s.Ic.u.x86.ApicBackend))
1832# define PDMCPU_TO_APICBACKEND(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->pdmr0.s.Ic.u.x86.ApicBackend))
1833#endif
1834#else
1835# ifdef IN_RING3
1836# define PDM_TO_GICBACKEND(a_pVM) (&((a_pVM)->pdm.s.Ic.u.armv8.GicBackend))
1837# define PDMCPU_TO_GICBACKEND(a_pVCpu) (&((a_pVCpu)->CTX_SUFF(pVM)->pdm.s.Ic.u.armv8.GicBackend))
1838#else
1839# error "Implement me"
1840#endif
1841#endif
1842
1843/*******************************************************************************
1844* Internal Functions *
1845*******************************************************************************/
1846#ifdef IN_RING3
1847bool pdmR3IsValidName(const char *pszName);
1848
1849int pdmR3CritSectBothInitStatsAndInfo(PVM pVM);
1850int pdmR3CritSectBothDeleteDevice(PVM pVM, PPDMDEVINS pDevIns);
1851int pdmR3CritSectBothDeleteDriver(PVM pVM, PPDMDRVINS pDrvIns);
1852int pdmR3CritSectInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1853 const char *pszNameFmt, va_list va);
1854int pdmR3CritSectInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1855 const char *pszNameFmt, ...);
1856int pdmR3CritSectInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1857 const char *pszNameFmt, ...);
1858int pdmR3CritSectRwInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1859 const char *pszNameFmt, va_list va);
1860int pdmR3CritSectRwInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1861 const char *pszNameFmt, ...);
1862int pdmR3CritSectRwInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1863 const char *pszNameFmt, ...);
1864
1865int pdmR3DevInit(PVM pVM);
1866int pdmR3DevInitComplete(PVM pVM);
1867PPDMDEV pdmR3DevLookup(PVM pVM, const char *pszName);
1868int pdmR3DevFindLun(PVM pVM, const char *pszDevice, unsigned iInstance, unsigned iLun, PPDMLUN *ppLun);
1869DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem);
1870
1871int pdmR3UsbLoadModules(PVM pVM);
1872int pdmR3UsbInstantiateDevices(PVM pVM);
1873PPDMUSB pdmR3UsbLookup(PVM pVM, const char *pszName);
1874int pdmR3UsbRegisterHub(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fVersions, uint32_t cPorts, PCPDMUSBHUBREG pUsbHubReg, PPCPDMUSBHUBHLP ppUsbHubHlp);
1875int pdmR3UsbVMInitComplete(PVM pVM);
1876
1877int pdmR3DrvInit(PVM pVM);
1878int pdmR3DrvInstantiate(PVM pVM, PCFGMNODE pNode, PPDMIBASE pBaseInterface, PPDMDRVINS pDrvAbove,
1879 PPDMLUN pLun, PPDMIBASE *ppBaseInterface);
1880int pdmR3DrvDetach(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fFlags);
1881void pdmR3DrvDestroyChain(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fFlags);
1882PPDMDRV pdmR3DrvLookup(PVM pVM, const char *pszName);
1883
1884int pdmR3LdrInitU(PUVM pUVM);
1885void pdmR3LdrTermU(PUVM pUVM, bool fFinal);
1886char *pdmR3FileR3(const char *pszFile, bool fShared);
1887int pdmR3LoadR3U(PUVM pUVM, const char *pszFilename, const char *pszName);
1888#endif /* IN_RING3 */
1889
1890void pdmQueueInit(PPDMQUEUE pQueue, uint32_t cbBitmap, uint32_t cbItem, uint32_t cItems,
1891 const char *pszName, PDMQUEUETYPE enmType, RTR3PTR pfnCallback, RTR3PTR pvOwner);
1892
1893#ifdef IN_RING3
1894int pdmR3TaskInit(PVM pVM);
1895void pdmR3TaskTerm(PVM pVM);
1896
1897int pdmR3ThreadCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
1898 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1899int pdmR3ThreadCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADUSB pfnThread,
1900 PFNPDMTHREADWAKEUPUSB pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1901int pdmR3ThreadCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDRV pfnThread,
1902 PFNPDMTHREADWAKEUPDRV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1903int pdmR3ThreadDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1904int pdmR3ThreadDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1905int pdmR3ThreadDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1906void pdmR3ThreadDestroyAll(PVM pVM);
1907int pdmR3ThreadResumeAll(PVM pVM);
1908int pdmR3ThreadSuspendAll(PVM pVM);
1909
1910# ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
1911int pdmR3AsyncCompletionInit(PVM pVM);
1912int pdmR3AsyncCompletionTerm(PVM pVM);
1913void pdmR3AsyncCompletionResume(PVM pVM);
1914int pdmR3AsyncCompletionTemplateCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEDEV pfnCompleted, const char *pszDesc);
1915int pdmR3AsyncCompletionTemplateCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate,
1916 PFNPDMASYNCCOMPLETEDRV pfnCompleted, void *pvTemplateUser, const char *pszDesc);
1917int pdmR3AsyncCompletionTemplateCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEUSB pfnCompleted, const char *pszDesc);
1918int pdmR3AsyncCompletionTemplateDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1919int pdmR3AsyncCompletionTemplateDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1920int pdmR3AsyncCompletionTemplateDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1921# endif
1922
1923# ifdef VBOX_WITH_NETSHAPER
1924int pdmR3NetShaperInit(PVM pVM);
1925void pdmR3NetShaperTerm(PVM pVM);
1926# endif
1927
1928int pdmR3BlkCacheInit(PVM pVM);
1929void pdmR3BlkCacheTerm(PVM pVM);
1930int pdmR3BlkCacheResume(PVM pVM);
1931
1932DECLHIDDEN(void) pdmR3QueueTerm(PVM pVM);
1933#endif /* IN_RING3 */
1934
1935void pdmLock(PVMCC pVM);
1936int pdmLockEx(PVMCC pVM, int rcBusy);
1937void pdmUnlock(PVMCC pVM);
1938bool pdmLockIsOwner(PVMCC pVM);
1939
1940#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
1941bool pdmIommuIsPresent(PPDMDEVINS pDevIns);
1942int pdmIommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut);
1943int pdmIommuMemAccessRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1944int pdmIommuMemAccessWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1945# ifdef IN_RING3
1946int pdmR3IommuMemAccessReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock);
1947int pdmR3IommuMemAccessWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock);
1948int pdmR3IommuMemAccessBulkReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, const void **papvPages, PPGMPAGEMAPLOCK paLocks);
1949int pdmR3IommuMemAccessBulkWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks);
1950# endif
1951#endif
1952
1953#if defined(IN_RING3) || defined(IN_RING0)
1954void pdmCritSectRwLeaveSharedQueued(PVMCC pVM, PPDMCRITSECTRW pThis);
1955void pdmCritSectRwLeaveExclQueued(PVMCC pVM, PPDMCRITSECTRW pThis);
1956#endif
1957
1958#ifdef IN_RING0
1959DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc);
1960DECLHIDDEN(void) pdmR0QueueDestroy(PGVM pGVM, uint32_t iQueue);
1961
1962#endif
1963
1964#ifdef VBOX_WITH_DBGF_TRACING
1965# ifdef IN_RING3
1966DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
1967 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1968 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
1969 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts);
1970DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port);
1971DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts);
1972DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
1973 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
1974 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
1975 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion);
1976DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys);
1977DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion);
1978DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1979DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1980DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1981DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1982DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1983DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1984DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1985DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1986# elif defined(IN_RING0)
1987DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
1988 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1989 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
1990 void *pvUser);
1991DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
1992 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser);
1993DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1994DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1995DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1996DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1997DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1998DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1999DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
2000DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
2001# else
2002# error "Invalid environment selected"
2003# endif
2004#endif
2005
2006
2007/** @} */
2008
2009RT_C_DECLS_END
2010
2011#endif /* !VMM_INCLUDED_SRC_include_PDMInternal_h */
2012
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