VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PDMInternal.h@ 84431

Last change on this file since 84431 was 84431, checked in by vboxsync, 5 years ago

AMD IOMMU: bugref:9654 IOMMU interrupt remapping callback skeleton.
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1/* $Id: PDMInternal.h 84431 2020-05-21 08:42:19Z vboxsync $ */
2/** @file
3 * PDM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_PDMInternal_h
19#define VMM_INCLUDED_SRC_include_PDMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/types.h>
25#include <VBox/param.h>
26#include <VBox/vmm/cfgm.h>
27#include <VBox/vmm/stam.h>
28#include <VBox/vusb.h>
29#include <VBox/vmm/pdmasynccompletion.h>
30#ifdef VBOX_WITH_NETSHAPER
31# include <VBox/vmm/pdmnetshaper.h>
32#endif
33#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
34# include <VBox/vmm/pdmasynccompletion.h>
35#endif
36#include <VBox/vmm/pdmblkcache.h>
37#include <VBox/vmm/pdmcommon.h>
38#include <VBox/vmm/pdmtask.h>
39#include <VBox/sup.h>
40#include <iprt/assert.h>
41#include <iprt/critsect.h>
42#ifdef IN_RING3
43# include <iprt/thread.h>
44#endif
45
46RT_C_DECLS_BEGIN
47
48
49/** @defgroup grp_pdm_int Internal
50 * @ingroup grp_pdm
51 * @internal
52 * @{
53 */
54
55/** @def PDM_WITH_R3R0_CRIT_SECT
56 * Enables or disabled ring-3/ring-0 critical sections. */
57#if defined(DOXYGEN_RUNNING) || 1
58# define PDM_WITH_R3R0_CRIT_SECT
59#endif
60
61/** @def PDMCRITSECT_STRICT
62 * Enables/disables PDM critsect strictness like deadlock detection. */
63#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECT_STRICT)) \
64 || defined(DOXYGEN_RUNNING)
65# define PDMCRITSECT_STRICT
66#endif
67
68/** @def PDMCRITSECT_STRICT
69 * Enables/disables PDM read/write critsect strictness like deadlock
70 * detection. */
71#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECTRW_STRICT)) \
72 || defined(DOXYGEN_RUNNING)
73# define PDMCRITSECTRW_STRICT
74#endif
75
76/** The maximum device instance (total) size, ring-0/raw-mode capable devices. */
77#define PDM_MAX_DEVICE_INSTANCE_SIZE _4M
78/** The maximum device instance (total) size, ring-3 only devices. */
79#define PDM_MAX_DEVICE_INSTANCE_SIZE_R3 _8M
80
81
82
83/*******************************************************************************
84* Structures and Typedefs *
85*******************************************************************************/
86
87/** Pointer to a PDM Device. */
88typedef struct PDMDEV *PPDMDEV;
89/** Pointer to a pointer to a PDM Device. */
90typedef PPDMDEV *PPPDMDEV;
91
92/** Pointer to a PDM USB Device. */
93typedef struct PDMUSB *PPDMUSB;
94/** Pointer to a pointer to a PDM USB Device. */
95typedef PPDMUSB *PPPDMUSB;
96
97/** Pointer to a PDM Driver. */
98typedef struct PDMDRV *PPDMDRV;
99/** Pointer to a pointer to a PDM Driver. */
100typedef PPDMDRV *PPPDMDRV;
101
102/** Pointer to a PDM Logical Unit. */
103typedef struct PDMLUN *PPDMLUN;
104/** Pointer to a pointer to a PDM Logical Unit. */
105typedef PPDMLUN *PPPDMLUN;
106
107/** Pointer to a PDM PCI Bus instance. */
108typedef struct PDMPCIBUS *PPDMPCIBUS;
109/** Pointer to a PDM IOMMU instance. */
110typedef struct PDMIOMMU *PPDMIOMMU;
111/** Pointer to a DMAC instance. */
112typedef struct PDMDMAC *PPDMDMAC;
113/** Pointer to a RTC instance. */
114typedef struct PDMRTC *PPDMRTC;
115
116/** Pointer to an USB HUB registration record. */
117typedef struct PDMUSBHUB *PPDMUSBHUB;
118
119/**
120 * Supported asynchronous completion endpoint classes.
121 */
122typedef enum PDMASYNCCOMPLETIONEPCLASSTYPE
123{
124 /** File class. */
125 PDMASYNCCOMPLETIONEPCLASSTYPE_FILE = 0,
126 /** Number of supported classes. */
127 PDMASYNCCOMPLETIONEPCLASSTYPE_MAX,
128 /** 32bit hack. */
129 PDMASYNCCOMPLETIONEPCLASSTYPE_32BIT_HACK = 0x7fffffff
130} PDMASYNCCOMPLETIONEPCLASSTYPE;
131
132/**
133 * Private device instance data, ring-3.
134 */
135typedef struct PDMDEVINSINTR3
136{
137 /** Pointer to the next instance.
138 * (Head is pointed to by PDM::pDevInstances.) */
139 R3PTRTYPE(PPDMDEVINS) pNextR3;
140 /** Pointer to the next per device instance.
141 * (Head is pointed to by PDMDEV::pInstances.) */
142 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
143 /** Pointer to device structure. */
144 R3PTRTYPE(PPDMDEV) pDevR3;
145 /** Pointer to the list of logical units associated with the device. (FIFO) */
146 R3PTRTYPE(PPDMLUN) pLunsR3;
147 /** Pointer to the asynchronous notification callback set while in
148 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
149 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
150 /** Configuration handle to the instance node. */
151 R3PTRTYPE(PCFGMNODE) pCfgHandle;
152
153 /** R3 pointer to the VM this instance was created for. */
154 PVMR3 pVMR3;
155
156 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
157 uint32_t fIntFlags;
158 /** The last IRQ tag (for tracing it thru clearing). */
159 uint32_t uLastIrqTag;
160 /** The ring-0 device index (for making ring-0 calls). */
161 uint32_t idxR0Device;
162} PDMDEVINSINTR3;
163
164
165/**
166 * Private device instance data, ring-0.
167 */
168typedef struct PDMDEVINSINTR0
169{
170 /** Pointer to the VM this instance was created for. */
171 R0PTRTYPE(PGVM) pGVM;
172 /** Pointer to device structure. */
173 R0PTRTYPE(struct PDMDEVREGR0 const *) pRegR0;
174 /** The ring-0 module reference. */
175 RTR0PTR hMod;
176 /** Pointer to the ring-0 mapping of the ring-3 internal data (for uLastIrqTag). */
177 R0PTRTYPE(PDMDEVINSINTR3 *) pIntR3R0;
178 /** Pointer to the ring-0 mapping of the ring-3 instance (for idTracing). */
179 R0PTRTYPE(struct PDMDEVINSR3 *) pInsR3R0;
180 /** The device instance memory. */
181 RTR0MEMOBJ hMemObj;
182 /** The ring-3 mapping object. */
183 RTR0MEMOBJ hMapObj;
184 /** Index into PDMR0PERVM::apDevInstances. */
185 uint32_t idxR0Device;
186} PDMDEVINSINTR0;
187
188
189/**
190 * Private device instance data, raw-mode
191 */
192typedef struct PDMDEVINSINTRC
193{
194 /** Pointer to the VM this instance was created for. */
195 RGPTRTYPE(PVM) pVMRC;
196} PDMDEVINSINTRC;
197
198
199/**
200 * Private device instance data.
201 */
202typedef struct PDMDEVINSINT
203{
204 /** Pointer to the next instance (HC Ptr).
205 * (Head is pointed to by PDM::pDevInstances.) */
206 R3PTRTYPE(PPDMDEVINS) pNextR3;
207 /** Pointer to the next per device instance (HC Ptr).
208 * (Head is pointed to by PDMDEV::pInstances.) */
209 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
210 /** Pointer to device structure - HC Ptr. */
211 R3PTRTYPE(PPDMDEV) pDevR3;
212 /** Pointer to the list of logical units associated with the device. (FIFO) */
213 R3PTRTYPE(PPDMLUN) pLunsR3;
214 /** Pointer to the asynchronous notification callback set while in
215 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
216 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
217 /** Configuration handle to the instance node. */
218 R3PTRTYPE(PCFGMNODE) pCfgHandle;
219
220 /** R3 pointer to the VM this instance was created for. */
221 PVMR3 pVMR3;
222
223 /** R0 pointer to the VM this instance was created for. */
224 R0PTRTYPE(PVMCC) pVMR0;
225
226 /** RC pointer to the VM this instance was created for. */
227 PVMRC pVMRC;
228
229 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
230 uint32_t fIntFlags;
231 /** The last IRQ tag (for tracing it thru clearing). */
232 uint32_t uLastIrqTag;
233} PDMDEVINSINT;
234
235/** @name PDMDEVINSINT::fIntFlags
236 * @{ */
237/** Used by pdmR3Load to mark device instances it found in the saved state. */
238#define PDMDEVINSINT_FLAGS_FOUND RT_BIT_32(0)
239/** Indicates that the device hasn't been powered on or resumed.
240 * This is used by PDMR3PowerOn, PDMR3Resume, PDMR3Suspend and PDMR3PowerOff
241 * to make sure each device gets exactly one notification for each of those
242 * events. PDMR3Resume and PDMR3PowerOn also makes use of it to bail out on
243 * a failure (already resumed/powered-on devices are suspended).
244 * PDMR3PowerOff resets this flag once before going through the devices to make sure
245 * every device gets the power off notification even if it was suspended before with
246 * PDMR3Suspend.
247 */
248#define PDMDEVINSINT_FLAGS_SUSPENDED RT_BIT_32(1)
249/** Indicates that the device has been reset already. Used by PDMR3Reset. */
250#define PDMDEVINSINT_FLAGS_RESET RT_BIT_32(2)
251#define PDMDEVINSINT_FLAGS_R0_ENABLED RT_BIT_32(3)
252#define PDMDEVINSINT_FLAGS_RC_ENABLED RT_BIT_32(4)
253/** Set if we've called the ring-0 constructor. */
254#define PDMDEVINSINT_FLAGS_R0_CONTRUCT RT_BIT_32(5)
255/** Set if using non-default critical section. */
256#define PDMDEVINSINT_FLAGS_CHANGED_CRITSECT RT_BIT_32(6)
257/** @} */
258
259
260/**
261 * Private USB device instance data.
262 */
263typedef struct PDMUSBINSINT
264{
265 /** The UUID of this instance. */
266 RTUUID Uuid;
267 /** Pointer to the next instance.
268 * (Head is pointed to by PDM::pUsbInstances.) */
269 R3PTRTYPE(PPDMUSBINS) pNext;
270 /** Pointer to the next per USB device instance.
271 * (Head is pointed to by PDMUSB::pInstances.) */
272 R3PTRTYPE(PPDMUSBINS) pPerDeviceNext;
273
274 /** Pointer to device structure. */
275 R3PTRTYPE(PPDMUSB) pUsbDev;
276
277 /** Pointer to the VM this instance was created for. */
278 PVMR3 pVM;
279 /** Pointer to the list of logical units associated with the device. (FIFO) */
280 R3PTRTYPE(PPDMLUN) pLuns;
281 /** The per instance device configuration. */
282 R3PTRTYPE(PCFGMNODE) pCfg;
283 /** Same as pCfg if the configuration should be deleted when detaching the device. */
284 R3PTRTYPE(PCFGMNODE) pCfgDelete;
285 /** The global device configuration. */
286 R3PTRTYPE(PCFGMNODE) pCfgGlobal;
287
288 /** Pointer to the USB hub this device is attached to.
289 * This is NULL if the device isn't connected to any HUB. */
290 R3PTRTYPE(PPDMUSBHUB) pHub;
291 /** The port number that we're connected to. */
292 uint32_t iPort;
293 /** Indicates that the USB device hasn't been powered on or resumed.
294 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
295 bool fVMSuspended;
296 /** Indicates that the USB device has been reset. */
297 bool fVMReset;
298 /** Pointer to the asynchronous notification callback set while in
299 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
300 R3PTRTYPE(PFNPDMUSBASYNCNOTIFY) pfnAsyncNotify;
301} PDMUSBINSINT;
302
303
304/**
305 * Private driver instance data.
306 */
307typedef struct PDMDRVINSINT
308{
309 /** Pointer to the driver instance above.
310 * This is NULL for the topmost drive. */
311 R3PTRTYPE(PPDMDRVINS) pUp;
312 /** Pointer to the driver instance below.
313 * This is NULL for the bottommost driver. */
314 R3PTRTYPE(PPDMDRVINS) pDown;
315 /** Pointer to the logical unit this driver chained on. */
316 R3PTRTYPE(PPDMLUN) pLun;
317 /** Pointer to driver structure from which this was instantiated. */
318 R3PTRTYPE(PPDMDRV) pDrv;
319 /** Pointer to the VM this instance was created for, ring-3 context. */
320 PVMR3 pVMR3;
321 /** Pointer to the VM this instance was created for, ring-0 context. */
322 R0PTRTYPE(PVMCC) pVMR0;
323 /** Pointer to the VM this instance was created for, raw-mode context. */
324 PVMRC pVMRC;
325 /** Flag indicating that the driver is being detached and destroyed.
326 * (Helps detect potential recursive detaching.) */
327 bool fDetaching;
328 /** Indicates that the driver hasn't been powered on or resumed.
329 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
330 bool fVMSuspended;
331 /** Indicates that the driver has been reset already. */
332 bool fVMReset;
333 /** Set if allocated on the hyper heap, false if on the ring-3 heap. */
334 bool fHyperHeap;
335 /** Pointer to the asynchronous notification callback set while in
336 * PDMUSBREG::pfnVMSuspend or PDMUSBREG::pfnVMPowerOff. */
337 R3PTRTYPE(PFNPDMDRVASYNCNOTIFY) pfnAsyncNotify;
338 /** Configuration handle to the instance node. */
339 R3PTRTYPE(PCFGMNODE) pCfgHandle;
340 /** Pointer to the ring-0 request handler function. */
341 PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
342} PDMDRVINSINT;
343
344
345/**
346 * Private critical section data.
347 */
348typedef struct PDMCRITSECTINT
349{
350 /** The critical section core which is shared with IPRT.
351 * @note The semaphore is a SUPSEMEVENT. */
352 RTCRITSECT Core;
353 /** Pointer to the next critical section.
354 * This chain is used for relocating pVMRC and device cleanup. */
355 R3PTRTYPE(struct PDMCRITSECTINT *) pNext;
356 /** Owner identifier.
357 * This is pDevIns if the owner is a device. Similarly for a driver or service.
358 * PDMR3CritSectInit() sets this to point to the critsect itself. */
359 RTR3PTR pvKey;
360 /** Pointer to the VM - R3Ptr. */
361 PVMR3 pVMR3;
362 /** Pointer to the VM - R0Ptr. */
363 R0PTRTYPE(PVMCC) pVMR0;
364 /** Pointer to the VM - GCPtr. */
365 PVMRC pVMRC;
366 /** Set if this critical section is the automatically created default
367 * section of a device. */
368 bool fAutomaticDefaultCritsect;
369 /** Set if the critical section is used by a timer or similar.
370 * See PDMR3DevGetCritSect. */
371 bool fUsedByTimerOrSimilar;
372 /** Alignment padding. */
373 bool afPadding[2];
374 /** Support driver event semaphore that is scheduled to be signaled upon leaving
375 * the critical section. This is only for Ring-3 and Ring-0. */
376 SUPSEMEVENT hEventToSignal;
377 /** The lock name. */
378 R3PTRTYPE(const char *) pszName;
379 /** R0/RC lock contention. */
380 STAMCOUNTER StatContentionRZLock;
381 /** R0/RC unlock contention. */
382 STAMCOUNTER StatContentionRZUnlock;
383 /** R3 lock contention. */
384 STAMCOUNTER StatContentionR3;
385 /** Profiling the time the section is locked. */
386 STAMPROFILEADV StatLocked;
387} PDMCRITSECTINT;
388AssertCompileMemberAlignment(PDMCRITSECTINT, StatContentionRZLock, 8);
389/** Pointer to private critical section data. */
390typedef PDMCRITSECTINT *PPDMCRITSECTINT;
391
392/** Indicates that the critical section is queued for unlock.
393 * PDMCritSectIsOwner and PDMCritSectIsOwned optimizations. */
394#define PDMCRITSECT_FLAGS_PENDING_UNLOCK RT_BIT_32(17)
395
396
397/**
398 * Private critical section data.
399 */
400typedef struct PDMCRITSECTRWINT
401{
402 /** The read/write critical section core which is shared with IPRT.
403 * @note The semaphores are SUPSEMEVENT and SUPSEMEVENTMULTI. */
404 RTCRITSECTRW Core;
405
406 /** Pointer to the next critical section.
407 * This chain is used for relocating pVMRC and device cleanup. */
408 R3PTRTYPE(struct PDMCRITSECTRWINT *) pNext;
409 /** Owner identifier.
410 * This is pDevIns if the owner is a device. Similarly for a driver or service.
411 * PDMR3CritSectInit() sets this to point to the critsect itself. */
412 RTR3PTR pvKey;
413 /** Pointer to the VM - R3Ptr. */
414 PVMR3 pVMR3;
415 /** Pointer to the VM - R0Ptr. */
416 R0PTRTYPE(PVMCC) pVMR0;
417 /** Pointer to the VM - GCPtr. */
418 PVMRC pVMRC;
419#if HC_ARCH_BITS == 64
420 /** Alignment padding. */
421 RTRCPTR RCPtrPadding;
422#endif
423 /** The lock name. */
424 R3PTRTYPE(const char *) pszName;
425 /** R0/RC write lock contention. */
426 STAMCOUNTER StatContentionRZEnterExcl;
427 /** R0/RC write unlock contention. */
428 STAMCOUNTER StatContentionRZLeaveExcl;
429 /** R0/RC read lock contention. */
430 STAMCOUNTER StatContentionRZEnterShared;
431 /** R0/RC read unlock contention. */
432 STAMCOUNTER StatContentionRZLeaveShared;
433 /** R0/RC writes. */
434 STAMCOUNTER StatRZEnterExcl;
435 /** R0/RC reads. */
436 STAMCOUNTER StatRZEnterShared;
437 /** R3 write lock contention. */
438 STAMCOUNTER StatContentionR3EnterExcl;
439 /** R3 read lock contention. */
440 STAMCOUNTER StatContentionR3EnterShared;
441 /** R3 writes. */
442 STAMCOUNTER StatR3EnterExcl;
443 /** R3 reads. */
444 STAMCOUNTER StatR3EnterShared;
445 /** Profiling the time the section is write locked. */
446 STAMPROFILEADV StatWriteLocked;
447} PDMCRITSECTRWINT;
448AssertCompileMemberAlignment(PDMCRITSECTRWINT, StatContentionRZEnterExcl, 8);
449AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u64State, 8);
450/** Pointer to private critical section data. */
451typedef PDMCRITSECTRWINT *PPDMCRITSECTRWINT;
452
453
454
455/**
456 * The usual device/driver/internal/external stuff.
457 */
458typedef enum
459{
460 /** The usual invalid entry. */
461 PDMTHREADTYPE_INVALID = 0,
462 /** Device type. */
463 PDMTHREADTYPE_DEVICE,
464 /** USB Device type. */
465 PDMTHREADTYPE_USB,
466 /** Driver type. */
467 PDMTHREADTYPE_DRIVER,
468 /** Internal type. */
469 PDMTHREADTYPE_INTERNAL,
470 /** External type. */
471 PDMTHREADTYPE_EXTERNAL,
472 /** The usual 32-bit hack. */
473 PDMTHREADTYPE_32BIT_HACK = 0x7fffffff
474} PDMTHREADTYPE;
475
476
477/**
478 * The internal structure for the thread.
479 */
480typedef struct PDMTHREADINT
481{
482 /** The VM pointer. */
483 PVMR3 pVM;
484 /** The event semaphore the thread blocks on when not running. */
485 RTSEMEVENTMULTI BlockEvent;
486 /** The event semaphore the thread sleeps on while running. */
487 RTSEMEVENTMULTI SleepEvent;
488 /** Pointer to the next thread. */
489 R3PTRTYPE(struct PDMTHREAD *) pNext;
490 /** The thread type. */
491 PDMTHREADTYPE enmType;
492} PDMTHREADINT;
493
494
495
496/* Must be included after PDMDEVINSINT is defined. */
497#define PDMDEVINSINT_DECLARED
498#define PDMUSBINSINT_DECLARED
499#define PDMDRVINSINT_DECLARED
500#define PDMCRITSECTINT_DECLARED
501#define PDMCRITSECTRWINT_DECLARED
502#define PDMTHREADINT_DECLARED
503#ifdef ___VBox_pdm_h
504# error "Invalid header PDM order. Include PDMInternal.h before VBox/vmm/pdm.h!"
505#endif
506RT_C_DECLS_END
507#include <VBox/vmm/pdm.h>
508RT_C_DECLS_BEGIN
509
510/**
511 * PDM Logical Unit.
512 *
513 * This typically the representation of a physical port on a
514 * device, like for instance the PS/2 keyboard port on the
515 * keyboard controller device. The LUNs are chained on the
516 * device they belong to (PDMDEVINSINT::pLunsR3).
517 */
518typedef struct PDMLUN
519{
520 /** The LUN - The Logical Unit Number. */
521 RTUINT iLun;
522 /** Pointer to the next LUN. */
523 PPDMLUN pNext;
524 /** Pointer to the top driver in the driver chain. */
525 PPDMDRVINS pTop;
526 /** Pointer to the bottom driver in the driver chain. */
527 PPDMDRVINS pBottom;
528 /** Pointer to the device instance which the LUN belongs to.
529 * Either this is set or pUsbIns is set. Both is never set at the same time. */
530 PPDMDEVINS pDevIns;
531 /** Pointer to the USB device instance which the LUN belongs to. */
532 PPDMUSBINS pUsbIns;
533 /** Pointer to the device base interface. */
534 PPDMIBASE pBase;
535 /** Description of this LUN. */
536 const char *pszDesc;
537} PDMLUN;
538
539
540/**
541 * PDM Device, ring-3.
542 */
543typedef struct PDMDEV
544{
545 /** Pointer to the next device (R3 Ptr). */
546 R3PTRTYPE(PPDMDEV) pNext;
547 /** Device name length. (search optimization) */
548 uint32_t cchName;
549 /** Registration structure. */
550 R3PTRTYPE(const struct PDMDEVREGR3 *) pReg;
551 /** Number of instances. */
552 uint32_t cInstances;
553 /** Pointer to chain of instances (R3 Ptr). */
554 PPDMDEVINSR3 pInstances;
555 /** The search path for raw-mode context modules (';' as separator). */
556 char *pszRCSearchPath;
557 /** The search path for ring-0 context modules (';' as separator). */
558 char *pszR0SearchPath;
559} PDMDEV;
560
561
562#if 0
563/**
564 * PDM Device, ring-0.
565 */
566typedef struct PDMDEVR0
567{
568 /** Pointer to the next device. */
569 R0PTRTYPE(PPDMDEVR0) pNext;
570 /** Device name length. (search optimization) */
571 uint32_t cchName;
572 /** Registration structure. */
573 R3PTRTYPE(const struct PDMDEVREGR0 *) pReg;
574 /** Number of instances. */
575 uint32_t cInstances;
576 /** Pointer to chain of instances. */
577 PPDMDEVINSR0 pInstances;
578} PDMDEVR0;
579#endif
580
581
582/**
583 * PDM USB Device.
584 */
585typedef struct PDMUSB
586{
587 /** Pointer to the next device (R3 Ptr). */
588 R3PTRTYPE(PPDMUSB) pNext;
589 /** Device name length. (search optimization) */
590 RTUINT cchName;
591 /** Registration structure. */
592 R3PTRTYPE(const struct PDMUSBREG *) pReg;
593 /** Next instance number. */
594 uint32_t iNextInstance;
595 /** Pointer to chain of instances (R3 Ptr). */
596 R3PTRTYPE(PPDMUSBINS) pInstances;
597} PDMUSB;
598
599
600/**
601 * PDM Driver.
602 */
603typedef struct PDMDRV
604{
605 /** Pointer to the next device. */
606 PPDMDRV pNext;
607 /** Registration structure. */
608 const struct PDMDRVREG * pReg;
609 /** Current number of instances. */
610 uint32_t cInstances;
611 /** The next instance number. */
612 uint32_t iNextInstance;
613 /** The search path for raw-mode context modules (';' as separator). */
614 char *pszRCSearchPath;
615 /** The search path for ring-0 context modules (';' as separator). */
616 char *pszR0SearchPath;
617} PDMDRV;
618
619
620/**
621 * PDM registered IOMMU device.
622 */
623typedef struct PDMIOMMU
624{
625 /** IOMMU index. */
626 uint32_t idxIommu;
627 uint32_t uPadding0; /**< Alignment padding.*/
628
629 /** Pointer to the IOMMU device instance - R3. */
630 PPDMDEVINSR3 pDevInsR3;
631 /** @copydoc PDMIOMMUREGR3::pfnMemRead */
632 DECLR3CALLBACKMEMBER(int, pfnMemRead,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbRead,
633 PRTGCPHYS pGCPhysSpa));
634 /** @copydoc PDMIOMMUREGR3::pfnMemWrite */
635 DECLR3CALLBACKMEMBER(int, pfnMemWrite,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbWrite,
636 PRTGCPHYS pGCPhysSpa));
637 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
638 DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevId, RTGCPHYS GCPhysIn, uint32_t uDataIn,
639 PRTGCPHYS pGCPhysOut, uint32_t *puDataOut));
640} PDMIOMMU;
641
642
643/**
644 * Ring-0 PDM IOMMU instance data.
645 */
646typedef struct PDMIOMMUR0
647{
648 /** IOMMU index. */
649 uint32_t idxIommu;
650 uint32_t uPadding0; /**< Alignment padding.*/
651
652 /** Pointer to IOMMU device instance. */
653 PPDMDEVINSR0 pDevInsR0;
654 /** @copydoc PDMIOMMUREGR0::pfnMemRead */
655 DECLR0CALLBACKMEMBER(int, pfnMemRead,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbRead,
656 PRTGCPHYS pGCPhysSpa));
657 /** @copydoc PDMIOMMUREGR3::pfnMemWrite */
658 DECLR0CALLBACKMEMBER(int, pfnMemWrite,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbWrite,
659 PRTGCPHYS pGCPhysSpa));
660 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
661 DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevId, RTGCPHYS GCPhysIn, uint32_t uDataIn,
662 PRTGCPHYS pGCPhysOut, uint32_t *puDataOut));
663} PDMIOMMUR0;
664/** Pointer to a ring-0 IOMMU data. */
665typedef PDMIOMMUR0 *PPDMIOMMUR0;
666/** Pointer to a const ring-0 IOMMU data. */
667typedef const PDMIOMMUR0 *PCPDMIOMMUR0;
668
669
670/**
671 * PDM registered PIC device.
672 */
673typedef struct PDMPIC
674{
675 /** Pointer to the PIC device instance - R3. */
676 PPDMDEVINSR3 pDevInsR3;
677 /** @copydoc PDMPICREG::pfnSetIrq */
678 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
679 /** @copydoc PDMPICREG::pfnGetInterrupt */
680 DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
681
682 /** Pointer to the PIC device instance - R0. */
683 PPDMDEVINSR0 pDevInsR0;
684 /** @copydoc PDMPICREG::pfnSetIrq */
685 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
686 /** @copydoc PDMPICREG::pfnGetInterrupt */
687 DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
688
689 /** Pointer to the PIC device instance - RC. */
690 PPDMDEVINSRC pDevInsRC;
691 /** @copydoc PDMPICREG::pfnSetIrq */
692 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
693 /** @copydoc PDMPICREG::pfnGetInterrupt */
694 DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
695 /** Alignment padding. */
696 RTRCPTR RCPtrPadding;
697} PDMPIC;
698
699
700/**
701 * PDM registered APIC device.
702 */
703typedef struct PDMAPIC
704{
705 /** Pointer to the APIC device instance - R3 Ptr. */
706 PPDMDEVINSR3 pDevInsR3;
707 /** Pointer to the APIC device instance - R0 Ptr. */
708 PPDMDEVINSR0 pDevInsR0;
709 /** Pointer to the APIC device instance - RC Ptr. */
710 PPDMDEVINSRC pDevInsRC;
711 uint8_t Alignment[4];
712} PDMAPIC;
713
714
715/**
716 * PDM registered I/O APIC device.
717 */
718typedef struct PDMIOAPIC
719{
720 /** Pointer to the APIC device instance - R3 Ptr. */
721 PPDMDEVINSR3 pDevInsR3;
722 /** @copydoc PDMIOAPICREG::pfnSetIrq */
723 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
724 /** @copydoc PDMIOAPICREG::pfnSendMsi */
725 DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc));
726 /** @copydoc PDMIOAPICREG::pfnSetEoi */
727 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
728
729 /** Pointer to the PIC device instance - R0. */
730 PPDMDEVINSR0 pDevInsR0;
731 /** @copydoc PDMIOAPICREG::pfnSetIrq */
732 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
733 /** @copydoc PDMIOAPICREG::pfnSendMsi */
734 DECLR0CALLBACKMEMBER(void, pfnSendMsiR0,(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc));
735 /** @copydoc PDMIOAPICREG::pfnSetEoi */
736 DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiR0,(PPDMDEVINS pDevIns, uint8_t u8Vector));
737
738 /** Pointer to the APIC device instance - RC Ptr. */
739 PPDMDEVINSRC pDevInsRC;
740 /** @copydoc PDMIOAPICREG::pfnSetIrq */
741 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
742 /** @copydoc PDMIOAPICREG::pfnSendMsi */
743 DECLRCCALLBACKMEMBER(void, pfnSendMsiRC,(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc));
744 /** @copydoc PDMIOAPICREG::pfnSendMsi */
745 DECLRCCALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiRC,(PPDMDEVINS pDevIns, uint8_t u8Vector));
746} PDMIOAPIC;
747
748/** Maximum number of PCI busses for a VM. */
749#define PDM_PCI_BUSSES_MAX 8
750/** Maximum number of IOMMUs (at most one per PCI bus). */
751#define PDM_IOMMUS_MAX PDM_PCI_BUSSES_MAX
752
753
754#ifdef IN_RING3
755/**
756 * PDM registered firmware device.
757 */
758typedef struct PDMFW
759{
760 /** Pointer to the firmware device instance. */
761 PPDMDEVINSR3 pDevIns;
762 /** Copy of the registration structure. */
763 PDMFWREG Reg;
764} PDMFW;
765/** Pointer to a firmware instance. */
766typedef PDMFW *PPDMFW;
767#endif
768
769
770/**
771 * PDM PCI bus instance.
772 */
773typedef struct PDMPCIBUS
774{
775 /** PCI bus number. */
776 uint32_t iBus;
777 uint32_t uPadding0; /**< Alignment padding.*/
778
779 /** Pointer to PCI bus device instance. */
780 PPDMDEVINSR3 pDevInsR3;
781 /** @copydoc PDMPCIBUSREGR3::pfnSetIrqR3 */
782 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
783
784 /** @copydoc PDMPCIBUSREGR3::pfnRegisterR3 */
785 DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
786 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
787 /** @copydoc PDMPCIBUSREGR3::pfnRegisterMsiR3 */
788 DECLR3CALLBACKMEMBER(int, pfnRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
789 /** @copydoc PDMPCIBUSREGR3::pfnIORegionRegisterR3 */
790 DECLR3CALLBACKMEMBER(int, pfnIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
791 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
792 uint64_t hHandle, PFNPCIIOREGIONMAP pfnCallback));
793 /** @copydoc PDMPCIBUSREGR3::pfnInterceptConfigAccesses */
794 DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
795 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
796 /** @copydoc PDMPCIBUSREGR3::pfnConfigWrite */
797 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
798 uint32_t uAddress, unsigned cb, uint32_t u32Value));
799 /** @copydoc PDMPCIBUSREGR3::pfnConfigRead */
800 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
801 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
802} PDMPCIBUS;
803
804
805/**
806 * Ring-0 PDM PCI bus instance data.
807 */
808typedef struct PDMPCIBUSR0
809{
810 /** PCI bus number. */
811 uint32_t iBus;
812 uint32_t uPadding0; /**< Alignment padding.*/
813 /** Pointer to PCI bus device instance. */
814 PPDMDEVINSR0 pDevInsR0;
815 /** @copydoc PDMPCIBUSREGR0::pfnSetIrq */
816 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
817} PDMPCIBUSR0;
818/** Pointer to the ring-0 PCI bus data. */
819typedef PDMPCIBUSR0 *PPDMPCIBUSR0;
820
821
822#ifdef IN_RING3
823/**
824 * PDM registered DMAC (DMA Controller) device.
825 */
826typedef struct PDMDMAC
827{
828 /** Pointer to the DMAC device instance. */
829 PPDMDEVINSR3 pDevIns;
830 /** Copy of the registration structure. */
831 PDMDMACREG Reg;
832} PDMDMAC;
833
834
835/**
836 * PDM registered RTC (Real Time Clock) device.
837 */
838typedef struct PDMRTC
839{
840 /** Pointer to the RTC device instance. */
841 PPDMDEVINSR3 pDevIns;
842 /** Copy of the registration structure. */
843 PDMRTCREG Reg;
844} PDMRTC;
845
846#endif /* IN_RING3 */
847
848/**
849 * Module type.
850 */
851typedef enum PDMMODTYPE
852{
853 /** Raw-mode (RC) context module. */
854 PDMMOD_TYPE_RC,
855 /** Ring-0 (host) context module. */
856 PDMMOD_TYPE_R0,
857 /** Ring-3 (host) context module. */
858 PDMMOD_TYPE_R3
859} PDMMODTYPE;
860
861
862/** The module name length including the terminator. */
863#define PDMMOD_NAME_LEN 32
864
865/**
866 * Loaded module instance.
867 */
868typedef struct PDMMOD
869{
870 /** Module name. This is used for referring to
871 * the module internally, sort of like a handle. */
872 char szName[PDMMOD_NAME_LEN];
873 /** Module type. */
874 PDMMODTYPE eType;
875 /** Loader module handle. Not used for R0 modules. */
876 RTLDRMOD hLdrMod;
877 /** Loaded address.
878 * This is the 'handle' for R0 modules. */
879 RTUINTPTR ImageBase;
880 /** Old loaded address.
881 * This is used during relocation of GC modules. Not used for R0 modules. */
882 RTUINTPTR OldImageBase;
883 /** Where the R3 HC bits are stored.
884 * This can be equal to ImageBase but doesn't have to. Not used for R0 modules. */
885 void *pvBits;
886
887 /** Pointer to next module. */
888 struct PDMMOD *pNext;
889 /** Module filename. */
890 char szFilename[1];
891} PDMMOD;
892/** Pointer to loaded module instance. */
893typedef PDMMOD *PPDMMOD;
894
895
896
897/** Extra space in the free array. */
898#define PDMQUEUE_FREE_SLACK 16
899
900/**
901 * Queue type.
902 */
903typedef enum PDMQUEUETYPE
904{
905 /** Device consumer. */
906 PDMQUEUETYPE_DEV = 1,
907 /** Driver consumer. */
908 PDMQUEUETYPE_DRV,
909 /** Internal consumer. */
910 PDMQUEUETYPE_INTERNAL,
911 /** External consumer. */
912 PDMQUEUETYPE_EXTERNAL
913} PDMQUEUETYPE;
914
915/** Pointer to a PDM Queue. */
916typedef struct PDMQUEUE *PPDMQUEUE;
917
918/**
919 * PDM Queue.
920 */
921typedef struct PDMQUEUE
922{
923 /** Pointer to the next queue in the list. */
924 R3PTRTYPE(PPDMQUEUE) pNext;
925 /** Type specific data. */
926 union
927 {
928 /** PDMQUEUETYPE_DEV */
929 struct
930 {
931 /** Pointer to consumer function. */
932 R3PTRTYPE(PFNPDMQUEUEDEV) pfnCallback;
933 /** Pointer to the device instance owning the queue. */
934 R3PTRTYPE(PPDMDEVINS) pDevIns;
935 } Dev;
936 /** PDMQUEUETYPE_DRV */
937 struct
938 {
939 /** Pointer to consumer function. */
940 R3PTRTYPE(PFNPDMQUEUEDRV) pfnCallback;
941 /** Pointer to the driver instance owning the queue. */
942 R3PTRTYPE(PPDMDRVINS) pDrvIns;
943 } Drv;
944 /** PDMQUEUETYPE_INTERNAL */
945 struct
946 {
947 /** Pointer to consumer function. */
948 R3PTRTYPE(PFNPDMQUEUEINT) pfnCallback;
949 } Int;
950 /** PDMQUEUETYPE_EXTERNAL */
951 struct
952 {
953 /** Pointer to consumer function. */
954 R3PTRTYPE(PFNPDMQUEUEEXT) pfnCallback;
955 /** Pointer to user argument. */
956 R3PTRTYPE(void *) pvUser;
957 } Ext;
958 } u;
959 /** Queue type. */
960 PDMQUEUETYPE enmType;
961 /** The interval between checking the queue for events.
962 * The realtime timer below is used to do the waiting.
963 * If 0, the queue will use the VM_FF_PDM_QUEUE forced action. */
964 uint32_t cMilliesInterval;
965 /** Interval timer. Only used if cMilliesInterval is non-zero. */
966 PTMTIMERR3 pTimer;
967 /** Pointer to the VM - R3. */
968 PVMR3 pVMR3;
969 /** LIFO of pending items - R3. */
970 R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR3;
971 /** Pointer to the VM - R0. */
972 PVMR0 pVMR0;
973 /** LIFO of pending items - R0. */
974 R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR0;
975 /** Pointer to the GC VM and indicator for GC enabled queue.
976 * If this is NULL, the queue cannot be used in GC.
977 */
978 PVMRC pVMRC;
979 /** LIFO of pending items - GC. */
980 RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingRC;
981
982 /** Item size (bytes). */
983 uint32_t cbItem;
984 /** Number of items in the queue. */
985 uint32_t cItems;
986 /** Index to the free head (where we insert). */
987 uint32_t volatile iFreeHead;
988 /** Index to the free tail (where we remove). */
989 uint32_t volatile iFreeTail;
990
991 /** Unique queue name. */
992 R3PTRTYPE(const char *) pszName;
993#if HC_ARCH_BITS == 32
994 RTR3PTR Alignment1;
995#endif
996 /** Stat: Times PDMQueueAlloc fails. */
997 STAMCOUNTER StatAllocFailures;
998 /** Stat: PDMQueueInsert calls. */
999 STAMCOUNTER StatInsert;
1000 /** Stat: Queue flushes. */
1001 STAMCOUNTER StatFlush;
1002 /** Stat: Queue flushes with pending items left over. */
1003 STAMCOUNTER StatFlushLeftovers;
1004#ifdef VBOX_WITH_STATISTICS
1005 /** State: Profiling the flushing. */
1006 STAMPROFILE StatFlushPrf;
1007 /** State: Pending items. */
1008 uint32_t volatile cStatPending;
1009 uint32_t volatile cAlignment;
1010#endif
1011
1012 /** Array of pointers to free items. Variable size. */
1013 struct PDMQUEUEFREEITEM
1014 {
1015 /** Pointer to the free item - HC Ptr. */
1016 R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR3;
1017 /** Pointer to the free item - HC Ptr. */
1018 R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR0;
1019 /** Pointer to the free item - GC Ptr. */
1020 RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pItemRC;
1021#if HC_ARCH_BITS == 64
1022 RTRCPTR Alignment0;
1023#endif
1024 } aFreeItems[1];
1025} PDMQUEUE;
1026
1027/** @name PDM::fQueueFlushing
1028 * @{ */
1029/** Used to make sure only one EMT will flush the queues.
1030 * Set when an EMT is flushing queues, clear otherwise. */
1031#define PDM_QUEUE_FLUSH_FLAG_ACTIVE_BIT 0
1032/** Indicating there are queues with items pending.
1033 * This is make sure we don't miss inserts happening during flushing. The FF
1034 * cannot be used for this since it has to be cleared immediately to prevent
1035 * other EMTs from spinning. */
1036#define PDM_QUEUE_FLUSH_FLAG_PENDING_BIT 1
1037/** @} */
1038
1039
1040/** @name PDM task structures.
1041 * @{ */
1042
1043/**
1044 * A asynchronous user mode task.
1045 */
1046typedef struct PDMTASK
1047{
1048 /** Task owner type. */
1049 PDMTASKTYPE volatile enmType;
1050 /** Queue flags. */
1051 uint32_t volatile fFlags;
1052 /** User argument for the callback. */
1053 R3PTRTYPE(void *) volatile pvUser;
1054 /** The callback (will be cast according to enmType before callout). */
1055 R3PTRTYPE(PFNRT) volatile pfnCallback;
1056 /** The owner identifier. */
1057 R3PTRTYPE(void *) volatile pvOwner;
1058 /** Task name. */
1059 R3PTRTYPE(const char *) pszName;
1060 /** Number of times already triggered when PDMTaskTrigger was called. */
1061 uint32_t volatile cAlreadyTrigged;
1062 /** Number of runs. */
1063 uint32_t cRuns;
1064} PDMTASK;
1065/** Pointer to a PDM task. */
1066typedef PDMTASK *PPDMTASK;
1067
1068/**
1069 * A task set.
1070 *
1071 * This is served by one task executor thread.
1072 */
1073typedef struct PDMTASKSET
1074{
1075 /** Magic value (PDMTASKSET_MAGIC). */
1076 uint32_t u32Magic;
1077 /** Set if this task set works for ring-0 and raw-mode. */
1078 bool fRZEnabled;
1079 /** Number of allocated taks. */
1080 uint8_t volatile cAllocated;
1081 /** Base handle value for this set. */
1082 uint16_t uHandleBase;
1083 /** The task executor thread. */
1084 R3PTRTYPE(RTTHREAD) hThread;
1085 /** Event semaphore for waking up the thread when fRZEnabled is set. */
1086 SUPSEMEVENT hEventR0;
1087 /** Event semaphore for waking up the thread when fRZEnabled is clear. */
1088 R3PTRTYPE(RTSEMEVENT) hEventR3;
1089 /** The VM pointer. */
1090 PVM pVM;
1091 /** Padding so fTriggered is in its own cacheline. */
1092 uint64_t au64Padding2[3];
1093
1094 /** Bitmask of triggered tasks. */
1095 uint64_t volatile fTriggered;
1096 /** Shutdown thread indicator. */
1097 bool volatile fShutdown;
1098 /** Padding. */
1099 bool volatile afPadding3[3];
1100 /** Task currently running, UINT32_MAX if idle. */
1101 uint32_t volatile idxRunning;
1102 /** Padding so fTriggered and fShutdown are in their own cacheline. */
1103 uint64_t volatile au64Padding3[6];
1104
1105 /** The individual tasks. (Unallocated tasks have NULL pvOwner.) */
1106 PDMTASK aTasks[64];
1107} PDMTASKSET;
1108AssertCompileMemberAlignment(PDMTASKSET, fTriggered, 64);
1109AssertCompileMemberAlignment(PDMTASKSET, aTasks, 64);
1110/** Magic value for PDMTASKSET::u32Magic. */
1111#define PDMTASKSET_MAGIC UINT32_C(0x19320314)
1112/** Pointer to a task set. */
1113typedef PDMTASKSET *PPDMTASKSET;
1114
1115/** @} */
1116
1117
1118/**
1119 * Queue device helper task operation.
1120 */
1121typedef enum PDMDEVHLPTASKOP
1122{
1123 /** The usual invalid 0 entry. */
1124 PDMDEVHLPTASKOP_INVALID = 0,
1125 /** ISASetIrq */
1126 PDMDEVHLPTASKOP_ISA_SET_IRQ,
1127 /** PCISetIrq */
1128 PDMDEVHLPTASKOP_PCI_SET_IRQ,
1129 /** PCISetIrq */
1130 PDMDEVHLPTASKOP_IOAPIC_SET_IRQ,
1131 /** The usual 32-bit hack. */
1132 PDMDEVHLPTASKOP_32BIT_HACK = 0x7fffffff
1133} PDMDEVHLPTASKOP;
1134
1135/**
1136 * Queued Device Helper Task.
1137 */
1138typedef struct PDMDEVHLPTASK
1139{
1140 /** The queue item core (don't touch). */
1141 PDMQUEUEITEMCORE Core;
1142 /** Pointer to the device instance (R3 Ptr). */
1143 PPDMDEVINSR3 pDevInsR3;
1144 /** This operation to perform. */
1145 PDMDEVHLPTASKOP enmOp;
1146#if HC_ARCH_BITS == 64
1147 uint32_t Alignment0;
1148#endif
1149 /** Parameters to the operation. */
1150 union PDMDEVHLPTASKPARAMS
1151 {
1152 /**
1153 * PDMDEVHLPTASKOP_ISA_SET_IRQ and PDMDEVHLPTASKOP_IOAPIC_SET_IRQ.
1154 */
1155 struct PDMDEVHLPTASKISASETIRQ
1156 {
1157 /** The IRQ */
1158 int iIrq;
1159 /** The new level. */
1160 int iLevel;
1161 /** The IRQ tag and source. */
1162 uint32_t uTagSrc;
1163 } IsaSetIRQ, IoApicSetIRQ;
1164
1165 /**
1166 * PDMDEVHLPTASKOP_PCI_SET_IRQ
1167 */
1168 struct PDMDEVHLPTASKPCISETIRQ
1169 {
1170 /** Pointer to the PCI device (R3 Ptr). */
1171 R3PTRTYPE(PPDMPCIDEV) pPciDevR3;
1172 /** The IRQ */
1173 int iIrq;
1174 /** The new level. */
1175 int iLevel;
1176 /** The IRQ tag and source. */
1177 uint32_t uTagSrc;
1178 } PciSetIRQ;
1179
1180 /** Expanding the structure. */
1181 uint64_t au64[3];
1182 } u;
1183} PDMDEVHLPTASK;
1184/** Pointer to a queued Device Helper Task. */
1185typedef PDMDEVHLPTASK *PPDMDEVHLPTASK;
1186/** Pointer to a const queued Device Helper Task. */
1187typedef const PDMDEVHLPTASK *PCPDMDEVHLPTASK;
1188
1189
1190
1191/**
1192 * An USB hub registration record.
1193 */
1194typedef struct PDMUSBHUB
1195{
1196 /** The USB versions this hub support.
1197 * Note that 1.1 hubs can take on 2.0 devices. */
1198 uint32_t fVersions;
1199 /** The number of ports on the hub. */
1200 uint32_t cPorts;
1201 /** The number of available ports (0..cPorts). */
1202 uint32_t cAvailablePorts;
1203 /** The driver instance of the hub. */
1204 PPDMDRVINS pDrvIns;
1205 /** Copy of the to the registration structure. */
1206 PDMUSBHUBREG Reg;
1207
1208 /** Pointer to the next hub in the list. */
1209 struct PDMUSBHUB *pNext;
1210} PDMUSBHUB;
1211
1212/** Pointer to a const USB HUB registration record. */
1213typedef const PDMUSBHUB *PCPDMUSBHUB;
1214
1215/** Pointer to a PDM Async I/O template. */
1216typedef struct PDMASYNCCOMPLETIONTEMPLATE *PPDMASYNCCOMPLETIONTEMPLATE;
1217
1218/** Pointer to the main PDM Async completion endpoint class. */
1219typedef struct PDMASYNCCOMPLETIONEPCLASS *PPDMASYNCCOMPLETIONEPCLASS;
1220
1221/** Pointer to the global block cache structure. */
1222typedef struct PDMBLKCACHEGLOBAL *PPDMBLKCACHEGLOBAL;
1223
1224/**
1225 * PDM VMCPU Instance data.
1226 * Changes to this must checked against the padding of the pdm union in VMCPU!
1227 */
1228typedef struct PDMCPU
1229{
1230 /** The number of entries in the apQueuedCritSectsLeaves table that's currently
1231 * in use. */
1232 uint32_t cQueuedCritSectLeaves;
1233 uint32_t uPadding0; /**< Alignment padding.*/
1234 /** Critical sections queued in RC/R0 because of contention preventing leave to
1235 * complete. (R3 Ptrs)
1236 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1237 R3PTRTYPE(PPDMCRITSECT) apQueuedCritSectLeaves[8];
1238
1239 /** The number of entries in the apQueuedCritSectRwExclLeaves table that's
1240 * currently in use. */
1241 uint32_t cQueuedCritSectRwExclLeaves;
1242 uint32_t uPadding1; /**< Alignment padding.*/
1243 /** Read/write critical sections queued in RC/R0 because of contention
1244 * preventing exclusive leave to complete. (R3 Ptrs)
1245 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1246 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwExclLeaves[8];
1247
1248 /** The number of entries in the apQueuedCritSectsRwShrdLeaves table that's
1249 * currently in use. */
1250 uint32_t cQueuedCritSectRwShrdLeaves;
1251 uint32_t uPadding2; /**< Alignment padding.*/
1252 /** Read/write critical sections queued in RC/R0 because of contention
1253 * preventing shared leave to complete. (R3 Ptrs)
1254 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1255 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwShrdLeaves[8];
1256} PDMCPU;
1257
1258
1259/**
1260 * PDM VM Instance data.
1261 * Changes to this must checked against the padding of the cfgm union in VM!
1262 */
1263typedef struct PDM
1264{
1265 /** The PDM lock.
1266 * This is used to protect everything that deals with interrupts, i.e.
1267 * the PIC, APIC, IOAPIC and PCI devices plus some PDM functions. */
1268 PDMCRITSECT CritSect;
1269 /** The NOP critical section.
1270 * This is a dummy critical section that will not do any thread
1271 * serialization but instead let all threads enter immediately and
1272 * concurrently. */
1273 PDMCRITSECT NopCritSect;
1274
1275 /** The ring-0 capable task sets (max 128). */
1276 PDMTASKSET aTaskSets[2];
1277 /** Pointer to task sets (max 512). */
1278 R3PTRTYPE(PPDMTASKSET) apTaskSets[8];
1279
1280 /** PCI Buses. */
1281 PDMPCIBUS aPciBuses[PDM_PCI_BUSSES_MAX];
1282 /** IOMMU devices. */
1283 PDMIOMMU aIommus[PDM_IOMMUS_MAX];
1284 /** The register PIC device. */
1285 PDMPIC Pic;
1286 /** The registered APIC device. */
1287 PDMAPIC Apic;
1288 /** The registered I/O APIC device. */
1289 PDMIOAPIC IoApic;
1290 /** The registered HPET device. */
1291 PPDMDEVINSR3 pHpet;
1292
1293 /** List of registered devices. (FIFO) */
1294 R3PTRTYPE(PPDMDEV) pDevs;
1295 /** List of devices instances. (FIFO) */
1296 R3PTRTYPE(PPDMDEVINS) pDevInstances;
1297 /** List of registered USB devices. (FIFO) */
1298 R3PTRTYPE(PPDMUSB) pUsbDevs;
1299 /** List of USB devices instances. (FIFO) */
1300 R3PTRTYPE(PPDMUSBINS) pUsbInstances;
1301 /** List of registered drivers. (FIFO) */
1302 R3PTRTYPE(PPDMDRV) pDrvs;
1303 /** The registered firmware device (can be NULL). */
1304 R3PTRTYPE(PPDMFW) pFirmware;
1305 /** The registered DMAC device. */
1306 R3PTRTYPE(PPDMDMAC) pDmac;
1307 /** The registered RTC device. */
1308 R3PTRTYPE(PPDMRTC) pRtc;
1309 /** The registered USB HUBs. (FIFO) */
1310 R3PTRTYPE(PPDMUSBHUB) pUsbHubs;
1311
1312 /** @name Queues
1313 * @{ */
1314 /** Queue in which devhlp tasks are queued for R3 execution - R3 Ptr. */
1315 R3PTRTYPE(PPDMQUEUE) pDevHlpQueueR3;
1316 /** Queue in which devhlp tasks are queued for R3 execution - R0 Ptr. */
1317 R0PTRTYPE(PPDMQUEUE) pDevHlpQueueR0;
1318 /** Queue in which devhlp tasks are queued for R3 execution - RC Ptr. */
1319 RCPTRTYPE(PPDMQUEUE) pDevHlpQueueRC;
1320 /** Pointer to the queue which should be manually flushed - RC Ptr.
1321 * Only touched by EMT. */
1322 RCPTRTYPE(struct PDMQUEUE *) pQueueFlushRC;
1323 /** Pointer to the queue which should be manually flushed - R0 Ptr.
1324 * Only touched by EMT. */
1325 R0PTRTYPE(struct PDMQUEUE *) pQueueFlushR0;
1326 /** Bitmask controlling the queue flushing.
1327 * See PDM_QUEUE_FLUSH_FLAG_ACTIVE and PDM_QUEUE_FLUSH_FLAG_PENDING. */
1328 uint32_t volatile fQueueFlushing;
1329 /** @} */
1330
1331 /** The current IRQ tag (tracing purposes). */
1332 uint32_t volatile uIrqTag;
1333
1334 /** Pending reset flags (PDMVMRESET_F_XXX). */
1335 uint32_t volatile fResetFlags;
1336
1337 /** Set by pdmR3LoadExec for use in assertions. */
1338 bool fStateLoaded;
1339 /** Alignment padding. */
1340 bool afPadding[3];
1341
1342 /** The tracing ID of the next device instance.
1343 *
1344 * @remarks We keep the device tracing ID seperate from the rest as these are
1345 * then more likely to end up with the same ID from one run to
1346 * another, making analysis somewhat easier. Drivers and USB devices
1347 * are more volatile and can be changed at runtime, thus these are much
1348 * less likely to remain stable, so just heap them all together. */
1349 uint32_t idTracingDev;
1350 /** The tracing ID of the next driver instance, USB device instance or other
1351 * PDM entity requiring an ID. */
1352 uint32_t idTracingOther;
1353
1354 /** @name VMM device heap
1355 * @{ */
1356 /** The heap size. */
1357 uint32_t cbVMMDevHeap;
1358 /** Free space. */
1359 uint32_t cbVMMDevHeapLeft;
1360 /** Pointer to the heap base (MMIO2 ring-3 mapping). NULL if not registered. */
1361 RTR3PTR pvVMMDevHeap;
1362 /** Ring-3 mapping/unmapping notification callback for the user. */
1363 PFNPDMVMMDEVHEAPNOTIFY pfnVMMDevHeapNotify;
1364 /** The current mapping. NIL_RTGCPHYS if not mapped or registered. */
1365 RTGCPHYS GCPhysVMMDevHeap;
1366 /** @} */
1367
1368 /** Number of times a critical section leave request needed to be queued for ring-3 execution. */
1369 STAMCOUNTER StatQueuedCritSectLeaves;
1370} PDM;
1371AssertCompileMemberAlignment(PDM, CritSect, 8);
1372AssertCompileMemberAlignment(PDM, aTaskSets, 64);
1373AssertCompileMemberAlignment(PDM, StatQueuedCritSectLeaves, 8);
1374AssertCompileMemberAlignment(PDM, GCPhysVMMDevHeap, sizeof(RTGCPHYS));
1375/** Pointer to PDM VM instance data. */
1376typedef PDM *PPDM;
1377
1378
1379/**
1380 * PDM data kept in the ring-0 GVM.
1381 */
1382typedef struct PDMR0PERVM
1383{
1384 /** PCI Buses, ring-0 data. */
1385 PDMPCIBUSR0 aPciBuses[PDM_PCI_BUSSES_MAX];
1386 /** IOMMUs, ring-0 data. */
1387 PDMIOMMUR0 aIommus[PDM_IOMMUS_MAX];
1388 /** Number of valid ring-0 device instances (apDevInstances). */
1389 uint32_t cDevInstances;
1390 uint32_t u32Padding;
1391 /** Pointer to ring-0 device instances. */
1392 R0PTRTYPE(struct PDMDEVINSR0 *) apDevInstances[190];
1393} PDMR0PERVM;
1394
1395
1396/**
1397 * PDM data kept in the UVM.
1398 */
1399typedef struct PDMUSERPERVM
1400{
1401 /** @todo move more stuff over here. */
1402
1403 /** Linked list of timer driven PDM queues.
1404 * Currently serialized by PDM::CritSect. */
1405 R3PTRTYPE(struct PDMQUEUE *) pQueuesTimer;
1406 /** Linked list of force action driven PDM queues.
1407 * Currently serialized by PDM::CritSect. */
1408 R3PTRTYPE(struct PDMQUEUE *) pQueuesForced;
1409
1410 /** Lock protecting the lists below it. */
1411 RTCRITSECT ListCritSect;
1412 /** Pointer to list of loaded modules. */
1413 PPDMMOD pModules;
1414 /** List of initialized critical sections. (LIFO) */
1415 R3PTRTYPE(PPDMCRITSECTINT) pCritSects;
1416 /** List of initialized read/write critical sections. (LIFO) */
1417 R3PTRTYPE(PPDMCRITSECTRWINT) pRwCritSects;
1418 /** Head of the PDM Thread list. (singly linked) */
1419 R3PTRTYPE(PPDMTHREAD) pThreads;
1420 /** Tail of the PDM Thread list. (singly linked) */
1421 R3PTRTYPE(PPDMTHREAD) pThreadsTail;
1422
1423 /** @name PDM Async Completion
1424 * @{ */
1425 /** Pointer to the array of supported endpoint classes. */
1426 PPDMASYNCCOMPLETIONEPCLASS apAsyncCompletionEndpointClass[PDMASYNCCOMPLETIONEPCLASSTYPE_MAX];
1427 /** Head of the templates. Singly linked, protected by ListCritSect. */
1428 R3PTRTYPE(PPDMASYNCCOMPLETIONTEMPLATE) pAsyncCompletionTemplates;
1429 /** @} */
1430
1431 /** Global block cache data. */
1432 R3PTRTYPE(PPDMBLKCACHEGLOBAL) pBlkCacheGlobal;
1433#ifdef VBOX_WITH_NETSHAPER
1434 /** Pointer to network shaper instance. */
1435 R3PTRTYPE(PPDMNETSHAPER) pNetShaper;
1436#endif /* VBOX_WITH_NETSHAPER */
1437
1438} PDMUSERPERVM;
1439/** Pointer to the PDM data kept in the UVM. */
1440typedef PDMUSERPERVM *PPDMUSERPERVM;
1441
1442
1443
1444/*******************************************************************************
1445* Global Variables *
1446*******************************************************************************/
1447#ifdef IN_RING3
1448extern const PDMDRVHLPR3 g_pdmR3DrvHlp;
1449extern const PDMDEVHLPR3 g_pdmR3DevHlpTrusted;
1450extern const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted;
1451extern const PDMPICHLP g_pdmR3DevPicHlp;
1452extern const PDMIOAPICHLP g_pdmR3DevIoApicHlp;
1453extern const PDMFWHLPR3 g_pdmR3DevFirmwareHlp;
1454extern const PDMPCIHLPR3 g_pdmR3DevPciHlp;
1455extern const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp;
1456extern const PDMDMACHLP g_pdmR3DevDmacHlp;
1457extern const PDMRTCHLP g_pdmR3DevRtcHlp;
1458extern const PDMHPETHLPR3 g_pdmR3DevHpetHlp;
1459extern const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp;
1460#endif
1461
1462
1463/*******************************************************************************
1464* Defined Constants And Macros *
1465*******************************************************************************/
1466/** @def PDMDEV_ASSERT_DEVINS
1467 * Asserts the validity of the device instance.
1468 */
1469#ifdef VBOX_STRICT
1470# define PDMDEV_ASSERT_DEVINS(pDevIns) \
1471 do { \
1472 AssertPtr(pDevIns); \
1473 Assert(pDevIns->u32Version == PDM_DEVINS_VERSION); \
1474 Assert(pDevIns->CTX_SUFF(pvInstanceDataFor) == (void *)&pDevIns->achInstanceData[0]); \
1475 } while (0)
1476#else
1477# define PDMDEV_ASSERT_DEVINS(pDevIns) do { } while (0)
1478#endif
1479
1480/** @def PDMDRV_ASSERT_DRVINS
1481 * Asserts the validity of the driver instance.
1482 */
1483#ifdef VBOX_STRICT
1484# define PDMDRV_ASSERT_DRVINS(pDrvIns) \
1485 do { \
1486 AssertPtr(pDrvIns); \
1487 Assert(pDrvIns->u32Version == PDM_DRVINS_VERSION); \
1488 Assert(pDrvIns->CTX_SUFF(pvInstanceData) == (void *)&pDrvIns->achInstanceData[0]); \
1489 } while (0)
1490#else
1491# define PDMDRV_ASSERT_DRVINS(pDrvIns) do { } while (0)
1492#endif
1493
1494
1495/*******************************************************************************
1496* Internal Functions *
1497*******************************************************************************/
1498#ifdef IN_RING3
1499bool pdmR3IsValidName(const char *pszName);
1500
1501int pdmR3CritSectBothInitStats(PVM pVM);
1502void pdmR3CritSectBothRelocate(PVM pVM);
1503int pdmR3CritSectBothDeleteDevice(PVM pVM, PPDMDEVINS pDevIns);
1504int pdmR3CritSectBothDeleteDriver(PVM pVM, PPDMDRVINS pDrvIns);
1505int pdmR3CritSectInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1506 const char *pszNameFmt, va_list va);
1507int pdmR3CritSectInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1508 const char *pszNameFmt, ...);
1509int pdmR3CritSectInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1510 const char *pszNameFmt, ...);
1511int pdmR3CritSectRwInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1512 const char *pszNameFmt, va_list va);
1513int pdmR3CritSectRwInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1514 const char *pszNameFmt, ...);
1515int pdmR3CritSectRwInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1516 const char *pszNameFmt, ...);
1517
1518int pdmR3DevInit(PVM pVM);
1519int pdmR3DevInitComplete(PVM pVM);
1520PPDMDEV pdmR3DevLookup(PVM pVM, const char *pszName);
1521int pdmR3DevFindLun(PVM pVM, const char *pszDevice, unsigned iInstance, unsigned iLun, PPDMLUN *ppLun);
1522DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem);
1523
1524int pdmR3UsbLoadModules(PVM pVM);
1525int pdmR3UsbInstantiateDevices(PVM pVM);
1526PPDMUSB pdmR3UsbLookup(PVM pVM, const char *pszName);
1527int pdmR3UsbRegisterHub(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fVersions, uint32_t cPorts, PCPDMUSBHUBREG pUsbHubReg, PPCPDMUSBHUBHLP ppUsbHubHlp);
1528int pdmR3UsbVMInitComplete(PVM pVM);
1529
1530int pdmR3DrvInit(PVM pVM);
1531int pdmR3DrvInstantiate(PVM pVM, PCFGMNODE pNode, PPDMIBASE pBaseInterface, PPDMDRVINS pDrvAbove,
1532 PPDMLUN pLun, PPDMIBASE *ppBaseInterface);
1533int pdmR3DrvDetach(PPDMDRVINS pDrvIns, uint32_t fFlags);
1534void pdmR3DrvDestroyChain(PPDMDRVINS pDrvIns, uint32_t fFlags);
1535PPDMDRV pdmR3DrvLookup(PVM pVM, const char *pszName);
1536
1537int pdmR3LdrInitU(PUVM pUVM);
1538void pdmR3LdrTermU(PUVM pUVM);
1539char *pdmR3FileR3(const char *pszFile, bool fShared);
1540int pdmR3LoadR3U(PUVM pUVM, const char *pszFilename, const char *pszName);
1541
1542void pdmR3QueueRelocate(PVM pVM, RTGCINTPTR offDelta);
1543
1544int pdmR3TaskInit(PVM pVM);
1545void pdmR3TaskTerm(PVM pVM);
1546
1547int pdmR3ThreadCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
1548 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1549int pdmR3ThreadCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADUSB pfnThread,
1550 PFNPDMTHREADWAKEUPUSB pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1551int pdmR3ThreadCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDRV pfnThread,
1552 PFNPDMTHREADWAKEUPDRV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1553int pdmR3ThreadDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1554int pdmR3ThreadDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1555int pdmR3ThreadDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1556void pdmR3ThreadDestroyAll(PVM pVM);
1557int pdmR3ThreadResumeAll(PVM pVM);
1558int pdmR3ThreadSuspendAll(PVM pVM);
1559
1560#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
1561int pdmR3AsyncCompletionInit(PVM pVM);
1562int pdmR3AsyncCompletionTerm(PVM pVM);
1563void pdmR3AsyncCompletionResume(PVM pVM);
1564int pdmR3AsyncCompletionTemplateCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEDEV pfnCompleted, const char *pszDesc);
1565int pdmR3AsyncCompletionTemplateCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate,
1566 PFNPDMASYNCCOMPLETEDRV pfnCompleted, void *pvTemplateUser, const char *pszDesc);
1567int pdmR3AsyncCompletionTemplateCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEUSB pfnCompleted, const char *pszDesc);
1568int pdmR3AsyncCompletionTemplateDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1569int pdmR3AsyncCompletionTemplateDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1570int pdmR3AsyncCompletionTemplateDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1571#endif
1572
1573#ifdef VBOX_WITH_NETSHAPER
1574int pdmR3NetShaperInit(PVM pVM);
1575int pdmR3NetShaperTerm(PVM pVM);
1576#endif
1577
1578int pdmR3BlkCacheInit(PVM pVM);
1579void pdmR3BlkCacheTerm(PVM pVM);
1580int pdmR3BlkCacheResume(PVM pVM);
1581
1582#endif /* IN_RING3 */
1583
1584void pdmLock(PVMCC pVM);
1585int pdmLockEx(PVMCC pVM, int rc);
1586void pdmUnlock(PVMCC pVM);
1587
1588#if defined(IN_RING3) || defined(IN_RING0)
1589void pdmCritSectRwLeaveSharedQueued(PPDMCRITSECTRW pThis);
1590void pdmCritSectRwLeaveExclQueued(PPDMCRITSECTRW pThis);
1591#endif
1592
1593/** @} */
1594
1595RT_C_DECLS_END
1596
1597#endif /* !VMM_INCLUDED_SRC_include_PDMInternal_h */
1598
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