VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PDMInternal.h@ 84459

Last change on this file since 84459 was 84459, checked in by vboxsync, 5 years ago

VMM/PDM: DBGF even tracing integration, bugref:9210

Integrates the new DBGF event tracing framework into PDM
devices. The new CFGM key "TracingEnabled" for a device
instance enables tracing using DBGF. A special tracing variant
of the PDM device helper is provided.

Disabled by default for now, enable with VBOX_WITH_DBGF_TRACING
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 67.8 KB
Line 
1/* $Id: PDMInternal.h 84459 2020-05-22 12:55:07Z vboxsync $ */
2/** @file
3 * PDM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_PDMInternal_h
19#define VMM_INCLUDED_SRC_include_PDMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/types.h>
25#include <VBox/param.h>
26#include <VBox/vmm/cfgm.h>
27#include <VBox/vmm/stam.h>
28#include <VBox/vusb.h>
29#include <VBox/vmm/iom.h>
30#include <VBox/vmm/pdmasynccompletion.h>
31#ifdef VBOX_WITH_NETSHAPER
32# include <VBox/vmm/pdmnetshaper.h>
33#endif
34#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
35# include <VBox/vmm/pdmasynccompletion.h>
36#endif
37#include <VBox/vmm/pdmblkcache.h>
38#include <VBox/vmm/pdmcommon.h>
39#include <VBox/vmm/pdmtask.h>
40#include <VBox/sup.h>
41#include <iprt/assert.h>
42#include <iprt/critsect.h>
43#ifdef IN_RING3
44# include <iprt/thread.h>
45#endif
46
47RT_C_DECLS_BEGIN
48
49
50/** @defgroup grp_pdm_int Internal
51 * @ingroup grp_pdm
52 * @internal
53 * @{
54 */
55
56/** @def PDM_WITH_R3R0_CRIT_SECT
57 * Enables or disabled ring-3/ring-0 critical sections. */
58#if defined(DOXYGEN_RUNNING) || 1
59# define PDM_WITH_R3R0_CRIT_SECT
60#endif
61
62/** @def PDMCRITSECT_STRICT
63 * Enables/disables PDM critsect strictness like deadlock detection. */
64#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECT_STRICT)) \
65 || defined(DOXYGEN_RUNNING)
66# define PDMCRITSECT_STRICT
67#endif
68
69/** @def PDMCRITSECT_STRICT
70 * Enables/disables PDM read/write critsect strictness like deadlock
71 * detection. */
72#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECTRW_STRICT)) \
73 || defined(DOXYGEN_RUNNING)
74# define PDMCRITSECTRW_STRICT
75#endif
76
77/** The maximum device instance (total) size, ring-0/raw-mode capable devices. */
78#define PDM_MAX_DEVICE_INSTANCE_SIZE _4M
79/** The maximum device instance (total) size, ring-3 only devices. */
80#define PDM_MAX_DEVICE_INSTANCE_SIZE_R3 _8M
81/** The maximum size for the DBGF tracing tracking structure allocated for each device. */
82#define PDM_MAX_DEVICE_DBGF_TRACING_TRACK PAGE_SIZE
83
84
85
86/*******************************************************************************
87* Structures and Typedefs *
88*******************************************************************************/
89
90/** Pointer to a PDM Device. */
91typedef struct PDMDEV *PPDMDEV;
92/** Pointer to a pointer to a PDM Device. */
93typedef PPDMDEV *PPPDMDEV;
94
95/** Pointer to a PDM USB Device. */
96typedef struct PDMUSB *PPDMUSB;
97/** Pointer to a pointer to a PDM USB Device. */
98typedef PPDMUSB *PPPDMUSB;
99
100/** Pointer to a PDM Driver. */
101typedef struct PDMDRV *PPDMDRV;
102/** Pointer to a pointer to a PDM Driver. */
103typedef PPDMDRV *PPPDMDRV;
104
105/** Pointer to a PDM Logical Unit. */
106typedef struct PDMLUN *PPDMLUN;
107/** Pointer to a pointer to a PDM Logical Unit. */
108typedef PPDMLUN *PPPDMLUN;
109
110/** Pointer to a PDM PCI Bus instance. */
111typedef struct PDMPCIBUS *PPDMPCIBUS;
112/** Pointer to a PDM IOMMU instance. */
113typedef struct PDMIOMMU *PPDMIOMMU;
114/** Pointer to a DMAC instance. */
115typedef struct PDMDMAC *PPDMDMAC;
116/** Pointer to a RTC instance. */
117typedef struct PDMRTC *PPDMRTC;
118
119/** Pointer to an USB HUB registration record. */
120typedef struct PDMUSBHUB *PPDMUSBHUB;
121
122/**
123 * Supported asynchronous completion endpoint classes.
124 */
125typedef enum PDMASYNCCOMPLETIONEPCLASSTYPE
126{
127 /** File class. */
128 PDMASYNCCOMPLETIONEPCLASSTYPE_FILE = 0,
129 /** Number of supported classes. */
130 PDMASYNCCOMPLETIONEPCLASSTYPE_MAX,
131 /** 32bit hack. */
132 PDMASYNCCOMPLETIONEPCLASSTYPE_32BIT_HACK = 0x7fffffff
133} PDMASYNCCOMPLETIONEPCLASSTYPE;
134
135
136/**
137 * MMIO/IO port registration tracking structure for DBGF tracing.
138 */
139typedef struct PDMDEVINSDBGFTRACK
140{
141 /** Flag whether this tracks a IO port or MMIO registration. */
142 bool fMmio;
143 /** Opaque user data passed during registration. */
144 void *pvUser;
145 /** Type dependent data. */
146 union
147 {
148 /** I/O port registration. */
149 struct
150 {
151 /** IOM I/O port handle. */
152 IOMIOPORTHANDLE hIoPorts;
153 /** Original OUT handler of the device. */
154 PFNIOMIOPORTNEWOUT pfnOut;
155 /** Original IN handler of the device. */
156 PFNIOMIOPORTNEWIN pfnIn;
157 /** Original string OUT handler of the device. */
158 PFNIOMIOPORTNEWOUTSTRING pfnOutStr;
159 /** Original string IN handler of the device. */
160 PFNIOMIOPORTNEWINSTRING pfnInStr;
161 } IoPort;
162 /** MMIO registration. */
163 struct
164 {
165 /** IOM MMIO region handle. */
166 IOMMMIOHANDLE hMmioRegion;
167 /** Original MMIO write handler of the device. */
168 PFNIOMMMIONEWWRITE pfnWrite;
169 /** Original MMIO read handler of the device. */
170 PFNIOMMMIONEWREAD pfnRead;
171 /** Original MMIO fill handler of the device. */
172 PFNIOMMMIONEWFILL pfnFill;
173 } Mmio;
174 } u;
175} PDMDEVINSDBGFTRACK;
176/** Pointer to a MMIO/IO port registration tracking structure. */
177typedef PDMDEVINSDBGFTRACK *PPDMDEVINSDBGFTRACK;
178/** Pointer to a const MMIO/IO port registration tracking structure. */
179typedef const PDMDEVINSDBGFTRACK *PCPDMDEVINSDBGFTRACK;
180
181
182/**
183 * Private device instance data, ring-3.
184 */
185typedef struct PDMDEVINSINTR3
186{
187 /** Pointer to the next instance.
188 * (Head is pointed to by PDM::pDevInstances.) */
189 R3PTRTYPE(PPDMDEVINS) pNextR3;
190 /** Pointer to the next per device instance.
191 * (Head is pointed to by PDMDEV::pInstances.) */
192 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
193 /** Pointer to device structure. */
194 R3PTRTYPE(PPDMDEV) pDevR3;
195 /** Pointer to the list of logical units associated with the device. (FIFO) */
196 R3PTRTYPE(PPDMLUN) pLunsR3;
197 /** Pointer to the asynchronous notification callback set while in
198 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
199 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
200 /** Configuration handle to the instance node. */
201 R3PTRTYPE(PCFGMNODE) pCfgHandle;
202
203 /** R3 pointer to the VM this instance was created for. */
204 PVMR3 pVMR3;
205 /** DBGF trace event source handle if tracing is configured. */
206 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
207 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
208 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
209 /** Index of the next entry to use for tracking. */
210 uint32_t idxDbgfTraceTrackNext;
211 /** Maximum number of records fitting into the single page. */
212 uint32_t cDbgfTraceTrackMax;
213
214 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
215 uint32_t fIntFlags;
216 /** The last IRQ tag (for tracing it thru clearing). */
217 uint32_t uLastIrqTag;
218 /** The ring-0 device index (for making ring-0 calls). */
219 uint32_t idxR0Device;
220} PDMDEVINSINTR3;
221
222
223/**
224 * Private device instance data, ring-0.
225 */
226typedef struct PDMDEVINSINTR0
227{
228 /** Pointer to the VM this instance was created for. */
229 R0PTRTYPE(PGVM) pGVM;
230 /** Pointer to device structure. */
231 R0PTRTYPE(struct PDMDEVREGR0 const *) pRegR0;
232 /** The ring-0 module reference. */
233 RTR0PTR hMod;
234 /** Pointer to the ring-0 mapping of the ring-3 internal data (for uLastIrqTag). */
235 R0PTRTYPE(PDMDEVINSINTR3 *) pIntR3R0;
236 /** Pointer to the ring-0 mapping of the ring-3 instance (for idTracing). */
237 R0PTRTYPE(struct PDMDEVINSR3 *) pInsR3R0;
238 /** DBGF trace event source handle if tracing is configured. */
239 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
240 /** The device instance memory. */
241 RTR0MEMOBJ hMemObj;
242 /** The ring-3 mapping object. */
243 RTR0MEMOBJ hMapObj;
244 /** The page memory object for tracking MMIO and I/O port registrations when tracing is configured. */
245 RTR0MEMOBJ hDbgfTraceObj;
246 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
247 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
248 /** Index of the next entry to use for tracking. */
249 uint32_t idxDbgfTraceTrackNext;
250 /** Maximum number of records fitting into the single page. */
251 uint32_t cDbgfTraceTrackMax;
252 /** Index into PDMR0PERVM::apDevInstances. */
253 uint32_t idxR0Device;
254} PDMDEVINSINTR0;
255
256
257/**
258 * Private device instance data, raw-mode
259 */
260typedef struct PDMDEVINSINTRC
261{
262 /** Pointer to the VM this instance was created for. */
263 RGPTRTYPE(PVM) pVMRC;
264} PDMDEVINSINTRC;
265
266
267/**
268 * Private device instance data.
269 */
270typedef struct PDMDEVINSINT
271{
272 /** Pointer to the next instance (HC Ptr).
273 * (Head is pointed to by PDM::pDevInstances.) */
274 R3PTRTYPE(PPDMDEVINS) pNextR3;
275 /** Pointer to the next per device instance (HC Ptr).
276 * (Head is pointed to by PDMDEV::pInstances.) */
277 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
278 /** Pointer to device structure - HC Ptr. */
279 R3PTRTYPE(PPDMDEV) pDevR3;
280 /** Pointer to the list of logical units associated with the device. (FIFO) */
281 R3PTRTYPE(PPDMLUN) pLunsR3;
282 /** Pointer to the asynchronous notification callback set while in
283 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
284 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
285 /** Configuration handle to the instance node. */
286 R3PTRTYPE(PCFGMNODE) pCfgHandle;
287
288 /** R3 pointer to the VM this instance was created for. */
289 PVMR3 pVMR3;
290
291 /** R0 pointer to the VM this instance was created for. */
292 R0PTRTYPE(PVMCC) pVMR0;
293
294 /** RC pointer to the VM this instance was created for. */
295 PVMRC pVMRC;
296
297 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
298 uint32_t fIntFlags;
299 /** The last IRQ tag (for tracing it thru clearing). */
300 uint32_t uLastIrqTag;
301} PDMDEVINSINT;
302
303/** @name PDMDEVINSINT::fIntFlags
304 * @{ */
305/** Used by pdmR3Load to mark device instances it found in the saved state. */
306#define PDMDEVINSINT_FLAGS_FOUND RT_BIT_32(0)
307/** Indicates that the device hasn't been powered on or resumed.
308 * This is used by PDMR3PowerOn, PDMR3Resume, PDMR3Suspend and PDMR3PowerOff
309 * to make sure each device gets exactly one notification for each of those
310 * events. PDMR3Resume and PDMR3PowerOn also makes use of it to bail out on
311 * a failure (already resumed/powered-on devices are suspended).
312 * PDMR3PowerOff resets this flag once before going through the devices to make sure
313 * every device gets the power off notification even if it was suspended before with
314 * PDMR3Suspend.
315 */
316#define PDMDEVINSINT_FLAGS_SUSPENDED RT_BIT_32(1)
317/** Indicates that the device has been reset already. Used by PDMR3Reset. */
318#define PDMDEVINSINT_FLAGS_RESET RT_BIT_32(2)
319#define PDMDEVINSINT_FLAGS_R0_ENABLED RT_BIT_32(3)
320#define PDMDEVINSINT_FLAGS_RC_ENABLED RT_BIT_32(4)
321/** Set if we've called the ring-0 constructor. */
322#define PDMDEVINSINT_FLAGS_R0_CONTRUCT RT_BIT_32(5)
323/** Set if using non-default critical section. */
324#define PDMDEVINSINT_FLAGS_CHANGED_CRITSECT RT_BIT_32(6)
325/** @} */
326
327
328/**
329 * Private USB device instance data.
330 */
331typedef struct PDMUSBINSINT
332{
333 /** The UUID of this instance. */
334 RTUUID Uuid;
335 /** Pointer to the next instance.
336 * (Head is pointed to by PDM::pUsbInstances.) */
337 R3PTRTYPE(PPDMUSBINS) pNext;
338 /** Pointer to the next per USB device instance.
339 * (Head is pointed to by PDMUSB::pInstances.) */
340 R3PTRTYPE(PPDMUSBINS) pPerDeviceNext;
341
342 /** Pointer to device structure. */
343 R3PTRTYPE(PPDMUSB) pUsbDev;
344
345 /** Pointer to the VM this instance was created for. */
346 PVMR3 pVM;
347 /** Pointer to the list of logical units associated with the device. (FIFO) */
348 R3PTRTYPE(PPDMLUN) pLuns;
349 /** The per instance device configuration. */
350 R3PTRTYPE(PCFGMNODE) pCfg;
351 /** Same as pCfg if the configuration should be deleted when detaching the device. */
352 R3PTRTYPE(PCFGMNODE) pCfgDelete;
353 /** The global device configuration. */
354 R3PTRTYPE(PCFGMNODE) pCfgGlobal;
355
356 /** Pointer to the USB hub this device is attached to.
357 * This is NULL if the device isn't connected to any HUB. */
358 R3PTRTYPE(PPDMUSBHUB) pHub;
359 /** The port number that we're connected to. */
360 uint32_t iPort;
361 /** Indicates that the USB device hasn't been powered on or resumed.
362 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
363 bool fVMSuspended;
364 /** Indicates that the USB device has been reset. */
365 bool fVMReset;
366 /** Pointer to the asynchronous notification callback set while in
367 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
368 R3PTRTYPE(PFNPDMUSBASYNCNOTIFY) pfnAsyncNotify;
369} PDMUSBINSINT;
370
371
372/**
373 * Private driver instance data.
374 */
375typedef struct PDMDRVINSINT
376{
377 /** Pointer to the driver instance above.
378 * This is NULL for the topmost drive. */
379 R3PTRTYPE(PPDMDRVINS) pUp;
380 /** Pointer to the driver instance below.
381 * This is NULL for the bottommost driver. */
382 R3PTRTYPE(PPDMDRVINS) pDown;
383 /** Pointer to the logical unit this driver chained on. */
384 R3PTRTYPE(PPDMLUN) pLun;
385 /** Pointer to driver structure from which this was instantiated. */
386 R3PTRTYPE(PPDMDRV) pDrv;
387 /** Pointer to the VM this instance was created for, ring-3 context. */
388 PVMR3 pVMR3;
389 /** Pointer to the VM this instance was created for, ring-0 context. */
390 R0PTRTYPE(PVMCC) pVMR0;
391 /** Pointer to the VM this instance was created for, raw-mode context. */
392 PVMRC pVMRC;
393 /** Flag indicating that the driver is being detached and destroyed.
394 * (Helps detect potential recursive detaching.) */
395 bool fDetaching;
396 /** Indicates that the driver hasn't been powered on or resumed.
397 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
398 bool fVMSuspended;
399 /** Indicates that the driver has been reset already. */
400 bool fVMReset;
401 /** Set if allocated on the hyper heap, false if on the ring-3 heap. */
402 bool fHyperHeap;
403 /** Pointer to the asynchronous notification callback set while in
404 * PDMUSBREG::pfnVMSuspend or PDMUSBREG::pfnVMPowerOff. */
405 R3PTRTYPE(PFNPDMDRVASYNCNOTIFY) pfnAsyncNotify;
406 /** Configuration handle to the instance node. */
407 R3PTRTYPE(PCFGMNODE) pCfgHandle;
408 /** Pointer to the ring-0 request handler function. */
409 PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
410} PDMDRVINSINT;
411
412
413/**
414 * Private critical section data.
415 */
416typedef struct PDMCRITSECTINT
417{
418 /** The critical section core which is shared with IPRT.
419 * @note The semaphore is a SUPSEMEVENT. */
420 RTCRITSECT Core;
421 /** Pointer to the next critical section.
422 * This chain is used for relocating pVMRC and device cleanup. */
423 R3PTRTYPE(struct PDMCRITSECTINT *) pNext;
424 /** Owner identifier.
425 * This is pDevIns if the owner is a device. Similarly for a driver or service.
426 * PDMR3CritSectInit() sets this to point to the critsect itself. */
427 RTR3PTR pvKey;
428 /** Pointer to the VM - R3Ptr. */
429 PVMR3 pVMR3;
430 /** Pointer to the VM - R0Ptr. */
431 R0PTRTYPE(PVMCC) pVMR0;
432 /** Pointer to the VM - GCPtr. */
433 PVMRC pVMRC;
434 /** Set if this critical section is the automatically created default
435 * section of a device. */
436 bool fAutomaticDefaultCritsect;
437 /** Set if the critical section is used by a timer or similar.
438 * See PDMR3DevGetCritSect. */
439 bool fUsedByTimerOrSimilar;
440 /** Alignment padding. */
441 bool afPadding[2];
442 /** Support driver event semaphore that is scheduled to be signaled upon leaving
443 * the critical section. This is only for Ring-3 and Ring-0. */
444 SUPSEMEVENT hEventToSignal;
445 /** The lock name. */
446 R3PTRTYPE(const char *) pszName;
447 /** R0/RC lock contention. */
448 STAMCOUNTER StatContentionRZLock;
449 /** R0/RC unlock contention. */
450 STAMCOUNTER StatContentionRZUnlock;
451 /** R3 lock contention. */
452 STAMCOUNTER StatContentionR3;
453 /** Profiling the time the section is locked. */
454 STAMPROFILEADV StatLocked;
455} PDMCRITSECTINT;
456AssertCompileMemberAlignment(PDMCRITSECTINT, StatContentionRZLock, 8);
457/** Pointer to private critical section data. */
458typedef PDMCRITSECTINT *PPDMCRITSECTINT;
459
460/** Indicates that the critical section is queued for unlock.
461 * PDMCritSectIsOwner and PDMCritSectIsOwned optimizations. */
462#define PDMCRITSECT_FLAGS_PENDING_UNLOCK RT_BIT_32(17)
463
464
465/**
466 * Private critical section data.
467 */
468typedef struct PDMCRITSECTRWINT
469{
470 /** The read/write critical section core which is shared with IPRT.
471 * @note The semaphores are SUPSEMEVENT and SUPSEMEVENTMULTI. */
472 RTCRITSECTRW Core;
473
474 /** Pointer to the next critical section.
475 * This chain is used for relocating pVMRC and device cleanup. */
476 R3PTRTYPE(struct PDMCRITSECTRWINT *) pNext;
477 /** Owner identifier.
478 * This is pDevIns if the owner is a device. Similarly for a driver or service.
479 * PDMR3CritSectInit() sets this to point to the critsect itself. */
480 RTR3PTR pvKey;
481 /** Pointer to the VM - R3Ptr. */
482 PVMR3 pVMR3;
483 /** Pointer to the VM - R0Ptr. */
484 R0PTRTYPE(PVMCC) pVMR0;
485 /** Pointer to the VM - GCPtr. */
486 PVMRC pVMRC;
487#if HC_ARCH_BITS == 64
488 /** Alignment padding. */
489 RTRCPTR RCPtrPadding;
490#endif
491 /** The lock name. */
492 R3PTRTYPE(const char *) pszName;
493 /** R0/RC write lock contention. */
494 STAMCOUNTER StatContentionRZEnterExcl;
495 /** R0/RC write unlock contention. */
496 STAMCOUNTER StatContentionRZLeaveExcl;
497 /** R0/RC read lock contention. */
498 STAMCOUNTER StatContentionRZEnterShared;
499 /** R0/RC read unlock contention. */
500 STAMCOUNTER StatContentionRZLeaveShared;
501 /** R0/RC writes. */
502 STAMCOUNTER StatRZEnterExcl;
503 /** R0/RC reads. */
504 STAMCOUNTER StatRZEnterShared;
505 /** R3 write lock contention. */
506 STAMCOUNTER StatContentionR3EnterExcl;
507 /** R3 read lock contention. */
508 STAMCOUNTER StatContentionR3EnterShared;
509 /** R3 writes. */
510 STAMCOUNTER StatR3EnterExcl;
511 /** R3 reads. */
512 STAMCOUNTER StatR3EnterShared;
513 /** Profiling the time the section is write locked. */
514 STAMPROFILEADV StatWriteLocked;
515} PDMCRITSECTRWINT;
516AssertCompileMemberAlignment(PDMCRITSECTRWINT, StatContentionRZEnterExcl, 8);
517AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u64State, 8);
518/** Pointer to private critical section data. */
519typedef PDMCRITSECTRWINT *PPDMCRITSECTRWINT;
520
521
522
523/**
524 * The usual device/driver/internal/external stuff.
525 */
526typedef enum
527{
528 /** The usual invalid entry. */
529 PDMTHREADTYPE_INVALID = 0,
530 /** Device type. */
531 PDMTHREADTYPE_DEVICE,
532 /** USB Device type. */
533 PDMTHREADTYPE_USB,
534 /** Driver type. */
535 PDMTHREADTYPE_DRIVER,
536 /** Internal type. */
537 PDMTHREADTYPE_INTERNAL,
538 /** External type. */
539 PDMTHREADTYPE_EXTERNAL,
540 /** The usual 32-bit hack. */
541 PDMTHREADTYPE_32BIT_HACK = 0x7fffffff
542} PDMTHREADTYPE;
543
544
545/**
546 * The internal structure for the thread.
547 */
548typedef struct PDMTHREADINT
549{
550 /** The VM pointer. */
551 PVMR3 pVM;
552 /** The event semaphore the thread blocks on when not running. */
553 RTSEMEVENTMULTI BlockEvent;
554 /** The event semaphore the thread sleeps on while running. */
555 RTSEMEVENTMULTI SleepEvent;
556 /** Pointer to the next thread. */
557 R3PTRTYPE(struct PDMTHREAD *) pNext;
558 /** The thread type. */
559 PDMTHREADTYPE enmType;
560} PDMTHREADINT;
561
562
563
564/* Must be included after PDMDEVINSINT is defined. */
565#define PDMDEVINSINT_DECLARED
566#define PDMUSBINSINT_DECLARED
567#define PDMDRVINSINT_DECLARED
568#define PDMCRITSECTINT_DECLARED
569#define PDMCRITSECTRWINT_DECLARED
570#define PDMTHREADINT_DECLARED
571#ifdef ___VBox_pdm_h
572# error "Invalid header PDM order. Include PDMInternal.h before VBox/vmm/pdm.h!"
573#endif
574RT_C_DECLS_END
575#include <VBox/vmm/pdm.h>
576RT_C_DECLS_BEGIN
577
578/**
579 * PDM Logical Unit.
580 *
581 * This typically the representation of a physical port on a
582 * device, like for instance the PS/2 keyboard port on the
583 * keyboard controller device. The LUNs are chained on the
584 * device they belong to (PDMDEVINSINT::pLunsR3).
585 */
586typedef struct PDMLUN
587{
588 /** The LUN - The Logical Unit Number. */
589 RTUINT iLun;
590 /** Pointer to the next LUN. */
591 PPDMLUN pNext;
592 /** Pointer to the top driver in the driver chain. */
593 PPDMDRVINS pTop;
594 /** Pointer to the bottom driver in the driver chain. */
595 PPDMDRVINS pBottom;
596 /** Pointer to the device instance which the LUN belongs to.
597 * Either this is set or pUsbIns is set. Both is never set at the same time. */
598 PPDMDEVINS pDevIns;
599 /** Pointer to the USB device instance which the LUN belongs to. */
600 PPDMUSBINS pUsbIns;
601 /** Pointer to the device base interface. */
602 PPDMIBASE pBase;
603 /** Description of this LUN. */
604 const char *pszDesc;
605} PDMLUN;
606
607
608/**
609 * PDM Device, ring-3.
610 */
611typedef struct PDMDEV
612{
613 /** Pointer to the next device (R3 Ptr). */
614 R3PTRTYPE(PPDMDEV) pNext;
615 /** Device name length. (search optimization) */
616 uint32_t cchName;
617 /** Registration structure. */
618 R3PTRTYPE(const struct PDMDEVREGR3 *) pReg;
619 /** Number of instances. */
620 uint32_t cInstances;
621 /** Pointer to chain of instances (R3 Ptr). */
622 PPDMDEVINSR3 pInstances;
623 /** The search path for raw-mode context modules (';' as separator). */
624 char *pszRCSearchPath;
625 /** The search path for ring-0 context modules (';' as separator). */
626 char *pszR0SearchPath;
627} PDMDEV;
628
629
630#if 0
631/**
632 * PDM Device, ring-0.
633 */
634typedef struct PDMDEVR0
635{
636 /** Pointer to the next device. */
637 R0PTRTYPE(PPDMDEVR0) pNext;
638 /** Device name length. (search optimization) */
639 uint32_t cchName;
640 /** Registration structure. */
641 R3PTRTYPE(const struct PDMDEVREGR0 *) pReg;
642 /** Number of instances. */
643 uint32_t cInstances;
644 /** Pointer to chain of instances. */
645 PPDMDEVINSR0 pInstances;
646} PDMDEVR0;
647#endif
648
649
650/**
651 * PDM USB Device.
652 */
653typedef struct PDMUSB
654{
655 /** Pointer to the next device (R3 Ptr). */
656 R3PTRTYPE(PPDMUSB) pNext;
657 /** Device name length. (search optimization) */
658 RTUINT cchName;
659 /** Registration structure. */
660 R3PTRTYPE(const struct PDMUSBREG *) pReg;
661 /** Next instance number. */
662 uint32_t iNextInstance;
663 /** Pointer to chain of instances (R3 Ptr). */
664 R3PTRTYPE(PPDMUSBINS) pInstances;
665} PDMUSB;
666
667
668/**
669 * PDM Driver.
670 */
671typedef struct PDMDRV
672{
673 /** Pointer to the next device. */
674 PPDMDRV pNext;
675 /** Registration structure. */
676 const struct PDMDRVREG * pReg;
677 /** Current number of instances. */
678 uint32_t cInstances;
679 /** The next instance number. */
680 uint32_t iNextInstance;
681 /** The search path for raw-mode context modules (';' as separator). */
682 char *pszRCSearchPath;
683 /** The search path for ring-0 context modules (';' as separator). */
684 char *pszR0SearchPath;
685} PDMDRV;
686
687
688/**
689 * PDM registered IOMMU device.
690 */
691typedef struct PDMIOMMU
692{
693 /** IOMMU index. */
694 uint32_t idxIommu;
695 uint32_t uPadding0; /**< Alignment padding.*/
696
697 /** Pointer to the IOMMU device instance - R3. */
698 PPDMDEVINSR3 pDevInsR3;
699 /** @copydoc PDMIOMMUREGR3::pfnMemRead */
700 DECLR3CALLBACKMEMBER(int, pfnMemRead,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbRead,
701 PRTGCPHYS pGCPhysSpa));
702 /** @copydoc PDMIOMMUREGR3::pfnMemWrite */
703 DECLR3CALLBACKMEMBER(int, pfnMemWrite,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbWrite,
704 PRTGCPHYS pGCPhysSpa));
705 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
706 DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevId, RTGCPHYS GCPhysIn, uint32_t uDataIn,
707 PRTGCPHYS pGCPhysOut, uint32_t *puDataOut));
708} PDMIOMMU;
709
710
711/**
712 * Ring-0 PDM IOMMU instance data.
713 */
714typedef struct PDMIOMMUR0
715{
716 /** IOMMU index. */
717 uint32_t idxIommu;
718 uint32_t uPadding0; /**< Alignment padding.*/
719
720 /** Pointer to IOMMU device instance. */
721 PPDMDEVINSR0 pDevInsR0;
722 /** @copydoc PDMIOMMUREGR0::pfnMemRead */
723 DECLR0CALLBACKMEMBER(int, pfnMemRead,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbRead,
724 PRTGCPHYS pGCPhysSpa));
725 /** @copydoc PDMIOMMUREGR3::pfnMemWrite */
726 DECLR0CALLBACKMEMBER(int, pfnMemWrite,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbWrite,
727 PRTGCPHYS pGCPhysSpa));
728 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
729 DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevId, RTGCPHYS GCPhysIn, uint32_t uDataIn,
730 PRTGCPHYS pGCPhysOut, uint32_t *puDataOut));
731} PDMIOMMUR0;
732/** Pointer to a ring-0 IOMMU data. */
733typedef PDMIOMMUR0 *PPDMIOMMUR0;
734/** Pointer to a const ring-0 IOMMU data. */
735typedef const PDMIOMMUR0 *PCPDMIOMMUR0;
736
737
738/**
739 * PDM registered PIC device.
740 */
741typedef struct PDMPIC
742{
743 /** Pointer to the PIC device instance - R3. */
744 PPDMDEVINSR3 pDevInsR3;
745 /** @copydoc PDMPICREG::pfnSetIrq */
746 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
747 /** @copydoc PDMPICREG::pfnGetInterrupt */
748 DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
749
750 /** Pointer to the PIC device instance - R0. */
751 PPDMDEVINSR0 pDevInsR0;
752 /** @copydoc PDMPICREG::pfnSetIrq */
753 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
754 /** @copydoc PDMPICREG::pfnGetInterrupt */
755 DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
756
757 /** Pointer to the PIC device instance - RC. */
758 PPDMDEVINSRC pDevInsRC;
759 /** @copydoc PDMPICREG::pfnSetIrq */
760 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
761 /** @copydoc PDMPICREG::pfnGetInterrupt */
762 DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
763 /** Alignment padding. */
764 RTRCPTR RCPtrPadding;
765} PDMPIC;
766
767
768/**
769 * PDM registered APIC device.
770 */
771typedef struct PDMAPIC
772{
773 /** Pointer to the APIC device instance - R3 Ptr. */
774 PPDMDEVINSR3 pDevInsR3;
775 /** Pointer to the APIC device instance - R0 Ptr. */
776 PPDMDEVINSR0 pDevInsR0;
777 /** Pointer to the APIC device instance - RC Ptr. */
778 PPDMDEVINSRC pDevInsRC;
779 uint8_t Alignment[4];
780} PDMAPIC;
781
782
783/**
784 * PDM registered I/O APIC device.
785 */
786typedef struct PDMIOAPIC
787{
788 /** Pointer to the APIC device instance - R3 Ptr. */
789 PPDMDEVINSR3 pDevInsR3;
790 /** @copydoc PDMIOAPICREG::pfnSetIrq */
791 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
792 /** @copydoc PDMIOAPICREG::pfnSendMsi */
793 DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc));
794 /** @copydoc PDMIOAPICREG::pfnSetEoi */
795 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
796
797 /** Pointer to the PIC device instance - R0. */
798 PPDMDEVINSR0 pDevInsR0;
799 /** @copydoc PDMIOAPICREG::pfnSetIrq */
800 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
801 /** @copydoc PDMIOAPICREG::pfnSendMsi */
802 DECLR0CALLBACKMEMBER(void, pfnSendMsiR0,(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc));
803 /** @copydoc PDMIOAPICREG::pfnSetEoi */
804 DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiR0,(PPDMDEVINS pDevIns, uint8_t u8Vector));
805
806 /** Pointer to the APIC device instance - RC Ptr. */
807 PPDMDEVINSRC pDevInsRC;
808 /** @copydoc PDMIOAPICREG::pfnSetIrq */
809 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
810 /** @copydoc PDMIOAPICREG::pfnSendMsi */
811 DECLRCCALLBACKMEMBER(void, pfnSendMsiRC,(PPDMDEVINS pDevIns, RTGCPHYS GCAddr, uint32_t uValue, uint32_t uTagSrc));
812 /** @copydoc PDMIOAPICREG::pfnSendMsi */
813 DECLRCCALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiRC,(PPDMDEVINS pDevIns, uint8_t u8Vector));
814} PDMIOAPIC;
815
816/** Maximum number of PCI busses for a VM. */
817#define PDM_PCI_BUSSES_MAX 8
818/** Maximum number of IOMMUs (at most one per PCI bus). */
819#define PDM_IOMMUS_MAX PDM_PCI_BUSSES_MAX
820
821
822#ifdef IN_RING3
823/**
824 * PDM registered firmware device.
825 */
826typedef struct PDMFW
827{
828 /** Pointer to the firmware device instance. */
829 PPDMDEVINSR3 pDevIns;
830 /** Copy of the registration structure. */
831 PDMFWREG Reg;
832} PDMFW;
833/** Pointer to a firmware instance. */
834typedef PDMFW *PPDMFW;
835#endif
836
837
838/**
839 * PDM PCI bus instance.
840 */
841typedef struct PDMPCIBUS
842{
843 /** PCI bus number. */
844 uint32_t iBus;
845 uint32_t uPadding0; /**< Alignment padding.*/
846
847 /** Pointer to PCI bus device instance. */
848 PPDMDEVINSR3 pDevInsR3;
849 /** @copydoc PDMPCIBUSREGR3::pfnSetIrqR3 */
850 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
851
852 /** @copydoc PDMPCIBUSREGR3::pfnRegisterR3 */
853 DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
854 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
855 /** @copydoc PDMPCIBUSREGR3::pfnRegisterMsiR3 */
856 DECLR3CALLBACKMEMBER(int, pfnRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
857 /** @copydoc PDMPCIBUSREGR3::pfnIORegionRegisterR3 */
858 DECLR3CALLBACKMEMBER(int, pfnIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
859 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
860 uint64_t hHandle, PFNPCIIOREGIONMAP pfnCallback));
861 /** @copydoc PDMPCIBUSREGR3::pfnInterceptConfigAccesses */
862 DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
863 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
864 /** @copydoc PDMPCIBUSREGR3::pfnConfigWrite */
865 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
866 uint32_t uAddress, unsigned cb, uint32_t u32Value));
867 /** @copydoc PDMPCIBUSREGR3::pfnConfigRead */
868 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
869 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
870} PDMPCIBUS;
871
872
873/**
874 * Ring-0 PDM PCI bus instance data.
875 */
876typedef struct PDMPCIBUSR0
877{
878 /** PCI bus number. */
879 uint32_t iBus;
880 uint32_t uPadding0; /**< Alignment padding.*/
881 /** Pointer to PCI bus device instance. */
882 PPDMDEVINSR0 pDevInsR0;
883 /** @copydoc PDMPCIBUSREGR0::pfnSetIrq */
884 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
885} PDMPCIBUSR0;
886/** Pointer to the ring-0 PCI bus data. */
887typedef PDMPCIBUSR0 *PPDMPCIBUSR0;
888
889
890#ifdef IN_RING3
891/**
892 * PDM registered DMAC (DMA Controller) device.
893 */
894typedef struct PDMDMAC
895{
896 /** Pointer to the DMAC device instance. */
897 PPDMDEVINSR3 pDevIns;
898 /** Copy of the registration structure. */
899 PDMDMACREG Reg;
900} PDMDMAC;
901
902
903/**
904 * PDM registered RTC (Real Time Clock) device.
905 */
906typedef struct PDMRTC
907{
908 /** Pointer to the RTC device instance. */
909 PPDMDEVINSR3 pDevIns;
910 /** Copy of the registration structure. */
911 PDMRTCREG Reg;
912} PDMRTC;
913
914#endif /* IN_RING3 */
915
916/**
917 * Module type.
918 */
919typedef enum PDMMODTYPE
920{
921 /** Raw-mode (RC) context module. */
922 PDMMOD_TYPE_RC,
923 /** Ring-0 (host) context module. */
924 PDMMOD_TYPE_R0,
925 /** Ring-3 (host) context module. */
926 PDMMOD_TYPE_R3
927} PDMMODTYPE;
928
929
930/** The module name length including the terminator. */
931#define PDMMOD_NAME_LEN 32
932
933/**
934 * Loaded module instance.
935 */
936typedef struct PDMMOD
937{
938 /** Module name. This is used for referring to
939 * the module internally, sort of like a handle. */
940 char szName[PDMMOD_NAME_LEN];
941 /** Module type. */
942 PDMMODTYPE eType;
943 /** Loader module handle. Not used for R0 modules. */
944 RTLDRMOD hLdrMod;
945 /** Loaded address.
946 * This is the 'handle' for R0 modules. */
947 RTUINTPTR ImageBase;
948 /** Old loaded address.
949 * This is used during relocation of GC modules. Not used for R0 modules. */
950 RTUINTPTR OldImageBase;
951 /** Where the R3 HC bits are stored.
952 * This can be equal to ImageBase but doesn't have to. Not used for R0 modules. */
953 void *pvBits;
954
955 /** Pointer to next module. */
956 struct PDMMOD *pNext;
957 /** Module filename. */
958 char szFilename[1];
959} PDMMOD;
960/** Pointer to loaded module instance. */
961typedef PDMMOD *PPDMMOD;
962
963
964
965/** Extra space in the free array. */
966#define PDMQUEUE_FREE_SLACK 16
967
968/**
969 * Queue type.
970 */
971typedef enum PDMQUEUETYPE
972{
973 /** Device consumer. */
974 PDMQUEUETYPE_DEV = 1,
975 /** Driver consumer. */
976 PDMQUEUETYPE_DRV,
977 /** Internal consumer. */
978 PDMQUEUETYPE_INTERNAL,
979 /** External consumer. */
980 PDMQUEUETYPE_EXTERNAL
981} PDMQUEUETYPE;
982
983/** Pointer to a PDM Queue. */
984typedef struct PDMQUEUE *PPDMQUEUE;
985
986/**
987 * PDM Queue.
988 */
989typedef struct PDMQUEUE
990{
991 /** Pointer to the next queue in the list. */
992 R3PTRTYPE(PPDMQUEUE) pNext;
993 /** Type specific data. */
994 union
995 {
996 /** PDMQUEUETYPE_DEV */
997 struct
998 {
999 /** Pointer to consumer function. */
1000 R3PTRTYPE(PFNPDMQUEUEDEV) pfnCallback;
1001 /** Pointer to the device instance owning the queue. */
1002 R3PTRTYPE(PPDMDEVINS) pDevIns;
1003 } Dev;
1004 /** PDMQUEUETYPE_DRV */
1005 struct
1006 {
1007 /** Pointer to consumer function. */
1008 R3PTRTYPE(PFNPDMQUEUEDRV) pfnCallback;
1009 /** Pointer to the driver instance owning the queue. */
1010 R3PTRTYPE(PPDMDRVINS) pDrvIns;
1011 } Drv;
1012 /** PDMQUEUETYPE_INTERNAL */
1013 struct
1014 {
1015 /** Pointer to consumer function. */
1016 R3PTRTYPE(PFNPDMQUEUEINT) pfnCallback;
1017 } Int;
1018 /** PDMQUEUETYPE_EXTERNAL */
1019 struct
1020 {
1021 /** Pointer to consumer function. */
1022 R3PTRTYPE(PFNPDMQUEUEEXT) pfnCallback;
1023 /** Pointer to user argument. */
1024 R3PTRTYPE(void *) pvUser;
1025 } Ext;
1026 } u;
1027 /** Queue type. */
1028 PDMQUEUETYPE enmType;
1029 /** The interval between checking the queue for events.
1030 * The realtime timer below is used to do the waiting.
1031 * If 0, the queue will use the VM_FF_PDM_QUEUE forced action. */
1032 uint32_t cMilliesInterval;
1033 /** Interval timer. Only used if cMilliesInterval is non-zero. */
1034 PTMTIMERR3 pTimer;
1035 /** Pointer to the VM - R3. */
1036 PVMR3 pVMR3;
1037 /** LIFO of pending items - R3. */
1038 R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR3;
1039 /** Pointer to the VM - R0. */
1040 PVMR0 pVMR0;
1041 /** LIFO of pending items - R0. */
1042 R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR0;
1043 /** Pointer to the GC VM and indicator for GC enabled queue.
1044 * If this is NULL, the queue cannot be used in GC.
1045 */
1046 PVMRC pVMRC;
1047 /** LIFO of pending items - GC. */
1048 RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingRC;
1049
1050 /** Item size (bytes). */
1051 uint32_t cbItem;
1052 /** Number of items in the queue. */
1053 uint32_t cItems;
1054 /** Index to the free head (where we insert). */
1055 uint32_t volatile iFreeHead;
1056 /** Index to the free tail (where we remove). */
1057 uint32_t volatile iFreeTail;
1058
1059 /** Unique queue name. */
1060 R3PTRTYPE(const char *) pszName;
1061#if HC_ARCH_BITS == 32
1062 RTR3PTR Alignment1;
1063#endif
1064 /** Stat: Times PDMQueueAlloc fails. */
1065 STAMCOUNTER StatAllocFailures;
1066 /** Stat: PDMQueueInsert calls. */
1067 STAMCOUNTER StatInsert;
1068 /** Stat: Queue flushes. */
1069 STAMCOUNTER StatFlush;
1070 /** Stat: Queue flushes with pending items left over. */
1071 STAMCOUNTER StatFlushLeftovers;
1072#ifdef VBOX_WITH_STATISTICS
1073 /** State: Profiling the flushing. */
1074 STAMPROFILE StatFlushPrf;
1075 /** State: Pending items. */
1076 uint32_t volatile cStatPending;
1077 uint32_t volatile cAlignment;
1078#endif
1079
1080 /** Array of pointers to free items. Variable size. */
1081 struct PDMQUEUEFREEITEM
1082 {
1083 /** Pointer to the free item - HC Ptr. */
1084 R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR3;
1085 /** Pointer to the free item - HC Ptr. */
1086 R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR0;
1087 /** Pointer to the free item - GC Ptr. */
1088 RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pItemRC;
1089#if HC_ARCH_BITS == 64
1090 RTRCPTR Alignment0;
1091#endif
1092 } aFreeItems[1];
1093} PDMQUEUE;
1094
1095/** @name PDM::fQueueFlushing
1096 * @{ */
1097/** Used to make sure only one EMT will flush the queues.
1098 * Set when an EMT is flushing queues, clear otherwise. */
1099#define PDM_QUEUE_FLUSH_FLAG_ACTIVE_BIT 0
1100/** Indicating there are queues with items pending.
1101 * This is make sure we don't miss inserts happening during flushing. The FF
1102 * cannot be used for this since it has to be cleared immediately to prevent
1103 * other EMTs from spinning. */
1104#define PDM_QUEUE_FLUSH_FLAG_PENDING_BIT 1
1105/** @} */
1106
1107
1108/** @name PDM task structures.
1109 * @{ */
1110
1111/**
1112 * A asynchronous user mode task.
1113 */
1114typedef struct PDMTASK
1115{
1116 /** Task owner type. */
1117 PDMTASKTYPE volatile enmType;
1118 /** Queue flags. */
1119 uint32_t volatile fFlags;
1120 /** User argument for the callback. */
1121 R3PTRTYPE(void *) volatile pvUser;
1122 /** The callback (will be cast according to enmType before callout). */
1123 R3PTRTYPE(PFNRT) volatile pfnCallback;
1124 /** The owner identifier. */
1125 R3PTRTYPE(void *) volatile pvOwner;
1126 /** Task name. */
1127 R3PTRTYPE(const char *) pszName;
1128 /** Number of times already triggered when PDMTaskTrigger was called. */
1129 uint32_t volatile cAlreadyTrigged;
1130 /** Number of runs. */
1131 uint32_t cRuns;
1132} PDMTASK;
1133/** Pointer to a PDM task. */
1134typedef PDMTASK *PPDMTASK;
1135
1136/**
1137 * A task set.
1138 *
1139 * This is served by one task executor thread.
1140 */
1141typedef struct PDMTASKSET
1142{
1143 /** Magic value (PDMTASKSET_MAGIC). */
1144 uint32_t u32Magic;
1145 /** Set if this task set works for ring-0 and raw-mode. */
1146 bool fRZEnabled;
1147 /** Number of allocated taks. */
1148 uint8_t volatile cAllocated;
1149 /** Base handle value for this set. */
1150 uint16_t uHandleBase;
1151 /** The task executor thread. */
1152 R3PTRTYPE(RTTHREAD) hThread;
1153 /** Event semaphore for waking up the thread when fRZEnabled is set. */
1154 SUPSEMEVENT hEventR0;
1155 /** Event semaphore for waking up the thread when fRZEnabled is clear. */
1156 R3PTRTYPE(RTSEMEVENT) hEventR3;
1157 /** The VM pointer. */
1158 PVM pVM;
1159 /** Padding so fTriggered is in its own cacheline. */
1160 uint64_t au64Padding2[3];
1161
1162 /** Bitmask of triggered tasks. */
1163 uint64_t volatile fTriggered;
1164 /** Shutdown thread indicator. */
1165 bool volatile fShutdown;
1166 /** Padding. */
1167 bool volatile afPadding3[3];
1168 /** Task currently running, UINT32_MAX if idle. */
1169 uint32_t volatile idxRunning;
1170 /** Padding so fTriggered and fShutdown are in their own cacheline. */
1171 uint64_t volatile au64Padding3[6];
1172
1173 /** The individual tasks. (Unallocated tasks have NULL pvOwner.) */
1174 PDMTASK aTasks[64];
1175} PDMTASKSET;
1176AssertCompileMemberAlignment(PDMTASKSET, fTriggered, 64);
1177AssertCompileMemberAlignment(PDMTASKSET, aTasks, 64);
1178/** Magic value for PDMTASKSET::u32Magic. */
1179#define PDMTASKSET_MAGIC UINT32_C(0x19320314)
1180/** Pointer to a task set. */
1181typedef PDMTASKSET *PPDMTASKSET;
1182
1183/** @} */
1184
1185
1186/**
1187 * Queue device helper task operation.
1188 */
1189typedef enum PDMDEVHLPTASKOP
1190{
1191 /** The usual invalid 0 entry. */
1192 PDMDEVHLPTASKOP_INVALID = 0,
1193 /** ISASetIrq */
1194 PDMDEVHLPTASKOP_ISA_SET_IRQ,
1195 /** PCISetIrq */
1196 PDMDEVHLPTASKOP_PCI_SET_IRQ,
1197 /** PCISetIrq */
1198 PDMDEVHLPTASKOP_IOAPIC_SET_IRQ,
1199 /** The usual 32-bit hack. */
1200 PDMDEVHLPTASKOP_32BIT_HACK = 0x7fffffff
1201} PDMDEVHLPTASKOP;
1202
1203/**
1204 * Queued Device Helper Task.
1205 */
1206typedef struct PDMDEVHLPTASK
1207{
1208 /** The queue item core (don't touch). */
1209 PDMQUEUEITEMCORE Core;
1210 /** Pointer to the device instance (R3 Ptr). */
1211 PPDMDEVINSR3 pDevInsR3;
1212 /** This operation to perform. */
1213 PDMDEVHLPTASKOP enmOp;
1214#if HC_ARCH_BITS == 64
1215 uint32_t Alignment0;
1216#endif
1217 /** Parameters to the operation. */
1218 union PDMDEVHLPTASKPARAMS
1219 {
1220 /**
1221 * PDMDEVHLPTASKOP_ISA_SET_IRQ and PDMDEVHLPTASKOP_IOAPIC_SET_IRQ.
1222 */
1223 struct PDMDEVHLPTASKISASETIRQ
1224 {
1225 /** The IRQ */
1226 int iIrq;
1227 /** The new level. */
1228 int iLevel;
1229 /** The IRQ tag and source. */
1230 uint32_t uTagSrc;
1231 } IsaSetIRQ, IoApicSetIRQ;
1232
1233 /**
1234 * PDMDEVHLPTASKOP_PCI_SET_IRQ
1235 */
1236 struct PDMDEVHLPTASKPCISETIRQ
1237 {
1238 /** Pointer to the PCI device (R3 Ptr). */
1239 R3PTRTYPE(PPDMPCIDEV) pPciDevR3;
1240 /** The IRQ */
1241 int iIrq;
1242 /** The new level. */
1243 int iLevel;
1244 /** The IRQ tag and source. */
1245 uint32_t uTagSrc;
1246 } PciSetIRQ;
1247
1248 /** Expanding the structure. */
1249 uint64_t au64[3];
1250 } u;
1251} PDMDEVHLPTASK;
1252/** Pointer to a queued Device Helper Task. */
1253typedef PDMDEVHLPTASK *PPDMDEVHLPTASK;
1254/** Pointer to a const queued Device Helper Task. */
1255typedef const PDMDEVHLPTASK *PCPDMDEVHLPTASK;
1256
1257
1258
1259/**
1260 * An USB hub registration record.
1261 */
1262typedef struct PDMUSBHUB
1263{
1264 /** The USB versions this hub support.
1265 * Note that 1.1 hubs can take on 2.0 devices. */
1266 uint32_t fVersions;
1267 /** The number of ports on the hub. */
1268 uint32_t cPorts;
1269 /** The number of available ports (0..cPorts). */
1270 uint32_t cAvailablePorts;
1271 /** The driver instance of the hub. */
1272 PPDMDRVINS pDrvIns;
1273 /** Copy of the to the registration structure. */
1274 PDMUSBHUBREG Reg;
1275
1276 /** Pointer to the next hub in the list. */
1277 struct PDMUSBHUB *pNext;
1278} PDMUSBHUB;
1279
1280/** Pointer to a const USB HUB registration record. */
1281typedef const PDMUSBHUB *PCPDMUSBHUB;
1282
1283/** Pointer to a PDM Async I/O template. */
1284typedef struct PDMASYNCCOMPLETIONTEMPLATE *PPDMASYNCCOMPLETIONTEMPLATE;
1285
1286/** Pointer to the main PDM Async completion endpoint class. */
1287typedef struct PDMASYNCCOMPLETIONEPCLASS *PPDMASYNCCOMPLETIONEPCLASS;
1288
1289/** Pointer to the global block cache structure. */
1290typedef struct PDMBLKCACHEGLOBAL *PPDMBLKCACHEGLOBAL;
1291
1292/**
1293 * PDM VMCPU Instance data.
1294 * Changes to this must checked against the padding of the pdm union in VMCPU!
1295 */
1296typedef struct PDMCPU
1297{
1298 /** The number of entries in the apQueuedCritSectsLeaves table that's currently
1299 * in use. */
1300 uint32_t cQueuedCritSectLeaves;
1301 uint32_t uPadding0; /**< Alignment padding.*/
1302 /** Critical sections queued in RC/R0 because of contention preventing leave to
1303 * complete. (R3 Ptrs)
1304 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1305 R3PTRTYPE(PPDMCRITSECT) apQueuedCritSectLeaves[8];
1306
1307 /** The number of entries in the apQueuedCritSectRwExclLeaves table that's
1308 * currently in use. */
1309 uint32_t cQueuedCritSectRwExclLeaves;
1310 uint32_t uPadding1; /**< Alignment padding.*/
1311 /** Read/write critical sections queued in RC/R0 because of contention
1312 * preventing exclusive leave to complete. (R3 Ptrs)
1313 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1314 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwExclLeaves[8];
1315
1316 /** The number of entries in the apQueuedCritSectsRwShrdLeaves table that's
1317 * currently in use. */
1318 uint32_t cQueuedCritSectRwShrdLeaves;
1319 uint32_t uPadding2; /**< Alignment padding.*/
1320 /** Read/write critical sections queued in RC/R0 because of contention
1321 * preventing shared leave to complete. (R3 Ptrs)
1322 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1323 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwShrdLeaves[8];
1324} PDMCPU;
1325
1326
1327/**
1328 * PDM VM Instance data.
1329 * Changes to this must checked against the padding of the cfgm union in VM!
1330 */
1331typedef struct PDM
1332{
1333 /** The PDM lock.
1334 * This is used to protect everything that deals with interrupts, i.e.
1335 * the PIC, APIC, IOAPIC and PCI devices plus some PDM functions. */
1336 PDMCRITSECT CritSect;
1337 /** The NOP critical section.
1338 * This is a dummy critical section that will not do any thread
1339 * serialization but instead let all threads enter immediately and
1340 * concurrently. */
1341 PDMCRITSECT NopCritSect;
1342
1343 /** The ring-0 capable task sets (max 128). */
1344 PDMTASKSET aTaskSets[2];
1345 /** Pointer to task sets (max 512). */
1346 R3PTRTYPE(PPDMTASKSET) apTaskSets[8];
1347
1348 /** PCI Buses. */
1349 PDMPCIBUS aPciBuses[PDM_PCI_BUSSES_MAX];
1350 /** IOMMU devices. */
1351 PDMIOMMU aIommus[PDM_IOMMUS_MAX];
1352 /** The register PIC device. */
1353 PDMPIC Pic;
1354 /** The registered APIC device. */
1355 PDMAPIC Apic;
1356 /** The registered I/O APIC device. */
1357 PDMIOAPIC IoApic;
1358 /** The registered HPET device. */
1359 PPDMDEVINSR3 pHpet;
1360
1361 /** List of registered devices. (FIFO) */
1362 R3PTRTYPE(PPDMDEV) pDevs;
1363 /** List of devices instances. (FIFO) */
1364 R3PTRTYPE(PPDMDEVINS) pDevInstances;
1365 /** List of registered USB devices. (FIFO) */
1366 R3PTRTYPE(PPDMUSB) pUsbDevs;
1367 /** List of USB devices instances. (FIFO) */
1368 R3PTRTYPE(PPDMUSBINS) pUsbInstances;
1369 /** List of registered drivers. (FIFO) */
1370 R3PTRTYPE(PPDMDRV) pDrvs;
1371 /** The registered firmware device (can be NULL). */
1372 R3PTRTYPE(PPDMFW) pFirmware;
1373 /** The registered DMAC device. */
1374 R3PTRTYPE(PPDMDMAC) pDmac;
1375 /** The registered RTC device. */
1376 R3PTRTYPE(PPDMRTC) pRtc;
1377 /** The registered USB HUBs. (FIFO) */
1378 R3PTRTYPE(PPDMUSBHUB) pUsbHubs;
1379
1380 /** @name Queues
1381 * @{ */
1382 /** Queue in which devhlp tasks are queued for R3 execution - R3 Ptr. */
1383 R3PTRTYPE(PPDMQUEUE) pDevHlpQueueR3;
1384 /** Queue in which devhlp tasks are queued for R3 execution - R0 Ptr. */
1385 R0PTRTYPE(PPDMQUEUE) pDevHlpQueueR0;
1386 /** Queue in which devhlp tasks are queued for R3 execution - RC Ptr. */
1387 RCPTRTYPE(PPDMQUEUE) pDevHlpQueueRC;
1388 /** Pointer to the queue which should be manually flushed - RC Ptr.
1389 * Only touched by EMT. */
1390 RCPTRTYPE(struct PDMQUEUE *) pQueueFlushRC;
1391 /** Pointer to the queue which should be manually flushed - R0 Ptr.
1392 * Only touched by EMT. */
1393 R0PTRTYPE(struct PDMQUEUE *) pQueueFlushR0;
1394 /** Bitmask controlling the queue flushing.
1395 * See PDM_QUEUE_FLUSH_FLAG_ACTIVE and PDM_QUEUE_FLUSH_FLAG_PENDING. */
1396 uint32_t volatile fQueueFlushing;
1397 /** @} */
1398
1399 /** The current IRQ tag (tracing purposes). */
1400 uint32_t volatile uIrqTag;
1401
1402 /** Pending reset flags (PDMVMRESET_F_XXX). */
1403 uint32_t volatile fResetFlags;
1404
1405 /** Set by pdmR3LoadExec for use in assertions. */
1406 bool fStateLoaded;
1407 /** Alignment padding. */
1408 bool afPadding[3];
1409
1410 /** The tracing ID of the next device instance.
1411 *
1412 * @remarks We keep the device tracing ID seperate from the rest as these are
1413 * then more likely to end up with the same ID from one run to
1414 * another, making analysis somewhat easier. Drivers and USB devices
1415 * are more volatile and can be changed at runtime, thus these are much
1416 * less likely to remain stable, so just heap them all together. */
1417 uint32_t idTracingDev;
1418 /** The tracing ID of the next driver instance, USB device instance or other
1419 * PDM entity requiring an ID. */
1420 uint32_t idTracingOther;
1421
1422 /** @name VMM device heap
1423 * @{ */
1424 /** The heap size. */
1425 uint32_t cbVMMDevHeap;
1426 /** Free space. */
1427 uint32_t cbVMMDevHeapLeft;
1428 /** Pointer to the heap base (MMIO2 ring-3 mapping). NULL if not registered. */
1429 RTR3PTR pvVMMDevHeap;
1430 /** Ring-3 mapping/unmapping notification callback for the user. */
1431 PFNPDMVMMDEVHEAPNOTIFY pfnVMMDevHeapNotify;
1432 /** The current mapping. NIL_RTGCPHYS if not mapped or registered. */
1433 RTGCPHYS GCPhysVMMDevHeap;
1434 /** @} */
1435
1436 /** Number of times a critical section leave request needed to be queued for ring-3 execution. */
1437 STAMCOUNTER StatQueuedCritSectLeaves;
1438} PDM;
1439AssertCompileMemberAlignment(PDM, CritSect, 8);
1440AssertCompileMemberAlignment(PDM, aTaskSets, 64);
1441AssertCompileMemberAlignment(PDM, StatQueuedCritSectLeaves, 8);
1442AssertCompileMemberAlignment(PDM, GCPhysVMMDevHeap, sizeof(RTGCPHYS));
1443/** Pointer to PDM VM instance data. */
1444typedef PDM *PPDM;
1445
1446
1447/**
1448 * PDM data kept in the ring-0 GVM.
1449 */
1450typedef struct PDMR0PERVM
1451{
1452 /** PCI Buses, ring-0 data. */
1453 PDMPCIBUSR0 aPciBuses[PDM_PCI_BUSSES_MAX];
1454 /** IOMMUs, ring-0 data. */
1455 PDMIOMMUR0 aIommus[PDM_IOMMUS_MAX];
1456 /** Number of valid ring-0 device instances (apDevInstances). */
1457 uint32_t cDevInstances;
1458 uint32_t u32Padding;
1459 /** Pointer to ring-0 device instances. */
1460 R0PTRTYPE(struct PDMDEVINSR0 *) apDevInstances[190];
1461} PDMR0PERVM;
1462
1463
1464/**
1465 * PDM data kept in the UVM.
1466 */
1467typedef struct PDMUSERPERVM
1468{
1469 /** @todo move more stuff over here. */
1470
1471 /** Linked list of timer driven PDM queues.
1472 * Currently serialized by PDM::CritSect. */
1473 R3PTRTYPE(struct PDMQUEUE *) pQueuesTimer;
1474 /** Linked list of force action driven PDM queues.
1475 * Currently serialized by PDM::CritSect. */
1476 R3PTRTYPE(struct PDMQUEUE *) pQueuesForced;
1477
1478 /** Lock protecting the lists below it. */
1479 RTCRITSECT ListCritSect;
1480 /** Pointer to list of loaded modules. */
1481 PPDMMOD pModules;
1482 /** List of initialized critical sections. (LIFO) */
1483 R3PTRTYPE(PPDMCRITSECTINT) pCritSects;
1484 /** List of initialized read/write critical sections. (LIFO) */
1485 R3PTRTYPE(PPDMCRITSECTRWINT) pRwCritSects;
1486 /** Head of the PDM Thread list. (singly linked) */
1487 R3PTRTYPE(PPDMTHREAD) pThreads;
1488 /** Tail of the PDM Thread list. (singly linked) */
1489 R3PTRTYPE(PPDMTHREAD) pThreadsTail;
1490
1491 /** @name PDM Async Completion
1492 * @{ */
1493 /** Pointer to the array of supported endpoint classes. */
1494 PPDMASYNCCOMPLETIONEPCLASS apAsyncCompletionEndpointClass[PDMASYNCCOMPLETIONEPCLASSTYPE_MAX];
1495 /** Head of the templates. Singly linked, protected by ListCritSect. */
1496 R3PTRTYPE(PPDMASYNCCOMPLETIONTEMPLATE) pAsyncCompletionTemplates;
1497 /** @} */
1498
1499 /** Global block cache data. */
1500 R3PTRTYPE(PPDMBLKCACHEGLOBAL) pBlkCacheGlobal;
1501#ifdef VBOX_WITH_NETSHAPER
1502 /** Pointer to network shaper instance. */
1503 R3PTRTYPE(PPDMNETSHAPER) pNetShaper;
1504#endif /* VBOX_WITH_NETSHAPER */
1505
1506} PDMUSERPERVM;
1507/** Pointer to the PDM data kept in the UVM. */
1508typedef PDMUSERPERVM *PPDMUSERPERVM;
1509
1510
1511
1512/*******************************************************************************
1513* Global Variables *
1514*******************************************************************************/
1515#ifdef IN_RING3
1516extern const PDMDRVHLPR3 g_pdmR3DrvHlp;
1517extern const PDMDEVHLPR3 g_pdmR3DevHlpTrusted;
1518# ifdef VBOX_WITH_DBGF_TRACING
1519extern const PDMDEVHLPR3 g_pdmR3DevHlpTracing;
1520# endif
1521extern const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted;
1522extern const PDMPICHLP g_pdmR3DevPicHlp;
1523extern const PDMIOAPICHLP g_pdmR3DevIoApicHlp;
1524extern const PDMFWHLPR3 g_pdmR3DevFirmwareHlp;
1525extern const PDMPCIHLPR3 g_pdmR3DevPciHlp;
1526extern const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp;
1527extern const PDMDMACHLP g_pdmR3DevDmacHlp;
1528extern const PDMRTCHLP g_pdmR3DevRtcHlp;
1529extern const PDMHPETHLPR3 g_pdmR3DevHpetHlp;
1530extern const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp;
1531#endif
1532
1533
1534/*******************************************************************************
1535* Defined Constants And Macros *
1536*******************************************************************************/
1537/** @def PDMDEV_ASSERT_DEVINS
1538 * Asserts the validity of the device instance.
1539 */
1540#ifdef VBOX_STRICT
1541# define PDMDEV_ASSERT_DEVINS(pDevIns) \
1542 do { \
1543 AssertPtr(pDevIns); \
1544 Assert(pDevIns->u32Version == PDM_DEVINS_VERSION); \
1545 Assert(pDevIns->CTX_SUFF(pvInstanceDataFor) == (void *)&pDevIns->achInstanceData[0]); \
1546 } while (0)
1547#else
1548# define PDMDEV_ASSERT_DEVINS(pDevIns) do { } while (0)
1549#endif
1550
1551/** @def PDMDRV_ASSERT_DRVINS
1552 * Asserts the validity of the driver instance.
1553 */
1554#ifdef VBOX_STRICT
1555# define PDMDRV_ASSERT_DRVINS(pDrvIns) \
1556 do { \
1557 AssertPtr(pDrvIns); \
1558 Assert(pDrvIns->u32Version == PDM_DRVINS_VERSION); \
1559 Assert(pDrvIns->CTX_SUFF(pvInstanceData) == (void *)&pDrvIns->achInstanceData[0]); \
1560 } while (0)
1561#else
1562# define PDMDRV_ASSERT_DRVINS(pDrvIns) do { } while (0)
1563#endif
1564
1565
1566/*******************************************************************************
1567* Internal Functions *
1568*******************************************************************************/
1569#ifdef IN_RING3
1570bool pdmR3IsValidName(const char *pszName);
1571
1572int pdmR3CritSectBothInitStats(PVM pVM);
1573void pdmR3CritSectBothRelocate(PVM pVM);
1574int pdmR3CritSectBothDeleteDevice(PVM pVM, PPDMDEVINS pDevIns);
1575int pdmR3CritSectBothDeleteDriver(PVM pVM, PPDMDRVINS pDrvIns);
1576int pdmR3CritSectInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1577 const char *pszNameFmt, va_list va);
1578int pdmR3CritSectInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1579 const char *pszNameFmt, ...);
1580int pdmR3CritSectInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1581 const char *pszNameFmt, ...);
1582int pdmR3CritSectRwInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1583 const char *pszNameFmt, va_list va);
1584int pdmR3CritSectRwInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1585 const char *pszNameFmt, ...);
1586int pdmR3CritSectRwInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1587 const char *pszNameFmt, ...);
1588
1589int pdmR3DevInit(PVM pVM);
1590int pdmR3DevInitComplete(PVM pVM);
1591PPDMDEV pdmR3DevLookup(PVM pVM, const char *pszName);
1592int pdmR3DevFindLun(PVM pVM, const char *pszDevice, unsigned iInstance, unsigned iLun, PPDMLUN *ppLun);
1593DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem);
1594
1595int pdmR3UsbLoadModules(PVM pVM);
1596int pdmR3UsbInstantiateDevices(PVM pVM);
1597PPDMUSB pdmR3UsbLookup(PVM pVM, const char *pszName);
1598int pdmR3UsbRegisterHub(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fVersions, uint32_t cPorts, PCPDMUSBHUBREG pUsbHubReg, PPCPDMUSBHUBHLP ppUsbHubHlp);
1599int pdmR3UsbVMInitComplete(PVM pVM);
1600
1601int pdmR3DrvInit(PVM pVM);
1602int pdmR3DrvInstantiate(PVM pVM, PCFGMNODE pNode, PPDMIBASE pBaseInterface, PPDMDRVINS pDrvAbove,
1603 PPDMLUN pLun, PPDMIBASE *ppBaseInterface);
1604int pdmR3DrvDetach(PPDMDRVINS pDrvIns, uint32_t fFlags);
1605void pdmR3DrvDestroyChain(PPDMDRVINS pDrvIns, uint32_t fFlags);
1606PPDMDRV pdmR3DrvLookup(PVM pVM, const char *pszName);
1607
1608int pdmR3LdrInitU(PUVM pUVM);
1609void pdmR3LdrTermU(PUVM pUVM);
1610char *pdmR3FileR3(const char *pszFile, bool fShared);
1611int pdmR3LoadR3U(PUVM pUVM, const char *pszFilename, const char *pszName);
1612
1613void pdmR3QueueRelocate(PVM pVM, RTGCINTPTR offDelta);
1614
1615int pdmR3TaskInit(PVM pVM);
1616void pdmR3TaskTerm(PVM pVM);
1617
1618int pdmR3ThreadCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
1619 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1620int pdmR3ThreadCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADUSB pfnThread,
1621 PFNPDMTHREADWAKEUPUSB pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1622int pdmR3ThreadCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDRV pfnThread,
1623 PFNPDMTHREADWAKEUPDRV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1624int pdmR3ThreadDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1625int pdmR3ThreadDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1626int pdmR3ThreadDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1627void pdmR3ThreadDestroyAll(PVM pVM);
1628int pdmR3ThreadResumeAll(PVM pVM);
1629int pdmR3ThreadSuspendAll(PVM pVM);
1630
1631#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
1632int pdmR3AsyncCompletionInit(PVM pVM);
1633int pdmR3AsyncCompletionTerm(PVM pVM);
1634void pdmR3AsyncCompletionResume(PVM pVM);
1635int pdmR3AsyncCompletionTemplateCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEDEV pfnCompleted, const char *pszDesc);
1636int pdmR3AsyncCompletionTemplateCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate,
1637 PFNPDMASYNCCOMPLETEDRV pfnCompleted, void *pvTemplateUser, const char *pszDesc);
1638int pdmR3AsyncCompletionTemplateCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEUSB pfnCompleted, const char *pszDesc);
1639int pdmR3AsyncCompletionTemplateDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1640int pdmR3AsyncCompletionTemplateDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1641int pdmR3AsyncCompletionTemplateDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1642#endif
1643
1644#ifdef VBOX_WITH_NETSHAPER
1645int pdmR3NetShaperInit(PVM pVM);
1646int pdmR3NetShaperTerm(PVM pVM);
1647#endif
1648
1649int pdmR3BlkCacheInit(PVM pVM);
1650void pdmR3BlkCacheTerm(PVM pVM);
1651int pdmR3BlkCacheResume(PVM pVM);
1652
1653#endif /* IN_RING3 */
1654
1655void pdmLock(PVMCC pVM);
1656int pdmLockEx(PVMCC pVM, int rc);
1657void pdmUnlock(PVMCC pVM);
1658
1659#if defined(IN_RING3) || defined(IN_RING0)
1660void pdmCritSectRwLeaveSharedQueued(PPDMCRITSECTRW pThis);
1661void pdmCritSectRwLeaveExclQueued(PPDMCRITSECTRW pThis);
1662#endif
1663
1664#if defined IN_RING0
1665DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc);
1666#endif
1667
1668#ifdef VBOX_WITH_DBGF_TRACING
1669# if defined(IN_RING3)
1670DECLHIDDEN(DECLCALLBACK(int)) pdmR3DevHlpTracing_IoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
1671 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1672 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
1673 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts);
1674DECLHIDDEN(DECLCALLBACK(int)) pdmR3DevHlpTracing_IoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port);
1675DECLHIDDEN(DECLCALLBACK(int)) pdmR3DevHlpTracing_IoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts);
1676DECLHIDDEN(DECLCALLBACK(int)) pdmR3DevHlpTracing_MmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
1677 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
1678 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
1679 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion);
1680DECLHIDDEN(DECLCALLBACK(int)) pdmR3DevHlpTracing_MmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys);
1681DECLHIDDEN(DECLCALLBACK(int)) pdmR3DevHlpTracing_MmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion);
1682DECLHIDDEN(DECLCALLBACK(int)) pdmR3DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1683DECLHIDDEN(DECLCALLBACK(int)) pdmR3DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1684DECLHIDDEN(DECLCALLBACK(int)) pdmR3DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1685DECLHIDDEN(DECLCALLBACK(int)) pdmR3DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1686DECLHIDDEN(DECLCALLBACK(void)) pdmR3DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1687DECLHIDDEN(DECLCALLBACK(void)) pdmR3DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1688DECLHIDDEN(DECLCALLBACK(void)) pdmR3DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1689DECLHIDDEN(DECLCALLBACK(void)) pdmR3DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1690DECLHIDDEN(DECLCALLBACK(void)) pdmR3DevHlpTracing_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue);
1691# elif defined(IN_RING0)
1692DECLHIDDEN(DECLCALLBACK(int)) pdmR0DevHlpTracing_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
1693 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1694 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
1695 void *pvUser);
1696DECLHIDDEN(DECLCALLBACK(int)) pdmR0DevHlpTracing_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
1697 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser);
1698DECLHIDDEN(DECLCALLBACK(int)) pdmR0DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1699DECLHIDDEN(DECLCALLBACK(int)) pdmR0DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1700DECLHIDDEN(DECLCALLBACK(int)) pdmR0DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1701DECLHIDDEN(DECLCALLBACK(int)) pdmR0DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1702DECLHIDDEN(DECLCALLBACK(void)) pdmR0DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1703DECLHIDDEN(DECLCALLBACK(void)) pdmR0DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1704DECLHIDDEN(DECLCALLBACK(void)) pdmR0DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1705DECLHIDDEN(DECLCALLBACK(void)) pdmR0DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1706DECLHIDDEN(DECLCALLBACK(void)) pdmR0DevHlpTracing_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue);
1707# else
1708# error "Invalid environment selected"
1709# endif
1710#endif
1711
1712
1713/** @} */
1714
1715RT_C_DECLS_END
1716
1717#endif /* !VMM_INCLUDED_SRC_include_PDMInternal_h */
1718
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