PDMInternal.h@ 86661

Last change on this file since 86661 was 86661, checked in by vboxsync, 4 years ago
AMD IOMMU: bugref:9654: Add PDM interfaces for pfnPCIPhysGCPhys2CCPtr[ReadOnly] and merge IOMMU memory read/write interface into memory access interface with a flag.
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1	/* $Id: PDMInternal.h 86661 2020-10-21 11:39:04Z vboxsync $ */
2	/** @file
3	* PDM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_PDMInternal_h
19	#define VMM_INCLUDED_SRC_include_PDMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/types.h>
25	#include <VBox/param.h>
26	#include <VBox/vmm/cfgm.h>
27	#include <VBox/vmm/stam.h>
28	#include <VBox/vusb.h>
29	#include <VBox/vmm/iom.h>
30	#include <VBox/vmm/pdmasynccompletion.h>
31	#ifdef VBOX_WITH_NETSHAPER
32	# include <VBox/vmm/pdmnetshaper.h>
33	#endif
34	#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
35	# include <VBox/vmm/pdmasynccompletion.h>
36	#endif
37	#include <VBox/vmm/pdmblkcache.h>
38	#include <VBox/vmm/pdmcommon.h>
39	#include <VBox/vmm/pdmtask.h>
40	#include <VBox/sup.h>
41	#include <VBox/msi.h>
42	#include <iprt/assert.h>
43	#include <iprt/critsect.h>
44	#ifdef IN_RING3
45	# include <iprt/thread.h>
46	#endif
47
48	RT_C_DECLS_BEGIN
49
50
51	/** @defgroup grp_pdm_int Internal
52	* @ingroup grp_pdm
53	* @internal
54	* @{
55	*/
56
57	/** @def PDM_WITH_R3R0_CRIT_SECT
58	* Enables or disabled ring-3/ring-0 critical sections. */
59	#if defined(DOXYGEN_RUNNING) \|\| 1
60	# define PDM_WITH_R3R0_CRIT_SECT
61	#endif
62
63	/** @def PDMCRITSECT_STRICT
64	* Enables/disables PDM critsect strictness like deadlock detection. */
65	#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECT_STRICT)) \
66	\|\| defined(DOXYGEN_RUNNING)
67	# define PDMCRITSECT_STRICT
68	#endif
69
70	/** @def PDMCRITSECT_STRICT
71	* Enables/disables PDM read/write critsect strictness like deadlock
72	* detection. */
73	#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECTRW_STRICT)) \
74	\|\| defined(DOXYGEN_RUNNING)
75	# define PDMCRITSECTRW_STRICT
76	#endif
77
78	/** The maximum device instance (total) size, ring-0/raw-mode capable devices. */
79	#define PDM_MAX_DEVICE_INSTANCE_SIZE _4M
80	/** The maximum device instance (total) size, ring-3 only devices. */
81	#define PDM_MAX_DEVICE_INSTANCE_SIZE_R3 _8M
82	/** The maximum size for the DBGF tracing tracking structure allocated for each device. */
83	#define PDM_MAX_DEVICE_DBGF_TRACING_TRACK PAGE_SIZE
84
85
86
87	/*******************************************************************************
88	* Structures and Typedefs *
89	*******************************************************************************/
90
91	/** Pointer to a PDM Device. */
92	typedef struct PDMDEV *PPDMDEV;
93	/** Pointer to a pointer to a PDM Device. */
94	typedef PPDMDEV *PPPDMDEV;
95
96	/** Pointer to a PDM USB Device. */
97	typedef struct PDMUSB *PPDMUSB;
98	/** Pointer to a pointer to a PDM USB Device. */
99	typedef PPDMUSB *PPPDMUSB;
100
101	/** Pointer to a PDM Driver. */
102	typedef struct PDMDRV *PPDMDRV;
103	/** Pointer to a pointer to a PDM Driver. */
104	typedef PPDMDRV *PPPDMDRV;
105
106	/** Pointer to a PDM Logical Unit. */
107	typedef struct PDMLUN *PPDMLUN;
108	/** Pointer to a pointer to a PDM Logical Unit. */
109	typedef PPDMLUN *PPPDMLUN;
110
111	/** Pointer to a PDM PCI Bus instance. */
112	typedef struct PDMPCIBUS *PPDMPCIBUS;
113	/** Pointer to a PDM IOMMU instance. */
114	typedef struct PDMIOMMU *PPDMIOMMU;
115	/** Pointer to a DMAC instance. */
116	typedef struct PDMDMAC *PPDMDMAC;
117	/** Pointer to a RTC instance. */
118	typedef struct PDMRTC *PPDMRTC;
119
120	/** Pointer to an USB HUB registration record. */
121	typedef struct PDMUSBHUB *PPDMUSBHUB;
122
123	/**
124	* Supported asynchronous completion endpoint classes.
125	*/
126	typedef enum PDMASYNCCOMPLETIONEPCLASSTYPE
127	{
128	/** File class. */
129	PDMASYNCCOMPLETIONEPCLASSTYPE_FILE = 0,
130	/** Number of supported classes. */
131	PDMASYNCCOMPLETIONEPCLASSTYPE_MAX,
132	/** 32bit hack. */
133	PDMASYNCCOMPLETIONEPCLASSTYPE_32BIT_HACK = 0x7fffffff
134	} PDMASYNCCOMPLETIONEPCLASSTYPE;
135
136
137	/**
138	* MMIO/IO port registration tracking structure for DBGF tracing.
139	*/
140	typedef struct PDMDEVINSDBGFTRACK
141	{
142	/** Flag whether this tracks a IO port or MMIO registration. */
143	bool fMmio;
144	/** Opaque user data passed during registration. */
145	void *pvUser;
146	/** Type dependent data. */
147	union
148	{
149	/** I/O port registration. */
150	struct
151	{
152	/** IOM I/O port handle. */
153	IOMIOPORTHANDLE hIoPorts;
154	/** Original OUT handler of the device. */
155	PFNIOMIOPORTNEWOUT pfnOut;
156	/** Original IN handler of the device. */
157	PFNIOMIOPORTNEWIN pfnIn;
158	/** Original string OUT handler of the device. */
159	PFNIOMIOPORTNEWOUTSTRING pfnOutStr;
160	/** Original string IN handler of the device. */
161	PFNIOMIOPORTNEWINSTRING pfnInStr;
162	} IoPort;
163	/** MMIO registration. */
164	struct
165	{
166	/** IOM MMIO region handle. */
167	IOMMMIOHANDLE hMmioRegion;
168	/** Original MMIO write handler of the device. */
169	PFNIOMMMIONEWWRITE pfnWrite;
170	/** Original MMIO read handler of the device. */
171	PFNIOMMMIONEWREAD pfnRead;
172	/** Original MMIO fill handler of the device. */
173	PFNIOMMMIONEWFILL pfnFill;
174	} Mmio;
175	} u;
176	} PDMDEVINSDBGFTRACK;
177	/** Pointer to a MMIO/IO port registration tracking structure. */
178	typedef PDMDEVINSDBGFTRACK *PPDMDEVINSDBGFTRACK;
179	/** Pointer to a const MMIO/IO port registration tracking structure. */
180	typedef const PDMDEVINSDBGFTRACK *PCPDMDEVINSDBGFTRACK;
181
182
183	/**
184	* Private device instance data, ring-3.
185	*/
186	typedef struct PDMDEVINSINTR3
187	{
188	/** Pointer to the next instance.
189	* (Head is pointed to by PDM::pDevInstances.) */
190	R3PTRTYPE(PPDMDEVINS) pNextR3;
191	/** Pointer to the next per device instance.
192	* (Head is pointed to by PDMDEV::pInstances.) */
193	R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
194	/** Pointer to device structure. */
195	R3PTRTYPE(PPDMDEV) pDevR3;
196	/** Pointer to the list of logical units associated with the device. (FIFO) */
197	R3PTRTYPE(PPDMLUN) pLunsR3;
198	/** Pointer to the asynchronous notification callback set while in
199	* FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
200	R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
201	/** Configuration handle to the instance node. */
202	R3PTRTYPE(PCFGMNODE) pCfgHandle;
203
204	/** R3 pointer to the VM this instance was created for. */
205	PVMR3 pVMR3;
206	/** DBGF trace event source handle if tracing is configured. */
207	DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
208	/** Pointer to the base of the page containing the DBGF tracing tracking structures. */
209	PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
210	/** Index of the next entry to use for tracking. */
211	uint32_t idxDbgfTraceTrackNext;
212	/** Maximum number of records fitting into the single page. */
213	uint32_t cDbgfTraceTrackMax;
214
215	/** Flags, see PDMDEVINSINT_FLAGS_XXX. */
216	uint32_t fIntFlags;
217	/** The last IRQ tag (for tracing it thru clearing). */
218	uint32_t uLastIrqTag;
219	/** The ring-0 device index (for making ring-0 calls). */
220	uint32_t idxR0Device;
221	} PDMDEVINSINTR3;
222
223
224	/**
225	* Private device instance data, ring-0.
226	*/
227	typedef struct PDMDEVINSINTR0
228	{
229	/** Pointer to the VM this instance was created for. */
230	R0PTRTYPE(PGVM) pGVM;
231	/** Pointer to device structure. */
232	R0PTRTYPE(struct PDMDEVREGR0 const *) pRegR0;
233	/** The ring-0 module reference. */
234	RTR0PTR hMod;
235	/** Pointer to the ring-0 mapping of the ring-3 internal data (for uLastIrqTag). */
236	R0PTRTYPE(PDMDEVINSINTR3 *) pIntR3R0;
237	/** Pointer to the ring-0 mapping of the ring-3 instance (for idTracing). */
238	R0PTRTYPE(struct PDMDEVINSR3 *) pInsR3R0;
239	/** DBGF trace event source handle if tracing is configured. */
240	DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
241	/** The device instance memory. */
242	RTR0MEMOBJ hMemObj;
243	/** The ring-3 mapping object. */
244	RTR0MEMOBJ hMapObj;
245	/** The page memory object for tracking MMIO and I/O port registrations when tracing is configured. */
246	RTR0MEMOBJ hDbgfTraceObj;
247	/** Pointer to the base of the page containing the DBGF tracing tracking structures. */
248	PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
249	/** Index of the next entry to use for tracking. */
250	uint32_t idxDbgfTraceTrackNext;
251	/** Maximum number of records fitting into the single page. */
252	uint32_t cDbgfTraceTrackMax;
253	/** Index into PDMR0PERVM::apDevInstances. */
254	uint32_t idxR0Device;
255	} PDMDEVINSINTR0;
256
257
258	/**
259	* Private device instance data, raw-mode
260	*/
261	typedef struct PDMDEVINSINTRC
262	{
263	/** Pointer to the VM this instance was created for. */
264	RGPTRTYPE(PVM) pVMRC;
265	} PDMDEVINSINTRC;
266
267
268	/**
269	* Private device instance data.
270	*/
271	typedef struct PDMDEVINSINT
272	{
273	/** Pointer to the next instance (HC Ptr).
274	* (Head is pointed to by PDM::pDevInstances.) */
275	R3PTRTYPE(PPDMDEVINS) pNextR3;
276	/** Pointer to the next per device instance (HC Ptr).
277	* (Head is pointed to by PDMDEV::pInstances.) */
278	R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
279	/** Pointer to device structure - HC Ptr. */
280	R3PTRTYPE(PPDMDEV) pDevR3;
281	/** Pointer to the list of logical units associated with the device. (FIFO) */
282	R3PTRTYPE(PPDMLUN) pLunsR3;
283	/** Pointer to the asynchronous notification callback set while in
284	* FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
285	R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
286	/** Configuration handle to the instance node. */
287	R3PTRTYPE(PCFGMNODE) pCfgHandle;
288
289	/** R3 pointer to the VM this instance was created for. */
290	PVMR3 pVMR3;
291
292	/** R0 pointer to the VM this instance was created for. */
293	R0PTRTYPE(PVMCC) pVMR0;
294
295	/** RC pointer to the VM this instance was created for. */
296	PVMRC pVMRC;
297
298	/** Flags, see PDMDEVINSINT_FLAGS_XXX. */
299	uint32_t fIntFlags;
300	/** The last IRQ tag (for tracing it thru clearing). */
301	uint32_t uLastIrqTag;
302	} PDMDEVINSINT;
303
304	/** @name PDMDEVINSINT::fIntFlags
305	* @{ */
306	/** Used by pdmR3Load to mark device instances it found in the saved state. */
307	#define PDMDEVINSINT_FLAGS_FOUND RT_BIT_32(0)
308	/** Indicates that the device hasn't been powered on or resumed.
309	* This is used by PDMR3PowerOn, PDMR3Resume, PDMR3Suspend and PDMR3PowerOff
310	* to make sure each device gets exactly one notification for each of those
311	* events. PDMR3Resume and PDMR3PowerOn also makes use of it to bail out on
312	* a failure (already resumed/powered-on devices are suspended).
313	* PDMR3PowerOff resets this flag once before going through the devices to make sure
314	* every device gets the power off notification even if it was suspended before with
315	* PDMR3Suspend.
316	*/
317	#define PDMDEVINSINT_FLAGS_SUSPENDED RT_BIT_32(1)
318	/** Indicates that the device has been reset already. Used by PDMR3Reset. */
319	#define PDMDEVINSINT_FLAGS_RESET RT_BIT_32(2)
320	#define PDMDEVINSINT_FLAGS_R0_ENABLED RT_BIT_32(3)
321	#define PDMDEVINSINT_FLAGS_RC_ENABLED RT_BIT_32(4)
322	/** Set if we've called the ring-0 constructor. */
323	#define PDMDEVINSINT_FLAGS_R0_CONTRUCT RT_BIT_32(5)
324	/** Set if using non-default critical section. */
325	#define PDMDEVINSINT_FLAGS_CHANGED_CRITSECT RT_BIT_32(6)
326	/** @} */
327
328
329	/**
330	* Private USB device instance data.
331	*/
332	typedef struct PDMUSBINSINT
333	{
334	/** The UUID of this instance. */
335	RTUUID Uuid;
336	/** Pointer to the next instance.
337	* (Head is pointed to by PDM::pUsbInstances.) */
338	R3PTRTYPE(PPDMUSBINS) pNext;
339	/** Pointer to the next per USB device instance.
340	* (Head is pointed to by PDMUSB::pInstances.) */
341	R3PTRTYPE(PPDMUSBINS) pPerDeviceNext;
342
343	/** Pointer to device structure. */
344	R3PTRTYPE(PPDMUSB) pUsbDev;
345
346	/** Pointer to the VM this instance was created for. */
347	PVMR3 pVM;
348	/** Pointer to the list of logical units associated with the device. (FIFO) */
349	R3PTRTYPE(PPDMLUN) pLuns;
350	/** The per instance device configuration. */
351	R3PTRTYPE(PCFGMNODE) pCfg;
352	/** Same as pCfg if the configuration should be deleted when detaching the device. */
353	R3PTRTYPE(PCFGMNODE) pCfgDelete;
354	/** The global device configuration. */
355	R3PTRTYPE(PCFGMNODE) pCfgGlobal;
356
357	/** Pointer to the USB hub this device is attached to.
358	* This is NULL if the device isn't connected to any HUB. */
359	R3PTRTYPE(PPDMUSBHUB) pHub;
360	/** The port number that we're connected to. */
361	uint32_t iPort;
362	/** Indicates that the USB device hasn't been powered on or resumed.
363	* See PDMDEVINSINT_FLAGS_SUSPENDED. */
364	bool fVMSuspended;
365	/** Indicates that the USB device has been reset. */
366	bool fVMReset;
367	/** Pointer to the asynchronous notification callback set while in
368	* FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
369	R3PTRTYPE(PFNPDMUSBASYNCNOTIFY) pfnAsyncNotify;
370	} PDMUSBINSINT;
371
372
373	/**
374	* Private driver instance data.
375	*/
376	typedef struct PDMDRVINSINT
377	{
378	/** Pointer to the driver instance above.
379	* This is NULL for the topmost drive. */
380	R3PTRTYPE(PPDMDRVINS) pUp;
381	/** Pointer to the driver instance below.
382	* This is NULL for the bottommost driver. */
383	R3PTRTYPE(PPDMDRVINS) pDown;
384	/** Pointer to the logical unit this driver chained on. */
385	R3PTRTYPE(PPDMLUN) pLun;
386	/** Pointer to driver structure from which this was instantiated. */
387	R3PTRTYPE(PPDMDRV) pDrv;
388	/** Pointer to the VM this instance was created for, ring-3 context. */
389	PVMR3 pVMR3;
390	/** Pointer to the VM this instance was created for, ring-0 context. */
391	R0PTRTYPE(PVMCC) pVMR0;
392	/** Pointer to the VM this instance was created for, raw-mode context. */
393	PVMRC pVMRC;
394	/** Flag indicating that the driver is being detached and destroyed.
395	* (Helps detect potential recursive detaching.) */
396	bool fDetaching;
397	/** Indicates that the driver hasn't been powered on or resumed.
398	* See PDMDEVINSINT_FLAGS_SUSPENDED. */
399	bool fVMSuspended;
400	/** Indicates that the driver has been reset already. */
401	bool fVMReset;
402	/** Set if allocated on the hyper heap, false if on the ring-3 heap. */
403	bool fHyperHeap;
404	/** Pointer to the asynchronous notification callback set while in
405	* PDMUSBREG::pfnVMSuspend or PDMUSBREG::pfnVMPowerOff. */
406	R3PTRTYPE(PFNPDMDRVASYNCNOTIFY) pfnAsyncNotify;
407	/** Configuration handle to the instance node. */
408	R3PTRTYPE(PCFGMNODE) pCfgHandle;
409	/** Pointer to the ring-0 request handler function. */
410	PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
411	} PDMDRVINSINT;
412
413
414	/**
415	* Private critical section data.
416	*/
417	typedef struct PDMCRITSECTINT
418	{
419	/** The critical section core which is shared with IPRT.
420	* @note The semaphore is a SUPSEMEVENT. */
421	RTCRITSECT Core;
422	/** Pointer to the next critical section.
423	* This chain is used for relocating pVMRC and device cleanup. */
424	R3PTRTYPE(struct PDMCRITSECTINT *) pNext;
425	/** Owner identifier.
426	* This is pDevIns if the owner is a device. Similarly for a driver or service.
427	* PDMR3CritSectInit() sets this to point to the critsect itself. */
428	RTR3PTR pvKey;
429	/** Pointer to the VM - R3Ptr. */
430	PVMR3 pVMR3;
431	/** Pointer to the VM - R0Ptr. */
432	R0PTRTYPE(PVMCC) pVMR0;
433	/** Pointer to the VM - GCPtr. */
434	PVMRC pVMRC;
435	/** Set if this critical section is the automatically created default
436	* section of a device. */
437	bool fAutomaticDefaultCritsect;
438	/** Set if the critical section is used by a timer or similar.
439	* See PDMR3DevGetCritSect. */
440	bool fUsedByTimerOrSimilar;
441	/** Alignment padding. */
442	bool afPadding[2];
443	/** Support driver event semaphore that is scheduled to be signaled upon leaving
444	* the critical section. This is only for Ring-3 and Ring-0. */
445	SUPSEMEVENT hEventToSignal;
446	/** The lock name. */
447	R3PTRTYPE(const char *) pszName;
448	/** R0/RC lock contention. */
449	STAMCOUNTER StatContentionRZLock;
450	/** R0/RC unlock contention. */
451	STAMCOUNTER StatContentionRZUnlock;
452	/** R3 lock contention. */
453	STAMCOUNTER StatContentionR3;
454	/** Profiling the time the section is locked. */
455	STAMPROFILEADV StatLocked;
456	} PDMCRITSECTINT;
457	AssertCompileMemberAlignment(PDMCRITSECTINT, StatContentionRZLock, 8);
458	/** Pointer to private critical section data. */
459	typedef PDMCRITSECTINT *PPDMCRITSECTINT;
460
461	/** Indicates that the critical section is queued for unlock.
462	* PDMCritSectIsOwner and PDMCritSectIsOwned optimizations. */
463	#define PDMCRITSECT_FLAGS_PENDING_UNLOCK RT_BIT_32(17)
464
465
466	/**
467	* Private critical section data.
468	*/
469	typedef struct PDMCRITSECTRWINT
470	{
471	/** The read/write critical section core which is shared with IPRT.
472	* @note The semaphores are SUPSEMEVENT and SUPSEMEVENTMULTI. */
473	RTCRITSECTRW Core;
474
475	/** Pointer to the next critical section.
476	* This chain is used for relocating pVMRC and device cleanup. */
477	R3PTRTYPE(struct PDMCRITSECTRWINT *) pNext;
478	/** Owner identifier.
479	* This is pDevIns if the owner is a device. Similarly for a driver or service.
480	* PDMR3CritSectInit() sets this to point to the critsect itself. */
481	RTR3PTR pvKey;
482	/** Pointer to the VM - R3Ptr. */
483	PVMR3 pVMR3;
484	/** Pointer to the VM - R0Ptr. */
485	R0PTRTYPE(PVMCC) pVMR0;
486	/** Pointer to the VM - GCPtr. */
487	PVMRC pVMRC;
488	#if HC_ARCH_BITS == 64
489	/** Alignment padding. */
490	RTRCPTR RCPtrPadding;
491	#endif
492	/** The lock name. */
493	R3PTRTYPE(const char *) pszName;
494	/** R0/RC write lock contention. */
495	STAMCOUNTER StatContentionRZEnterExcl;
496	/** R0/RC write unlock contention. */
497	STAMCOUNTER StatContentionRZLeaveExcl;
498	/** R0/RC read lock contention. */
499	STAMCOUNTER StatContentionRZEnterShared;
500	/** R0/RC read unlock contention. */
501	STAMCOUNTER StatContentionRZLeaveShared;
502	/** R0/RC writes. */
503	STAMCOUNTER StatRZEnterExcl;
504	/** R0/RC reads. */
505	STAMCOUNTER StatRZEnterShared;
506	/** R3 write lock contention. */
507	STAMCOUNTER StatContentionR3EnterExcl;
508	/** R3 read lock contention. */
509	STAMCOUNTER StatContentionR3EnterShared;
510	/** R3 writes. */
511	STAMCOUNTER StatR3EnterExcl;
512	/** R3 reads. */
513	STAMCOUNTER StatR3EnterShared;
514	/** Profiling the time the section is write locked. */
515	STAMPROFILEADV StatWriteLocked;
516	} PDMCRITSECTRWINT;
517	AssertCompileMemberAlignment(PDMCRITSECTRWINT, StatContentionRZEnterExcl, 8);
518	AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u64State, 8);
519	/** Pointer to private critical section data. */
520	typedef PDMCRITSECTRWINT *PPDMCRITSECTRWINT;
521
522
523
524	/**
525	* The usual device/driver/internal/external stuff.
526	*/
527	typedef enum
528	{
529	/** The usual invalid entry. */
530	PDMTHREADTYPE_INVALID = 0,
531	/** Device type. */
532	PDMTHREADTYPE_DEVICE,
533	/** USB Device type. */
534	PDMTHREADTYPE_USB,
535	/** Driver type. */
536	PDMTHREADTYPE_DRIVER,
537	/** Internal type. */
538	PDMTHREADTYPE_INTERNAL,
539	/** External type. */
540	PDMTHREADTYPE_EXTERNAL,
541	/** The usual 32-bit hack. */
542	PDMTHREADTYPE_32BIT_HACK = 0x7fffffff
543	} PDMTHREADTYPE;
544
545
546	/**
547	* The internal structure for the thread.
548	*/
549	typedef struct PDMTHREADINT
550	{
551	/** The VM pointer. */
552	PVMR3 pVM;
553	/** The event semaphore the thread blocks on when not running. */
554	RTSEMEVENTMULTI BlockEvent;
555	/** The event semaphore the thread sleeps on while running. */
556	RTSEMEVENTMULTI SleepEvent;
557	/** Pointer to the next thread. */
558	R3PTRTYPE(struct PDMTHREAD *) pNext;
559	/** The thread type. */
560	PDMTHREADTYPE enmType;
561	} PDMTHREADINT;
562
563
564
565	/* Must be included after PDMDEVINSINT is defined. */
566	#define PDMDEVINSINT_DECLARED
567	#define PDMUSBINSINT_DECLARED
568	#define PDMDRVINSINT_DECLARED
569	#define PDMCRITSECTINT_DECLARED
570	#define PDMCRITSECTRWINT_DECLARED
571	#define PDMTHREADINT_DECLARED
572	#ifdef ___VBox_pdm_h
573	# error "Invalid header PDM order. Include PDMInternal.h before VBox/vmm/pdm.h!"
574	#endif
575	RT_C_DECLS_END
576	#include <VBox/vmm/pdm.h>
577	RT_C_DECLS_BEGIN
578
579	/**
580	* PDM Logical Unit.
581	*
582	* This typically the representation of a physical port on a
583	* device, like for instance the PS/2 keyboard port on the
584	* keyboard controller device. The LUNs are chained on the
585	* device they belong to (PDMDEVINSINT::pLunsR3).
586	*/
587	typedef struct PDMLUN
588	{
589	/** The LUN - The Logical Unit Number. */
590	RTUINT iLun;
591	/** Pointer to the next LUN. */
592	PPDMLUN pNext;
593	/** Pointer to the top driver in the driver chain. */
594	PPDMDRVINS pTop;
595	/** Pointer to the bottom driver in the driver chain. */
596	PPDMDRVINS pBottom;
597	/** Pointer to the device instance which the LUN belongs to.
598	* Either this is set or pUsbIns is set. Both is never set at the same time. */
599	PPDMDEVINS pDevIns;
600	/** Pointer to the USB device instance which the LUN belongs to. */
601	PPDMUSBINS pUsbIns;
602	/** Pointer to the device base interface. */
603	PPDMIBASE pBase;
604	/** Description of this LUN. */
605	const char *pszDesc;
606	} PDMLUN;
607
608
609	/**
610	* PDM Device, ring-3.
611	*/
612	typedef struct PDMDEV
613	{
614	/** Pointer to the next device (R3 Ptr). */
615	R3PTRTYPE(PPDMDEV) pNext;
616	/** Device name length. (search optimization) */
617	uint32_t cchName;
618	/** Registration structure. */
619	R3PTRTYPE(const struct PDMDEVREGR3 *) pReg;
620	/** Number of instances. */
621	uint32_t cInstances;
622	/** Pointer to chain of instances (R3 Ptr). */
623	PPDMDEVINSR3 pInstances;
624	/** The search path for raw-mode context modules (';' as separator). */
625	char *pszRCSearchPath;
626	/** The search path for ring-0 context modules (';' as separator). */
627	char *pszR0SearchPath;
628	} PDMDEV;
629
630
631	#if 0
632	/**
633	* PDM Device, ring-0.
634	*/
635	typedef struct PDMDEVR0
636	{
637	/** Pointer to the next device. */
638	R0PTRTYPE(PPDMDEVR0) pNext;
639	/** Device name length. (search optimization) */
640	uint32_t cchName;
641	/** Registration structure. */
642	R3PTRTYPE(const struct PDMDEVREGR0 *) pReg;
643	/** Number of instances. */
644	uint32_t cInstances;
645	/** Pointer to chain of instances. */
646	PPDMDEVINSR0 pInstances;
647	} PDMDEVR0;
648	#endif
649
650
651	/**
652	* PDM USB Device.
653	*/
654	typedef struct PDMUSB
655	{
656	/** Pointer to the next device (R3 Ptr). */
657	R3PTRTYPE(PPDMUSB) pNext;
658	/** Device name length. (search optimization) */
659	RTUINT cchName;
660	/** Registration structure. */
661	R3PTRTYPE(const struct PDMUSBREG *) pReg;
662	/** Next instance number. */
663	uint32_t iNextInstance;
664	/** Pointer to chain of instances (R3 Ptr). */
665	R3PTRTYPE(PPDMUSBINS) pInstances;
666	} PDMUSB;
667
668
669	/**
670	* PDM Driver.
671	*/
672	typedef struct PDMDRV
673	{
674	/** Pointer to the next device. */
675	PPDMDRV pNext;
676	/** Registration structure. */
677	const struct PDMDRVREG * pReg;
678	/** Current number of instances. */
679	uint32_t cInstances;
680	/** The next instance number. */
681	uint32_t iNextInstance;
682	/** The search path for raw-mode context modules (';' as separator). */
683	char *pszRCSearchPath;
684	/** The search path for ring-0 context modules (';' as separator). */
685	char *pszR0SearchPath;
686	} PDMDRV;
687
688
689	/**
690	* PDM registered IOMMU device.
691	*/
692	typedef struct PDMIOMMU
693	{
694	/** IOMMU index. */
695	uint32_t idxIommu;
696	uint32_t uPadding0; /*< Alignment padding./
697
698	/** Pointer to the IOMMU device instance - R3. */
699	PPDMDEVINSR3 pDevInsR3;
700	/** @copydoc PDMIOMMUREGR3::pfnMemAccess */
701	DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbAccess,
702	uint32_t fFlags, PRTGCPHYS pGCPhysSpa));
703	/** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
704	DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas,
705	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
706	/** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
707	DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
708	} PDMIOMMU;
709
710
711	/**
712	* Ring-0 PDM IOMMU instance data.
713	*/
714	typedef struct PDMIOMMUR0
715	{
716	/** IOMMU index. */
717	uint32_t idxIommu;
718	uint32_t uPadding0; /*< Alignment padding./
719
720	/** Pointer to IOMMU device instance. */
721	PPDMDEVINSR0 pDevInsR0;
722	/** @copydoc PDMIOMMUREGR3::pfnMemAccess */
723	DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, uint64_t uDva, size_t cbAccess,
724	uint32_t fFlags, PRTGCPHYS pGCPhysSpa));
725	/** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
726	DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t uDevId, size_t cIovas, uint64_t const *pauIovas,
727	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
728	/** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
729	DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
730	} PDMIOMMUR0;
731	/** Pointer to a ring-0 IOMMU data. */
732	typedef PDMIOMMUR0 *PPDMIOMMUR0;
733	/** Pointer to a const ring-0 IOMMU data. */
734	typedef const PDMIOMMUR0 *PCPDMIOMMUR0;
735
736
737	/**
738	* PDM registered PIC device.
739	*/
740	typedef struct PDMPIC
741	{
742	/** Pointer to the PIC device instance - R3. */
743	PPDMDEVINSR3 pDevInsR3;
744	/** @copydoc PDMPICREG::pfnSetIrq */
745	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
746	/** @copydoc PDMPICREG::pfnGetInterrupt */
747	DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
748
749	/** Pointer to the PIC device instance - R0. */
750	PPDMDEVINSR0 pDevInsR0;
751	/** @copydoc PDMPICREG::pfnSetIrq */
752	DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
753	/** @copydoc PDMPICREG::pfnGetInterrupt */
754	DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
755
756	/** Pointer to the PIC device instance - RC. */
757	PPDMDEVINSRC pDevInsRC;
758	/** @copydoc PDMPICREG::pfnSetIrq */
759	DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
760	/** @copydoc PDMPICREG::pfnGetInterrupt */
761	DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
762	/** Alignment padding. */
763	RTRCPTR RCPtrPadding;
764	} PDMPIC;
765
766
767	/**
768	* PDM registered APIC device.
769	*/
770	typedef struct PDMAPIC
771	{
772	/** Pointer to the APIC device instance - R3 Ptr. */
773	PPDMDEVINSR3 pDevInsR3;
774	/** Pointer to the APIC device instance - R0 Ptr. */
775	PPDMDEVINSR0 pDevInsR0;
776	/** Pointer to the APIC device instance - RC Ptr. */
777	PPDMDEVINSRC pDevInsRC;
778	uint8_t Alignment[4];
779	} PDMAPIC;
780
781
782	/**
783	* PDM registered I/O APIC device.
784	*/
785	typedef struct PDMIOAPIC
786	{
787	/** Pointer to the APIC device instance - R3 Ptr. */
788	PPDMDEVINSR3 pDevInsR3;
789	/** @copydoc PDMIOAPICREG::pfnSetIrq */
790	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
791	/** @copydoc PDMIOAPICREG::pfnSendMsi */
792	DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
793	/** @copydoc PDMIOAPICREG::pfnSetEoi */
794	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
795
796	/** Pointer to the PIC device instance - R0. */
797	PPDMDEVINSR0 pDevInsR0;
798	/** @copydoc PDMIOAPICREG::pfnSetIrq */
799	DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
800	/** @copydoc PDMIOAPICREG::pfnSendMsi */
801	DECLR0CALLBACKMEMBER(void, pfnSendMsiR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
802	/** @copydoc PDMIOAPICREG::pfnSetEoi */
803	DECLR0CALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiR0,(PPDMDEVINS pDevIns, uint8_t u8Vector));
804
805	/** Pointer to the APIC device instance - RC Ptr. */
806	PPDMDEVINSRC pDevInsRC;
807	/** @copydoc PDMIOAPICREG::pfnSetIrq */
808	DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
809	/** @copydoc PDMIOAPICREG::pfnSendMsi */
810	DECLRCCALLBACKMEMBER(void, pfnSendMsiRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
811	/** @copydoc PDMIOAPICREG::pfnSendMsi */
812	DECLRCCALLBACKMEMBER(VBOXSTRICTRC, pfnSetEoiRC,(PPDMDEVINS pDevIns, uint8_t u8Vector));
813	} PDMIOAPIC;
814
815	/** Maximum number of PCI busses for a VM. */
816	#define PDM_PCI_BUSSES_MAX 8
817	/** Maximum number of IOMMUs (at most one per PCI bus). */
818	#define PDM_IOMMUS_MAX PDM_PCI_BUSSES_MAX
819
820
821	#ifdef IN_RING3
822	/**
823	* PDM registered firmware device.
824	*/
825	typedef struct PDMFW
826	{
827	/** Pointer to the firmware device instance. */
828	PPDMDEVINSR3 pDevIns;
829	/** Copy of the registration structure. */
830	PDMFWREG Reg;
831	} PDMFW;
832	/** Pointer to a firmware instance. */
833	typedef PDMFW *PPDMFW;
834	#endif
835
836
837	/**
838	* PDM PCI bus instance.
839	*/
840	typedef struct PDMPCIBUS
841	{
842	/** PCI bus number. */
843	uint32_t iBus;
844	uint32_t uPadding0; /*< Alignment padding./
845
846	/** Pointer to PCI bus device instance. */
847	PPDMDEVINSR3 pDevInsR3;
848	/** @copydoc PDMPCIBUSREGR3::pfnSetIrqR3 */
849	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
850
851	/** @copydoc PDMPCIBUSREGR3::pfnRegisterR3 */
852	DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
853	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
854	/** @copydoc PDMPCIBUSREGR3::pfnRegisterMsiR3 */
855	DECLR3CALLBACKMEMBER(int, pfnRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
856	/** @copydoc PDMPCIBUSREGR3::pfnIORegionRegisterR3 */
857	DECLR3CALLBACKMEMBER(int, pfnIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
858	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
859	uint64_t hHandle, PFNPCIIOREGIONMAP pfnCallback));
860	/** @copydoc PDMPCIBUSREGR3::pfnInterceptConfigAccesses */
861	DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
862	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
863	/** @copydoc PDMPCIBUSREGR3::pfnConfigWrite */
864	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
865	uint32_t uAddress, unsigned cb, uint32_t u32Value));
866	/** @copydoc PDMPCIBUSREGR3::pfnConfigRead */
867	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
868	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
869	} PDMPCIBUS;
870
871
872	/**
873	* Ring-0 PDM PCI bus instance data.
874	*/
875	typedef struct PDMPCIBUSR0
876	{
877	/** PCI bus number. */
878	uint32_t iBus;
879	uint32_t uPadding0; /*< Alignment padding./
880	/** Pointer to PCI bus device instance. */
881	PPDMDEVINSR0 pDevInsR0;
882	/** @copydoc PDMPCIBUSREGR0::pfnSetIrq */
883	DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
884	} PDMPCIBUSR0;
885	/** Pointer to the ring-0 PCI bus data. */
886	typedef PDMPCIBUSR0 *PPDMPCIBUSR0;
887
888
889	#ifdef IN_RING3
890	/**
891	* PDM registered DMAC (DMA Controller) device.
892	*/
893	typedef struct PDMDMAC
894	{
895	/** Pointer to the DMAC device instance. */
896	PPDMDEVINSR3 pDevIns;
897	/** Copy of the registration structure. */
898	PDMDMACREG Reg;
899	} PDMDMAC;
900
901
902	/**
903	* PDM registered RTC (Real Time Clock) device.
904	*/
905	typedef struct PDMRTC
906	{
907	/** Pointer to the RTC device instance. */
908	PPDMDEVINSR3 pDevIns;
909	/** Copy of the registration structure. */
910	PDMRTCREG Reg;
911	} PDMRTC;
912
913	#endif /* IN_RING3 */
914
915	/**
916	* Module type.
917	*/
918	typedef enum PDMMODTYPE
919	{
920	/** Raw-mode (RC) context module. */
921	PDMMOD_TYPE_RC,
922	/** Ring-0 (host) context module. */
923	PDMMOD_TYPE_R0,
924	/** Ring-3 (host) context module. */
925	PDMMOD_TYPE_R3
926	} PDMMODTYPE;
927
928
929	/** The module name length including the terminator. */
930	#define PDMMOD_NAME_LEN 32
931
932	/**
933	* Loaded module instance.
934	*/
935	typedef struct PDMMOD
936	{
937	/** Module name. This is used for referring to
938	* the module internally, sort of like a handle. */
939	char szName[PDMMOD_NAME_LEN];
940	/** Module type. */
941	PDMMODTYPE eType;
942	/** Loader module handle. Not used for R0 modules. */
943	RTLDRMOD hLdrMod;
944	/** Loaded address.
945	* This is the 'handle' for R0 modules. */
946	RTUINTPTR ImageBase;
947	/** Old loaded address.
948	* This is used during relocation of GC modules. Not used for R0 modules. */
949	RTUINTPTR OldImageBase;
950	/** Where the R3 HC bits are stored.
951	* This can be equal to ImageBase but doesn't have to. Not used for R0 modules. */
952	void *pvBits;
953
954	/** Pointer to next module. */
955	struct PDMMOD *pNext;
956	/** Module filename. */
957	char szFilename[1];
958	} PDMMOD;
959	/** Pointer to loaded module instance. */
960	typedef PDMMOD *PPDMMOD;
961
962
963
964	/** Extra space in the free array. */
965	#define PDMQUEUE_FREE_SLACK 16
966
967	/**
968	* Queue type.
969	*/
970	typedef enum PDMQUEUETYPE
971	{
972	/** Device consumer. */
973	PDMQUEUETYPE_DEV = 1,
974	/** Driver consumer. */
975	PDMQUEUETYPE_DRV,
976	/** Internal consumer. */
977	PDMQUEUETYPE_INTERNAL,
978	/** External consumer. */
979	PDMQUEUETYPE_EXTERNAL
980	} PDMQUEUETYPE;
981
982	/** Pointer to a PDM Queue. */
983	typedef struct PDMQUEUE *PPDMQUEUE;
984
985	/**
986	* PDM Queue.
987	*/
988	typedef struct PDMQUEUE
989	{
990	/** Pointer to the next queue in the list. */
991	R3PTRTYPE(PPDMQUEUE) pNext;
992	/** Type specific data. */
993	union
994	{
995	/** PDMQUEUETYPE_DEV */
996	struct
997	{
998	/** Pointer to consumer function. */
999	R3PTRTYPE(PFNPDMQUEUEDEV) pfnCallback;
1000	/** Pointer to the device instance owning the queue. */
1001	R3PTRTYPE(PPDMDEVINS) pDevIns;
1002	} Dev;
1003	/** PDMQUEUETYPE_DRV */
1004	struct
1005	{
1006	/** Pointer to consumer function. */
1007	R3PTRTYPE(PFNPDMQUEUEDRV) pfnCallback;
1008	/** Pointer to the driver instance owning the queue. */
1009	R3PTRTYPE(PPDMDRVINS) pDrvIns;
1010	} Drv;
1011	/** PDMQUEUETYPE_INTERNAL */
1012	struct
1013	{
1014	/** Pointer to consumer function. */
1015	R3PTRTYPE(PFNPDMQUEUEINT) pfnCallback;
1016	} Int;
1017	/** PDMQUEUETYPE_EXTERNAL */
1018	struct
1019	{
1020	/** Pointer to consumer function. */
1021	R3PTRTYPE(PFNPDMQUEUEEXT) pfnCallback;
1022	/** Pointer to user argument. */
1023	R3PTRTYPE(void *) pvUser;
1024	} Ext;
1025	} u;
1026	/** Queue type. */
1027	PDMQUEUETYPE enmType;
1028	/** The interval between checking the queue for events.
1029	* The realtime timer below is used to do the waiting.
1030	* If 0, the queue will use the VM_FF_PDM_QUEUE forced action. */
1031	uint32_t cMilliesInterval;
1032	/** Interval timer. Only used if cMilliesInterval is non-zero. */
1033	PTMTIMERR3 pTimer;
1034	/** Pointer to the VM - R3. */
1035	PVMR3 pVMR3;
1036	/** LIFO of pending items - R3. */
1037	R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR3;
1038	/** Pointer to the VM - R0. */
1039	PVMR0 pVMR0;
1040	/** LIFO of pending items - R0. */
1041	R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR0;
1042	/** Pointer to the GC VM and indicator for GC enabled queue.
1043	* If this is NULL, the queue cannot be used in GC.
1044	*/
1045	PVMRC pVMRC;
1046	/** LIFO of pending items - GC. */
1047	RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingRC;
1048
1049	/** Item size (bytes). */
1050	uint32_t cbItem;
1051	/** Number of items in the queue. */
1052	uint32_t cItems;
1053	/** Index to the free head (where we insert). */
1054	uint32_t volatile iFreeHead;
1055	/** Index to the free tail (where we remove). */
1056	uint32_t volatile iFreeTail;
1057
1058	/** Unique queue name. */
1059	R3PTRTYPE(const char *) pszName;
1060	#if HC_ARCH_BITS == 32
1061	RTR3PTR Alignment1;
1062	#endif
1063	/** Stat: Times PDMQueueAlloc fails. */
1064	STAMCOUNTER StatAllocFailures;
1065	/** Stat: PDMQueueInsert calls. */
1066	STAMCOUNTER StatInsert;
1067	/** Stat: Queue flushes. */
1068	STAMCOUNTER StatFlush;
1069	/** Stat: Queue flushes with pending items left over. */
1070	STAMCOUNTER StatFlushLeftovers;
1071	#ifdef VBOX_WITH_STATISTICS
1072	/** State: Profiling the flushing. */
1073	STAMPROFILE StatFlushPrf;
1074	/** State: Pending items. */
1075	uint32_t volatile cStatPending;
1076	uint32_t volatile cAlignment;
1077	#endif
1078
1079	/** Array of pointers to free items. Variable size. */
1080	struct PDMQUEUEFREEITEM
1081	{
1082	/** Pointer to the free item - HC Ptr. */
1083	R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR3;
1084	/** Pointer to the free item - HC Ptr. */
1085	R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR0;
1086	/** Pointer to the free item - GC Ptr. */
1087	RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pItemRC;
1088	#if HC_ARCH_BITS == 64
1089	RTRCPTR Alignment0;
1090	#endif
1091	} aFreeItems[1];
1092	} PDMQUEUE;
1093
1094	/** @name PDM::fQueueFlushing
1095	* @{ */
1096	/** Used to make sure only one EMT will flush the queues.
1097	* Set when an EMT is flushing queues, clear otherwise. */
1098	#define PDM_QUEUE_FLUSH_FLAG_ACTIVE_BIT 0
1099	/** Indicating there are queues with items pending.
1100	* This is make sure we don't miss inserts happening during flushing. The FF
1101	* cannot be used for this since it has to be cleared immediately to prevent
1102	* other EMTs from spinning. */
1103	#define PDM_QUEUE_FLUSH_FLAG_PENDING_BIT 1
1104	/** @} */
1105
1106
1107	/** @name PDM task structures.
1108	* @{ */
1109
1110	/**
1111	* A asynchronous user mode task.
1112	*/
1113	typedef struct PDMTASK
1114	{
1115	/** Task owner type. */
1116	PDMTASKTYPE volatile enmType;
1117	/** Queue flags. */
1118	uint32_t volatile fFlags;
1119	/** User argument for the callback. */
1120	R3PTRTYPE(void *) volatile pvUser;
1121	/** The callback (will be cast according to enmType before callout). */
1122	R3PTRTYPE(PFNRT) volatile pfnCallback;
1123	/** The owner identifier. */
1124	R3PTRTYPE(void *) volatile pvOwner;
1125	/** Task name. */
1126	R3PTRTYPE(const char *) pszName;
1127	/** Number of times already triggered when PDMTaskTrigger was called. */
1128	uint32_t volatile cAlreadyTrigged;
1129	/** Number of runs. */
1130	uint32_t cRuns;
1131	} PDMTASK;
1132	/** Pointer to a PDM task. */
1133	typedef PDMTASK *PPDMTASK;
1134
1135	/**
1136	* A task set.
1137	*
1138	* This is served by one task executor thread.
1139	*/
1140	typedef struct PDMTASKSET
1141	{
1142	/** Magic value (PDMTASKSET_MAGIC). */
1143	uint32_t u32Magic;
1144	/** Set if this task set works for ring-0 and raw-mode. */
1145	bool fRZEnabled;
1146	/** Number of allocated taks. */
1147	uint8_t volatile cAllocated;
1148	/** Base handle value for this set. */
1149	uint16_t uHandleBase;
1150	/** The task executor thread. */
1151	R3PTRTYPE(RTTHREAD) hThread;
1152	/** Event semaphore for waking up the thread when fRZEnabled is set. */
1153	SUPSEMEVENT hEventR0;
1154	/** Event semaphore for waking up the thread when fRZEnabled is clear. */
1155	R3PTRTYPE(RTSEMEVENT) hEventR3;
1156	/** The VM pointer. */
1157	PVM pVM;
1158	/** Padding so fTriggered is in its own cacheline. */
1159	uint64_t au64Padding2[3];
1160
1161	/** Bitmask of triggered tasks. */
1162	uint64_t volatile fTriggered;
1163	/** Shutdown thread indicator. */
1164	bool volatile fShutdown;
1165	/** Padding. */
1166	bool volatile afPadding3[3];
1167	/** Task currently running, UINT32_MAX if idle. */
1168	uint32_t volatile idxRunning;
1169	/** Padding so fTriggered and fShutdown are in their own cacheline. */
1170	uint64_t volatile au64Padding3[6];
1171
1172	/** The individual tasks. (Unallocated tasks have NULL pvOwner.) */
1173	PDMTASK aTasks[64];
1174	} PDMTASKSET;
1175	AssertCompileMemberAlignment(PDMTASKSET, fTriggered, 64);
1176	AssertCompileMemberAlignment(PDMTASKSET, aTasks, 64);
1177	/** Magic value for PDMTASKSET::u32Magic. */
1178	#define PDMTASKSET_MAGIC UINT32_C(0x19320314)
1179	/** Pointer to a task set. */
1180	typedef PDMTASKSET *PPDMTASKSET;
1181
1182	/** @} */
1183
1184
1185	/**
1186	* Queue device helper task operation.
1187	*/
1188	typedef enum PDMDEVHLPTASKOP
1189	{
1190	/** The usual invalid 0 entry. */
1191	PDMDEVHLPTASKOP_INVALID = 0,
1192	/** ISASetIrq */
1193	PDMDEVHLPTASKOP_ISA_SET_IRQ,
1194	/** PCISetIrq */
1195	PDMDEVHLPTASKOP_PCI_SET_IRQ,
1196	/** PCISetIrq */
1197	PDMDEVHLPTASKOP_IOAPIC_SET_IRQ,
1198	/** The usual 32-bit hack. */
1199	PDMDEVHLPTASKOP_32BIT_HACK = 0x7fffffff
1200	} PDMDEVHLPTASKOP;
1201
1202	/**
1203	* Queued Device Helper Task.
1204	*/
1205	typedef struct PDMDEVHLPTASK
1206	{
1207	/** The queue item core (don't touch). */
1208	PDMQUEUEITEMCORE Core;
1209	/** Pointer to the device instance (R3 Ptr). */
1210	PPDMDEVINSR3 pDevInsR3;
1211	/** This operation to perform. */
1212	PDMDEVHLPTASKOP enmOp;
1213	#if HC_ARCH_BITS == 64
1214	uint32_t Alignment0;
1215	#endif
1216	/** Parameters to the operation. */
1217	union PDMDEVHLPTASKPARAMS
1218	{
1219	/**
1220	* PDMDEVHLPTASKOP_ISA_SET_IRQ and PDMDEVHLPTASKOP_IOAPIC_SET_IRQ.
1221	*/
1222	struct PDMDEVHLPTASKISASETIRQ
1223	{
1224	/** The bus:device:function of the device initiating the IRQ. Can be NIL_PCIBDF. */
1225	PCIBDF uBusDevFn;
1226	/** The IRQ */
1227	int iIrq;
1228	/** The new level. */
1229	int iLevel;
1230	/** The IRQ tag and source. */
1231	uint32_t uTagSrc;
1232	} IsaSetIRQ, IoApicSetIRQ;
1233
1234	/**
1235	* PDMDEVHLPTASKOP_PCI_SET_IRQ
1236	*/
1237	struct PDMDEVHLPTASKPCISETIRQ
1238	{
1239	/** Pointer to the PCI device (R3 Ptr). */
1240	R3PTRTYPE(PPDMPCIDEV) pPciDevR3;
1241	/** The IRQ */
1242	int iIrq;
1243	/** The new level. */
1244	int iLevel;
1245	/** The IRQ tag and source. */
1246	uint32_t uTagSrc;
1247	} PciSetIRQ;
1248
1249	/** Expanding the structure. */
1250	uint64_t au64[3];
1251	} u;
1252	} PDMDEVHLPTASK;
1253	/** Pointer to a queued Device Helper Task. */
1254	typedef PDMDEVHLPTASK *PPDMDEVHLPTASK;
1255	/** Pointer to a const queued Device Helper Task. */
1256	typedef const PDMDEVHLPTASK *PCPDMDEVHLPTASK;
1257
1258
1259
1260	/**
1261	* An USB hub registration record.
1262	*/
1263	typedef struct PDMUSBHUB
1264	{
1265	/** The USB versions this hub support.
1266	* Note that 1.1 hubs can take on 2.0 devices. */
1267	uint32_t fVersions;
1268	/** The number of ports on the hub. */
1269	uint32_t cPorts;
1270	/** The number of available ports (0..cPorts). */
1271	uint32_t cAvailablePorts;
1272	/** The driver instance of the hub. */
1273	PPDMDRVINS pDrvIns;
1274	/** Copy of the to the registration structure. */
1275	PDMUSBHUBREG Reg;
1276
1277	/** Pointer to the next hub in the list. */
1278	struct PDMUSBHUB *pNext;
1279	} PDMUSBHUB;
1280
1281	/** Pointer to a const USB HUB registration record. */
1282	typedef const PDMUSBHUB *PCPDMUSBHUB;
1283
1284	/** Pointer to a PDM Async I/O template. */
1285	typedef struct PDMASYNCCOMPLETIONTEMPLATE *PPDMASYNCCOMPLETIONTEMPLATE;
1286
1287	/** Pointer to the main PDM Async completion endpoint class. */
1288	typedef struct PDMASYNCCOMPLETIONEPCLASS *PPDMASYNCCOMPLETIONEPCLASS;
1289
1290	/** Pointer to the global block cache structure. */
1291	typedef struct PDMBLKCACHEGLOBAL *PPDMBLKCACHEGLOBAL;
1292
1293	/**
1294	* PDM VMCPU Instance data.
1295	* Changes to this must checked against the padding of the pdm union in VMCPU!
1296	*/
1297	typedef struct PDMCPU
1298	{
1299	/** The number of entries in the apQueuedCritSectsLeaves table that's currently
1300	* in use. */
1301	uint32_t cQueuedCritSectLeaves;
1302	uint32_t uPadding0; /*< Alignment padding./
1303	/** Critical sections queued in RC/R0 because of contention preventing leave to
1304	* complete. (R3 Ptrs)
1305	* We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1306	R3PTRTYPE(PPDMCRITSECT) apQueuedCritSectLeaves[8];
1307
1308	/** The number of entries in the apQueuedCritSectRwExclLeaves table that's
1309	* currently in use. */
1310	uint32_t cQueuedCritSectRwExclLeaves;
1311	uint32_t uPadding1; /*< Alignment padding./
1312	/** Read/write critical sections queued in RC/R0 because of contention
1313	* preventing exclusive leave to complete. (R3 Ptrs)
1314	* We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1315	R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwExclLeaves[8];
1316
1317	/** The number of entries in the apQueuedCritSectsRwShrdLeaves table that's
1318	* currently in use. */
1319	uint32_t cQueuedCritSectRwShrdLeaves;
1320	uint32_t uPadding2; /*< Alignment padding./
1321	/** Read/write critical sections queued in RC/R0 because of contention
1322	* preventing shared leave to complete. (R3 Ptrs)
1323	* We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1324	R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwShrdLeaves[8];
1325	} PDMCPU;
1326
1327
1328	/**
1329	* PDM VM Instance data.
1330	* Changes to this must checked against the padding of the cfgm union in VM!
1331	*/
1332	typedef struct PDM
1333	{
1334	/** The PDM lock.
1335	* This is used to protect everything that deals with interrupts, i.e.
1336	* the PIC, APIC, IOAPIC and PCI devices plus some PDM functions. */
1337	PDMCRITSECT CritSect;
1338	/** The NOP critical section.
1339	* This is a dummy critical section that will not do any thread
1340	* serialization but instead let all threads enter immediately and
1341	* concurrently. */
1342	PDMCRITSECT NopCritSect;
1343
1344	/** The ring-0 capable task sets (max 128). */
1345	PDMTASKSET aTaskSets[2];
1346	/** Pointer to task sets (max 512). */
1347	R3PTRTYPE(PPDMTASKSET) apTaskSets[8];
1348
1349	/** PCI Buses. */
1350	PDMPCIBUS aPciBuses[PDM_PCI_BUSSES_MAX];
1351	/** IOMMU devices. */
1352	PDMIOMMU aIommus[PDM_IOMMUS_MAX];
1353	/** The register PIC device. */
1354	PDMPIC Pic;
1355	/** The registered APIC device. */
1356	PDMAPIC Apic;
1357	/** The registered I/O APIC device. */
1358	PDMIOAPIC IoApic;
1359	/** The registered HPET device. */
1360	PPDMDEVINSR3 pHpet;
1361
1362	/** List of registered devices. (FIFO) */
1363	R3PTRTYPE(PPDMDEV) pDevs;
1364	/** List of devices instances. (FIFO) */
1365	R3PTRTYPE(PPDMDEVINS) pDevInstances;
1366	/** List of registered USB devices. (FIFO) */
1367	R3PTRTYPE(PPDMUSB) pUsbDevs;
1368	/** List of USB devices instances. (FIFO) */
1369	R3PTRTYPE(PPDMUSBINS) pUsbInstances;
1370	/** List of registered drivers. (FIFO) */
1371	R3PTRTYPE(PPDMDRV) pDrvs;
1372	/** The registered firmware device (can be NULL). */
1373	R3PTRTYPE(PPDMFW) pFirmware;
1374	/** The registered DMAC device. */
1375	R3PTRTYPE(PPDMDMAC) pDmac;
1376	/** The registered RTC device. */
1377	R3PTRTYPE(PPDMRTC) pRtc;
1378	/** The registered USB HUBs. (FIFO) */
1379	R3PTRTYPE(PPDMUSBHUB) pUsbHubs;
1380
1381	/** @name Queues
1382	* @{ */
1383	/** Queue in which devhlp tasks are queued for R3 execution - R3 Ptr. */
1384	R3PTRTYPE(PPDMQUEUE) pDevHlpQueueR3;
1385	/** Queue in which devhlp tasks are queued for R3 execution - R0 Ptr. */
1386	R0PTRTYPE(PPDMQUEUE) pDevHlpQueueR0;
1387	/** Queue in which devhlp tasks are queued for R3 execution - RC Ptr. */
1388	RCPTRTYPE(PPDMQUEUE) pDevHlpQueueRC;
1389	/** Pointer to the queue which should be manually flushed - RC Ptr.
1390	* Only touched by EMT. */
1391	RCPTRTYPE(struct PDMQUEUE *) pQueueFlushRC;
1392	/** Pointer to the queue which should be manually flushed - R0 Ptr.
1393	* Only touched by EMT. */
1394	R0PTRTYPE(struct PDMQUEUE *) pQueueFlushR0;
1395	/** Bitmask controlling the queue flushing.
1396	* See PDM_QUEUE_FLUSH_FLAG_ACTIVE and PDM_QUEUE_FLUSH_FLAG_PENDING. */
1397	uint32_t volatile fQueueFlushing;
1398	/** @} */
1399
1400	/** The current IRQ tag (tracing purposes). */
1401	uint32_t volatile uIrqTag;
1402
1403	/** Pending reset flags (PDMVMRESET_F_XXX). */
1404	uint32_t volatile fResetFlags;
1405
1406	/** Set by pdmR3LoadExec for use in assertions. */
1407	bool fStateLoaded;
1408	/** Alignment padding. */
1409	bool afPadding[3];
1410
1411	/** The tracing ID of the next device instance.
1412	*
1413	* @remarks We keep the device tracing ID seperate from the rest as these are
1414	* then more likely to end up with the same ID from one run to
1415	* another, making analysis somewhat easier. Drivers and USB devices
1416	* are more volatile and can be changed at runtime, thus these are much
1417	* less likely to remain stable, so just heap them all together. */
1418	uint32_t idTracingDev;
1419	/** The tracing ID of the next driver instance, USB device instance or other
1420	* PDM entity requiring an ID. */
1421	uint32_t idTracingOther;
1422
1423	/** @name VMM device heap
1424	* @{ */
1425	/** The heap size. */
1426	uint32_t cbVMMDevHeap;
1427	/** Free space. */
1428	uint32_t cbVMMDevHeapLeft;
1429	/** Pointer to the heap base (MMIO2 ring-3 mapping). NULL if not registered. */
1430	RTR3PTR pvVMMDevHeap;
1431	/** Ring-3 mapping/unmapping notification callback for the user. */
1432	PFNPDMVMMDEVHEAPNOTIFY pfnVMMDevHeapNotify;
1433	/** The current mapping. NIL_RTGCPHYS if not mapped or registered. */
1434	RTGCPHYS GCPhysVMMDevHeap;
1435	/** @} */
1436
1437	/** Number of times a critical section leave request needed to be queued for ring-3 execution. */
1438	STAMCOUNTER StatQueuedCritSectLeaves;
1439	} PDM;
1440	AssertCompileMemberAlignment(PDM, CritSect, 8);
1441	AssertCompileMemberAlignment(PDM, aTaskSets, 64);
1442	AssertCompileMemberAlignment(PDM, StatQueuedCritSectLeaves, 8);
1443	AssertCompileMemberAlignment(PDM, GCPhysVMMDevHeap, sizeof(RTGCPHYS));
1444	/** Pointer to PDM VM instance data. */
1445	typedef PDM *PPDM;
1446
1447
1448	/**
1449	* PDM data kept in the ring-0 GVM.
1450	*/
1451	typedef struct PDMR0PERVM
1452	{
1453	/** PCI Buses, ring-0 data. */
1454	PDMPCIBUSR0 aPciBuses[PDM_PCI_BUSSES_MAX];
1455	/** IOMMUs, ring-0 data. */
1456	PDMIOMMUR0 aIommus[PDM_IOMMUS_MAX];
1457	/** Number of valid ring-0 device instances (apDevInstances). */
1458	uint32_t cDevInstances;
1459	uint32_t u32Padding;
1460	/** Pointer to ring-0 device instances. */
1461	R0PTRTYPE(struct PDMDEVINSR0 *) apDevInstances[190];
1462	} PDMR0PERVM;
1463
1464
1465	/**
1466	* PDM data kept in the UVM.
1467	*/
1468	typedef struct PDMUSERPERVM
1469	{
1470	/** @todo move more stuff over here. */
1471
1472	/** Linked list of timer driven PDM queues.
1473	* Currently serialized by PDM::CritSect. */
1474	R3PTRTYPE(struct PDMQUEUE *) pQueuesTimer;
1475	/** Linked list of force action driven PDM queues.
1476	* Currently serialized by PDM::CritSect. */
1477	R3PTRTYPE(struct PDMQUEUE *) pQueuesForced;
1478
1479	/** Lock protecting the lists below it. */
1480	RTCRITSECT ListCritSect;
1481	/** Pointer to list of loaded modules. */
1482	PPDMMOD pModules;
1483	/** List of initialized critical sections. (LIFO) */
1484	R3PTRTYPE(PPDMCRITSECTINT) pCritSects;
1485	/** List of initialized read/write critical sections. (LIFO) */
1486	R3PTRTYPE(PPDMCRITSECTRWINT) pRwCritSects;
1487	/** Head of the PDM Thread list. (singly linked) */
1488	R3PTRTYPE(PPDMTHREAD) pThreads;
1489	/** Tail of the PDM Thread list. (singly linked) */
1490	R3PTRTYPE(PPDMTHREAD) pThreadsTail;
1491
1492	/** @name PDM Async Completion
1493	* @{ */
1494	/** Pointer to the array of supported endpoint classes. */
1495	PPDMASYNCCOMPLETIONEPCLASS apAsyncCompletionEndpointClass[PDMASYNCCOMPLETIONEPCLASSTYPE_MAX];
1496	/** Head of the templates. Singly linked, protected by ListCritSect. */
1497	R3PTRTYPE(PPDMASYNCCOMPLETIONTEMPLATE) pAsyncCompletionTemplates;
1498	/** @} */
1499
1500	/** Global block cache data. */
1501	R3PTRTYPE(PPDMBLKCACHEGLOBAL) pBlkCacheGlobal;
1502	#ifdef VBOX_WITH_NETSHAPER
1503	/** Pointer to network shaper instance. */
1504	R3PTRTYPE(PPDMNETSHAPER) pNetShaper;
1505	#endif /* VBOX_WITH_NETSHAPER */
1506
1507	} PDMUSERPERVM;
1508	/** Pointer to the PDM data kept in the UVM. */
1509	typedef PDMUSERPERVM *PPDMUSERPERVM;
1510
1511
1512
1513	/*******************************************************************************
1514	* Global Variables *
1515	*******************************************************************************/
1516	#ifdef IN_RING3
1517	extern const PDMDRVHLPR3 g_pdmR3DrvHlp;
1518	extern const PDMDEVHLPR3 g_pdmR3DevHlpTrusted;
1519	# ifdef VBOX_WITH_DBGF_TRACING
1520	extern const PDMDEVHLPR3 g_pdmR3DevHlpTracing;
1521	# endif
1522	extern const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted;
1523	extern const PDMPICHLP g_pdmR3DevPicHlp;
1524	extern const PDMIOAPICHLP g_pdmR3DevIoApicHlp;
1525	extern const PDMFWHLPR3 g_pdmR3DevFirmwareHlp;
1526	extern const PDMPCIHLPR3 g_pdmR3DevPciHlp;
1527	extern const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp;
1528	extern const PDMDMACHLP g_pdmR3DevDmacHlp;
1529	extern const PDMRTCHLP g_pdmR3DevRtcHlp;
1530	extern const PDMHPETHLPR3 g_pdmR3DevHpetHlp;
1531	extern const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp;
1532	#endif
1533
1534
1535	/*******************************************************************************
1536	* Defined Constants And Macros *
1537	*******************************************************************************/
1538	/** @def PDMDEV_ASSERT_DEVINS
1539	* Asserts the validity of the device instance.
1540	*/
1541	#ifdef VBOX_STRICT
1542	# define PDMDEV_ASSERT_DEVINS(pDevIns) \
1543	do { \
1544	AssertPtr(pDevIns); \
1545	Assert(pDevIns->u32Version == PDM_DEVINS_VERSION); \
1546	Assert(pDevIns->CTX_SUFF(pvInstanceDataFor) == (void *)&pDevIns->achInstanceData[0]); \
1547	} while (0)
1548	#else
1549	# define PDMDEV_ASSERT_DEVINS(pDevIns) do { } while (0)
1550	#endif
1551
1552	/** @def PDMDRV_ASSERT_DRVINS
1553	* Asserts the validity of the driver instance.
1554	*/
1555	#ifdef VBOX_STRICT
1556	# define PDMDRV_ASSERT_DRVINS(pDrvIns) \
1557	do { \
1558	AssertPtr(pDrvIns); \
1559	Assert(pDrvIns->u32Version == PDM_DRVINS_VERSION); \
1560	Assert(pDrvIns->CTX_SUFF(pvInstanceData) == (void *)&pDrvIns->achInstanceData[0]); \
1561	} while (0)
1562	#else
1563	# define PDMDRV_ASSERT_DRVINS(pDrvIns) do { } while (0)
1564	#endif
1565
1566
1567	/*******************************************************************************
1568	* Internal Functions *
1569	*******************************************************************************/
1570	#ifdef IN_RING3
1571	bool pdmR3IsValidName(const char *pszName);
1572
1573	int pdmR3CritSectBothInitStats(PVM pVM);
1574	void pdmR3CritSectBothRelocate(PVM pVM);
1575	int pdmR3CritSectBothDeleteDevice(PVM pVM, PPDMDEVINS pDevIns);
1576	int pdmR3CritSectBothDeleteDriver(PVM pVM, PPDMDRVINS pDrvIns);
1577	int pdmR3CritSectInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1578	const char *pszNameFmt, va_list va);
1579	int pdmR3CritSectInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1580	const char *pszNameFmt, ...);
1581	int pdmR3CritSectInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1582	const char *pszNameFmt, ...);
1583	int pdmR3CritSectRwInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1584	const char *pszNameFmt, va_list va);
1585	int pdmR3CritSectRwInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1586	const char *pszNameFmt, ...);
1587	int pdmR3CritSectRwInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1588	const char *pszNameFmt, ...);
1589
1590	int pdmR3DevInit(PVM pVM);
1591	int pdmR3DevInitComplete(PVM pVM);
1592	PPDMDEV pdmR3DevLookup(PVM pVM, const char *pszName);
1593	int pdmR3DevFindLun(PVM pVM, const char pszDevice, unsigned iInstance, unsigned iLun, PPDMLUN ppLun);
1594	DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem);
1595
1596	int pdmR3UsbLoadModules(PVM pVM);
1597	int pdmR3UsbInstantiateDevices(PVM pVM);
1598	PPDMUSB pdmR3UsbLookup(PVM pVM, const char *pszName);
1599	int pdmR3UsbRegisterHub(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fVersions, uint32_t cPorts, PCPDMUSBHUBREG pUsbHubReg, PPCPDMUSBHUBHLP ppUsbHubHlp);
1600	int pdmR3UsbVMInitComplete(PVM pVM);
1601
1602	int pdmR3DrvInit(PVM pVM);
1603	int pdmR3DrvInstantiate(PVM pVM, PCFGMNODE pNode, PPDMIBASE pBaseInterface, PPDMDRVINS pDrvAbove,
1604	PPDMLUN pLun, PPDMIBASE *ppBaseInterface);
1605	int pdmR3DrvDetach(PPDMDRVINS pDrvIns, uint32_t fFlags);
1606	void pdmR3DrvDestroyChain(PPDMDRVINS pDrvIns, uint32_t fFlags);
1607	PPDMDRV pdmR3DrvLookup(PVM pVM, const char *pszName);
1608
1609	int pdmR3LdrInitU(PUVM pUVM);
1610	void pdmR3LdrTermU(PUVM pUVM, bool fFinal);
1611	char pdmR3FileR3(const char pszFile, bool fShared);
1612	int pdmR3LoadR3U(PUVM pUVM, const char pszFilename, const char pszName);
1613
1614	void pdmR3QueueRelocate(PVM pVM, RTGCINTPTR offDelta);
1615
1616	int pdmR3TaskInit(PVM pVM);
1617	void pdmR3TaskTerm(PVM pVM);
1618
1619	int pdmR3ThreadCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
1620	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1621	int pdmR3ThreadCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADUSB pfnThread,
1622	PFNPDMTHREADWAKEUPUSB pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1623	int pdmR3ThreadCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDRV pfnThread,
1624	PFNPDMTHREADWAKEUPDRV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1625	int pdmR3ThreadDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1626	int pdmR3ThreadDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1627	int pdmR3ThreadDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1628	void pdmR3ThreadDestroyAll(PVM pVM);
1629	int pdmR3ThreadResumeAll(PVM pVM);
1630	int pdmR3ThreadSuspendAll(PVM pVM);
1631
1632	#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
1633	int pdmR3AsyncCompletionInit(PVM pVM);
1634	int pdmR3AsyncCompletionTerm(PVM pVM);
1635	void pdmR3AsyncCompletionResume(PVM pVM);
1636	int pdmR3AsyncCompletionTemplateCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEDEV pfnCompleted, const char *pszDesc);
1637	int pdmR3AsyncCompletionTemplateCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate,
1638	PFNPDMASYNCCOMPLETEDRV pfnCompleted, void pvTemplateUser, const char pszDesc);
1639	int pdmR3AsyncCompletionTemplateCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEUSB pfnCompleted, const char *pszDesc);
1640	int pdmR3AsyncCompletionTemplateDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1641	int pdmR3AsyncCompletionTemplateDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1642	int pdmR3AsyncCompletionTemplateDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1643	#endif
1644
1645	#ifdef VBOX_WITH_NETSHAPER
1646	int pdmR3NetShaperInit(PVM pVM);
1647	int pdmR3NetShaperTerm(PVM pVM);
1648	#endif
1649
1650	int pdmR3BlkCacheInit(PVM pVM);
1651	void pdmR3BlkCacheTerm(PVM pVM);
1652	int pdmR3BlkCacheResume(PVM pVM);
1653
1654	#endif /* IN_RING3 */
1655
1656	void pdmLock(PVMCC pVM);
1657	int pdmLockEx(PVMCC pVM, int rc);
1658	void pdmUnlock(PVMCC pVM);
1659
1660	#if defined(IN_RING3) \|\| defined(IN_RING0)
1661	void pdmCritSectRwLeaveSharedQueued(PPDMCRITSECTRW pThis);
1662	void pdmCritSectRwLeaveExclQueued(PPDMCRITSECTRW pThis);
1663	#endif
1664
1665	#ifdef IN_RING0
1666	DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc);
1667	#endif
1668
1669	#ifdef VBOX_WITH_DBGF_TRACING
1670	# ifdef IN_RING3
1671	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
1672	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1673	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
1674	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts);
1675	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port);
1676	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts);
1677	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
1678	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
1679	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
1680	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion);
1681	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys);
1682	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion);
1683	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1684	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1685	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1686	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1687	DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1688	DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1689	DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1690	DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1691	# elif defined(IN_RING0)
1692	DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
1693	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1694	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
1695	void *pvUser);
1696	DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
1697	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser);
1698	DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1699	DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1700	DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1701	DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1702	DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1703	DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1704	DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1705	DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1706	# else
1707	# error "Invalid environment selected"
1708	# endif
1709	#endif
1710
1711
1712	/** @} */
1713
1714	RT_C_DECLS_END
1715
1716	#endif /* !VMM_INCLUDED_SRC_include_PDMInternal_h */
1717

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source: vbox/trunk/src/VBox/VMM/include/PDMInternal.h@ 86661

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