VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PDMInternal.h@ 90486

Last change on this file since 90486 was 90486, checked in by vboxsync, 4 years ago

VMM/PDM: Tighten read/write critical section code a bit. bugref:6695
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 70.7 KB
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1/* $Id: PDMInternal.h 90486 2021-08-02 20:40:40Z vboxsync $ */
2/** @file
3 * PDM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_PDMInternal_h
19#define VMM_INCLUDED_SRC_include_PDMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/types.h>
25#include <VBox/param.h>
26#include <VBox/vmm/cfgm.h>
27#include <VBox/vmm/stam.h>
28#include <VBox/vusb.h>
29#include <VBox/vmm/iom.h>
30#include <VBox/vmm/pdmasynccompletion.h>
31#ifdef VBOX_WITH_NETSHAPER
32# include <VBox/vmm/pdmnetshaper.h>
33#endif
34#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
35# include <VBox/vmm/pdmasynccompletion.h>
36#endif
37#include <VBox/vmm/pdmblkcache.h>
38#include <VBox/vmm/pdmcommon.h>
39#include <VBox/vmm/pdmtask.h>
40#include <VBox/sup.h>
41#include <VBox/msi.h>
42#include <iprt/assert.h>
43#include <iprt/critsect.h>
44#ifdef IN_RING3
45# include <iprt/thread.h>
46#endif
47
48RT_C_DECLS_BEGIN
49
50
51/** @defgroup grp_pdm_int Internal
52 * @ingroup grp_pdm
53 * @internal
54 * @{
55 */
56
57/** @def PDM_WITH_R3R0_CRIT_SECT
58 * Enables or disabled ring-3/ring-0 critical sections. */
59#if defined(DOXYGEN_RUNNING) || 1
60# define PDM_WITH_R3R0_CRIT_SECT
61#endif
62
63/** @def PDMCRITSECT_STRICT
64 * Enables/disables PDM critsect strictness like deadlock detection. */
65#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECT_STRICT)) \
66 || defined(DOXYGEN_RUNNING)
67# define PDMCRITSECT_STRICT
68#endif
69
70/** @def PDMCRITSECT_STRICT
71 * Enables/disables PDM read/write critsect strictness like deadlock
72 * detection. */
73#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECTRW_STRICT)) \
74 || defined(DOXYGEN_RUNNING)
75# define PDMCRITSECTRW_STRICT
76#endif
77
78/** The maximum device instance (total) size, ring-0/raw-mode capable devices. */
79#define PDM_MAX_DEVICE_INSTANCE_SIZE _4M
80/** The maximum device instance (total) size, ring-3 only devices. */
81#define PDM_MAX_DEVICE_INSTANCE_SIZE_R3 _8M
82/** The maximum size for the DBGF tracing tracking structure allocated for each device. */
83#define PDM_MAX_DEVICE_DBGF_TRACING_TRACK PAGE_SIZE
84
85
86
87/*******************************************************************************
88* Structures and Typedefs *
89*******************************************************************************/
90
91/** Pointer to a PDM Device. */
92typedef struct PDMDEV *PPDMDEV;
93/** Pointer to a pointer to a PDM Device. */
94typedef PPDMDEV *PPPDMDEV;
95
96/** Pointer to a PDM USB Device. */
97typedef struct PDMUSB *PPDMUSB;
98/** Pointer to a pointer to a PDM USB Device. */
99typedef PPDMUSB *PPPDMUSB;
100
101/** Pointer to a PDM Driver. */
102typedef struct PDMDRV *PPDMDRV;
103/** Pointer to a pointer to a PDM Driver. */
104typedef PPDMDRV *PPPDMDRV;
105
106/** Pointer to a PDM Logical Unit. */
107typedef struct PDMLUN *PPDMLUN;
108/** Pointer to a pointer to a PDM Logical Unit. */
109typedef PPDMLUN *PPPDMLUN;
110
111/** Pointer to a DMAC instance. */
112typedef struct PDMDMAC *PPDMDMAC;
113/** Pointer to a RTC instance. */
114typedef struct PDMRTC *PPDMRTC;
115
116/** Pointer to an USB HUB registration record. */
117typedef struct PDMUSBHUB *PPDMUSBHUB;
118
119/**
120 * Supported asynchronous completion endpoint classes.
121 */
122typedef enum PDMASYNCCOMPLETIONEPCLASSTYPE
123{
124 /** File class. */
125 PDMASYNCCOMPLETIONEPCLASSTYPE_FILE = 0,
126 /** Number of supported classes. */
127 PDMASYNCCOMPLETIONEPCLASSTYPE_MAX,
128 /** 32bit hack. */
129 PDMASYNCCOMPLETIONEPCLASSTYPE_32BIT_HACK = 0x7fffffff
130} PDMASYNCCOMPLETIONEPCLASSTYPE;
131
132
133/**
134 * MMIO/IO port registration tracking structure for DBGF tracing.
135 */
136typedef struct PDMDEVINSDBGFTRACK
137{
138 /** Flag whether this tracks a IO port or MMIO registration. */
139 bool fMmio;
140 /** Opaque user data passed during registration. */
141 void *pvUser;
142 /** Type dependent data. */
143 union
144 {
145 /** I/O port registration. */
146 struct
147 {
148 /** IOM I/O port handle. */
149 IOMIOPORTHANDLE hIoPorts;
150 /** Original OUT handler of the device. */
151 PFNIOMIOPORTNEWOUT pfnOut;
152 /** Original IN handler of the device. */
153 PFNIOMIOPORTNEWIN pfnIn;
154 /** Original string OUT handler of the device. */
155 PFNIOMIOPORTNEWOUTSTRING pfnOutStr;
156 /** Original string IN handler of the device. */
157 PFNIOMIOPORTNEWINSTRING pfnInStr;
158 } IoPort;
159 /** MMIO registration. */
160 struct
161 {
162 /** IOM MMIO region handle. */
163 IOMMMIOHANDLE hMmioRegion;
164 /** Original MMIO write handler of the device. */
165 PFNIOMMMIONEWWRITE pfnWrite;
166 /** Original MMIO read handler of the device. */
167 PFNIOMMMIONEWREAD pfnRead;
168 /** Original MMIO fill handler of the device. */
169 PFNIOMMMIONEWFILL pfnFill;
170 } Mmio;
171 } u;
172} PDMDEVINSDBGFTRACK;
173/** Pointer to a MMIO/IO port registration tracking structure. */
174typedef PDMDEVINSDBGFTRACK *PPDMDEVINSDBGFTRACK;
175/** Pointer to a const MMIO/IO port registration tracking structure. */
176typedef const PDMDEVINSDBGFTRACK *PCPDMDEVINSDBGFTRACK;
177
178
179/**
180 * Private device instance data, ring-3.
181 */
182typedef struct PDMDEVINSINTR3
183{
184 /** Pointer to the next instance.
185 * (Head is pointed to by PDM::pDevInstances.) */
186 R3PTRTYPE(PPDMDEVINS) pNextR3;
187 /** Pointer to the next per device instance.
188 * (Head is pointed to by PDMDEV::pInstances.) */
189 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
190 /** Pointer to device structure. */
191 R3PTRTYPE(PPDMDEV) pDevR3;
192 /** Pointer to the list of logical units associated with the device. (FIFO) */
193 R3PTRTYPE(PPDMLUN) pLunsR3;
194 /** Pointer to the asynchronous notification callback set while in
195 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
196 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
197 /** Configuration handle to the instance node. */
198 R3PTRTYPE(PCFGMNODE) pCfgHandle;
199
200 /** R3 pointer to the VM this instance was created for. */
201 PVMR3 pVMR3;
202 /** DBGF trace event source handle if tracing is configured. */
203 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
204 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
205 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
206 /** Index of the next entry to use for tracking. */
207 uint32_t idxDbgfTraceTrackNext;
208 /** Maximum number of records fitting into the single page. */
209 uint32_t cDbgfTraceTrackMax;
210
211 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
212 uint32_t fIntFlags;
213 /** The last IRQ tag (for tracing it thru clearing). */
214 uint32_t uLastIrqTag;
215 /** The ring-0 device index (for making ring-0 calls). */
216 uint32_t idxR0Device;
217} PDMDEVINSINTR3;
218
219
220/**
221 * Private device instance data, ring-0.
222 */
223typedef struct PDMDEVINSINTR0
224{
225 /** Pointer to the VM this instance was created for. */
226 R0PTRTYPE(PGVM) pGVM;
227 /** Pointer to device structure. */
228 R0PTRTYPE(struct PDMDEVREGR0 const *) pRegR0;
229 /** The ring-0 module reference. */
230 RTR0PTR hMod;
231 /** Pointer to the ring-0 mapping of the ring-3 internal data (for uLastIrqTag). */
232 R0PTRTYPE(PDMDEVINSINTR3 *) pIntR3R0;
233 /** Pointer to the ring-0 mapping of the ring-3 instance (for idTracing). */
234 R0PTRTYPE(struct PDMDEVINSR3 *) pInsR3R0;
235 /** DBGF trace event source handle if tracing is configured. */
236 DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
237 /** The device instance memory. */
238 RTR0MEMOBJ hMemObj;
239 /** The ring-3 mapping object. */
240 RTR0MEMOBJ hMapObj;
241 /** The page memory object for tracking MMIO and I/O port registrations when tracing is configured. */
242 RTR0MEMOBJ hDbgfTraceObj;
243 /** Pointer to the base of the page containing the DBGF tracing tracking structures. */
244 PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
245 /** Index of the next entry to use for tracking. */
246 uint32_t idxDbgfTraceTrackNext;
247 /** Maximum number of records fitting into the single page. */
248 uint32_t cDbgfTraceTrackMax;
249 /** Index into PDMR0PERVM::apDevInstances. */
250 uint32_t idxR0Device;
251} PDMDEVINSINTR0;
252
253
254/**
255 * Private device instance data, raw-mode
256 */
257typedef struct PDMDEVINSINTRC
258{
259 /** Pointer to the VM this instance was created for. */
260 RGPTRTYPE(PVM) pVMRC;
261} PDMDEVINSINTRC;
262
263
264/**
265 * Private device instance data.
266 */
267typedef struct PDMDEVINSINT
268{
269 /** Pointer to the next instance (HC Ptr).
270 * (Head is pointed to by PDM::pDevInstances.) */
271 R3PTRTYPE(PPDMDEVINS) pNextR3;
272 /** Pointer to the next per device instance (HC Ptr).
273 * (Head is pointed to by PDMDEV::pInstances.) */
274 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
275 /** Pointer to device structure - HC Ptr. */
276 R3PTRTYPE(PPDMDEV) pDevR3;
277 /** Pointer to the list of logical units associated with the device. (FIFO) */
278 R3PTRTYPE(PPDMLUN) pLunsR3;
279 /** Pointer to the asynchronous notification callback set while in
280 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
281 R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
282 /** Configuration handle to the instance node. */
283 R3PTRTYPE(PCFGMNODE) pCfgHandle;
284
285 /** R3 pointer to the VM this instance was created for. */
286 PVMR3 pVMR3;
287
288 /** R0 pointer to the VM this instance was created for. */
289 R0PTRTYPE(PVMCC) pVMR0;
290
291 /** RC pointer to the VM this instance was created for. */
292 PVMRC pVMRC;
293
294 /** Flags, see PDMDEVINSINT_FLAGS_XXX. */
295 uint32_t fIntFlags;
296 /** The last IRQ tag (for tracing it thru clearing). */
297 uint32_t uLastIrqTag;
298} PDMDEVINSINT;
299
300/** @name PDMDEVINSINT::fIntFlags
301 * @{ */
302/** Used by pdmR3Load to mark device instances it found in the saved state. */
303#define PDMDEVINSINT_FLAGS_FOUND RT_BIT_32(0)
304/** Indicates that the device hasn't been powered on or resumed.
305 * This is used by PDMR3PowerOn, PDMR3Resume, PDMR3Suspend and PDMR3PowerOff
306 * to make sure each device gets exactly one notification for each of those
307 * events. PDMR3Resume and PDMR3PowerOn also makes use of it to bail out on
308 * a failure (already resumed/powered-on devices are suspended).
309 * PDMR3PowerOff resets this flag once before going through the devices to make sure
310 * every device gets the power off notification even if it was suspended before with
311 * PDMR3Suspend.
312 */
313#define PDMDEVINSINT_FLAGS_SUSPENDED RT_BIT_32(1)
314/** Indicates that the device has been reset already. Used by PDMR3Reset. */
315#define PDMDEVINSINT_FLAGS_RESET RT_BIT_32(2)
316#define PDMDEVINSINT_FLAGS_R0_ENABLED RT_BIT_32(3)
317#define PDMDEVINSINT_FLAGS_RC_ENABLED RT_BIT_32(4)
318/** Set if we've called the ring-0 constructor. */
319#define PDMDEVINSINT_FLAGS_R0_CONTRUCT RT_BIT_32(5)
320/** Set if using non-default critical section. */
321#define PDMDEVINSINT_FLAGS_CHANGED_CRITSECT RT_BIT_32(6)
322/** @} */
323
324
325/**
326 * Private USB device instance data.
327 */
328typedef struct PDMUSBINSINT
329{
330 /** The UUID of this instance. */
331 RTUUID Uuid;
332 /** Pointer to the next instance.
333 * (Head is pointed to by PDM::pUsbInstances.) */
334 R3PTRTYPE(PPDMUSBINS) pNext;
335 /** Pointer to the next per USB device instance.
336 * (Head is pointed to by PDMUSB::pInstances.) */
337 R3PTRTYPE(PPDMUSBINS) pPerDeviceNext;
338
339 /** Pointer to device structure. */
340 R3PTRTYPE(PPDMUSB) pUsbDev;
341
342 /** Pointer to the VM this instance was created for. */
343 PVMR3 pVM;
344 /** Pointer to the list of logical units associated with the device. (FIFO) */
345 R3PTRTYPE(PPDMLUN) pLuns;
346 /** The per instance device configuration. */
347 R3PTRTYPE(PCFGMNODE) pCfg;
348 /** Same as pCfg if the configuration should be deleted when detaching the device. */
349 R3PTRTYPE(PCFGMNODE) pCfgDelete;
350 /** The global device configuration. */
351 R3PTRTYPE(PCFGMNODE) pCfgGlobal;
352
353 /** Pointer to the USB hub this device is attached to.
354 * This is NULL if the device isn't connected to any HUB. */
355 R3PTRTYPE(PPDMUSBHUB) pHub;
356 /** The port number that we're connected to. */
357 uint32_t iPort;
358 /** Indicates that the USB device hasn't been powered on or resumed.
359 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
360 bool fVMSuspended;
361 /** Indicates that the USB device has been reset. */
362 bool fVMReset;
363 /** Pointer to the asynchronous notification callback set while in
364 * FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
365 R3PTRTYPE(PFNPDMUSBASYNCNOTIFY) pfnAsyncNotify;
366} PDMUSBINSINT;
367
368
369/**
370 * Private driver instance data.
371 */
372typedef struct PDMDRVINSINT
373{
374 /** Pointer to the driver instance above.
375 * This is NULL for the topmost drive. */
376 R3PTRTYPE(PPDMDRVINS) pUp;
377 /** Pointer to the driver instance below.
378 * This is NULL for the bottommost driver. */
379 R3PTRTYPE(PPDMDRVINS) pDown;
380 /** Pointer to the logical unit this driver chained on. */
381 R3PTRTYPE(PPDMLUN) pLun;
382 /** Pointer to driver structure from which this was instantiated. */
383 R3PTRTYPE(PPDMDRV) pDrv;
384 /** Pointer to the VM this instance was created for, ring-3 context. */
385 PVMR3 pVMR3;
386 /** Pointer to the VM this instance was created for, ring-0 context. */
387 R0PTRTYPE(PVMCC) pVMR0;
388 /** Pointer to the VM this instance was created for, raw-mode context. */
389 PVMRC pVMRC;
390 /** Flag indicating that the driver is being detached and destroyed.
391 * (Helps detect potential recursive detaching.) */
392 bool fDetaching;
393 /** Indicates that the driver hasn't been powered on or resumed.
394 * See PDMDEVINSINT_FLAGS_SUSPENDED. */
395 bool fVMSuspended;
396 /** Indicates that the driver has been reset already. */
397 bool fVMReset;
398 /** Set if allocated on the hyper heap, false if on the ring-3 heap. */
399 bool fHyperHeap;
400 /** Pointer to the asynchronous notification callback set while in
401 * PDMUSBREG::pfnVMSuspend or PDMUSBREG::pfnVMPowerOff. */
402 R3PTRTYPE(PFNPDMDRVASYNCNOTIFY) pfnAsyncNotify;
403 /** Configuration handle to the instance node. */
404 R3PTRTYPE(PCFGMNODE) pCfgHandle;
405 /** Pointer to the ring-0 request handler function. */
406 PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
407} PDMDRVINSINT;
408
409
410/**
411 * Private critical section data.
412 */
413typedef struct PDMCRITSECTINT
414{
415 /** The critical section core which is shared with IPRT.
416 * @note The semaphore is a SUPSEMEVENT. */
417 RTCRITSECT Core;
418 /** Pointer to the next critical section.
419 * This chain is used for relocating pVMRC and device cleanup. */
420 R3PTRTYPE(struct PDMCRITSECTINT *) pNext;
421 /** Owner identifier.
422 * This is pDevIns if the owner is a device. Similarly for a driver or service.
423 * PDMR3CritSectInit() sets this to point to the critsect itself. */
424 RTR3PTR pvKey;
425 /** Set if this critical section is the automatically created default
426 * section of a device. */
427 bool fAutomaticDefaultCritsect;
428 /** Set if the critical section is used by a timer or similar.
429 * See PDMR3DevGetCritSect. */
430 bool fUsedByTimerOrSimilar;
431 /** Alignment padding. */
432 bool afPadding[2+4];
433 /** Support driver event semaphore that is scheduled to be signaled upon leaving
434 * the critical section. This is only for Ring-3 and Ring-0. */
435 SUPSEMEVENT hEventToSignal;
436 /** The lock name. */
437 R3PTRTYPE(const char *) pszName;
438 /** R0/RC lock contention. */
439 STAMCOUNTER StatContentionRZLock;
440 /** R0/RC lock contention, returning rcBusy or VERR_SEM_BUSY (try). */
441 STAMCOUNTER StatContentionRZLockBusy;
442 /** R0/RC unlock contention. */
443 STAMCOUNTER StatContentionRZUnlock;
444 /** R3 lock contention. */
445 STAMCOUNTER StatContentionR3;
446 /** Profiling waiting on the lock (all rings). */
447 STAMPROFILE StatContentionWait;
448 /** Profiling the time the section is locked. */
449 STAMPROFILEADV StatLocked;
450} PDMCRITSECTINT;
451AssertCompileMemberAlignment(PDMCRITSECTINT, StatContentionRZLock, 8);
452/** Pointer to private critical section data. */
453typedef PDMCRITSECTINT *PPDMCRITSECTINT;
454
455/** Special magic value set when we failed to abort entering in ring-0 due to a
456 * timeout, interruption or pending thread termination. */
457#define PDMCRITSECT_MAGIC_FAILED_ABORT UINT32_C(0x0bad0326)
458
459/** Indicates that the critical section is queued for unlock.
460 * PDMCritSectIsOwner and PDMCritSectIsOwned optimizations. */
461#define PDMCRITSECT_FLAGS_PENDING_UNLOCK RT_BIT_32(17)
462
463
464/**
465 * Private critical section data.
466 */
467typedef struct PDMCRITSECTRWINT
468{
469 /** The read/write critical section core which is shared with IPRT.
470 * @note The semaphores are SUPSEMEVENT and SUPSEMEVENTMULTI. */
471 RTCRITSECTRW Core;
472
473 /** Pointer to the next critical section.
474 * This chain is used for relocating pVMRC and device cleanup. */
475 R3PTRTYPE(struct PDMCRITSECTRWINT *) pNext;
476 /** Owner identifier.
477 * This is pDevIns if the owner is a device. Similarly for a driver or service.
478 * PDMR3CritSectInit() sets this to point to the critsect itself. */
479 RTR3PTR pvKey;
480 /** The lock name. */
481 R3PTRTYPE(const char *) pszName;
482 /** R0/RC write lock contention. */
483 STAMCOUNTER StatContentionRZEnterExcl;
484 /** R0/RC write unlock contention. */
485 STAMCOUNTER StatContentionRZLeaveExcl;
486 /** R0/RC read lock contention. */
487 STAMCOUNTER StatContentionRZEnterShared;
488 /** R0/RC read unlock contention. */
489 STAMCOUNTER StatContentionRZLeaveShared;
490 /** R0/RC writes. */
491 STAMCOUNTER StatRZEnterExcl;
492 /** R0/RC reads. */
493 STAMCOUNTER StatRZEnterShared;
494 /** R3 write lock contention. */
495 STAMCOUNTER StatContentionR3EnterExcl;
496 /** R3 read lock contention. */
497 STAMCOUNTER StatContentionR3EnterShared;
498 /** R3 writes. */
499 STAMCOUNTER StatR3EnterExcl;
500 /** R3 reads. */
501 STAMCOUNTER StatR3EnterShared;
502 /** Profiling the time the section is write locked. */
503 STAMPROFILEADV StatWriteLocked;
504} PDMCRITSECTRWINT;
505AssertCompileMemberAlignment(PDMCRITSECTRWINT, StatContentionRZEnterExcl, 8);
506AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u64State, 8);
507/** Pointer to private critical section data. */
508typedef PDMCRITSECTRWINT *PPDMCRITSECTRWINT;
509
510/** Special magic value we set the structure has become corrupted. */
511#define PDMCRITSECTRW_MAGIC_CORRUPT UINT32_C(0x0bad0620)
512
513
514/**
515 * The usual device/driver/internal/external stuff.
516 */
517typedef enum
518{
519 /** The usual invalid entry. */
520 PDMTHREADTYPE_INVALID = 0,
521 /** Device type. */
522 PDMTHREADTYPE_DEVICE,
523 /** USB Device type. */
524 PDMTHREADTYPE_USB,
525 /** Driver type. */
526 PDMTHREADTYPE_DRIVER,
527 /** Internal type. */
528 PDMTHREADTYPE_INTERNAL,
529 /** External type. */
530 PDMTHREADTYPE_EXTERNAL,
531 /** The usual 32-bit hack. */
532 PDMTHREADTYPE_32BIT_HACK = 0x7fffffff
533} PDMTHREADTYPE;
534
535
536/**
537 * The internal structure for the thread.
538 */
539typedef struct PDMTHREADINT
540{
541 /** The VM pointer. */
542 PVMR3 pVM;
543 /** The event semaphore the thread blocks on when not running. */
544 RTSEMEVENTMULTI BlockEvent;
545 /** The event semaphore the thread sleeps on while running. */
546 RTSEMEVENTMULTI SleepEvent;
547 /** Pointer to the next thread. */
548 R3PTRTYPE(struct PDMTHREAD *) pNext;
549 /** The thread type. */
550 PDMTHREADTYPE enmType;
551} PDMTHREADINT;
552
553
554
555/* Must be included after PDMDEVINSINT is defined. */
556#define PDMDEVINSINT_DECLARED
557#define PDMUSBINSINT_DECLARED
558#define PDMDRVINSINT_DECLARED
559#define PDMCRITSECTINT_DECLARED
560#define PDMCRITSECTRWINT_DECLARED
561#define PDMTHREADINT_DECLARED
562#ifdef ___VBox_pdm_h
563# error "Invalid header PDM order. Include PDMInternal.h before VBox/vmm/pdm.h!"
564#endif
565RT_C_DECLS_END
566#include <VBox/vmm/pdm.h>
567RT_C_DECLS_BEGIN
568
569/**
570 * PDM Logical Unit.
571 *
572 * This typically the representation of a physical port on a
573 * device, like for instance the PS/2 keyboard port on the
574 * keyboard controller device. The LUNs are chained on the
575 * device they belong to (PDMDEVINSINT::pLunsR3).
576 */
577typedef struct PDMLUN
578{
579 /** The LUN - The Logical Unit Number. */
580 RTUINT iLun;
581 /** Pointer to the next LUN. */
582 PPDMLUN pNext;
583 /** Pointer to the top driver in the driver chain. */
584 PPDMDRVINS pTop;
585 /** Pointer to the bottom driver in the driver chain. */
586 PPDMDRVINS pBottom;
587 /** Pointer to the device instance which the LUN belongs to.
588 * Either this is set or pUsbIns is set. Both is never set at the same time. */
589 PPDMDEVINS pDevIns;
590 /** Pointer to the USB device instance which the LUN belongs to. */
591 PPDMUSBINS pUsbIns;
592 /** Pointer to the device base interface. */
593 PPDMIBASE pBase;
594 /** Description of this LUN. */
595 const char *pszDesc;
596} PDMLUN;
597
598
599/**
600 * PDM Device, ring-3.
601 */
602typedef struct PDMDEV
603{
604 /** Pointer to the next device (R3 Ptr). */
605 R3PTRTYPE(PPDMDEV) pNext;
606 /** Device name length. (search optimization) */
607 uint32_t cchName;
608 /** Registration structure. */
609 R3PTRTYPE(const struct PDMDEVREGR3 *) pReg;
610 /** Number of instances. */
611 uint32_t cInstances;
612 /** Pointer to chain of instances (R3 Ptr). */
613 PPDMDEVINSR3 pInstances;
614 /** The search path for raw-mode context modules (';' as separator). */
615 char *pszRCSearchPath;
616 /** The search path for ring-0 context modules (';' as separator). */
617 char *pszR0SearchPath;
618} PDMDEV;
619
620
621#if 0
622/**
623 * PDM Device, ring-0.
624 */
625typedef struct PDMDEVR0
626{
627 /** Pointer to the next device. */
628 R0PTRTYPE(PPDMDEVR0) pNext;
629 /** Device name length. (search optimization) */
630 uint32_t cchName;
631 /** Registration structure. */
632 R3PTRTYPE(const struct PDMDEVREGR0 *) pReg;
633 /** Number of instances. */
634 uint32_t cInstances;
635 /** Pointer to chain of instances. */
636 PPDMDEVINSR0 pInstances;
637} PDMDEVR0;
638#endif
639
640
641/**
642 * PDM USB Device.
643 */
644typedef struct PDMUSB
645{
646 /** Pointer to the next device (R3 Ptr). */
647 R3PTRTYPE(PPDMUSB) pNext;
648 /** Device name length. (search optimization) */
649 RTUINT cchName;
650 /** Registration structure. */
651 R3PTRTYPE(const struct PDMUSBREG *) pReg;
652 /** Next instance number. */
653 uint32_t iNextInstance;
654 /** Pointer to chain of instances (R3 Ptr). */
655 R3PTRTYPE(PPDMUSBINS) pInstances;
656} PDMUSB;
657
658
659/**
660 * PDM Driver.
661 */
662typedef struct PDMDRV
663{
664 /** Pointer to the next device. */
665 PPDMDRV pNext;
666 /** Registration structure. */
667 const struct PDMDRVREG * pReg;
668 /** Current number of instances. */
669 uint32_t cInstances;
670 /** The next instance number. */
671 uint32_t iNextInstance;
672 /** The search path for raw-mode context modules (';' as separator). */
673 char *pszRCSearchPath;
674 /** The search path for ring-0 context modules (';' as separator). */
675 char *pszR0SearchPath;
676} PDMDRV;
677
678
679/**
680 * PDM IOMMU, shared ring-3.
681 */
682typedef struct PDMIOMMUR3
683{
684 /** IOMMU index. */
685 uint32_t idxIommu;
686 uint32_t uPadding0; /**< Alignment padding.*/
687
688 /** Pointer to the IOMMU device instance - R3. */
689 PPDMDEVINSR3 pDevInsR3;
690 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
691 DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
692 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
693 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
694 DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
695 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
696 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
697 DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
698} PDMIOMMUR3;
699/** Pointer to a PDM IOMMU instance. */
700typedef PDMIOMMUR3 *PPDMIOMMUR3;
701/** Pointer to a const PDM IOMMU instance. */
702typedef const PDMIOMMUR3 *PCPDMIOMMUR3;
703
704
705/**
706 * PDM IOMMU, ring-0.
707 */
708typedef struct PDMIOMMUR0
709{
710 /** IOMMU index. */
711 uint32_t idxIommu;
712 uint32_t uPadding0; /**< Alignment padding.*/
713
714 /** Pointer to IOMMU device instance. */
715 PPDMDEVINSR0 pDevInsR0;
716 /** @copydoc PDMIOMMUREGR3::pfnMemAccess */
717 DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
718 uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
719 /** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
720 DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
721 uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
722 /** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
723 DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
724} PDMIOMMUR0;
725/** Pointer to a ring-0 IOMMU data. */
726typedef PDMIOMMUR0 *PPDMIOMMUR0;
727/** Pointer to a const ring-0 IOMMU data. */
728typedef const PDMIOMMUR0 *PCPDMIOMMUR0;
729
730/** Pointer to a PDM IOMMU for the current context. */
731#ifdef IN_RING3
732typedef PPDMIOMMUR3 PPDMIOMMU;
733#else
734typedef PPDMIOMMUR0 PPDMIOMMU;
735#endif
736
737
738/**
739 * PDM registered PIC device.
740 */
741typedef struct PDMPIC
742{
743 /** Pointer to the PIC device instance - R3. */
744 PPDMDEVINSR3 pDevInsR3;
745 /** @copydoc PDMPICREG::pfnSetIrq */
746 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
747 /** @copydoc PDMPICREG::pfnGetInterrupt */
748 DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
749
750 /** Pointer to the PIC device instance - R0. */
751 PPDMDEVINSR0 pDevInsR0;
752 /** @copydoc PDMPICREG::pfnSetIrq */
753 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
754 /** @copydoc PDMPICREG::pfnGetInterrupt */
755 DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
756
757 /** Pointer to the PIC device instance - RC. */
758 PPDMDEVINSRC pDevInsRC;
759 /** @copydoc PDMPICREG::pfnSetIrq */
760 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
761 /** @copydoc PDMPICREG::pfnGetInterrupt */
762 DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
763 /** Alignment padding. */
764 RTRCPTR RCPtrPadding;
765} PDMPIC;
766
767
768/**
769 * PDM registered APIC device.
770 */
771typedef struct PDMAPIC
772{
773 /** Pointer to the APIC device instance - R3 Ptr. */
774 PPDMDEVINSR3 pDevInsR3;
775 /** Pointer to the APIC device instance - R0 Ptr. */
776 PPDMDEVINSR0 pDevInsR0;
777 /** Pointer to the APIC device instance - RC Ptr. */
778 PPDMDEVINSRC pDevInsRC;
779 uint8_t Alignment[4];
780} PDMAPIC;
781
782
783/**
784 * PDM registered I/O APIC device.
785 */
786typedef struct PDMIOAPIC
787{
788 /** Pointer to the I/O APIC device instance - R3 Ptr. */
789 PPDMDEVINSR3 pDevInsR3;
790 /** @copydoc PDMIOAPICREG::pfnSetIrq */
791 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
792 /** @copydoc PDMIOAPICREG::pfnSendMsi */
793 DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
794 /** @copydoc PDMIOAPICREG::pfnSetEoi */
795 DECLR3CALLBACKMEMBER(void, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
796
797 /** Pointer to the I/O APIC device instance - R0. */
798 PPDMDEVINSR0 pDevInsR0;
799 /** @copydoc PDMIOAPICREG::pfnSetIrq */
800 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
801 /** @copydoc PDMIOAPICREG::pfnSendMsi */
802 DECLR0CALLBACKMEMBER(void, pfnSendMsiR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
803 /** @copydoc PDMIOAPICREG::pfnSetEoi */
804 DECLR0CALLBACKMEMBER(void, pfnSetEoiR0,(PPDMDEVINS pDevIns, uint8_t u8Vector));
805
806 /** Pointer to the I/O APIC device instance - RC Ptr. */
807 PPDMDEVINSRC pDevInsRC;
808 /** @copydoc PDMIOAPICREG::pfnSetIrq */
809 DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
810 /** @copydoc PDMIOAPICREG::pfnSendMsi */
811 DECLRCCALLBACKMEMBER(void, pfnSendMsiRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
812 /** @copydoc PDMIOAPICREG::pfnSendMsi */
813 DECLRCCALLBACKMEMBER(void, pfnSetEoiRC,(PPDMDEVINS pDevIns, uint8_t u8Vector));
814} PDMIOAPIC;
815/** Pointer to a PDM IOAPIC instance. */
816typedef PDMIOAPIC *PPDMIOAPIC;
817/** Pointer to a const PDM IOAPIC instance. */
818typedef PDMIOAPIC const *PCPDMIOAPIC;
819
820/** Maximum number of PCI busses for a VM. */
821#define PDM_PCI_BUSSES_MAX 8
822/** Maximum number of IOMMUs (at most one per PCI bus). */
823#define PDM_IOMMUS_MAX PDM_PCI_BUSSES_MAX
824
825
826#ifdef IN_RING3
827/**
828 * PDM registered firmware device.
829 */
830typedef struct PDMFW
831{
832 /** Pointer to the firmware device instance. */
833 PPDMDEVINSR3 pDevIns;
834 /** Copy of the registration structure. */
835 PDMFWREG Reg;
836} PDMFW;
837/** Pointer to a firmware instance. */
838typedef PDMFW *PPDMFW;
839#endif
840
841
842/**
843 * PDM PCI bus instance.
844 */
845typedef struct PDMPCIBUS
846{
847 /** PCI bus number. */
848 uint32_t iBus;
849 uint32_t uPadding0; /**< Alignment padding.*/
850
851 /** Pointer to PCI bus device instance. */
852 PPDMDEVINSR3 pDevInsR3;
853 /** @copydoc PDMPCIBUSREGR3::pfnSetIrqR3 */
854 DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
855
856 /** @copydoc PDMPCIBUSREGR3::pfnRegisterR3 */
857 DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
858 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
859 /** @copydoc PDMPCIBUSREGR3::pfnRegisterMsiR3 */
860 DECLR3CALLBACKMEMBER(int, pfnRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
861 /** @copydoc PDMPCIBUSREGR3::pfnIORegionRegisterR3 */
862 DECLR3CALLBACKMEMBER(int, pfnIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
863 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
864 uint64_t hHandle, PFNPCIIOREGIONMAP pfnCallback));
865 /** @copydoc PDMPCIBUSREGR3::pfnInterceptConfigAccesses */
866 DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
867 PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
868 /** @copydoc PDMPCIBUSREGR3::pfnConfigWrite */
869 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
870 uint32_t uAddress, unsigned cb, uint32_t u32Value));
871 /** @copydoc PDMPCIBUSREGR3::pfnConfigRead */
872 DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
873 uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
874} PDMPCIBUS;
875/** Pointer to a PDM PCI Bus instance. */
876typedef PDMPCIBUS *PPDMPCIBUS;
877/** Pointer to a const PDM PCI Bus instance. */
878typedef const PDMPCIBUS *PCPDMPCIBUS;
879
880
881/**
882 * Ring-0 PDM PCI bus instance data.
883 */
884typedef struct PDMPCIBUSR0
885{
886 /** PCI bus number. */
887 uint32_t iBus;
888 uint32_t uPadding0; /**< Alignment padding.*/
889 /** Pointer to PCI bus device instance. */
890 PPDMDEVINSR0 pDevInsR0;
891 /** @copydoc PDMPCIBUSREGR0::pfnSetIrq */
892 DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
893} PDMPCIBUSR0;
894/** Pointer to the ring-0 PCI bus data. */
895typedef PDMPCIBUSR0 *PPDMPCIBUSR0;
896/** Pointer to the const ring-0 PCI bus data. */
897typedef const PDMPCIBUSR0 *PCPDMPCIBUSR0;
898
899
900#ifdef IN_RING3
901/**
902 * PDM registered DMAC (DMA Controller) device.
903 */
904typedef struct PDMDMAC
905{
906 /** Pointer to the DMAC device instance. */
907 PPDMDEVINSR3 pDevIns;
908 /** Copy of the registration structure. */
909 PDMDMACREG Reg;
910} PDMDMAC;
911
912
913/**
914 * PDM registered RTC (Real Time Clock) device.
915 */
916typedef struct PDMRTC
917{
918 /** Pointer to the RTC device instance. */
919 PPDMDEVINSR3 pDevIns;
920 /** Copy of the registration structure. */
921 PDMRTCREG Reg;
922} PDMRTC;
923
924#endif /* IN_RING3 */
925
926/**
927 * Module type.
928 */
929typedef enum PDMMODTYPE
930{
931 /** Raw-mode (RC) context module. */
932 PDMMOD_TYPE_RC,
933 /** Ring-0 (host) context module. */
934 PDMMOD_TYPE_R0,
935 /** Ring-3 (host) context module. */
936 PDMMOD_TYPE_R3
937} PDMMODTYPE;
938
939
940/** The module name length including the terminator. */
941#define PDMMOD_NAME_LEN 32
942
943/**
944 * Loaded module instance.
945 */
946typedef struct PDMMOD
947{
948 /** Module name. This is used for referring to
949 * the module internally, sort of like a handle. */
950 char szName[PDMMOD_NAME_LEN];
951 /** Module type. */
952 PDMMODTYPE eType;
953 /** Loader module handle. Not used for R0 modules. */
954 RTLDRMOD hLdrMod;
955 /** Loaded address.
956 * This is the 'handle' for R0 modules. */
957 RTUINTPTR ImageBase;
958 /** Old loaded address.
959 * This is used during relocation of GC modules. Not used for R0 modules. */
960 RTUINTPTR OldImageBase;
961 /** Where the R3 HC bits are stored.
962 * This can be equal to ImageBase but doesn't have to. Not used for R0 modules. */
963 void *pvBits;
964
965 /** Pointer to next module. */
966 struct PDMMOD *pNext;
967 /** Module filename. */
968 char szFilename[1];
969} PDMMOD;
970/** Pointer to loaded module instance. */
971typedef PDMMOD *PPDMMOD;
972
973
974
975/** Extra space in the free array. */
976#define PDMQUEUE_FREE_SLACK 16
977
978/**
979 * Queue type.
980 */
981typedef enum PDMQUEUETYPE
982{
983 /** Device consumer. */
984 PDMQUEUETYPE_DEV = 1,
985 /** Driver consumer. */
986 PDMQUEUETYPE_DRV,
987 /** Internal consumer. */
988 PDMQUEUETYPE_INTERNAL,
989 /** External consumer. */
990 PDMQUEUETYPE_EXTERNAL
991} PDMQUEUETYPE;
992
993/** Pointer to a PDM Queue. */
994typedef struct PDMQUEUE *PPDMQUEUE;
995
996/**
997 * PDM Queue.
998 */
999typedef struct PDMQUEUE
1000{
1001 /** Pointer to the next queue in the list. */
1002 R3PTRTYPE(PPDMQUEUE) pNext;
1003 /** Type specific data. */
1004 union
1005 {
1006 /** PDMQUEUETYPE_DEV */
1007 struct
1008 {
1009 /** Pointer to consumer function. */
1010 R3PTRTYPE(PFNPDMQUEUEDEV) pfnCallback;
1011 /** Pointer to the device instance owning the queue. */
1012 R3PTRTYPE(PPDMDEVINS) pDevIns;
1013 } Dev;
1014 /** PDMQUEUETYPE_DRV */
1015 struct
1016 {
1017 /** Pointer to consumer function. */
1018 R3PTRTYPE(PFNPDMQUEUEDRV) pfnCallback;
1019 /** Pointer to the driver instance owning the queue. */
1020 R3PTRTYPE(PPDMDRVINS) pDrvIns;
1021 } Drv;
1022 /** PDMQUEUETYPE_INTERNAL */
1023 struct
1024 {
1025 /** Pointer to consumer function. */
1026 R3PTRTYPE(PFNPDMQUEUEINT) pfnCallback;
1027 } Int;
1028 /** PDMQUEUETYPE_EXTERNAL */
1029 struct
1030 {
1031 /** Pointer to consumer function. */
1032 R3PTRTYPE(PFNPDMQUEUEEXT) pfnCallback;
1033 /** Pointer to user argument. */
1034 R3PTRTYPE(void *) pvUser;
1035 } Ext;
1036 } u;
1037 /** Queue type. */
1038 PDMQUEUETYPE enmType;
1039 /** The interval between checking the queue for events.
1040 * The realtime timer below is used to do the waiting.
1041 * If 0, the queue will use the VM_FF_PDM_QUEUE forced action. */
1042 uint32_t cMilliesInterval;
1043 /** Interval timer. Only used if cMilliesInterval is non-zero. */
1044 TMTIMERHANDLE hTimer;
1045 /** Pointer to the VM - R3. */
1046 PVMR3 pVMR3;
1047 /** LIFO of pending items - R3. */
1048 R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR3;
1049 /** Pointer to the VM - R0. */
1050 PVMR0 pVMR0;
1051 /** LIFO of pending items - R0. */
1052 R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR0;
1053 /** Pointer to the GC VM and indicator for GC enabled queue.
1054 * If this is NULL, the queue cannot be used in GC.
1055 */
1056 PVMRC pVMRC;
1057 /** LIFO of pending items - GC. */
1058 RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingRC;
1059
1060 /** Item size (bytes). */
1061 uint32_t cbItem;
1062 /** Number of items in the queue. */
1063 uint32_t cItems;
1064 /** Index to the free head (where we insert). */
1065 uint32_t volatile iFreeHead;
1066 /** Index to the free tail (where we remove). */
1067 uint32_t volatile iFreeTail;
1068
1069 /** Unique queue name. */
1070 R3PTRTYPE(const char *) pszName;
1071#if HC_ARCH_BITS == 32
1072 RTR3PTR Alignment1;
1073#endif
1074 /** Stat: Times PDMQueueAlloc fails. */
1075 STAMCOUNTER StatAllocFailures;
1076 /** Stat: PDMQueueInsert calls. */
1077 STAMCOUNTER StatInsert;
1078 /** Stat: Queue flushes. */
1079 STAMCOUNTER StatFlush;
1080 /** Stat: Queue flushes with pending items left over. */
1081 STAMCOUNTER StatFlushLeftovers;
1082#ifdef VBOX_WITH_STATISTICS
1083 /** State: Profiling the flushing. */
1084 STAMPROFILE StatFlushPrf;
1085 /** State: Pending items. */
1086 uint32_t volatile cStatPending;
1087 uint32_t volatile cAlignment;
1088#endif
1089
1090 /** Array of pointers to free items. Variable size. */
1091 struct PDMQUEUEFREEITEM
1092 {
1093 /** Pointer to the free item - HC Ptr. */
1094 R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR3;
1095 /** Pointer to the free item - HC Ptr. */
1096 R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR0;
1097 /** Pointer to the free item - GC Ptr. */
1098 RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pItemRC;
1099#if HC_ARCH_BITS == 64
1100 RTRCPTR Alignment0;
1101#endif
1102 } aFreeItems[1];
1103} PDMQUEUE;
1104
1105/** @name PDM::fQueueFlushing
1106 * @{ */
1107/** Used to make sure only one EMT will flush the queues.
1108 * Set when an EMT is flushing queues, clear otherwise. */
1109#define PDM_QUEUE_FLUSH_FLAG_ACTIVE_BIT 0
1110/** Indicating there are queues with items pending.
1111 * This is make sure we don't miss inserts happening during flushing. The FF
1112 * cannot be used for this since it has to be cleared immediately to prevent
1113 * other EMTs from spinning. */
1114#define PDM_QUEUE_FLUSH_FLAG_PENDING_BIT 1
1115/** @} */
1116
1117
1118/** @name PDM task structures.
1119 * @{ */
1120
1121/**
1122 * A asynchronous user mode task.
1123 */
1124typedef struct PDMTASK
1125{
1126 /** Task owner type. */
1127 PDMTASKTYPE volatile enmType;
1128 /** Queue flags. */
1129 uint32_t volatile fFlags;
1130 /** User argument for the callback. */
1131 R3PTRTYPE(void *) volatile pvUser;
1132 /** The callback (will be cast according to enmType before callout). */
1133 R3PTRTYPE(PFNRT) volatile pfnCallback;
1134 /** The owner identifier. */
1135 R3PTRTYPE(void *) volatile pvOwner;
1136 /** Task name. */
1137 R3PTRTYPE(const char *) pszName;
1138 /** Number of times already triggered when PDMTaskTrigger was called. */
1139 uint32_t volatile cAlreadyTrigged;
1140 /** Number of runs. */
1141 uint32_t cRuns;
1142} PDMTASK;
1143/** Pointer to a PDM task. */
1144typedef PDMTASK *PPDMTASK;
1145
1146/**
1147 * A task set.
1148 *
1149 * This is served by one task executor thread.
1150 */
1151typedef struct PDMTASKSET
1152{
1153 /** Magic value (PDMTASKSET_MAGIC). */
1154 uint32_t u32Magic;
1155 /** Set if this task set works for ring-0 and raw-mode. */
1156 bool fRZEnabled;
1157 /** Number of allocated taks. */
1158 uint8_t volatile cAllocated;
1159 /** Base handle value for this set. */
1160 uint16_t uHandleBase;
1161 /** The task executor thread. */
1162 R3PTRTYPE(RTTHREAD) hThread;
1163 /** Event semaphore for waking up the thread when fRZEnabled is set. */
1164 SUPSEMEVENT hEventR0;
1165 /** Event semaphore for waking up the thread when fRZEnabled is clear. */
1166 R3PTRTYPE(RTSEMEVENT) hEventR3;
1167 /** The VM pointer. */
1168 PVM pVM;
1169 /** Padding so fTriggered is in its own cacheline. */
1170 uint64_t au64Padding2[3];
1171
1172 /** Bitmask of triggered tasks. */
1173 uint64_t volatile fTriggered;
1174 /** Shutdown thread indicator. */
1175 bool volatile fShutdown;
1176 /** Padding. */
1177 bool volatile afPadding3[3];
1178 /** Task currently running, UINT32_MAX if idle. */
1179 uint32_t volatile idxRunning;
1180 /** Padding so fTriggered and fShutdown are in their own cacheline. */
1181 uint64_t volatile au64Padding3[6];
1182
1183 /** The individual tasks. (Unallocated tasks have NULL pvOwner.) */
1184 PDMTASK aTasks[64];
1185} PDMTASKSET;
1186AssertCompileMemberAlignment(PDMTASKSET, fTriggered, 64);
1187AssertCompileMemberAlignment(PDMTASKSET, aTasks, 64);
1188/** Magic value for PDMTASKSET::u32Magic. */
1189#define PDMTASKSET_MAGIC UINT32_C(0x19320314)
1190/** Pointer to a task set. */
1191typedef PDMTASKSET *PPDMTASKSET;
1192
1193/** @} */
1194
1195
1196/**
1197 * Queue device helper task operation.
1198 */
1199typedef enum PDMDEVHLPTASKOP
1200{
1201 /** The usual invalid 0 entry. */
1202 PDMDEVHLPTASKOP_INVALID = 0,
1203 /** IsaSetIrq, IoApicSetIrq */
1204 PDMDEVHLPTASKOP_ISA_SET_IRQ,
1205 /** PciSetIrq */
1206 PDMDEVHLPTASKOP_PCI_SET_IRQ,
1207 /** PciSetIrq */
1208 PDMDEVHLPTASKOP_IOAPIC_SET_IRQ,
1209 /** IoApicSendMsi */
1210 PDMDEVHLPTASKOP_IOAPIC_SEND_MSI,
1211 /** IoApicSettEoi */
1212 PDMDEVHLPTASKOP_IOAPIC_SET_EOI,
1213 /** The usual 32-bit hack. */
1214 PDMDEVHLPTASKOP_32BIT_HACK = 0x7fffffff
1215} PDMDEVHLPTASKOP;
1216
1217/**
1218 * Queued Device Helper Task.
1219 */
1220typedef struct PDMDEVHLPTASK
1221{
1222 /** The queue item core (don't touch). */
1223 PDMQUEUEITEMCORE Core;
1224 /** Pointer to the device instance (R3 Ptr). */
1225 PPDMDEVINSR3 pDevInsR3;
1226 /** This operation to perform. */
1227 PDMDEVHLPTASKOP enmOp;
1228#if HC_ARCH_BITS == 64
1229 uint32_t Alignment0;
1230#endif
1231 /** Parameters to the operation. */
1232 union PDMDEVHLPTASKPARAMS
1233 {
1234 /**
1235 * PDMDEVHLPTASKOP_ISA_SET_IRQ and PDMDEVHLPTASKOP_IOAPIC_SET_IRQ.
1236 */
1237 struct PDMDEVHLPTASKISASETIRQ
1238 {
1239 /** The bus:device:function of the device initiating the IRQ. Can be NIL_PCIBDF. */
1240 PCIBDF uBusDevFn;
1241 /** The IRQ */
1242 int iIrq;
1243 /** The new level. */
1244 int iLevel;
1245 /** The IRQ tag and source. */
1246 uint32_t uTagSrc;
1247 } IsaSetIrq, IoApicSetIrq;
1248
1249 /**
1250 * PDMDEVHLPTASKOP_PCI_SET_IRQ
1251 */
1252 struct PDMDEVHLPTASKPCISETIRQ
1253 {
1254 /** Pointer to the PCI device (R3 Ptr). */
1255 R3PTRTYPE(PPDMPCIDEV) pPciDevR3;
1256 /** The IRQ */
1257 int iIrq;
1258 /** The new level. */
1259 int iLevel;
1260 /** The IRQ tag and source. */
1261 uint32_t uTagSrc;
1262 } PciSetIrq;
1263
1264 /**
1265 * PDMDEVHLPTASKOP_IOAPIC_SEND_MSI
1266 */
1267 struct PDMDEVHLPTASKIOAPICSENDMSI
1268 {
1269 /** The bus:device:function of the device sending the MSI. */
1270 PCIBDF uBusDevFn;
1271 /** The MSI. */
1272 MSIMSG Msi;
1273 /** The IRQ tag and source. */
1274 uint32_t uTagSrc;
1275 } IoApicSendMsi;
1276
1277 /**
1278 * PDMDEVHLPTASKOP_IOAPIC_SET_EOI
1279 */
1280 struct PDMDEVHLPTASKIOAPICSETEOI
1281 {
1282 /** The vector corresponding to the EOI. */
1283 uint8_t uVector;
1284 } IoApicSetEoi;
1285
1286 /** Expanding the structure. */
1287 uint64_t au64[3];
1288 } u;
1289} PDMDEVHLPTASK;
1290/** Pointer to a queued Device Helper Task. */
1291typedef PDMDEVHLPTASK *PPDMDEVHLPTASK;
1292/** Pointer to a const queued Device Helper Task. */
1293typedef const PDMDEVHLPTASK *PCPDMDEVHLPTASK;
1294
1295
1296
1297/**
1298 * An USB hub registration record.
1299 */
1300typedef struct PDMUSBHUB
1301{
1302 /** The USB versions this hub support.
1303 * Note that 1.1 hubs can take on 2.0 devices. */
1304 uint32_t fVersions;
1305 /** The number of ports on the hub. */
1306 uint32_t cPorts;
1307 /** The number of available ports (0..cPorts). */
1308 uint32_t cAvailablePorts;
1309 /** The driver instance of the hub. */
1310 PPDMDRVINS pDrvIns;
1311 /** Copy of the to the registration structure. */
1312 PDMUSBHUBREG Reg;
1313
1314 /** Pointer to the next hub in the list. */
1315 struct PDMUSBHUB *pNext;
1316} PDMUSBHUB;
1317
1318/** Pointer to a const USB HUB registration record. */
1319typedef const PDMUSBHUB *PCPDMUSBHUB;
1320
1321/** Pointer to a PDM Async I/O template. */
1322typedef struct PDMASYNCCOMPLETIONTEMPLATE *PPDMASYNCCOMPLETIONTEMPLATE;
1323
1324/** Pointer to the main PDM Async completion endpoint class. */
1325typedef struct PDMASYNCCOMPLETIONEPCLASS *PPDMASYNCCOMPLETIONEPCLASS;
1326
1327/** Pointer to the global block cache structure. */
1328typedef struct PDMBLKCACHEGLOBAL *PPDMBLKCACHEGLOBAL;
1329
1330/**
1331 * PDM VMCPU Instance data.
1332 * Changes to this must checked against the padding of the pdm union in VMCPU!
1333 */
1334typedef struct PDMCPU
1335{
1336 /** The number of entries in the apQueuedCritSectsLeaves table that's currently
1337 * in use. */
1338 uint32_t cQueuedCritSectLeaves;
1339 uint32_t uPadding0; /**< Alignment padding.*/
1340 /** Critical sections queued in RC/R0 because of contention preventing leave to
1341 * complete. (R3 Ptrs)
1342 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1343 R3PTRTYPE(PPDMCRITSECT) apQueuedCritSectLeaves[8];
1344
1345 /** The number of entries in the apQueuedCritSectRwExclLeaves table that's
1346 * currently in use. */
1347 uint32_t cQueuedCritSectRwExclLeaves;
1348 uint32_t uPadding1; /**< Alignment padding.*/
1349 /** Read/write critical sections queued in RC/R0 because of contention
1350 * preventing exclusive leave to complete. (R3 Ptrs)
1351 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1352 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwExclLeaves[8];
1353
1354 /** The number of entries in the apQueuedCritSectsRwShrdLeaves table that's
1355 * currently in use. */
1356 uint32_t cQueuedCritSectRwShrdLeaves;
1357 uint32_t uPadding2; /**< Alignment padding.*/
1358 /** Read/write critical sections queued in RC/R0 because of contention
1359 * preventing shared leave to complete. (R3 Ptrs)
1360 * We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1361 R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwShrdLeaves[8];
1362} PDMCPU;
1363
1364
1365/**
1366 * PDM VM Instance data.
1367 * Changes to this must checked against the padding of the cfgm union in VM!
1368 */
1369typedef struct PDM
1370{
1371 /** The PDM lock.
1372 * This is used to protect everything that deals with interrupts, i.e.
1373 * the PIC, APIC, IOAPIC and PCI devices plus some PDM functions. */
1374 PDMCRITSECT CritSect;
1375 /** The NOP critical section.
1376 * This is a dummy critical section that will not do any thread
1377 * serialization but instead let all threads enter immediately and
1378 * concurrently. */
1379 PDMCRITSECT NopCritSect;
1380
1381 /** The ring-0 capable task sets (max 128). */
1382 PDMTASKSET aTaskSets[2];
1383 /** Pointer to task sets (max 512). */
1384 R3PTRTYPE(PPDMTASKSET) apTaskSets[8];
1385
1386 /** PCI Buses. */
1387 PDMPCIBUS aPciBuses[PDM_PCI_BUSSES_MAX];
1388 /** IOMMU devices. */
1389 PDMIOMMUR3 aIommus[PDM_IOMMUS_MAX];
1390 /** The register PIC device. */
1391 PDMPIC Pic;
1392 /** The registered APIC device. */
1393 PDMAPIC Apic;
1394 /** The registered I/O APIC device. */
1395 PDMIOAPIC IoApic;
1396 /** The registered HPET device. */
1397 PPDMDEVINSR3 pHpet;
1398
1399 /** List of registered devices. (FIFO) */
1400 R3PTRTYPE(PPDMDEV) pDevs;
1401 /** List of devices instances. (FIFO) */
1402 R3PTRTYPE(PPDMDEVINS) pDevInstances;
1403 /** List of registered USB devices. (FIFO) */
1404 R3PTRTYPE(PPDMUSB) pUsbDevs;
1405 /** List of USB devices instances. (FIFO) */
1406 R3PTRTYPE(PPDMUSBINS) pUsbInstances;
1407 /** List of registered drivers. (FIFO) */
1408 R3PTRTYPE(PPDMDRV) pDrvs;
1409 /** The registered firmware device (can be NULL). */
1410 R3PTRTYPE(PPDMFW) pFirmware;
1411 /** The registered DMAC device. */
1412 R3PTRTYPE(PPDMDMAC) pDmac;
1413 /** The registered RTC device. */
1414 R3PTRTYPE(PPDMRTC) pRtc;
1415 /** The registered USB HUBs. (FIFO) */
1416 R3PTRTYPE(PPDMUSBHUB) pUsbHubs;
1417
1418 /** @name Queues
1419 * @{ */
1420 /** Queue in which devhlp tasks are queued for R3 execution - R3 Ptr. */
1421 R3PTRTYPE(PPDMQUEUE) pDevHlpQueueR3;
1422 /** Queue in which devhlp tasks are queued for R3 execution - R0 Ptr. */
1423 R0PTRTYPE(PPDMQUEUE) pDevHlpQueueR0;
1424 /** Queue in which devhlp tasks are queued for R3 execution - RC Ptr. */
1425 RCPTRTYPE(PPDMQUEUE) pDevHlpQueueRC;
1426 /** Pointer to the queue which should be manually flushed - RC Ptr.
1427 * Only touched by EMT. */
1428 RCPTRTYPE(struct PDMQUEUE *) pQueueFlushRC;
1429 /** Pointer to the queue which should be manually flushed - R0 Ptr.
1430 * Only touched by EMT. */
1431 R0PTRTYPE(struct PDMQUEUE *) pQueueFlushR0;
1432 /** Bitmask controlling the queue flushing.
1433 * See PDM_QUEUE_FLUSH_FLAG_ACTIVE and PDM_QUEUE_FLUSH_FLAG_PENDING. */
1434 uint32_t volatile fQueueFlushing;
1435 /** @} */
1436
1437 /** The current IRQ tag (tracing purposes). */
1438 uint32_t volatile uIrqTag;
1439
1440 /** Pending reset flags (PDMVMRESET_F_XXX). */
1441 uint32_t volatile fResetFlags;
1442
1443 /** Set by pdmR3LoadExec for use in assertions. */
1444 bool fStateLoaded;
1445 /** Alignment padding. */
1446 bool afPadding[3];
1447
1448 /** The tracing ID of the next device instance.
1449 *
1450 * @remarks We keep the device tracing ID seperate from the rest as these are
1451 * then more likely to end up with the same ID from one run to
1452 * another, making analysis somewhat easier. Drivers and USB devices
1453 * are more volatile and can be changed at runtime, thus these are much
1454 * less likely to remain stable, so just heap them all together. */
1455 uint32_t idTracingDev;
1456 /** The tracing ID of the next driver instance, USB device instance or other
1457 * PDM entity requiring an ID. */
1458 uint32_t idTracingOther;
1459
1460 /** @name VMM device heap
1461 * @{ */
1462 /** The heap size. */
1463 uint32_t cbVMMDevHeap;
1464 /** Free space. */
1465 uint32_t cbVMMDevHeapLeft;
1466 /** Pointer to the heap base (MMIO2 ring-3 mapping). NULL if not registered. */
1467 RTR3PTR pvVMMDevHeap;
1468 /** Ring-3 mapping/unmapping notification callback for the user. */
1469 PFNPDMVMMDEVHEAPNOTIFY pfnVMMDevHeapNotify;
1470 /** The current mapping. NIL_RTGCPHYS if not mapped or registered. */
1471 RTGCPHYS GCPhysVMMDevHeap;
1472 /** @} */
1473
1474 /** Number of times a critical section leave request needed to be queued for ring-3 execution. */
1475 STAMCOUNTER StatQueuedCritSectLeaves;
1476 /** Number of times we've successfully aborted a wait in ring-0. */
1477 STAMCOUNTER StatAbortedCritSectEnters;
1478 /** Number of times we've got the critical section ownership while trying to
1479 * abort a wait due to VERR_INTERRUPTED. */
1480 STAMCOUNTER StatCritSectEntersWhileAborting;
1481 STAMCOUNTER StatCritSectVerrTimeout;
1482 STAMCOUNTER StatCritSectVerrInterrupted;
1483 STAMCOUNTER StatCritSectNonInterruptibleWaits;
1484} PDM;
1485AssertCompileMemberAlignment(PDM, CritSect, 8);
1486AssertCompileMemberAlignment(PDM, aTaskSets, 64);
1487AssertCompileMemberAlignment(PDM, StatQueuedCritSectLeaves, 8);
1488AssertCompileMemberAlignment(PDM, GCPhysVMMDevHeap, sizeof(RTGCPHYS));
1489/** Pointer to PDM VM instance data. */
1490typedef PDM *PPDM;
1491
1492
1493/**
1494 * PDM data kept in the ring-0 GVM.
1495 */
1496typedef struct PDMR0PERVM
1497{
1498 /** PCI Buses, ring-0 data. */
1499 PDMPCIBUSR0 aPciBuses[PDM_PCI_BUSSES_MAX];
1500 /** IOMMUs, ring-0 data. */
1501 PDMIOMMUR0 aIommus[PDM_IOMMUS_MAX];
1502 /** Number of valid ring-0 device instances (apDevInstances). */
1503 uint32_t cDevInstances;
1504 uint32_t u32Padding;
1505 /** Pointer to ring-0 device instances. */
1506 R0PTRTYPE(struct PDMDEVINSR0 *) apDevInstances[190];
1507} PDMR0PERVM;
1508
1509
1510/**
1511 * PDM data kept in the UVM.
1512 */
1513typedef struct PDMUSERPERVM
1514{
1515 /** @todo move more stuff over here. */
1516
1517 /** Linked list of timer driven PDM queues.
1518 * Currently serialized by PDM::CritSect. */
1519 R3PTRTYPE(struct PDMQUEUE *) pQueuesTimer;
1520 /** Linked list of force action driven PDM queues.
1521 * Currently serialized by PDM::CritSect. */
1522 R3PTRTYPE(struct PDMQUEUE *) pQueuesForced;
1523
1524 /** Lock protecting the lists below it. */
1525 RTCRITSECT ListCritSect;
1526 /** Pointer to list of loaded modules. */
1527 PPDMMOD pModules;
1528 /** List of initialized critical sections. (LIFO) */
1529 R3PTRTYPE(PPDMCRITSECTINT) pCritSects;
1530 /** List of initialized read/write critical sections. (LIFO) */
1531 R3PTRTYPE(PPDMCRITSECTRWINT) pRwCritSects;
1532 /** Head of the PDM Thread list. (singly linked) */
1533 R3PTRTYPE(PPDMTHREAD) pThreads;
1534 /** Tail of the PDM Thread list. (singly linked) */
1535 R3PTRTYPE(PPDMTHREAD) pThreadsTail;
1536
1537 /** @name PDM Async Completion
1538 * @{ */
1539 /** Pointer to the array of supported endpoint classes. */
1540 PPDMASYNCCOMPLETIONEPCLASS apAsyncCompletionEndpointClass[PDMASYNCCOMPLETIONEPCLASSTYPE_MAX];
1541 /** Head of the templates. Singly linked, protected by ListCritSect. */
1542 R3PTRTYPE(PPDMASYNCCOMPLETIONTEMPLATE) pAsyncCompletionTemplates;
1543 /** @} */
1544
1545 /** Global block cache data. */
1546 R3PTRTYPE(PPDMBLKCACHEGLOBAL) pBlkCacheGlobal;
1547#ifdef VBOX_WITH_NETSHAPER
1548 /** Pointer to network shaper instance. */
1549 R3PTRTYPE(PPDMNETSHAPER) pNetShaper;
1550#endif /* VBOX_WITH_NETSHAPER */
1551
1552} PDMUSERPERVM;
1553/** Pointer to the PDM data kept in the UVM. */
1554typedef PDMUSERPERVM *PPDMUSERPERVM;
1555
1556
1557
1558/*******************************************************************************
1559* Global Variables *
1560*******************************************************************************/
1561#ifdef IN_RING3
1562extern const PDMDRVHLPR3 g_pdmR3DrvHlp;
1563extern const PDMDEVHLPR3 g_pdmR3DevHlpTrusted;
1564# ifdef VBOX_WITH_DBGF_TRACING
1565extern const PDMDEVHLPR3 g_pdmR3DevHlpTracing;
1566# endif
1567extern const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted;
1568extern const PDMPICHLP g_pdmR3DevPicHlp;
1569extern const PDMIOAPICHLP g_pdmR3DevIoApicHlp;
1570extern const PDMFWHLPR3 g_pdmR3DevFirmwareHlp;
1571extern const PDMPCIHLPR3 g_pdmR3DevPciHlp;
1572extern const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp;
1573extern const PDMDMACHLP g_pdmR3DevDmacHlp;
1574extern const PDMRTCHLP g_pdmR3DevRtcHlp;
1575extern const PDMHPETHLPR3 g_pdmR3DevHpetHlp;
1576extern const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp;
1577#endif
1578
1579
1580/*******************************************************************************
1581* Defined Constants And Macros *
1582*******************************************************************************/
1583/** @def PDMDEV_ASSERT_DEVINS
1584 * Asserts the validity of the device instance.
1585 */
1586#ifdef VBOX_STRICT
1587# define PDMDEV_ASSERT_DEVINS(pDevIns) \
1588 do { \
1589 AssertPtr(pDevIns); \
1590 Assert(pDevIns->u32Version == PDM_DEVINS_VERSION); \
1591 Assert(pDevIns->CTX_SUFF(pvInstanceDataFor) == (void *)&pDevIns->achInstanceData[0]); \
1592 } while (0)
1593#else
1594# define PDMDEV_ASSERT_DEVINS(pDevIns) do { } while (0)
1595#endif
1596
1597/** @def PDMDRV_ASSERT_DRVINS
1598 * Asserts the validity of the driver instance.
1599 */
1600#ifdef VBOX_STRICT
1601# define PDMDRV_ASSERT_DRVINS(pDrvIns) \
1602 do { \
1603 AssertPtr(pDrvIns); \
1604 Assert(pDrvIns->u32Version == PDM_DRVINS_VERSION); \
1605 Assert(pDrvIns->CTX_SUFF(pvInstanceData) == (void *)&pDrvIns->achInstanceData[0]); \
1606 } while (0)
1607#else
1608# define PDMDRV_ASSERT_DRVINS(pDrvIns) do { } while (0)
1609#endif
1610
1611
1612/*******************************************************************************
1613* Internal Functions *
1614*******************************************************************************/
1615#ifdef IN_RING3
1616bool pdmR3IsValidName(const char *pszName);
1617
1618int pdmR3CritSectBothInitStats(PVM pVM);
1619int pdmR3CritSectBothDeleteDevice(PVM pVM, PPDMDEVINS pDevIns);
1620int pdmR3CritSectBothDeleteDriver(PVM pVM, PPDMDRVINS pDrvIns);
1621int pdmR3CritSectInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1622 const char *pszNameFmt, va_list va);
1623int pdmR3CritSectInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1624 const char *pszNameFmt, ...);
1625int pdmR3CritSectInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1626 const char *pszNameFmt, ...);
1627int pdmR3CritSectRwInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1628 const char *pszNameFmt, va_list va);
1629int pdmR3CritSectRwInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1630 const char *pszNameFmt, ...);
1631int pdmR3CritSectRwInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1632 const char *pszNameFmt, ...);
1633
1634int pdmR3DevInit(PVM pVM);
1635int pdmR3DevInitComplete(PVM pVM);
1636PPDMDEV pdmR3DevLookup(PVM pVM, const char *pszName);
1637int pdmR3DevFindLun(PVM pVM, const char *pszDevice, unsigned iInstance, unsigned iLun, PPDMLUN *ppLun);
1638DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem);
1639
1640int pdmR3UsbLoadModules(PVM pVM);
1641int pdmR3UsbInstantiateDevices(PVM pVM);
1642PPDMUSB pdmR3UsbLookup(PVM pVM, const char *pszName);
1643int pdmR3UsbRegisterHub(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fVersions, uint32_t cPorts, PCPDMUSBHUBREG pUsbHubReg, PPCPDMUSBHUBHLP ppUsbHubHlp);
1644int pdmR3UsbVMInitComplete(PVM pVM);
1645
1646int pdmR3DrvInit(PVM pVM);
1647int pdmR3DrvInstantiate(PVM pVM, PCFGMNODE pNode, PPDMIBASE pBaseInterface, PPDMDRVINS pDrvAbove,
1648 PPDMLUN pLun, PPDMIBASE *ppBaseInterface);
1649int pdmR3DrvDetach(PPDMDRVINS pDrvIns, uint32_t fFlags);
1650void pdmR3DrvDestroyChain(PPDMDRVINS pDrvIns, uint32_t fFlags);
1651PPDMDRV pdmR3DrvLookup(PVM pVM, const char *pszName);
1652
1653int pdmR3LdrInitU(PUVM pUVM);
1654void pdmR3LdrTermU(PUVM pUVM, bool fFinal);
1655char *pdmR3FileR3(const char *pszFile, bool fShared);
1656int pdmR3LoadR3U(PUVM pUVM, const char *pszFilename, const char *pszName);
1657
1658void pdmR3QueueRelocate(PVM pVM, RTGCINTPTR offDelta);
1659
1660int pdmR3TaskInit(PVM pVM);
1661void pdmR3TaskTerm(PVM pVM);
1662
1663int pdmR3ThreadCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
1664 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1665int pdmR3ThreadCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADUSB pfnThread,
1666 PFNPDMTHREADWAKEUPUSB pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1667int pdmR3ThreadCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDRV pfnThread,
1668 PFNPDMTHREADWAKEUPDRV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1669int pdmR3ThreadDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1670int pdmR3ThreadDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1671int pdmR3ThreadDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1672void pdmR3ThreadDestroyAll(PVM pVM);
1673int pdmR3ThreadResumeAll(PVM pVM);
1674int pdmR3ThreadSuspendAll(PVM pVM);
1675
1676#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
1677int pdmR3AsyncCompletionInit(PVM pVM);
1678int pdmR3AsyncCompletionTerm(PVM pVM);
1679void pdmR3AsyncCompletionResume(PVM pVM);
1680int pdmR3AsyncCompletionTemplateCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEDEV pfnCompleted, const char *pszDesc);
1681int pdmR3AsyncCompletionTemplateCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate,
1682 PFNPDMASYNCCOMPLETEDRV pfnCompleted, void *pvTemplateUser, const char *pszDesc);
1683int pdmR3AsyncCompletionTemplateCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEUSB pfnCompleted, const char *pszDesc);
1684int pdmR3AsyncCompletionTemplateDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1685int pdmR3AsyncCompletionTemplateDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1686int pdmR3AsyncCompletionTemplateDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1687#endif
1688
1689#ifdef VBOX_WITH_NETSHAPER
1690int pdmR3NetShaperInit(PVM pVM);
1691int pdmR3NetShaperTerm(PVM pVM);
1692#endif
1693
1694int pdmR3BlkCacheInit(PVM pVM);
1695void pdmR3BlkCacheTerm(PVM pVM);
1696int pdmR3BlkCacheResume(PVM pVM);
1697
1698#endif /* IN_RING3 */
1699
1700void pdmLock(PVMCC pVM);
1701int pdmLockEx(PVMCC pVM, int rcBusy);
1702void pdmUnlock(PVMCC pVM);
1703bool pdmLockIsOwner(PVMCC pVM);
1704
1705#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
1706bool pdmIommuIsPresent(PPDMDEVINS pDevIns);
1707int pdmIommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut);
1708int pdmIommuMemAccessRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1709int pdmIommuMemAccessWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1710# ifdef IN_RING3
1711int pdmR3IommuMemAccessReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock);
1712int pdmR3IommuMemAccessWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock);
1713int pdmR3IommuMemAccessBulkReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, const void **papvPages, PPGMPAGEMAPLOCK paLocks);
1714int pdmR3IommuMemAccessBulkWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks);
1715# endif
1716#endif
1717
1718#if defined(IN_RING3) || defined(IN_RING0)
1719void pdmCritSectRwLeaveSharedQueued(PVMCC pVM, PPDMCRITSECTRW pThis);
1720void pdmCritSectRwLeaveExclQueued(PVMCC pVM, PPDMCRITSECTRW pThis);
1721#endif
1722
1723#ifdef IN_RING0
1724DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc);
1725#endif
1726
1727#ifdef VBOX_WITH_DBGF_TRACING
1728# ifdef IN_RING3
1729DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
1730 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1731 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
1732 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts);
1733DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port);
1734DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts);
1735DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
1736 uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
1737 PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
1738 void *pvUser, const char *pszDesc, PIOMMMIOHANDLE phRegion);
1739DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys);
1740DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion);
1741DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1742DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1743DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1744DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1745DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1746DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1747DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1748DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1749# elif defined(IN_RING0)
1750DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
1751 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1752 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
1753 void *pvUser);
1754DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
1755 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser);
1756DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1757DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1758DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1759DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1760DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1761DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1762DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1763DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1764# else
1765# error "Invalid environment selected"
1766# endif
1767#endif
1768
1769
1770/** @} */
1771
1772RT_C_DECLS_END
1773
1774#endif /* !VMM_INCLUDED_SRC_include_PDMInternal_h */
1775
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