PDMInternal.h@ 90570

Last change on this file since 90570 was 90570, checked in by vboxsync, 4 years ago
VMM/PDMCritSectRw: Added a self pointer for use with queued-leave to the read/write critical sections as well. bugref:6695
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
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1	/* $Id: PDMInternal.h 90570 2021-08-07 13:01:04Z vboxsync $ */
2	/** @file
3	* PDM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VMM_INCLUDED_SRC_include_PDMInternal_h
19	#define VMM_INCLUDED_SRC_include_PDMInternal_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <VBox/types.h>
25	#include <VBox/param.h>
26	#include <VBox/vmm/cfgm.h>
27	#include <VBox/vmm/stam.h>
28	#include <VBox/vusb.h>
29	#include <VBox/vmm/iom.h>
30	#include <VBox/vmm/pdmasynccompletion.h>
31	#ifdef VBOX_WITH_NETSHAPER
32	# include <VBox/vmm/pdmnetshaper.h>
33	#endif
34	#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
35	# include <VBox/vmm/pdmasynccompletion.h>
36	#endif
37	#include <VBox/vmm/pdmblkcache.h>
38	#include <VBox/vmm/pdmcommon.h>
39	#include <VBox/vmm/pdmtask.h>
40	#include <VBox/sup.h>
41	#include <VBox/msi.h>
42	#include <iprt/assert.h>
43	#include <iprt/critsect.h>
44	#ifdef IN_RING3
45	# include <iprt/thread.h>
46	#endif
47
48	RT_C_DECLS_BEGIN
49
50
51	/** @defgroup grp_pdm_int Internal
52	* @ingroup grp_pdm
53	* @internal
54	* @{
55	*/
56
57	/** @def PDM_WITH_R3R0_CRIT_SECT
58	* Enables or disabled ring-3/ring-0 critical sections. */
59	#if defined(DOXYGEN_RUNNING) \|\| 1
60	# define PDM_WITH_R3R0_CRIT_SECT
61	#endif
62
63	/** @def PDMCRITSECT_STRICT
64	* Enables/disables PDM critsect strictness like deadlock detection. */
65	#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECT_STRICT)) \
66	\|\| defined(DOXYGEN_RUNNING)
67	# define PDMCRITSECT_STRICT
68	#endif
69
70	/** @def PDMCRITSECT_STRICT
71	* Enables/disables PDM read/write critsect strictness like deadlock
72	* detection. */
73	#if (defined(RT_LOCK_STRICT) && defined(IN_RING3) && !defined(PDMCRITSECTRW_STRICT)) \
74	\|\| defined(DOXYGEN_RUNNING)
75	# define PDMCRITSECTRW_STRICT
76	#endif
77
78	/** The maximum device instance (total) size, ring-0/raw-mode capable devices. */
79	#define PDM_MAX_DEVICE_INSTANCE_SIZE _4M
80	/** The maximum device instance (total) size, ring-3 only devices. */
81	#define PDM_MAX_DEVICE_INSTANCE_SIZE_R3 _8M
82	/** The maximum size for the DBGF tracing tracking structure allocated for each device. */
83	#define PDM_MAX_DEVICE_DBGF_TRACING_TRACK PAGE_SIZE
84
85
86
87	/*******************************************************************************
88	* Structures and Typedefs *
89	*******************************************************************************/
90
91	/** Pointer to a PDM Device. */
92	typedef struct PDMDEV *PPDMDEV;
93	/** Pointer to a pointer to a PDM Device. */
94	typedef PPDMDEV *PPPDMDEV;
95
96	/** Pointer to a PDM USB Device. */
97	typedef struct PDMUSB *PPDMUSB;
98	/** Pointer to a pointer to a PDM USB Device. */
99	typedef PPDMUSB *PPPDMUSB;
100
101	/** Pointer to a PDM Driver. */
102	typedef struct PDMDRV *PPDMDRV;
103	/** Pointer to a pointer to a PDM Driver. */
104	typedef PPDMDRV *PPPDMDRV;
105
106	/** Pointer to a PDM Logical Unit. */
107	typedef struct PDMLUN *PPDMLUN;
108	/** Pointer to a pointer to a PDM Logical Unit. */
109	typedef PPDMLUN *PPPDMLUN;
110
111	/** Pointer to a DMAC instance. */
112	typedef struct PDMDMAC *PPDMDMAC;
113	/** Pointer to a RTC instance. */
114	typedef struct PDMRTC *PPDMRTC;
115
116	/** Pointer to an USB HUB registration record. */
117	typedef struct PDMUSBHUB *PPDMUSBHUB;
118
119	/**
120	* Supported asynchronous completion endpoint classes.
121	*/
122	typedef enum PDMASYNCCOMPLETIONEPCLASSTYPE
123	{
124	/** File class. */
125	PDMASYNCCOMPLETIONEPCLASSTYPE_FILE = 0,
126	/** Number of supported classes. */
127	PDMASYNCCOMPLETIONEPCLASSTYPE_MAX,
128	/** 32bit hack. */
129	PDMASYNCCOMPLETIONEPCLASSTYPE_32BIT_HACK = 0x7fffffff
130	} PDMASYNCCOMPLETIONEPCLASSTYPE;
131
132
133	/**
134	* MMIO/IO port registration tracking structure for DBGF tracing.
135	*/
136	typedef struct PDMDEVINSDBGFTRACK
137	{
138	/** Flag whether this tracks a IO port or MMIO registration. */
139	bool fMmio;
140	/** Opaque user data passed during registration. */
141	void *pvUser;
142	/** Type dependent data. */
143	union
144	{
145	/** I/O port registration. */
146	struct
147	{
148	/** IOM I/O port handle. */
149	IOMIOPORTHANDLE hIoPorts;
150	/** Original OUT handler of the device. */
151	PFNIOMIOPORTNEWOUT pfnOut;
152	/** Original IN handler of the device. */
153	PFNIOMIOPORTNEWIN pfnIn;
154	/** Original string OUT handler of the device. */
155	PFNIOMIOPORTNEWOUTSTRING pfnOutStr;
156	/** Original string IN handler of the device. */
157	PFNIOMIOPORTNEWINSTRING pfnInStr;
158	} IoPort;
159	/** MMIO registration. */
160	struct
161	{
162	/** IOM MMIO region handle. */
163	IOMMMIOHANDLE hMmioRegion;
164	/** Original MMIO write handler of the device. */
165	PFNIOMMMIONEWWRITE pfnWrite;
166	/** Original MMIO read handler of the device. */
167	PFNIOMMMIONEWREAD pfnRead;
168	/** Original MMIO fill handler of the device. */
169	PFNIOMMMIONEWFILL pfnFill;
170	} Mmio;
171	} u;
172	} PDMDEVINSDBGFTRACK;
173	/** Pointer to a MMIO/IO port registration tracking structure. */
174	typedef PDMDEVINSDBGFTRACK *PPDMDEVINSDBGFTRACK;
175	/** Pointer to a const MMIO/IO port registration tracking structure. */
176	typedef const PDMDEVINSDBGFTRACK *PCPDMDEVINSDBGFTRACK;
177
178
179	/**
180	* Private device instance data, ring-3.
181	*/
182	typedef struct PDMDEVINSINTR3
183	{
184	/** Pointer to the next instance.
185	* (Head is pointed to by PDM::pDevInstances.) */
186	R3PTRTYPE(PPDMDEVINS) pNextR3;
187	/** Pointer to the next per device instance.
188	* (Head is pointed to by PDMDEV::pInstances.) */
189	R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
190	/** Pointer to device structure. */
191	R3PTRTYPE(PPDMDEV) pDevR3;
192	/** Pointer to the list of logical units associated with the device. (FIFO) */
193	R3PTRTYPE(PPDMLUN) pLunsR3;
194	/** Pointer to the asynchronous notification callback set while in
195	* FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
196	R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
197	/** Configuration handle to the instance node. */
198	R3PTRTYPE(PCFGMNODE) pCfgHandle;
199
200	/** R3 pointer to the VM this instance was created for. */
201	PVMR3 pVMR3;
202	/** DBGF trace event source handle if tracing is configured. */
203	DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
204	/** Pointer to the base of the page containing the DBGF tracing tracking structures. */
205	PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
206	/** Index of the next entry to use for tracking. */
207	uint32_t idxDbgfTraceTrackNext;
208	/** Maximum number of records fitting into the single page. */
209	uint32_t cDbgfTraceTrackMax;
210
211	/** Flags, see PDMDEVINSINT_FLAGS_XXX. */
212	uint32_t fIntFlags;
213	/** The last IRQ tag (for tracing it thru clearing). */
214	uint32_t uLastIrqTag;
215	/** The ring-0 device index (for making ring-0 calls). */
216	uint32_t idxR0Device;
217	} PDMDEVINSINTR3;
218
219
220	/**
221	* Private device instance data, ring-0.
222	*/
223	typedef struct PDMDEVINSINTR0
224	{
225	/** Pointer to the VM this instance was created for. */
226	R0PTRTYPE(PGVM) pGVM;
227	/** Pointer to device structure. */
228	R0PTRTYPE(struct PDMDEVREGR0 const *) pRegR0;
229	/** The ring-0 module reference. */
230	RTR0PTR hMod;
231	/** Pointer to the ring-0 mapping of the ring-3 internal data (for uLastIrqTag). */
232	R0PTRTYPE(PDMDEVINSINTR3 *) pIntR3R0;
233	/** Pointer to the ring-0 mapping of the ring-3 instance (for idTracing). */
234	R0PTRTYPE(struct PDMDEVINSR3 *) pInsR3R0;
235	/** DBGF trace event source handle if tracing is configured. */
236	DBGFTRACEREVTSRC hDbgfTraceEvtSrc;
237	/** The device instance memory. */
238	RTR0MEMOBJ hMemObj;
239	/** The ring-3 mapping object. */
240	RTR0MEMOBJ hMapObj;
241	/** The page memory object for tracking MMIO and I/O port registrations when tracing is configured. */
242	RTR0MEMOBJ hDbgfTraceObj;
243	/** Pointer to the base of the page containing the DBGF tracing tracking structures. */
244	PPDMDEVINSDBGFTRACK paDbgfTraceTrack;
245	/** Index of the next entry to use for tracking. */
246	uint32_t idxDbgfTraceTrackNext;
247	/** Maximum number of records fitting into the single page. */
248	uint32_t cDbgfTraceTrackMax;
249	/** Index into PDMR0PERVM::apDevInstances. */
250	uint32_t idxR0Device;
251	} PDMDEVINSINTR0;
252
253
254	/**
255	* Private device instance data, raw-mode
256	*/
257	typedef struct PDMDEVINSINTRC
258	{
259	/** Pointer to the VM this instance was created for. */
260	RGPTRTYPE(PVM) pVMRC;
261	} PDMDEVINSINTRC;
262
263
264	/**
265	* Private device instance data.
266	*/
267	typedef struct PDMDEVINSINT
268	{
269	/** Pointer to the next instance (HC Ptr).
270	* (Head is pointed to by PDM::pDevInstances.) */
271	R3PTRTYPE(PPDMDEVINS) pNextR3;
272	/** Pointer to the next per device instance (HC Ptr).
273	* (Head is pointed to by PDMDEV::pInstances.) */
274	R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3;
275	/** Pointer to device structure - HC Ptr. */
276	R3PTRTYPE(PPDMDEV) pDevR3;
277	/** Pointer to the list of logical units associated with the device. (FIFO) */
278	R3PTRTYPE(PPDMLUN) pLunsR3;
279	/** Pointer to the asynchronous notification callback set while in
280	* FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
281	R3PTRTYPE(PFNPDMDEVASYNCNOTIFY) pfnAsyncNotify;
282	/** Configuration handle to the instance node. */
283	R3PTRTYPE(PCFGMNODE) pCfgHandle;
284
285	/** R3 pointer to the VM this instance was created for. */
286	PVMR3 pVMR3;
287
288	/** R0 pointer to the VM this instance was created for. */
289	R0PTRTYPE(PVMCC) pVMR0;
290
291	/** RC pointer to the VM this instance was created for. */
292	PVMRC pVMRC;
293
294	/** Flags, see PDMDEVINSINT_FLAGS_XXX. */
295	uint32_t fIntFlags;
296	/** The last IRQ tag (for tracing it thru clearing). */
297	uint32_t uLastIrqTag;
298	} PDMDEVINSINT;
299
300	/** @name PDMDEVINSINT::fIntFlags
301	* @{ */
302	/** Used by pdmR3Load to mark device instances it found in the saved state. */
303	#define PDMDEVINSINT_FLAGS_FOUND RT_BIT_32(0)
304	/** Indicates that the device hasn't been powered on or resumed.
305	* This is used by PDMR3PowerOn, PDMR3Resume, PDMR3Suspend and PDMR3PowerOff
306	* to make sure each device gets exactly one notification for each of those
307	* events. PDMR3Resume and PDMR3PowerOn also makes use of it to bail out on
308	* a failure (already resumed/powered-on devices are suspended).
309	* PDMR3PowerOff resets this flag once before going through the devices to make sure
310	* every device gets the power off notification even if it was suspended before with
311	* PDMR3Suspend.
312	*/
313	#define PDMDEVINSINT_FLAGS_SUSPENDED RT_BIT_32(1)
314	/** Indicates that the device has been reset already. Used by PDMR3Reset. */
315	#define PDMDEVINSINT_FLAGS_RESET RT_BIT_32(2)
316	#define PDMDEVINSINT_FLAGS_R0_ENABLED RT_BIT_32(3)
317	#define PDMDEVINSINT_FLAGS_RC_ENABLED RT_BIT_32(4)
318	/** Set if we've called the ring-0 constructor. */
319	#define PDMDEVINSINT_FLAGS_R0_CONTRUCT RT_BIT_32(5)
320	/** Set if using non-default critical section. */
321	#define PDMDEVINSINT_FLAGS_CHANGED_CRITSECT RT_BIT_32(6)
322	/** @} */
323
324
325	/**
326	* Private USB device instance data.
327	*/
328	typedef struct PDMUSBINSINT
329	{
330	/** The UUID of this instance. */
331	RTUUID Uuid;
332	/** Pointer to the next instance.
333	* (Head is pointed to by PDM::pUsbInstances.) */
334	R3PTRTYPE(PPDMUSBINS) pNext;
335	/** Pointer to the next per USB device instance.
336	* (Head is pointed to by PDMUSB::pInstances.) */
337	R3PTRTYPE(PPDMUSBINS) pPerDeviceNext;
338
339	/** Pointer to device structure. */
340	R3PTRTYPE(PPDMUSB) pUsbDev;
341
342	/** Pointer to the VM this instance was created for. */
343	PVMR3 pVM;
344	/** Pointer to the list of logical units associated with the device. (FIFO) */
345	R3PTRTYPE(PPDMLUN) pLuns;
346	/** The per instance device configuration. */
347	R3PTRTYPE(PCFGMNODE) pCfg;
348	/** Same as pCfg if the configuration should be deleted when detaching the device. */
349	R3PTRTYPE(PCFGMNODE) pCfgDelete;
350	/** The global device configuration. */
351	R3PTRTYPE(PCFGMNODE) pCfgGlobal;
352
353	/** Pointer to the USB hub this device is attached to.
354	* This is NULL if the device isn't connected to any HUB. */
355	R3PTRTYPE(PPDMUSBHUB) pHub;
356	/** The port number that we're connected to. */
357	uint32_t iPort;
358	/** Indicates that the USB device hasn't been powered on or resumed.
359	* See PDMDEVINSINT_FLAGS_SUSPENDED. */
360	bool fVMSuspended;
361	/** Indicates that the USB device has been reset. */
362	bool fVMReset;
363	/** Pointer to the asynchronous notification callback set while in
364	* FNPDMDEVSUSPEND or FNPDMDEVPOWEROFF. */
365	R3PTRTYPE(PFNPDMUSBASYNCNOTIFY) pfnAsyncNotify;
366	} PDMUSBINSINT;
367
368
369	/**
370	* Private driver instance data.
371	*/
372	typedef struct PDMDRVINSINT
373	{
374	/** Pointer to the driver instance above.
375	* This is NULL for the topmost drive. */
376	R3PTRTYPE(PPDMDRVINS) pUp;
377	/** Pointer to the driver instance below.
378	* This is NULL for the bottommost driver. */
379	R3PTRTYPE(PPDMDRVINS) pDown;
380	/** Pointer to the logical unit this driver chained on. */
381	R3PTRTYPE(PPDMLUN) pLun;
382	/** Pointer to driver structure from which this was instantiated. */
383	R3PTRTYPE(PPDMDRV) pDrv;
384	/** Pointer to the VM this instance was created for, ring-3 context. */
385	PVMR3 pVMR3;
386	/** Pointer to the VM this instance was created for, ring-0 context. */
387	R0PTRTYPE(PVMCC) pVMR0;
388	/** Pointer to the VM this instance was created for, raw-mode context. */
389	PVMRC pVMRC;
390	/** Flag indicating that the driver is being detached and destroyed.
391	* (Helps detect potential recursive detaching.) */
392	bool fDetaching;
393	/** Indicates that the driver hasn't been powered on or resumed.
394	* See PDMDEVINSINT_FLAGS_SUSPENDED. */
395	bool fVMSuspended;
396	/** Indicates that the driver has been reset already. */
397	bool fVMReset;
398	/** Set if allocated on the hyper heap, false if on the ring-3 heap. */
399	bool fHyperHeap;
400	/** Pointer to the asynchronous notification callback set while in
401	* PDMUSBREG::pfnVMSuspend or PDMUSBREG::pfnVMPowerOff. */
402	R3PTRTYPE(PFNPDMDRVASYNCNOTIFY) pfnAsyncNotify;
403	/** Configuration handle to the instance node. */
404	R3PTRTYPE(PCFGMNODE) pCfgHandle;
405	/** Pointer to the ring-0 request handler function. */
406	PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
407	} PDMDRVINSINT;
408
409
410	/**
411	* Private critical section data.
412	*/
413	typedef struct PDMCRITSECTINT
414	{
415	/** The critical section core which is shared with IPRT.
416	* @note The semaphore is a SUPSEMEVENT. */
417	RTCRITSECT Core;
418	/** Pointer to the next critical section.
419	* This chain is used for device cleanup and the dbgf info item. */
420	R3PTRTYPE(struct PDMCRITSECTINT *) pNext;
421	/** Owner identifier.
422	* This is pDevIns if the owner is a device. Similarly for a driver or service.
423	* PDMR3CritSectInit() sets this to point to the critsect itself. */
424	RTR3PTR pvKey;
425	/** Set if this critical section is the automatically created default
426	* section of a device. */
427	bool fAutomaticDefaultCritsect;
428	/** Set if the critical section is used by a timer or similar.
429	* See PDMR3DevGetCritSect. */
430	bool fUsedByTimerOrSimilar;
431	/** Alignment padding. */
432	bool afPadding[2+4];
433	/** Support driver event semaphore that is scheduled to be signaled upon leaving
434	* the critical section. This is only for Ring-3 and Ring-0. */
435	SUPSEMEVENT volatile hEventToSignal;
436	/** The lock name. */
437	R3PTRTYPE(const char *) pszName;
438	/** The ring-3 pointer to this critical section, for leave queueing. */
439	R3PTRTYPE(PPDMCRITSECT) pSelfR3;
440	/** R0/RC lock contention. */
441	STAMCOUNTER StatContentionRZLock;
442	/** R0/RC lock contention: returning rcBusy or VERR_SEM_BUSY (try). */
443	STAMCOUNTER StatContentionRZLockBusy;
444	/** R0/RC lock contention: Profiling waiting time. */
445	STAMPROFILE StatContentionRZWait;
446	/** R0/RC unlock contention. */
447	STAMCOUNTER StatContentionRZUnlock;
448	/** R3 lock contention. */
449	STAMCOUNTER StatContentionR3;
450	/** R3 lock contention: Profiling waiting time. */
451	STAMPROFILE StatContentionR3Wait;
452	/** Profiling the time the section is locked. */
453	STAMPROFILEADV StatLocked;
454	} PDMCRITSECTINT;
455	AssertCompileMemberAlignment(PDMCRITSECTINT, StatContentionRZLock, 8);
456	/** Pointer to private critical section data. */
457	typedef PDMCRITSECTINT *PPDMCRITSECTINT;
458
459	/** Special magic value set when we failed to abort entering in ring-0 due to a
460	* timeout, interruption or pending thread termination. */
461	#define PDMCRITSECT_MAGIC_FAILED_ABORT UINT32_C(0x0bad0326)
462	/** Special magic value set if we detected data/state corruption. */
463	#define PDMCRITSECT_MAGIC_CORRUPTED UINT32_C(0x0bad2603)
464
465	/** Indicates that the critical section is queued for unlock.
466	* PDMCritSectIsOwner and PDMCritSectIsOwned optimizations. */
467	#define PDMCRITSECT_FLAGS_PENDING_UNLOCK RT_BIT_32(17)
468
469
470	/**
471	* Private critical section data.
472	*/
473	typedef struct PDMCRITSECTRWINT
474	{
475	/** The read/write critical section core which is shared with IPRT.
476	* @note The semaphores are SUPSEMEVENT and SUPSEMEVENTMULTI. */
477	RTCRITSECTRW Core;
478
479	/** Pointer to the next critical section.
480	* This chain is used for device cleanup and the dbgf info item. */
481	R3PTRTYPE(struct PDMCRITSECTRWINT *) pNext;
482	/** Self pointer. */
483	R3PTRTYPE(PPDMCRITSECTRW) pSelfR3;
484	/** Owner identifier.
485	* This is pDevIns if the owner is a device. Similarly for a driver or service.
486	* PDMR3CritSectRwInit() sets this to point to the critsect itself. */
487	RTR3PTR pvKey;
488	/** The lock name. */
489	R3PTRTYPE(const char *) pszName;
490
491	/** R0/RC write lock contention. */
492	STAMCOUNTER StatContentionRZEnterExcl;
493	/** R0/RC write unlock contention. */
494	STAMCOUNTER StatContentionRZLeaveExcl;
495	/** R0/RC read lock contention. */
496	STAMCOUNTER StatContentionRZEnterShared;
497	/** R0/RC read unlock contention. */
498	STAMCOUNTER StatContentionRZLeaveShared;
499	/** R0/RC writes. */
500	STAMCOUNTER StatRZEnterExcl;
501	/** R0/RC reads. */
502	STAMCOUNTER StatRZEnterShared;
503	/** R3 write lock contention. */
504	STAMCOUNTER StatContentionR3EnterExcl;
505	/** R3 read lock contention. */
506	STAMCOUNTER StatContentionR3EnterShared;
507	/** R3 writes. */
508	STAMCOUNTER StatR3EnterExcl;
509	/** R3 reads. */
510	STAMCOUNTER StatR3EnterShared;
511	/** Profiling the time the section is write locked. */
512	STAMPROFILEADV StatWriteLocked;
513	} PDMCRITSECTRWINT;
514	AssertCompileMemberAlignment(PDMCRITSECTRWINT, StatContentionRZEnterExcl, 8);
515	AssertCompileMemberAlignment(PDMCRITSECTRWINT, Core.u64State, 8);
516	/** Pointer to private critical section data. */
517	typedef PDMCRITSECTRWINT *PPDMCRITSECTRWINT;
518
519	/** Special magic value we set the structure has become corrupted. */
520	#define PDMCRITSECTRW_MAGIC_CORRUPT UINT32_C(0x0bad0620)
521
522
523	/**
524	* The usual device/driver/internal/external stuff.
525	*/
526	typedef enum
527	{
528	/** The usual invalid entry. */
529	PDMTHREADTYPE_INVALID = 0,
530	/** Device type. */
531	PDMTHREADTYPE_DEVICE,
532	/** USB Device type. */
533	PDMTHREADTYPE_USB,
534	/** Driver type. */
535	PDMTHREADTYPE_DRIVER,
536	/** Internal type. */
537	PDMTHREADTYPE_INTERNAL,
538	/** External type. */
539	PDMTHREADTYPE_EXTERNAL,
540	/** The usual 32-bit hack. */
541	PDMTHREADTYPE_32BIT_HACK = 0x7fffffff
542	} PDMTHREADTYPE;
543
544
545	/**
546	* The internal structure for the thread.
547	*/
548	typedef struct PDMTHREADINT
549	{
550	/** The VM pointer. */
551	PVMR3 pVM;
552	/** The event semaphore the thread blocks on when not running. */
553	RTSEMEVENTMULTI BlockEvent;
554	/** The event semaphore the thread sleeps on while running. */
555	RTSEMEVENTMULTI SleepEvent;
556	/** Pointer to the next thread. */
557	R3PTRTYPE(struct PDMTHREAD *) pNext;
558	/** The thread type. */
559	PDMTHREADTYPE enmType;
560	} PDMTHREADINT;
561
562
563
564	/* Must be included after PDMDEVINSINT is defined. */
565	#define PDMDEVINSINT_DECLARED
566	#define PDMUSBINSINT_DECLARED
567	#define PDMDRVINSINT_DECLARED
568	#define PDMCRITSECTINT_DECLARED
569	#define PDMCRITSECTRWINT_DECLARED
570	#define PDMTHREADINT_DECLARED
571	#ifdef ___VBox_pdm_h
572	# error "Invalid header PDM order. Include PDMInternal.h before VBox/vmm/pdm.h!"
573	#endif
574	RT_C_DECLS_END
575	#include <VBox/vmm/pdm.h>
576	RT_C_DECLS_BEGIN
577
578	/**
579	* PDM Logical Unit.
580	*
581	* This typically the representation of a physical port on a
582	* device, like for instance the PS/2 keyboard port on the
583	* keyboard controller device. The LUNs are chained on the
584	* device they belong to (PDMDEVINSINT::pLunsR3).
585	*/
586	typedef struct PDMLUN
587	{
588	/** The LUN - The Logical Unit Number. */
589	RTUINT iLun;
590	/** Pointer to the next LUN. */
591	PPDMLUN pNext;
592	/** Pointer to the top driver in the driver chain. */
593	PPDMDRVINS pTop;
594	/** Pointer to the bottom driver in the driver chain. */
595	PPDMDRVINS pBottom;
596	/** Pointer to the device instance which the LUN belongs to.
597	* Either this is set or pUsbIns is set. Both is never set at the same time. */
598	PPDMDEVINS pDevIns;
599	/** Pointer to the USB device instance which the LUN belongs to. */
600	PPDMUSBINS pUsbIns;
601	/** Pointer to the device base interface. */
602	PPDMIBASE pBase;
603	/** Description of this LUN. */
604	const char *pszDesc;
605	} PDMLUN;
606
607
608	/**
609	* PDM Device, ring-3.
610	*/
611	typedef struct PDMDEV
612	{
613	/** Pointer to the next device (R3 Ptr). */
614	R3PTRTYPE(PPDMDEV) pNext;
615	/** Device name length. (search optimization) */
616	uint32_t cchName;
617	/** Registration structure. */
618	R3PTRTYPE(const struct PDMDEVREGR3 *) pReg;
619	/** Number of instances. */
620	uint32_t cInstances;
621	/** Pointer to chain of instances (R3 Ptr). */
622	PPDMDEVINSR3 pInstances;
623	/** The search path for raw-mode context modules (';' as separator). */
624	char *pszRCSearchPath;
625	/** The search path for ring-0 context modules (';' as separator). */
626	char *pszR0SearchPath;
627	} PDMDEV;
628
629
630	#if 0
631	/**
632	* PDM Device, ring-0.
633	*/
634	typedef struct PDMDEVR0
635	{
636	/** Pointer to the next device. */
637	R0PTRTYPE(PPDMDEVR0) pNext;
638	/** Device name length. (search optimization) */
639	uint32_t cchName;
640	/** Registration structure. */
641	R3PTRTYPE(const struct PDMDEVREGR0 *) pReg;
642	/** Number of instances. */
643	uint32_t cInstances;
644	/** Pointer to chain of instances. */
645	PPDMDEVINSR0 pInstances;
646	} PDMDEVR0;
647	#endif
648
649
650	/**
651	* PDM USB Device.
652	*/
653	typedef struct PDMUSB
654	{
655	/** Pointer to the next device (R3 Ptr). */
656	R3PTRTYPE(PPDMUSB) pNext;
657	/** Device name length. (search optimization) */
658	RTUINT cchName;
659	/** Registration structure. */
660	R3PTRTYPE(const struct PDMUSBREG *) pReg;
661	/** Next instance number. */
662	uint32_t iNextInstance;
663	/** Pointer to chain of instances (R3 Ptr). */
664	R3PTRTYPE(PPDMUSBINS) pInstances;
665	} PDMUSB;
666
667
668	/**
669	* PDM Driver.
670	*/
671	typedef struct PDMDRV
672	{
673	/** Pointer to the next device. */
674	PPDMDRV pNext;
675	/** Registration structure. */
676	const struct PDMDRVREG * pReg;
677	/** Current number of instances. */
678	uint32_t cInstances;
679	/** The next instance number. */
680	uint32_t iNextInstance;
681	/** The search path for raw-mode context modules (';' as separator). */
682	char *pszRCSearchPath;
683	/** The search path for ring-0 context modules (';' as separator). */
684	char *pszR0SearchPath;
685	} PDMDRV;
686
687
688	/**
689	* PDM IOMMU, shared ring-3.
690	*/
691	typedef struct PDMIOMMUR3
692	{
693	/** IOMMU index. */
694	uint32_t idxIommu;
695	uint32_t uPadding0; /*< Alignment padding./
696
697	/** Pointer to the IOMMU device instance - R3. */
698	PPDMDEVINSR3 pDevInsR3;
699	/** @copydoc PDMIOMMUREGR3::pfnMemAccess */
700	DECLR3CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
701	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
702	/** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
703	DECLR3CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
704	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
705	/** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
706	DECLR3CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
707	} PDMIOMMUR3;
708	/** Pointer to a PDM IOMMU instance. */
709	typedef PDMIOMMUR3 *PPDMIOMMUR3;
710	/** Pointer to a const PDM IOMMU instance. */
711	typedef const PDMIOMMUR3 *PCPDMIOMMUR3;
712
713
714	/**
715	* PDM IOMMU, ring-0.
716	*/
717	typedef struct PDMIOMMUR0
718	{
719	/** IOMMU index. */
720	uint32_t idxIommu;
721	uint32_t uPadding0; /*< Alignment padding./
722
723	/** Pointer to IOMMU device instance. */
724	PPDMDEVINSR0 pDevInsR0;
725	/** @copydoc PDMIOMMUREGR3::pfnMemAccess */
726	DECLR0CALLBACKMEMBER(int, pfnMemAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, uint64_t uIova, size_t cbIova,
727	uint32_t fFlags, PRTGCPHYS pGCPhysSpa, size_t *pcbContig));
728	/** @copydoc PDMIOMMUREGR3::pfnMemBulkAccess */
729	DECLR0CALLBACKMEMBER(int, pfnMemBulkAccess,(PPDMDEVINS pDevIns, uint16_t idDevice, size_t cIovas, uint64_t const *pauIovas,
730	uint32_t fFlags, PRTGCPHYS paGCPhysSpa));
731	/** @copydoc PDMIOMMUREGR3::pfnMsiRemap */
732	DECLR0CALLBACKMEMBER(int, pfnMsiRemap,(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut));
733	} PDMIOMMUR0;
734	/** Pointer to a ring-0 IOMMU data. */
735	typedef PDMIOMMUR0 *PPDMIOMMUR0;
736	/** Pointer to a const ring-0 IOMMU data. */
737	typedef const PDMIOMMUR0 *PCPDMIOMMUR0;
738
739	/** Pointer to a PDM IOMMU for the current context. */
740	#ifdef IN_RING3
741	typedef PPDMIOMMUR3 PPDMIOMMU;
742	#else
743	typedef PPDMIOMMUR0 PPDMIOMMU;
744	#endif
745
746
747	/**
748	* PDM registered PIC device.
749	*/
750	typedef struct PDMPIC
751	{
752	/** Pointer to the PIC device instance - R3. */
753	PPDMDEVINSR3 pDevInsR3;
754	/** @copydoc PDMPICREG::pfnSetIrq */
755	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
756	/** @copydoc PDMPICREG::pfnGetInterrupt */
757	DECLR3CALLBACKMEMBER(int, pfnGetInterruptR3,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
758
759	/** Pointer to the PIC device instance - R0. */
760	PPDMDEVINSR0 pDevInsR0;
761	/** @copydoc PDMPICREG::pfnSetIrq */
762	DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
763	/** @copydoc PDMPICREG::pfnGetInterrupt */
764	DECLR0CALLBACKMEMBER(int, pfnGetInterruptR0,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
765
766	/** Pointer to the PIC device instance - RC. */
767	PPDMDEVINSRC pDevInsRC;
768	/** @copydoc PDMPICREG::pfnSetIrq */
769	DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc));
770	/** @copydoc PDMPICREG::pfnGetInterrupt */
771	DECLRCCALLBACKMEMBER(int, pfnGetInterruptRC,(PPDMDEVINS pDevIns, uint32_t *puTagSrc));
772	/** Alignment padding. */
773	RTRCPTR RCPtrPadding;
774	} PDMPIC;
775
776
777	/**
778	* PDM registered APIC device.
779	*/
780	typedef struct PDMAPIC
781	{
782	/** Pointer to the APIC device instance - R3 Ptr. */
783	PPDMDEVINSR3 pDevInsR3;
784	/** Pointer to the APIC device instance - R0 Ptr. */
785	PPDMDEVINSR0 pDevInsR0;
786	/** Pointer to the APIC device instance - RC Ptr. */
787	PPDMDEVINSRC pDevInsRC;
788	uint8_t Alignment[4];
789	} PDMAPIC;
790
791
792	/**
793	* PDM registered I/O APIC device.
794	*/
795	typedef struct PDMIOAPIC
796	{
797	/** Pointer to the I/O APIC device instance - R3 Ptr. */
798	PPDMDEVINSR3 pDevInsR3;
799	/** @copydoc PDMIOAPICREG::pfnSetIrq */
800	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
801	/** @copydoc PDMIOAPICREG::pfnSendMsi */
802	DECLR3CALLBACKMEMBER(void, pfnSendMsiR3,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
803	/** @copydoc PDMIOAPICREG::pfnSetEoi */
804	DECLR3CALLBACKMEMBER(void, pfnSetEoiR3,(PPDMDEVINS pDevIns, uint8_t u8Vector));
805
806	/** Pointer to the I/O APIC device instance - R0. */
807	PPDMDEVINSR0 pDevInsR0;
808	/** @copydoc PDMIOAPICREG::pfnSetIrq */
809	DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
810	/** @copydoc PDMIOAPICREG::pfnSendMsi */
811	DECLR0CALLBACKMEMBER(void, pfnSendMsiR0,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
812	/** @copydoc PDMIOAPICREG::pfnSetEoi */
813	DECLR0CALLBACKMEMBER(void, pfnSetEoiR0,(PPDMDEVINS pDevIns, uint8_t u8Vector));
814
815	/** Pointer to the I/O APIC device instance - RC Ptr. */
816	PPDMDEVINSRC pDevInsRC;
817	/** @copydoc PDMIOAPICREG::pfnSetIrq */
818	DECLRCCALLBACKMEMBER(void, pfnSetIrqRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc));
819	/** @copydoc PDMIOAPICREG::pfnSendMsi */
820	DECLRCCALLBACKMEMBER(void, pfnSendMsiRC,(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc));
821	/** @copydoc PDMIOAPICREG::pfnSendMsi */
822	DECLRCCALLBACKMEMBER(void, pfnSetEoiRC,(PPDMDEVINS pDevIns, uint8_t u8Vector));
823	} PDMIOAPIC;
824	/** Pointer to a PDM IOAPIC instance. */
825	typedef PDMIOAPIC *PPDMIOAPIC;
826	/** Pointer to a const PDM IOAPIC instance. */
827	typedef PDMIOAPIC const *PCPDMIOAPIC;
828
829	/** Maximum number of PCI busses for a VM. */
830	#define PDM_PCI_BUSSES_MAX 8
831	/** Maximum number of IOMMUs (at most one per PCI bus). */
832	#define PDM_IOMMUS_MAX PDM_PCI_BUSSES_MAX
833
834
835	#ifdef IN_RING3
836	/**
837	* PDM registered firmware device.
838	*/
839	typedef struct PDMFW
840	{
841	/** Pointer to the firmware device instance. */
842	PPDMDEVINSR3 pDevIns;
843	/** Copy of the registration structure. */
844	PDMFWREG Reg;
845	} PDMFW;
846	/** Pointer to a firmware instance. */
847	typedef PDMFW *PPDMFW;
848	#endif
849
850
851	/**
852	* PDM PCI bus instance.
853	*/
854	typedef struct PDMPCIBUS
855	{
856	/** PCI bus number. */
857	uint32_t iBus;
858	uint32_t uPadding0; /*< Alignment padding./
859
860	/** Pointer to PCI bus device instance. */
861	PPDMDEVINSR3 pDevInsR3;
862	/** @copydoc PDMPCIBUSREGR3::pfnSetIrqR3 */
863	DECLR3CALLBACKMEMBER(void, pfnSetIrqR3,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
864
865	/** @copydoc PDMPCIBUSREGR3::pfnRegisterR3 */
866	DECLR3CALLBACKMEMBER(int, pfnRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t fFlags,
867	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName));
868	/** @copydoc PDMPCIBUSREGR3::pfnRegisterMsiR3 */
869	DECLR3CALLBACKMEMBER(int, pfnRegisterMsi,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg));
870	/** @copydoc PDMPCIBUSREGR3::pfnIORegionRegisterR3 */
871	DECLR3CALLBACKMEMBER(int, pfnIORegionRegister,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
872	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, uint32_t fFlags,
873	uint64_t hHandle, PFNPCIIOREGIONMAP pfnCallback));
874	/** @copydoc PDMPCIBUSREGR3::pfnInterceptConfigAccesses */
875	DECLR3CALLBACKMEMBER(void, pfnInterceptConfigAccesses,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
876	PFNPCICONFIGREAD pfnRead, PFNPCICONFIGWRITE pfnWrite));
877	/** @copydoc PDMPCIBUSREGR3::pfnConfigWrite */
878	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigWrite,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
879	uint32_t uAddress, unsigned cb, uint32_t u32Value));
880	/** @copydoc PDMPCIBUSREGR3::pfnConfigRead */
881	DECLR3CALLBACKMEMBER(VBOXSTRICTRC, pfnConfigRead,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev,
882	uint32_t uAddress, unsigned cb, uint32_t *pu32Value));
883	} PDMPCIBUS;
884	/** Pointer to a PDM PCI Bus instance. */
885	typedef PDMPCIBUS *PPDMPCIBUS;
886	/** Pointer to a const PDM PCI Bus instance. */
887	typedef const PDMPCIBUS *PCPDMPCIBUS;
888
889
890	/**
891	* Ring-0 PDM PCI bus instance data.
892	*/
893	typedef struct PDMPCIBUSR0
894	{
895	/** PCI bus number. */
896	uint32_t iBus;
897	uint32_t uPadding0; /*< Alignment padding./
898	/** Pointer to PCI bus device instance. */
899	PPDMDEVINSR0 pDevInsR0;
900	/** @copydoc PDMPCIBUSREGR0::pfnSetIrq */
901	DECLR0CALLBACKMEMBER(void, pfnSetIrqR0,(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc));
902	} PDMPCIBUSR0;
903	/** Pointer to the ring-0 PCI bus data. */
904	typedef PDMPCIBUSR0 *PPDMPCIBUSR0;
905	/** Pointer to the const ring-0 PCI bus data. */
906	typedef const PDMPCIBUSR0 *PCPDMPCIBUSR0;
907
908
909	#ifdef IN_RING3
910	/**
911	* PDM registered DMAC (DMA Controller) device.
912	*/
913	typedef struct PDMDMAC
914	{
915	/** Pointer to the DMAC device instance. */
916	PPDMDEVINSR3 pDevIns;
917	/** Copy of the registration structure. */
918	PDMDMACREG Reg;
919	} PDMDMAC;
920
921
922	/**
923	* PDM registered RTC (Real Time Clock) device.
924	*/
925	typedef struct PDMRTC
926	{
927	/** Pointer to the RTC device instance. */
928	PPDMDEVINSR3 pDevIns;
929	/** Copy of the registration structure. */
930	PDMRTCREG Reg;
931	} PDMRTC;
932
933	#endif /* IN_RING3 */
934
935	/**
936	* Module type.
937	*/
938	typedef enum PDMMODTYPE
939	{
940	/** Raw-mode (RC) context module. */
941	PDMMOD_TYPE_RC,
942	/** Ring-0 (host) context module. */
943	PDMMOD_TYPE_R0,
944	/** Ring-3 (host) context module. */
945	PDMMOD_TYPE_R3
946	} PDMMODTYPE;
947
948
949	/** The module name length including the terminator. */
950	#define PDMMOD_NAME_LEN 32
951
952	/**
953	* Loaded module instance.
954	*/
955	typedef struct PDMMOD
956	{
957	/** Module name. This is used for referring to
958	* the module internally, sort of like a handle. */
959	char szName[PDMMOD_NAME_LEN];
960	/** Module type. */
961	PDMMODTYPE eType;
962	/** Loader module handle. Not used for R0 modules. */
963	RTLDRMOD hLdrMod;
964	/** Loaded address.
965	* This is the 'handle' for R0 modules. */
966	RTUINTPTR ImageBase;
967	/** Old loaded address.
968	* This is used during relocation of GC modules. Not used for R0 modules. */
969	RTUINTPTR OldImageBase;
970	/** Where the R3 HC bits are stored.
971	* This can be equal to ImageBase but doesn't have to. Not used for R0 modules. */
972	void *pvBits;
973
974	/** Pointer to next module. */
975	struct PDMMOD *pNext;
976	/** Module filename. */
977	char szFilename[1];
978	} PDMMOD;
979	/** Pointer to loaded module instance. */
980	typedef PDMMOD *PPDMMOD;
981
982
983
984	/** Extra space in the free array. */
985	#define PDMQUEUE_FREE_SLACK 16
986
987	/**
988	* Queue type.
989	*/
990	typedef enum PDMQUEUETYPE
991	{
992	/** Device consumer. */
993	PDMQUEUETYPE_DEV = 1,
994	/** Driver consumer. */
995	PDMQUEUETYPE_DRV,
996	/** Internal consumer. */
997	PDMQUEUETYPE_INTERNAL,
998	/** External consumer. */
999	PDMQUEUETYPE_EXTERNAL
1000	} PDMQUEUETYPE;
1001
1002	/** Pointer to a PDM Queue. */
1003	typedef struct PDMQUEUE *PPDMQUEUE;
1004
1005	/**
1006	* PDM Queue.
1007	*/
1008	typedef struct PDMQUEUE
1009	{
1010	/** Pointer to the next queue in the list. */
1011	R3PTRTYPE(PPDMQUEUE) pNext;
1012	/** Type specific data. */
1013	union
1014	{
1015	/** PDMQUEUETYPE_DEV */
1016	struct
1017	{
1018	/** Pointer to consumer function. */
1019	R3PTRTYPE(PFNPDMQUEUEDEV) pfnCallback;
1020	/** Pointer to the device instance owning the queue. */
1021	R3PTRTYPE(PPDMDEVINS) pDevIns;
1022	} Dev;
1023	/** PDMQUEUETYPE_DRV */
1024	struct
1025	{
1026	/** Pointer to consumer function. */
1027	R3PTRTYPE(PFNPDMQUEUEDRV) pfnCallback;
1028	/** Pointer to the driver instance owning the queue. */
1029	R3PTRTYPE(PPDMDRVINS) pDrvIns;
1030	} Drv;
1031	/** PDMQUEUETYPE_INTERNAL */
1032	struct
1033	{
1034	/** Pointer to consumer function. */
1035	R3PTRTYPE(PFNPDMQUEUEINT) pfnCallback;
1036	} Int;
1037	/** PDMQUEUETYPE_EXTERNAL */
1038	struct
1039	{
1040	/** Pointer to consumer function. */
1041	R3PTRTYPE(PFNPDMQUEUEEXT) pfnCallback;
1042	/** Pointer to user argument. */
1043	R3PTRTYPE(void *) pvUser;
1044	} Ext;
1045	} u;
1046	/** Queue type. */
1047	PDMQUEUETYPE enmType;
1048	/** The interval between checking the queue for events.
1049	* The realtime timer below is used to do the waiting.
1050	* If 0, the queue will use the VM_FF_PDM_QUEUE forced action. */
1051	uint32_t cMilliesInterval;
1052	/** Interval timer. Only used if cMilliesInterval is non-zero. */
1053	TMTIMERHANDLE hTimer;
1054	/** Pointer to the VM - R3. */
1055	PVMR3 pVMR3;
1056	/** LIFO of pending items - R3. */
1057	R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR3;
1058	/** Pointer to the VM - R0. */
1059	PVMR0 pVMR0;
1060	/** LIFO of pending items - R0. */
1061	R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingR0;
1062	/** Pointer to the GC VM and indicator for GC enabled queue.
1063	* If this is NULL, the queue cannot be used in GC.
1064	*/
1065	PVMRC pVMRC;
1066	/** LIFO of pending items - GC. */
1067	RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pPendingRC;
1068
1069	/** Item size (bytes). */
1070	uint32_t cbItem;
1071	/** Number of items in the queue. */
1072	uint32_t cItems;
1073	/** Index to the free head (where we insert). */
1074	uint32_t volatile iFreeHead;
1075	/** Index to the free tail (where we remove). */
1076	uint32_t volatile iFreeTail;
1077
1078	/** Unique queue name. */
1079	R3PTRTYPE(const char *) pszName;
1080	#if HC_ARCH_BITS == 32
1081	RTR3PTR Alignment1;
1082	#endif
1083	/** Stat: Times PDMQueueAlloc fails. */
1084	STAMCOUNTER StatAllocFailures;
1085	/** Stat: PDMQueueInsert calls. */
1086	STAMCOUNTER StatInsert;
1087	/** Stat: Queue flushes. */
1088	STAMCOUNTER StatFlush;
1089	/** Stat: Queue flushes with pending items left over. */
1090	STAMCOUNTER StatFlushLeftovers;
1091	#ifdef VBOX_WITH_STATISTICS
1092	/** State: Profiling the flushing. */
1093	STAMPROFILE StatFlushPrf;
1094	/** State: Pending items. */
1095	uint32_t volatile cStatPending;
1096	uint32_t volatile cAlignment;
1097	#endif
1098
1099	/** Array of pointers to free items. Variable size. */
1100	struct PDMQUEUEFREEITEM
1101	{
1102	/** Pointer to the free item - HC Ptr. */
1103	R3PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR3;
1104	/** Pointer to the free item - HC Ptr. */
1105	R0PTRTYPE(PPDMQUEUEITEMCORE) volatile pItemR0;
1106	/** Pointer to the free item - GC Ptr. */
1107	RCPTRTYPE(PPDMQUEUEITEMCORE) volatile pItemRC;
1108	#if HC_ARCH_BITS == 64
1109	RTRCPTR Alignment0;
1110	#endif
1111	} aFreeItems[1];
1112	} PDMQUEUE;
1113
1114	/** @name PDM::fQueueFlushing
1115	* @{ */
1116	/** Used to make sure only one EMT will flush the queues.
1117	* Set when an EMT is flushing queues, clear otherwise. */
1118	#define PDM_QUEUE_FLUSH_FLAG_ACTIVE_BIT 0
1119	/** Indicating there are queues with items pending.
1120	* This is make sure we don't miss inserts happening during flushing. The FF
1121	* cannot be used for this since it has to be cleared immediately to prevent
1122	* other EMTs from spinning. */
1123	#define PDM_QUEUE_FLUSH_FLAG_PENDING_BIT 1
1124	/** @} */
1125
1126
1127	/** @name PDM task structures.
1128	* @{ */
1129
1130	/**
1131	* A asynchronous user mode task.
1132	*/
1133	typedef struct PDMTASK
1134	{
1135	/** Task owner type. */
1136	PDMTASKTYPE volatile enmType;
1137	/** Queue flags. */
1138	uint32_t volatile fFlags;
1139	/** User argument for the callback. */
1140	R3PTRTYPE(void *) volatile pvUser;
1141	/** The callback (will be cast according to enmType before callout). */
1142	R3PTRTYPE(PFNRT) volatile pfnCallback;
1143	/** The owner identifier. */
1144	R3PTRTYPE(void *) volatile pvOwner;
1145	/** Task name. */
1146	R3PTRTYPE(const char *) pszName;
1147	/** Number of times already triggered when PDMTaskTrigger was called. */
1148	uint32_t volatile cAlreadyTrigged;
1149	/** Number of runs. */
1150	uint32_t cRuns;
1151	} PDMTASK;
1152	/** Pointer to a PDM task. */
1153	typedef PDMTASK *PPDMTASK;
1154
1155	/**
1156	* A task set.
1157	*
1158	* This is served by one task executor thread.
1159	*/
1160	typedef struct PDMTASKSET
1161	{
1162	/** Magic value (PDMTASKSET_MAGIC). */
1163	uint32_t u32Magic;
1164	/** Set if this task set works for ring-0 and raw-mode. */
1165	bool fRZEnabled;
1166	/** Number of allocated taks. */
1167	uint8_t volatile cAllocated;
1168	/** Base handle value for this set. */
1169	uint16_t uHandleBase;
1170	/** The task executor thread. */
1171	R3PTRTYPE(RTTHREAD) hThread;
1172	/** Event semaphore for waking up the thread when fRZEnabled is set. */
1173	SUPSEMEVENT hEventR0;
1174	/** Event semaphore for waking up the thread when fRZEnabled is clear. */
1175	R3PTRTYPE(RTSEMEVENT) hEventR3;
1176	/** The VM pointer. */
1177	PVM pVM;
1178	/** Padding so fTriggered is in its own cacheline. */
1179	uint64_t au64Padding2[3];
1180
1181	/** Bitmask of triggered tasks. */
1182	uint64_t volatile fTriggered;
1183	/** Shutdown thread indicator. */
1184	bool volatile fShutdown;
1185	/** Padding. */
1186	bool volatile afPadding3[3];
1187	/** Task currently running, UINT32_MAX if idle. */
1188	uint32_t volatile idxRunning;
1189	/** Padding so fTriggered and fShutdown are in their own cacheline. */
1190	uint64_t volatile au64Padding3[6];
1191
1192	/** The individual tasks. (Unallocated tasks have NULL pvOwner.) */
1193	PDMTASK aTasks[64];
1194	} PDMTASKSET;
1195	AssertCompileMemberAlignment(PDMTASKSET, fTriggered, 64);
1196	AssertCompileMemberAlignment(PDMTASKSET, aTasks, 64);
1197	/** Magic value for PDMTASKSET::u32Magic. */
1198	#define PDMTASKSET_MAGIC UINT32_C(0x19320314)
1199	/** Pointer to a task set. */
1200	typedef PDMTASKSET *PPDMTASKSET;
1201
1202	/** @} */
1203
1204
1205	/**
1206	* Queue device helper task operation.
1207	*/
1208	typedef enum PDMDEVHLPTASKOP
1209	{
1210	/** The usual invalid 0 entry. */
1211	PDMDEVHLPTASKOP_INVALID = 0,
1212	/** IsaSetIrq, IoApicSetIrq */
1213	PDMDEVHLPTASKOP_ISA_SET_IRQ,
1214	/** PciSetIrq */
1215	PDMDEVHLPTASKOP_PCI_SET_IRQ,
1216	/** PciSetIrq */
1217	PDMDEVHLPTASKOP_IOAPIC_SET_IRQ,
1218	/** IoApicSendMsi */
1219	PDMDEVHLPTASKOP_IOAPIC_SEND_MSI,
1220	/** IoApicSettEoi */
1221	PDMDEVHLPTASKOP_IOAPIC_SET_EOI,
1222	/** The usual 32-bit hack. */
1223	PDMDEVHLPTASKOP_32BIT_HACK = 0x7fffffff
1224	} PDMDEVHLPTASKOP;
1225
1226	/**
1227	* Queued Device Helper Task.
1228	*/
1229	typedef struct PDMDEVHLPTASK
1230	{
1231	/** The queue item core (don't touch). */
1232	PDMQUEUEITEMCORE Core;
1233	/** Pointer to the device instance (R3 Ptr). */
1234	PPDMDEVINSR3 pDevInsR3;
1235	/** This operation to perform. */
1236	PDMDEVHLPTASKOP enmOp;
1237	#if HC_ARCH_BITS == 64
1238	uint32_t Alignment0;
1239	#endif
1240	/** Parameters to the operation. */
1241	union PDMDEVHLPTASKPARAMS
1242	{
1243	/**
1244	* PDMDEVHLPTASKOP_ISA_SET_IRQ and PDMDEVHLPTASKOP_IOAPIC_SET_IRQ.
1245	*/
1246	struct PDMDEVHLPTASKISASETIRQ
1247	{
1248	/** The bus:device:function of the device initiating the IRQ. Can be NIL_PCIBDF. */
1249	PCIBDF uBusDevFn;
1250	/** The IRQ */
1251	int iIrq;
1252	/** The new level. */
1253	int iLevel;
1254	/** The IRQ tag and source. */
1255	uint32_t uTagSrc;
1256	} IsaSetIrq, IoApicSetIrq;
1257
1258	/**
1259	* PDMDEVHLPTASKOP_PCI_SET_IRQ
1260	*/
1261	struct PDMDEVHLPTASKPCISETIRQ
1262	{
1263	/** Pointer to the PCI device (R3 Ptr). */
1264	R3PTRTYPE(PPDMPCIDEV) pPciDevR3;
1265	/** The IRQ */
1266	int iIrq;
1267	/** The new level. */
1268	int iLevel;
1269	/** The IRQ tag and source. */
1270	uint32_t uTagSrc;
1271	} PciSetIrq;
1272
1273	/**
1274	* PDMDEVHLPTASKOP_IOAPIC_SEND_MSI
1275	*/
1276	struct PDMDEVHLPTASKIOAPICSENDMSI
1277	{
1278	/** The bus:device:function of the device sending the MSI. */
1279	PCIBDF uBusDevFn;
1280	/** The MSI. */
1281	MSIMSG Msi;
1282	/** The IRQ tag and source. */
1283	uint32_t uTagSrc;
1284	} IoApicSendMsi;
1285
1286	/**
1287	* PDMDEVHLPTASKOP_IOAPIC_SET_EOI
1288	*/
1289	struct PDMDEVHLPTASKIOAPICSETEOI
1290	{
1291	/** The vector corresponding to the EOI. */
1292	uint8_t uVector;
1293	} IoApicSetEoi;
1294
1295	/** Expanding the structure. */
1296	uint64_t au64[3];
1297	} u;
1298	} PDMDEVHLPTASK;
1299	/** Pointer to a queued Device Helper Task. */
1300	typedef PDMDEVHLPTASK *PPDMDEVHLPTASK;
1301	/** Pointer to a const queued Device Helper Task. */
1302	typedef const PDMDEVHLPTASK *PCPDMDEVHLPTASK;
1303
1304
1305
1306	/**
1307	* An USB hub registration record.
1308	*/
1309	typedef struct PDMUSBHUB
1310	{
1311	/** The USB versions this hub support.
1312	* Note that 1.1 hubs can take on 2.0 devices. */
1313	uint32_t fVersions;
1314	/** The number of ports on the hub. */
1315	uint32_t cPorts;
1316	/** The number of available ports (0..cPorts). */
1317	uint32_t cAvailablePorts;
1318	/** The driver instance of the hub. */
1319	PPDMDRVINS pDrvIns;
1320	/** Copy of the to the registration structure. */
1321	PDMUSBHUBREG Reg;
1322
1323	/** Pointer to the next hub in the list. */
1324	struct PDMUSBHUB *pNext;
1325	} PDMUSBHUB;
1326
1327	/** Pointer to a const USB HUB registration record. */
1328	typedef const PDMUSBHUB *PCPDMUSBHUB;
1329
1330	/** Pointer to a PDM Async I/O template. */
1331	typedef struct PDMASYNCCOMPLETIONTEMPLATE *PPDMASYNCCOMPLETIONTEMPLATE;
1332
1333	/** Pointer to the main PDM Async completion endpoint class. */
1334	typedef struct PDMASYNCCOMPLETIONEPCLASS *PPDMASYNCCOMPLETIONEPCLASS;
1335
1336	/** Pointer to the global block cache structure. */
1337	typedef struct PDMBLKCACHEGLOBAL *PPDMBLKCACHEGLOBAL;
1338
1339	/**
1340	* PDM VMCPU Instance data.
1341	* Changes to this must checked against the padding of the pdm union in VMCPU!
1342	*/
1343	typedef struct PDMCPU
1344	{
1345	/** The number of entries in the apQueuedCritSectsLeaves table that's currently
1346	* in use. */
1347	uint32_t cQueuedCritSectLeaves;
1348	uint32_t uPadding0; /*< Alignment padding./
1349	/** Critical sections queued in RC/R0 because of contention preventing leave to
1350	* complete. (R3 Ptrs)
1351	* We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1352	R3PTRTYPE(PPDMCRITSECT) apQueuedCritSectLeaves[8];
1353
1354	/** The number of entries in the apQueuedCritSectRwExclLeaves table that's
1355	* currently in use. */
1356	uint32_t cQueuedCritSectRwExclLeaves;
1357	uint32_t uPadding1; /*< Alignment padding./
1358	/** Read/write critical sections queued in RC/R0 because of contention
1359	* preventing exclusive leave to complete. (R3 Ptrs)
1360	* We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1361	R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwExclLeaves[8];
1362
1363	/** The number of entries in the apQueuedCritSectsRwShrdLeaves table that's
1364	* currently in use. */
1365	uint32_t cQueuedCritSectRwShrdLeaves;
1366	uint32_t uPadding2; /*< Alignment padding./
1367	/** Read/write critical sections queued in RC/R0 because of contention
1368	* preventing shared leave to complete. (R3 Ptrs)
1369	* We will return to Ring-3 ASAP, so this queue doesn't have to be very long. */
1370	R3PTRTYPE(PPDMCRITSECTRW) apQueuedCritSectRwShrdLeaves[8];
1371	} PDMCPU;
1372
1373
1374	/**
1375	* PDM VM Instance data.
1376	* Changes to this must checked against the padding of the cfgm union in VM!
1377	*/
1378	typedef struct PDM
1379	{
1380	/** The PDM lock.
1381	* This is used to protect everything that deals with interrupts, i.e.
1382	* the PIC, APIC, IOAPIC and PCI devices plus some PDM functions. */
1383	PDMCRITSECT CritSect;
1384	/** The NOP critical section.
1385	* This is a dummy critical section that will not do any thread
1386	* serialization but instead let all threads enter immediately and
1387	* concurrently. */
1388	PDMCRITSECT NopCritSect;
1389
1390	/** The ring-0 capable task sets (max 128). */
1391	PDMTASKSET aTaskSets[2];
1392	/** Pointer to task sets (max 512). */
1393	R3PTRTYPE(PPDMTASKSET) apTaskSets[8];
1394
1395	/** PCI Buses. */
1396	PDMPCIBUS aPciBuses[PDM_PCI_BUSSES_MAX];
1397	/** IOMMU devices. */
1398	PDMIOMMUR3 aIommus[PDM_IOMMUS_MAX];
1399	/** The register PIC device. */
1400	PDMPIC Pic;
1401	/** The registered APIC device. */
1402	PDMAPIC Apic;
1403	/** The registered I/O APIC device. */
1404	PDMIOAPIC IoApic;
1405	/** The registered HPET device. */
1406	PPDMDEVINSR3 pHpet;
1407
1408	/** List of registered devices. (FIFO) */
1409	R3PTRTYPE(PPDMDEV) pDevs;
1410	/** List of devices instances. (FIFO) */
1411	R3PTRTYPE(PPDMDEVINS) pDevInstances;
1412	/** List of registered USB devices. (FIFO) */
1413	R3PTRTYPE(PPDMUSB) pUsbDevs;
1414	/** List of USB devices instances. (FIFO) */
1415	R3PTRTYPE(PPDMUSBINS) pUsbInstances;
1416	/** List of registered drivers. (FIFO) */
1417	R3PTRTYPE(PPDMDRV) pDrvs;
1418	/** The registered firmware device (can be NULL). */
1419	R3PTRTYPE(PPDMFW) pFirmware;
1420	/** The registered DMAC device. */
1421	R3PTRTYPE(PPDMDMAC) pDmac;
1422	/** The registered RTC device. */
1423	R3PTRTYPE(PPDMRTC) pRtc;
1424	/** The registered USB HUBs. (FIFO) */
1425	R3PTRTYPE(PPDMUSBHUB) pUsbHubs;
1426
1427	/** @name Queues
1428	* @{ */
1429	/** Queue in which devhlp tasks are queued for R3 execution - R3 Ptr. */
1430	R3PTRTYPE(PPDMQUEUE) pDevHlpQueueR3;
1431	/** Queue in which devhlp tasks are queued for R3 execution - R0 Ptr. */
1432	R0PTRTYPE(PPDMQUEUE) pDevHlpQueueR0;
1433	/** Queue in which devhlp tasks are queued for R3 execution - RC Ptr. */
1434	RCPTRTYPE(PPDMQUEUE) pDevHlpQueueRC;
1435	/** Pointer to the queue which should be manually flushed - RC Ptr.
1436	* Only touched by EMT. */
1437	RCPTRTYPE(struct PDMQUEUE *) pQueueFlushRC;
1438	/** Pointer to the queue which should be manually flushed - R0 Ptr.
1439	* Only touched by EMT. */
1440	R0PTRTYPE(struct PDMQUEUE *) pQueueFlushR0;
1441	/** Bitmask controlling the queue flushing.
1442	* See PDM_QUEUE_FLUSH_FLAG_ACTIVE and PDM_QUEUE_FLUSH_FLAG_PENDING. */
1443	uint32_t volatile fQueueFlushing;
1444	/** @} */
1445
1446	/** The current IRQ tag (tracing purposes). */
1447	uint32_t volatile uIrqTag;
1448
1449	/** Pending reset flags (PDMVMRESET_F_XXX). */
1450	uint32_t volatile fResetFlags;
1451
1452	/** Set by pdmR3LoadExec for use in assertions. */
1453	bool fStateLoaded;
1454	/** Alignment padding. */
1455	bool afPadding[3];
1456
1457	/** The tracing ID of the next device instance.
1458	*
1459	* @remarks We keep the device tracing ID seperate from the rest as these are
1460	* then more likely to end up with the same ID from one run to
1461	* another, making analysis somewhat easier. Drivers and USB devices
1462	* are more volatile and can be changed at runtime, thus these are much
1463	* less likely to remain stable, so just heap them all together. */
1464	uint32_t idTracingDev;
1465	/** The tracing ID of the next driver instance, USB device instance or other
1466	* PDM entity requiring an ID. */
1467	uint32_t idTracingOther;
1468
1469	/** @name VMM device heap
1470	* @{ */
1471	/** The heap size. */
1472	uint32_t cbVMMDevHeap;
1473	/** Free space. */
1474	uint32_t cbVMMDevHeapLeft;
1475	/** Pointer to the heap base (MMIO2 ring-3 mapping). NULL if not registered. */
1476	RTR3PTR pvVMMDevHeap;
1477	/** Ring-3 mapping/unmapping notification callback for the user. */
1478	PFNPDMVMMDEVHEAPNOTIFY pfnVMMDevHeapNotify;
1479	/** The current mapping. NIL_RTGCPHYS if not mapped or registered. */
1480	RTGCPHYS GCPhysVMMDevHeap;
1481	/** @} */
1482
1483	/** Number of times a critical section leave request needed to be queued for ring-3 execution. */
1484	STAMCOUNTER StatQueuedCritSectLeaves;
1485	/** Number of times we've successfully aborted a wait in ring-0. */
1486	STAMCOUNTER StatAbortedCritSectEnters;
1487	/** Number of times we've got the critical section ownership while trying to
1488	* abort a wait due to VERR_INTERRUPTED. */
1489	STAMCOUNTER StatCritSectEntersWhileAborting;
1490	STAMCOUNTER StatCritSectVerrTimeout;
1491	STAMCOUNTER StatCritSectVerrInterrupted;
1492	STAMCOUNTER StatCritSectNonInterruptibleWaits;
1493	} PDM;
1494	AssertCompileMemberAlignment(PDM, CritSect, 8);
1495	AssertCompileMemberAlignment(PDM, aTaskSets, 64);
1496	AssertCompileMemberAlignment(PDM, StatQueuedCritSectLeaves, 8);
1497	AssertCompileMemberAlignment(PDM, GCPhysVMMDevHeap, sizeof(RTGCPHYS));
1498	/** Pointer to PDM VM instance data. */
1499	typedef PDM *PPDM;
1500
1501
1502	/**
1503	* PDM data kept in the ring-0 GVM.
1504	*/
1505	typedef struct PDMR0PERVM
1506	{
1507	/** PCI Buses, ring-0 data. */
1508	PDMPCIBUSR0 aPciBuses[PDM_PCI_BUSSES_MAX];
1509	/** IOMMUs, ring-0 data. */
1510	PDMIOMMUR0 aIommus[PDM_IOMMUS_MAX];
1511	/** Number of valid ring-0 device instances (apDevInstances). */
1512	uint32_t cDevInstances;
1513	uint32_t u32Padding;
1514	/** Pointer to ring-0 device instances. */
1515	R0PTRTYPE(struct PDMDEVINSR0 *) apDevInstances[190];
1516	} PDMR0PERVM;
1517
1518
1519	/**
1520	* PDM data kept in the UVM.
1521	*/
1522	typedef struct PDMUSERPERVM
1523	{
1524	/** @todo move more stuff over here. */
1525
1526	/** Linked list of timer driven PDM queues.
1527	* Currently serialized by PDM::CritSect. */
1528	R3PTRTYPE(struct PDMQUEUE *) pQueuesTimer;
1529	/** Linked list of force action driven PDM queues.
1530	* Currently serialized by PDM::CritSect. */
1531	R3PTRTYPE(struct PDMQUEUE *) pQueuesForced;
1532
1533	/** Lock protecting the lists below it. */
1534	RTCRITSECT ListCritSect;
1535	/** Pointer to list of loaded modules. */
1536	PPDMMOD pModules;
1537	/** List of initialized critical sections. (LIFO) */
1538	R3PTRTYPE(PPDMCRITSECTINT) pCritSects;
1539	/** List of initialized read/write critical sections. (LIFO) */
1540	R3PTRTYPE(PPDMCRITSECTRWINT) pRwCritSects;
1541	/** Head of the PDM Thread list. (singly linked) */
1542	R3PTRTYPE(PPDMTHREAD) pThreads;
1543	/** Tail of the PDM Thread list. (singly linked) */
1544	R3PTRTYPE(PPDMTHREAD) pThreadsTail;
1545
1546	/** @name PDM Async Completion
1547	* @{ */
1548	/** Pointer to the array of supported endpoint classes. */
1549	PPDMASYNCCOMPLETIONEPCLASS apAsyncCompletionEndpointClass[PDMASYNCCOMPLETIONEPCLASSTYPE_MAX];
1550	/** Head of the templates. Singly linked, protected by ListCritSect. */
1551	R3PTRTYPE(PPDMASYNCCOMPLETIONTEMPLATE) pAsyncCompletionTemplates;
1552	/** @} */
1553
1554	/** Global block cache data. */
1555	R3PTRTYPE(PPDMBLKCACHEGLOBAL) pBlkCacheGlobal;
1556	#ifdef VBOX_WITH_NETSHAPER
1557	/** Pointer to network shaper instance. */
1558	R3PTRTYPE(PPDMNETSHAPER) pNetShaper;
1559	#endif /* VBOX_WITH_NETSHAPER */
1560
1561	} PDMUSERPERVM;
1562	/** Pointer to the PDM data kept in the UVM. */
1563	typedef PDMUSERPERVM *PPDMUSERPERVM;
1564
1565
1566
1567	/*******************************************************************************
1568	* Global Variables *
1569	*******************************************************************************/
1570	#ifdef IN_RING3
1571	extern const PDMDRVHLPR3 g_pdmR3DrvHlp;
1572	extern const PDMDEVHLPR3 g_pdmR3DevHlpTrusted;
1573	# ifdef VBOX_WITH_DBGF_TRACING
1574	extern const PDMDEVHLPR3 g_pdmR3DevHlpTracing;
1575	# endif
1576	extern const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted;
1577	extern const PDMPICHLP g_pdmR3DevPicHlp;
1578	extern const PDMIOAPICHLP g_pdmR3DevIoApicHlp;
1579	extern const PDMFWHLPR3 g_pdmR3DevFirmwareHlp;
1580	extern const PDMPCIHLPR3 g_pdmR3DevPciHlp;
1581	extern const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp;
1582	extern const PDMDMACHLP g_pdmR3DevDmacHlp;
1583	extern const PDMRTCHLP g_pdmR3DevRtcHlp;
1584	extern const PDMHPETHLPR3 g_pdmR3DevHpetHlp;
1585	extern const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp;
1586	#endif
1587
1588
1589	/*******************************************************************************
1590	* Defined Constants And Macros *
1591	*******************************************************************************/
1592	/** @def PDMDEV_ASSERT_DEVINS
1593	* Asserts the validity of the device instance.
1594	*/
1595	#ifdef VBOX_STRICT
1596	# define PDMDEV_ASSERT_DEVINS(pDevIns) \
1597	do { \
1598	AssertPtr(pDevIns); \
1599	Assert(pDevIns->u32Version == PDM_DEVINS_VERSION); \
1600	Assert(pDevIns->CTX_SUFF(pvInstanceDataFor) == (void *)&pDevIns->achInstanceData[0]); \
1601	} while (0)
1602	#else
1603	# define PDMDEV_ASSERT_DEVINS(pDevIns) do { } while (0)
1604	#endif
1605
1606	/** @def PDMDRV_ASSERT_DRVINS
1607	* Asserts the validity of the driver instance.
1608	*/
1609	#ifdef VBOX_STRICT
1610	# define PDMDRV_ASSERT_DRVINS(pDrvIns) \
1611	do { \
1612	AssertPtr(pDrvIns); \
1613	Assert(pDrvIns->u32Version == PDM_DRVINS_VERSION); \
1614	Assert(pDrvIns->CTX_SUFF(pvInstanceData) == (void *)&pDrvIns->achInstanceData[0]); \
1615	} while (0)
1616	#else
1617	# define PDMDRV_ASSERT_DRVINS(pDrvIns) do { } while (0)
1618	#endif
1619
1620
1621	/*******************************************************************************
1622	* Internal Functions *
1623	*******************************************************************************/
1624	#ifdef IN_RING3
1625	bool pdmR3IsValidName(const char *pszName);
1626
1627	int pdmR3CritSectBothInitStatsAndInfo(PVM pVM);
1628	int pdmR3CritSectBothDeleteDevice(PVM pVM, PPDMDEVINS pDevIns);
1629	int pdmR3CritSectBothDeleteDriver(PVM pVM, PPDMDRVINS pDrvIns);
1630	int pdmR3CritSectInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1631	const char *pszNameFmt, va_list va);
1632	int pdmR3CritSectInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1633	const char *pszNameFmt, ...);
1634	int pdmR3CritSectInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1635	const char *pszNameFmt, ...);
1636	int pdmR3CritSectRwInitDevice( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1637	const char *pszNameFmt, va_list va);
1638	int pdmR3CritSectRwInitDeviceAuto( PVM pVM, PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1639	const char *pszNameFmt, ...);
1640	int pdmR3CritSectRwInitDriver( PVM pVM, PPDMDRVINS pDrvIns, PPDMCRITSECTRW pCritSect, RT_SRC_POS_DECL,
1641	const char *pszNameFmt, ...);
1642
1643	int pdmR3DevInit(PVM pVM);
1644	int pdmR3DevInitComplete(PVM pVM);
1645	PPDMDEV pdmR3DevLookup(PVM pVM, const char *pszName);
1646	int pdmR3DevFindLun(PVM pVM, const char pszDevice, unsigned iInstance, unsigned iLun, PPDMLUN ppLun);
1647	DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem);
1648
1649	int pdmR3UsbLoadModules(PVM pVM);
1650	int pdmR3UsbInstantiateDevices(PVM pVM);
1651	PPDMUSB pdmR3UsbLookup(PVM pVM, const char *pszName);
1652	int pdmR3UsbRegisterHub(PVM pVM, PPDMDRVINS pDrvIns, uint32_t fVersions, uint32_t cPorts, PCPDMUSBHUBREG pUsbHubReg, PPCPDMUSBHUBHLP ppUsbHubHlp);
1653	int pdmR3UsbVMInitComplete(PVM pVM);
1654
1655	int pdmR3DrvInit(PVM pVM);
1656	int pdmR3DrvInstantiate(PVM pVM, PCFGMNODE pNode, PPDMIBASE pBaseInterface, PPDMDRVINS pDrvAbove,
1657	PPDMLUN pLun, PPDMIBASE *ppBaseInterface);
1658	int pdmR3DrvDetach(PPDMDRVINS pDrvIns, uint32_t fFlags);
1659	void pdmR3DrvDestroyChain(PPDMDRVINS pDrvIns, uint32_t fFlags);
1660	PPDMDRV pdmR3DrvLookup(PVM pVM, const char *pszName);
1661
1662	int pdmR3LdrInitU(PUVM pUVM);
1663	void pdmR3LdrTermU(PUVM pUVM, bool fFinal);
1664	char pdmR3FileR3(const char pszFile, bool fShared);
1665	int pdmR3LoadR3U(PUVM pUVM, const char pszFilename, const char pszName);
1666
1667	void pdmR3QueueRelocate(PVM pVM, RTGCINTPTR offDelta);
1668
1669	int pdmR3TaskInit(PVM pVM);
1670	void pdmR3TaskTerm(PVM pVM);
1671
1672	int pdmR3ThreadCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
1673	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1674	int pdmR3ThreadCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADUSB pfnThread,
1675	PFNPDMTHREADWAKEUPUSB pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1676	int pdmR3ThreadCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDRV pfnThread,
1677	PFNPDMTHREADWAKEUPDRV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName);
1678	int pdmR3ThreadDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1679	int pdmR3ThreadDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1680	int pdmR3ThreadDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1681	void pdmR3ThreadDestroyAll(PVM pVM);
1682	int pdmR3ThreadResumeAll(PVM pVM);
1683	int pdmR3ThreadSuspendAll(PVM pVM);
1684
1685	#ifdef VBOX_WITH_PDM_ASYNC_COMPLETION
1686	int pdmR3AsyncCompletionInit(PVM pVM);
1687	int pdmR3AsyncCompletionTerm(PVM pVM);
1688	void pdmR3AsyncCompletionResume(PVM pVM);
1689	int pdmR3AsyncCompletionTemplateCreateDevice(PVM pVM, PPDMDEVINS pDevIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEDEV pfnCompleted, const char *pszDesc);
1690	int pdmR3AsyncCompletionTemplateCreateDriver(PVM pVM, PPDMDRVINS pDrvIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate,
1691	PFNPDMASYNCCOMPLETEDRV pfnCompleted, void pvTemplateUser, const char pszDesc);
1692	int pdmR3AsyncCompletionTemplateCreateUsb(PVM pVM, PPDMUSBINS pUsbIns, PPPDMASYNCCOMPLETIONTEMPLATE ppTemplate, PFNPDMASYNCCOMPLETEUSB pfnCompleted, const char *pszDesc);
1693	int pdmR3AsyncCompletionTemplateDestroyDevice(PVM pVM, PPDMDEVINS pDevIns);
1694	int pdmR3AsyncCompletionTemplateDestroyDriver(PVM pVM, PPDMDRVINS pDrvIns);
1695	int pdmR3AsyncCompletionTemplateDestroyUsb(PVM pVM, PPDMUSBINS pUsbIns);
1696	#endif
1697
1698	#ifdef VBOX_WITH_NETSHAPER
1699	int pdmR3NetShaperInit(PVM pVM);
1700	int pdmR3NetShaperTerm(PVM pVM);
1701	#endif
1702
1703	int pdmR3BlkCacheInit(PVM pVM);
1704	void pdmR3BlkCacheTerm(PVM pVM);
1705	int pdmR3BlkCacheResume(PVM pVM);
1706
1707	#endif /* IN_RING3 */
1708
1709	void pdmLock(PVMCC pVM);
1710	int pdmLockEx(PVMCC pVM, int rcBusy);
1711	void pdmUnlock(PVMCC pVM);
1712	bool pdmLockIsOwner(PVMCC pVM);
1713
1714	#if defined(VBOX_WITH_IOMMU_AMD) \|\| defined(VBOX_WITH_IOMMU_INTEL)
1715	bool pdmIommuIsPresent(PPDMDEVINS pDevIns);
1716	int pdmIommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut);
1717	int pdmIommuMemAccessRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1718	int pdmIommuMemAccessWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1719	# ifdef IN_RING3
1720	int pdmR3IommuMemAccessReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void const **ppv, PPGMPAGEMAPLOCK pLock);
1721	int pdmR3IommuMemAccessWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock);
1722	int pdmR3IommuMemAccessBulkReadCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, const void **papvPages, PPGMPAGEMAPLOCK paLocks);
1723	int pdmR3IommuMemAccessBulkWriteCCPtr(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t cPages, PCRTGCPHYS paGCPhysPages, uint32_t fFlags, void **papvPages, PPGMPAGEMAPLOCK paLocks);
1724	# endif
1725	#endif
1726
1727	#if defined(IN_RING3) \|\| defined(IN_RING0)
1728	void pdmCritSectRwLeaveSharedQueued(PVMCC pVM, PPDMCRITSECTRW pThis);
1729	void pdmCritSectRwLeaveExclQueued(PVMCC pVM, PPDMCRITSECTRW pThis);
1730	#endif
1731
1732	#ifdef IN_RING0
1733	DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc);
1734	#endif
1735
1736	#ifdef VBOX_WITH_DBGF_TRACING
1737	# ifdef IN_RING3
1738	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortCreateEx(PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
1739	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1740	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
1741	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts);
1742	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortMap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT Port);
1743	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_IoPortUnmap(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts);
1744	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioCreateEx(PPDMDEVINS pDevIns, RTGCPHYS cbRegion,
1745	uint32_t fFlags, PPDMPCIDEV pPciDev, uint32_t iPciRegion,
1746	PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill,
1747	void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion);
1748	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioMap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys);
1749	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_MmioUnmap(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion);
1750	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1751	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1752	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1753	DECL_HIDDEN_CALLBACK(int) pdmR3DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1754	DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1755	DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1756	DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1757	DECL_HIDDEN_CALLBACK(void) pdmR3DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1758	# elif defined(IN_RING0)
1759	DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
1760	PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
1761	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
1762	void *pvUser);
1763	DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
1764	PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser);
1765	DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1766	DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1767	DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags);
1768	DECL_HIDDEN_CALLBACK(int) pdmR0DevHlpTracing_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags);
1769	DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1770	DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel);
1771	DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1772	DECL_HIDDEN_CALLBACK(void) pdmR0DevHlpTracing_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel);
1773	# else
1774	# error "Invalid environment selected"
1775	# endif
1776	#endif
1777
1778
1779	/** @} */
1780
1781	RT_C_DECLS_END
1782
1783	#endif /* !VMM_INCLUDED_SRC_include_PDMInternal_h */
1784

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source: vbox/trunk/src/VBox/VMM/include/PDMInternal.h@ 90570

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