PGMInternal.h@ 58591

Last change on this file since 58591 was 58123, checked in by vboxsync, 9 years ago
VMM: Made @param pVCpu more uniform and to the point.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
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1	/* $Id: PGMInternal.h 58123 2015-10-08 18:09:45Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___PGMInternal_h
19	#define ___PGMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/err.h>
24	#include <VBox/dbg.h>
25	#include <VBox/vmm/stam.h>
26	#include <VBox/param.h>
27	#include <VBox/vmm/vmm.h>
28	#include <VBox/vmm/mm.h>
29	#include <VBox/vmm/pdmcritsect.h>
30	#include <VBox/vmm/pdmapi.h>
31	#include <VBox/dis.h>
32	#include <VBox/vmm/dbgf.h>
33	#include <VBox/log.h>
34	#include <VBox/vmm/gmm.h>
35	#include <VBox/vmm/hm.h>
36	#include <VBox/vmm/hm_vmx.h>
37	#include "internal/pgm.h"
38	#include <iprt/asm.h>
39	#include <iprt/assert.h>
40	#include <iprt/avl.h>
41	#include <iprt/critsect.h>
42	#include <iprt/list-off32.h>
43	#include <iprt/sha.h>
44
45
46
47	/** @defgroup grp_pgm_int Internals
48	* @ingroup grp_pgm
49	* @internal
50	* @{
51	*/
52
53
54	/** @name PGM Compile Time Config
55	* @{
56	*/
57
58	/**
59	* Indicates that there are no guest mappings in the shadow tables.
60	*
61	* Note! In ring-3 the macro is also used to exclude the managment of the
62	* intermediate context page tables. On 32-bit systems we use the intermediate
63	* context to support 64-bit guest execution. Thus, we cannot fully make it
64	* without mappings there even when VBOX_WITH_RAW_MODE is not defined.
65	*
66	* In raw-mode context there are by design always guest mappings (the code is
67	* executed from one), while in ring-0 there are none at all. Neither context
68	* manages the page tables for intermediate switcher context, that's all done in
69	* ring-3.
70	*/
71	#if defined(IN_RING0) \
72	\|\| ( !defined(VBOX_WITH_RAW_MODE) \
73	&& ( HC_ARCH_BITS != 32 \
74	\|\| !defined(VBOX_WITH_64_BITS_GUESTS) \
75	) \
76	)
77	# define PGM_WITHOUT_MAPPINGS
78	#endif
79
80	/**
81	* Check and skip global PDEs for non-global flushes
82	*/
83	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
84
85	/**
86	* Optimization for PAE page tables that are modified often
87	*/
88	//#if 0 /* disabled again while debugging */
89	#ifndef IN_RC
90	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
91	#endif
92	//#endif
93
94	/**
95	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
96	*/
97	#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
98	# define PGM_WITH_LARGE_PAGES
99	#endif
100
101	/**
102	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
103	* VMX_EXIT_EPT_MISCONFIG.
104	*/
105	#if 1 /* testing */
106	# define PGM_WITH_MMIO_OPTIMIZATIONS
107	#endif
108
109	/**
110	* Sync N pages instead of a whole page table
111	*/
112	#define PGM_SYNC_N_PAGES
113
114	/**
115	* Number of pages to sync during a page fault
116	*
117	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
118	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
119	*
120	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
121	* world switch overhead, so let's sync more.
122	*/
123	# ifdef IN_RING0
124	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
125	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
126	* but ~5% fewer faults.
127	*/
128	# define PGM_SYNC_NR_PAGES 32
129	#else
130	# define PGM_SYNC_NR_PAGES 8
131	#endif
132
133	/**
134	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
135	*/
136	#define PGM_MAX_PHYSCACHE_ENTRIES 64
137	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
138
139
140	/** @def PGMPOOL_CFG_MAX_GROW
141	* The maximum number of pages to add to the pool in one go.
142	*/
143	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
144
145	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
146	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
147	*/
148	#ifdef VBOX_STRICT
149	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
150	#endif
151
152	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
153	* Enables the experimental lazy page allocation code. */
154	#ifdef DOXYGEN_RUNNING
155	# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
156	#endif
157
158	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
159	* Enables real write monitoring of pages, i.e. mapping them read-only and
160	* only making them writable when getting a write access \#PF. */
161	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
162
163	/** @} */
164
165
166	/** @name PDPT and PML4 flags.
167	* These are placed in the three bits available for system programs in
168	* the PDPT and PML4 entries.
169	* @{ */
170	/** The entry is a permanent one and it's must always be present.
171	* Never free such an entry. */
172	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
173	/** Mapping (hypervisor allocated pagetable). */
174	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
175	/** @} */
176
177	/** @name Page directory flags.
178	* These are placed in the three bits available for system programs in
179	* the page directory entries.
180	* @{ */
181	/** Mapping (hypervisor allocated pagetable). */
182	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
183	/** Made read-only to facilitate dirty bit tracking. */
184	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
185	/** @} */
186
187	/** @name Page flags.
188	* These are placed in the three bits available for system programs in
189	* the page entries.
190	* @{ */
191	/** Made read-only to facilitate dirty bit tracking. */
192	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
193
194	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
195	/** Scanned and approved by CSAM (tm).
196	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
197	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
198	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
199	#endif
200
201	/** @} */
202
203	/** @name Defines used to indicate the shadow and guest paging in the templates.
204	* @{ */
205	#define PGM_TYPE_REAL 1
206	#define PGM_TYPE_PROT 2
207	#define PGM_TYPE_32BIT 3
208	#define PGM_TYPE_PAE 4
209	#define PGM_TYPE_AMD64 5
210	#define PGM_TYPE_NESTED 6
211	#define PGM_TYPE_EPT 7
212	#define PGM_TYPE_MAX PGM_TYPE_EPT
213	/** @} */
214
215	/** Macro for checking if the guest is using paging.
216	* @param uGstType PGM_TYPE_*
217	* @param uShwType PGM_TYPE_*
218	* @remark ASSUMES certain order of the PGM_TYPE_* values.
219	*/
220	#define PGM_WITH_PAGING(uGstType, uShwType) \
221	( (uGstType) >= PGM_TYPE_32BIT \
222	&& (uShwType) != PGM_TYPE_NESTED \
223	&& (uShwType) != PGM_TYPE_EPT)
224
225	/** Macro for checking if the guest supports the NX bit.
226	* @param uGstType PGM_TYPE_*
227	* @param uShwType PGM_TYPE_*
228	* @remark ASSUMES certain order of the PGM_TYPE_* values.
229	*/
230	#define PGM_WITH_NX(uGstType, uShwType) \
231	( (uGstType) >= PGM_TYPE_PAE \
232	&& (uShwType) != PGM_TYPE_NESTED \
233	&& (uShwType) != PGM_TYPE_EPT)
234
235
236	/** @def PGM_HCPHYS_2_PTR
237	* Maps a HC physical page pool address to a virtual address.
238	*
239	* @returns VBox status code.
240	* @param pVM The cross context VM structure.
241	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
242	* @param HCPhys The HC physical address to map to a virtual one.
243	* @param ppv Where to store the virtual address. No need to cast
244	* this.
245	*
246	* @remark Use with care as we don't have so much dynamic mapping space in
247	* ring-0 on 32-bit darwin and in RC.
248	* @remark There is no need to assert on the result.
249	*/
250	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
251	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
252	pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
253	#else
254	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
255	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
256	#endif
257
258	/** @def PGM_GCPHYS_2_PTR_V2
259	* Maps a GC physical page address to a virtual address.
260	*
261	* @returns VBox status code.
262	* @param pVM The cross context VM structure.
263	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
264	* @param GCPhys The GC physical address to map to a virtual one.
265	* @param ppv Where to store the virtual address. No need to cast this.
266	*
267	* @remark Use with care as we don't have so much dynamic mapping space in
268	* ring-0 on 32-bit darwin and in RC.
269	* @remark There is no need to assert on the result.
270	*/
271	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
272	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
273	pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
274	#else
275	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
276	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
277	#endif
278
279	/** @def PGM_GCPHYS_2_PTR
280	* Maps a GC physical page address to a virtual address.
281	*
282	* @returns VBox status code.
283	* @param pVM The cross context VM structure.
284	* @param GCPhys The GC physical address to map to a virtual one.
285	* @param ppv Where to store the virtual address. No need to cast this.
286	*
287	* @remark Use with care as we don't have so much dynamic mapping space in
288	* ring-0 on 32-bit darwin and in RC.
289	* @remark There is no need to assert on the result.
290	*/
291	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
292
293	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
294	* Maps a GC physical page address to a virtual address.
295	*
296	* @returns VBox status code.
297	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
298	* @param GCPhys The GC physical address to map to a virtual one.
299	* @param ppv Where to store the virtual address. No need to cast this.
300	*
301	* @remark Use with care as we don't have so much dynamic mapping space in
302	* ring-0 on 32-bit darwin and in RC.
303	* @remark There is no need to assert on the result.
304	*/
305	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
306
307	/** @def PGM_GCPHYS_2_PTR_EX
308	* Maps a unaligned GC physical page address to a virtual address.
309	*
310	* @returns VBox status code.
311	* @param pVM The cross context VM structure.
312	* @param GCPhys The GC physical address to map to a virtual one.
313	* @param ppv Where to store the virtual address. No need to cast this.
314	*
315	* @remark Use with care as we don't have so much dynamic mapping space in
316	* ring-0 on 32-bit darwin and in RC.
317	* @remark There is no need to assert on the result.
318	*/
319	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
320	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
321	pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
322	#else
323	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
324	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
325	#endif
326
327	/** @def PGM_DYNMAP_UNUSED_HINT
328	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
329	* is no longer used.
330	*
331	* For best effect only apply this to the page that was mapped most recently.
332	*
333	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
334	* @param pvPage The pool page.
335	*/
336	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
337	# ifdef LOG_ENABLED
338	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
339	# else
340	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
341	# endif
342	#else
343	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
344	#endif
345
346	/** @def PGM_DYNMAP_UNUSED_HINT_VM
347	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
348	* is no longer used.
349	*
350	* For best effect only apply this to the page that was mapped most recently.
351	*
352	* @param pVM The cross context VM structure.
353	* @param pvPage The pool page.
354	*/
355	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
356
357
358	/** @def PGM_INVL_PG
359	* Invalidates a page.
360	*
361	* @param pVCpu The cross context virtual CPU structure.
362	* @param GCVirt The virtual address of the page to invalidate.
363	*/
364	#ifdef IN_RC
365	# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
366	#elif defined(IN_RING0)
367	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
368	#else
369	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
370	#endif
371
372	/** @def PGM_INVL_PG_ALL_VCPU
373	* Invalidates a page on all VCPUs
374	*
375	* @param pVM The cross context VM structure.
376	* @param GCVirt The virtual address of the page to invalidate.
377	*/
378	#ifdef IN_RC
379	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
380	#elif defined(IN_RING0)
381	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
382	#else
383	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
384	#endif
385
386	/** @def PGM_INVL_BIG_PG
387	* Invalidates a 4MB page directory entry.
388	*
389	* @param pVCpu The cross context virtual CPU structure.
390	* @param GCVirt The virtual address within the page directory to invalidate.
391	*/
392	#ifdef IN_RC
393	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
394	#elif defined(IN_RING0)
395	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
396	#else
397	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
398	#endif
399
400	/** @def PGM_INVL_VCPU_TLBS()
401	* Invalidates the TLBs of the specified VCPU
402	*
403	* @param pVCpu The cross context virtual CPU structure.
404	*/
405	#ifdef IN_RC
406	# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
407	#elif defined(IN_RING0)
408	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
409	#else
410	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
411	#endif
412
413	/** @def PGM_INVL_ALL_VCPU_TLBS()
414	* Invalidates the TLBs of all VCPUs
415	*
416	* @param pVM The cross context VM structure.
417	*/
418	#ifdef IN_RC
419	# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
420	#elif defined(IN_RING0)
421	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
422	#else
423	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
424	#endif
425
426
427	/** @name Safer Shadow PAE PT/PTE
428	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
429	* present.
430	*
431	* @{
432	*/
433	#if 1
434	/**
435	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
436	* invalid entries for present.
437	* @sa X86PTEPAE.
438	*/
439	typedef union PGMSHWPTEPAE
440	{
441	/** Unsigned integer view */
442	X86PGPAEUINT uCareful;
443	/* Not other views. */
444	} PGMSHWPTEPAE;
445
446	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
447	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
448	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
449	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
450	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
451	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
452	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
453	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
454	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
455	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
456	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
457	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
458	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
459	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
460	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
461	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
462
463	/**
464	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
465	* invalid entries for present.
466	* @sa X86PTPAE.
467	*/
468	typedef struct PGMSHWPTPAE
469	{
470	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
471	} PGMSHWPTPAE;
472
473	#else
474	typedef X86PTEPAE PGMSHWPTEPAE;
475	typedef X86PTPAE PGMSHWPTPAE;
476	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
477	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
478	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
479	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
480	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
481	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
482	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
483	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
484	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
485	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
486	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
487	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
488	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
489	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
490	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
491	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
492
493	#endif
494
495	/** Pointer to a shadow PAE PTE. */
496	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
497	/** Pointer to a const shadow PAE PTE. */
498	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
499
500	/** Pointer to a shadow PAE page table. */
501	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
502	/** Pointer to a const shadow PAE page table. */
503	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
504	/** @} */
505
506
507	/** Size of the GCPtrConflict array in PGMMAPPING.
508	* @remarks Must be a power of two. */
509	#define PGMMAPPING_CONFLICT_MAX 8
510
511	/**
512	* Structure for tracking GC Mappings.
513	*
514	* This structure is used by linked list in both GC and HC.
515	*/
516	typedef struct PGMMAPPING
517	{
518	/** Pointer to next entry. */
519	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
520	/** Pointer to next entry. */
521	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
522	/** Pointer to next entry. */
523	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
524	/** Indicate whether this entry is finalized. */
525	bool fFinalized;
526	/** Start Virtual address. */
527	RTGCPTR GCPtr;
528	/** Last Virtual address (inclusive). */
529	RTGCPTR GCPtrLast;
530	/** Range size (bytes). */
531	RTGCPTR cb;
532	/** Pointer to relocation callback function. */
533	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
534	/** User argument to the callback. */
535	R3PTRTYPE(void *) pvUser;
536	/** Mapping description / name. For easing debugging. */
537	R3PTRTYPE(const char *) pszDesc;
538	/** Last 8 addresses that caused conflicts. */
539	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
540	/** Number of conflicts for this hypervisor mapping. */
541	uint32_t cConflicts;
542	/** Number of page tables. */
543	uint32_t cPTs;
544
545	/** Array of page table mapping data. Each entry
546	* describes one page table. The array can be longer
547	* than the declared length.
548	*/
549	struct
550	{
551	/** The HC physical address of the page table. */
552	RTHCPHYS HCPhysPT;
553	/** The HC physical address of the first PAE page table. */
554	RTHCPHYS HCPhysPaePT0;
555	/** The HC physical address of the second PAE page table. */
556	RTHCPHYS HCPhysPaePT1;
557	/** The HC virtual address of the 32-bit page table. */
558	R3PTRTYPE(PX86PT) pPTR3;
559	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
560	R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
561	/** The RC virtual address of the 32-bit page table. */
562	RCPTRTYPE(PX86PT) pPTRC;
563	/** The RC virtual address of the two PAE page table. */
564	RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
565	/** The R0 virtual address of the 32-bit page table. */
566	R0PTRTYPE(PX86PT) pPTR0;
567	/** The R0 virtual address of the two PAE page table. */
568	R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
569	} aPTs[1];
570	} PGMMAPPING;
571	/** Pointer to structure for tracking GC Mappings. */
572	typedef struct PGMMAPPING *PPGMMAPPING;
573
574
575	/**
576	* Physical page access handler type registration.
577	*/
578	typedef struct PGMPHYSHANDLERTYPEINT
579	{
580	/** Number of references. */
581	uint32_t volatile cRefs;
582	/** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
583	uint32_t u32Magic;
584	/** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
585	RTLISTOFF32NODE ListNode;
586	/** The kind of accesses we're handling. */
587	PGMPHYSHANDLERKIND enmKind;
588	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
589	uint32_t uState;
590	/** Pointer to RC callback function. */
591	RCPTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerRC;
592	/** Pointer to RC callback function for \#PFs. */
593	RCPTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerRC;
594	/** Pointer to R3 callback function. */
595	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
596	/** Pointer to R0 callback function. */
597	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
598	/** Pointer to R0 callback function for \#PFs. */
599	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
600	/** Description / Name. For easing debugging. */
601	R3PTRTYPE(const char *) pszDesc;
602	} PGMPHYSHANDLERTYPEINT;
603	/** Pointer to a physical access handler type registration. */
604	typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
605	/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
606	#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
607	/** Magic value for the physical handler callbacks. */
608	#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
609
610	/**
611	* Converts a handle to a pointer.
612	* @returns PPGMPHYSHANDLERTYPEINT
613	* @param a_pVM The cross context VM structure.
614	* @param a_hType Physical access handler type handle.
615	*/
616	#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
617
618
619	/**
620	* Physical page access handler structure.
621	*
622	* This is used to keep track of physical address ranges
623	* which are being monitored in some kind of way.
624	*/
625	typedef struct PGMPHYSHANDLER
626	{
627	AVLROGCPHYSNODECORE Core;
628	/** Number of pages to update. */
629	uint32_t cPages;
630	/** Set if we have pages that have been aliased. */
631	uint32_t cAliasedPages;
632	/** Set if we have pages that have temporarily been disabled. */
633	uint32_t cTmpOffPages;
634	/** Registered handler type handle (heap offset). */
635	PGMPHYSHANDLERTYPE hType;
636	/** User argument for RC handlers. */
637	RCPTRTYPE(void *) pvUserRC;
638	#if HC_ARCH_BITS == 64
639	RTRCPTR Padding0; /*< Explicit alignment padding. /
640	#endif
641	/** User argument for R3 handlers. */
642	R3PTRTYPE(void *) pvUserR3;
643	/** User argument for R0 handlers. */
644	R0PTRTYPE(void *) pvUserR0;
645	/** Description / Name. For easing debugging. */
646	R3PTRTYPE(const char *) pszDesc;
647	#ifdef VBOX_WITH_STATISTICS
648	/** Profiling of this handler. */
649	STAMPROFILE Stat;
650	#endif
651	} PGMPHYSHANDLER;
652	/** Pointer to a physical page access handler structure. */
653	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
654
655	/**
656	* Gets the type record for a physical handler (no reference added).
657	* @returns PPGMPHYSHANDLERTYPEINT
658	* @param a_pVM The cross context VM structure.
659	* @param a_pPhysHandler Pointer to the physical handler structure
660	* (PGMPHYSHANDLER).
661	*/
662	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
663
664
665	#ifdef VBOX_WITH_RAW_MODE
666
667	/**
668	* Cache node for the physical addresses covered by a virtual handler.
669	*/
670	typedef struct PGMPHYS2VIRTHANDLER
671	{
672	/** Core node for the tree based on physical ranges. */
673	AVLROGCPHYSNODECORE Core;
674	/** Offset from this struct to the PGMVIRTHANDLER structure. */
675	int32_t offVirtHandler;
676	/** Offset of the next alias relative to this one.
677	* Bit 0 is used for indicating whether we're in the tree.
678	* Bit 1 is used for indicating that we're the head node.
679	*/
680	int32_t offNextAlias;
681	} PGMPHYS2VIRTHANDLER;
682	/** Pointer to a phys to virtual handler structure. */
683	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
684
685	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
686	* node is in the tree. */
687	# define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
688	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
689	* node is in the head of an alias chain.
690	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
691	# define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
692	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
693	# define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
694
695
696	/**
697	* Virtual page access handler type registration.
698	*/
699	typedef struct PGMVIRTANDLERTYPEINT
700	{
701	/** Number of references. */
702	uint32_t volatile cRefs;
703	/** Magic number (PGMVIRTHANDLERTYPEINT_MAGIC). */
704	uint32_t u32Magic;
705	/** Link of handler types anchored in PGMTREES::HeadVirtHandlerTypes. */
706	RTLISTOFF32NODE ListNode;
707	/** The kind of accesses we're handling. */
708	PGMVIRTHANDLERKIND enmKind;
709	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
710	uint32_t uState;
711	/** Whether the pvUserRC argument should be automatically relocated or not. */
712	bool fRelocUserRC;
713	bool afPadding[HC_ARCH_BITS == 64 ? 7 : 3];
714	/** Pointer to RC callback function. */
715	RCPTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerRC;
716	/** Pointer to RC callback function for \#PFs. */
717	RCPTRTYPE(PFNPGMRCVIRTPFHANDLER) pfnPfHandlerRC;
718	/** Pointer to the R3 callback function for invalidation. */
719	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
720	/** Pointer to R3 callback function. */
721	R3PTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerR3;
722	/** Description / Name. For easing debugging. */
723	R3PTRTYPE(const char *) pszDesc;
724	} PGMVIRTHANDLERTYPEINT;
725	/** Pointer to a virtual access handler type registration. */
726	typedef PGMVIRTHANDLERTYPEINT *PPGMVIRTHANDLERTYPEINT;
727	/** Magic value for the virtual handler callbacks (Sir Arthur Charles Clarke). */
728	# define PGMVIRTHANDLERTYPEINT_MAGIC UINT32_C(0x19171216)
729	/** Magic value for the virtual handler callbacks. */
730	# define PGMVIRTHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x20080319)
731
732	/**
733	* Converts a handle to a pointer.
734	* @returns PPGMVIRTHANDLERTYPEINT
735	* @param a_pVM The cross context VM structure.
736	* @param a_hType Vitual access handler type handle.
737	*/
738	# define PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMVIRTHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
739
740
741	/**
742	* Virtual page access handler structure.
743	*
744	* This is used to keep track of virtual address ranges
745	* which are being monitored in some kind of way.
746	*/
747	typedef struct PGMVIRTHANDLER
748	{
749	/** Core node for the tree based on virtual ranges. */
750	AVLROGCPTRNODECORE Core;
751	/** Size of the range (in bytes). */
752	uint32_t cb;
753	/** Number of cache pages. */
754	uint32_t cPages;
755	/** Registered handler type handle (heap offset). */
756	PGMVIRTHANDLERTYPE hType;
757	/** User argument for RC handlers. */
758	RCPTRTYPE(void *) pvUserRC;
759	/** User argument for R3 handlers. */
760	R3PTRTYPE(void *) pvUserR3;
761	/** Description / Name. For easing debugging. */
762	R3PTRTYPE(const char *) pszDesc;
763	# ifdef VBOX_WITH_STATISTICS
764	/** Profiling of this handler. */
765	STAMPROFILE Stat;
766	# endif
767	/** Array of cached physical addresses for the monitored ranged. */
768	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
769	} PGMVIRTHANDLER;
770	/** Pointer to a virtual page access handler structure. */
771	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
772
773	/**
774	* Gets the type record for a virtual handler (no reference added).
775	* @returns PPGMVIRTHANDLERTYPEINT
776	* @param a_pVM The cross context VM structure.
777	* @param a_pVirtHandler Pointer to the virtual handler structure
778	* (PGMVIRTHANDLER).
779	*/
780	# define PGMVIRTANDLER_GET_TYPE(a_pVM, a_pVirtHandler) PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pVirtHandler)->hType)
781
782	#endif /* VBOX_WITH_RAW_MODE */
783
784
785	/** @name Page type predicates.
786	* @{ */
787	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
788	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
789	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
790	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
791	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
792	/** @} */
793
794
795	/**
796	* A Physical Guest Page tracking structure.
797	*
798	* The format of this structure is complicated because we have to fit a lot
799	* of information into as few bits as possible. The format is also subject
800	* to change (there is one coming up soon). Which means that for we'll be
801	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
802	* accesses to the structure.
803	*/
804	typedef union PGMPAGE
805	{
806	/** Structured view. */
807	struct
808	{
809	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
810	uint64_t u2HandlerPhysStateY : 2;
811	/** 3:2 - Paging structure needed to map the page
812	* (PGM_PAGE_PDE_TYPE_). /
813	uint64_t u2PDETypeY : 2;
814	/** 4 - Indicator of dirty page for fault tolerance tracking. */
815	uint64_t fFTDirtyY : 1;
816	/** 5 - Flag indicating that a write monitored page was written to
817	* when set. */
818	uint64_t fWrittenToY : 1;
819	/** 7:6 - Unused. */
820	uint64_t u2Unused0 : 2;
821	/** 9:8 - The physical handler state (PGM_PAGE_HNDL_VIRT_STATE_). /
822	uint64_t u2HandlerVirtStateY : 2;
823	/** 11:10 - Unused. */
824	uint64_t u2Unused1 : 2;
825	/** 12:48 - The host physical frame number (shift left to get the
826	* address). */
827	uint64_t HCPhysFN : 36;
828	/** 50:48 - The page state. */
829	uint64_t uStateY : 3;
830	/** 51:53 - The page type (PGMPAGETYPE). */
831	uint64_t uTypeY : 3;
832	/** 63:54 - PTE index for usage tracking (page pool). */
833	uint64_t u10PteIdx : 10;
834
835	/** The GMM page ID.
836	* @remarks In the current implementation, MMIO2 and pages aliased to
837	* MMIO2 pages will be exploiting this field to calculate the
838	* ring-3 mapping address corresponding to the page.
839	* Later we may consider including MMIO2 management into GMM. */
840	uint32_t idPage;
841	/** Usage tracking (page pool). */
842	uint16_t u16TrackingY;
843	/** The number of read locks on this page. */
844	uint8_t cReadLocksY;
845	/** The number of write locks on this page. */
846	uint8_t cWriteLocksY;
847	} s;
848
849	/** 64-bit integer view. */
850	uint64_t au64[2];
851	/** 16-bit view. */
852	uint32_t au32[4];
853	/** 16-bit view. */
854	uint16_t au16[8];
855	/** 8-bit view. */
856	uint8_t au8[16];
857	} PGMPAGE;
858	AssertCompileSize(PGMPAGE, 16);
859	/** Pointer to a physical guest page. */
860	typedef PGMPAGE *PPGMPAGE;
861	/** Pointer to a const physical guest page. */
862	typedef const PGMPAGE *PCPGMPAGE;
863	/** Pointer to a physical guest page pointer. */
864	typedef PPGMPAGE *PPPGMPAGE;
865
866
867	/**
868	* Clears the page structure.
869	* @param a_pPage Pointer to the physical guest page tracking structure.
870	*/
871	#define PGM_PAGE_CLEAR(a_pPage) \
872	do { \
873	(a_pPage)->au64[0] = 0; \
874	(a_pPage)->au64[1] = 0; \
875	} while (0)
876
877	/**
878	* Initializes the page structure.
879	* @param a_pPage Pointer to the physical guest page tracking structure.
880	* @param a_HCPhys The host physical address of the page.
881	* @param a_idPage The (GMM) page ID of the page.
882	* @param a_uType The page type (PGMPAGETYPE).
883	* @param a_uState The page state (PGM_PAGE_STATE_XXX).
884	*/
885	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
886	do { \
887	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
888	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
889	(a_pPage)->au64[0] = SetHCPhysTmp; \
890	(a_pPage)->au64[1] = 0; \
891	(a_pPage)->s.idPage = (a_idPage); \
892	(a_pPage)->s.uStateY = (a_uState); \
893	(a_pPage)->s.uTypeY = (a_uType); \
894	} while (0)
895
896	/**
897	* Initializes the page structure of a ZERO page.
898	* @param a_pPage Pointer to the physical guest page tracking structure.
899	* @param a_pVM The VM handle (for getting the zero page address).
900	* @param a_uType The page type (PGMPAGETYPE).
901	*/
902	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
903	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
904
905
906	/** @name The Page state, PGMPAGE::uStateY.
907	* @{ */
908	/** The zero page.
909	* This is a per-VM page that's never ever mapped writable. */
910	#define PGM_PAGE_STATE_ZERO 0
911	/** A allocated page.
912	* This is a per-VM page allocated from the page pool (or wherever
913	* we get MMIO2 pages from if the type is MMIO2).
914	*/
915	#define PGM_PAGE_STATE_ALLOCATED 1
916	/** A allocated page that's being monitored for writes.
917	* The shadow page table mappings are read-only. When a write occurs, the
918	* fWrittenTo member is set, the page remapped as read-write and the state
919	* moved back to allocated. */
920	#define PGM_PAGE_STATE_WRITE_MONITORED 2
921	/** The page is shared, aka. copy-on-write.
922	* This is a page that's shared with other VMs. */
923	#define PGM_PAGE_STATE_SHARED 3
924	/** The page is ballooned, so no longer available for this VM. */
925	#define PGM_PAGE_STATE_BALLOONED 4
926	/** @} */
927
928
929	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
930	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
931	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
932	#else
933	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
934	#endif
935
936	/**
937	* Gets the page state.
938	* @returns page state (PGM_PAGE_STATE_*).
939	* @param a_pPage Pointer to the physical guest page tracking structure.
940	*
941	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
942	* builds.
943	*/
944	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
945	#if defined(__GNUC__) && defined(VBOX_STRICT)
946	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
947	#else
948	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
949	#endif
950
951	/**
952	* Sets the page state.
953	* @param a_pVM The VM handle, only used for lock ownership assertions.
954	* @param a_pPage Pointer to the physical guest page tracking structure.
955	* @param a_uState The new page state.
956	*/
957	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
958	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
959
960
961	/**
962	* Gets the host physical address of the guest page.
963	* @returns host physical address (RTHCPHYS).
964	* @param a_pPage Pointer to the physical guest page tracking structure.
965	*
966	* @remarks In strict builds on gcc platforms, this macro will make some ugly
967	* assumption about a valid pVM variable/parameter being in the
968	* current context. It will use this pVM variable to assert that the
969	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
970	* pVM is not around.
971	*/
972	#if 0
973	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
974	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
975	#else
976	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
977	# if defined(__GNUC__) && defined(VBOX_STRICT)
978	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
979	# else
980	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
981	# endif
982	#endif
983
984	/**
985	* Sets the host physical address of the guest page.
986	*
987	* @param a_pVM The VM handle, only used for lock ownership assertions.
988	* @param a_pPage Pointer to the physical guest page tracking structure.
989	* @param a_HCPhys The new host physical address.
990	*/
991	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
992	do { \
993	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
994	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
995	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
996	PGM_PAGE_ASSERT_LOCK(a_pVM); \
997	} while (0)
998
999	/**
1000	* Get the Page ID.
1001	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
1002	* @param a_pPage Pointer to the physical guest page tracking structure.
1003	*/
1004	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
1005
1006	/**
1007	* Sets the Page ID.
1008	* @param a_pVM The VM handle, only used for lock ownership assertions.
1009	* @param a_pPage Pointer to the physical guest page tracking structure.
1010	* @param a_idPage The new page ID.
1011	*/
1012	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
1013	do { \
1014	(a_pPage)->s.idPage = (a_idPage); \
1015	PGM_PAGE_ASSERT_LOCK(a_pVM); \
1016	} while (0)
1017
1018	/**
1019	* Get the Chunk ID.
1020	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
1021	* @param a_pPage Pointer to the physical guest page tracking structure.
1022	*/
1023	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
1024
1025	/**
1026	* Get the index of the page within the allocation chunk.
1027	* @returns The page index.
1028	* @param a_pPage Pointer to the physical guest page tracking structure.
1029	*/
1030	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
1031
1032	/**
1033	* Gets the page type.
1034	* @returns The page type.
1035	* @param a_pPage Pointer to the physical guest page tracking structure.
1036	*
1037	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
1038	* builds.
1039	*/
1040	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
1041	#if defined(__GNUC__) && defined(VBOX_STRICT)
1042	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
1043	#else
1044	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
1045	#endif
1046
1047	/**
1048	* Sets the page type.
1049	*
1050	* @param a_pVM The VM handle, only used for lock ownership assertions.
1051	* @param a_pPage Pointer to the physical guest page tracking structure.
1052	* @param a_enmType The new page type (PGMPAGETYPE).
1053	*/
1054	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
1055	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1056
1057	/**
1058	* Gets the page table index
1059	* @returns The page table index.
1060	* @param a_pPage Pointer to the physical guest page tracking structure.
1061	*/
1062	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
1063
1064	/**
1065	* Sets the page table index.
1066	* @param a_pVM The VM handle, only used for lock ownership assertions.
1067	* @param a_pPage Pointer to the physical guest page tracking structure.
1068	* @param a_iPte New page table index.
1069	*/
1070	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
1071	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1072
1073	/**
1074	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
1075	* @returns true/false.
1076	* @param a_pPage Pointer to the physical guest page tracking structure.
1077	*/
1078	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
1079
1080	/**
1081	* Checks if the page is marked for MMIO, including both aliases.
1082	* @returns true/false.
1083	* @param a_pPage Pointer to the physical guest page tracking structure.
1084	*/
1085	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1086	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
1087	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
1088	)
1089
1090	/**
1091	* Checks if the page is marked for MMIO, including special aliases.
1092	* @returns true/false.
1093	* @param a_pPage Pointer to the physical guest page tracking structure.
1094	*/
1095	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1096	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1097
1098	/**
1099	* Checks if the page is a special aliased MMIO page.
1100	* @returns true/false.
1101	* @param a_pPage Pointer to the physical guest page tracking structure.
1102	*/
1103	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1104
1105	/**
1106	* Checks if the page is backed by the ZERO page.
1107	* @returns true/false.
1108	* @param a_pPage Pointer to the physical guest page tracking structure.
1109	*/
1110	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
1111
1112	/**
1113	* Checks if the page is backed by a SHARED page.
1114	* @returns true/false.
1115	* @param a_pPage Pointer to the physical guest page tracking structure.
1116	*/
1117	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
1118
1119	/**
1120	* Checks if the page is ballooned.
1121	* @returns true/false.
1122	* @param a_pPage Pointer to the physical guest page tracking structure.
1123	*/
1124	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
1125
1126	/**
1127	* Checks if the page is allocated.
1128	* @returns true/false.
1129	* @param a_pPage Pointer to the physical guest page tracking structure.
1130	*/
1131	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1132
1133	/**
1134	* Marks the page as written to (for GMM change monitoring).
1135	* @param a_pVM The VM handle, only used for lock ownership assertions.
1136	* @param a_pPage Pointer to the physical guest page tracking structure.
1137	*/
1138	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1139	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1140
1141	/**
1142	* Clears the written-to indicator.
1143	* @param a_pVM The VM handle, only used for lock ownership assertions.
1144	* @param a_pPage Pointer to the physical guest page tracking structure.
1145	*/
1146	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1147	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1148
1149	/**
1150	* Checks if the page was marked as written-to.
1151	* @returns true/false.
1152	* @param a_pPage Pointer to the physical guest page tracking structure.
1153	*/
1154	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1155
1156	/**
1157	* Marks the page as dirty for FTM
1158	* @param a_pPage Pointer to the physical guest page tracking structure.
1159	*/
1160	#define PGM_PAGE_SET_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 1; } while (0)
1161
1162	/**
1163	* Clears the FTM dirty indicator
1164	* @param a_pPage Pointer to the physical guest page tracking structure.
1165	*/
1166	#define PGM_PAGE_CLEAR_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 0; } while (0)
1167
1168	/**
1169	* Checks if the page was marked as dirty for FTM
1170	* @returns true/false.
1171	* @param a_pPage Pointer to the physical guest page tracking structure.
1172	*/
1173	#define PGM_PAGE_IS_FT_DIRTY(a_pPage) ( (a_pPage)->s.fFTDirtyY )
1174
1175
1176	/** @name PT usage values (PGMPAGE::u2PDEType).
1177	*
1178	* @{ */
1179	/** Either as a PT or PDE. */
1180	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1181	/** Must use a page table to map the range. */
1182	#define PGM_PAGE_PDE_TYPE_PT 1
1183	/** Can use a page directory entry to map the continuous range. */
1184	#define PGM_PAGE_PDE_TYPE_PDE 2
1185	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1186	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1187	/** @} */
1188
1189	/**
1190	* Set the PDE type of the page
1191	* @param a_pVM The VM handle, only used for lock ownership assertions.
1192	* @param a_pPage Pointer to the physical guest page tracking structure.
1193	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1194	*/
1195	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1196	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1197
1198	/**
1199	* Checks if the page was marked being part of a large page
1200	* @returns true/false.
1201	* @param a_pPage Pointer to the physical guest page tracking structure.
1202	*/
1203	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1204
1205	/** Enabled optimized access handler tests.
1206	* These optimizations makes ASSUMPTIONS about the state values and the s1
1207	* layout. When enabled, the compiler should normally generate more compact
1208	* code.
1209	*/
1210	#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1211
1212	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1213	*
1214	* @remarks The values are assigned in order of priority, so we can calculate
1215	* the correct state for a page with different handlers installed.
1216	* @{ */
1217	/** No handler installed. */
1218	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1219	/** Monitoring is temporarily disabled. */
1220	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1221	/** Write access is monitored. */
1222	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1223	/** All access is monitored. */
1224	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1225	/** @} */
1226
1227	/**
1228	* Gets the physical access handler state of a page.
1229	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1230	* @param a_pPage Pointer to the physical guest page tracking structure.
1231	*/
1232	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1233
1234	/**
1235	* Sets the physical access handler state of a page.
1236	* @param a_pPage Pointer to the physical guest page tracking structure.
1237	* @param a_uState The new state value.
1238	*/
1239	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1240	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1241
1242	/**
1243	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1244	* @returns true/false
1245	* @param a_pPage Pointer to the physical guest page tracking structure.
1246	*/
1247	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1248	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1249
1250	/**
1251	* Checks if the page has any active physical access handlers.
1252	* @returns true/false
1253	* @param a_pPage Pointer to the physical guest page tracking structure.
1254	*/
1255	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1256	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1257
1258
1259	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1260	*
1261	* @remarks The values are assigned in order of priority, so we can calculate
1262	* the correct state for a page with different handlers installed.
1263	* @{ */
1264	/** No handler installed. */
1265	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1266	/* 1 is reserved so the lineup is identical with the physical ones. */
1267	/** Write access is monitored. */
1268	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1269	/** All access is monitored. */
1270	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1271	/** @} */
1272
1273	/**
1274	* Gets the virtual access handler state of a page.
1275	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1276	* @param a_pPage Pointer to the physical guest page tracking structure.
1277	*/
1278	#define PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) ( (a_pPage)->s.u2HandlerVirtStateY )
1279
1280	/**
1281	* Sets the virtual access handler state of a page.
1282	* @param a_pPage Pointer to the physical guest page tracking structure.
1283	* @param a_uState The new state value.
1284	*/
1285	#define PGM_PAGE_SET_HNDL_VIRT_STATE(a_pPage, a_uState) \
1286	do { (a_pPage)->s.u2HandlerVirtStateY = (a_uState); } while (0)
1287
1288	/**
1289	* Checks if the page has any virtual access handlers.
1290	* @returns true/false
1291	* @param a_pPage Pointer to the physical guest page tracking structure.
1292	*/
1293	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage) \
1294	( PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1295
1296	/**
1297	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1298	* virtual handlers.
1299	* @returns true/false
1300	* @param a_pPage Pointer to the physical guest page tracking structure.
1301	*/
1302	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
1303	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage)
1304
1305
1306	/**
1307	* Checks if the page has any access handlers, including temporarily disabled ones.
1308	* @returns true/false
1309	* @param a_pPage Pointer to the physical guest page tracking structure.
1310	*/
1311	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1312	# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1313	( ((a_pPage)->au32[0] & UINT16_C(0x0303)) != 0 )
1314	#else
1315	# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1316	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1317	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1318	#endif
1319
1320	/**
1321	* Checks if the page has any active access handlers.
1322	* @returns true/false
1323	* @param a_pPage Pointer to the physical guest page tracking structure.
1324	*/
1325	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1326	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1327	( ((a_pPage)->au32[0] & UINT16_C(0x0202)) != 0 )
1328	#else
1329	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1330	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1331	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1332	#endif
1333
1334	/**
1335	* Checks if the page has any active access handlers catching all accesses.
1336	* @returns true/false
1337	* @param a_pPage Pointer to the physical guest page tracking structure.
1338	*/
1339	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1340	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1341	( ( ((a_pPage)->au8[0] \| (a_pPage)->au8[1]) & UINT8_C(0x3) ) \
1342	== PGM_PAGE_HNDL_PHYS_STATE_ALL )
1343	#else
1344	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1345	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1346	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1347	#endif
1348
1349
1350	/** @def PGM_PAGE_GET_TRACKING
1351	* Gets the packed shadow page pool tracking data associated with a guest page.
1352	* @returns uint16_t containing the data.
1353	* @param a_pPage Pointer to the physical guest page tracking structure.
1354	*/
1355	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1356	#if defined(__GNUC__) && defined(VBOX_STRICT)
1357	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1358	#else
1359	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1360	#endif
1361
1362	/** @def PGM_PAGE_SET_TRACKING
1363	* Sets the packed shadow page pool tracking data associated with a guest page.
1364	* @param a_pVM The VM handle, only used for lock ownership assertions.
1365	* @param a_pPage Pointer to the physical guest page tracking structure.
1366	* @param a_u16TrackingData The tracking data to store.
1367	*/
1368	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1369	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1370
1371	/** @def PGM_PAGE_GET_TD_CREFS
1372	* Gets the @a cRefs tracking data member.
1373	* @returns cRefs.
1374	* @param a_pPage Pointer to the physical guest page tracking structure.
1375	*/
1376	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1377	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1378	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1379	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1380
1381	/** @def PGM_PAGE_GET_TD_IDX
1382	* Gets the @a idx tracking data member.
1383	* @returns idx.
1384	* @param a_pPage Pointer to the physical guest page tracking structure.
1385	*/
1386	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1387	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1388	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1389	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1390
1391
1392	/** Max number of locks on a page. */
1393	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1394
1395	/** Get the read lock count.
1396	* @returns count.
1397	* @param a_pPage Pointer to the physical guest page tracking structure.
1398	*/
1399	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1400
1401	/** Get the write lock count.
1402	* @returns count.
1403	* @param a_pPage Pointer to the physical guest page tracking structure.
1404	*/
1405	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1406
1407	/** Decrement the read lock counter.
1408	* @param a_pPage Pointer to the physical guest page tracking structure.
1409	*/
1410	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1411
1412	/** Decrement the write lock counter.
1413	* @param a_pPage Pointer to the physical guest page tracking structure.
1414	*/
1415	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1416
1417	/** Increment the read lock counter.
1418	* @param a_pPage Pointer to the physical guest page tracking structure.
1419	*/
1420	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1421
1422	/** Increment the write lock counter.
1423	* @param a_pPage Pointer to the physical guest page tracking structure.
1424	*/
1425	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1426
1427
1428	#if 0
1429	/** Enables sanity checking of write monitoring using CRC-32. */
1430	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1431	#endif
1432
1433	/**
1434	* Per page live save tracking data.
1435	*/
1436	typedef struct PGMLIVESAVERAMPAGE
1437	{
1438	/** Number of times it has been dirtied. */
1439	uint32_t cDirtied : 24;
1440	/** Whether it is currently dirty. */
1441	uint32_t fDirty : 1;
1442	/** Ignore the page.
1443	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1444	* deal with these after pausing the VM and DevPCI have said it bit about
1445	* remappings. */
1446	uint32_t fIgnore : 1;
1447	/** Was a ZERO page last time around. */
1448	uint32_t fZero : 1;
1449	/** Was a SHARED page last time around. */
1450	uint32_t fShared : 1;
1451	/** Whether the page is/was write monitored in a previous pass. */
1452	uint32_t fWriteMonitored : 1;
1453	/** Whether the page is/was write monitored earlier in this pass. */
1454	uint32_t fWriteMonitoredJustNow : 1;
1455	/** Bits reserved for future use. */
1456	uint32_t u2Reserved : 2;
1457	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1458	/** CRC-32 for the page. This is for internal consistency checks. */
1459	uint32_t u32Crc;
1460	#endif
1461	} PGMLIVESAVERAMPAGE;
1462	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1463	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1464	#else
1465	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1466	#endif
1467	/** Pointer to the per page live save tracking data. */
1468	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1469
1470	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1471	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1472
1473
1474	/**
1475	* RAM range for GC Phys to HC Phys conversion.
1476	*
1477	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1478	* conversions too, but we'll let MM handle that for now.
1479	*
1480	* This structure is used by linked lists in both GC and HC.
1481	*/
1482	typedef struct PGMRAMRANGE
1483	{
1484	/** Start of the range. Page aligned. */
1485	RTGCPHYS GCPhys;
1486	/** Size of the range. (Page aligned of course). */
1487	RTGCPHYS cb;
1488	/** Pointer to the next RAM range - for R3. */
1489	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1490	/** Pointer to the next RAM range - for R0. */
1491	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1492	/** Pointer to the next RAM range - for RC. */
1493	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1494	/** PGM_RAM_RANGE_FLAGS_* flags. */
1495	uint32_t fFlags;
1496	/** Last address in the range (inclusive). Page aligned (-1). */
1497	RTGCPHYS GCPhysLast;
1498	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1499	R3PTRTYPE(void *) pvR3;
1500	/** Live save per page tracking data. */
1501	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1502	/** The range description. */
1503	R3PTRTYPE(const char *) pszDesc;
1504	/** Pointer to self - R0 pointer. */
1505	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1506	/** Pointer to self - RC pointer. */
1507	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1508
1509	/** Alignment padding. */
1510	RTRCPTR Alignment0;
1511	/** Pointer to the left search three node - ring-3 context. */
1512	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1513	/** Pointer to the right search three node - ring-3 context. */
1514	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1515	/** Pointer to the left search three node - ring-0 context. */
1516	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1517	/** Pointer to the right search three node - ring-0 context. */
1518	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1519	/** Pointer to the left search three node - raw-mode context. */
1520	RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1521	/** Pointer to the right search three node - raw-mode context. */
1522	RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1523
1524	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1525	#if HC_ARCH_BITS == 32
1526	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1527	#endif
1528	/** Array of physical guest page tracking structures. */
1529	PGMPAGE aPages[1];
1530	} PGMRAMRANGE;
1531	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1532	typedef PGMRAMRANGE *PPGMRAMRANGE;
1533
1534	/** @name PGMRAMRANGE::fFlags
1535	* @{ */
1536	/** The RAM range is floating around as an independent guest mapping. */
1537	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1538	/** Ad hoc RAM range for an ROM mapping. */
1539	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1540	/** Ad hoc RAM range for an MMIO mapping. */
1541	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1542	/** Ad hoc RAM range for an MMIO2 mapping. */
1543	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1544	/** @} */
1545
1546	/** Tests if a RAM range is an ad hoc one or not.
1547	* @returns true/false.
1548	* @param pRam The RAM range.
1549	*/
1550	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1551	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1552
1553	/** The number of entries in the RAM range TLBs (there is one for each
1554	* context). Must be a power of two. */
1555	#define PGM_RAMRANGE_TLB_ENTRIES 8
1556
1557	/**
1558	* Calculates the RAM range TLB index for the physical address.
1559	*
1560	* @returns RAM range TLB index.
1561	* @param a_GCPhys The guest physical address.
1562	*/
1563	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1564
1565
1566
1567	/**
1568	* Per page tracking structure for ROM image.
1569	*
1570	* A ROM image may have a shadow page, in which case we may have two pages
1571	* backing it. This structure contains the PGMPAGE for both while
1572	* PGMRAMRANGE have a copy of the active one. It is important that these
1573	* aren't out of sync in any regard other than page pool tracking data.
1574	*/
1575	typedef struct PGMROMPAGE
1576	{
1577	/** The page structure for the virgin ROM page. */
1578	PGMPAGE Virgin;
1579	/** The page structure for the shadow RAM page. */
1580	PGMPAGE Shadow;
1581	/** The current protection setting. */
1582	PGMROMPROT enmProt;
1583	/** Live save status information. Makes use of unused alignment space. */
1584	struct
1585	{
1586	/** The previous protection value. */
1587	uint8_t u8Prot;
1588	/** Written to flag set by the handler. */
1589	bool fWrittenTo;
1590	/** Whether the shadow page is dirty or not. */
1591	bool fDirty;
1592	/** Whether it was dirtied in the recently. */
1593	bool fDirtiedRecently;
1594	} LiveSave;
1595	} PGMROMPAGE;
1596	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1597	/** Pointer to a ROM page tracking structure. */
1598	typedef PGMROMPAGE *PPGMROMPAGE;
1599
1600
1601	/**
1602	* A registered ROM image.
1603	*
1604	* This is needed to keep track of ROM image since they generally intrude
1605	* into a PGMRAMRANGE. It also keeps track of additional info like the
1606	* two page sets (read-only virgin and read-write shadow), the current
1607	* state of each page.
1608	*
1609	* Because access handlers cannot easily be executed in a different
1610	* context, the ROM ranges needs to be accessible and in all contexts.
1611	*/
1612	typedef struct PGMROMRANGE
1613	{
1614	/** Pointer to the next range - R3. */
1615	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1616	/** Pointer to the next range - R0. */
1617	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1618	/** Pointer to the next range - RC. */
1619	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1620	/** Pointer alignment */
1621	RTRCPTR RCPtrAlignment;
1622	/** Address of the range. */
1623	RTGCPHYS GCPhys;
1624	/** Address of the last byte in the range. */
1625	RTGCPHYS GCPhysLast;
1626	/** Size of the range. */
1627	RTGCPHYS cb;
1628	/** The flags (PGMPHYS_ROM_FLAGS_). /
1629	uint32_t fFlags;
1630	/** The saved state range ID. */
1631	uint8_t idSavedState;
1632	/** Alignment padding. */
1633	uint8_t au8Alignment[3];
1634	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1635	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1636	/** The size bits pvOriginal points to. */
1637	uint32_t cbOriginal;
1638	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1639	* This is used for strictness checks. */
1640	R3PTRTYPE(const void *) pvOriginal;
1641	/** The ROM description. */
1642	R3PTRTYPE(const char *) pszDesc;
1643	/** The per page tracking structures. */
1644	PGMROMPAGE aPages[1];
1645	} PGMROMRANGE;
1646	/** Pointer to a ROM range. */
1647	typedef PGMROMRANGE *PPGMROMRANGE;
1648
1649
1650	/**
1651	* Live save per page data for an MMIO2 page.
1652	*
1653	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1654	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1655	* CRC-32 for detecting changes as well as special handling of zero pages. This
1656	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1657	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1658	* because of speed (2.5x and 6x slower).)
1659	*
1660	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1661	* save but normally is disabled. Since we can write monitor guest
1662	* accesses on our own, we only need this for host accesses. Shouldn't be
1663	* too difficult for DevVGA, VMMDev might be doable, the planned
1664	* networking fun will be fun since it involves ring-0.
1665	*/
1666	typedef struct PGMLIVESAVEMMIO2PAGE
1667	{
1668	/** Set if the page is considered dirty. */
1669	bool fDirty;
1670	/** The number of scans this page has remained unchanged for.
1671	* Only updated for dirty pages. */
1672	uint8_t cUnchangedScans;
1673	/** Whether this page was zero at the last scan. */
1674	bool fZero;
1675	/** Alignment padding. */
1676	bool fReserved;
1677	/** CRC-32 for the first half of the page.
1678	* This is used together with u32CrcH2 to quickly detect changes in the page
1679	* during the non-final passes. */
1680	uint32_t u32CrcH1;
1681	/** CRC-32 for the second half of the page. */
1682	uint32_t u32CrcH2;
1683	/** SHA-1 for the saved page.
1684	* This is used in the final pass to skip pages without changes. */
1685	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1686	} PGMLIVESAVEMMIO2PAGE;
1687	/** Pointer to a live save status data for an MMIO2 page. */
1688	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1689
1690	/**
1691	* A registered MMIO2 (= Device RAM) range.
1692	*
1693	* There are a few reason why we need to keep track of these
1694	* registrations. One of them is the deregistration & cleanup stuff,
1695	* while another is that the PGMRAMRANGE associated with such a region may
1696	* have to be removed from the ram range list.
1697	*
1698	* Overlapping with a RAM range has to be 100% or none at all. The pages
1699	* in the existing RAM range must not be ROM nor MMIO. A guru meditation
1700	* will be raised if a partial overlap or an overlap of ROM pages is
1701	* encountered. On an overlap we will free all the existing RAM pages and
1702	* put in the ram range pages instead.
1703	*/
1704	typedef struct PGMMMIO2RANGE
1705	{
1706	/** The owner of the range. (a device) */
1707	PPDMDEVINSR3 pDevInsR3;
1708	/** Pointer to the ring-3 mapping of the allocation. */
1709	RTR3PTR pvR3;
1710	/** Pointer to the next range - R3. */
1711	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1712	/** Whether it's mapped or not. */
1713	bool fMapped;
1714	/** Whether it's overlapping or not. */
1715	bool fOverlapping;
1716	/** The PCI region number.
1717	* @remarks This ASSUMES that nobody will ever really need to have multiple
1718	* PCI devices with matching MMIO region numbers on a single device. */
1719	uint8_t iRegion;
1720	/** The saved state range ID. */
1721	uint8_t idSavedState;
1722	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1723	uint8_t idMmio2;
1724	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1725	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 11 : 11];
1726	/** Live save per page tracking data. */
1727	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1728	/** The associated RAM range. */
1729	PGMRAMRANGE RamRange;
1730	} PGMMMIO2RANGE;
1731	/** Pointer to a MMIO2 range. */
1732	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1733
1734	/** @name Intenal MMIO2 constants.
1735	* @{ */
1736	/** The maximum number of MMIO2 ranges. */
1737	#define PGM_MMIO2_MAX_RANGES 8
1738	/** The maximum number of pages in a MMIO2 range. */
1739	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x00ffffff)
1740	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1741	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1742	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1743	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1744	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1745	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1746	/** @} */
1747
1748
1749
1750	/**
1751	* PGMPhysRead/Write cache entry
1752	*/
1753	typedef struct PGMPHYSCACHEENTRY
1754	{
1755	/** R3 pointer to physical page. */
1756	R3PTRTYPE(uint8_t *) pbR3;
1757	/** GC Physical address for cache entry */
1758	RTGCPHYS GCPhys;
1759	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1760	RTGCPHYS u32Padding0; /*< alignment padding. /
1761	#endif
1762	} PGMPHYSCACHEENTRY;
1763
1764	/**
1765	* PGMPhysRead/Write cache to reduce REM memory access overhead
1766	*/
1767	typedef struct PGMPHYSCACHE
1768	{
1769	/** Bitmap of valid cache entries */
1770	uint64_t aEntries;
1771	/** Cache entries */
1772	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1773	} PGMPHYSCACHE;
1774
1775
1776	/** Pointer to an allocation chunk ring-3 mapping. */
1777	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1778	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1779	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1780
1781	/**
1782	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1783	*
1784	* The primary tree (Core) uses the chunk id as key.
1785	*/
1786	typedef struct PGMCHUNKR3MAP
1787	{
1788	/** The key is the chunk id. */
1789	AVLU32NODECORE Core;
1790	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1791	* selection. */
1792	uint32_t iLastUsed;
1793	/** The current reference count. */
1794	uint32_t volatile cRefs;
1795	/** The current permanent reference count. */
1796	uint32_t volatile cPermRefs;
1797	/** The mapping address. */
1798	void *pv;
1799	} PGMCHUNKR3MAP;
1800
1801	/**
1802	* Allocation chunk ring-3 mapping TLB entry.
1803	*/
1804	typedef struct PGMCHUNKR3MAPTLBE
1805	{
1806	/** The chunk id. */
1807	uint32_t volatile idChunk;
1808	#if HC_ARCH_BITS == 64
1809	uint32_t u32Padding; /*< alignment padding. /
1810	#endif
1811	/** The chunk map. */
1812	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1813	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1814	#else
1815	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1816	#endif
1817	} PGMCHUNKR3MAPTLBE;
1818	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1819	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1820
1821	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1822	* @remark Must be a power of two value. */
1823	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1824
1825	/**
1826	* Allocation chunk ring-3 mapping TLB.
1827	*
1828	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1829	* At first glance this might look kinda odd since AVL trees are
1830	* supposed to give the most optimal lookup times of all trees
1831	* due to their balancing. However, take a tree with 1023 nodes
1832	* in it, that's 10 levels, meaning that most searches has to go
1833	* down 9 levels before they find what they want. This isn't fast
1834	* compared to a TLB hit. There is the factor of cache misses,
1835	* and of course the problem with trees and branch prediction.
1836	* This is why we use TLBs in front of most of the trees.
1837	*
1838	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1839	* difficult when we switch to the new inlined AVL trees (from kStuff).
1840	*/
1841	typedef struct PGMCHUNKR3MAPTLB
1842	{
1843	/** The TLB entries. */
1844	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1845	} PGMCHUNKR3MAPTLB;
1846
1847	/**
1848	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1849	* @returns Chunk TLB index.
1850	* @param idChunk The Chunk ID.
1851	*/
1852	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1853
1854
1855	/**
1856	* Ring-3 guest page mapping TLB entry.
1857	* @remarks used in ring-0 as well at the moment.
1858	*/
1859	typedef struct PGMPAGER3MAPTLBE
1860	{
1861	/** Address of the page. */
1862	RTGCPHYS volatile GCPhys;
1863	/** The guest page. */
1864	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1865	R3PTRTYPE(PPGMPAGE) volatile pPage;
1866	#else
1867	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1868	#endif
1869	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1870	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1871	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1872	#else
1873	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1874	#endif
1875	/** The address */
1876	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1877	R3PTRTYPE(void *) volatile pv;
1878	#else
1879	R3R0PTRTYPE(void *) volatile pv;
1880	#endif
1881	#if HC_ARCH_BITS == 32
1882	uint32_t u32Padding; /*< alignment padding. /
1883	#endif
1884	} PGMPAGER3MAPTLBE;
1885	/** Pointer to an entry in the HC physical TLB. */
1886	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1887
1888
1889	/** The number of entries in the ring-3 guest page mapping TLB.
1890	* @remarks The value must be a power of two. */
1891	#define PGM_PAGER3MAPTLB_ENTRIES 256
1892
1893	/**
1894	* Ring-3 guest page mapping TLB.
1895	* @remarks used in ring-0 as well at the moment.
1896	*/
1897	typedef struct PGMPAGER3MAPTLB
1898	{
1899	/** The TLB entries. */
1900	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1901	} PGMPAGER3MAPTLB;
1902	/** Pointer to the ring-3 guest page mapping TLB. */
1903	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1904
1905	/**
1906	* Calculates the index of the TLB entry for the specified guest page.
1907	* @returns Physical TLB index.
1908	* @param GCPhys The guest physical address.
1909	*/
1910	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1911
1912
1913	/**
1914	* Raw-mode context dynamic mapping cache entry.
1915	*
1916	* Because of raw-mode context being reloctable and all relocations are applied
1917	* in ring-3, this has to be defined here and be RC specific.
1918	*
1919	* @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1920	*/
1921	typedef struct PGMRCDYNMAPENTRY
1922	{
1923	/** The physical address of the currently mapped page.
1924	* This is duplicate for three reasons: cache locality, cache policy of the PT
1925	* mappings and sanity checks. */
1926	RTHCPHYS HCPhys;
1927	/** Pointer to the page. */
1928	RTRCPTR pvPage;
1929	/** The number of references. */
1930	int32_t volatile cRefs;
1931	/** PTE pointer union. */
1932	struct PGMRCDYNMAPENTRY_PPTE
1933	{
1934	/** PTE pointer, 32-bit legacy version. */
1935	RCPTRTYPE(PX86PTE) pLegacy;
1936	/** PTE pointer, PAE version. */
1937	RCPTRTYPE(PX86PTEPAE) pPae;
1938	} uPte;
1939	} PGMRCDYNMAPENTRY;
1940	/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1941	typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1942
1943
1944	/**
1945	* Dynamic mapping cache for the raw-mode context.
1946	*
1947	* This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1948	* paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1949	* so that we can perform relocations from PGMR3Relocate. This has the
1950	* consequence that we must have separate ring-0 and raw-mode context versions
1951	* of this struct even if they share the basic elements.
1952	*
1953	* @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1954	*/
1955	typedef struct PGMRCDYNMAP
1956	{
1957	/** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1958	uint32_t u32Magic;
1959	/** Array for tracking and managing the pages. */
1960	RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1961	/** The cache size given as a number of pages. */
1962	uint32_t cPages;
1963	/** The current load.
1964	* This does not include guard pages. */
1965	uint32_t cLoad;
1966	/** The max load ever.
1967	* This is maintained to get trigger adding of more mapping space. */
1968	uint32_t cMaxLoad;
1969	/** The number of guard pages. */
1970	uint32_t cGuardPages;
1971	/** The number of users (protected by hInitLock). */
1972	uint32_t cUsers;
1973	} PGMRCDYNMAP;
1974	/** Pointer to the dynamic cache for the raw-mode context. */
1975	typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1976
1977
1978	/**
1979	* Mapping cache usage set entry.
1980	*
1981	* @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1982	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1983	* cache. If it's extended to include ring-3, well, then something
1984	* will have be changed here...
1985	*/
1986	typedef struct PGMMAPSETENTRY
1987	{
1988	/** Pointer to the page. */
1989	#ifndef IN_RC
1990	RTR0PTR pvPage;
1991	#else
1992	RTRCPTR pvPage;
1993	# if HC_ARCH_BITS == 64
1994	uint32_t u32Alignment2;
1995	# endif
1996	#endif
1997	/** The mapping cache index. */
1998	uint16_t iPage;
1999	/** The number of references.
2000	* The max is UINT16_MAX - 1. */
2001	uint16_t cRefs;
2002	/** The number inlined references.
2003	* The max is UINT16_MAX - 1. */
2004	uint16_t cInlinedRefs;
2005	/** Unreferences. */
2006	uint16_t cUnrefs;
2007
2008	#if HC_ARCH_BITS == 32
2009	uint32_t u32Alignment1;
2010	#endif
2011	/** The physical address for this entry. */
2012	RTHCPHYS HCPhys;
2013	} PGMMAPSETENTRY;
2014	AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
2015	AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
2016	/** Pointer to a mapping cache usage set entry. */
2017	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
2018
2019	/**
2020	* Mapping cache usage set.
2021	*
2022	* This is used in ring-0 and the raw-mode context to track dynamic mappings
2023	* done during exits / traps. The set is
2024	*/
2025	typedef struct PGMMAPSET
2026	{
2027	/** The number of occupied entries.
2028	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
2029	* dynamic mappings. */
2030	uint32_t cEntries;
2031	/** The start of the current subset.
2032	* This is UINT32_MAX if no subset is currently open. */
2033	uint32_t iSubset;
2034	/** The index of the current CPU, only valid if the set is open. */
2035	int32_t iCpu;
2036	uint32_t alignment;
2037	/** The entries. */
2038	PGMMAPSETENTRY aEntries[64];
2039	/** HCPhys -> iEntry fast lookup table.
2040	* Use PGMMAPSET_HASH for hashing.
2041	* The entries may or may not be valid, check against cEntries. */
2042	uint8_t aiHashTable[128];
2043	} PGMMAPSET;
2044	AssertCompileSizeAlignment(PGMMAPSET, 8);
2045	/** Pointer to the mapping cache set. */
2046	typedef PGMMAPSET *PPGMMAPSET;
2047
2048	/** PGMMAPSET::cEntries value for a closed set. */
2049	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
2050
2051	/** Hash function for aiHashTable. */
2052	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
2053
2054
2055	/** @name Context neutral page mapper TLB.
2056	*
2057	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
2058	* code is writting in a kind of context neutral way. Time will show whether
2059	* this actually makes sense or not...
2060	*
2061	* @todo this needs to be reconsidered and dropped/redone since the ring-0
2062	* context ends up using a global mapping cache on some platforms
2063	* (darwin).
2064	*
2065	* @{ */
2066	/** @typedef PPGMPAGEMAPTLB
2067	* The page mapper TLB pointer type for the current context. */
2068	/** @typedef PPGMPAGEMAPTLB
2069	* The page mapper TLB entry pointer type for the current context. */
2070	/** @typedef PPGMPAGEMAPTLB
2071	* The page mapper TLB entry pointer pointer type for the current context. */
2072	/** @def PGM_PAGEMAPTLB_ENTRIES
2073	* The number of TLB entries in the page mapper TLB for the current context. */
2074	/** @def PGM_PAGEMAPTLB_IDX
2075	* Calculate the TLB index for a guest physical address.
2076	* @returns The TLB index.
2077	* @param GCPhys The guest physical address. */
2078	/** @typedef PPGMPAGEMAP
2079	* Pointer to a page mapper unit for current context. */
2080	/** @typedef PPPGMPAGEMAP
2081	* Pointer to a page mapper unit pointer for current context. */
2082	#if defined(IN_RC) && !defined(DOXYGEN_RUNNING)
2083	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
2084	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
2085	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
2086	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
2087	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
2088	typedef void * PPGMPAGEMAP;
2089	typedef void ** PPPGMPAGEMAP;
2090	//#elif IN_RING0
2091	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
2092	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
2093	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
2094	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
2095	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
2096	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
2097	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
2098	#else
2099	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
2100	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
2101	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
2102	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
2103	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
2104	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
2105	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
2106	#endif
2107	/** @} */
2108
2109
2110	/** @name PGM Pool Indexes.
2111	* Aka. the unique shadow page identifier.
2112	* @{ */
2113	/** NIL page pool IDX. */
2114	#define NIL_PGMPOOL_IDX 0
2115	/** The first normal index. There used to be 5 fictive pages up front, now
2116	* there is only the NIL page. */
2117	#define PGMPOOL_IDX_FIRST 1
2118	/** The last valid index. (inclusive, 14 bits) */
2119	#define PGMPOOL_IDX_LAST 0x3fff
2120	/** @} */
2121
2122	/** The NIL index for the parent chain. */
2123	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
2124	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
2125
2126	/**
2127	* Node in the chain linking a shadowed page to it's parent (user).
2128	*/
2129	#pragma pack(1)
2130	typedef struct PGMPOOLUSER
2131	{
2132	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
2133	uint16_t iNext;
2134	/** The user page index. */
2135	uint16_t iUser;
2136	/** Index into the user table. */
2137	uint32_t iUserTable;
2138	} PGMPOOLUSER, *PPGMPOOLUSER;
2139	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
2140	#pragma pack()
2141
2142
2143	/** The NIL index for the phys ext chain. */
2144	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
2145	/** The NIL pte index for a phys ext chain slot. */
2146	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
2147
2148	/**
2149	* Node in the chain of physical cross reference extents.
2150	* @todo Calling this an 'extent' is not quite right, find a better name.
2151	* @todo find out the optimal size of the aidx array
2152	*/
2153	#pragma pack(1)
2154	typedef struct PGMPOOLPHYSEXT
2155	{
2156	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
2157	uint16_t iNext;
2158	/** Alignment. */
2159	uint16_t u16Align;
2160	/** The user page index. */
2161	uint16_t aidx[3];
2162	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
2163	uint16_t apte[3];
2164	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
2165	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
2166	#pragma pack()
2167
2168
2169	/**
2170	* The kind of page that's being shadowed.
2171	*/
2172	typedef enum PGMPOOLKIND
2173	{
2174	/** The virtual invalid 0 entry. */
2175	PGMPOOLKIND_INVALID = 0,
2176	/** The entry is free (=unused). */
2177	PGMPOOLKIND_FREE,
2178
2179	/** Shw: 32-bit page table; Gst: no paging. */
2180	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
2181	/** Shw: 32-bit page table; Gst: 32-bit page table. */
2182	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
2183	/** Shw: 32-bit page table; Gst: 4MB page. */
2184	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2185	/** Shw: PAE page table; Gst: no paging. */
2186	PGMPOOLKIND_PAE_PT_FOR_PHYS,
2187	/** Shw: PAE page table; Gst: 32-bit page table. */
2188	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2189	/** Shw: PAE page table; Gst: Half of a 4MB page. */
2190	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2191	/** Shw: PAE page table; Gst: PAE page table. */
2192	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2193	/** Shw: PAE page table; Gst: 2MB page. */
2194	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2195
2196	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2197	PGMPOOLKIND_32BIT_PD,
2198	/** Shw: 32-bit page directory. Gst: no paging. */
2199	PGMPOOLKIND_32BIT_PD_PHYS,
2200	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2201	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2202	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2203	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2204	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2205	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2206	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2207	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2208	/** Shw: PAE page directory; Gst: PAE page directory. */
2209	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2210	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2211	PGMPOOLKIND_PAE_PD_PHYS,
2212
2213	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2214	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2215	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2216	PGMPOOLKIND_PAE_PDPT,
2217	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2218	PGMPOOLKIND_PAE_PDPT_PHYS,
2219
2220	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2221	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2222	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
2223	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2224	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2225	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2226	/** Shw: 64-bit page directory table; Gst: no paging. */
2227	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2228
2229	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2230	PGMPOOLKIND_64BIT_PML4,
2231
2232	/** Shw: EPT page directory pointer table; Gst: no paging. */
2233	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2234	/** Shw: EPT page directory table; Gst: no paging. */
2235	PGMPOOLKIND_EPT_PD_FOR_PHYS,
2236	/** Shw: EPT page table; Gst: no paging. */
2237	PGMPOOLKIND_EPT_PT_FOR_PHYS,
2238
2239	/** Shw: Root Nested paging table. */
2240	PGMPOOLKIND_ROOT_NESTED,
2241
2242	/** The last valid entry. */
2243	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2244	} PGMPOOLKIND;
2245
2246	/**
2247	* The access attributes of the page; only applies to big pages.
2248	*/
2249	typedef enum
2250	{
2251	PGMPOOLACCESS_DONTCARE = 0,
2252	PGMPOOLACCESS_USER_RW,
2253	PGMPOOLACCESS_USER_R,
2254	PGMPOOLACCESS_USER_RW_NX,
2255	PGMPOOLACCESS_USER_R_NX,
2256	PGMPOOLACCESS_SUPERVISOR_RW,
2257	PGMPOOLACCESS_SUPERVISOR_R,
2258	PGMPOOLACCESS_SUPERVISOR_RW_NX,
2259	PGMPOOLACCESS_SUPERVISOR_R_NX
2260	} PGMPOOLACCESS;
2261
2262	/**
2263	* The tracking data for a page in the pool.
2264	*/
2265	typedef struct PGMPOOLPAGE
2266	{
2267	/** AVL node code with the (HC) physical address of this page. */
2268	AVLOHCPHYSNODECORE Core;
2269	/** Pointer to the R3 mapping of the page. */
2270	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2271	R3PTRTYPE(void *) pvPageR3;
2272	#else
2273	R3R0PTRTYPE(void *) pvPageR3;
2274	#endif
2275	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2276	uint32_t Alignment0;
2277	#endif
2278	/** The guest physical address. */
2279	RTGCPHYS GCPhys;
2280	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2281	uint8_t enmKind;
2282	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2283	uint8_t enmAccess;
2284	/** This supplements enmKind and enmAccess */
2285	bool fA20Enabled : 1;
2286
2287	/** Used to indicate that the page is zeroed. */
2288	bool fZeroed : 1;
2289	/** Used to indicate that a PT has non-global entries. */
2290	bool fSeenNonGlobal : 1;
2291	/** Used to indicate that we're monitoring writes to the guest page. */
2292	bool fMonitored : 1;
2293	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2294	* (All pages are in the age list.) */
2295	bool fCached : 1;
2296	/** This is used by the R3 access handlers when invoked by an async thread.
2297	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2298	bool volatile fReusedFlushPending : 1;
2299	/** Used to mark the page as dirty (write monitoring is temporarily
2300	* off). */
2301	bool fDirty : 1;
2302	bool fPadding1 : 1;
2303	bool fPadding2;
2304
2305	/** The index of this page. */
2306	uint16_t idx;
2307	/** The next entry in the list this page currently resides in.
2308	* It's either in the free list or in the GCPhys hash. */
2309	uint16_t iNext;
2310	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2311	uint16_t iUserHead;
2312	/** The number of present entries. */
2313	uint16_t cPresent;
2314	/** The first entry in the table which is present. */
2315	uint16_t iFirstPresent;
2316	/** The number of modifications to the monitored page. */
2317	uint16_t cModifications;
2318	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2319	uint16_t iModifiedNext;
2320	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2321	uint16_t iModifiedPrev;
2322	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2323	uint16_t iMonitoredNext;
2324	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2325	uint16_t iMonitoredPrev;
2326	/** The next page in the age list. */
2327	uint16_t iAgeNext;
2328	/** The previous page in the age list. */
2329	uint16_t iAgePrev;
2330	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2331	uint8_t idxDirtyEntry;
2332
2333	/** @name Access handler statistics to determine whether the guest is
2334	* (re)initializing a page table.
2335	* @{ */
2336	RTGCPTR GCPtrLastAccessHandlerRip;
2337	RTGCPTR GCPtrLastAccessHandlerFault;
2338	uint64_t cLastAccessHandler;
2339	/** @} */
2340	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2341	uint32_t volatile cLocked;
2342	#if GC_ARCH_BITS == 64
2343	uint32_t u32Alignment3;
2344	#endif
2345	# ifdef VBOX_STRICT
2346	RTGCPTR GCPtrDirtyFault;
2347	# endif
2348	} PGMPOOLPAGE;
2349	/** Pointer to a pool page. */
2350	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2351	/** Pointer to a const pool page. */
2352	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2353	/** Pointer to a pool page pointer. */
2354	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2355
2356
2357	/** The hash table size. */
2358	# define PGMPOOL_HASH_SIZE 0x40
2359	/** The hash function. */
2360	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2361
2362
2363	/**
2364	* The shadow page pool instance data.
2365	*
2366	* It's all one big allocation made at init time, except for the
2367	* pages that is. The user nodes follows immediately after the
2368	* page structures.
2369	*/
2370	typedef struct PGMPOOL
2371	{
2372	/** The VM handle - R3 Ptr. */
2373	PVMR3 pVMR3;
2374	/** The VM handle - R0 Ptr. */
2375	PVMR0 pVMR0;
2376	/** The VM handle - RC Ptr. */
2377	PVMRC pVMRC;
2378	/** The max pool size. This includes the special IDs. */
2379	uint16_t cMaxPages;
2380	/** The current pool size. */
2381	uint16_t cCurPages;
2382	/** The head of the free page list. */
2383	uint16_t iFreeHead;
2384	/* Padding. */
2385	uint16_t u16Padding;
2386	/** Head of the chain of free user nodes. */
2387	uint16_t iUserFreeHead;
2388	/** The number of user nodes we've allocated. */
2389	uint16_t cMaxUsers;
2390	/** The number of present page table entries in the entire pool. */
2391	uint32_t cPresent;
2392	/** Pointer to the array of user nodes - RC pointer. */
2393	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2394	/** Pointer to the array of user nodes - R3 pointer. */
2395	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2396	/** Pointer to the array of user nodes - R0 pointer. */
2397	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2398	/** Head of the chain of free phys ext nodes. */
2399	uint16_t iPhysExtFreeHead;
2400	/** The number of user nodes we've allocated. */
2401	uint16_t cMaxPhysExts;
2402	/** Pointer to the array of physical xref extent - RC pointer. */
2403	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2404	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2405	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2406	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2407	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2408	/** Hash table for GCPhys addresses. */
2409	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2410	/** The head of the age list. */
2411	uint16_t iAgeHead;
2412	/** The tail of the age list. */
2413	uint16_t iAgeTail;
2414	/** Set if the cache is enabled. */
2415	bool fCacheEnabled;
2416	/** Alignment padding. */
2417	bool afPadding1[3];
2418	/** Head of the list of modified pages. */
2419	uint16_t iModifiedHead;
2420	/** The current number of modified pages. */
2421	uint16_t cModifiedPages;
2422	/** Physical access handler type registration handle. */
2423	PGMPHYSHANDLERTYPE hAccessHandlerType;
2424	/** Next available slot (in aDirtyPages). */
2425	uint32_t idxFreeDirtyPage;
2426	/** Number of active dirty pages. */
2427	uint32_t cDirtyPages;
2428	/** Array of current dirty pgm pool page indices. */
2429	struct
2430	{
2431	uint16_t uIdx;
2432	uint16_t Alignment[3];
2433	uint64_t aPage[512];
2434	} aDirtyPages[16];
2435	/** The number of pages currently in use. */
2436	uint16_t cUsedPages;
2437	#ifdef VBOX_WITH_STATISTICS
2438	/** The high water mark for cUsedPages. */
2439	uint16_t cUsedPagesHigh;
2440	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2441	/** Profiling pgmPoolAlloc(). */
2442	STAMPROFILEADV StatAlloc;
2443	/** Profiling pgmR3PoolClearDoIt(). */
2444	STAMPROFILE StatClearAll;
2445	/** Profiling pgmR3PoolReset(). */
2446	STAMPROFILE StatR3Reset;
2447	/** Profiling pgmPoolFlushPage(). */
2448	STAMPROFILE StatFlushPage;
2449	/** Profiling pgmPoolFree(). */
2450	STAMPROFILE StatFree;
2451	/** Counting explicit flushes by PGMPoolFlushPage(). */
2452	STAMCOUNTER StatForceFlushPage;
2453	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2454	STAMCOUNTER StatForceFlushDirtyPage;
2455	/** Counting flushes for reused pages. */
2456	STAMCOUNTER StatForceFlushReused;
2457	/** Profiling time spent zeroing pages. */
2458	STAMPROFILE StatZeroPage;
2459	/** Profiling of pgmPoolTrackDeref. */
2460	STAMPROFILE StatTrackDeref;
2461	/** Profiling pgmTrackFlushGCPhysPT. */
2462	STAMPROFILE StatTrackFlushGCPhysPT;
2463	/** Profiling pgmTrackFlushGCPhysPTs. */
2464	STAMPROFILE StatTrackFlushGCPhysPTs;
2465	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2466	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2467	/** Number of times we've been out of user records. */
2468	STAMCOUNTER StatTrackFreeUpOneUser;
2469	/** Nr of flushed entries. */
2470	STAMCOUNTER StatTrackFlushEntry;
2471	/** Nr of updated entries. */
2472	STAMCOUNTER StatTrackFlushEntryKeep;
2473	/** Profiling deref activity related tracking GC physical pages. */
2474	STAMPROFILE StatTrackDerefGCPhys;
2475	/** Number of linear searches for a HCPhys in the ram ranges. */
2476	STAMCOUNTER StatTrackLinearRamSearches;
2477	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2478	STAMCOUNTER StamTrackPhysExtAllocFailures;
2479	/** Profiling the RC/R0 access handler. */
2480	STAMPROFILE StatMonitorRZ;
2481	/** Times we've failed interpreting the instruction. */
2482	STAMCOUNTER StatMonitorRZEmulateInstr;
2483	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2484	STAMPROFILE StatMonitorRZFlushPage;
2485	/* Times we've detected a page table reinit. */
2486	STAMCOUNTER StatMonitorRZFlushReinit;
2487	/** Counting flushes for pages that are modified too often. */
2488	STAMCOUNTER StatMonitorRZFlushModOverflow;
2489	/** Times we've detected fork(). */
2490	STAMCOUNTER StatMonitorRZFork;
2491	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2492	STAMPROFILE StatMonitorRZHandled;
2493	/** Times we've failed interpreting a patch code instruction. */
2494	STAMCOUNTER StatMonitorRZIntrFailPatch1;
2495	/** Times we've failed interpreting a patch code instruction during flushing. */
2496	STAMCOUNTER StatMonitorRZIntrFailPatch2;
2497	/** The number of times we've seen rep prefixes we can't handle. */
2498	STAMCOUNTER StatMonitorRZRepPrefix;
2499	/** Profiling the REP STOSD cases we've handled. */
2500	STAMPROFILE StatMonitorRZRepStosd;
2501	/** Nr of handled PT faults. */
2502	STAMCOUNTER StatMonitorRZFaultPT;
2503	/** Nr of handled PD faults. */
2504	STAMCOUNTER StatMonitorRZFaultPD;
2505	/** Nr of handled PDPT faults. */
2506	STAMCOUNTER StatMonitorRZFaultPDPT;
2507	/** Nr of handled PML4 faults. */
2508	STAMCOUNTER StatMonitorRZFaultPML4;
2509
2510	/** Profiling the R3 access handler. */
2511	STAMPROFILE StatMonitorR3;
2512	/** Times we've failed interpreting the instruction. */
2513	STAMCOUNTER StatMonitorR3EmulateInstr;
2514	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2515	STAMPROFILE StatMonitorR3FlushPage;
2516	/* Times we've detected a page table reinit. */
2517	STAMCOUNTER StatMonitorR3FlushReinit;
2518	/** Counting flushes for pages that are modified too often. */
2519	STAMCOUNTER StatMonitorR3FlushModOverflow;
2520	/** Times we've detected fork(). */
2521	STAMCOUNTER StatMonitorR3Fork;
2522	/** Profiling the R3 access we've handled (except REP STOSD). */
2523	STAMPROFILE StatMonitorR3Handled;
2524	/** The number of times we've seen rep prefixes we can't handle. */
2525	STAMCOUNTER StatMonitorR3RepPrefix;
2526	/** Profiling the REP STOSD cases we've handled. */
2527	STAMPROFILE StatMonitorR3RepStosd;
2528	/** Nr of handled PT faults. */
2529	STAMCOUNTER StatMonitorR3FaultPT;
2530	/** Nr of handled PD faults. */
2531	STAMCOUNTER StatMonitorR3FaultPD;
2532	/** Nr of handled PDPT faults. */
2533	STAMCOUNTER StatMonitorR3FaultPDPT;
2534	/** Nr of handled PML4 faults. */
2535	STAMCOUNTER StatMonitorR3FaultPML4;
2536	/** The number of times we're called in an async thread an need to flush. */
2537	STAMCOUNTER StatMonitorR3Async;
2538	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2539	STAMCOUNTER StatResetDirtyPages;
2540	/** Times we've called pgmPoolAddDirtyPage. */
2541	STAMCOUNTER StatDirtyPage;
2542	/** Times we've had to flush duplicates for dirty page management. */
2543	STAMCOUNTER StatDirtyPageDupFlush;
2544	/** Times we've had to flush because of overflow. */
2545	STAMCOUNTER StatDirtyPageOverFlowFlush;
2546
2547	/** The high water mark for cModifiedPages. */
2548	uint16_t cModifiedPagesHigh;
2549	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2550
2551	/** The number of cache hits. */
2552	STAMCOUNTER StatCacheHits;
2553	/** The number of cache misses. */
2554	STAMCOUNTER StatCacheMisses;
2555	/** The number of times we've got a conflict of 'kind' in the cache. */
2556	STAMCOUNTER StatCacheKindMismatches;
2557	/** Number of times we've been out of pages. */
2558	STAMCOUNTER StatCacheFreeUpOne;
2559	/** The number of cacheable allocations. */
2560	STAMCOUNTER StatCacheCacheable;
2561	/** The number of uncacheable allocations. */
2562	STAMCOUNTER StatCacheUncacheable;
2563	#else
2564	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2565	#endif
2566	/** The AVL tree for looking up a page by its HC physical address. */
2567	AVLOHCPHYSTREE HCPhysTree;
2568	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2569	/** Array of pages. (cMaxPages in length)
2570	* The Id is the index into thist array.
2571	*/
2572	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2573	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2574	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2575	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2576	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2577	#ifdef VBOX_WITH_STATISTICS
2578	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2579	#endif
2580	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2581
2582
2583	/** @def PGMPOOL_PAGE_2_PTR
2584	* Maps a pool page pool into the current context.
2585	*
2586	* @returns VBox status code.
2587	* @param a_pVM Pointer to the VM.
2588	* @param a_pPage The pool page.
2589	*
2590	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2591	* small page window employeed by that function. Be careful.
2592	* @remark There is no need to assert on the result.
2593	*/
2594	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2595	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2596	#elif defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2597	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2598	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2599	{
2600	AssertPtr(a_pPage);
2601	AssertReleaseMsg(RT_VALID_PTR(a_pPage->pvPageR3), ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp caller=%s\n", a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, pszCaller));
2602	return a_pPage->pvPageR3;
2603	}
2604	#else
2605	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2606	#endif
2607
2608
2609	/** @def PGMPOOL_PAGE_2_PTR_V2
2610	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2611	*
2612	* @returns VBox status code.
2613	* @param a_pVM Pointer to the VM.
2614	* @param a_pVCpu The current CPU.
2615	* @param a_pPage The pool page.
2616	*
2617	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2618	* small page window employeed by that function. Be careful.
2619	* @remark There is no need to assert on the result.
2620	*/
2621	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2622	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2623	#else
2624	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2625	#endif
2626
2627
2628	/** @name Per guest page tracking data.
2629	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2630	* is to use more bits for it and split it up later on. But for now we'll play
2631	* safe and change as little as possible.
2632	*
2633	* The 16-bit word has two parts:
2634	*
2635	* The first 14-bit forms the @a idx field. It is either the index of a page in
2636	* the shadow page pool, or and index into the extent list.
2637	*
2638	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2639	* shadow page pool references to the page. If cRefs equals
2640	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2641	* (misnomer) table and not the shadow page pool.
2642	*
2643	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2644	* the 16-bit word.
2645	*
2646	* @{ */
2647	/** The shift count for getting to the cRefs part. */
2648	#define PGMPOOL_TD_CREFS_SHIFT 14
2649	/** The mask applied after shifting the tracking data down by
2650	* PGMPOOL_TD_CREFS_SHIFT. */
2651	#define PGMPOOL_TD_CREFS_MASK 0x3
2652	/** The cRefs value used to indicate that the idx is the head of a
2653	* physical cross reference list. */
2654	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2655	/** The shift used to get idx. */
2656	#define PGMPOOL_TD_IDX_SHIFT 0
2657	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2658	#define PGMPOOL_TD_IDX_MASK 0x3fff
2659	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2660	* simply too many mappings of this page. */
2661	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2662
2663	/** @def PGMPOOL_TD_MAKE
2664	* Makes a 16-bit tracking data word.
2665	*
2666	* @returns tracking data.
2667	* @param cRefs The @a cRefs field. Must be within bounds!
2668	* @param idx The @a idx field. Must also be within bounds! */
2669	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2670
2671	/** @def PGMPOOL_TD_GET_CREFS
2672	* Get the @a cRefs field from a tracking data word.
2673	*
2674	* @returns The @a cRefs field
2675	* @param u16 The tracking data word.
2676	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2677	* non-zero @a u16. */
2678	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2679
2680	/** @def PGMPOOL_TD_GET_IDX
2681	* Get the @a idx field from a tracking data word.
2682	*
2683	* @returns The @a idx field
2684	* @param u16 The tracking data word. */
2685	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2686	/** @} */
2687
2688
2689
2690	/** @name A20 gate macros
2691	* @{ */
2692	#define PGM_WITH_A20
2693	#ifdef PGM_WITH_A20
2694	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2695	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2696	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2697	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2698	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2699	#else
2700	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2701	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2702	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2703	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2704	#endif
2705	/** @} */
2706
2707
2708	/**
2709	* Roots and anchors for trees and list employing self relative offsets as
2710	* pointers.
2711	*
2712	* When using self-relative offsets instead of pointers, the offsets needs to be
2713	* the same in all offsets. Thus the roots and anchors needs to live on the
2714	* hyper heap just like the nodes.
2715	*/
2716	typedef struct PGMTREES
2717	{
2718	/** List of physical access handler types (offset pointers) of type
2719	* PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2720	RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2721	/** Physical access handlers (AVL range+offsetptr tree). */
2722	AVLROGCPHYSTREE PhysHandlers;
2723	#ifdef VBOX_WITH_RAW_MODE
2724	/** Virtual access handlers (AVL range + GC ptr tree). */
2725	AVLROGCPTRTREE VirtHandlers;
2726	/** Virtual access handlers (Phys range AVL range + offsetptr tree).
2727	* @remarks Handler of the hypervisor kind are of course not present. */
2728	AVLROGCPHYSTREE PhysToVirtHandlers;
2729	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2730	AVLROGCPTRTREE HyperVirtHandlers;
2731	/** List of virtual access handler types (offset pointers) of type
2732	* PGMVIRTHANDLERTYPEINT. This is needed for relocations. */
2733	RTLISTOFF32ANCHOR HeadVirtHandlerTypes;
2734	#endif
2735	} PGMTREES;
2736	/** Pointer to PGM trees. */
2737	typedef PGMTREES *PPGMTREES;
2738
2739
2740	/**
2741	* Page fault guest state for the AMD64 paging mode.
2742	*/
2743	typedef struct PGMPTWALKCORE
2744	{
2745	/** The guest virtual address that is being resolved by the walk
2746	* (input). */
2747	RTGCPTR GCPtr;
2748
2749	/** The guest physical address that is the result of the walk.
2750	* @remarks only valid if fSucceeded is set. */
2751	RTGCPHYS GCPhys;
2752
2753	/** Set if the walk succeeded, i.d. GCPhys is valid. */
2754	bool fSucceeded;
2755	/** The level problem arrised at.
2756	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2757	* level 8. This is 0 on success. */
2758	uint8_t uLevel;
2759	/** Set if the page isn't present. */
2760	bool fNotPresent;
2761	/** Encountered a bad physical address. */
2762	bool fBadPhysAddr;
2763	/** Set if there was reserved bit violations. */
2764	bool fRsvdError;
2765	/** Set if it involves a big page (2/4 MB). */
2766	bool fBigPage;
2767	/** Set if it involves a gigantic page (1 GB). */
2768	bool fGigantPage;
2769	/** The effect X86_PTE_US flag for the address. */
2770	bool fEffectiveUS;
2771	/** The effect X86_PTE_RW flag for the address. */
2772	bool fEffectiveRW;
2773	/** The effect X86_PTE_NX flag for the address. */
2774	bool fEffectiveNX;
2775	} PGMPTWALKCORE;
2776
2777
2778	/**
2779	* Guest page table walk for the AMD64 mode.
2780	*/
2781	typedef struct PGMPTWALKGSTAMD64
2782	{
2783	/** The common core. */
2784	PGMPTWALKCORE Core;
2785
2786	PX86PML4 pPml4;
2787	PX86PML4E pPml4e;
2788	X86PML4E Pml4e;
2789
2790	PX86PDPT pPdpt;
2791	PX86PDPE pPdpe;
2792	X86PDPE Pdpe;
2793
2794	PX86PDPAE pPd;
2795	PX86PDEPAE pPde;
2796	X86PDEPAE Pde;
2797
2798	PX86PTPAE pPt;
2799	PX86PTEPAE pPte;
2800	X86PTEPAE Pte;
2801	} PGMPTWALKGSTAMD64;
2802	/** Pointer to a AMD64 guest page table walk. */
2803	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2804	/** Pointer to a const AMD64 guest page table walk. */
2805	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2806
2807	/**
2808	* Guest page table walk for the PAE mode.
2809	*/
2810	typedef struct PGMPTWALKGSTPAE
2811	{
2812	/** The common core. */
2813	PGMPTWALKCORE Core;
2814
2815	PX86PDPT pPdpt;
2816	PX86PDPE pPdpe;
2817	X86PDPE Pdpe;
2818
2819	PX86PDPAE pPd;
2820	PX86PDEPAE pPde;
2821	X86PDEPAE Pde;
2822
2823	PX86PTPAE pPt;
2824	PX86PTEPAE pPte;
2825	X86PTEPAE Pte;
2826	} PGMPTWALKGSTPAE;
2827	/** Pointer to a PAE guest page table walk. */
2828	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2829	/** Pointer to a const AMD64 guest page table walk. */
2830	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2831
2832	/**
2833	* Guest page table walk for the 32-bit mode.
2834	*/
2835	typedef struct PGMPTWALKGST32BIT
2836	{
2837	/** The common core. */
2838	PGMPTWALKCORE Core;
2839
2840	PX86PD pPd;
2841	PX86PDE pPde;
2842	X86PDE Pde;
2843
2844	PX86PT pPt;
2845	PX86PTE pPte;
2846	X86PTE Pte;
2847	} PGMPTWALKGST32BIT;
2848	/** Pointer to a 32-bit guest page table walk. */
2849	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2850	/** Pointer to a const 32-bit guest page table walk. */
2851	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2852
2853	/**
2854	* Which part of PGMPTWALKGST that is valid.
2855	*/
2856	typedef enum PGMPTWALKGSTTYPE
2857	{
2858	/** Customary invalid 0 value. */
2859	PGMPTWALKGSTTYPE_INVALID = 0,
2860	/** PGMPTWALKGST::u.Amd64 is valid. */
2861	PGMPTWALKGSTTYPE_AMD64,
2862	/** PGMPTWALKGST::u.Pae is valid. */
2863	PGMPTWALKGSTTYPE_PAE,
2864	/** PGMPTWALKGST::u.Legacy is valid. */
2865	PGMPTWALKGSTTYPE_32BIT,
2866	/** Customary 32-bit type hack. */
2867	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2868	} PGMPTWALKGSTTYPE;
2869
2870	/**
2871	* Combined guest page table walk result.
2872	*/
2873	typedef struct PGMPTWALKGST
2874	{
2875	union
2876	{
2877	/** The page walker core - always valid. */
2878	PGMPTWALKCORE Core;
2879	/** The page walker for AMD64. */
2880	PGMPTWALKGSTAMD64 Amd64;
2881	/** The page walker for PAE (32-bit). */
2882	PGMPTWALKGSTPAE Pae;
2883	/** The page walker for 32-bit paging (called legacy due to C naming
2884	* convension). */
2885	PGMPTWALKGST32BIT Legacy;
2886	} u;
2887	/** Indicates which part of the union is valid. */
2888	PGMPTWALKGSTTYPE enmType;
2889	} PGMPTWALKGST;
2890	/** Pointer to a combined guest page table walk result. */
2891	typedef PGMPTWALKGST *PPGMPTWALKGST;
2892	/** Pointer to a read-only combined guest page table walk result. */
2893	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2894
2895
2896	/** @name Paging mode macros
2897	* @{
2898	*/
2899	#ifdef IN_RC
2900	# define PGM_CTX(a,b) a##RC##b
2901	# define PGM_CTX_STR(a,b) a "GC" b
2902	# define PGM_CTX_DECL(type) VMMRCDECL(type)
2903	#else
2904	# ifdef IN_RING3
2905	# define PGM_CTX(a,b) a##R3##b
2906	# define PGM_CTX_STR(a,b) a "R3" b
2907	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2908	# else
2909	# define PGM_CTX(a,b) a##R0##b
2910	# define PGM_CTX_STR(a,b) a "R0" b
2911	# define PGM_CTX_DECL(type) VMMDECL(type)
2912	# endif
2913	#endif
2914
2915	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2916	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2917	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2918	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2919	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2920	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2921	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2922	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2923	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2924	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2925	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2926	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2927	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2928	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2929	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2930	#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2931	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2932
2933	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2934	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2935	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2936	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2937	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2938	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2939	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2940	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2941	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2942	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2943	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2944	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2945	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2946	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2947	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2948	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2949	#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2950
2951	/* Shw_Gst */
2952	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2953	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2954	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2955	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2956	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2957	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2958	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2959	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2960	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2961	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2962	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2963	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2964	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2965	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2966	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2967	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2968	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2969	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2970	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2971
2972	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2973	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2974	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2975	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2976	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2977	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2978	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2979	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2980	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2981	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2982	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2983	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2984	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2985	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2986	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2987	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2988	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2989	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2990	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2991	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2992	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2993	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2994	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2995	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2996	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2997	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2998	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2999	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
3000	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
3001	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
3002	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
3003	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
3004	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
3005	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
3006	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
3007	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
3008	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
3009
3010	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
3011	#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
3012	/** @} */
3013
3014	/**
3015	* Data for each paging mode.
3016	*/
3017	typedef struct PGMMODEDATA
3018	{
3019	/** The guest mode type. */
3020	uint32_t uGstType;
3021	/** The shadow mode type. */
3022	uint32_t uShwType;
3023
3024	/** @name Function pointers for Shadow paging.
3025	* @{
3026	*/
3027	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3028	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3029	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3030	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3031
3032	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3033	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3034
3035	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3036	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3037	/** @} */
3038
3039	/** @name Function pointers for Guest paging.
3040	* @{
3041	*/
3042	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3043	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3044	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3045	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3046	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3047	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3048	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3049	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3050	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3051	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3052	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3053	/** @} */
3054
3055	/** @name Function pointers for Both Shadow and Guest paging.
3056	* @{
3057	*/
3058	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3059	/* no pfnR3BthTrap0eHandler */
3060	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3061	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3062	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3063	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3064	#ifdef VBOX_STRICT
3065	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3066	#endif
3067	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3068	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3069
3070	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3071	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3072	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3073	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3074	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3075	#ifdef VBOX_STRICT
3076	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3077	#endif
3078	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3079	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3080
3081	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3082	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3083	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3084	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3085	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3086	#ifdef VBOX_STRICT
3087	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3088	#endif
3089	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3090	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3091	/** @} */
3092	} PGMMODEDATA, *PPGMMODEDATA;
3093
3094
3095	#ifdef VBOX_WITH_STATISTICS
3096	/**
3097	* PGM statistics.
3098	*
3099	* These lives on the heap when compiled in as they would otherwise waste
3100	* unnecessary space in release builds.
3101	*/
3102	typedef struct PGMSTATS
3103	{
3104	/* R3 only: */
3105	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
3106	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
3107
3108	/* R3+RZ */
3109	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
3110	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
3111	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
3112	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
3113	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
3114	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
3115	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
3116	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
3117	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
3118	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
3119	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
3120	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
3121	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
3122	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
3123	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
3124	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
3125	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
3126	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
3127	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
3128	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
3129	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
3130	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
3131	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
3132	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
3133	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
3134	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
3135	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
3136	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
3137	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
3138	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
3139	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
3140	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
3141
3142	/* RC only: */
3143	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
3144	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
3145
3146	STAMCOUNTER StatRZPhysRead;
3147	STAMCOUNTER StatRZPhysReadBytes;
3148	STAMCOUNTER StatRZPhysWrite;
3149	STAMCOUNTER StatRZPhysWriteBytes;
3150	STAMCOUNTER StatR3PhysRead;
3151	STAMCOUNTER StatR3PhysReadBytes;
3152	STAMCOUNTER StatR3PhysWrite;
3153	STAMCOUNTER StatR3PhysWriteBytes;
3154	STAMCOUNTER StatRCPhysRead;
3155	STAMCOUNTER StatRCPhysReadBytes;
3156	STAMCOUNTER StatRCPhysWrite;
3157	STAMCOUNTER StatRCPhysWriteBytes;
3158
3159	STAMCOUNTER StatRZPhysSimpleRead;
3160	STAMCOUNTER StatRZPhysSimpleReadBytes;
3161	STAMCOUNTER StatRZPhysSimpleWrite;
3162	STAMCOUNTER StatRZPhysSimpleWriteBytes;
3163	STAMCOUNTER StatR3PhysSimpleRead;
3164	STAMCOUNTER StatR3PhysSimpleReadBytes;
3165	STAMCOUNTER StatR3PhysSimpleWrite;
3166	STAMCOUNTER StatR3PhysSimpleWriteBytes;
3167	STAMCOUNTER StatRCPhysSimpleRead;
3168	STAMCOUNTER StatRCPhysSimpleReadBytes;
3169	STAMCOUNTER StatRCPhysSimpleWrite;
3170	STAMCOUNTER StatRCPhysSimpleWriteBytes;
3171
3172	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
3173	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
3174	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
3175	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
3176	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
3177	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
3178	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
3179
3180	/** Time spent by the host OS for large page allocation. */
3181	STAMPROFILE StatAllocLargePage;
3182	/** Time spent clearing the newly allocated large pages. */
3183	STAMPROFILE StatClearLargePage;
3184	/** The number of times allocating a large pages takes more than the allowed period. */
3185	STAMCOUNTER StatLargePageOverflow;
3186	/** pgmPhysIsValidLargePage profiling - R3 */
3187	STAMPROFILE StatR3IsValidLargePage;
3188	/** pgmPhysIsValidLargePage profiling - RZ*/
3189	STAMPROFILE StatRZIsValidLargePage;
3190
3191	STAMPROFILE StatChunkAging;
3192	STAMPROFILE StatChunkFindCandidate;
3193	STAMPROFILE StatChunkUnmap;
3194	STAMPROFILE StatChunkMap;
3195	} PGMSTATS;
3196	#endif /* VBOX_WITH_STATISTICS */
3197
3198
3199	/**
3200	* Converts a PGM pointer into a VM pointer.
3201	* @returns Pointer to the VM structure the PGM is part of.
3202	* @param pPGM Pointer to PGM instance data.
3203	*/
3204	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
3205
3206	/**
3207	* PGM Data (part of VM)
3208	*/
3209	typedef struct PGM
3210	{
3211	/** Offset to the VM structure. */
3212	int32_t offVM;
3213	/** Offset of the PGMCPU structure relative to VMCPU. */
3214	int32_t offVCpuPGM;
3215
3216	/** @cfgm{/RamPreAlloc, boolean, false}
3217	* Indicates whether the base RAM should all be allocated before starting
3218	* the VM (default), or if it should be allocated when first written to.
3219	*/
3220	bool fRamPreAlloc;
3221	/** Indicates whether write monitoring is currently in use.
3222	* This is used to prevent conflicts between live saving and page sharing
3223	* detection. */
3224	bool fPhysWriteMonitoringEngaged;
3225	/** Set if the CPU has less than 52-bit physical address width.
3226	* This is used */
3227	bool fLessThan52PhysicalAddressBits;
3228	/** Set when nested paging is active.
3229	* This is meant to save calls to HMIsNestedPagingActive and let the
3230	* compilers optimize the code better. Whether we use nested paging or
3231	* not is something we find out during VMM initialization and we won't
3232	* change this later on. */
3233	bool fNestedPaging;
3234	/** The host paging mode. (This is what SUPLib reports.) */
3235	SUPPAGINGMODE enmHostMode;
3236	/** We're not in a state which permits writes to guest memory.
3237	* (Only used in strict builds.) */
3238	bool fNoMorePhysWrites;
3239	/** @cfgm{/PageFusionAllowed, boolean, false}
3240	* Whether page fusion is allowed. */
3241	bool fPageFusionAllowed;
3242	/** @cfgm{/PGM/PciPassThrough, boolean, false}
3243	* Whether PCI passthrough is enabled. */
3244	bool fPciPassthrough;
3245	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3246	uint8_t cMmio2Regions;
3247	/** Alignment padding that makes the next member start on a 8 byte boundary. */
3248	bool afAlignment1[1];
3249
3250	/** Indicates that PGMR3FinalizeMappings has been called and that further
3251	* PGMR3MapIntermediate calls will be rejected. */
3252	bool fFinalizedMappings;
3253	/** If set no conflict checks are required. */
3254	bool fMappingsFixed;
3255	/** If set if restored as fixed but we were unable to re-fixate at the old
3256	* location because of room or address incompatibilities. */
3257	bool fMappingsFixedRestored;
3258	/** Size of fixed mapping.
3259	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3260	uint32_t cbMappingFixed;
3261	/** Generation ID for the RAM ranges. This member is incremented everytime
3262	* a RAM range is linked or unlinked. */
3263	uint32_t volatile idRamRangesGen;
3264
3265	/** Base address (GC) of fixed mapping.
3266	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3267	RTGCPTR GCPtrMappingFixed;
3268	/** The address of the previous RAM range mapping. */
3269	RTGCPTR GCPtrPrevRamRangeMapping;
3270
3271	/** Physical access handler type for ROM protection. */
3272	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3273	/** Alignment padding. */
3274	uint32_t u32Padding;
3275
3276	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3277	RTGCPHYS GCPhys4MBPSEMask;
3278	/** Mask containing the invalid bits of a guest physical address.
3279	* @remarks this does not stop at bit 52. */
3280	RTGCPHYS GCPhysInvAddrMask;
3281
3282
3283	/** RAM range TLB for R3. */
3284	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3285	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3286	* This is sorted by physical address and contains no overlapping ranges. */
3287	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3288	/** Root of the RAM range search tree for ring-3. */
3289	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3290	/** PGM offset based trees - R3 Ptr. */
3291	R3PTRTYPE(PPGMTREES) pTreesR3;
3292	/** Caching the last physical handler we looked up in R3. */
3293	R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3294	/** Shadow Page Pool - R3 Ptr. */
3295	R3PTRTYPE(PPGMPOOL) pPoolR3;
3296	/** Linked list of GC mappings - for HC.
3297	* The list is sorted ascending on address. */
3298	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3299	/** Pointer to the list of ROM ranges - for R3.
3300	* This is sorted by physical address and contains no overlapping ranges. */
3301	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3302	/** Pointer to the list of MMIO2 ranges - for R3.
3303	* Registration order. */
3304	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
3305	/** Pointer to SHW+GST mode data (function pointers).
3306	* The index into this table is made up from */
3307	R3PTRTYPE(PPGMMODEDATA) paModeData;
3308	RTR3PTR R3PtrAlignment0;
3309	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3310	R3PTRTYPE(PPGMMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3311
3312	/** RAM range TLB for R0. */
3313	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3314	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3315	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3316	/** Root of the RAM range search tree for ring-0. */
3317	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3318	/** PGM offset based trees - R0 Ptr. */
3319	R0PTRTYPE(PPGMTREES) pTreesR0;
3320	/** Caching the last physical handler we looked up in R0. */
3321	R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3322	/** Shadow Page Pool - R0 Ptr. */
3323	R0PTRTYPE(PPGMPOOL) pPoolR0;
3324	/** Linked list of GC mappings - for R0.
3325	* The list is sorted ascending on address. */
3326	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3327	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3328	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3329	RTR0PTR R0PtrAlignment0;
3330	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3331	R0PTRTYPE(PPGMMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3332
3333	/** RAM range TLB for RC. */
3334	RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3335	/** RC pointer corresponding to PGM::pRamRangesXR3. */
3336	RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3337	/** Root of the RAM range search tree for raw-mode context. */
3338	RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3339	/** PGM offset based trees - RC Ptr. */
3340	RCPTRTYPE(PPGMTREES) pTreesRC;
3341	/** Caching the last physical handler we looked up in RC. */
3342	RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3343	/** Shadow Page Pool - RC Ptr. */
3344	RCPTRTYPE(PPGMPOOL) pPoolRC;
3345	/** Linked list of GC mappings - for RC.
3346	* The list is sorted ascending on address. */
3347	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3348	/** RC pointer corresponding to PGM::pRomRangesR3. */
3349	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3350	RTRCPTR RCPtrAlignment0;
3351	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3352	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3353	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3354	RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3355
3356
3357	/** Pointer to the 5 page CR3 content mapping.
3358	* The first page is always the CR3 (in some form) while the 4 other pages
3359	* are used of the PDs in PAE mode. */
3360	RTGCPTR GCPtrCR3Mapping;
3361
3362	/** @name Intermediate Context
3363	* @{ */
3364	/** Pointer to the intermediate page directory - Normal. */
3365	R3PTRTYPE(PX86PD) pInterPD;
3366	/** Pointer to the intermediate page tables - Normal.
3367	* There are two page tables, one for the identity mapping and one for
3368	* the host context mapping (of the core code). */
3369	R3PTRTYPE(PX86PT) apInterPTs[2];
3370	/** Pointer to the intermediate page tables - PAE. */
3371	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3372	/** Pointer to the intermediate page directory - PAE. */
3373	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3374	/** Pointer to the intermediate page directory - PAE. */
3375	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3376	/** Pointer to the intermediate page-map level 4 - AMD64. */
3377	R3PTRTYPE(PX86PML4) pInterPaePML4;
3378	/** Pointer to the intermediate page directory - AMD64. */
3379	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3380	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3381	RTHCPHYS HCPhysInterPD;
3382	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3383	RTHCPHYS HCPhysInterPaePDPT;
3384	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3385	RTHCPHYS HCPhysInterPaePML4;
3386	/** @} */
3387
3388	/** Base address of the dynamic page mapping area.
3389	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3390	*
3391	* @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3392	* work out. Some cleaning up of the initialization that would
3393	* remove this memory is yet to be done...
3394	*/
3395	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3396	/** The address of the raw-mode context mapping cache. */
3397	RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3398	/** The address of the ring-0 mapping cache if we're making use of it. */
3399	RTR0PTR pvR0DynMapUsed;
3400
3401	/** Hack: Number of deprecated page mapping locks taken by the current lock
3402	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3403	uint32_t cDeprecatedPageLocks;
3404	#if HC_ARCH_BITS == 64
3405	/** Alignment padding. */
3406	uint32_t u32Alignment2;
3407	#endif
3408
3409
3410	/** PGM critical section.
3411	* This protects the physical & virtual access handlers, ram ranges,
3412	* and the page flag updating (some of it anyway).
3413	*/
3414	PDMCRITSECT CritSectX;
3415
3416	/**
3417	* Data associated with managing the ring-3 mappings of the allocation chunks.
3418	*/
3419	struct
3420	{
3421	/** The chunk tree, ordered by chunk id. */
3422	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3423	R3PTRTYPE(PAVLU32NODECORE) pTree;
3424	#else
3425	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3426	#endif
3427	#if HC_ARCH_BITS == 32
3428	uint32_t u32Alignment0;
3429	#endif
3430	/** The chunk mapping TLB. */
3431	PGMCHUNKR3MAPTLB Tlb;
3432	/** The number of mapped chunks. */
3433	uint32_t c;
3434	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3435	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3436	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3437	uint32_t cMax;
3438	/** The current time. This is incremented whenever a chunk is inserted. */
3439	uint32_t iNow;
3440	/** Alignment padding. */
3441	uint32_t u32Alignment1;
3442	} ChunkR3Map;
3443
3444	/**
3445	* The page mapping TLB for ring-3 and (for the time being) ring-0.
3446	*/
3447	PGMPAGER3MAPTLB PhysTlbHC;
3448
3449	/** @name The zero page.
3450	* @{ */
3451	/** The host physical address of the zero page. */
3452	RTHCPHYS HCPhysZeroPg;
3453	/** The ring-3 mapping of the zero page. */
3454	RTR3PTR pvZeroPgR3;
3455	/** The ring-0 mapping of the zero page. */
3456	RTR0PTR pvZeroPgR0;
3457	/** The GC mapping of the zero page. */
3458	RTRCPTR pvZeroPgRC;
3459	RTRCPTR RCPtrAlignment3;
3460	/** @}*/
3461
3462	/** @name The Invalid MMIO page.
3463	* This page is filled with 0xfeedface.
3464	* @{ */
3465	/** The host physical address of the invalid MMIO page. */
3466	RTHCPHYS HCPhysMmioPg;
3467	/** The host pysical address of the invalid MMIO page plus all invalid
3468	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3469	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3470	RTHCPHYS HCPhysInvMmioPg;
3471	/** The ring-3 mapping of the invalid MMIO page. */
3472	RTR3PTR pvMmioPgR3;
3473	#if HC_ARCH_BITS == 32
3474	RTR3PTR R3PtrAlignment4;
3475	#endif
3476	/** @} */
3477
3478
3479	/** The number of handy pages. */
3480	uint32_t cHandyPages;
3481
3482	/** The number of large handy pages. */
3483	uint32_t cLargeHandyPages;
3484
3485	/**
3486	* Array of handy pages.
3487	*
3488	* This array is used in a two way communication between pgmPhysAllocPage
3489	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3490	* an intermediary.
3491	*
3492	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3493	* (The current size of 32 pages, means 128 KB of handy memory.)
3494	*/
3495	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3496
3497	/**
3498	* Array of large handy pages. (currently size 1)
3499	*
3500	* This array is used in a two way communication between pgmPhysAllocLargePage
3501	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3502	* an intermediary.
3503	*/
3504	GMMPAGEDESC aLargeHandyPage[1];
3505
3506	/**
3507	* Live save data.
3508	*/
3509	struct
3510	{
3511	/** Per type statistics. */
3512	struct
3513	{
3514	/** The number of ready pages. */
3515	uint32_t cReadyPages;
3516	/** The number of dirty pages. */
3517	uint32_t cDirtyPages;
3518	/** The number of ready zero pages. */
3519	uint32_t cZeroPages;
3520	/** The number of write monitored pages. */
3521	uint32_t cMonitoredPages;
3522	} Rom,
3523	Mmio2,
3524	Ram;
3525	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3526	uint32_t cIgnoredPages;
3527	/** Indicates that a live save operation is active. */
3528	bool fActive;
3529	/** Padding. */
3530	bool afReserved[2];
3531	/** The next history index. */
3532	uint8_t iDirtyPagesHistory;
3533	/** History of the total amount of dirty pages. */
3534	uint32_t acDirtyPagesHistory[64];
3535	/** Short term dirty page average. */
3536	uint32_t cDirtyPagesShort;
3537	/** Long term dirty page average. */
3538	uint32_t cDirtyPagesLong;
3539	/** The number of saved pages. This is used to get some kind of estimate of the
3540	* link speed so we can decide when we're done. It is reset after the first
3541	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3542	* zero pages. */
3543	uint64_t cSavedPages;
3544	/** The nanosecond timestamp when cSavedPages was 0. */
3545	uint64_t uSaveStartNS;
3546	/** Pages per second (for statistics). */
3547	uint32_t cPagesPerSecond;
3548	uint32_t cAlignment;
3549	} LiveSave;
3550
3551	/** @name Error injection.
3552	* @{ */
3553	/** Inject handy page allocation errors pretending we're completely out of
3554	* memory. */
3555	bool volatile fErrInjHandyPages;
3556	/** Padding. */
3557	bool afReserved[3];
3558	/** @} */
3559
3560	/** @name Release Statistics
3561	* @{ */
3562	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3563	uint32_t cPrivatePages; /*< The number of private pages. /
3564	uint32_t cSharedPages; /*< The number of shared pages. /
3565	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3566	uint32_t cZeroPages; /*< The number of zero backed pages. /
3567	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3568	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3569	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3570	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3571	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3572	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3573	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3574	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3575	uint32_t cLargePages; /*< The number of large pages. /
3576	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3577	/* uint32_t aAlignment4[1]; */
3578
3579	/** The number of times we were forced to change the hypervisor region location. */
3580	STAMCOUNTER cRelocations;
3581
3582	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3583	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3584	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3585
3586	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3587	/** @} */
3588
3589	#ifdef VBOX_WITH_STATISTICS
3590	/** @name Statistics on the heap.
3591	* @{ */
3592	R3PTRTYPE(PGMSTATS *) pStatsR3;
3593	R0PTRTYPE(PGMSTATS *) pStatsR0;
3594	RCPTRTYPE(PGMSTATS *) pStatsRC;
3595	RTRCPTR RCPtrAlignment;
3596	/** @} */
3597	#endif
3598	} PGM;
3599	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3600	AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3601	AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3602	AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3603	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3604	AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3605	AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3606	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3607	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3608	AssertCompileMemberAlignment(PGM, cRelocations, 8);
3609	#endif /* !IN_TSTVMSTRUCTGC */
3610	/** Pointer to the PGM instance data. */
3611	typedef PGM *PPGM;
3612
3613
3614
3615	typedef struct PGMCPUSTATS
3616	{
3617	/* Common */
3618	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3619	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3620
3621	/* R0 only: */
3622	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3623	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3624
3625	/* RZ only: */
3626	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3627	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3628	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3629	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3630	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3631	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3632	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
3633	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3634	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3635	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3636	STAMPROFILE StatRZTrap0eTime2Mapping; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. /
3637	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3638	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3639	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3640	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
3641	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3642	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3643	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3644	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3645	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3646	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3647	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
3648	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3649	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3650	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3651	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3652	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
3653	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
3654	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
3655	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3656	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3657	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3658	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3659	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3660	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3661	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3662	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3663	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3664	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3665	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3666	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3667	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3668	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3669	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest \#PF to HMA or other mapping. /
3670	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3671	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3672	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3673	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3674	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3675	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3676	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3677	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3678	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3679	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3680	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3681	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3682	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3683	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3684	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3685	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3686	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3687	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3688	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3689	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3690	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3691	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3692	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3693	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3694	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3695	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3696	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3697	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3698	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3699	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3700	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3701	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3702	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3703	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3704
3705	/* HC - R3 and (maybe) R0: */
3706
3707	/* RZ & R3: */
3708	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3709	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3710	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3711	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3712	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3713	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3714	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3715	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3716	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3717	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3718	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3719	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3720	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3721	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3722	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3723	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3724	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3725	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). /
3726	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3727	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3728	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3729	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3730	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3731	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3732	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3733	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3734	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3735	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3736	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3737	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3738	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3739	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3740	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3741	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3742	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3743	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3744	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3745	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3746	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3747	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3748	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3749	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3750	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3751	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3752	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3753	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3754	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3755
3756	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3757	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3758	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3759	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3760	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3761	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3762	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3763	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3764	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3765	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3766	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3767	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3768	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3769	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3770	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3771	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3772	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3773	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3774	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3775	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3776	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3777	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3778	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3779	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3780	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3781	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3782	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3783	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3784	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3785	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3786	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3787	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3788	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3789	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3790	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3791	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3792	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3793	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3794	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3795	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3796	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3797	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3798	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3799	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3800	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3801	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3802	/** @} */
3803	} PGMCPUSTATS;
3804
3805
3806	/**
3807	* Converts a PGMCPU pointer into a VM pointer.
3808	* @returns Pointer to the VM structure the PGM is part of.
3809	* @param pPGM Pointer to PGMCPU instance data.
3810	*/
3811	#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3812
3813	/**
3814	* Converts a PGMCPU pointer into a PGM pointer.
3815	* @returns Pointer to the VM structure the PGM is part of.
3816	* @param pPGMCpu Pointer to PGMCPU instance data.
3817	*/
3818	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3819
3820	/**
3821	* PGMCPU Data (part of VMCPU).
3822	*/
3823	typedef struct PGMCPU
3824	{
3825	/** Offset to the VM structure. */
3826	int32_t offVM;
3827	/** Offset to the VMCPU structure. */
3828	int32_t offVCpu;
3829	/** Offset of the PGM structure relative to VMCPU. */
3830	int32_t offPGM;
3831	uint32_t uPadding0; /*< structure size alignment. /
3832
3833	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAW_MODE)
3834	/** Automatically tracked physical memory mapping set.
3835	* Ring-0 and strict raw-mode builds. */
3836	PGMMAPSET AutoSet;
3837	#endif
3838
3839	/** A20 gate mask.
3840	* Our current approach to A20 emulation is to let REM do it and don't bother
3841	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3842	* But whould need arrise, we'll subject physical addresses to this mask. */
3843	RTGCPHYS GCPhysA20Mask;
3844	/** A20 gate state - boolean! */
3845	bool fA20Enabled;
3846	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3847	bool fNoExecuteEnabled;
3848	/** Unused bits. */
3849	bool afUnused[2];
3850
3851	/** What needs syncing (PGM_SYNC_*).
3852	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3853	* PGMFlushTLB, and PGMR3Load. */
3854	uint32_t fSyncFlags;
3855
3856	/** The shadow paging mode. */
3857	PGMMODE enmShadowMode;
3858	/** The guest paging mode. */
3859	PGMMODE enmGuestMode;
3860
3861	/** The current physical address representing in the guest CR3 register. */
3862	RTGCPHYS GCPhysCR3;
3863
3864	/** @name 32-bit Guest Paging.
3865	* @{ */
3866	/** The guest's page directory, R3 pointer. */
3867	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3868	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3869	/** The guest's page directory, R0 pointer. */
3870	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3871	#endif
3872	/** The guest's page directory, static RC mapping. */
3873	RCPTRTYPE(PX86PD) pGst32BitPdRC;
3874	/** Mask containing the MBZ bits of a big page PDE. */
3875	uint32_t fGst32BitMbzBigPdeMask;
3876	/** Set if the page size extension (PSE) is enabled. */
3877	bool fGst32BitPageSizeExtension;
3878	/** Alignment padding. */
3879	bool afAlignment2[3];
3880	/** @} */
3881
3882	/** @name PAE Guest Paging.
3883	* @{ */
3884	/** The guest's page directory pointer table, static RC mapping. */
3885	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3886	/** The guest's page directory pointer table, R3 pointer. */
3887	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3888	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3889	/** The guest's page directory pointer table, R0 pointer. */
3890	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3891	#endif
3892
3893	/** The guest's page directories, R3 pointers.
3894	* These are individual pointers and don't have to be adjacent.
3895	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3896	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3897	/** The guest's page directories, R0 pointers.
3898	* Same restrictions as apGstPaePDsR3. */
3899	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3900	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3901	#endif
3902	/** The guest's page directories, static GC mapping.
3903	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3904	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3905	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3906	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
3907	* @todo Remove this and use aGstPaePdpeRegs instead? */
3908	RTGCPHYS aGCPhysGstPaePDs[4];
3909	/** The values of the 4 PDPE CPU registers (PAE). */
3910	X86PDPE aGstPaePdpeRegs[4];
3911	/** The physical addresses of the monitored guest page directories (PAE). */
3912	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3913	/** Mask containing the MBZ PTE bits. */
3914	uint64_t fGstPaeMbzPteMask;
3915	/** Mask containing the MBZ PDE bits. */
3916	uint64_t fGstPaeMbzPdeMask;
3917	/** Mask containing the MBZ big page PDE bits. */
3918	uint64_t fGstPaeMbzBigPdeMask;
3919	/** Mask containing the MBZ PDPE bits. */
3920	uint64_t fGstPaeMbzPdpeMask;
3921	/** @} */
3922
3923	/** @name AMD64 Guest Paging.
3924	* @{ */
3925	/** The guest's page directory pointer table, R3 pointer. */
3926	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3927	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3928	/** The guest's page directory pointer table, R0 pointer. */
3929	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3930	#else
3931	RTR0PTR alignment6b; /*< alignment equalizer. /
3932	#endif
3933	/** Mask containing the MBZ PTE bits. */
3934	uint64_t fGstAmd64MbzPteMask;
3935	/** Mask containing the MBZ PDE bits. */
3936	uint64_t fGstAmd64MbzPdeMask;
3937	/** Mask containing the MBZ big page PDE bits. */
3938	uint64_t fGstAmd64MbzBigPdeMask;
3939	/** Mask containing the MBZ PDPE bits. */
3940	uint64_t fGstAmd64MbzPdpeMask;
3941	/** Mask containing the MBZ big page PDPE bits. */
3942	uint64_t fGstAmd64MbzBigPdpeMask;
3943	/** Mask containing the MBZ PML4E bits. */
3944	uint64_t fGstAmd64MbzPml4eMask;
3945	/** Mask containing the PDPE bits that we shadow. */
3946	uint64_t fGstAmd64ShadowedPdpeMask;
3947	/** Mask containing the PML4E bits that we shadow. */
3948	uint64_t fGstAmd64ShadowedPml4eMask;
3949	/** @} */
3950
3951	/** @name PAE and AMD64 Guest Paging.
3952	* @{ */
3953	/** Mask containing the PTE bits that we shadow. */
3954	uint64_t fGst64ShadowedPteMask;
3955	/** Mask containing the PDE bits that we shadow. */
3956	uint64_t fGst64ShadowedPdeMask;
3957	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3958	uint64_t fGst64ShadowedBigPdeMask;
3959	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3960	uint64_t fGst64ShadowedBigPde4PteMask;
3961	/** @} */
3962
3963	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3964	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3965	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3966	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3967	/** Pointer to the page of the current active CR3 - RC Ptr. */
3968	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3969	# if HC_ARCH_BITS == 64
3970	RTRCPTR alignment6; /*< structure size alignment. /
3971	# endif
3972	/** @} */
3973
3974	/** @name Function pointers for Shadow paging.
3975	* @{
3976	*/
3977	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3978	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3979	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3980	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3981
3982	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3983	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3984
3985	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3986	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3987
3988	/** @} */
3989
3990	/** @name Function pointers for Guest paging.
3991	* @{
3992	*/
3993	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3994	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3995	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3996	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3997	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3998	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3999	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
4000	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
4001	#if HC_ARCH_BITS == 64
4002	RTRCPTR alignment3; /*< structure size alignment. /
4003	#endif
4004
4005	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
4006	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
4007	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
4008	/** @} */
4009
4010	/** @name Function pointers for Both Shadow and Guest paging.
4011	* @{
4012	*/
4013	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
4014	/* no pfnR3BthTrap0eHandler */
4015	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4016	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4017	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4018	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4019	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4020	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4021	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
4022
4023	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
4024	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4025	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4026	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4027	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4028	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4029	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4030	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
4031
4032	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
4033	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4034	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
4035	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
4036	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
4037	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
4038	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
4039	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
4040	#if 0
4041	RTRCPTR alignment2; /*< structure size alignment. /
4042	#endif
4043	/** @} */
4044
4045	/** For saving stack space, the disassembler state is allocated here instead of
4046	* on the stack. */
4047	DISCPUSTATE DisState;
4048
4049	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
4050	uint64_t cNetwareWp0Hacks;
4051
4052	/** Count the number of pgm pool access handler calls. */
4053	uint64_t cPoolAccessHandler;
4054
4055	/** @name Release Statistics
4056	* @{ */
4057	/** The number of times the guest has switched mode since last reset or statistics reset. */
4058	STAMCOUNTER cGuestModeChanges;
4059	/** The number of times the guest has switched mode since last reset or statistics reset. */
4060	STAMCOUNTER cA20Changes;
4061	/** @} */
4062
4063	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
4064	/** @name Statistics
4065	* @{ */
4066	/** RC: Pointer to the statistics. */
4067	RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
4068	/** RC: Which statistic this \#PF should be attributed to. */
4069	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
4070	/** R0: Pointer to the statistics. */
4071	R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
4072	/** R0: Which statistic this \#PF should be attributed to. */
4073	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
4074	/** R3: Pointer to the statistics. */
4075	R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
4076	/** Alignment padding. */
4077	RTR3PTR pPaddingR3;
4078	/** @} */
4079	#endif /* VBOX_WITH_STATISTICS */
4080	} PGMCPU;
4081	/** Pointer to the per-cpu PGM data. */
4082	typedef PGMCPU *PPGMCPU;
4083
4084
4085	/** @name PGM::fSyncFlags Flags
4086	* @{
4087	*/
4088	/** Updates the virtual access handler state bit in PGMPAGE. */
4089	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
4090	/** Always sync CR3. */
4091	#define PGM_SYNC_ALWAYS RT_BIT(1)
4092	/** Check monitoring on next CR3 (re)load and invalidate page.
4093	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
4094	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
4095	/** Check guest mapping in SyncCR3. */
4096	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
4097	/** Clear the page pool (a light weight flush). */
4098	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
4099	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
4100	/** @} */
4101
4102
4103	RT_C_DECLS_BEGIN
4104
4105	#if defined(VBOX_STRICT) && defined(IN_RING3)
4106	int pgmLockDebug(PVM pVM, RT_SRC_POS_DECL);
4107	# define pgmLock(a_pVM) pgmLockDebug(a_pVM, RT_SRC_POS)
4108	#else
4109	int pgmLock(PVM pVM);
4110	#endif
4111	void pgmUnlock(PVM pVM);
4112	/**
4113	* Asserts that the caller owns the PDM lock.
4114	* This is the internal variant of PGMIsLockOwner.
4115	* @param a_pVM Pointer to the VM.
4116	*/
4117	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSectX))
4118	/**
4119	* Asserts that the caller owns the PDM lock.
4120	* This is the internal variant of PGMIsLockOwner.
4121	* @param a_pVM Pointer to the VM.
4122	* @param a_pVCpu The current CPU handle.
4123	*/
4124	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, pVCpu))
4125
4126	#ifndef PGM_WITHOUT_MAPPINGS
4127	int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
4128	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
4129	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
4130	int pgmMapResolveConflicts(PVM pVM);
4131	#endif /* !PGM_WITHOUT_MAPPINGS */
4132	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
4133	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4134
4135	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
4136	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
4137	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
4138	#ifdef VBOX_WITH_RAW_MODE
4139	PPGMVIRTHANDLER pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, unsigned *piPage);
4140	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
4141	# if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
4142	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
4143	# else
4144	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
4145	# endif
4146	#endif /* VBOX_WITH_RAW_MODE */
4147	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4148	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
4149
4150	int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4151	int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
4152	int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
4153	int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
4154	int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4155	void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
4156	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4157	int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4158	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4159	int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
4160	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
4161	int pgmPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4162	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4163	int pgmPhysGCPhys2CCPtrInternalDepr(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4164	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
4165	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
4166	void pgmPhysReleaseInternalPageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
4167	PGM_ALL_CB2_DECL(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
4168	#ifndef IN_RING3
4169	DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
4170	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
4171	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
4172	#endif
4173	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
4174	void pgmPhysInvalidRamRangeTlbs(PVM pVM);
4175	void pgmPhysInvalidatePageMapTLB(PVM pVM);
4176	void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
4177	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
4178	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
4179	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
4180	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
4181	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
4182
4183	#ifdef IN_RING3
4184	void pgmR3PhysRelinkRamRanges(PVM pVM);
4185	int pgmR3PhysRamPreAllocate(PVM pVM);
4186	int pgmR3PhysRamReset(PVM pVM);
4187	int pgmR3PhysRomReset(PVM pVM);
4188	int pgmR3PhysRamZeroAll(PVM pVM);
4189	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
4190	int pgmR3PhysRamTerm(PVM pVM);
4191	void pgmR3PhysRomTerm(PVM pVM);
4192	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
4193
4194	int pgmR3PoolInit(PVM pVM);
4195	void pgmR3PoolRelocate(PVM pVM);
4196	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
4197	void pgmR3PoolReset(PVM pVM);
4198	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
4199	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4200	void pgmR3PoolWriteProtectPages(PVM pVM);
4201
4202	#endif /* IN_RING3 */
4203	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
4204	int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4205	int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4206	# ifdef LOG_ENABLED
4207	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
4208	# else
4209	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
4210	# endif
4211	#endif
4212	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4213	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4214	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4215	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4216	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4217	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4218	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4219	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4220	int pgmPoolSyncCR3(PVMCPU pVCpu);
4221	bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
4222	void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
4223	int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4224	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4225	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4226	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4227	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4228	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4229	PGM_ALL_CB2_DECL(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
4230	#ifndef IN_RING3
4231	DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPoolAccessPfHandler;
4232	#endif
4233
4234	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4235	void pgmPoolResetDirtyPages(PVM pVM);
4236	void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
4237
4238	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4239	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4240	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4241
4242	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
4243	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
4244	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4245	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4246
4247	int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4248	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4249	int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4250
4251	int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
4252	int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
4253	int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4254	int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
4255	int pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4256
4257	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4258	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4259	FNDBGCCMD pgmR3CmdShowSharedModules;
4260	# endif
4261
4262	RT_C_DECLS_END
4263
4264	/** @} */
4265
4266	#endif
4267

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 58591

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