VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 74251

Last change on this file since 74251 was 73324, checked in by vboxsync, 6 years ago

PGM: Introduced a special shadow paging mode for NEM that translates to minimal unnecessary work. bugref:9044
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1/* $Id: PGMInternal.h 73324 2018-07-23 14:06:55Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/dbg.h>
25#include <VBox/vmm/stam.h>
26#include <VBox/param.h>
27#include <VBox/vmm/vmm.h>
28#include <VBox/vmm/mm.h>
29#include <VBox/vmm/pdmcritsect.h>
30#include <VBox/vmm/pdmapi.h>
31#include <VBox/dis.h>
32#include <VBox/vmm/dbgf.h>
33#include <VBox/log.h>
34#include <VBox/vmm/gmm.h>
35#include <VBox/vmm/hm.h>
36#include <VBox/vmm/hm_vmx.h>
37#include <iprt/asm.h>
38#include <iprt/assert.h>
39#include <iprt/avl.h>
40#include <iprt/critsect.h>
41#include <iprt/list-off32.h>
42#include <iprt/sha.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Indicates that there are no guest mappings in the shadow tables.
59 *
60 * Note! In ring-3 the macro is also used to exclude the managment of the
61 * intermediate context page tables. On 32-bit systems we use the intermediate
62 * context to support 64-bit guest execution. Thus, we cannot fully make it
63 * without mappings there even when VBOX_WITH_RAW_MODE is not defined.
64 *
65 * In raw-mode context there are by design always guest mappings (the code is
66 * executed from one), while in ring-0 there are none at all. Neither context
67 * manages the page tables for intermediate switcher context, that's all done in
68 * ring-3.
69 */
70#if defined(IN_RING0) \
71 || ( !defined(VBOX_WITH_RAW_MODE) \
72 && ( HC_ARCH_BITS != 32 \
73 || !defined(VBOX_WITH_64_BITS_GUESTS) \
74 ) \
75 )
76# define PGM_WITHOUT_MAPPINGS
77#endif
78
79/**
80 * Check and skip global PDEs for non-global flushes
81 */
82#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
83
84/**
85 * Optimization for PAE page tables that are modified often
86 */
87//#if 0 /* disabled again while debugging */
88#ifndef IN_RC
89# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
90#endif
91//#endif
92
93/**
94 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
95 */
96#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
97# define PGM_WITH_LARGE_PAGES
98#endif
99
100/**
101 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
102 * VMX_EXIT_EPT_MISCONFIG.
103 */
104#if 1 /* testing */
105# define PGM_WITH_MMIO_OPTIMIZATIONS
106#endif
107
108/**
109 * Sync N pages instead of a whole page table
110 */
111#define PGM_SYNC_N_PAGES
112
113/**
114 * Number of pages to sync during a page fault
115 *
116 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
117 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
118 *
119 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
120 * world switch overhead, so let's sync more.
121 */
122# ifdef IN_RING0
123/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
124 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
125 * but ~5% fewer faults.
126 */
127# define PGM_SYNC_NR_PAGES 32
128#else
129# define PGM_SYNC_NR_PAGES 8
130#endif
131
132/**
133 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
134 */
135#define PGM_MAX_PHYSCACHE_ENTRIES 64
136#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
137
138
139/** @def PGMPOOL_CFG_MAX_GROW
140 * The maximum number of pages to add to the pool in one go.
141 */
142#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
143
144/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
145 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
146 */
147#ifdef VBOX_STRICT
148# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
149#endif
150
151/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
152 * Enables the experimental lazy page allocation code. */
153#ifdef DOXYGEN_RUNNING
154# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
155#endif
156
157/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
158 * Enables real write monitoring of pages, i.e. mapping them read-only and
159 * only making them writable when getting a write access \#PF. */
160#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
161
162/** @} */
163
164
165/** @name PDPT and PML4 flags.
166 * These are placed in the three bits available for system programs in
167 * the PDPT and PML4 entries.
168 * @{ */
169/** The entry is a permanent one and it's must always be present.
170 * Never free such an entry. */
171#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
172/** Mapping (hypervisor allocated pagetable). */
173#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
174/** @} */
175
176/** @name Page directory flags.
177 * These are placed in the three bits available for system programs in
178 * the page directory entries.
179 * @{ */
180/** Indicates the original entry was a big page.
181 * @remarks This is currently only used for statistics and can be recycled. */
182#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
183/** Mapping (hypervisor allocated pagetable). */
184#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
185/** Made read-only to facilitate dirty bit tracking. */
186#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
187/** @} */
188
189/** @name Page flags.
190 * These are placed in the three bits available for system programs in
191 * the page entries.
192 * @{ */
193/** Made read-only to facilitate dirty bit tracking. */
194#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
195
196#ifndef PGM_PTFLAGS_CSAM_VALIDATED
197/** Scanned and approved by CSAM (tm).
198 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
199 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
200#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
201#endif
202
203/** @} */
204
205/** @name Defines used to indicate the shadow and guest paging in the templates.
206 * @{ */
207#define PGM_TYPE_REAL 1
208#define PGM_TYPE_PROT 2
209#define PGM_TYPE_32BIT 3
210#define PGM_TYPE_PAE 4
211#define PGM_TYPE_AMD64 5
212#define PGM_TYPE_NESTED_32BIT 6
213#define PGM_TYPE_NESTED_PAE 7
214#define PGM_TYPE_NESTED_AMD64 8
215#define PGM_TYPE_EPT 9
216#define PGM_TYPE_NONE 10 /**< Dummy shadow paging mode for NEM. */
217#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
218#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /**< The first type used by shadow paging. */
219/** @} */
220
221/** Macro for checking if the guest is using paging.
222 * @param uGstType PGM_TYPE_*
223 * @param uShwType PGM_TYPE_*
224 * @remark ASSUMES certain order of the PGM_TYPE_* values.
225 */
226#define PGM_WITH_PAGING(uGstType, uShwType) \
227 ( (uGstType) >= PGM_TYPE_32BIT \
228 && (uShwType) < PGM_TYPE_NESTED_32BIT)
229
230/** Macro for checking if the guest supports the NX bit.
231 * @param uGstType PGM_TYPE_*
232 * @param uShwType PGM_TYPE_*
233 * @remark ASSUMES certain order of the PGM_TYPE_* values.
234 */
235#define PGM_WITH_NX(uGstType, uShwType) \
236 ( (uGstType) >= PGM_TYPE_PAE \
237 && (uShwType) < PGM_TYPE_NESTED_32BIT)
238
239/** Macro for checking for nested or EPT.
240 * @param uType PGM_TYPE_*
241 */
242#define PGM_TYPE_IS_NESTED(uType) \
243 ( (uType) == PGM_TYPE_NESTED_32BIT \
244 || (uType) == PGM_TYPE_NESTED_PAE \
245 || (uType) == PGM_TYPE_NESTED_AMD64)
246
247/** Macro for checking for nested or EPT.
248 * @param uType PGM_TYPE_*
249 */
250#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
251 ( (uType) == PGM_TYPE_NESTED_32BIT \
252 || (uType) == PGM_TYPE_NESTED_PAE \
253 || (uType) == PGM_TYPE_NESTED_AMD64 \
254 || (uType) == PGM_TYPE_EPT)
255
256
257
258/** @def PGM_HCPHYS_2_PTR
259 * Maps a HC physical page pool address to a virtual address.
260 *
261 * @returns VBox status code.
262 * @param pVM The cross context VM structure.
263 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
264 * @param HCPhys The HC physical address to map to a virtual one.
265 * @param ppv Where to store the virtual address. No need to cast
266 * this.
267 *
268 * @remark Use with care as we don't have so much dynamic mapping space in
269 * ring-0 on 32-bit darwin and in RC.
270 * @remark There is no need to assert on the result.
271 */
272#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
273# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
274 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
275#else
276# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
277 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
278#endif
279
280/** @def PGM_GCPHYS_2_PTR_V2
281 * Maps a GC physical page address to a virtual address.
282 *
283 * @returns VBox status code.
284 * @param pVM The cross context VM structure.
285 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
286 * @param GCPhys The GC physical address to map to a virtual one.
287 * @param ppv Where to store the virtual address. No need to cast this.
288 *
289 * @remark Use with care as we don't have so much dynamic mapping space in
290 * ring-0 on 32-bit darwin and in RC.
291 * @remark There is no need to assert on the result.
292 */
293#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
294# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
295 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
296#else
297# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
298 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
299#endif
300
301/** @def PGM_GCPHYS_2_PTR
302 * Maps a GC physical page address to a virtual address.
303 *
304 * @returns VBox status code.
305 * @param pVM The cross context VM structure.
306 * @param GCPhys The GC physical address to map to a virtual one.
307 * @param ppv Where to store the virtual address. No need to cast this.
308 *
309 * @remark Use with care as we don't have so much dynamic mapping space in
310 * ring-0 on 32-bit darwin and in RC.
311 * @remark There is no need to assert on the result.
312 */
313#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
314
315/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
316 * Maps a GC physical page address to a virtual address.
317 *
318 * @returns VBox status code.
319 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
320 * @param GCPhys The GC physical address to map to a virtual one.
321 * @param ppv Where to store the virtual address. No need to cast this.
322 *
323 * @remark Use with care as we don't have so much dynamic mapping space in
324 * ring-0 on 32-bit darwin and in RC.
325 * @remark There is no need to assert on the result.
326 */
327#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
328
329/** @def PGM_GCPHYS_2_PTR_EX
330 * Maps a unaligned GC physical page address to a virtual address.
331 *
332 * @returns VBox status code.
333 * @param pVM The cross context VM structure.
334 * @param GCPhys The GC physical address to map to a virtual one.
335 * @param ppv Where to store the virtual address. No need to cast this.
336 *
337 * @remark Use with care as we don't have so much dynamic mapping space in
338 * ring-0 on 32-bit darwin and in RC.
339 * @remark There is no need to assert on the result.
340 */
341#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
342# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
343 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
344#else
345# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
346 pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
347#endif
348
349/** @def PGM_DYNMAP_UNUSED_HINT
350 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
351 * is no longer used.
352 *
353 * For best effect only apply this to the page that was mapped most recently.
354 *
355 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
356 * @param pvPage The pool page.
357 */
358#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
359# ifdef LOG_ENABLED
360# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
361# else
362# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
363# endif
364#else
365# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
366#endif
367
368/** @def PGM_DYNMAP_UNUSED_HINT_VM
369 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
370 * is no longer used.
371 *
372 * For best effect only apply this to the page that was mapped most recently.
373 *
374 * @param pVM The cross context VM structure.
375 * @param pvPage The pool page.
376 */
377#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
378
379
380/** @def PGM_INVL_PG
381 * Invalidates a page.
382 *
383 * @param pVCpu The cross context virtual CPU structure.
384 * @param GCVirt The virtual address of the page to invalidate.
385 */
386#ifdef IN_RC
387# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((uintptr_t)(GCVirt))
388#elif defined(IN_RING0)
389# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
390#else
391# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
392#endif
393
394/** @def PGM_INVL_PG_ALL_VCPU
395 * Invalidates a page on all VCPUs
396 *
397 * @param pVM The cross context VM structure.
398 * @param GCVirt The virtual address of the page to invalidate.
399 */
400#ifdef IN_RC
401# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((uintptr_t)(GCVirt))
402#elif defined(IN_RING0)
403# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
404#else
405# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
406#endif
407
408/** @def PGM_INVL_BIG_PG
409 * Invalidates a 4MB page directory entry.
410 *
411 * @param pVCpu The cross context virtual CPU structure.
412 * @param GCVirt The virtual address within the page directory to invalidate.
413 */
414#ifdef IN_RC
415# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
416#elif defined(IN_RING0)
417# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
418#else
419# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
420#endif
421
422/** @def PGM_INVL_VCPU_TLBS()
423 * Invalidates the TLBs of the specified VCPU
424 *
425 * @param pVCpu The cross context virtual CPU structure.
426 */
427#ifdef IN_RC
428# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
429#elif defined(IN_RING0)
430# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
431#else
432# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
433#endif
434
435/** @def PGM_INVL_ALL_VCPU_TLBS()
436 * Invalidates the TLBs of all VCPUs
437 *
438 * @param pVM The cross context VM structure.
439 */
440#ifdef IN_RC
441# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
442#elif defined(IN_RING0)
443# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
444#else
445# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
446#endif
447
448
449/** @name Safer Shadow PAE PT/PTE
450 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
451 * present.
452 *
453 * @{
454 */
455#if 1
456/**
457 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
458 * invalid entries for present.
459 * @sa X86PTEPAE.
460 */
461typedef union PGMSHWPTEPAE
462{
463 /** Unsigned integer view */
464 X86PGPAEUINT uCareful;
465 /* Not other views. */
466} PGMSHWPTEPAE;
467
468# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
469# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
470# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
471# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
472# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
473# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
474# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
475# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
476# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
477# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
478# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
479# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
480# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
481# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
482# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
483# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
484
485/**
486 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
487 * invalid entries for present.
488 * @sa X86PTPAE.
489 */
490typedef struct PGMSHWPTPAE
491{
492 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
493} PGMSHWPTPAE;
494
495#else
496typedef X86PTEPAE PGMSHWPTEPAE;
497typedef X86PTPAE PGMSHWPTPAE;
498# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
499# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
500# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
501# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
502# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
503# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
504# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
505# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
506# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
507# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
508# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
509# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
510# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
511# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
512# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
513# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
514
515#endif
516
517/** Pointer to a shadow PAE PTE. */
518typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
519/** Pointer to a const shadow PAE PTE. */
520typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
521
522/** Pointer to a shadow PAE page table. */
523typedef PGMSHWPTPAE *PPGMSHWPTPAE;
524/** Pointer to a const shadow PAE page table. */
525typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
526/** @} */
527
528
529/** Size of the GCPtrConflict array in PGMMAPPING.
530 * @remarks Must be a power of two. */
531#define PGMMAPPING_CONFLICT_MAX 8
532
533/**
534 * Structure for tracking GC Mappings.
535 *
536 * This structure is used by linked list in both GC and HC.
537 */
538typedef struct PGMMAPPING
539{
540 /** Pointer to next entry. */
541 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
542 /** Pointer to next entry. */
543 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
544 /** Pointer to next entry. */
545 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
546 /** Indicate whether this entry is finalized. */
547 bool fFinalized;
548 /** Start Virtual address. */
549 RTGCPTR GCPtr;
550 /** Last Virtual address (inclusive). */
551 RTGCPTR GCPtrLast;
552 /** Range size (bytes). */
553 RTGCPTR cb;
554 /** Pointer to relocation callback function. */
555 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
556 /** User argument to the callback. */
557 R3PTRTYPE(void *) pvUser;
558 /** Mapping description / name. For easing debugging. */
559 R3PTRTYPE(const char *) pszDesc;
560 /** Last 8 addresses that caused conflicts. */
561 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
562 /** Number of conflicts for this hypervisor mapping. */
563 uint32_t cConflicts;
564 /** Number of page tables. */
565 uint32_t cPTs;
566
567 /** Array of page table mapping data. Each entry
568 * describes one page table. The array can be longer
569 * than the declared length.
570 */
571 struct
572 {
573 /** The HC physical address of the page table. */
574 RTHCPHYS HCPhysPT;
575 /** The HC physical address of the first PAE page table. */
576 RTHCPHYS HCPhysPaePT0;
577 /** The HC physical address of the second PAE page table. */
578 RTHCPHYS HCPhysPaePT1;
579 /** The HC virtual address of the 32-bit page table. */
580 R3PTRTYPE(PX86PT) pPTR3;
581 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
582 R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
583 /** The RC virtual address of the 32-bit page table. */
584 RCPTRTYPE(PX86PT) pPTRC;
585 /** The RC virtual address of the two PAE page table. */
586 RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
587 /** The R0 virtual address of the 32-bit page table. */
588 R0PTRTYPE(PX86PT) pPTR0;
589 /** The R0 virtual address of the two PAE page table. */
590 R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
591 } aPTs[1];
592} PGMMAPPING;
593/** Pointer to structure for tracking GC Mappings. */
594typedef struct PGMMAPPING *PPGMMAPPING;
595
596
597/**
598 * Physical page access handler type registration.
599 */
600typedef struct PGMPHYSHANDLERTYPEINT
601{
602 /** Number of references. */
603 uint32_t volatile cRefs;
604 /** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
605 uint32_t u32Magic;
606 /** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
607 RTLISTOFF32NODE ListNode;
608 /** The kind of accesses we're handling. */
609 PGMPHYSHANDLERKIND enmKind;
610 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
611 uint32_t uState;
612 /** Pointer to RC callback function. */
613 RCPTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerRC;
614 /** Pointer to RC callback function for \#PFs. */
615 RCPTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerRC;
616 /** Pointer to R3 callback function. */
617 R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR3;
618 /** Pointer to R0 callback function. */
619 R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandlerR0;
620 /** Pointer to R0 callback function for \#PFs. */
621 R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandlerR0;
622 /** Description / Name. For easing debugging. */
623 R3PTRTYPE(const char *) pszDesc;
624} PGMPHYSHANDLERTYPEINT;
625/** Pointer to a physical access handler type registration. */
626typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
627/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
628#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
629/** Magic value for the physical handler callbacks. */
630#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
631
632/**
633 * Converts a handle to a pointer.
634 * @returns PPGMPHYSHANDLERTYPEINT
635 * @param a_pVM The cross context VM structure.
636 * @param a_hType Physical access handler type handle.
637 */
638#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
639
640
641/**
642 * Physical page access handler structure.
643 *
644 * This is used to keep track of physical address ranges
645 * which are being monitored in some kind of way.
646 */
647typedef struct PGMPHYSHANDLER
648{
649 AVLROGCPHYSNODECORE Core;
650 /** Number of pages to update. */
651 uint32_t cPages;
652 /** Set if we have pages that have been aliased. */
653 uint32_t cAliasedPages;
654 /** Set if we have pages that have temporarily been disabled. */
655 uint32_t cTmpOffPages;
656 /** Registered handler type handle (heap offset). */
657 PGMPHYSHANDLERTYPE hType;
658 /** User argument for RC handlers. */
659 RCPTRTYPE(void *) pvUserRC;
660#if HC_ARCH_BITS == 64
661 RTRCPTR Padding0; /**< Explicit alignment padding. */
662#endif
663 /** User argument for R3 handlers. */
664 R3PTRTYPE(void *) pvUserR3;
665 /** User argument for R0 handlers. */
666 R0PTRTYPE(void *) pvUserR0;
667 /** Description / Name. For easing debugging. */
668 R3PTRTYPE(const char *) pszDesc;
669#ifdef VBOX_WITH_STATISTICS
670 /** Profiling of this handler. */
671 STAMPROFILE Stat;
672#endif
673} PGMPHYSHANDLER;
674/** Pointer to a physical page access handler structure. */
675typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
676
677/**
678 * Gets the type record for a physical handler (no reference added).
679 * @returns PPGMPHYSHANDLERTYPEINT
680 * @param a_pVM The cross context VM structure.
681 * @param a_pPhysHandler Pointer to the physical handler structure
682 * (PGMPHYSHANDLER).
683 */
684#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
685
686
687#ifdef VBOX_WITH_RAW_MODE
688
689/**
690 * Cache node for the physical addresses covered by a virtual handler.
691 */
692typedef struct PGMPHYS2VIRTHANDLER
693{
694 /** Core node for the tree based on physical ranges. */
695 AVLROGCPHYSNODECORE Core;
696 /** Offset from this struct to the PGMVIRTHANDLER structure. */
697 int32_t offVirtHandler;
698 /** Offset of the next alias relative to this one.
699 * Bit 0 is used for indicating whether we're in the tree.
700 * Bit 1 is used for indicating that we're the head node.
701 */
702 int32_t offNextAlias;
703} PGMPHYS2VIRTHANDLER;
704/** Pointer to a phys to virtual handler structure. */
705typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
706
707/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
708 * node is in the tree. */
709# define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
710/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
711 * node is in the head of an alias chain.
712 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
713# define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
714/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
715# define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
716
717
718/**
719 * Virtual page access handler type registration.
720 */
721typedef struct PGMVIRTANDLERTYPEINT
722{
723 /** Number of references. */
724 uint32_t volatile cRefs;
725 /** Magic number (PGMVIRTHANDLERTYPEINT_MAGIC). */
726 uint32_t u32Magic;
727 /** Link of handler types anchored in PGMTREES::HeadVirtHandlerTypes. */
728 RTLISTOFF32NODE ListNode;
729 /** The kind of accesses we're handling. */
730 PGMVIRTHANDLERKIND enmKind;
731 /** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
732 uint32_t uState;
733 /** Whether the pvUserRC argument should be automatically relocated or not. */
734 bool fRelocUserRC;
735 bool afPadding[HC_ARCH_BITS == 64 ? 7 : 3];
736 /** Pointer to RC callback function. */
737 RCPTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerRC;
738 /** Pointer to RC callback function for \#PFs. */
739 RCPTRTYPE(PFNPGMRCVIRTPFHANDLER) pfnPfHandlerRC;
740 /** Pointer to the R3 callback function for invalidation. */
741 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
742 /** Pointer to R3 callback function. */
743 R3PTRTYPE(PFNPGMVIRTHANDLER) pfnHandlerR3;
744 /** Description / Name. For easing debugging. */
745 R3PTRTYPE(const char *) pszDesc;
746} PGMVIRTHANDLERTYPEINT;
747/** Pointer to a virtual access handler type registration. */
748typedef PGMVIRTHANDLERTYPEINT *PPGMVIRTHANDLERTYPEINT;
749/** Magic value for the virtual handler callbacks (Sir Arthur Charles Clarke). */
750# define PGMVIRTHANDLERTYPEINT_MAGIC UINT32_C(0x19171216)
751/** Magic value for the virtual handler callbacks. */
752# define PGMVIRTHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x20080319)
753
754/**
755 * Converts a handle to a pointer.
756 * @returns PPGMVIRTHANDLERTYPEINT
757 * @param a_pVM The cross context VM structure.
758 * @param a_hType Vitual access handler type handle.
759 */
760# define PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMVIRTHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
761
762
763/**
764 * Virtual page access handler structure.
765 *
766 * This is used to keep track of virtual address ranges
767 * which are being monitored in some kind of way.
768 */
769typedef struct PGMVIRTHANDLER
770{
771 /** Core node for the tree based on virtual ranges. */
772 AVLROGCPTRNODECORE Core;
773 /** Size of the range (in bytes). */
774 uint32_t cb;
775 /** Number of cache pages. */
776 uint32_t cPages;
777 /** Registered handler type handle (heap offset). */
778 PGMVIRTHANDLERTYPE hType;
779 /** User argument for RC handlers. */
780 RCPTRTYPE(void *) pvUserRC;
781 /** User argument for R3 handlers. */
782 R3PTRTYPE(void *) pvUserR3;
783 /** Description / Name. For easing debugging. */
784 R3PTRTYPE(const char *) pszDesc;
785# ifdef VBOX_WITH_STATISTICS
786 /** Profiling of this handler. */
787 STAMPROFILE Stat;
788# endif
789 /** Array of cached physical addresses for the monitored ranged. */
790 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
791} PGMVIRTHANDLER;
792/** Pointer to a virtual page access handler structure. */
793typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
794
795/**
796 * Gets the type record for a virtual handler (no reference added).
797 * @returns PPGMVIRTHANDLERTYPEINT
798 * @param a_pVM The cross context VM structure.
799 * @param a_pVirtHandler Pointer to the virtual handler structure
800 * (PGMVIRTHANDLER).
801 */
802# define PGMVIRTANDLER_GET_TYPE(a_pVM, a_pVirtHandler) PGMVIRTHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pVirtHandler)->hType)
803
804#endif /* VBOX_WITH_RAW_MODE */
805
806
807/**
808 * A Physical Guest Page tracking structure.
809 *
810 * The format of this structure is complicated because we have to fit a lot
811 * of information into as few bits as possible. The format is also subject
812 * to change (there is one coming up soon). Which means that for we'll be
813 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
814 * accesses to the structure.
815 */
816typedef union PGMPAGE
817{
818 /** Structured view. */
819 struct
820 {
821 /** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_*). */
822 uint64_t u2HandlerPhysStateY : 2;
823 /** 3:2 - Paging structure needed to map the page
824 * (PGM_PAGE_PDE_TYPE_*). */
825 uint64_t u2PDETypeY : 2;
826 /** 4 - Indicator of dirty page for fault tolerance tracking. */
827 uint64_t fFTDirtyY : 1;
828 /** 5 - Flag indicating that a write monitored page was written to
829 * when set. */
830 uint64_t fWrittenToY : 1;
831 /** 7:6 - Unused. */
832 uint64_t u2Unused0 : 2;
833 /** 9:8 - The physical handler state (PGM_PAGE_HNDL_VIRT_STATE_*). */
834 uint64_t u2HandlerVirtStateY : 2;
835 /** 11:10 - NEM state bits. */
836 uint64_t u2NemStateY : 2;
837 /** 12:48 - The host physical frame number (shift left to get the
838 * address). */
839 uint64_t HCPhysFN : 36;
840 /** 50:48 - The page state. */
841 uint64_t uStateY : 3;
842 /** 51:53 - The page type (PGMPAGETYPE). */
843 uint64_t uTypeY : 3;
844 /** 63:54 - PTE index for usage tracking (page pool). */
845 uint64_t u10PteIdx : 10;
846
847 /** The GMM page ID.
848 * @remarks In the current implementation, MMIO2 and pages aliased to
849 * MMIO2 pages will be exploiting this field to calculate the
850 * ring-3 mapping address corresponding to the page.
851 * Later we may consider including MMIO2 management into GMM. */
852 uint32_t idPage;
853 /** Usage tracking (page pool). */
854 uint16_t u16TrackingY;
855 /** The number of read locks on this page. */
856 uint8_t cReadLocksY;
857 /** The number of write locks on this page. */
858 uint8_t cWriteLocksY;
859 } s;
860
861 /** 64-bit integer view. */
862 uint64_t au64[2];
863 /** 16-bit view. */
864 uint32_t au32[4];
865 /** 16-bit view. */
866 uint16_t au16[8];
867 /** 8-bit view. */
868 uint8_t au8[16];
869} PGMPAGE;
870AssertCompileSize(PGMPAGE, 16);
871/** Pointer to a physical guest page. */
872typedef PGMPAGE *PPGMPAGE;
873/** Pointer to a const physical guest page. */
874typedef const PGMPAGE *PCPGMPAGE;
875/** Pointer to a physical guest page pointer. */
876typedef PPGMPAGE *PPPGMPAGE;
877
878
879/**
880 * Clears the page structure.
881 * @param a_pPage Pointer to the physical guest page tracking structure.
882 */
883#define PGM_PAGE_CLEAR(a_pPage) \
884 do { \
885 (a_pPage)->au64[0] = 0; \
886 (a_pPage)->au64[1] = 0; \
887 } while (0)
888
889/**
890 * Initializes the page structure.
891 * @param a_pPage Pointer to the physical guest page tracking structure.
892 * @param a_HCPhys The host physical address of the page.
893 * @param a_idPage The (GMM) page ID of the page.
894 * @param a_uType The page type (PGMPAGETYPE).
895 * @param a_uState The page state (PGM_PAGE_STATE_XXX).
896 */
897#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
898 do { \
899 RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
900 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
901 (a_pPage)->au64[0] = SetHCPhysTmp; \
902 (a_pPage)->au64[1] = 0; \
903 (a_pPage)->s.idPage = (a_idPage); \
904 (a_pPage)->s.uStateY = (a_uState); \
905 (a_pPage)->s.uTypeY = (a_uType); \
906 } while (0)
907
908/**
909 * Initializes the page structure of a ZERO page.
910 * @param a_pPage Pointer to the physical guest page tracking structure.
911 * @param a_pVM The VM handle (for getting the zero page address).
912 * @param a_uType The page type (PGMPAGETYPE).
913 */
914#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
915 PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
916
917
918/** @name The Page state, PGMPAGE::uStateY.
919 * @{ */
920/** The zero page.
921 * This is a per-VM page that's never ever mapped writable. */
922#define PGM_PAGE_STATE_ZERO 0U
923/** A allocated page.
924 * This is a per-VM page allocated from the page pool (or wherever
925 * we get MMIO2 pages from if the type is MMIO2).
926 */
927#define PGM_PAGE_STATE_ALLOCATED 1U
928/** A allocated page that's being monitored for writes.
929 * The shadow page table mappings are read-only. When a write occurs, the
930 * fWrittenTo member is set, the page remapped as read-write and the state
931 * moved back to allocated. */
932#define PGM_PAGE_STATE_WRITE_MONITORED 2U
933/** The page is shared, aka. copy-on-write.
934 * This is a page that's shared with other VMs. */
935#define PGM_PAGE_STATE_SHARED 3U
936/** The page is ballooned, so no longer available for this VM. */
937#define PGM_PAGE_STATE_BALLOONED 4U
938/** @} */
939
940
941/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
942#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
943# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
944#else
945# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
946#endif
947
948/**
949 * Gets the page state.
950 * @returns page state (PGM_PAGE_STATE_*).
951 * @param a_pPage Pointer to the physical guest page tracking structure.
952 *
953 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
954 * builds.
955 */
956#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
957#if defined(__GNUC__) && defined(VBOX_STRICT)
958# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
959#else
960# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
961#endif
962
963/**
964 * Sets the page state.
965 * @param a_pVM The VM handle, only used for lock ownership assertions.
966 * @param a_pPage Pointer to the physical guest page tracking structure.
967 * @param a_uState The new page state.
968 */
969#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
970 do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
971
972
973/**
974 * Gets the host physical address of the guest page.
975 * @returns host physical address (RTHCPHYS).
976 * @param a_pPage Pointer to the physical guest page tracking structure.
977 *
978 * @remarks In strict builds on gcc platforms, this macro will make some ugly
979 * assumption about a valid pVM variable/parameter being in the
980 * current context. It will use this pVM variable to assert that the
981 * PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
982 * pVM is not around.
983 */
984#if 0
985# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
986# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
987#else
988# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
989# if defined(__GNUC__) && defined(VBOX_STRICT)
990# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
991# else
992# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
993# endif
994#endif
995
996/**
997 * Sets the host physical address of the guest page.
998 *
999 * @param a_pVM The VM handle, only used for lock ownership assertions.
1000 * @param a_pPage Pointer to the physical guest page tracking structure.
1001 * @param a_HCPhys The new host physical address.
1002 */
1003#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
1004 do { \
1005 RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
1006 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
1007 (a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
1008 PGM_PAGE_ASSERT_LOCK(a_pVM); \
1009 } while (0)
1010
1011/**
1012 * Get the Page ID.
1013 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
1014 * @param a_pPage Pointer to the physical guest page tracking structure.
1015 */
1016#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
1017
1018/**
1019 * Sets the Page ID.
1020 * @param a_pVM The VM handle, only used for lock ownership assertions.
1021 * @param a_pPage Pointer to the physical guest page tracking structure.
1022 * @param a_idPage The new page ID.
1023 */
1024#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
1025 do { \
1026 (a_pPage)->s.idPage = (a_idPage); \
1027 PGM_PAGE_ASSERT_LOCK(a_pVM); \
1028 } while (0)
1029
1030/**
1031 * Get the Chunk ID.
1032 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
1033 * @param a_pPage Pointer to the physical guest page tracking structure.
1034 */
1035#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
1036
1037/**
1038 * Get the index of the page within the allocation chunk.
1039 * @returns The page index.
1040 * @param a_pPage Pointer to the physical guest page tracking structure.
1041 */
1042#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
1043
1044/**
1045 * Gets the page type.
1046 * @returns The page type.
1047 * @param a_pPage Pointer to the physical guest page tracking structure.
1048 *
1049 * @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
1050 * builds.
1051 */
1052#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
1053#if defined(__GNUC__) && defined(VBOX_STRICT)
1054# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
1055#else
1056# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
1057#endif
1058
1059/**
1060 * Sets the page type.
1061 *
1062 * @param a_pVM The VM handle, only used for lock ownership assertions.
1063 * @param a_pPage Pointer to the physical guest page tracking structure.
1064 * @param a_enmType The new page type (PGMPAGETYPE).
1065 */
1066#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
1067 do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1068
1069/**
1070 * Gets the page table index
1071 * @returns The page table index.
1072 * @param a_pPage Pointer to the physical guest page tracking structure.
1073 */
1074#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
1075
1076/**
1077 * Sets the page table index.
1078 * @param a_pVM The VM handle, only used for lock ownership assertions.
1079 * @param a_pPage Pointer to the physical guest page tracking structure.
1080 * @param a_iPte New page table index.
1081 */
1082#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
1083 do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1084
1085/**
1086 * Checks if the page is marked for MMIO, no MMIO2 aliasing.
1087 * @returns true/false.
1088 * @param a_pPage Pointer to the physical guest page tracking structure.
1089 */
1090#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
1091
1092/**
1093 * Checks if the page is marked for MMIO, including both aliases.
1094 * @returns true/false.
1095 * @param a_pPage Pointer to the physical guest page tracking structure.
1096 */
1097#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1098 || (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
1099 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
1100 )
1101
1102/**
1103 * Checks if the page is marked for MMIO, including special aliases.
1104 * @returns true/false.
1105 * @param a_pPage Pointer to the physical guest page tracking structure.
1106 */
1107#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1108 || (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1109
1110/**
1111 * Checks if the page is a special aliased MMIO page.
1112 * @returns true/false.
1113 * @param a_pPage Pointer to the physical guest page tracking structure.
1114 */
1115#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1116
1117/**
1118 * Checks if the page is backed by the ZERO page.
1119 * @returns true/false.
1120 * @param a_pPage Pointer to the physical guest page tracking structure.
1121 */
1122#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
1123
1124/**
1125 * Checks if the page is backed by a SHARED page.
1126 * @returns true/false.
1127 * @param a_pPage Pointer to the physical guest page tracking structure.
1128 */
1129#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
1130
1131/**
1132 * Checks if the page is ballooned.
1133 * @returns true/false.
1134 * @param a_pPage Pointer to the physical guest page tracking structure.
1135 */
1136#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
1137
1138/**
1139 * Checks if the page is allocated.
1140 * @returns true/false.
1141 * @param a_pPage Pointer to the physical guest page tracking structure.
1142 */
1143#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1144
1145/**
1146 * Marks the page as written to (for GMM change monitoring).
1147 * @param a_pVM The VM handle, only used for lock ownership assertions.
1148 * @param a_pPage Pointer to the physical guest page tracking structure.
1149 */
1150#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1151 do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1152
1153/**
1154 * Clears the written-to indicator.
1155 * @param a_pVM The VM handle, only used for lock ownership assertions.
1156 * @param a_pPage Pointer to the physical guest page tracking structure.
1157 */
1158#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1159 do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1160
1161/**
1162 * Checks if the page was marked as written-to.
1163 * @returns true/false.
1164 * @param a_pPage Pointer to the physical guest page tracking structure.
1165 */
1166#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1167
1168/**
1169 * Marks the page as dirty for FTM
1170 * @param a_pPage Pointer to the physical guest page tracking structure.
1171 */
1172#define PGM_PAGE_SET_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 1; } while (0)
1173
1174/**
1175 * Clears the FTM dirty indicator
1176 * @param a_pPage Pointer to the physical guest page tracking structure.
1177 */
1178#define PGM_PAGE_CLEAR_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 0; } while (0)
1179
1180/**
1181 * Checks if the page was marked as dirty for FTM
1182 * @returns true/false.
1183 * @param a_pPage Pointer to the physical guest page tracking structure.
1184 */
1185#define PGM_PAGE_IS_FT_DIRTY(a_pPage) ( (a_pPage)->s.fFTDirtyY )
1186
1187
1188/** @name PT usage values (PGMPAGE::u2PDEType).
1189 *
1190 * @{ */
1191/** Either as a PT or PDE. */
1192#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1193/** Must use a page table to map the range. */
1194#define PGM_PAGE_PDE_TYPE_PT 1
1195/** Can use a page directory entry to map the continuous range. */
1196#define PGM_PAGE_PDE_TYPE_PDE 2
1197/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1198#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1199/** @} */
1200
1201/**
1202 * Set the PDE type of the page
1203 * @param a_pVM The VM handle, only used for lock ownership assertions.
1204 * @param a_pPage Pointer to the physical guest page tracking structure.
1205 * @param a_uType PGM_PAGE_PDE_TYPE_*.
1206 */
1207#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1208 do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1209
1210/**
1211 * Checks if the page was marked being part of a large page
1212 * @returns true/false.
1213 * @param a_pPage Pointer to the physical guest page tracking structure.
1214 */
1215#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1216
1217/** Enabled optimized access handler tests.
1218 * These optimizations makes ASSUMPTIONS about the state values and the s1
1219 * layout. When enabled, the compiler should normally generate more compact
1220 * code.
1221 */
1222#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1223
1224/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1225 *
1226 * @remarks The values are assigned in order of priority, so we can calculate
1227 * the correct state for a page with different handlers installed.
1228 * @{ */
1229/** No handler installed. */
1230#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1231/** Monitoring is temporarily disabled. */
1232#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1233/** Write access is monitored. */
1234#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1235/** All access is monitored. */
1236#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1237/** @} */
1238
1239/**
1240 * Gets the physical access handler state of a page.
1241 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1242 * @param a_pPage Pointer to the physical guest page tracking structure.
1243 */
1244#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1245
1246/**
1247 * Sets the physical access handler state of a page.
1248 * @param a_pPage Pointer to the physical guest page tracking structure.
1249 * @param a_uState The new state value.
1250 */
1251#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1252 do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1253
1254/**
1255 * Checks if the page has any physical access handlers, including temporarily disabled ones.
1256 * @returns true/false
1257 * @param a_pPage Pointer to the physical guest page tracking structure.
1258 */
1259#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1260 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1261
1262/**
1263 * Checks if the page has any active physical access handlers.
1264 * @returns true/false
1265 * @param a_pPage Pointer to the physical guest page tracking structure.
1266 */
1267#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1268 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1269
1270
1271/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1272 *
1273 * @remarks The values are assigned in order of priority, so we can calculate
1274 * the correct state for a page with different handlers installed.
1275 * @{ */
1276/** No handler installed. */
1277#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1278/* 1 is reserved so the lineup is identical with the physical ones. */
1279/** Write access is monitored. */
1280#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1281/** All access is monitored. */
1282#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1283/** @} */
1284
1285/**
1286 * Gets the virtual access handler state of a page.
1287 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1288 * @param a_pPage Pointer to the physical guest page tracking structure.
1289 */
1290#define PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) ( (a_pPage)->s.u2HandlerVirtStateY )
1291
1292/**
1293 * Sets the virtual access handler state of a page.
1294 * @param a_pPage Pointer to the physical guest page tracking structure.
1295 * @param a_uState The new state value.
1296 */
1297#define PGM_PAGE_SET_HNDL_VIRT_STATE(a_pPage, a_uState) \
1298 do { (a_pPage)->s.u2HandlerVirtStateY = (a_uState); } while (0)
1299
1300/**
1301 * Checks if the page has any virtual access handlers.
1302 * @returns true/false
1303 * @param a_pPage Pointer to the physical guest page tracking structure.
1304 */
1305#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage) \
1306 ( PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1307
1308/**
1309 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1310 * virtual handlers.
1311 * @returns true/false
1312 * @param a_pPage Pointer to the physical guest page tracking structure.
1313 */
1314#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
1315 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage)
1316
1317
1318/**
1319 * Checks if the page has any access handlers, including temporarily disabled ones.
1320 * @returns true/false
1321 * @param a_pPage Pointer to the physical guest page tracking structure.
1322 */
1323#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1324# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1325 ( ((a_pPage)->au32[0] & UINT16_C(0x0303)) != 0 )
1326#else
1327# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1328 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1329 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1330#endif
1331
1332/**
1333 * Checks if the page has any active access handlers.
1334 * @returns true/false
1335 * @param a_pPage Pointer to the physical guest page tracking structure.
1336 */
1337#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1338# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1339 ( ((a_pPage)->au32[0] & UINT16_C(0x0202)) != 0 )
1340#else
1341# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1342 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1343 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1344#endif
1345
1346/**
1347 * Checks if the page has any active access handlers catching all accesses.
1348 * @returns true/false
1349 * @param a_pPage Pointer to the physical guest page tracking structure.
1350 */
1351#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1352# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1353 ( ( ((a_pPage)->au8[0] | (a_pPage)->au8[1]) & UINT8_C(0x3) ) \
1354 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1355#else
1356# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1357 ( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1358 || PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1359#endif
1360
1361
1362/** @def PGM_PAGE_GET_TRACKING
1363 * Gets the packed shadow page pool tracking data associated with a guest page.
1364 * @returns uint16_t containing the data.
1365 * @param a_pPage Pointer to the physical guest page tracking structure.
1366 */
1367#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1368#if defined(__GNUC__) && defined(VBOX_STRICT)
1369# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1370#else
1371# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1372#endif
1373
1374/** @def PGM_PAGE_SET_TRACKING
1375 * Sets the packed shadow page pool tracking data associated with a guest page.
1376 * @param a_pVM The VM handle, only used for lock ownership assertions.
1377 * @param a_pPage Pointer to the physical guest page tracking structure.
1378 * @param a_u16TrackingData The tracking data to store.
1379 */
1380#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1381 do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1382
1383/** @def PGM_PAGE_GET_TD_CREFS
1384 * Gets the @a cRefs tracking data member.
1385 * @returns cRefs.
1386 * @param a_pPage Pointer to the physical guest page tracking structure.
1387 */
1388#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1389 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1390#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1391 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1392
1393/** @def PGM_PAGE_GET_TD_IDX
1394 * Gets the @a idx tracking data member.
1395 * @returns idx.
1396 * @param a_pPage Pointer to the physical guest page tracking structure.
1397 */
1398#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1399 ((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1400#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1401 ((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1402
1403
1404/** Max number of locks on a page. */
1405#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1406
1407/** Get the read lock count.
1408 * @returns count.
1409 * @param a_pPage Pointer to the physical guest page tracking structure.
1410 */
1411#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1412
1413/** Get the write lock count.
1414 * @returns count.
1415 * @param a_pPage Pointer to the physical guest page tracking structure.
1416 */
1417#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1418
1419/** Decrement the read lock counter.
1420 * @param a_pPage Pointer to the physical guest page tracking structure.
1421 */
1422#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1423
1424/** Decrement the write lock counter.
1425 * @param a_pPage Pointer to the physical guest page tracking structure.
1426 */
1427#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1428
1429/** Increment the read lock counter.
1430 * @param a_pPage Pointer to the physical guest page tracking structure.
1431 */
1432#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1433
1434/** Increment the write lock counter.
1435 * @param a_pPage Pointer to the physical guest page tracking structure.
1436 */
1437#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1438
1439
1440/** Gets the NEM state.
1441 * @returns NEM state value (two bits).
1442 * @param a_pPage Pointer to the physical guest page tracking structure.
1443 */
1444#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1445
1446/** Sets the NEM state.
1447 * @param a_pPage Pointer to the physical guest page tracking structure.
1448 * @param a_u2State The NEM state value (specific to NEM impl.).
1449 */
1450#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1451 do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1452
1453
1454#if 0
1455/** Enables sanity checking of write monitoring using CRC-32. */
1456# define PGMLIVESAVERAMPAGE_WITH_CRC32
1457#endif
1458
1459/**
1460 * Per page live save tracking data.
1461 */
1462typedef struct PGMLIVESAVERAMPAGE
1463{
1464 /** Number of times it has been dirtied. */
1465 uint32_t cDirtied : 24;
1466 /** Whether it is currently dirty. */
1467 uint32_t fDirty : 1;
1468 /** Ignore the page.
1469 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1470 * deal with these after pausing the VM and DevPCI have said it bit about
1471 * remappings. */
1472 uint32_t fIgnore : 1;
1473 /** Was a ZERO page last time around. */
1474 uint32_t fZero : 1;
1475 /** Was a SHARED page last time around. */
1476 uint32_t fShared : 1;
1477 /** Whether the page is/was write monitored in a previous pass. */
1478 uint32_t fWriteMonitored : 1;
1479 /** Whether the page is/was write monitored earlier in this pass. */
1480 uint32_t fWriteMonitoredJustNow : 1;
1481 /** Bits reserved for future use. */
1482 uint32_t u2Reserved : 2;
1483#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1484 /** CRC-32 for the page. This is for internal consistency checks. */
1485 uint32_t u32Crc;
1486#endif
1487} PGMLIVESAVERAMPAGE;
1488#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1489AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1490#else
1491AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1492#endif
1493/** Pointer to the per page live save tracking data. */
1494typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1495
1496/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1497#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1498
1499
1500/**
1501 * RAM range for GC Phys to HC Phys conversion.
1502 *
1503 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1504 * conversions too, but we'll let MM handle that for now.
1505 *
1506 * This structure is used by linked lists in both GC and HC.
1507 */
1508typedef struct PGMRAMRANGE
1509{
1510 /** Start of the range. Page aligned. */
1511 RTGCPHYS GCPhys;
1512 /** Size of the range. (Page aligned of course). */
1513 RTGCPHYS cb;
1514 /** Pointer to the next RAM range - for R3. */
1515 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1516 /** Pointer to the next RAM range - for R0. */
1517 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1518 /** Pointer to the next RAM range - for RC. */
1519 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1520 /** PGM_RAM_RANGE_FLAGS_* flags. */
1521 uint32_t fFlags;
1522 /** Last address in the range (inclusive). Page aligned (-1). */
1523 RTGCPHYS GCPhysLast;
1524 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1525 R3PTRTYPE(void *) pvR3;
1526 /** Live save per page tracking data. */
1527 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1528 /** The range description. */
1529 R3PTRTYPE(const char *) pszDesc;
1530 /** Pointer to self - R0 pointer. */
1531 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1532 /** Pointer to self - RC pointer. */
1533 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1534
1535 /** Alignment padding. */
1536 RTRCPTR Alignment0;
1537 /** Pointer to the left search three node - ring-3 context. */
1538 R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1539 /** Pointer to the right search three node - ring-3 context. */
1540 R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1541 /** Pointer to the left search three node - ring-0 context. */
1542 R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1543 /** Pointer to the right search three node - ring-0 context. */
1544 R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1545 /** Pointer to the left search three node - raw-mode context. */
1546 RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1547 /** Pointer to the right search three node - raw-mode context. */
1548 RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1549
1550 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1551#if HC_ARCH_BITS == 32
1552 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1553#endif
1554 /** Array of physical guest page tracking structures. */
1555 PGMPAGE aPages[1];
1556} PGMRAMRANGE;
1557/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1558typedef PGMRAMRANGE *PPGMRAMRANGE;
1559
1560/** @name PGMRAMRANGE::fFlags
1561 * @{ */
1562/** The RAM range is floating around as an independent guest mapping. */
1563#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1564/** Ad hoc RAM range for an ROM mapping. */
1565#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1566/** Ad hoc RAM range for an MMIO mapping. */
1567#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1568/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1569#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1570/** @} */
1571
1572/** Tests if a RAM range is an ad hoc one or not.
1573 * @returns true/false.
1574 * @param pRam The RAM range.
1575 */
1576#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1577 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1578
1579/** The number of entries in the RAM range TLBs (there is one for each
1580 * context). Must be a power of two. */
1581#define PGM_RAMRANGE_TLB_ENTRIES 8
1582
1583/**
1584 * Calculates the RAM range TLB index for the physical address.
1585 *
1586 * @returns RAM range TLB index.
1587 * @param a_GCPhys The guest physical address.
1588 */
1589#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1590
1591
1592
1593/**
1594 * Per page tracking structure for ROM image.
1595 *
1596 * A ROM image may have a shadow page, in which case we may have two pages
1597 * backing it. This structure contains the PGMPAGE for both while
1598 * PGMRAMRANGE have a copy of the active one. It is important that these
1599 * aren't out of sync in any regard other than page pool tracking data.
1600 */
1601typedef struct PGMROMPAGE
1602{
1603 /** The page structure for the virgin ROM page. */
1604 PGMPAGE Virgin;
1605 /** The page structure for the shadow RAM page. */
1606 PGMPAGE Shadow;
1607 /** The current protection setting. */
1608 PGMROMPROT enmProt;
1609 /** Live save status information. Makes use of unused alignment space. */
1610 struct
1611 {
1612 /** The previous protection value. */
1613 uint8_t u8Prot;
1614 /** Written to flag set by the handler. */
1615 bool fWrittenTo;
1616 /** Whether the shadow page is dirty or not. */
1617 bool fDirty;
1618 /** Whether it was dirtied in the recently. */
1619 bool fDirtiedRecently;
1620 } LiveSave;
1621} PGMROMPAGE;
1622AssertCompileSizeAlignment(PGMROMPAGE, 8);
1623/** Pointer to a ROM page tracking structure. */
1624typedef PGMROMPAGE *PPGMROMPAGE;
1625
1626
1627/**
1628 * A registered ROM image.
1629 *
1630 * This is needed to keep track of ROM image since they generally intrude
1631 * into a PGMRAMRANGE. It also keeps track of additional info like the
1632 * two page sets (read-only virgin and read-write shadow), the current
1633 * state of each page.
1634 *
1635 * Because access handlers cannot easily be executed in a different
1636 * context, the ROM ranges needs to be accessible and in all contexts.
1637 */
1638typedef struct PGMROMRANGE
1639{
1640 /** Pointer to the next range - R3. */
1641 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1642 /** Pointer to the next range - R0. */
1643 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1644 /** Pointer to the next range - RC. */
1645 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1646 /** Pointer alignment */
1647 RTRCPTR RCPtrAlignment;
1648 /** Address of the range. */
1649 RTGCPHYS GCPhys;
1650 /** Address of the last byte in the range. */
1651 RTGCPHYS GCPhysLast;
1652 /** Size of the range. */
1653 RTGCPHYS cb;
1654 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1655 uint32_t fFlags;
1656 /** The saved state range ID. */
1657 uint8_t idSavedState;
1658 /** Alignment padding. */
1659 uint8_t au8Alignment[3];
1660 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1661 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1662 /** The size bits pvOriginal points to. */
1663 uint32_t cbOriginal;
1664 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1665 * This is used for strictness checks. */
1666 R3PTRTYPE(const void *) pvOriginal;
1667 /** The ROM description. */
1668 R3PTRTYPE(const char *) pszDesc;
1669 /** The per page tracking structures. */
1670 PGMROMPAGE aPages[1];
1671} PGMROMRANGE;
1672/** Pointer to a ROM range. */
1673typedef PGMROMRANGE *PPGMROMRANGE;
1674
1675
1676/**
1677 * Live save per page data for an MMIO2 page.
1678 *
1679 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1680 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1681 * CRC-32 for detecting changes as well as special handling of zero pages. This
1682 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1683 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1684 * because of speed (2.5x and 6x slower).)
1685 *
1686 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1687 * save but normally is disabled. Since we can write monitor guest
1688 * accesses on our own, we only need this for host accesses. Shouldn't be
1689 * too difficult for DevVGA, VMMDev might be doable, the planned
1690 * networking fun will be fun since it involves ring-0.
1691 */
1692typedef struct PGMLIVESAVEMMIO2PAGE
1693{
1694 /** Set if the page is considered dirty. */
1695 bool fDirty;
1696 /** The number of scans this page has remained unchanged for.
1697 * Only updated for dirty pages. */
1698 uint8_t cUnchangedScans;
1699 /** Whether this page was zero at the last scan. */
1700 bool fZero;
1701 /** Alignment padding. */
1702 bool fReserved;
1703 /** CRC-32 for the first half of the page.
1704 * This is used together with u32CrcH2 to quickly detect changes in the page
1705 * during the non-final passes. */
1706 uint32_t u32CrcH1;
1707 /** CRC-32 for the second half of the page. */
1708 uint32_t u32CrcH2;
1709 /** SHA-1 for the saved page.
1710 * This is used in the final pass to skip pages without changes. */
1711 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1712} PGMLIVESAVEMMIO2PAGE;
1713/** Pointer to a live save status data for an MMIO2 page. */
1714typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1715
1716/**
1717 * A registered MMIO2 (= Device RAM) or pre-registered MMIO range.
1718 *
1719 * There are a few reason why we need to keep track of these registrations. One
1720 * of them is the deregistration & cleanup stuff, while another is that the
1721 * PGMRAMRANGE associated with such a region may have to be removed from the ram
1722 * range list.
1723 *
1724 * Overlapping with a RAM range has to be 100% or none at all. The pages in the
1725 * existing RAM range must not be ROM nor MMIO. A guru meditation will be
1726 * raised if a partial overlap or an overlap of ROM pages is encountered. On an
1727 * overlap we will free all the existing RAM pages and put in the ram range
1728 * pages instead.
1729 */
1730typedef struct PGMREGMMIORANGE
1731{
1732 /** The owner of the range. (a device) */
1733 PPDMDEVINSR3 pDevInsR3;
1734 /** Pointer to the ring-3 mapping of the allocation, if MMIO2. */
1735 RTR3PTR pvR3;
1736 /** Pointer to the next range - R3. */
1737 R3PTRTYPE(struct PGMREGMMIORANGE *) pNextR3;
1738 /** Flags (PGMREGMMIORANGE_F_XXX). */
1739 uint16_t fFlags;
1740 /** The sub device number (internal PCI config (CFGM) number). */
1741 uint8_t iSubDev;
1742 /** The PCI region number. */
1743 uint8_t iRegion;
1744 /** The saved state range ID. */
1745 uint8_t idSavedState;
1746 /** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1747 uint8_t idMmio2;
1748 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1749 uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1750 /** The real size.
1751 * This may be larger than indicated by RamRange.cb if the range has been
1752 * reduced during saved state loading. */
1753 RTGCPHYS cbReal;
1754 /** Pointer to the physical handler for MMIO. */
1755 R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1756 /** Live save per page tracking data for MMIO2. */
1757 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1758 /** The associated RAM range. */
1759 PGMRAMRANGE RamRange;
1760} PGMREGMMIORANGE;
1761AssertCompileMemberAlignment(PGMREGMMIORANGE, RamRange, 16);
1762/** Pointer to a MMIO2 or pre-registered MMIO range. */
1763typedef PGMREGMMIORANGE *PPGMREGMMIORANGE;
1764
1765/** @name PGMREGMMIORANGE_F_XXX - Registered MMIO range flags.
1766 * @{ */
1767/** Set if it's an MMIO2 range. */
1768#define PGMREGMMIORANGE_F_MMIO2 UINT16_C(0x0001)
1769/** Set if this is the first chunk in the MMIO2 range. */
1770#define PGMREGMMIORANGE_F_FIRST_CHUNK UINT16_C(0x0002)
1771/** Set if this is the last chunk in the MMIO2 range. */
1772#define PGMREGMMIORANGE_F_LAST_CHUNK UINT16_C(0x0004)
1773/** Set if the whole range is mapped. */
1774#define PGMREGMMIORANGE_F_MAPPED UINT16_C(0x0008)
1775/** Set if it's overlapping, clear if not. */
1776#define PGMREGMMIORANGE_F_OVERLAPPING UINT16_C(0x0010)
1777/** @} */
1778
1779
1780/** @name Internal MMIO2 constants.
1781 * @{ */
1782/** The maximum number of MMIO2 ranges. */
1783#define PGM_MMIO2_MAX_RANGES 8
1784/** The maximum number of pages in a MMIO2 range. */
1785#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1786/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1787#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) | (uint32_t)(a_iPage) )
1788/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1789#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1790/** Gets the MMIO2 page index from an MMIO2 page ID. */
1791#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1792/** @} */
1793
1794
1795
1796/**
1797 * PGMPhysRead/Write cache entry
1798 */
1799typedef struct PGMPHYSCACHEENTRY
1800{
1801 /** R3 pointer to physical page. */
1802 R3PTRTYPE(uint8_t *) pbR3;
1803 /** GC Physical address for cache entry */
1804 RTGCPHYS GCPhys;
1805#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1806 RTGCPHYS u32Padding0; /**< alignment padding. */
1807#endif
1808} PGMPHYSCACHEENTRY;
1809
1810/**
1811 * PGMPhysRead/Write cache to reduce REM memory access overhead
1812 */
1813typedef struct PGMPHYSCACHE
1814{
1815 /** Bitmap of valid cache entries */
1816 uint64_t aEntries;
1817 /** Cache entries */
1818 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1819} PGMPHYSCACHE;
1820
1821
1822/** Pointer to an allocation chunk ring-3 mapping. */
1823typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1824/** Pointer to an allocation chunk ring-3 mapping pointer. */
1825typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1826
1827/**
1828 * Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1829 *
1830 * The primary tree (Core) uses the chunk id as key.
1831 */
1832typedef struct PGMCHUNKR3MAP
1833{
1834 /** The key is the chunk id. */
1835 AVLU32NODECORE Core;
1836 /** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1837 * selection. */
1838 uint32_t iLastUsed;
1839 /** The current reference count. */
1840 uint32_t volatile cRefs;
1841 /** The current permanent reference count. */
1842 uint32_t volatile cPermRefs;
1843 /** The mapping address. */
1844 void *pv;
1845} PGMCHUNKR3MAP;
1846
1847/**
1848 * Allocation chunk ring-3 mapping TLB entry.
1849 */
1850typedef struct PGMCHUNKR3MAPTLBE
1851{
1852 /** The chunk id. */
1853 uint32_t volatile idChunk;
1854#if HC_ARCH_BITS == 64
1855 uint32_t u32Padding; /**< alignment padding. */
1856#endif
1857 /** The chunk map. */
1858#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1859 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1860#else
1861 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1862#endif
1863} PGMCHUNKR3MAPTLBE;
1864/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1865typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1866
1867/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1868 * @remark Must be a power of two value. */
1869#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1870
1871/**
1872 * Allocation chunk ring-3 mapping TLB.
1873 *
1874 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1875 * At first glance this might look kinda odd since AVL trees are
1876 * supposed to give the most optimal lookup times of all trees
1877 * due to their balancing. However, take a tree with 1023 nodes
1878 * in it, that's 10 levels, meaning that most searches has to go
1879 * down 9 levels before they find what they want. This isn't fast
1880 * compared to a TLB hit. There is the factor of cache misses,
1881 * and of course the problem with trees and branch prediction.
1882 * This is why we use TLBs in front of most of the trees.
1883 *
1884 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1885 * difficult when we switch to the new inlined AVL trees (from kStuff).
1886 */
1887typedef struct PGMCHUNKR3MAPTLB
1888{
1889 /** The TLB entries. */
1890 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1891} PGMCHUNKR3MAPTLB;
1892
1893/**
1894 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1895 * @returns Chunk TLB index.
1896 * @param idChunk The Chunk ID.
1897 */
1898#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1899
1900
1901/**
1902 * Ring-3 guest page mapping TLB entry.
1903 * @remarks used in ring-0 as well at the moment.
1904 */
1905typedef struct PGMPAGER3MAPTLBE
1906{
1907 /** Address of the page. */
1908 RTGCPHYS volatile GCPhys;
1909 /** The guest page. */
1910#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1911 R3PTRTYPE(PPGMPAGE) volatile pPage;
1912#else
1913 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1914#endif
1915 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1916#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1917 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1918#else
1919 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1920#endif
1921 /** The address */
1922#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1923 R3PTRTYPE(void *) volatile pv;
1924#else
1925 R3R0PTRTYPE(void *) volatile pv;
1926#endif
1927#if HC_ARCH_BITS == 32
1928 uint32_t u32Padding; /**< alignment padding. */
1929#endif
1930} PGMPAGER3MAPTLBE;
1931/** Pointer to an entry in the HC physical TLB. */
1932typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1933
1934
1935/** The number of entries in the ring-3 guest page mapping TLB.
1936 * @remarks The value must be a power of two. */
1937#define PGM_PAGER3MAPTLB_ENTRIES 256
1938
1939/**
1940 * Ring-3 guest page mapping TLB.
1941 * @remarks used in ring-0 as well at the moment.
1942 */
1943typedef struct PGMPAGER3MAPTLB
1944{
1945 /** The TLB entries. */
1946 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1947} PGMPAGER3MAPTLB;
1948/** Pointer to the ring-3 guest page mapping TLB. */
1949typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1950
1951/**
1952 * Calculates the index of the TLB entry for the specified guest page.
1953 * @returns Physical TLB index.
1954 * @param GCPhys The guest physical address.
1955 */
1956#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1957
1958
1959/**
1960 * Raw-mode context dynamic mapping cache entry.
1961 *
1962 * Because of raw-mode context being reloctable and all relocations are applied
1963 * in ring-3, this has to be defined here and be RC specific.
1964 *
1965 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1966 */
1967typedef struct PGMRCDYNMAPENTRY
1968{
1969 /** The physical address of the currently mapped page.
1970 * This is duplicate for three reasons: cache locality, cache policy of the PT
1971 * mappings and sanity checks. */
1972 RTHCPHYS HCPhys;
1973 /** Pointer to the page. */
1974 RTRCPTR pvPage;
1975 /** The number of references. */
1976 int32_t volatile cRefs;
1977 /** PTE pointer union. */
1978 struct PGMRCDYNMAPENTRY_PPTE
1979 {
1980 /** PTE pointer, 32-bit legacy version. */
1981 RCPTRTYPE(PX86PTE) pLegacy;
1982 /** PTE pointer, PAE version. */
1983 RCPTRTYPE(PX86PTEPAE) pPae;
1984 } uPte;
1985} PGMRCDYNMAPENTRY;
1986/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1987typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1988
1989
1990/**
1991 * Dynamic mapping cache for the raw-mode context.
1992 *
1993 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1994 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1995 * so that we can perform relocations from PGMR3Relocate. This has the
1996 * consequence that we must have separate ring-0 and raw-mode context versions
1997 * of this struct even if they share the basic elements.
1998 *
1999 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
2000 */
2001typedef struct PGMRCDYNMAP
2002{
2003 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
2004 uint32_t u32Magic;
2005 /** Array for tracking and managing the pages. */
2006 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
2007 /** The cache size given as a number of pages. */
2008 uint32_t cPages;
2009 /** The current load.
2010 * This does not include guard pages. */
2011 uint32_t cLoad;
2012 /** The max load ever.
2013 * This is maintained to get trigger adding of more mapping space. */
2014 uint32_t cMaxLoad;
2015 /** The number of guard pages. */
2016 uint32_t cGuardPages;
2017 /** The number of users (protected by hInitLock). */
2018 uint32_t cUsers;
2019} PGMRCDYNMAP;
2020/** Pointer to the dynamic cache for the raw-mode context. */
2021typedef PGMRCDYNMAP *PPGMRCDYNMAP;
2022
2023
2024/**
2025 * Mapping cache usage set entry.
2026 *
2027 * @remarks 16-bit ints was chosen as the set is not expected to be used beyond
2028 * the dynamic ring-0 and (to some extent) raw-mode context mapping
2029 * cache. If it's extended to include ring-3, well, then something
2030 * will have be changed here...
2031 */
2032typedef struct PGMMAPSETENTRY
2033{
2034 /** Pointer to the page. */
2035#ifndef IN_RC
2036 RTR0PTR pvPage;
2037#else
2038 RTRCPTR pvPage;
2039# if HC_ARCH_BITS == 64
2040 uint32_t u32Alignment2;
2041# endif
2042#endif
2043 /** The mapping cache index. */
2044 uint16_t iPage;
2045 /** The number of references.
2046 * The max is UINT16_MAX - 1. */
2047 uint16_t cRefs;
2048 /** The number inlined references.
2049 * The max is UINT16_MAX - 1. */
2050 uint16_t cInlinedRefs;
2051 /** Unreferences. */
2052 uint16_t cUnrefs;
2053
2054#if HC_ARCH_BITS == 32
2055 uint32_t u32Alignment1;
2056#endif
2057 /** The physical address for this entry. */
2058 RTHCPHYS HCPhys;
2059} PGMMAPSETENTRY;
2060AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
2061AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
2062/** Pointer to a mapping cache usage set entry. */
2063typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
2064
2065/**
2066 * Mapping cache usage set.
2067 *
2068 * This is used in ring-0 and the raw-mode context to track dynamic mappings
2069 * done during exits / traps. The set is
2070 */
2071typedef struct PGMMAPSET
2072{
2073 /** The number of occupied entries.
2074 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
2075 * dynamic mappings. */
2076 uint32_t cEntries;
2077 /** The start of the current subset.
2078 * This is UINT32_MAX if no subset is currently open. */
2079 uint32_t iSubset;
2080 /** The index of the current CPU, only valid if the set is open. */
2081 int32_t iCpu;
2082 uint32_t alignment;
2083 /** The entries. */
2084 PGMMAPSETENTRY aEntries[64];
2085 /** HCPhys -> iEntry fast lookup table.
2086 * Use PGMMAPSET_HASH for hashing.
2087 * The entries may or may not be valid, check against cEntries. */
2088 uint8_t aiHashTable[128];
2089} PGMMAPSET;
2090AssertCompileSizeAlignment(PGMMAPSET, 8);
2091/** Pointer to the mapping cache set. */
2092typedef PGMMAPSET *PPGMMAPSET;
2093
2094/** PGMMAPSET::cEntries value for a closed set. */
2095#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
2096
2097/** Hash function for aiHashTable. */
2098#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
2099
2100
2101/** @name Context neutral page mapper TLB.
2102 *
2103 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
2104 * code is writting in a kind of context neutral way. Time will show whether
2105 * this actually makes sense or not...
2106 *
2107 * @todo this needs to be reconsidered and dropped/redone since the ring-0
2108 * context ends up using a global mapping cache on some platforms
2109 * (darwin).
2110 *
2111 * @{ */
2112/** @typedef PPGMPAGEMAPTLB
2113 * The page mapper TLB pointer type for the current context. */
2114/** @typedef PPGMPAGEMAPTLB
2115 * The page mapper TLB entry pointer type for the current context. */
2116/** @typedef PPGMPAGEMAPTLB
2117 * The page mapper TLB entry pointer pointer type for the current context. */
2118/** @def PGM_PAGEMAPTLB_ENTRIES
2119 * The number of TLB entries in the page mapper TLB for the current context. */
2120/** @def PGM_PAGEMAPTLB_IDX
2121 * Calculate the TLB index for a guest physical address.
2122 * @returns The TLB index.
2123 * @param GCPhys The guest physical address. */
2124/** @typedef PPGMPAGEMAP
2125 * Pointer to a page mapper unit for current context. */
2126/** @typedef PPPGMPAGEMAP
2127 * Pointer to a page mapper unit pointer for current context. */
2128#if defined(IN_RC) && !defined(DOXYGEN_RUNNING)
2129// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
2130// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
2131// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
2132# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
2133# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
2134 typedef void * PPGMPAGEMAP;
2135 typedef void ** PPPGMPAGEMAP;
2136//#elif IN_RING0
2137// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
2138// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
2139// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
2140//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
2141//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
2142// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
2143// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
2144#else
2145 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
2146 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
2147 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
2148# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
2149# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
2150 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
2151 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
2152#endif
2153/** @} */
2154
2155
2156/** @name PGM Pool Indexes.
2157 * Aka. the unique shadow page identifier.
2158 * @{ */
2159/** NIL page pool IDX. */
2160#define NIL_PGMPOOL_IDX 0
2161/** The first normal index. There used to be 5 fictive pages up front, now
2162 * there is only the NIL page. */
2163#define PGMPOOL_IDX_FIRST 1
2164/** The last valid index. (inclusive, 14 bits) */
2165#define PGMPOOL_IDX_LAST 0x3fff
2166/** @} */
2167
2168/** The NIL index for the parent chain. */
2169#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
2170#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
2171
2172/**
2173 * Node in the chain linking a shadowed page to it's parent (user).
2174 */
2175#pragma pack(1)
2176typedef struct PGMPOOLUSER
2177{
2178 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
2179 uint16_t iNext;
2180 /** The user page index. */
2181 uint16_t iUser;
2182 /** Index into the user table. */
2183 uint32_t iUserTable;
2184} PGMPOOLUSER, *PPGMPOOLUSER;
2185typedef const PGMPOOLUSER *PCPGMPOOLUSER;
2186#pragma pack()
2187
2188
2189/** The NIL index for the phys ext chain. */
2190#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
2191/** The NIL pte index for a phys ext chain slot. */
2192#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
2193
2194/**
2195 * Node in the chain of physical cross reference extents.
2196 * @todo Calling this an 'extent' is not quite right, find a better name.
2197 * @todo find out the optimal size of the aidx array
2198 */
2199#pragma pack(1)
2200typedef struct PGMPOOLPHYSEXT
2201{
2202 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
2203 uint16_t iNext;
2204 /** Alignment. */
2205 uint16_t u16Align;
2206 /** The user page index. */
2207 uint16_t aidx[3];
2208 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
2209 uint16_t apte[3];
2210} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
2211typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
2212#pragma pack()
2213
2214
2215/**
2216 * The kind of page that's being shadowed.
2217 */
2218typedef enum PGMPOOLKIND
2219{
2220 /** The virtual invalid 0 entry. */
2221 PGMPOOLKIND_INVALID = 0,
2222 /** The entry is free (=unused). */
2223 PGMPOOLKIND_FREE,
2224
2225 /** Shw: 32-bit page table; Gst: no paging. */
2226 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
2227 /** Shw: 32-bit page table; Gst: 32-bit page table. */
2228 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
2229 /** Shw: 32-bit page table; Gst: 4MB page. */
2230 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2231 /** Shw: PAE page table; Gst: no paging. */
2232 PGMPOOLKIND_PAE_PT_FOR_PHYS,
2233 /** Shw: PAE page table; Gst: 32-bit page table. */
2234 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2235 /** Shw: PAE page table; Gst: Half of a 4MB page. */
2236 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2237 /** Shw: PAE page table; Gst: PAE page table. */
2238 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2239 /** Shw: PAE page table; Gst: 2MB page. */
2240 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2241
2242 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2243 PGMPOOLKIND_32BIT_PD,
2244 /** Shw: 32-bit page directory. Gst: no paging. */
2245 PGMPOOLKIND_32BIT_PD_PHYS,
2246 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2247 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2248 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2249 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2250 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2251 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2252 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2253 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2254 /** Shw: PAE page directory; Gst: PAE page directory. */
2255 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2256 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2257 PGMPOOLKIND_PAE_PD_PHYS,
2258
2259 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2260 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2261 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2262 PGMPOOLKIND_PAE_PDPT,
2263 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2264 PGMPOOLKIND_PAE_PDPT_PHYS,
2265
2266 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2267 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2268 /** Shw: 64-bit page directory pointer table; Gst: no paging. */
2269 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2270 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2271 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2272 /** Shw: 64-bit page directory table; Gst: no paging. */
2273 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2274
2275 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2276 PGMPOOLKIND_64BIT_PML4,
2277
2278 /** Shw: EPT page directory pointer table; Gst: no paging. */
2279 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2280 /** Shw: EPT page directory table; Gst: no paging. */
2281 PGMPOOLKIND_EPT_PD_FOR_PHYS,
2282 /** Shw: EPT page table; Gst: no paging. */
2283 PGMPOOLKIND_EPT_PT_FOR_PHYS,
2284
2285 /** Shw: Root Nested paging table. */
2286 PGMPOOLKIND_ROOT_NESTED,
2287
2288 /** The last valid entry. */
2289 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2290} PGMPOOLKIND;
2291
2292/**
2293 * The access attributes of the page; only applies to big pages.
2294 */
2295typedef enum
2296{
2297 PGMPOOLACCESS_DONTCARE = 0,
2298 PGMPOOLACCESS_USER_RW,
2299 PGMPOOLACCESS_USER_R,
2300 PGMPOOLACCESS_USER_RW_NX,
2301 PGMPOOLACCESS_USER_R_NX,
2302 PGMPOOLACCESS_SUPERVISOR_RW,
2303 PGMPOOLACCESS_SUPERVISOR_R,
2304 PGMPOOLACCESS_SUPERVISOR_RW_NX,
2305 PGMPOOLACCESS_SUPERVISOR_R_NX
2306} PGMPOOLACCESS;
2307
2308/**
2309 * The tracking data for a page in the pool.
2310 */
2311typedef struct PGMPOOLPAGE
2312{
2313 /** AVL node code with the (HC) physical address of this page. */
2314 AVLOHCPHYSNODECORE Core;
2315 /** Pointer to the R3 mapping of the page. */
2316#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2317 R3PTRTYPE(void *) pvPageR3;
2318#else
2319 R3R0PTRTYPE(void *) pvPageR3;
2320#endif
2321#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2322 uint32_t Alignment0;
2323#endif
2324 /** The guest physical address. */
2325 RTGCPHYS GCPhys;
2326 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2327 uint8_t enmKind;
2328 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2329 uint8_t enmAccess;
2330 /** This supplements enmKind and enmAccess */
2331 bool fA20Enabled : 1;
2332
2333 /** Used to indicate that the page is zeroed. */
2334 bool fZeroed : 1;
2335 /** Used to indicate that a PT has non-global entries. */
2336 bool fSeenNonGlobal : 1;
2337 /** Used to indicate that we're monitoring writes to the guest page. */
2338 bool fMonitored : 1;
2339 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2340 * (All pages are in the age list.) */
2341 bool fCached : 1;
2342 /** This is used by the R3 access handlers when invoked by an async thread.
2343 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2344 bool volatile fReusedFlushPending : 1;
2345 /** Used to mark the page as dirty (write monitoring is temporarily
2346 * off). */
2347 bool fDirty : 1;
2348 bool fPadding1 : 1;
2349 bool fPadding2;
2350
2351 /** The index of this page. */
2352 uint16_t idx;
2353 /** The next entry in the list this page currently resides in.
2354 * It's either in the free list or in the GCPhys hash. */
2355 uint16_t iNext;
2356 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2357 uint16_t iUserHead;
2358 /** The number of present entries. */
2359 uint16_t cPresent;
2360 /** The first entry in the table which is present. */
2361 uint16_t iFirstPresent;
2362 /** The number of modifications to the monitored page. */
2363 uint16_t cModifications;
2364 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2365 uint16_t iModifiedNext;
2366 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2367 uint16_t iModifiedPrev;
2368 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2369 uint16_t iMonitoredNext;
2370 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2371 uint16_t iMonitoredPrev;
2372 /** The next page in the age list. */
2373 uint16_t iAgeNext;
2374 /** The previous page in the age list. */
2375 uint16_t iAgePrev;
2376 /** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2377 uint8_t idxDirtyEntry;
2378
2379 /** @name Access handler statistics to determine whether the guest is
2380 * (re)initializing a page table.
2381 * @{ */
2382 RTGCPTR GCPtrLastAccessHandlerRip;
2383 RTGCPTR GCPtrLastAccessHandlerFault;
2384 uint64_t cLastAccessHandler;
2385 /** @} */
2386 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2387 uint32_t volatile cLocked;
2388#if GC_ARCH_BITS == 64
2389 uint32_t u32Alignment3;
2390#endif
2391# ifdef VBOX_STRICT
2392 RTGCPTR GCPtrDirtyFault;
2393# endif
2394} PGMPOOLPAGE;
2395/** Pointer to a pool page. */
2396typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2397/** Pointer to a const pool page. */
2398typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2399/** Pointer to a pool page pointer. */
2400typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2401
2402
2403/** The hash table size. */
2404# define PGMPOOL_HASH_SIZE 0x40
2405/** The hash function. */
2406# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2407
2408
2409/**
2410 * The shadow page pool instance data.
2411 *
2412 * It's all one big allocation made at init time, except for the
2413 * pages that is. The user nodes follows immediately after the
2414 * page structures.
2415 */
2416typedef struct PGMPOOL
2417{
2418 /** The VM handle - R3 Ptr. */
2419 PVMR3 pVMR3;
2420 /** The VM handle - R0 Ptr. */
2421 PVMR0 pVMR0;
2422 /** The VM handle - RC Ptr. */
2423 PVMRC pVMRC;
2424 /** The max pool size. This includes the special IDs. */
2425 uint16_t cMaxPages;
2426 /** The current pool size. */
2427 uint16_t cCurPages;
2428 /** The head of the free page list. */
2429 uint16_t iFreeHead;
2430 /* Padding. */
2431 uint16_t u16Padding;
2432 /** Head of the chain of free user nodes. */
2433 uint16_t iUserFreeHead;
2434 /** The number of user nodes we've allocated. */
2435 uint16_t cMaxUsers;
2436 /** The number of present page table entries in the entire pool. */
2437 uint32_t cPresent;
2438 /** Pointer to the array of user nodes - RC pointer. */
2439 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2440 /** Pointer to the array of user nodes - R3 pointer. */
2441 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2442 /** Pointer to the array of user nodes - R0 pointer. */
2443 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2444 /** Head of the chain of free phys ext nodes. */
2445 uint16_t iPhysExtFreeHead;
2446 /** The number of user nodes we've allocated. */
2447 uint16_t cMaxPhysExts;
2448 /** Pointer to the array of physical xref extent - RC pointer. */
2449 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2450 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2451 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2452 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2453 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2454 /** Hash table for GCPhys addresses. */
2455 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2456 /** The head of the age list. */
2457 uint16_t iAgeHead;
2458 /** The tail of the age list. */
2459 uint16_t iAgeTail;
2460 /** Set if the cache is enabled. */
2461 bool fCacheEnabled;
2462 /** Alignment padding. */
2463 bool afPadding1[3];
2464 /** Head of the list of modified pages. */
2465 uint16_t iModifiedHead;
2466 /** The current number of modified pages. */
2467 uint16_t cModifiedPages;
2468 /** Physical access handler type registration handle. */
2469 PGMPHYSHANDLERTYPE hAccessHandlerType;
2470 /** Next available slot (in aDirtyPages). */
2471 uint32_t idxFreeDirtyPage;
2472 /** Number of active dirty pages. */
2473 uint32_t cDirtyPages;
2474 /** Array of current dirty pgm pool page indices. */
2475 struct
2476 {
2477 uint16_t uIdx;
2478 uint16_t Alignment[3];
2479 uint64_t aPage[512];
2480 } aDirtyPages[16];
2481 /** The number of pages currently in use. */
2482 uint16_t cUsedPages;
2483#ifdef VBOX_WITH_STATISTICS
2484 /** The high water mark for cUsedPages. */
2485 uint16_t cUsedPagesHigh;
2486 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2487 /** Profiling pgmPoolAlloc(). */
2488 STAMPROFILEADV StatAlloc;
2489 /** Profiling pgmR3PoolClearDoIt(). */
2490 STAMPROFILE StatClearAll;
2491 /** Profiling pgmR3PoolReset(). */
2492 STAMPROFILE StatR3Reset;
2493 /** Profiling pgmPoolFlushPage(). */
2494 STAMPROFILE StatFlushPage;
2495 /** Profiling pgmPoolFree(). */
2496 STAMPROFILE StatFree;
2497 /** Counting explicit flushes by PGMPoolFlushPage(). */
2498 STAMCOUNTER StatForceFlushPage;
2499 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2500 STAMCOUNTER StatForceFlushDirtyPage;
2501 /** Counting flushes for reused pages. */
2502 STAMCOUNTER StatForceFlushReused;
2503 /** Profiling time spent zeroing pages. */
2504 STAMPROFILE StatZeroPage;
2505 /** Profiling of pgmPoolTrackDeref. */
2506 STAMPROFILE StatTrackDeref;
2507 /** Profiling pgmTrackFlushGCPhysPT. */
2508 STAMPROFILE StatTrackFlushGCPhysPT;
2509 /** Profiling pgmTrackFlushGCPhysPTs. */
2510 STAMPROFILE StatTrackFlushGCPhysPTs;
2511 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2512 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2513 /** Number of times we've been out of user records. */
2514 STAMCOUNTER StatTrackFreeUpOneUser;
2515 /** Nr of flushed entries. */
2516 STAMCOUNTER StatTrackFlushEntry;
2517 /** Nr of updated entries. */
2518 STAMCOUNTER StatTrackFlushEntryKeep;
2519 /** Profiling deref activity related tracking GC physical pages. */
2520 STAMPROFILE StatTrackDerefGCPhys;
2521 /** Number of linear searches for a HCPhys in the ram ranges. */
2522 STAMCOUNTER StatTrackLinearRamSearches;
2523 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2524 STAMCOUNTER StamTrackPhysExtAllocFailures;
2525
2526 /** Profiling the RC/R0 \#PF access handler. */
2527 STAMPROFILE StatMonitorPfRZ;
2528 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2529 STAMPROFILE StatMonitorPfRZHandled;
2530 /** Times we've failed interpreting the instruction. */
2531 STAMCOUNTER StatMonitorPfRZEmulateInstr;
2532 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2533 STAMPROFILE StatMonitorPfRZFlushPage;
2534 /* Times we've detected a page table reinit. */
2535 STAMCOUNTER StatMonitorPfRZFlushReinit;
2536 /** Counting flushes for pages that are modified too often. */
2537 STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2538 /** Times we've detected fork(). */
2539 STAMCOUNTER StatMonitorPfRZFork;
2540 /** Times we've failed interpreting a patch code instruction. */
2541 STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2542 /** Times we've failed interpreting a patch code instruction during flushing. */
2543 STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2544 /** The number of times we've seen rep prefixes we can't handle. */
2545 STAMCOUNTER StatMonitorPfRZRepPrefix;
2546 /** Profiling the REP STOSD cases we've handled. */
2547 STAMPROFILE StatMonitorPfRZRepStosd;
2548
2549 /** Profiling the R0/RC regular access handler. */
2550 STAMPROFILE StatMonitorRZ;
2551 /** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2552 STAMPROFILE StatMonitorRZFlushPage;
2553 /** Per access size counts indexed by size minus 1, last for larger. */
2554 STAMCOUNTER aStatMonitorRZSizes[16+3];
2555 /** Missaligned access counts indexed by offset - 1. */
2556 STAMCOUNTER aStatMonitorRZMisaligned[7];
2557
2558 /** Nr of handled PT faults. */
2559 STAMCOUNTER StatMonitorRZFaultPT;
2560 /** Nr of handled PD faults. */
2561 STAMCOUNTER StatMonitorRZFaultPD;
2562 /** Nr of handled PDPT faults. */
2563 STAMCOUNTER StatMonitorRZFaultPDPT;
2564 /** Nr of handled PML4 faults. */
2565 STAMCOUNTER StatMonitorRZFaultPML4;
2566
2567 /** Profiling the R3 access handler. */
2568 STAMPROFILE StatMonitorR3;
2569 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2570 STAMPROFILE StatMonitorR3FlushPage;
2571 /** Per access size counts indexed by size minus 1, last for larger. */
2572 STAMCOUNTER aStatMonitorR3Sizes[16+3];
2573 /** Missaligned access counts indexed by offset - 1. */
2574 STAMCOUNTER aStatMonitorR3Misaligned[7];
2575 /** Nr of handled PT faults. */
2576 STAMCOUNTER StatMonitorR3FaultPT;
2577 /** Nr of handled PD faults. */
2578 STAMCOUNTER StatMonitorR3FaultPD;
2579 /** Nr of handled PDPT faults. */
2580 STAMCOUNTER StatMonitorR3FaultPDPT;
2581 /** Nr of handled PML4 faults. */
2582 STAMCOUNTER StatMonitorR3FaultPML4;
2583
2584 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2585 STAMCOUNTER StatResetDirtyPages;
2586 /** Times we've called pgmPoolAddDirtyPage. */
2587 STAMCOUNTER StatDirtyPage;
2588 /** Times we've had to flush duplicates for dirty page management. */
2589 STAMCOUNTER StatDirtyPageDupFlush;
2590 /** Times we've had to flush because of overflow. */
2591 STAMCOUNTER StatDirtyPageOverFlowFlush;
2592
2593 /** The high water mark for cModifiedPages. */
2594 uint16_t cModifiedPagesHigh;
2595 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2596
2597 /** The number of cache hits. */
2598 STAMCOUNTER StatCacheHits;
2599 /** The number of cache misses. */
2600 STAMCOUNTER StatCacheMisses;
2601 /** The number of times we've got a conflict of 'kind' in the cache. */
2602 STAMCOUNTER StatCacheKindMismatches;
2603 /** Number of times we've been out of pages. */
2604 STAMCOUNTER StatCacheFreeUpOne;
2605 /** The number of cacheable allocations. */
2606 STAMCOUNTER StatCacheCacheable;
2607 /** The number of uncacheable allocations. */
2608 STAMCOUNTER StatCacheUncacheable;
2609#else
2610 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2611#endif
2612 /** The AVL tree for looking up a page by its HC physical address. */
2613 AVLOHCPHYSTREE HCPhysTree;
2614 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2615 /** Array of pages. (cMaxPages in length)
2616 * The Id is the index into thist array.
2617 */
2618 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2619} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2620AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2621AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2622AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2623#ifdef VBOX_WITH_STATISTICS
2624AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2625#endif
2626AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2627
2628
2629/** @def PGMPOOL_PAGE_2_PTR
2630 * Maps a pool page pool into the current context.
2631 *
2632 * @returns VBox status code.
2633 * @param a_pVM Pointer to the VM.
2634 * @param a_pPage The pool page.
2635 *
2636 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2637 * small page window employeed by that function. Be careful.
2638 * @remark There is no need to assert on the result.
2639 */
2640#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2641# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2642#elif defined(VBOX_STRICT) || 1 /* temporarily going strict here */
2643# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2644DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char *pszCaller)
2645{
2646 AssertPtr(a_pPage);
2647 AssertReleaseMsg(RT_VALID_PTR(a_pPage->pvPageR3), ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp caller=%s\n", a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, pszCaller));
2648 return a_pPage->pvPageR3;
2649}
2650#else
2651# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2652#endif
2653
2654
2655/** @def PGMPOOL_PAGE_2_PTR_V2
2656 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2657 *
2658 * @returns VBox status code.
2659 * @param a_pVM Pointer to the VM.
2660 * @param a_pVCpu The current CPU.
2661 * @param a_pPage The pool page.
2662 *
2663 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2664 * small page window employeed by that function. Be careful.
2665 * @remark There is no need to assert on the result.
2666 */
2667#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2668# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2669#else
2670# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2671#endif
2672
2673
2674/** @name Per guest page tracking data.
2675 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2676 * is to use more bits for it and split it up later on. But for now we'll play
2677 * safe and change as little as possible.
2678 *
2679 * The 16-bit word has two parts:
2680 *
2681 * The first 14-bit forms the @a idx field. It is either the index of a page in
2682 * the shadow page pool, or and index into the extent list.
2683 *
2684 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2685 * shadow page pool references to the page. If cRefs equals
2686 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2687 * (misnomer) table and not the shadow page pool.
2688 *
2689 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2690 * the 16-bit word.
2691 *
2692 * @{ */
2693/** The shift count for getting to the cRefs part. */
2694#define PGMPOOL_TD_CREFS_SHIFT 14
2695/** The mask applied after shifting the tracking data down by
2696 * PGMPOOL_TD_CREFS_SHIFT. */
2697#define PGMPOOL_TD_CREFS_MASK 0x3
2698/** The cRefs value used to indicate that the idx is the head of a
2699 * physical cross reference list. */
2700#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2701/** The shift used to get idx. */
2702#define PGMPOOL_TD_IDX_SHIFT 0
2703/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2704#define PGMPOOL_TD_IDX_MASK 0x3fff
2705/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2706 * simply too many mappings of this page. */
2707#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2708
2709/** @def PGMPOOL_TD_MAKE
2710 * Makes a 16-bit tracking data word.
2711 *
2712 * @returns tracking data.
2713 * @param cRefs The @a cRefs field. Must be within bounds!
2714 * @param idx The @a idx field. Must also be within bounds! */
2715#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2716
2717/** @def PGMPOOL_TD_GET_CREFS
2718 * Get the @a cRefs field from a tracking data word.
2719 *
2720 * @returns The @a cRefs field
2721 * @param u16 The tracking data word.
2722 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2723 * non-zero @a u16. */
2724#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2725
2726/** @def PGMPOOL_TD_GET_IDX
2727 * Get the @a idx field from a tracking data word.
2728 *
2729 * @returns The @a idx field
2730 * @param u16 The tracking data word. */
2731#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2732/** @} */
2733
2734
2735
2736/** @name A20 gate macros
2737 * @{ */
2738#define PGM_WITH_A20
2739#ifdef PGM_WITH_A20
2740# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2741# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2742# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2743 do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2744# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2745#else
2746# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2747# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2748# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2749# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2750#endif
2751/** @} */
2752
2753
2754/**
2755 * Roots and anchors for trees and list employing self relative offsets as
2756 * pointers.
2757 *
2758 * When using self-relative offsets instead of pointers, the offsets needs to be
2759 * the same in all offsets. Thus the roots and anchors needs to live on the
2760 * hyper heap just like the nodes.
2761 */
2762typedef struct PGMTREES
2763{
2764 /** List of physical access handler types (offset pointers) of type
2765 * PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2766 RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2767 /** Physical access handlers (AVL range+offsetptr tree). */
2768 AVLROGCPHYSTREE PhysHandlers;
2769#ifdef VBOX_WITH_RAW_MODE
2770 /** Virtual access handlers (AVL range + GC ptr tree). */
2771 AVLROGCPTRTREE VirtHandlers;
2772 /** Virtual access handlers (Phys range AVL range + offsetptr tree).
2773 * @remarks Handler of the hypervisor kind are of course not present. */
2774 AVLROGCPHYSTREE PhysToVirtHandlers;
2775 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2776 AVLROGCPTRTREE HyperVirtHandlers;
2777 /** List of virtual access handler types (offset pointers) of type
2778 * PGMVIRTHANDLERTYPEINT. This is needed for relocations. */
2779 RTLISTOFF32ANCHOR HeadVirtHandlerTypes;
2780#endif
2781} PGMTREES;
2782/** Pointer to PGM trees. */
2783typedef PGMTREES *PPGMTREES;
2784
2785
2786/**
2787 * Page fault guest state for the AMD64 paging mode.
2788 */
2789typedef struct PGMPTWALKCORE
2790{
2791 /** The guest virtual address that is being resolved by the walk
2792 * (input). */
2793 RTGCPTR GCPtr;
2794
2795 /** The guest physical address that is the result of the walk.
2796 * @remarks only valid if fSucceeded is set. */
2797 RTGCPHYS GCPhys;
2798
2799 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2800 bool fSucceeded;
2801 /** The level problem arrised at.
2802 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2803 * level 8. This is 0 on success. */
2804 uint8_t uLevel;
2805 /** Set if the page isn't present. */
2806 bool fNotPresent;
2807 /** Encountered a bad physical address. */
2808 bool fBadPhysAddr;
2809 /** Set if there was reserved bit violations. */
2810 bool fRsvdError;
2811 /** Set if it involves a big page (2/4 MB). */
2812 bool fBigPage;
2813 /** Set if it involves a gigantic page (1 GB). */
2814 bool fGigantPage;
2815 /** The effective X86_PTE_US flag for the address. */
2816 bool fEffectiveUS;
2817 /** The effective X86_PTE_RW flag for the address. */
2818 bool fEffectiveRW;
2819 /** The effective X86_PTE_NX flag for the address. */
2820 bool fEffectiveNX;
2821 bool afPadding1[2];
2822 /** Effective flags thus far: RW, US, PWT, PCD, A, ~NX >> 63.
2823 * The NX bit is inverted and shifted down 63 places to bit 0. */
2824 uint32_t fEffective;
2825} PGMPTWALKCORE;
2826
2827/** @name PGMPTWALKCORE::fEffective bits.
2828 * @{ */
2829/** Effective execute bit (!NX). */
2830#define PGMPTWALK_EFF_X UINT32_C(1)
2831/** Effective write access bit. */
2832#define PGMPTWALK_EFF_RW X86_PTE_RW
2833/** Effective user-mode access bit. */
2834#define PGMPTWALK_EFF_US X86_PTE_US
2835/** Effective write through cache bit. */
2836#define PGMPTWALK_EFF_PWT X86_PTE_PWT
2837/** Effective cache disabled bit. */
2838#define PGMPTWALK_EFF_PCD X86_PTE_PCD
2839/** Effective accessed bit. */
2840#define PGMPTWALK_EFF_A X86_PTE_A
2841/** The dirty bit of the final entry. */
2842#define PGMPTWALK_EFF_D X86_PTE_D
2843/** The PAT bit of the final entry. */
2844#define PGMPTWALK_EFF_PAT X86_PTE_PAT
2845/** The global bit of the final entry. */
2846#define PGMPTWALK_EFF_G X86_PTE_G
2847/** @} */
2848
2849
2850/**
2851 * Guest page table walk for the AMD64 mode.
2852 */
2853typedef struct PGMPTWALKGSTAMD64
2854{
2855 /** The common core. */
2856 PGMPTWALKCORE Core;
2857
2858 PX86PML4 pPml4;
2859 PX86PML4E pPml4e;
2860 X86PML4E Pml4e;
2861
2862 PX86PDPT pPdpt;
2863 PX86PDPE pPdpe;
2864 X86PDPE Pdpe;
2865
2866 PX86PDPAE pPd;
2867 PX86PDEPAE pPde;
2868 X86PDEPAE Pde;
2869
2870 PX86PTPAE pPt;
2871 PX86PTEPAE pPte;
2872 X86PTEPAE Pte;
2873} PGMPTWALKGSTAMD64;
2874/** Pointer to a AMD64 guest page table walk. */
2875typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2876/** Pointer to a const AMD64 guest page table walk. */
2877typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2878
2879/**
2880 * Guest page table walk for the PAE mode.
2881 */
2882typedef struct PGMPTWALKGSTPAE
2883{
2884 /** The common core. */
2885 PGMPTWALKCORE Core;
2886
2887 PX86PDPT pPdpt;
2888 PX86PDPE pPdpe;
2889 X86PDPE Pdpe;
2890
2891 PX86PDPAE pPd;
2892 PX86PDEPAE pPde;
2893 X86PDEPAE Pde;
2894
2895 PX86PTPAE pPt;
2896 PX86PTEPAE pPte;
2897 X86PTEPAE Pte;
2898} PGMPTWALKGSTPAE;
2899/** Pointer to a PAE guest page table walk. */
2900typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2901/** Pointer to a const AMD64 guest page table walk. */
2902typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2903
2904/**
2905 * Guest page table walk for the 32-bit mode.
2906 */
2907typedef struct PGMPTWALKGST32BIT
2908{
2909 /** The common core. */
2910 PGMPTWALKCORE Core;
2911
2912 PX86PD pPd;
2913 PX86PDE pPde;
2914 X86PDE Pde;
2915
2916 PX86PT pPt;
2917 PX86PTE pPte;
2918 X86PTE Pte;
2919} PGMPTWALKGST32BIT;
2920/** Pointer to a 32-bit guest page table walk. */
2921typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2922/** Pointer to a const 32-bit guest page table walk. */
2923typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2924
2925/**
2926 * Which part of PGMPTWALKGST that is valid.
2927 */
2928typedef enum PGMPTWALKGSTTYPE
2929{
2930 /** Customary invalid 0 value. */
2931 PGMPTWALKGSTTYPE_INVALID = 0,
2932 /** PGMPTWALKGST::u.Amd64 is valid. */
2933 PGMPTWALKGSTTYPE_AMD64,
2934 /** PGMPTWALKGST::u.Pae is valid. */
2935 PGMPTWALKGSTTYPE_PAE,
2936 /** PGMPTWALKGST::u.Legacy is valid. */
2937 PGMPTWALKGSTTYPE_32BIT,
2938 /** Customary 32-bit type hack. */
2939 PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2940} PGMPTWALKGSTTYPE;
2941
2942/**
2943 * Combined guest page table walk result.
2944 */
2945typedef struct PGMPTWALKGST
2946{
2947 union
2948 {
2949 /** The page walker core - always valid. */
2950 PGMPTWALKCORE Core;
2951 /** The page walker for AMD64. */
2952 PGMPTWALKGSTAMD64 Amd64;
2953 /** The page walker for PAE (32-bit). */
2954 PGMPTWALKGSTPAE Pae;
2955 /** The page walker for 32-bit paging (called legacy due to C naming
2956 * convension). */
2957 PGMPTWALKGST32BIT Legacy;
2958 } u;
2959 /** Indicates which part of the union is valid. */
2960 PGMPTWALKGSTTYPE enmType;
2961} PGMPTWALKGST;
2962/** Pointer to a combined guest page table walk result. */
2963typedef PGMPTWALKGST *PPGMPTWALKGST;
2964/** Pointer to a read-only combined guest page table walk result. */
2965typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2966
2967
2968/** @name Paging mode macros
2969 * @{
2970 */
2971#ifdef IN_RC
2972# define PGM_CTX(a,b) a##RC##b
2973# define PGM_CTX_STR(a,b) a "GC" b
2974# define PGM_CTX_DECL(type) VMMRCDECL(type)
2975#else
2976# ifdef IN_RING3
2977# define PGM_CTX(a,b) a##R3##b
2978# define PGM_CTX_STR(a,b) a "R3" b
2979# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2980# else
2981# define PGM_CTX(a,b) a##R0##b
2982# define PGM_CTX_STR(a,b) a "R0" b
2983# define PGM_CTX_DECL(type) VMMDECL(type)
2984# endif
2985#endif
2986
2987#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2988#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2989#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2990#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2991#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2992#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2993#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2994#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2995#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2996#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2997#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2998#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2999#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
3000#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
3001#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
3002#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
3003
3004#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
3005#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
3006#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
3007#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
3008#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
3009#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
3010#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
3011#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
3012#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
3013#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
3014#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
3015#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
3016#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
3017#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
3018#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
3019#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
3020#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
3021#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
3022#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
3023#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
3024#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
3025#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
3026#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
3027#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
3028#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
3029
3030/* Shw_Gst */
3031#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
3032#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
3033#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
3034#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
3035#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
3036#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
3037#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
3038#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
3039#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
3040#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
3041#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
3042#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
3043#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
3044#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
3045#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
3046#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
3047#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
3048#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
3049#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
3050#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
3051#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
3052#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
3053#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
3054#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
3055#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
3056#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
3057#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
3058#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
3059#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
3060#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
3061#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
3062#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
3063#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
3064#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
3065
3066#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
3067#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
3068#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
3069#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
3070#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
3071#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
3072#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
3073#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
3074#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
3075#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
3076#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
3077#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
3078#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
3079#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
3080#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
3081#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
3082#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
3083#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
3084#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
3085#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
3086#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
3087#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
3088#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
3089#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
3090#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
3091#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
3092#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
3093#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
3094
3095#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
3096#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
3097#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
3098#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
3099#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
3100#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
3101#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
3102#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
3103#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
3104#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
3105#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
3106#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
3107#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
3108#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
3109#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
3110#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
3111#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
3112#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
3113#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
3114#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
3115#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
3116#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
3117#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
3118#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
3119#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
3120#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
3121#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
3122#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
3123#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
3124
3125#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
3126/** @} */
3127
3128
3129/**
3130 * Function pointers for guest paging.
3131 */
3132typedef struct PGMMODEDATAGST
3133{
3134 /** The guest mode type. */
3135 uint32_t uType;
3136 DECLCALLBACKMEMBER(int, pfnGetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys);
3137 DECLCALLBACKMEMBER(int, pfnModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask);
3138 DECLCALLBACKMEMBER(int, pfnGetPDE)(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde);
3139 DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
3140 DECLCALLBACKMEMBER(int, pfnExit)(PVMCPU pVCpu);
3141#ifdef IN_RING3
3142 DECLCALLBACKMEMBER(int, pfnRelocate)(PVMCPU pVCpu, RTGCPTR offDelta); /**< Only in ring-3. */
3143#endif
3144} PGMMODEDATAGST;
3145
3146/** The length of g_aPgmGuestModeData. */
3147#if defined(VBOX_WITH_64_BITS_GUESTS) && !defined(IN_RC)
3148# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
3149#else
3150# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
3151#endif
3152/** The guest mode data array. */
3153extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
3154
3155
3156/**
3157 * Function pointers for shadow paging.
3158 */
3159typedef struct PGMMODEDATASHW
3160{
3161 /** The shadow mode type. */
3162 uint32_t uType;
3163 DECLCALLBACKMEMBER(int, pfnGetPage)(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys);
3164 DECLCALLBACKMEMBER(int, pfnModifyPage)(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
3165 uint64_t fMask, uint32_t fOpFlags);
3166 DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPU pVCpu, bool fIs64BitsPagingMode);
3167 DECLCALLBACKMEMBER(int, pfnExit)(PVMCPU pVCpu);
3168#ifdef IN_RING3
3169 DECLCALLBACKMEMBER(int, pfnRelocate)(PVMCPU pVCpu, RTGCPTR offDelta); /**< Only in ring-3. */
3170#endif
3171} PGMMODEDATASHW;
3172
3173/** The length of g_aPgmShadowModeData. */
3174#ifndef IN_RC
3175# define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
3176#else
3177# define PGM_SHADOW_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
3178#endif
3179/** The shadow mode data array. */
3180extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
3181
3182
3183/**
3184 * Function pointers for guest+shadow paging.
3185 */
3186typedef struct PGMMODEDATABTH
3187{
3188 /** The shadow mode type. */
3189 uint32_t uShwType;
3190 /** The guest mode type. */
3191 uint32_t uGstType;
3192
3193 DECLCALLBACKMEMBER(int, pfnInvalidatePage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
3194 DECLCALLBACKMEMBER(int, pfnSyncCR3)(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal);
3195 DECLCALLBACKMEMBER(int, pfnPrefetchPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage);
3196 DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage)(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError);
3197 DECLCALLBACKMEMBER(int, pfnMapCR3)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
3198 DECLCALLBACKMEMBER(int, pfnUnmapCR3)(PVMCPU pVCpu);
3199 DECLCALLBACKMEMBER(int, pfnEnter)(PVMCPU pVCpu, RTGCPHYS GCPhysCR3);
3200#ifndef IN_RING3
3201 DECLCALLBACKMEMBER(int, pfnTrap0eHandler)(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken);
3202#endif
3203#ifdef VBOX_STRICT
3204 DECLCALLBACKMEMBER(unsigned, pfnAssertCR3)(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb);
3205#endif
3206} PGMMODEDATABTH;
3207
3208/** The length of g_aPgmBothModeData. */
3209#ifndef IN_RC
3210# define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
3211#else
3212# define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_PAE + 1 - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
3213#endif
3214/** The guest+shadow mode data array. */
3215extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
3216
3217
3218#ifdef VBOX_WITH_STATISTICS
3219/**
3220 * PGM statistics.
3221 *
3222 * These lives on the heap when compiled in as they would otherwise waste
3223 * unnecessary space in release builds.
3224 */
3225typedef struct PGMSTATS
3226{
3227 /* R3 only: */
3228 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
3229 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
3230
3231 /* R3+RZ */
3232 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
3233 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
3234 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
3235 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
3236 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
3237 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
3238 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
3239 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
3240 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
3241 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
3242 STAMCOUNTER StatRZRamRangeTlbHits; /**< RC/R0: RAM range TLB hits. */
3243 STAMCOUNTER StatRZRamRangeTlbMisses; /**< RC/R0: RAM range TLB misses. */
3244 STAMCOUNTER StatR3RamRangeTlbHits; /**< R3: RAM range TLB hits. */
3245 STAMCOUNTER StatR3RamRangeTlbMisses; /**< R3: RAM range TLB misses. */
3246 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
3247 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
3248 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
3249 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
3250 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
3251 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
3252 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
3253 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
3254 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
3255 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
3256 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
3257 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
3258 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
3259 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
3260/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
3261 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
3262 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
3263/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
3264
3265 /* RC only: */
3266 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
3267 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
3268
3269 STAMCOUNTER StatRZPhysRead;
3270 STAMCOUNTER StatRZPhysReadBytes;
3271 STAMCOUNTER StatRZPhysWrite;
3272 STAMCOUNTER StatRZPhysWriteBytes;
3273 STAMCOUNTER StatR3PhysRead;
3274 STAMCOUNTER StatR3PhysReadBytes;
3275 STAMCOUNTER StatR3PhysWrite;
3276 STAMCOUNTER StatR3PhysWriteBytes;
3277 STAMCOUNTER StatRCPhysRead;
3278 STAMCOUNTER StatRCPhysReadBytes;
3279 STAMCOUNTER StatRCPhysWrite;
3280 STAMCOUNTER StatRCPhysWriteBytes;
3281
3282 STAMCOUNTER StatRZPhysSimpleRead;
3283 STAMCOUNTER StatRZPhysSimpleReadBytes;
3284 STAMCOUNTER StatRZPhysSimpleWrite;
3285 STAMCOUNTER StatRZPhysSimpleWriteBytes;
3286 STAMCOUNTER StatR3PhysSimpleRead;
3287 STAMCOUNTER StatR3PhysSimpleReadBytes;
3288 STAMCOUNTER StatR3PhysSimpleWrite;
3289 STAMCOUNTER StatR3PhysSimpleWriteBytes;
3290 STAMCOUNTER StatRCPhysSimpleRead;
3291 STAMCOUNTER StatRCPhysSimpleReadBytes;
3292 STAMCOUNTER StatRCPhysSimpleWrite;
3293 STAMCOUNTER StatRCPhysSimpleWriteBytes;
3294
3295 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
3296 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
3297 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
3298 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
3299 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
3300 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
3301 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
3302
3303 /** Time spent by the host OS for large page allocation. */
3304 STAMPROFILE StatAllocLargePage;
3305 /** Time spent clearing the newly allocated large pages. */
3306 STAMPROFILE StatClearLargePage;
3307 /** The number of times allocating a large pages takes more than the allowed period. */
3308 STAMCOUNTER StatLargePageOverflow;
3309 /** pgmPhysIsValidLargePage profiling - R3 */
3310 STAMPROFILE StatR3IsValidLargePage;
3311 /** pgmPhysIsValidLargePage profiling - RZ*/
3312 STAMPROFILE StatRZIsValidLargePage;
3313
3314 STAMPROFILE StatChunkAging;
3315 STAMPROFILE StatChunkFindCandidate;
3316 STAMPROFILE StatChunkUnmap;
3317 STAMPROFILE StatChunkMap;
3318} PGMSTATS;
3319#endif /* VBOX_WITH_STATISTICS */
3320
3321
3322/**
3323 * Converts a PGM pointer into a VM pointer.
3324 * @returns Pointer to the VM structure the PGM is part of.
3325 * @param pPGM Pointer to PGM instance data.
3326 */
3327#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
3328
3329/**
3330 * PGM Data (part of VM)
3331 */
3332typedef struct PGM
3333{
3334 /** Offset to the VM structure. */
3335 int32_t offVM;
3336 /** Offset of the PGMCPU structure relative to VMCPU. */
3337 int32_t offVCpuPGM;
3338
3339 /** @cfgm{/RamPreAlloc, boolean, false}
3340 * Indicates whether the base RAM should all be allocated before starting
3341 * the VM (default), or if it should be allocated when first written to.
3342 */
3343 bool fRamPreAlloc;
3344 /** Indicates whether write monitoring is currently in use.
3345 * This is used to prevent conflicts between live saving and page sharing
3346 * detection. */
3347 bool fPhysWriteMonitoringEngaged;
3348 /** Set if the CPU has less than 52-bit physical address width.
3349 * This is used */
3350 bool fLessThan52PhysicalAddressBits;
3351 /** Set when nested paging is active.
3352 * This is meant to save calls to HMIsNestedPagingActive and let the
3353 * compilers optimize the code better. Whether we use nested paging or
3354 * not is something we find out during VMM initialization and we won't
3355 * change this later on. */
3356 bool fNestedPaging;
3357 /** The host paging mode. (This is what SUPLib reports.) */
3358 SUPPAGINGMODE enmHostMode;
3359 /** We're not in a state which permits writes to guest memory.
3360 * (Only used in strict builds.) */
3361 bool fNoMorePhysWrites;
3362 /** @cfgm{/PageFusionAllowed, boolean, false}
3363 * Whether page fusion is allowed. */
3364 bool fPageFusionAllowed;
3365 /** @cfgm{/PGM/PciPassThrough, boolean, false}
3366 * Whether PCI passthrough is enabled. */
3367 bool fPciPassthrough;
3368 /** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3369 uint8_t cMmio2Regions;
3370 /** Restore original ROM page content when resetting after loading state.
3371 * The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3372 * enables the VM to start using an updated ROM without requiring powering
3373 * down the VM, just rebooting or resetting it. */
3374 bool fRestoreRomPagesOnReset;
3375 /** Whether to automatically clear all RAM pages on reset. */
3376 bool fZeroRamPagesOnReset;
3377 /** Alignment padding. */
3378 bool afAlignment3[7];
3379
3380 /** Indicates that PGMR3FinalizeMappings has been called and that further
3381 * PGMR3MapIntermediate calls will be rejected. */
3382 bool fFinalizedMappings;
3383 /** If set no conflict checks are required. */
3384 bool fMappingsFixed;
3385 /** If set if restored as fixed but we were unable to re-fixate at the old
3386 * location because of room or address incompatibilities. */
3387 bool fMappingsFixedRestored;
3388 /** Size of fixed mapping.
3389 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3390 uint32_t cbMappingFixed;
3391 /** Generation ID for the RAM ranges. This member is incremented everytime
3392 * a RAM range is linked or unlinked. */
3393 uint32_t volatile idRamRangesGen;
3394
3395 /** Base address (GC) of fixed mapping.
3396 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3397 RTGCPTR GCPtrMappingFixed;
3398 /** The address of the previous RAM range mapping. */
3399 RTGCPTR GCPtrPrevRamRangeMapping;
3400
3401 /** Physical access handler type for ROM protection. */
3402 PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3403 /** Alignment padding. */
3404 uint32_t u32Padding;
3405
3406 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3407 RTGCPHYS GCPhys4MBPSEMask;
3408 /** Mask containing the invalid bits of a guest physical address.
3409 * @remarks this does not stop at bit 52. */
3410 RTGCPHYS GCPhysInvAddrMask;
3411
3412
3413 /** RAM range TLB for R3. */
3414 R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3415 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3416 * This is sorted by physical address and contains no overlapping ranges. */
3417 R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3418 /** Root of the RAM range search tree for ring-3. */
3419 R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3420 /** PGM offset based trees - R3 Ptr. */
3421 R3PTRTYPE(PPGMTREES) pTreesR3;
3422 /** Caching the last physical handler we looked up in R3. */
3423 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3424 /** Shadow Page Pool - R3 Ptr. */
3425 R3PTRTYPE(PPGMPOOL) pPoolR3;
3426 /** Linked list of GC mappings - for HC.
3427 * The list is sorted ascending on address. */
3428 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3429 /** Pointer to the list of ROM ranges - for R3.
3430 * This is sorted by physical address and contains no overlapping ranges. */
3431 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3432 /** Pointer to the list of MMIO2 ranges - for R3.
3433 * Registration order. */
3434 R3PTRTYPE(PPGMREGMMIORANGE) pRegMmioRangesR3;
3435 /** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3436 R3PTRTYPE(PPGMREGMMIORANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3437
3438 /** RAM range TLB for R0. */
3439 R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3440 /** R0 pointer corresponding to PGM::pRamRangesXR3. */
3441 R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3442 /** Root of the RAM range search tree for ring-0. */
3443 R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3444 /** PGM offset based trees - R0 Ptr. */
3445 R0PTRTYPE(PPGMTREES) pTreesR0;
3446 /** Caching the last physical handler we looked up in R0. */
3447 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3448 /** Shadow Page Pool - R0 Ptr. */
3449 R0PTRTYPE(PPGMPOOL) pPoolR0;
3450 /** Linked list of GC mappings - for R0.
3451 * The list is sorted ascending on address. */
3452 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3453 /** R0 pointer corresponding to PGM::pRomRangesR3. */
3454 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3455 RTR0PTR R0PtrAlignment0;
3456 /** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3457 R0PTRTYPE(PPGMREGMMIORANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3458
3459 /** RAM range TLB for RC. */
3460 RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3461 /** RC pointer corresponding to PGM::pRamRangesXR3. */
3462 RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3463 /** Root of the RAM range search tree for raw-mode context. */
3464 RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3465 /** PGM offset based trees - RC Ptr. */
3466 RCPTRTYPE(PPGMTREES) pTreesRC;
3467 /** Caching the last physical handler we looked up in RC. */
3468 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3469 /** Shadow Page Pool - RC Ptr. */
3470 RCPTRTYPE(PPGMPOOL) pPoolRC;
3471 /** Linked list of GC mappings - for RC.
3472 * The list is sorted ascending on address. */
3473 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3474 /** RC pointer corresponding to PGM::pRomRangesR3. */
3475 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3476 RTRCPTR RCPtrAlignment0;
3477 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3478 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3479 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3480 RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3481
3482
3483 /** Pointer to the 5 page CR3 content mapping.
3484 * The first page is always the CR3 (in some form) while the 4 other pages
3485 * are used for the PDs in PAE mode. */
3486 RTGCPTR GCPtrCR3Mapping;
3487
3488 /** @name Intermediate Context
3489 * @{ */
3490 /** Pointer to the intermediate page directory - Normal. */
3491 R3PTRTYPE(PX86PD) pInterPD;
3492 /** Pointer to the intermediate page tables - Normal.
3493 * There are two page tables, one for the identity mapping and one for
3494 * the host context mapping (of the core code). */
3495 R3PTRTYPE(PX86PT) apInterPTs[2];
3496 /** Pointer to the intermediate page tables - PAE. */
3497 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3498 /** Pointer to the intermediate page directory - PAE. */
3499 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3500 /** Pointer to the intermediate page directory - PAE. */
3501 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3502 /** Pointer to the intermediate page-map level 4 - AMD64. */
3503 R3PTRTYPE(PX86PML4) pInterPaePML4;
3504 /** Pointer to the intermediate page directory - AMD64. */
3505 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3506 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3507 RTHCPHYS HCPhysInterPD;
3508 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3509 RTHCPHYS HCPhysInterPaePDPT;
3510 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3511 RTHCPHYS HCPhysInterPaePML4;
3512 /** @} */
3513
3514 /** Base address of the dynamic page mapping area.
3515 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3516 *
3517 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3518 * work out. Some cleaning up of the initialization that would
3519 * remove this memory is yet to be done...
3520 */
3521 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3522 /** The address of the raw-mode context mapping cache. */
3523 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3524 /** The address of the ring-0 mapping cache if we're making use of it. */
3525 RTR0PTR pvR0DynMapUsed;
3526
3527 /** Hack: Number of deprecated page mapping locks taken by the current lock
3528 * owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3529 uint32_t cDeprecatedPageLocks;
3530#if HC_ARCH_BITS == 64
3531 /** Alignment padding. */
3532 uint32_t u32Alignment2;
3533#endif
3534
3535
3536 /** PGM critical section.
3537 * This protects the physical & virtual access handlers, ram ranges,
3538 * and the page flag updating (some of it anyway).
3539 */
3540 PDMCRITSECT CritSectX;
3541
3542 /**
3543 * Data associated with managing the ring-3 mappings of the allocation chunks.
3544 */
3545 struct
3546 {
3547 /** The chunk tree, ordered by chunk id. */
3548#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3549 R3PTRTYPE(PAVLU32NODECORE) pTree;
3550#else
3551 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3552#endif
3553#if HC_ARCH_BITS == 32
3554 uint32_t u32Alignment0;
3555#endif
3556 /** The chunk mapping TLB. */
3557 PGMCHUNKR3MAPTLB Tlb;
3558 /** The number of mapped chunks. */
3559 uint32_t c;
3560 /** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3561 * The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3562 * on 32-bit it defaults to 1 or 3 GB depending on the host. */
3563 uint32_t cMax;
3564 /** The current time. This is incremented whenever a chunk is inserted. */
3565 uint32_t iNow;
3566 /** Alignment padding. */
3567 uint32_t u32Alignment1;
3568 } ChunkR3Map;
3569
3570 /**
3571 * The page mapping TLB for ring-3 and (for the time being) ring-0.
3572 */
3573 PGMPAGER3MAPTLB PhysTlbHC;
3574
3575 /** @name The zero page.
3576 * @{ */
3577 /** The host physical address of the zero page. */
3578 RTHCPHYS HCPhysZeroPg;
3579 /** The ring-3 mapping of the zero page. */
3580 RTR3PTR pvZeroPgR3;
3581 /** The ring-0 mapping of the zero page. */
3582 RTR0PTR pvZeroPgR0;
3583 /** The GC mapping of the zero page. */
3584 RTRCPTR pvZeroPgRC;
3585 RTRCPTR RCPtrAlignment3;
3586 /** @}*/
3587
3588 /** @name The Invalid MMIO page.
3589 * This page is filled with 0xfeedface.
3590 * @{ */
3591 /** The host physical address of the invalid MMIO page. */
3592 RTHCPHYS HCPhysMmioPg;
3593 /** The host pysical address of the invalid MMIO page plus all invalid
3594 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3595 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3596 RTHCPHYS HCPhysInvMmioPg;
3597 /** The ring-3 mapping of the invalid MMIO page. */
3598 RTR3PTR pvMmioPgR3;
3599#if HC_ARCH_BITS == 32
3600 RTR3PTR R3PtrAlignment4;
3601#endif
3602 /** @} */
3603
3604
3605 /** The number of handy pages. */
3606 uint32_t cHandyPages;
3607
3608 /** The number of large handy pages. */
3609 uint32_t cLargeHandyPages;
3610
3611 /**
3612 * Array of handy pages.
3613 *
3614 * This array is used in a two way communication between pgmPhysAllocPage
3615 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3616 * an intermediary.
3617 *
3618 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3619 * (The current size of 32 pages, means 128 KB of handy memory.)
3620 */
3621 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3622
3623 /**
3624 * Array of large handy pages. (currently size 1)
3625 *
3626 * This array is used in a two way communication between pgmPhysAllocLargePage
3627 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3628 * an intermediary.
3629 */
3630 GMMPAGEDESC aLargeHandyPage[1];
3631
3632 /**
3633 * Live save data.
3634 */
3635 struct
3636 {
3637 /** Per type statistics. */
3638 struct
3639 {
3640 /** The number of ready pages. */
3641 uint32_t cReadyPages;
3642 /** The number of dirty pages. */
3643 uint32_t cDirtyPages;
3644 /** The number of ready zero pages. */
3645 uint32_t cZeroPages;
3646 /** The number of write monitored pages. */
3647 uint32_t cMonitoredPages;
3648 } Rom,
3649 Mmio2,
3650 Ram;
3651 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3652 uint32_t cIgnoredPages;
3653 /** Indicates that a live save operation is active. */
3654 bool fActive;
3655 /** Padding. */
3656 bool afReserved[2];
3657 /** The next history index. */
3658 uint8_t iDirtyPagesHistory;
3659 /** History of the total amount of dirty pages. */
3660 uint32_t acDirtyPagesHistory[64];
3661 /** Short term dirty page average. */
3662 uint32_t cDirtyPagesShort;
3663 /** Long term dirty page average. */
3664 uint32_t cDirtyPagesLong;
3665 /** The number of saved pages. This is used to get some kind of estimate of the
3666 * link speed so we can decide when we're done. It is reset after the first
3667 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3668 * zero pages. */
3669 uint64_t cSavedPages;
3670 /** The nanosecond timestamp when cSavedPages was 0. */
3671 uint64_t uSaveStartNS;
3672 /** Pages per second (for statistics). */
3673 uint32_t cPagesPerSecond;
3674 uint32_t cAlignment;
3675 } LiveSave;
3676
3677 /** @name Error injection.
3678 * @{ */
3679 /** Inject handy page allocation errors pretending we're completely out of
3680 * memory. */
3681 bool volatile fErrInjHandyPages;
3682 /** Padding. */
3683 bool afReserved[3];
3684 /** @} */
3685
3686 /** @name Release Statistics
3687 * @{ */
3688 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3689 uint32_t cPrivatePages; /**< The number of private pages. */
3690 uint32_t cSharedPages; /**< The number of shared pages. */
3691 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3692 uint32_t cZeroPages; /**< The number of zero backed pages. */
3693 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3694 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3695 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3696 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3697 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3698 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3699 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3700 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3701 uint32_t cLargePages; /**< The number of large pages. */
3702 uint32_t cLargePagesDisabled; /**< The number of disabled large pages. */
3703/* uint32_t aAlignment4[1]; */
3704
3705 /** The number of times we were forced to change the hypervisor region location. */
3706 STAMCOUNTER cRelocations;
3707
3708 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3709 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3710 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3711
3712 STAMPROFILE StatShModCheck; /**< Profiles shared module checks. */
3713 /** @} */
3714
3715#ifdef VBOX_WITH_STATISTICS
3716 /** @name Statistics on the heap.
3717 * @{ */
3718 R3PTRTYPE(PGMSTATS *) pStatsR3;
3719 R0PTRTYPE(PGMSTATS *) pStatsR0;
3720 RCPTRTYPE(PGMSTATS *) pStatsRC;
3721 RTRCPTR RCPtrAlignment;
3722 /** @} */
3723#endif
3724} PGM;
3725#ifndef IN_TSTVMSTRUCTGC /* HACK */
3726AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3727AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3728AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3729AssertCompileMemberAlignment(PGM, CritSectX, 8);
3730AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3731AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3732AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3733AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3734AssertCompileMemberAlignment(PGM, cRelocations, 8);
3735#endif /* !IN_TSTVMSTRUCTGC */
3736/** Pointer to the PGM instance data. */
3737typedef PGM *PPGM;
3738
3739
3740
3741typedef struct PGMCPUSTATS
3742{
3743 /* Common */
3744 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3745 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3746
3747 /* R0 only: */
3748 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3749 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3750
3751 /* RZ only: */
3752 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3753 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3754 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3755 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3756 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3757 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3758 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3759 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3760 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3761 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3762 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3763 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3764 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3765 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3766 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3767 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3768 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3769 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3770 STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. */
3771 STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. */
3772 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3773 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3774 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3775 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3776 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3777 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3778 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3779 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3780 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3781 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3782 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3783 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3784 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3785 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3786 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3787 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3788 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3789 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3790 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3791 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3792 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3793 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3794 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3795 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3796 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3797 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3798 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3799 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3800 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3801 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3802 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3803 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3804 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3805 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3806 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3807 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3808 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3809 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3810 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3811 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3812 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3813 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3814 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3815 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3816 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3817 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3818 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3819 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3820 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3821 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3822 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3823 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3824 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3825 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3826 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3827 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3828 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3829 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3830
3831 /* HC - R3 and (maybe) R0: */
3832
3833 /* RZ & R3: */
3834 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3835 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3836 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3837 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3838 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3839 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3840 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3841 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3842 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3843 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3844 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3845 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3846 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3847 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3848 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3849 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3850 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3851 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). */
3852 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3853 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3854 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3855 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3856 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3857 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3858 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3859 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3860 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3861 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3862 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3863 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3864 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3865 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3866 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3867 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3868 STAMCOUNTER StatRZInvalidatePageSizeChanges ; /**< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3869 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3870 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3871 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3872 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3873 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3874 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3875 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3876 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3877 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3878 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3879 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3880 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3881 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3882
3883 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3884 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3885 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3886 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3887 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3888 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3889 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3890 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3891 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3892 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3893 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3894 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3895 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3896 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3897 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3898 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3899 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3900 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3901 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3902 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3903 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3904 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3905 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3906 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3907 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3908 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3909 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3910 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3911 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3912 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3913 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3914 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3915 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3916 STAMCOUNTER StatR3InvalidatePageSizeChanges ; /**< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). */
3917 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3918 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3919 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3920 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3921 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3922 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3923 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3924 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3925 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3926 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3927 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3928 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3929 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3930 /** @} */
3931} PGMCPUSTATS;
3932
3933
3934/**
3935 * Converts a PGMCPU pointer into a VM pointer.
3936 * @returns Pointer to the VM structure the PGM is part of.
3937 * @param pPGM Pointer to PGMCPU instance data.
3938 */
3939#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3940
3941/**
3942 * Converts a PGMCPU pointer into a PGM pointer.
3943 * @returns Pointer to the VM structure the PGM is part of.
3944 * @param pPGMCpu Pointer to PGMCPU instance data.
3945 */
3946#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3947
3948/**
3949 * PGMCPU Data (part of VMCPU).
3950 */
3951typedef struct PGMCPU
3952{
3953 /** Offset to the VM structure. */
3954 int32_t offVM;
3955 /** Offset to the VMCPU structure. */
3956 int32_t offVCpu;
3957 /** Offset of the PGM structure relative to VMCPU. */
3958 int32_t offPGM;
3959 uint32_t uPadding0; /**< structure size alignment. */
3960
3961#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
3962 /** Automatically tracked physical memory mapping set.
3963 * Ring-0 and strict raw-mode builds. */
3964 PGMMAPSET AutoSet;
3965#endif
3966
3967 /** A20 gate mask.
3968 * Our current approach to A20 emulation is to let REM do it and don't bother
3969 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3970 * But whould need arrise, we'll subject physical addresses to this mask. */
3971 RTGCPHYS GCPhysA20Mask;
3972 /** A20 gate state - boolean! */
3973 bool fA20Enabled;
3974 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3975 bool fNoExecuteEnabled;
3976 /** Unused bits. */
3977 bool afUnused[2];
3978
3979 /** What needs syncing (PGM_SYNC_*).
3980 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3981 * PGMFlushTLB, and PGMR3Load. */
3982 uint32_t fSyncFlags;
3983
3984 /** The shadow paging mode. */
3985 PGMMODE enmShadowMode;
3986 /** The guest paging mode. */
3987 PGMMODE enmGuestMode;
3988 /** Guest mode data table index (PGM_TYPE_XXX). */
3989 uint8_t volatile idxGuestModeData;
3990 /** Shadow mode data table index (PGM_TYPE_XXX). */
3991 uint8_t volatile idxShadowModeData;
3992 /** Both mode data table index (complicated). */
3993 uint8_t volatile idxBothModeData;
3994 /** Alignment padding. */
3995 uint8_t abPadding[5];
3996
3997 /** The current physical address represented in the guest CR3 register. */
3998 RTGCPHYS GCPhysCR3;
3999
4000 /** @name 32-bit Guest Paging.
4001 * @{ */
4002 /** The guest's page directory, R3 pointer. */
4003 R3PTRTYPE(PX86PD) pGst32BitPdR3;
4004#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4005 /** The guest's page directory, R0 pointer. */
4006 R0PTRTYPE(PX86PD) pGst32BitPdR0;
4007#endif
4008 /** The guest's page directory, static RC mapping. */
4009 RCPTRTYPE(PX86PD) pGst32BitPdRC;
4010 /** Mask containing the MBZ bits of a big page PDE. */
4011 uint32_t fGst32BitMbzBigPdeMask;
4012 /** Set if the page size extension (PSE) is enabled. */
4013 bool fGst32BitPageSizeExtension;
4014 /** Alignment padding. */
4015 bool afAlignment2[3];
4016 /** @} */
4017
4018 /** @name PAE Guest Paging.
4019 * @{ */
4020 /** The guest's page directory pointer table, static RC mapping. */
4021 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
4022 /** The guest's page directory pointer table, R3 pointer. */
4023 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
4024#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4025 /** The guest's page directory pointer table, R0 pointer. */
4026 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
4027#endif
4028
4029 /** The guest's page directories, R3 pointers.
4030 * These are individual pointers and don't have to be adjacent.
4031 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
4032 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
4033 /** The guest's page directories, R0 pointers.
4034 * Same restrictions as apGstPaePDsR3. */
4035#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4036 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
4037#endif
4038 /** The guest's page directories, static GC mapping.
4039 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
4040 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
4041 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
4042 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
4043 * @todo Remove this and use aGstPaePdpeRegs instead? */
4044 RTGCPHYS aGCPhysGstPaePDs[4];
4045 /** The values of the 4 PDPE CPU registers (PAE). */
4046 X86PDPE aGstPaePdpeRegs[4];
4047 /** The physical addresses of the monitored guest page directories (PAE). */
4048 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
4049 /** Mask containing the MBZ PTE bits. */
4050 uint64_t fGstPaeMbzPteMask;
4051 /** Mask containing the MBZ PDE bits. */
4052 uint64_t fGstPaeMbzPdeMask;
4053 /** Mask containing the MBZ big page PDE bits. */
4054 uint64_t fGstPaeMbzBigPdeMask;
4055 /** Mask containing the MBZ PDPE bits. */
4056 uint64_t fGstPaeMbzPdpeMask;
4057 /** @} */
4058
4059 /** @name AMD64 Guest Paging.
4060 * @{ */
4061 /** The guest's page directory pointer table, R3 pointer. */
4062 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
4063#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
4064 /** The guest's page directory pointer table, R0 pointer. */
4065 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
4066#else
4067 RTR0PTR alignment6b; /**< alignment equalizer. */
4068#endif
4069 /** Mask containing the MBZ PTE bits. */
4070 uint64_t fGstAmd64MbzPteMask;
4071 /** Mask containing the MBZ PDE bits. */
4072 uint64_t fGstAmd64MbzPdeMask;
4073 /** Mask containing the MBZ big page PDE bits. */
4074 uint64_t fGstAmd64MbzBigPdeMask;
4075 /** Mask containing the MBZ PDPE bits. */
4076 uint64_t fGstAmd64MbzPdpeMask;
4077 /** Mask containing the MBZ big page PDPE bits. */
4078 uint64_t fGstAmd64MbzBigPdpeMask;
4079 /** Mask containing the MBZ PML4E bits. */
4080 uint64_t fGstAmd64MbzPml4eMask;
4081 /** Mask containing the PDPE bits that we shadow. */
4082 uint64_t fGstAmd64ShadowedPdpeMask;
4083 /** Mask containing the PML4E bits that we shadow. */
4084 uint64_t fGstAmd64ShadowedPml4eMask;
4085 /** @} */
4086
4087 /** @name PAE and AMD64 Guest Paging.
4088 * @{ */
4089 /** Mask containing the PTE bits that we shadow. */
4090 uint64_t fGst64ShadowedPteMask;
4091 /** Mask containing the PDE bits that we shadow. */
4092 uint64_t fGst64ShadowedPdeMask;
4093 /** Mask containing the big page PDE bits that we shadow in the PDE. */
4094 uint64_t fGst64ShadowedBigPdeMask;
4095 /** Mask containing the big page PDE bits that we shadow in the PTE. */
4096 uint64_t fGst64ShadowedBigPde4PteMask;
4097 /** @} */
4098
4099 /** Pointer to the page of the current active CR3 - R3 Ptr. */
4100 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
4101 /** Pointer to the page of the current active CR3 - R0 Ptr. */
4102 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
4103 /** Pointer to the page of the current active CR3 - RC Ptr. */
4104 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
4105 /** Explicit alignment. */
4106 RTRCPTR alignment6;
4107 /** @} */
4108
4109 /** For saving stack space, the disassembler state is allocated here instead of
4110 * on the stack. */
4111 DISCPUSTATE DisState;
4112
4113 /** Counts the number of times the netware WP0+RO+US hack has been applied. */
4114 uint64_t cNetwareWp0Hacks;
4115
4116 /** Count the number of pgm pool access handler calls. */
4117 uint64_t cPoolAccessHandler;
4118
4119 /** @name Release Statistics
4120 * @{ */
4121 /** The number of times the guest has switched mode since last reset or statistics reset. */
4122 STAMCOUNTER cGuestModeChanges;
4123 /** The number of times the guest has switched mode since last reset or statistics reset. */
4124 STAMCOUNTER cA20Changes;
4125 /** @} */
4126
4127#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
4128 /** @name Statistics
4129 * @{ */
4130 /** RC: Pointer to the statistics. */
4131 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
4132 /** RC: Which statistic this \#PF should be attributed to. */
4133 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
4134 /** R0: Pointer to the statistics. */
4135 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
4136 /** R0: Which statistic this \#PF should be attributed to. */
4137 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
4138 /** R3: Pointer to the statistics. */
4139 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
4140 /** Alignment padding. */
4141 RTR3PTR pPaddingR3;
4142 /** @} */
4143#endif /* VBOX_WITH_STATISTICS */
4144} PGMCPU;
4145/** Pointer to the per-cpu PGM data. */
4146typedef PGMCPU *PPGMCPU;
4147
4148
4149/** @name PGM::fSyncFlags Flags
4150 * @note Was part of saved state a long time ago.
4151 * @{
4152 */
4153/** Updates the virtual access handler state bit in PGMPAGE. */
4154#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
4155/** Always sync CR3. */
4156#define PGM_SYNC_ALWAYS RT_BIT(1)
4157/** Check monitoring on next CR3 (re)load and invalidate page.
4158 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
4159#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
4160/** Check guest mapping in SyncCR3. */
4161#define PGM_SYNC_MAP_CR3 RT_BIT(3)
4162/** Clear the page pool (a light weight flush). */
4163#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
4164#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
4165/** @} */
4166
4167
4168RT_C_DECLS_BEGIN
4169
4170#if defined(VBOX_STRICT) && defined(IN_RING3)
4171int pgmLockDebug(PVM pVM, RT_SRC_POS_DECL);
4172# define pgmLock(a_pVM) pgmLockDebug(a_pVM, RT_SRC_POS)
4173#else
4174int pgmLock(PVM pVM);
4175#endif
4176void pgmUnlock(PVM pVM);
4177/**
4178 * Asserts that the caller owns the PDM lock.
4179 * This is the internal variant of PGMIsLockOwner.
4180 * @param a_pVM Pointer to the VM.
4181 */
4182#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSectX))
4183/**
4184 * Asserts that the caller owns the PDM lock.
4185 * This is the internal variant of PGMIsLockOwner.
4186 * @param a_pVM Pointer to the VM.
4187 * @param a_pVCpu The current CPU handle.
4188 */
4189#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, a_pVCpu))
4190
4191#ifndef PGM_WITHOUT_MAPPINGS
4192int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
4193int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
4194int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
4195int pgmMapResolveConflicts(PVM pVM);
4196#endif /* !PGM_WITHOUT_MAPPINGS */
4197PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
4198DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4199
4200int pgmHandlerPhysicalExCreate(PVM pVM, PGMPHYSHANDLERTYPE hType, RTR3PTR pvUserR3, RTR0PTR pvUserR0,
4201 RTRCPTR pvUserRC, R3PTRTYPE(const char *) pszDesc, PPGMPHYSHANDLER *ppPhysHandler);
4202int pgmHandlerPhysicalExDup(PVM pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
4203int pgmHandlerPhysicalExRegister(PVM pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
4204int pgmHandlerPhysicalExDeregister(PVM pVM, PPGMPHYSHANDLER pPhysHandler, int fRestoreAsRAM);
4205int pgmHandlerPhysicalExDestroy(PVM pVM, PPGMPHYSHANDLER pHandler);
4206void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
4207bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
4208void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
4209#ifdef VBOX_WITH_RAW_MODE
4210PPGMVIRTHANDLER pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, unsigned *piPage);
4211DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
4212# if defined(VBOX_STRICT) || defined(LOG_ENABLED)
4213void pgmHandlerVirtualDumpPhysPages(PVM pVM);
4214# else
4215# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
4216# endif
4217#endif /* VBOX_WITH_RAW_MODE */
4218DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4219int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
4220
4221int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4222int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
4223int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
4224int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
4225int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4226void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4227int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4228int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4229int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4230int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
4231int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
4232int pgmPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4233int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4234int pgmPhysGCPhys2CCPtrInternalDepr(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4235int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
4236int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
4237void pgmPhysReleaseInternalPageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
4238PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
4239#ifndef IN_RING3
4240DECLEXPORT(FNPGMPHYSHANDLER) pgmPhysHandlerRedirectToHC;
4241DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysPfHandlerRedirectToHC;
4242DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
4243#endif
4244int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
4245 PGMPAGETYPE enmNewType);
4246void pgmPhysInvalidRamRangeTlbs(PVM pVM);
4247void pgmPhysInvalidatePageMapTLB(PVM pVM);
4248void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
4249PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
4250PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
4251PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
4252int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
4253int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
4254
4255#ifdef IN_RING3
4256void pgmR3PhysRelinkRamRanges(PVM pVM);
4257int pgmR3PhysRamPreAllocate(PVM pVM);
4258int pgmR3PhysRamReset(PVM pVM);
4259int pgmR3PhysRomReset(PVM pVM);
4260int pgmR3PhysRamZeroAll(PVM pVM);
4261int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
4262int pgmR3PhysRamTerm(PVM pVM);
4263void pgmR3PhysRomTerm(PVM pVM);
4264void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
4265
4266int pgmR3PoolInit(PVM pVM);
4267void pgmR3PoolRelocate(PVM pVM);
4268void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
4269void pgmR3PoolReset(PVM pVM);
4270void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
4271DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4272void pgmR3PoolWriteProtectPages(PVM pVM);
4273
4274#endif /* IN_RING3 */
4275#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
4276int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4277int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4278# ifdef LOG_ENABLED
4279void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
4280# else
4281void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
4282# endif
4283#endif
4284int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4285 uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4286void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4287void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4288int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4289void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4290PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4291PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4292int pgmPoolSyncCR3(PVMCPU pVCpu);
4293bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
4294void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
4295int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4296void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4297uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4298void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4299void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4300void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4301PGM_ALL_CB2_PROTO(FNPGMPHYSHANDLER) pgmPoolAccessHandler;
4302#ifndef IN_RING3
4303DECLEXPORT(FNPGMRZPHYSPFHANDLER) pgmRZPoolAccessPfHandler;
4304#endif
4305
4306void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4307void pgmPoolResetDirtyPages(PVM pVM);
4308void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
4309
4310int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4311int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4312void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4313
4314void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
4315void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
4316int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4317int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4318
4319int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4320int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4321int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4322
4323int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
4324int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
4325int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4326int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
4327int pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4328int pgmGstPtWalkNext(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4329
4330# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4331FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4332FNDBGCCMD pgmR3CmdShowSharedModules;
4333# endif
4334
4335void pgmLogState(PVM pVM);
4336
4337RT_C_DECLS_END
4338
4339/** @} */
4340
4341#endif
4342
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