PGMInternal.h@ 104407

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1	/* $Id: PGMInternal.h 100998 2023-08-31 19:53:44Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_PGMInternal_h
29	#define VMM_INCLUDED_SRC_include_PGMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#include <VBox/cdefs.h>
35	#include <VBox/types.h>
36	#include <VBox/err.h>
37	#include <VBox/dbg.h>
38	#include <VBox/vmm/stam.h>
39	#include <VBox/param.h>
40	#include <VBox/vmm/vmm.h>
41	#include <VBox/vmm/mm.h>
42	#include <VBox/vmm/pdmcritsect.h>
43	#include <VBox/vmm/pdmapi.h>
44	#include <VBox/dis.h>
45	#include <VBox/vmm/dbgf.h>
46	#include <VBox/log.h>
47	#include <VBox/vmm/gmm.h>
48	#include <VBox/vmm/hm.h>
49	#include <iprt/asm.h>
50	#include <iprt/assert.h>
51	#include <iprt/avl.h>
52	#include <iprt/critsect.h>
53	#include <iprt/list-off32.h>
54	#include <iprt/sha.h>
55	#include <iprt/cpp/hardavlrange.h>
56
57
58
59	/** @defgroup grp_pgm_int Internals
60	* @ingroup grp_pgm
61	* @internal
62	* @{
63	*/
64
65
66	/** @name PGM Compile Time Config
67	* @{
68	*/
69
70	/**
71	* Check and skip global PDEs for non-global flushes
72	*/
73	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
74
75	/**
76	* Optimization for PAE page tables that are modified often
77	*/
78	#ifndef VBOX_VMM_TARGET_ARMV8
79	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
80	#endif
81
82	/**
83	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
84	*/
85	#define PGM_WITH_LARGE_PAGES
86
87	/**
88	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
89	* VMX_EXIT_EPT_MISCONFIG.
90	*/
91	#define PGM_WITH_MMIO_OPTIMIZATIONS
92
93	/**
94	* Sync N pages instead of a whole page table
95	*/
96	#define PGM_SYNC_N_PAGES
97
98	/**
99	* Number of pages to sync during a page fault
100	*
101	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
102	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
103	*
104	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
105	* world switch overhead, so let's sync more.
106	*/
107	#ifdef IN_RING0
108	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
109	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
110	* but ~5% fewer faults.
111	*/
112	# define PGM_SYNC_NR_PAGES 32
113	#else
114	# define PGM_SYNC_NR_PAGES 8
115	#endif
116
117	/**
118	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
119	*/
120	#define PGM_MAX_PHYSCACHE_ENTRIES 64
121	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
122
123
124	/** @def PGMPOOL_CFG_MAX_GROW
125	* The maximum number of pages to add to the pool in one go.
126	*/
127	#define PGMPOOL_CFG_MAX_GROW (_2M >> GUEST_PAGE_SHIFT) /** @todo or HOST_PAGE_SHIFT ? */
128
129	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
130	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
131	*/
132	#ifdef VBOX_STRICT
133	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
134	#endif
135
136	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
137	* Enables the experimental lazy page allocation code.
138	* @todo Problems with zero page tracking, see \@bugref{10509}. */
139	#if defined(DOXYGEN_RUNNING)
140	# define VBOX_WITH_NEW_LAZY_PAGE_ALLOC
141	#endif
142
143	/** @def PGM_WITH_PAGE_ZEROING_DETECTION
144	* Enables the code for detecting guest zeroing page in the ZERO state and
145	* tries to avoid allocating them in response.
146	* This kind of relies upon VBOX_WITH_NEW_LAZY_PAGE_ALLOC to work atm. */
147	#if defined(DOXYGEN_RUNNING)
148	# define PGM_WITH_PAGE_ZEROING_DETECTION
149	#endif
150
151	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152	* Enables real write monitoring of pages, i.e. mapping them read-only and
153	* only making them writable when getting a write access \#PF. */
154	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
155
156	/** @def VBOX_WITH_PGM_NEM_MODE
157	* Enabled the NEM memory management mode in PGM. See PGM::fNemMode for
158	* details. */
159	#ifdef DOXYGEN_RUNNING
160	# define VBOX_WITH_PGM_NEM_MODE
161	#endif
162
163	/** @} */
164
165
166	/** @name PDPT and PML4 flags.
167	* These are placed in the three bits available for system programs in
168	* the PDPT and PML4 entries.
169	* @{ */
170	/** The entry is a permanent one and it's must always be present.
171	* Never free such an entry. */
172	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
173	/** PGM specific bits in PML4 entries. */
174	#define PGM_PML4_FLAGS 0
175	/** PGM specific bits in PDPT entries. */
176	#define PGM_PDPT_FLAGS (PGM_PLXFLAGS_PERMANENT)
177	/** @} */
178
179	/** @name Page directory flags.
180	* These are placed in the three bits available for system programs in
181	* the page directory entries.
182	* @{ */
183	/** Indicates the original entry was a big page.
184	* @remarks This is currently only used for statistics and can be recycled. */
185	#define PGM_PDFLAGS_BIG_PAGE RT_BIT_64(9)
186	/** Made read-only to facilitate dirty bit tracking. */
187	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
188	/** @} */
189
190	/** @name Page flags.
191	* These are placed in the three bits available for system programs in
192	* the page entries.
193	* @{ */
194	/** Made read-only to facilitate dirty bit tracking. */
195	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
196	/** @} */
197
198	/** @name Defines used to indicate the shadow and guest paging in the templates.
199	* @{ */
200	#define PGM_TYPE_REAL 1
201	#define PGM_TYPE_PROT 2
202	#define PGM_TYPE_32BIT 3
203	#define PGM_TYPE_PAE 4
204	#define PGM_TYPE_AMD64 5
205	#define PGM_TYPE_NESTED_32BIT 6
206	#define PGM_TYPE_NESTED_PAE 7
207	#define PGM_TYPE_NESTED_AMD64 8
208	#define PGM_TYPE_EPT 9
209	#define PGM_TYPE_NONE 10 /*< Dummy shadow paging mode for NEM. /
210	#define PGM_TYPE_END (PGM_TYPE_NONE + 1)
211	#define PGM_TYPE_FIRST_SHADOW PGM_TYPE_32BIT /*< The first type used by shadow paging. /
212	/** @} */
213
214	/** @name Defines used to indicate the second-level
215	* address translation (SLAT) modes in the templates.
216	* @{ */
217	#define PGM_SLAT_TYPE_DIRECT (PGM_TYPE_END + 1)
218	#define PGM_SLAT_TYPE_EPT (PGM_TYPE_END + 2)
219	#define PGM_SLAT_TYPE_32BIT (PGM_TYPE_END + 3)
220	#define PGM_SLAT_TYPE_PAE (PGM_TYPE_END + 4)
221	#define PGM_SLAT_TYPE_AMD64 (PGM_TYPE_END + 5)
222	/** @} */
223
224	/** Macro for checking if the guest is using paging.
225	* @param uGstType PGM_TYPE_*
226	* @param uShwType PGM_TYPE_*
227	* @remark ASSUMES certain order of the PGM_TYPE_* values.
228	*/
229	#define PGM_WITH_PAGING(uGstType, uShwType) \
230	( (uGstType) >= PGM_TYPE_32BIT \
231	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
232
233	/** Macro for checking if the guest supports the NX bit.
234	* @param uGstType PGM_TYPE_*
235	* @param uShwType PGM_TYPE_*
236	* @remark ASSUMES certain order of the PGM_TYPE_* values.
237	*/
238	#define PGM_WITH_NX(uGstType, uShwType) \
239	( (uGstType) >= PGM_TYPE_PAE \
240	&& (uShwType) < PGM_TYPE_NESTED_32BIT)
241
242	/** Macro for checking for nested.
243	* @param uType PGM_TYPE_*
244	*/
245	#define PGM_TYPE_IS_NESTED(uType) \
246	( (uType) == PGM_TYPE_NESTED_32BIT \
247	\|\| (uType) == PGM_TYPE_NESTED_PAE \
248	\|\| (uType) == PGM_TYPE_NESTED_AMD64)
249
250	/** Macro for checking for nested or EPT.
251	* @param uType PGM_TYPE_*
252	*/
253	#define PGM_TYPE_IS_NESTED_OR_EPT(uType) \
254	( (uType) == PGM_TYPE_NESTED_32BIT \
255	\|\| (uType) == PGM_TYPE_NESTED_PAE \
256	\|\| (uType) == PGM_TYPE_NESTED_AMD64 \
257	\|\| (uType) == PGM_TYPE_EPT)
258
259
260
261	/** @def PGM_HCPHYS_2_PTR
262	* Maps a HC physical page pool address to a virtual address.
263	*
264	* @returns VBox status code.
265	* @param pVM The cross context VM structure.
266	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
267	* @param HCPhys The HC physical address to map to a virtual one.
268	* @param ppv Where to store the virtual address. No need to cast
269	* this.
270	*
271	* @remark There is no need to assert on the result.
272	*/
273	#define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) pgmPoolHCPhys2Ptr(pVM, HCPhys, (void **)(ppv))
274
275	/** @def PGM_GCPHYS_2_PTR_V2
276	* Maps a GC physical page address to a virtual address.
277	*
278	* @returns VBox status code.
279	* @param pVM The cross context VM structure.
280	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
281	* @param GCPhys The GC physical address to map to a virtual one.
282	* @param ppv Where to store the virtual address. No need to cast this.
283	*
284	* @remark Use with care as we don't have so much dynamic mapping space in
285	* ring-0 on 32-bit darwin and in RC.
286	* @remark There is no need to assert on the result.
287	*/
288	#define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
289	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
290
291	/** @def PGM_GCPHYS_2_PTR
292	* Maps a GC physical page address to a virtual address.
293	*
294	* @returns VBox status code.
295	* @param pVM The cross context VM structure.
296	* @param GCPhys The GC physical address to map to a virtual one.
297	* @param ppv Where to store the virtual address. No need to cast this.
298	*
299	* @remark Use with care as we don't have so much dynamic mapping space in
300	* ring-0 on 32-bit darwin and in RC.
301	* @remark There is no need to assert on the result.
302	*/
303	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
304
305	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
306	* Maps a GC physical page address to a virtual address.
307	*
308	* @returns VBox status code.
309	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
310	* @param GCPhys The GC physical address to map to a virtual one.
311	* @param ppv Where to store the virtual address. No need to cast this.
312	*
313	* @remark Use with care as we don't have so much dynamic mapping space in
314	* ring-0 on 32-bit darwin and in RC.
315	* @remark There is no need to assert on the result.
316	*/
317	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
318
319	/** @def PGM_GCPHYS_2_PTR_EX
320	* Maps a unaligned GC physical page address to a virtual address.
321	*
322	* @returns VBox status code.
323	* @param pVM The cross context VM structure.
324	* @param GCPhys The GC physical address to map to a virtual one.
325	* @param ppv Where to store the virtual address. No need to cast this.
326	*
327	* @remark Use with care as we don't have so much dynamic mapping space in
328	* ring-0 on 32-bit darwin and in RC.
329	* @remark There is no need to assert on the result.
330	*/
331	#define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
332	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
333
334	/** @def PGM_DYNMAP_UNUSED_HINT
335	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
336	* is no longer used.
337	*
338	* For best effect only apply this to the page that was mapped most recently.
339	*
340	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
341	* @param pvPage The pool page.
342	*/
343	#define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
344
345	/** @def PGM_DYNMAP_UNUSED_HINT_VM
346	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
347	* is no longer used.
348	*
349	* For best effect only apply this to the page that was mapped most recently.
350	*
351	* @param pVM The cross context VM structure.
352	* @param pvPage The pool page.
353	*/
354	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
355
356
357	/** @def PGM_INVL_PG
358	* Invalidates a page.
359	*
360	* @param pVCpu The cross context virtual CPU structure.
361	* @param GCVirt The virtual address of the page to invalidate.
362	*/
363	#ifdef IN_RING0
364	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
365	#elif defined(IN_RING3)
366	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
367	#else
368	# error "Not IN_RING0 or IN_RING3!"
369	#endif
370
371	/** @def PGM_INVL_PG_ALL_VCPU
372	* Invalidates a page on all VCPUs
373	*
374	* @param pVM The cross context VM structure.
375	* @param GCVirt The virtual address of the page to invalidate.
376	*/
377	#if defined(VBOX_VMM_TARGET_ARMV8)
378	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) do { } while(0)
379	#else
380	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
381	#endif
382
383	/** @def PGM_INVL_BIG_PG
384	* Invalidates a 4MB page directory entry.
385	*
386	* @param pVCpu The cross context virtual CPU structure.
387	* @param GCVirt The virtual address within the page directory to invalidate.
388	*/
389	#if defined(VBOX_VMM_TARGET_ARMV8)
390	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) do { } while(0)
391	#else
392	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTlb(pVCpu)
393	#endif
394
395	/** @def PGM_INVL_VCPU_TLBS()
396	* Invalidates the TLBs of the specified VCPU
397	*
398	* @param pVCpu The cross context virtual CPU structure.
399	*/
400	#if defined(VBOX_VMM_TARGET_ARMV8)
401	# define PGM_INVL_VCPU_TLBS(pVCpu) do { } while(0)
402	#else
403	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTlb(pVCpu)
404	#endif
405
406	/** @def PGM_INVL_ALL_VCPU_TLBS()
407	* Invalidates the TLBs of all VCPUs
408	*
409	* @param pVM The cross context VM structure.
410	*/
411	#if defined(VBOX_VMM_TARGET_ARMV8)
412	# define PGM_INVL_ALL_VCPU_TLBS(pVM) do { } while(0)
413	#else
414	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTlbOnAllVCpus(pVM)
415	#endif
416
417
418	/** @name Safer Shadow PAE PT/PTE
419	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
420	* present.
421	*
422	* @{
423	*/
424	#if 1
425	/**
426	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
427	* invalid entries for present.
428	* @sa X86PTEPAE.
429	*/
430	typedef union PGMSHWPTEPAE
431	{
432	/** Unsigned integer view */
433	X86PGPAEUINT uCareful;
434	/* Not other views. */
435	} PGMSHWPTEPAE;
436
437	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
438	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
439	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
440	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
441	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
442	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
443	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
444	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
445	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
446	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
447	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
448	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
449	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
450	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
451	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
452	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
453
454	/**
455	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
456	* invalid entries for present.
457	* @sa X86PTPAE.
458	*/
459	typedef struct PGMSHWPTPAE
460	{
461	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
462	} PGMSHWPTPAE;
463
464	#else
465	typedef X86PTEPAE PGMSHWPTEPAE;
466	typedef X86PTPAE PGMSHWPTPAE;
467	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
468	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
469	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
470	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
471	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
472	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
473	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
474	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
475	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
476	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
477	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
478	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
479	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
480	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
481	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
482	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
483
484	#endif
485
486	/** Pointer to a shadow PAE PTE. */
487	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
488	/** Pointer to a const shadow PAE PTE. */
489	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
490
491	/** Pointer to a shadow PAE page table. */
492	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
493	/** Pointer to a const shadow PAE page table. */
494	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
495	/** @} */
496
497
498	/** The physical access handler type handle count (power of two). */
499	#define PGMPHYSHANDLERTYPE_COUNT 0x20
500	/** Mask for getting the array index from an access handler type handle.
501	* The other handle bits are random and non-zero to avoid mixups due to zero
502	* initialized fields. */
503	#define PGMPHYSHANDLERTYPE_IDX_MASK 0x1f
504
505	/**
506	* Physical page access handler type registration, ring-0 part.
507	*/
508	typedef struct PGMPHYSHANDLERTYPEINTR0
509	{
510	/** The handle value for verfication. */
511	PGMPHYSHANDLERTYPE hType;
512	/** The kind of accesses we're handling. */
513	PGMPHYSHANDLERKIND enmKind;
514	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
515	uint8_t uState;
516	/** Whether to keep the PGM lock when calling the handler.
517	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
518	bool fKeepPgmLock;
519	/** Set if this is registered by a device instance and uUser should be
520	* translated from a device instance ID to a pointer.
521	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
522	bool fRing0DevInsIdx;
523	/** See PGMPHYSHANDLER_F_NOT_IN_HM. */
524	bool fNotInHm : 1;
525	/** Pointer to the ring-0 callback function. */
526	R0PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
527	/** Pointer to the ring-0 callback function for \#PFs, can be NULL. */
528	R0PTRTYPE(PFNPGMRZPHYSPFHANDLER) pfnPfHandler;
529	/** Description / Name. For easing debugging. */
530	R0PTRTYPE(const char *) pszDesc;
531	} PGMPHYSHANDLERTYPEINTR0;
532	/** Pointer to a physical access handler type registration. */
533	typedef PGMPHYSHANDLERTYPEINTR0 *PPGMPHYSHANDLERTYPEINTR0;
534
535	/**
536	* Physical page access handler type registration, shared/ring-3 part.
537	*/
538	typedef struct PGMPHYSHANDLERTYPEINTR3
539	{
540	/** The handle value for verfication. */
541	PGMPHYSHANDLERTYPE hType;
542	/** The kind of accesses we're handling. */
543	PGMPHYSHANDLERKIND enmKind;
544	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
545	uint8_t uState;
546	/** Whether to keep the PGM lock when calling the handler.
547	* @sa PGMPHYSHANDLER_F_KEEP_PGM_LOCK */
548	bool fKeepPgmLock;
549	/** Set if this is registered by a device instance and uUser should be
550	* translated from a device instance ID to a pointer.
551	* @sa PGMPHYSHANDLER_F_R0_DEVINS_IDX */
552	bool fRing0DevInsIdx;
553	/** Set by ring-0 if the handler is ring-0 enabled (for debug). */
554	bool fRing0Enabled : 1;
555	/** See PGMPHYSHANDLER_F_NOT_IN_HM. */
556	bool fNotInHm : 1;
557	/** Pointer to the ring-3 callback function. */
558	R3PTRTYPE(PFNPGMPHYSHANDLER) pfnHandler;
559	/** Description / Name. For easing debugging. */
560	R3PTRTYPE(const char *) pszDesc;
561	} PGMPHYSHANDLERTYPEINTR3;
562	/** Pointer to a physical access handler type registration. */
563	typedef PGMPHYSHANDLERTYPEINTR3 *PPGMPHYSHANDLERTYPEINTR3;
564
565	/** Pointer to a physical access handler type record for the current context. */
566	typedef CTX_SUFF(PPGMPHYSHANDLERTYPEINT) PPGMPHYSHANDLERTYPEINT;
567	/** Pointer to a const physical access handler type record for the current context. */
568	typedef CTX_SUFF(PGMPHYSHANDLERTYPEINT) const *PCPGMPHYSHANDLERTYPEINT;
569	/** Dummy physical access handler type record. */
570	extern CTX_SUFF(PGMPHYSHANDLERTYPEINT) const g_pgmHandlerPhysicalDummyType;
571
572
573	/**
574	* Physical page access handler structure.
575	*
576	* This is used to keep track of physical address ranges
577	* which are being monitored in some kind of way.
578	*/
579	typedef struct PGMPHYSHANDLER
580	{
581	/** @name Tree stuff.
582	* @{ */
583	/** First address. */
584	RTGCPHYS Key;
585	/** Last address. */
586	RTGCPHYS KeyLast;
587	uint32_t idxLeft;
588	uint32_t idxRight;
589	uint8_t cHeight;
590	/** @} */
591	uint8_t abPadding[3];
592	/** Number of pages to update. */
593	uint32_t cPages;
594	/** Set if we have pages that have been aliased. */
595	uint32_t cAliasedPages;
596	/** Set if we have pages that have temporarily been disabled. */
597	uint32_t cTmpOffPages;
598	/** Registered handler type handle.
599	* @note Marked volatile to prevent re-reading after validation. */
600	PGMPHYSHANDLERTYPE volatile hType;
601	/** User argument for the handlers. */
602	uint64_t uUser;
603	/** Description / Name. For easing debugging. */
604	R3PTRTYPE(const char *) pszDesc;
605	/** Profiling of this handler.
606	* @note VBOX_WITH_STATISTICS only, but included to keep structure stable. */
607	STAMPROFILE Stat;
608	} PGMPHYSHANDLER;
609	AssertCompileSize(PGMPHYSHANDLER, 12*8);
610	/** Pointer to a physical page access handler structure. */
611	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
612
613	/**
614	* Gets the type record for a physical handler (no reference added).
615	* @returns PCPGMPHYSHANDLERTYPEINT, can be NULL
616	* @param a_pVM The cross context VM structure.
617	* @param a_pPhysHandler Pointer to the physical handler structure
618	* (PGMPHYSHANDLER).
619	*/
620	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) \
621	pgmHandlerPhysicalTypeHandleToPtr(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
622
623	/**
624	* Gets the type record for a physical handler, never returns NULL.
625	*
626	* @returns PCPGMPHYSHANDLERTYPEINT, never NULL.
627	* @param a_pVM The cross context VM structure.
628	* @param a_pPhysHandler Pointer to the physical handler structure
629	* (PGMPHYSHANDLER).
630	*/
631	#define PGMPHYSHANDLER_GET_TYPE_NO_NULL(a_pVM, a_pPhysHandler) \
632	pgmHandlerPhysicalTypeHandleToPtr2(a_pVM, (a_pPhysHandler) ? (a_pPhysHandler)->hType : NIL_PGMPHYSHANDLERTYPE)
633
634	/** Physical access handler allocator. */
635	typedef RTCHardAvlTreeSlabAllocator<PGMPHYSHANDLER> PGMPHYSHANDLERALLOCATOR;
636
637	/** Physical access handler tree. */
638	typedef RTCHardAvlRangeTree<PGMPHYSHANDLER, RTGCPHYS> PGMPHYSHANDLERTREE;
639	/** Pointer to a physical access handler tree. */
640	typedef PGMPHYSHANDLERTREE *PPGMPHYSHANDLERTREE;
641
642
643	/**
644	* A Physical Guest Page tracking structure.
645	*
646	* The format of this structure is complicated because we have to fit a lot
647	* of information into as few bits as possible. The format is also subject
648	* to change (there is one coming up soon). Which means that for we'll be
649	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
650	* accesses to the structure.
651	*/
652	typedef union PGMPAGE
653	{
654	/** Structured view. */
655	struct
656	{
657	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
658	uint64_t u2HandlerPhysStateY : 2;
659	/** 2 - Don't apply the physical handler in HM mode (nested APIC hack). */
660	uint64_t fHandlerPhysNotInHm : 1;
661	/** 3 - Flag indicating that a write monitored page was written to when set. */
662	uint64_t fWrittenToY : 1;
663	/** 4 - Set when the page is write monitored because it's an IEM TB code
664	* page. Save recompiled code the need to verify opcode bytes.
665	*
666	* IEM fetches this flag as part of the TLB queries. The flag is cleared when
667	* the page is made writable and IEM is informed and will invalidate its
668	* physical TLB layer.
669	*
670	* @note Can possibly be set on ROM pages that are not in the monitored state. */
671	uint64_t fCodePageY : 1;
672	/** 7:5 - Unused. */
673	uint64_t u2Unused0 : 3;
674	/** 9:8 - Paging structure needed to map the page
675	* (PGM_PAGE_PDE_TYPE_). /
676	uint64_t u2PDETypeY : 2;
677	/** 11:10 - NEM state bits. */
678	uint64_t u2NemStateY : 2;
679	/** 12:48 - The host physical frame number (shift left to get the
680	* address). */
681	uint64_t HCPhysFN : 36;
682	/** 50:48 - The page state. */
683	uint64_t uStateY : 3;
684	/** 51:53 - The page type (PGMPAGETYPE). */
685	uint64_t uTypeY : 3;
686	/** 63:54 - PTE index for usage tracking (page pool). */
687	uint64_t u10PteIdx : 10;
688
689	/** The GMM page ID.
690	* @remarks In the current implementation, MMIO2 and pages aliased to
691	* MMIO2 pages will be exploiting this field to calculate the
692	* ring-3 mapping address corresponding to the page.
693	* Later we may consider including MMIO2 management into GMM. */
694	uint32_t idPage;
695	/** Usage tracking (page pool). */
696	uint16_t u16TrackingY;
697	/** The number of read locks on this page. */
698	uint8_t cReadLocksY;
699	/** The number of write locks on this page. */
700	uint8_t cWriteLocksY;
701	} s;
702
703	/** 64-bit integer view. */
704	uint64_t au64[2];
705	/** 16-bit view. */
706	uint32_t au32[4];
707	/** 16-bit view. */
708	uint16_t au16[8];
709	/** 8-bit view. */
710	uint8_t au8[16];
711	} PGMPAGE;
712	AssertCompileSize(PGMPAGE, 16);
713	/** Pointer to a physical guest page. */
714	typedef PGMPAGE *PPGMPAGE;
715	/** Pointer to a const physical guest page. */
716	typedef const PGMPAGE *PCPGMPAGE;
717	/** Pointer to a physical guest page pointer. */
718	typedef PPGMPAGE *PPPGMPAGE;
719
720
721	/**
722	* Clears the page structure.
723	* @param a_pPage Pointer to the physical guest page tracking structure.
724	*/
725	#define PGM_PAGE_CLEAR(a_pPage) \
726	do { \
727	(a_pPage)->au64[0] = 0; \
728	(a_pPage)->au64[1] = 0; \
729	} while (0)
730
731	/**
732	* Initializes the page structure.
733	* @param a_pPage Pointer to the physical guest page tracking structure.
734	* @param a_HCPhys The host physical address of the page.
735	* @param a_idPage The (GMM) page ID of the page.
736	* @param a_uType The page type (PGMPAGETYPE).
737	* @param a_uState The page state (PGM_PAGE_STATE_XXX).
738	*/
739	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
740	do { \
741	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
742	AssertFatalMsg(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000)), ("%RHp\n", SetHCPhysTmp)); \
743	(a_pPage)->au64[0] = SetHCPhysTmp; \
744	(a_pPage)->au64[1] = 0; \
745	(a_pPage)->s.idPage = (a_idPage); \
746	(a_pPage)->s.uStateY = (a_uState); \
747	(a_pPage)->s.uTypeY = (a_uType); \
748	} while (0)
749
750	/**
751	* Initializes the page structure of a ZERO page.
752	* @param a_pPage Pointer to the physical guest page tracking structure.
753	* @param a_pVM The VM handle (for getting the zero page address).
754	* @param a_uType The page type (PGMPAGETYPE).
755	*/
756	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
757	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
758
759
760	/** @name The Page state, PGMPAGE::uStateY.
761	* @{ */
762	/** The zero page.
763	* This is a per-VM page that's never ever mapped writable. */
764	#define PGM_PAGE_STATE_ZERO 0U
765	/** A allocated page.
766	* This is a per-VM page allocated from the page pool (or wherever
767	* we get MMIO2 pages from if the type is MMIO2).
768	*/
769	#define PGM_PAGE_STATE_ALLOCATED 1U
770	/** A allocated page that's being monitored for writes.
771	* The shadow page table mappings are read-only. When a write occurs, the
772	* fWrittenTo member is set, the page remapped as read-write and the state
773	* moved back to allocated. */
774	#define PGM_PAGE_STATE_WRITE_MONITORED 2U
775	/** The page is shared, aka. copy-on-write.
776	* This is a page that's shared with other VMs. */
777	#define PGM_PAGE_STATE_SHARED 3U
778	/** The page is ballooned, so no longer available for this VM. */
779	#define PGM_PAGE_STATE_BALLOONED 4U
780	/** @} */
781
782
783	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
784	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
785	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
786	#else
787	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
788	#endif
789
790	/**
791	* Gets the page state.
792	* @returns page state (PGM_PAGE_STATE_*).
793	* @param a_pPage Pointer to the physical guest page tracking structure.
794	*
795	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
796	* builds.
797	*/
798	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
799	#if defined(__GNUC__) && defined(VBOX_STRICT)
800	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
801	#else
802	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
803	#endif
804
805	/**
806	* Sets the page state.
807	* @param a_pVM The VM handle, only used for lock ownership assertions.
808	* @param a_pPage Pointer to the physical guest page tracking structure.
809	* @param a_uState The new page state.
810	*/
811	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
812	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
813
814
815	/**
816	* Gets the host physical address of the guest page.
817	* @returns host physical address (RTHCPHYS).
818	* @param a_pPage Pointer to the physical guest page tracking structure.
819	*
820	* @remarks In strict builds on gcc platforms, this macro will make some ugly
821	* assumption about a valid pVM variable/parameter being in the
822	* current context. It will use this pVM variable to assert that the
823	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
824	* pVM is not around.
825	*/
826	#if 0
827	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
828	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
829	#else
830	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
831	# if defined(__GNUC__) && defined(VBOX_STRICT)
832	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
833	# else
834	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
835	# endif
836	#endif
837
838	/**
839	* Sets the host physical address of the guest page.
840	*
841	* @param a_pVM The VM handle, only used for lock ownership assertions.
842	* @param a_pPage Pointer to the physical guest page tracking structure.
843	* @param a_HCPhys The new host physical address.
844	*/
845	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
846	do { \
847	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
848	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
849	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
850	PGM_PAGE_ASSERT_LOCK(a_pVM); \
851	} while (0)
852
853	/**
854	* Get the Page ID.
855	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
856	* @param a_pPage Pointer to the physical guest page tracking structure.
857	*/
858	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
859
860	/**
861	* Sets the Page ID.
862	* @param a_pVM The VM handle, only used for lock ownership assertions.
863	* @param a_pPage Pointer to the physical guest page tracking structure.
864	* @param a_idPage The new page ID.
865	*/
866	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
867	do { \
868	(a_pPage)->s.idPage = (a_idPage); \
869	PGM_PAGE_ASSERT_LOCK(a_pVM); \
870	} while (0)
871
872	/**
873	* Get the Chunk ID.
874	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
875	* @param a_pPage Pointer to the physical guest page tracking structure.
876	*/
877	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
878
879	/**
880	* Get the index of the page within the allocation chunk.
881	* @returns The page index.
882	* @param a_pPage Pointer to the physical guest page tracking structure.
883	*/
884	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
885
886	/**
887	* Gets the page type.
888	* @returns The page type.
889	* @param a_pPage Pointer to the physical guest page tracking structure.
890	*
891	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
892	* builds.
893	*/
894	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
895	#if defined(__GNUC__) && defined(VBOX_STRICT)
896	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
897	#else
898	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
899	#endif
900
901	/**
902	* Sets the page type.
903	*
904	* @param a_pVM The VM handle, only used for lock ownership assertions.
905	* @param a_pPage Pointer to the physical guest page tracking structure.
906	* @param a_enmType The new page type (PGMPAGETYPE).
907	*/
908	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
909	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
910
911	/**
912	* Gets the page table index
913	* @returns The page table index.
914	* @param a_pPage Pointer to the physical guest page tracking structure.
915	*/
916	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
917
918	/**
919	* Sets the page table index.
920	* @param a_pVM The VM handle, only used for lock ownership assertions.
921	* @param a_pPage Pointer to the physical guest page tracking structure.
922	* @param a_iPte New page table index.
923	*/
924	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
925	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
926
927	/**
928	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
929	* @returns true/false.
930	* @param a_pPage Pointer to the physical guest page tracking structure.
931	*/
932	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
933
934	/**
935	* Checks if the page is marked for MMIO, including both aliases.
936	* @returns true/false.
937	* @param a_pPage Pointer to the physical guest page tracking structure.
938	*/
939	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
940	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
941	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
942	)
943
944	/**
945	* Checks if the page is marked for MMIO, including special aliases.
946	* @returns true/false.
947	* @param a_pPage Pointer to the physical guest page tracking structure.
948	*/
949	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
950	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
951
952	/**
953	* Checks if the page is a special aliased MMIO page.
954	* @returns true/false.
955	* @param a_pPage Pointer to the physical guest page tracking structure.
956	*/
957	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
958
959	/**
960	* Checks if the page is backed by the ZERO page.
961	* @returns true/false.
962	* @param a_pPage Pointer to the physical guest page tracking structure.
963	*/
964	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
965
966	/**
967	* Checks if the page is backed by a SHARED page.
968	* @returns true/false.
969	* @param a_pPage Pointer to the physical guest page tracking structure.
970	*/
971	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
972
973	/**
974	* Checks if the page is ballooned.
975	* @returns true/false.
976	* @param a_pPage Pointer to the physical guest page tracking structure.
977	*/
978	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
979
980	/**
981	* Checks if the page is allocated.
982	* @returns true/false.
983	* @param a_pPage Pointer to the physical guest page tracking structure.
984	*/
985	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
986
987
988	/**
989	* Marks the page as written to (for GMM change monitoring).
990	* @param a_pVM The VM handle, only used for lock ownership assertions.
991	* @param a_pPage Pointer to the physical guest page tracking structure.
992	*/
993	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
994	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
995
996	/**
997	* Clears the written-to indicator.
998	* @param a_pVM The VM handle, only used for lock ownership assertions.
999	* @param a_pPage Pointer to the physical guest page tracking structure.
1000	*/
1001	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1002	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1003
1004	/**
1005	* Checks if the page was marked as written-to.
1006	* @returns true/false.
1007	* @param a_pPage Pointer to the physical guest page tracking structure.
1008	*/
1009	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1010
1011
1012	/**
1013	* Marks the page as an IEM code page (being write monitored or a ROM page).
1014	* @param a_pVM The VM handle, only used for lock ownership assertions.
1015	* @param a_pPage Pointer to the physical guest page tracking structure.
1016	*/
1017	#define PGM_PAGE_SET_CODE_PAGE(a_pVM, a_pPage) \
1018	do { (a_pPage)->s.fCodePageY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1019
1020	/**
1021	* Clears the code page indicator.
1022	* @param a_pVM The VM handle, only used for lock ownership assertions.
1023	* @param a_pPage Pointer to the physical guest page tracking structure.
1024	*/
1025	#define PGM_PAGE_CLEAR_CODE_PAGE(a_pVM, a_pPage) \
1026	do { (a_pPage)->s.fCodePageY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1027
1028	/**
1029	* Checks if the page is an IEM code page (implies write monitored or ROM page).
1030	* @returns true/false.
1031	* @param a_pPage Pointer to the physical guest page tracking structure.
1032	*/
1033	#define PGM_PAGE_IS_CODE_PAGE(a_pPage) ( (a_pPage)->s.fCodePageY )
1034
1035
1036	/** @name PT usage values (PGMPAGE::u2PDEType).
1037	*
1038	* @{ */
1039	/** Either as a PT or PDE. */
1040	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1041	/** Must use a page table to map the range. */
1042	#define PGM_PAGE_PDE_TYPE_PT 1
1043	/** Can use a page directory entry to map the continuous range. */
1044	#define PGM_PAGE_PDE_TYPE_PDE 2
1045	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1046	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1047	/** @} */
1048
1049	/**
1050	* Set the PDE type of the page
1051	* @param a_pVM The VM handle, only used for lock ownership assertions.
1052	* @param a_pPage Pointer to the physical guest page tracking structure.
1053	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1054	*/
1055	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1056	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1057
1058	/**
1059	* Checks if the page was marked being part of a large page
1060	* @returns true/false.
1061	* @param a_pPage Pointer to the physical guest page tracking structure.
1062	*/
1063	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1064
1065	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1066	*
1067	* @remarks The values are assigned in order of priority, so we can calculate
1068	* the correct state for a page with different handlers installed.
1069	* @{ */
1070	/** No handler installed. */
1071	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1072	/** Monitoring is temporarily disabled. */
1073	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1074	/** Write access is monitored. */
1075	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1076	/** All access is monitored. */
1077	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1078	/** @} */
1079
1080	/**
1081	* Gets the physical access handler state of a page.
1082	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1083	* @param a_pPage Pointer to the physical guest page tracking structure.
1084	*/
1085	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1086
1087	/**
1088	* Sets the physical access handler state of a page.
1089	* @param a_pPage Pointer to the physical guest page tracking structure.
1090	* @param a_uState The new state value.
1091	* @param a_fNotInHm The PGMPHYSHANDLER_F_NOT_HM bit.
1092	*/
1093	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState, a_fNotInHm) \
1094	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); (a_pPage)->s.fHandlerPhysNotInHm = (a_fNotInHm); } while (0)
1095
1096	/**
1097	* Sets the physical access handler state of a page.
1098	* @param a_pPage Pointer to the physical guest page tracking structure.
1099	* @param a_uState The new state value.
1100	*/
1101	#define PGM_PAGE_SET_HNDL_PHYS_STATE_ONLY(a_pPage, a_uState) \
1102	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1103
1104	/**
1105	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1106	* @returns true/false
1107	* @param a_pPage Pointer to the physical guest page tracking structure.
1108	*/
1109	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1110	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1111
1112	/**
1113	* Checks if the page has any active physical access handlers.
1114	* @returns true/false
1115	* @param a_pPage Pointer to the physical guest page tracking structure.
1116	*/
1117	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1118	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1119
1120	/**
1121	* Checks if the page has any access handlers, including temporarily disabled ones.
1122	* @returns true/false
1123	* @param a_pPage Pointer to the physical guest page tracking structure.
1124	*/
1125	#define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1126	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1127
1128	/**
1129	* Checks if the page has any active access handlers.
1130	* @returns true/false
1131	* @param a_pPage Pointer to the physical guest page tracking structure.
1132	*/
1133	#define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1134	(PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1135
1136	/**
1137	* Checks if the page has any active access handlers catching all accesses.
1138	* @returns true/false
1139	* @param a_pPage Pointer to the physical guest page tracking structure.
1140	*/
1141	#define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1142	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1143
1144	/** @def PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM
1145	* Checks if the physical handlers of the page should be ignored in shadow page
1146	* tables and such.
1147	* @returns true/false
1148	* @param a_pPage Pointer to the physical guest page tracking structure.
1149	*/
1150	#define PGM_PAGE_IS_HNDL_PHYS_NOT_IN_HM(a_pPage) ((a_pPage)->s.fHandlerPhysNotInHm)
1151
1152	/** @def PGM_PAGE_GET_TRACKING
1153	* Gets the packed shadow page pool tracking data associated with a guest page.
1154	* @returns uint16_t containing the data.
1155	* @param a_pPage Pointer to the physical guest page tracking structure.
1156	*/
1157	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1158	#if defined(__GNUC__) && defined(VBOX_STRICT)
1159	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1160	#else
1161	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1162	#endif
1163
1164	/** @def PGM_PAGE_SET_TRACKING
1165	* Sets the packed shadow page pool tracking data associated with a guest page.
1166	* @param a_pVM The VM handle, only used for lock ownership assertions.
1167	* @param a_pPage Pointer to the physical guest page tracking structure.
1168	* @param a_u16TrackingData The tracking data to store.
1169	*/
1170	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1171	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1172
1173	/** @def PGM_PAGE_GET_TD_CREFS
1174	* Gets the @a cRefs tracking data member.
1175	* @returns cRefs.
1176	* @param a_pPage Pointer to the physical guest page tracking structure.
1177	*/
1178	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1179	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1180	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1181	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1182
1183	/** @def PGM_PAGE_GET_TD_IDX
1184	* Gets the @a idx tracking data member.
1185	* @returns idx.
1186	* @param a_pPage Pointer to the physical guest page tracking structure.
1187	*/
1188	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1189	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1190	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1191	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1192
1193
1194	/** Max number of locks on a page. */
1195	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1196
1197	/** Get the read lock count.
1198	* @returns count.
1199	* @param a_pPage Pointer to the physical guest page tracking structure.
1200	*/
1201	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1202
1203	/** Get the write lock count.
1204	* @returns count.
1205	* @param a_pPage Pointer to the physical guest page tracking structure.
1206	*/
1207	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1208
1209	/** Decrement the read lock counter.
1210	* @param a_pPage Pointer to the physical guest page tracking structure.
1211	*/
1212	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1213
1214	/** Decrement the write lock counter.
1215	* @param a_pPage Pointer to the physical guest page tracking structure.
1216	*/
1217	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1218
1219	/** Increment the read lock counter.
1220	* @param a_pPage Pointer to the physical guest page tracking structure.
1221	*/
1222	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1223
1224	/** Increment the write lock counter.
1225	* @param a_pPage Pointer to the physical guest page tracking structure.
1226	*/
1227	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1228
1229
1230	/** Gets the NEM state.
1231	* @returns NEM state value (two bits).
1232	* @param a_pPage Pointer to the physical guest page tracking structure.
1233	*/
1234	#define PGM_PAGE_GET_NEM_STATE(a_pPage) ((a_pPage)->s.u2NemStateY)
1235
1236	/** Sets the NEM state.
1237	* @param a_pPage Pointer to the physical guest page tracking structure.
1238	* @param a_u2State The NEM state value (specific to NEM impl.).
1239	*/
1240	#define PGM_PAGE_SET_NEM_STATE(a_pPage, a_u2State) \
1241	do { Assert((a_u2State) < 4); (a_pPage)->s.u2NemStateY = (a_u2State); } while (0)
1242
1243
1244	#if 0
1245	/** Enables sanity checking of write monitoring using CRC-32. */
1246	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1247	#endif
1248
1249	/**
1250	* Per page live save tracking data.
1251	*/
1252	typedef struct PGMLIVESAVERAMPAGE
1253	{
1254	/** Number of times it has been dirtied. */
1255	uint32_t cDirtied : 24;
1256	/** Whether it is currently dirty. */
1257	uint32_t fDirty : 1;
1258	/** Ignore the page.
1259	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1260	* deal with these after pausing the VM and DevPCI have said it bit about
1261	* remappings. */
1262	uint32_t fIgnore : 1;
1263	/** Was a ZERO page last time around. */
1264	uint32_t fZero : 1;
1265	/** Was a SHARED page last time around. */
1266	uint32_t fShared : 1;
1267	/** Whether the page is/was write monitored in a previous pass. */
1268	uint32_t fWriteMonitored : 1;
1269	/** Whether the page is/was write monitored earlier in this pass. */
1270	uint32_t fWriteMonitoredJustNow : 1;
1271	/** Bits reserved for future use. */
1272	uint32_t u2Reserved : 2;
1273	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1274	/** CRC-32 for the page. This is for internal consistency checks. */
1275	uint32_t u32Crc;
1276	#endif
1277	} PGMLIVESAVERAMPAGE;
1278	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1279	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1280	#else
1281	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1282	#endif
1283	/** Pointer to the per page live save tracking data. */
1284	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1285
1286	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1287	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1288
1289
1290	/**
1291	* RAM range for GC Phys to HC Phys conversion.
1292	*
1293	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1294	* conversions too, but we'll let MM handle that for now.
1295	*
1296	* This structure is used by linked lists in both GC and HC.
1297	*/
1298	typedef struct PGMRAMRANGE
1299	{
1300	/** Start of the range. Page aligned. */
1301	RTGCPHYS GCPhys;
1302	/** Size of the range. (Page aligned of course). */
1303	RTGCPHYS cb;
1304	/** Pointer to the next RAM range - for R3. */
1305	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1306	/** Pointer to the next RAM range - for R0. */
1307	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1308	/** PGM_RAM_RANGE_FLAGS_* flags. */
1309	uint32_t fFlags;
1310	/** NEM specific info, UINT32_MAX if not used. */
1311	uint32_t uNemRange;
1312	/** Last address in the range (inclusive). Page aligned (-1). */
1313	RTGCPHYS GCPhysLast;
1314	/** Start of the HC mapping of the range. This is only used for MMIO2 and in NEM mode. */
1315	R3PTRTYPE(void *) pvR3;
1316	/** Live save per page tracking data. */
1317	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1318	/** The range description. */
1319	R3PTRTYPE(const char *) pszDesc;
1320	/** Pointer to self - R0 pointer. */
1321	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1322
1323	/** Pointer to the left search three node - ring-3 context. */
1324	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1325	/** Pointer to the right search three node - ring-3 context. */
1326	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1327	/** Pointer to the left search three node - ring-0 context. */
1328	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1329	/** Pointer to the right search three node - ring-0 context. */
1330	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1331
1332	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1333	#if HC_ARCH_BITS == 32
1334	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1335	#endif
1336	/** Array of physical guest page tracking structures.
1337	* @note Number of entries is PGMRAMRANGE::cb / GUEST_PAGE_SIZE. */
1338	PGMPAGE aPages[1];
1339	} PGMRAMRANGE;
1340	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1341	typedef PGMRAMRANGE *PPGMRAMRANGE;
1342
1343	/** @name PGMRAMRANGE::fFlags
1344	* @{ */
1345	/** The RAM range is floating around as an independent guest mapping. */
1346	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1347	/** Ad hoc RAM range for an ROM mapping. */
1348	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1349	/** Ad hoc RAM range for an MMIO mapping. */
1350	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1351	/** Ad hoc RAM range for an MMIO2 or pre-registered MMIO mapping. */
1352	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX RT_BIT(23)
1353	/** @} */
1354
1355	/** Tests if a RAM range is an ad hoc one or not.
1356	* @returns true/false.
1357	* @param pRam The RAM range.
1358	*/
1359	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1360	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO_EX) ) )
1361
1362	/** The number of entries in the RAM range TLBs (there is one for each
1363	* context). Must be a power of two. */
1364	#define PGM_RAMRANGE_TLB_ENTRIES 8
1365
1366	/**
1367	* Calculates the RAM range TLB index for the physical address.
1368	*
1369	* @returns RAM range TLB index.
1370	* @param a_GCPhys The guest physical address.
1371	*/
1372	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1373
1374	/**
1375	* Calculates the ring-3 address for a_GCPhysPage if the RAM range has a
1376	* mapping address.
1377	*/
1378	#define PGM_RAMRANGE_CALC_PAGE_R3PTR(a_pRam, a_GCPhysPage) \
1379	( (a_pRam)->pvR3 ? (R3PTRTYPE(uint8_t *))(a_pRam)->pvR3 + (a_GCPhysPage) - (a_pRam)->GCPhys : NULL )
1380
1381
1382	/**
1383	* Per page tracking structure for ROM image.
1384	*
1385	* A ROM image may have a shadow page, in which case we may have two pages
1386	* backing it. This structure contains the PGMPAGE for both while
1387	* PGMRAMRANGE have a copy of the active one. It is important that these
1388	* aren't out of sync in any regard other than page pool tracking data.
1389	*/
1390	typedef struct PGMROMPAGE
1391	{
1392	/** The page structure for the virgin ROM page. */
1393	PGMPAGE Virgin;
1394	/** The page structure for the shadow RAM page. */
1395	PGMPAGE Shadow;
1396	/** The current protection setting. */
1397	PGMROMPROT enmProt;
1398	/** Live save status information. Makes use of unused alignment space. */
1399	struct
1400	{
1401	/** The previous protection value. */
1402	uint8_t u8Prot;
1403	/** Written to flag set by the handler. */
1404	bool fWrittenTo;
1405	/** Whether the shadow page is dirty or not. */
1406	bool fDirty;
1407	/** Whether it was dirtied in the recently. */
1408	bool fDirtiedRecently;
1409	} LiveSave;
1410	} PGMROMPAGE;
1411	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1412	/** Pointer to a ROM page tracking structure. */
1413	typedef PGMROMPAGE *PPGMROMPAGE;
1414
1415
1416	/**
1417	* A registered ROM image.
1418	*
1419	* This is needed to keep track of ROM image since they generally intrude
1420	* into a PGMRAMRANGE. It also keeps track of additional info like the
1421	* two page sets (read-only virgin and read-write shadow), the current
1422	* state of each page.
1423	*
1424	* Because access handlers cannot easily be executed in a different
1425	* context, the ROM ranges needs to be accessible and in all contexts.
1426	*/
1427	typedef struct PGMROMRANGE
1428	{
1429	/** Pointer to the next range - R3. */
1430	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1431	/** Pointer to the next range - R0. */
1432	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1433	/** Pointer to the this range - R0. */
1434	R0PTRTYPE(struct PGMROMRANGE *) pSelfR0;
1435	/** Address of the range. */
1436	RTGCPHYS GCPhys;
1437	/** Address of the last byte in the range. */
1438	RTGCPHYS GCPhysLast;
1439	/** Size of the range. */
1440	RTGCPHYS cb;
1441	/** The flags (PGMPHYS_ROM_FLAGS_). /
1442	uint8_t fFlags;
1443	/** The saved state range ID. */
1444	uint8_t idSavedState;
1445	/** Alignment padding. */
1446	uint8_t au8Alignment[2];
1447	/** The size bits pvOriginal points to. */
1448	uint32_t cbOriginal;
1449	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1450	* This is used for strictness checks. */
1451	R3PTRTYPE(const void *) pvOriginal;
1452	/** The ROM description. */
1453	R3PTRTYPE(const char *) pszDesc;
1454	#ifdef VBOX_WITH_PGM_NEM_MODE
1455	/** In simplified memory mode this provides alternate backing for shadowed ROMs.
1456	* - PGMROMPROT_READ_ROM_WRITE_IGNORE: Shadow
1457	* - PGMROMPROT_READ_ROM_WRITE_RAM: Shadow
1458	* - PGMROMPROT_READ_RAM_WRITE_IGNORE: ROM
1459	* - PGMROMPROT_READ_RAM_WRITE_RAM: ROM */
1460	R3PTRTYPE(uint8_t *) pbR3Alternate;
1461	RTR3PTR pvAlignment2;
1462	#endif
1463	/** The per page tracking structures. */
1464	PGMROMPAGE aPages[1];
1465	} PGMROMRANGE;
1466	/** Pointer to a ROM range. */
1467	typedef PGMROMRANGE *PPGMROMRANGE;
1468
1469
1470	/**
1471	* Live save per page data for an MMIO2 page.
1472	*
1473	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1474	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1475	* CRC-32 for detecting changes as well as special handling of zero pages. This
1476	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1477	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1478	* because of speed (2.5x and 6x slower).)
1479	*
1480	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1481	* save but normally is disabled. Since we can write monitor guest
1482	* accesses on our own, we only need this for host accesses. Shouldn't be
1483	* too difficult for DevVGA, VMMDev might be doable, the planned
1484	* networking fun will be fun since it involves ring-0.
1485	*/
1486	typedef struct PGMLIVESAVEMMIO2PAGE
1487	{
1488	/** Set if the page is considered dirty. */
1489	bool fDirty;
1490	/** The number of scans this page has remained unchanged for.
1491	* Only updated for dirty pages. */
1492	uint8_t cUnchangedScans;
1493	/** Whether this page was zero at the last scan. */
1494	bool fZero;
1495	/** Alignment padding. */
1496	bool fReserved;
1497	/** CRC-32 for the first half of the page.
1498	* This is used together with u32CrcH2 to quickly detect changes in the page
1499	* during the non-final passes. */
1500	uint32_t u32CrcH1;
1501	/** CRC-32 for the second half of the page. */
1502	uint32_t u32CrcH2;
1503	/** SHA-1 for the saved page.
1504	* This is used in the final pass to skip pages without changes. */
1505	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1506	} PGMLIVESAVEMMIO2PAGE;
1507	/** Pointer to a live save status data for an MMIO2 page. */
1508	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1509
1510	/**
1511	* A registered MMIO2 (= Device RAM) range.
1512	*
1513	* There are a few reason why we need to keep track of these registrations. One
1514	* of them is the deregistration & cleanup stuff, while another is that the
1515	* PGMRAMRANGE associated with such a region may have to be removed from the ram
1516	* range list.
1517	*
1518	* Overlapping with a RAM range has to be 100% or none at all. The pages in the
1519	* existing RAM range must not be ROM nor MMIO. A guru meditation will be
1520	* raised if a partial overlap or an overlap of ROM pages is encountered. On an
1521	* overlap we will free all the existing RAM pages and put in the ram range
1522	* pages instead.
1523	*/
1524	typedef struct PGMREGMMIO2RANGE
1525	{
1526	/** The owner of the range. (a device) */
1527	PPDMDEVINSR3 pDevInsR3;
1528	/** Pointer to the ring-3 mapping of the allocation. */
1529	RTR3PTR pvR3;
1530	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1531	/** Pointer to the ring-0 mapping of the allocation. */
1532	RTR0PTR pvR0;
1533	#endif
1534	/** Pointer to the next range - R3. */
1535	R3PTRTYPE(struct PGMREGMMIO2RANGE *) pNextR3;
1536	/** Flags (PGMREGMMIO2RANGE_F_XXX). */
1537	uint16_t fFlags;
1538	/** The sub device number (internal PCI config (CFGM) number). */
1539	uint8_t iSubDev;
1540	/** The PCI region number. */
1541	uint8_t iRegion;
1542	/** The saved state range ID. */
1543	uint8_t idSavedState;
1544	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1545	uint8_t idMmio2;
1546	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1547	#ifndef VBOX_WITH_LINEAR_HOST_PHYS_MEM
1548	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 4 : 2];
1549	#else
1550	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 6 + 8 : 2 + 8];
1551	#endif
1552	/** The real size.
1553	* This may be larger than indicated by RamRange.cb if the range has been
1554	* reduced during saved state loading. */
1555	RTGCPHYS cbReal;
1556	/** Pointer to the physical handler for MMIO.
1557	* If NEM is responsible for tracking dirty pages in simple memory mode, this
1558	* will be NULL. */
1559	R3PTRTYPE(PPGMPHYSHANDLER) pPhysHandlerR3;
1560	/** Live save per page tracking data for MMIO2. */
1561	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1562	/** The associated RAM range. */
1563	PGMRAMRANGE RamRange;
1564	} PGMREGMMIO2RANGE;
1565	AssertCompileMemberAlignment(PGMREGMMIO2RANGE, RamRange, 16);
1566	/** Pointer to a MMIO2 or pre-registered MMIO range. */
1567	typedef PGMREGMMIO2RANGE *PPGMREGMMIO2RANGE;
1568
1569	/** @name PGMREGMMIO2RANGE_F_XXX - Registered MMIO2 range flags.
1570	* @{ */
1571	/** Set if this is the first chunk in the MMIO2 range. */
1572	#define PGMREGMMIO2RANGE_F_FIRST_CHUNK UINT16_C(0x0001)
1573	/** Set if this is the last chunk in the MMIO2 range. */
1574	#define PGMREGMMIO2RANGE_F_LAST_CHUNK UINT16_C(0x0002)
1575	/** Set if the whole range is mapped. */
1576	#define PGMREGMMIO2RANGE_F_MAPPED UINT16_C(0x0004)
1577	/** Set if it's overlapping, clear if not. */
1578	#define PGMREGMMIO2RANGE_F_OVERLAPPING UINT16_C(0x0008)
1579	/** This mirrors the PGMPHYS_MMIO2_FLAGS_TRACK_DIRTY_PAGES creation flag.*/
1580	#define PGMREGMMIO2RANGE_F_TRACK_DIRTY_PAGES UINT16_C(0x0010)
1581	/** Set if the access handler is registered. */
1582	#define PGMREGMMIO2RANGE_F_IS_TRACKING UINT16_C(0x0020)
1583	/** Set if dirty page tracking is currently enabled. */
1584	#define PGMREGMMIO2RANGE_F_TRACKING_ENABLED UINT16_C(0x0040)
1585	/** Set if there are dirty pages in the range. */
1586	#define PGMREGMMIO2RANGE_F_IS_DIRTY UINT16_C(0x0080)
1587	/** @} */
1588
1589
1590	/** @name Internal MMIO2 constants.
1591	* @{ */
1592	/** The maximum number of MMIO2 ranges. */
1593	#define PGM_MMIO2_MAX_RANGES 32
1594	/** The maximum number of pages in a MMIO2 range. */
1595	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x01000000)
1596	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1597	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1598	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1599	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1600	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1601	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1602	/** @} */
1603
1604
1605
1606	/**
1607	* PGMPhysRead/Write cache entry
1608	*/
1609	typedef struct PGMPHYSCACHEENTRY
1610	{
1611	/** R3 pointer to physical page. */
1612	R3PTRTYPE(uint8_t *) pbR3;
1613	/** GC Physical address for cache entry */
1614	RTGCPHYS GCPhys;
1615	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1616	RTGCPHYS u32Padding0; /*< alignment padding. /
1617	#endif
1618	} PGMPHYSCACHEENTRY;
1619
1620	/**
1621	* PGMPhysRead/Write cache to reduce REM memory access overhead
1622	*/
1623	typedef struct PGMPHYSCACHE
1624	{
1625	/** Bitmap of valid cache entries */
1626	uint64_t aEntries;
1627	/** Cache entries */
1628	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1629	} PGMPHYSCACHE;
1630
1631
1632	/** @name Ring-3 page mapping TLBs
1633	* @{ */
1634
1635	/** Pointer to an allocation chunk ring-3 mapping. */
1636	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1637	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1638	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1639
1640	/**
1641	* Ring-3 tracking structure for an allocation chunk ring-3 mapping.
1642	*
1643	* The primary tree (Core) uses the chunk id as key.
1644	*/
1645	typedef struct PGMCHUNKR3MAP
1646	{
1647	/** The key is the chunk id. */
1648	AVLU32NODECORE Core;
1649	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1650	* selection. */
1651	uint32_t iLastUsed;
1652	/** The current reference count. */
1653	uint32_t volatile cRefs;
1654	/** The current permanent reference count. */
1655	uint32_t volatile cPermRefs;
1656	/** The mapping address. */
1657	void *pv;
1658	} PGMCHUNKR3MAP;
1659
1660	/**
1661	* Allocation chunk ring-3 mapping TLB entry.
1662	*/
1663	typedef struct PGMCHUNKR3MAPTLBE
1664	{
1665	/** The chunk id. */
1666	uint32_t volatile idChunk;
1667	#if HC_ARCH_BITS == 64
1668	uint32_t u32Padding; /*< alignment padding. /
1669	#endif
1670	/** The chunk map. */
1671	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1672	} PGMCHUNKR3MAPTLBE;
1673	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1674	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1675
1676	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1677	* @remark Must be a power of two value. */
1678	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1679
1680	/**
1681	* Allocation chunk ring-3 mapping TLB.
1682	*
1683	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1684	* At first glance this might look kinda odd since AVL trees are
1685	* supposed to give the most optimal lookup times of all trees
1686	* due to their balancing. However, take a tree with 1023 nodes
1687	* in it, that's 10 levels, meaning that most searches has to go
1688	* down 9 levels before they find what they want. This isn't fast
1689	* compared to a TLB hit. There is the factor of cache misses,
1690	* and of course the problem with trees and branch prediction.
1691	* This is why we use TLBs in front of most of the trees.
1692	*
1693	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1694	* difficult when we switch to the new inlined AVL trees (from kStuff).
1695	*/
1696	typedef struct PGMCHUNKR3MAPTLB
1697	{
1698	/** The TLB entries. */
1699	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1700	} PGMCHUNKR3MAPTLB;
1701
1702	/**
1703	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1704	* @returns Chunk TLB index.
1705	* @param idChunk The Chunk ID.
1706	*/
1707	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1708
1709
1710	/**
1711	* Ring-3 guest page mapping TLB entry.
1712	* @remarks used in ring-0 as well at the moment.
1713	*/
1714	typedef struct PGMPAGER3MAPTLBE
1715	{
1716	/** Address of the page. */
1717	RTGCPHYS volatile GCPhys;
1718	/** The guest page. */
1719	R3PTRTYPE(PPGMPAGE) volatile pPage;
1720	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1721	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1722	/** The address */
1723	R3PTRTYPE(void *) volatile pv;
1724	#if HC_ARCH_BITS == 32
1725	uint32_t u32Padding; /*< alignment padding. /
1726	#endif
1727	} PGMPAGER3MAPTLBE;
1728	/** Pointer to an entry in the HC physical TLB. */
1729	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1730
1731
1732	/** The number of entries in the ring-3 guest page mapping TLB.
1733	* @remarks The value must be a power of two. */
1734	#define PGM_PAGER3MAPTLB_ENTRIES 256
1735
1736	/**
1737	* Ring-3 guest page mapping TLB.
1738	* @remarks used in ring-0 as well at the moment.
1739	*/
1740	typedef struct PGMPAGER3MAPTLB
1741	{
1742	/** The TLB entries. */
1743	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1744	} PGMPAGER3MAPTLB;
1745	/** Pointer to the ring-3 guest page mapping TLB. */
1746	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1747
1748	/**
1749	* Calculates the index of the TLB entry for the specified guest page.
1750	* @returns Physical TLB index.
1751	* @param GCPhys The guest physical address.
1752	*/
1753	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1754
1755	/** @} */
1756
1757
1758	/** @name Ring-0 page mapping TLB
1759	* @{ */
1760	/**
1761	* Ring-0 guest page mapping TLB entry.
1762	*/
1763	typedef struct PGMPAGER0MAPTLBE
1764	{
1765	/** Address of the page. */
1766	RTGCPHYS volatile GCPhys;
1767	/** The guest page. */
1768	R0PTRTYPE(PPGMPAGE) volatile pPage;
1769	/** The address */
1770	R0PTRTYPE(void *) volatile pv;
1771	} PGMPAGER0MAPTLBE;
1772	/** Pointer to an entry in the HC physical TLB. */
1773	typedef PGMPAGER0MAPTLBE *PPGMPAGER0MAPTLBE;
1774
1775
1776	/** The number of entries in the ring-3 guest page mapping TLB.
1777	* @remarks The value must be a power of two. */
1778	#define PGM_PAGER0MAPTLB_ENTRIES 256
1779
1780	/**
1781	* Ring-3 guest page mapping TLB.
1782	* @remarks used in ring-0 as well at the moment.
1783	*/
1784	typedef struct PGMPAGER0MAPTLB
1785	{
1786	/** The TLB entries. */
1787	PGMPAGER0MAPTLBE aEntries[PGM_PAGER0MAPTLB_ENTRIES];
1788	} PGMPAGER0MAPTLB;
1789	/** Pointer to the ring-3 guest page mapping TLB. */
1790	typedef PGMPAGER0MAPTLB *PPGMPAGER0MAPTLB;
1791
1792	/**
1793	* Calculates the index of the TLB entry for the specified guest page.
1794	* @returns Physical TLB index.
1795	* @param GCPhys The guest physical address.
1796	*/
1797	#define PGM_PAGER0MAPTLB_IDX(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGM_PAGER0MAPTLB_ENTRIES - 1) )
1798	/** @} */
1799
1800
1801	/** @name Context neutral page mapper TLB.
1802	*
1803	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1804	* code is writting in a kind of context neutral way. Time will show whether
1805	* this actually makes sense or not...
1806	*
1807	* @todo this needs to be reconsidered and dropped/redone since the ring-0
1808	* context ends up using a global mapping cache on some platforms
1809	* (darwin).
1810	*
1811	* @{ */
1812	/** @typedef PPGMPAGEMAPTLB
1813	* The page mapper TLB pointer type for the current context. */
1814	/** @typedef PPGMPAGEMAPTLB
1815	* The page mapper TLB entry pointer type for the current context. */
1816	/** @typedef PPGMPAGEMAPTLB
1817	* The page mapper TLB entry pointer pointer type for the current context. */
1818	/** @def PGM_PAGEMAPTLB_ENTRIES
1819	* The number of TLB entries in the page mapper TLB for the current context. */
1820	/** @def PGM_PAGEMAPTLB_IDX
1821	* Calculate the TLB index for a guest physical address.
1822	* @returns The TLB index.
1823	* @param GCPhys The guest physical address. */
1824	/** @typedef PPGMPAGEMAP
1825	* Pointer to a page mapper unit for current context. */
1826	/** @typedef PPPGMPAGEMAP
1827	* Pointer to a page mapper unit pointer for current context. */
1828	#if defined(IN_RING0)
1829	typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1830	typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1831	typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1832	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1833	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1834	typedef struct PGMCHUNKR0MAP *PPGMPAGEMAP;
1835	typedef struct PGMCHUNKR0MAP **PPPGMPAGEMAP;
1836	#else
1837	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1838	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1839	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1840	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1841	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1842	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1843	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1844	#endif
1845	/** @} */
1846
1847
1848	/** @name PGM Pool Indexes.
1849	* Aka. the unique shadow page identifier.
1850	* @{ */
1851	/** NIL page pool IDX. */
1852	#define NIL_PGMPOOL_IDX 0
1853	/** The first normal index. There used to be 5 fictive pages up front, now
1854	* there is only the NIL page. */
1855	#define PGMPOOL_IDX_FIRST 1
1856	/** The last valid index. (inclusive, 14 bits) */
1857	#define PGMPOOL_IDX_LAST 0x3fff
1858	/** @} */
1859
1860	/** The NIL index for the parent chain. */
1861	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1862	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1863
1864	/**
1865	* Node in the chain linking a shadowed page to it's parent (user).
1866	*/
1867	#pragma pack(1)
1868	typedef struct PGMPOOLUSER
1869	{
1870	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1871	uint16_t iNext;
1872	/** The user page index. */
1873	uint16_t iUser;
1874	/** Index into the user table. */
1875	uint32_t iUserTable;
1876	} PGMPOOLUSER, *PPGMPOOLUSER;
1877	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1878	#pragma pack()
1879
1880
1881	/** The NIL index for the phys ext chain. */
1882	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1883	/** The NIL pte index for a phys ext chain slot. */
1884	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1885
1886	/**
1887	* Node in the chain of physical cross reference extents.
1888	* @todo Calling this an 'extent' is not quite right, find a better name.
1889	* @todo find out the optimal size of the aidx array
1890	*/
1891	#pragma pack(1)
1892	typedef struct PGMPOOLPHYSEXT
1893	{
1894	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1895	uint16_t iNext;
1896	/** Alignment. */
1897	uint16_t u16Align;
1898	/** The user page index. */
1899	uint16_t aidx[3];
1900	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1901	uint16_t apte[3];
1902	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1903	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1904	#pragma pack()
1905
1906
1907	/**
1908	* The kind of page that's being shadowed.
1909	*/
1910	typedef enum PGMPOOLKIND
1911	{
1912	/** The virtual invalid 0 entry. */
1913	PGMPOOLKIND_INVALID = 0,
1914	/** The entry is free (=unused). */
1915	PGMPOOLKIND_FREE,
1916
1917	/** Shw: 32-bit page table; Gst: no paging. */
1918	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1919	/** Shw: 32-bit page table; Gst: 32-bit page table. */
1920	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1921	/** Shw: 32-bit page table; Gst: 4MB page. */
1922	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1923	/** Shw: PAE page table; Gst: no paging. */
1924	PGMPOOLKIND_PAE_PT_FOR_PHYS,
1925	/** Shw: PAE page table; Gst: 32-bit page table. */
1926	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1927	/** Shw: PAE page table; Gst: Half of a 4MB page. */
1928	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1929	/** Shw: PAE page table; Gst: PAE page table. */
1930	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1931	/** Shw: PAE page table; Gst: 2MB page. */
1932	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1933
1934	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1935	PGMPOOLKIND_32BIT_PD,
1936	/** Shw: 32-bit page directory. Gst: no paging. */
1937	PGMPOOLKIND_32BIT_PD_PHYS,
1938	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1939	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1940	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1941	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1942	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1943	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1944	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1945	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1946	/** Shw: PAE page directory; Gst: PAE page directory. */
1947	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1948	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1949	PGMPOOLKIND_PAE_PD_PHYS,
1950
1951	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1952	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1953	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1954	PGMPOOLKIND_PAE_PDPT,
1955	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1956	PGMPOOLKIND_PAE_PDPT_PHYS,
1957
1958	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1959	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1960	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
1961	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1962	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1963	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1964	/** Shw: 64-bit page directory table; Gst: no paging. */
1965	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
1966
1967	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1968	PGMPOOLKIND_64BIT_PML4,
1969
1970	/** Shw: EPT page directory pointer table; Gst: no paging. */
1971	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1972	/** Shw: EPT page directory table; Gst: no paging. */
1973	PGMPOOLKIND_EPT_PD_FOR_PHYS,
1974	/** Shw: EPT page table; Gst: no paging. */
1975	PGMPOOLKIND_EPT_PT_FOR_PHYS,
1976
1977	/** Shw: Root Nested paging table. */
1978	PGMPOOLKIND_ROOT_NESTED,
1979
1980	/** Shw: EPT page table; Gst: EPT page table. */
1981	PGMPOOLKIND_EPT_PT_FOR_EPT_PT,
1982	/** Shw: EPT page table; Gst: 2MB page. */
1983	PGMPOOLKIND_EPT_PT_FOR_EPT_2MB,
1984	/** Shw: EPT page directory table; Gst: EPT page directory. */
1985	PGMPOOLKIND_EPT_PD_FOR_EPT_PD,
1986	/** Shw: EPT page directory pointer table; Gst: EPT page directory pointer table. */
1987	PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT,
1988	/** Shw: EPT PML4; Gst: EPT PML4. */
1989	PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4,
1990
1991	/** The last valid entry. */
1992	PGMPOOLKIND_LAST = PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4
1993	} PGMPOOLKIND;
1994
1995	/**
1996	* The access attributes of the page; only applies to big pages.
1997	*/
1998	typedef enum
1999	{
2000	PGMPOOLACCESS_DONTCARE = 0,
2001	PGMPOOLACCESS_USER_RW,
2002	PGMPOOLACCESS_USER_R,
2003	PGMPOOLACCESS_USER_RW_NX,
2004	PGMPOOLACCESS_USER_R_NX,
2005	PGMPOOLACCESS_SUPERVISOR_RW,
2006	PGMPOOLACCESS_SUPERVISOR_R,
2007	PGMPOOLACCESS_SUPERVISOR_RW_NX,
2008	PGMPOOLACCESS_SUPERVISOR_R_NX
2009	} PGMPOOLACCESS;
2010
2011	/**
2012	* The tracking data for a page in the pool.
2013	*/
2014	typedef struct PGMPOOLPAGE
2015	{
2016	/** AVL node code with the (HC) physical address of this page. */
2017	AVLOHCPHYSNODECORE Core;
2018	/** Pointer to the R3 mapping of the page. */
2019	R3PTRTYPE(void *) pvPageR3;
2020	/** Pointer to the R0 mapping of the page. */
2021	R0PTRTYPE(void *) pvPageR0;
2022	/** The guest physical address. */
2023	RTGCPHYS GCPhys;
2024	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2025	uint8_t enmKind;
2026	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2027	uint8_t enmAccess;
2028	/** This supplements enmKind and enmAccess */
2029	bool fA20Enabled : 1;
2030
2031	/** Used to indicate that the page is zeroed. */
2032	bool fZeroed : 1;
2033	/** Used to indicate that a PT has non-global entries. */
2034	bool fSeenNonGlobal : 1;
2035	/** Used to indicate that we're monitoring writes to the guest page. */
2036	bool fMonitored : 1;
2037	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2038	* (All pages are in the age list.) */
2039	bool fCached : 1;
2040	/** This is used by the R3 access handlers when invoked by an async thread.
2041	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2042	bool volatile fReusedFlushPending : 1;
2043	/** Used to mark the page as dirty (write monitoring is temporarily
2044	* off). */
2045	bool fDirty : 1;
2046	bool fPadding1 : 1;
2047	bool fPadding2;
2048
2049	/** The index of this page. */
2050	uint16_t idx;
2051	/** The next entry in the list this page currently resides in.
2052	* It's either in the free list or in the GCPhys hash. */
2053	uint16_t iNext;
2054	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2055	uint16_t iUserHead;
2056	/** The number of present entries. */
2057	uint16_t cPresent;
2058	/** The first entry in the table which is present. */
2059	uint16_t iFirstPresent;
2060	/** The number of modifications to the monitored page. */
2061	uint16_t cModifications;
2062	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2063	uint16_t iModifiedNext;
2064	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2065	uint16_t iModifiedPrev;
2066	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2067	uint16_t iMonitoredNext;
2068	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2069	uint16_t iMonitoredPrev;
2070	/** The next page in the age list. */
2071	uint16_t iAgeNext;
2072	/** The previous page in the age list. */
2073	uint16_t iAgePrev;
2074	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2075	uint8_t idxDirtyEntry;
2076
2077	/** @name Access handler statistics to determine whether the guest is
2078	* (re)initializing a page table.
2079	* @{ */
2080	RTGCPTR GCPtrLastAccessHandlerRip;
2081	RTGCPTR GCPtrLastAccessHandlerFault;
2082	uint64_t cLastAccessHandler;
2083	/** @} */
2084	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2085	uint32_t volatile cLocked;
2086	#if GC_ARCH_BITS == 64
2087	uint32_t u32Alignment3;
2088	#endif
2089	# ifdef VBOX_STRICT
2090	RTGCPTR GCPtrDirtyFault;
2091	# endif
2092	} PGMPOOLPAGE;
2093	/** Pointer to a pool page. */
2094	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2095	/** Pointer to a const pool page. */
2096	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2097	/** Pointer to a pool page pointer. */
2098	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2099
2100
2101	/** The hash table size. */
2102	# define PGMPOOL_HASH_SIZE 0x8000
2103	/** The hash function. */
2104	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> GUEST_PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2105
2106
2107	/**
2108	* The shadow page pool instance data.
2109	*
2110	* It's all one big allocation made at init time, except for the
2111	* pages that is. The user nodes follows immediately after the
2112	* page structures.
2113	*/
2114	typedef struct PGMPOOL
2115	{
2116	/** The VM handle - R3 Ptr. */
2117	PVMR3 pVMR3;
2118	/** The VM handle - R0 Ptr. */
2119	R0PTRTYPE(PVMCC) pVMR0;
2120	/** The ring-3 pointer to this structure. */
2121	R3PTRTYPE(struct PGMPOOL *) pPoolR3;
2122	/** The ring-0 pointer to this structure. */
2123	R0PTRTYPE(struct PGMPOOL *) pPoolR0;
2124	/** The max pool size. This includes the special IDs. */
2125	uint16_t cMaxPages;
2126	/** The current pool size. */
2127	uint16_t cCurPages;
2128	/** The head of the free page list. */
2129	uint16_t iFreeHead;
2130	/* Padding. */
2131	uint16_t u16Padding;
2132	/** Head of the chain of free user nodes. */
2133	uint16_t iUserFreeHead;
2134	/** The number of user nodes we've allocated. */
2135	uint16_t cMaxUsers;
2136	/** The number of present page table entries in the entire pool. */
2137	uint32_t cPresent;
2138	/** Pointer to the array of user nodes - R3 pointer. */
2139	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2140	/** Pointer to the array of user nodes - R0 pointer. */
2141	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2142	/** Head of the chain of free phys ext nodes. */
2143	uint16_t iPhysExtFreeHead;
2144	/** The number of user nodes we've allocated. */
2145	uint16_t cMaxPhysExts;
2146	uint32_t u32Padding0b;
2147	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2148	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2149	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2150	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2151	/** Hash table for GCPhys addresses. */
2152	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2153	/** The head of the age list. */
2154	uint16_t iAgeHead;
2155	/** The tail of the age list. */
2156	uint16_t iAgeTail;
2157	/** Set if the cache is enabled. */
2158	bool fCacheEnabled;
2159	/** Alignment padding. */
2160	bool afPadding1[3];
2161	/** Head of the list of modified pages. */
2162	uint16_t iModifiedHead;
2163	/** The current number of modified pages. */
2164	uint16_t cModifiedPages;
2165	/** Alignment padding. */
2166	uint32_t u32Padding2;
2167	/** Physical access handler type registration handle. */
2168	PGMPHYSHANDLERTYPE hAccessHandlerType;
2169	/** Next available slot (in aDirtyPages). */
2170	uint32_t idxFreeDirtyPage;
2171	/** Number of active dirty pages. */
2172	uint32_t cDirtyPages;
2173	/** Array of current dirty pgm pool page indices. */
2174	uint16_t aidxDirtyPages[16];
2175	/** Array running in parallel to aidxDirtyPages with the page data. */
2176	struct
2177	{
2178	uint64_t aPage[512];
2179	} aDirtyPages[16];
2180
2181	/** The number of pages currently in use. */
2182	uint16_t cUsedPages;
2183	#ifdef VBOX_WITH_STATISTICS
2184	/** The high water mark for cUsedPages. */
2185	uint16_t cUsedPagesHigh;
2186	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2187	/** Profiling pgmPoolAlloc(). */
2188	STAMPROFILEADV StatAlloc;
2189	/** Profiling pgmR3PoolClearDoIt(). */
2190	STAMPROFILE StatClearAll;
2191	/** Profiling pgmR3PoolReset(). */
2192	STAMPROFILE StatR3Reset;
2193	/** Profiling pgmPoolFlushPage(). */
2194	STAMPROFILE StatFlushPage;
2195	/** Profiling pgmPoolFree(). */
2196	STAMPROFILE StatFree;
2197	/** Counting explicit flushes by PGMPoolFlushPage(). */
2198	STAMCOUNTER StatForceFlushPage;
2199	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2200	STAMCOUNTER StatForceFlushDirtyPage;
2201	/** Counting flushes for reused pages. */
2202	STAMCOUNTER StatForceFlushReused;
2203	/** Profiling time spent zeroing pages. */
2204	STAMPROFILE StatZeroPage;
2205	/** Profiling of pgmPoolTrackDeref. */
2206	STAMPROFILE StatTrackDeref;
2207	/** Profiling pgmTrackFlushGCPhysPT. */
2208	STAMPROFILE StatTrackFlushGCPhysPT;
2209	/** Profiling pgmTrackFlushGCPhysPTs. */
2210	STAMPROFILE StatTrackFlushGCPhysPTs;
2211	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2212	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2213	/** Number of times we've been out of user records. */
2214	STAMCOUNTER StatTrackFreeUpOneUser;
2215	/** Nr of flushed entries. */
2216	STAMCOUNTER StatTrackFlushEntry;
2217	/** Nr of updated entries. */
2218	STAMCOUNTER StatTrackFlushEntryKeep;
2219	/** Profiling deref activity related tracking GC physical pages. */
2220	STAMPROFILE StatTrackDerefGCPhys;
2221	/** Number of linear searches for a HCPhys in the ram ranges. */
2222	STAMCOUNTER StatTrackLinearRamSearches;
2223	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2224	STAMCOUNTER StamTrackPhysExtAllocFailures;
2225
2226	/** Profiling the RC/R0 \#PF access handler. */
2227	STAMPROFILE StatMonitorPfRZ;
2228	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2229	STAMPROFILE StatMonitorPfRZHandled;
2230	/** Times we've failed interpreting the instruction. */
2231	STAMCOUNTER StatMonitorPfRZEmulateInstr;
2232	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2233	STAMPROFILE StatMonitorPfRZFlushPage;
2234	/** Times we've detected a page table reinit. */
2235	STAMCOUNTER StatMonitorPfRZFlushReinit;
2236	/** Counting flushes for pages that are modified too often. */
2237	STAMCOUNTER StatMonitorPfRZFlushModOverflow;
2238	/** Times we've detected fork(). */
2239	STAMCOUNTER StatMonitorPfRZFork;
2240	/** Times we've failed interpreting a patch code instruction. */
2241	STAMCOUNTER StatMonitorPfRZIntrFailPatch1;
2242	/** Times we've failed interpreting a patch code instruction during flushing. */
2243	STAMCOUNTER StatMonitorPfRZIntrFailPatch2;
2244	/** The number of times we've seen rep prefixes we can't handle. */
2245	STAMCOUNTER StatMonitorPfRZRepPrefix;
2246	/** Profiling the REP STOSD cases we've handled. */
2247	STAMPROFILE StatMonitorPfRZRepStosd;
2248
2249	/** Profiling the R0/RC regular access handler. */
2250	STAMPROFILE StatMonitorRZ;
2251	/** Profiling the pgmPoolFlushPage calls made from the regular access handler in R0/RC. */
2252	STAMPROFILE StatMonitorRZFlushPage;
2253	/** Per access size counts indexed by size minus 1, last for larger. */
2254	STAMCOUNTER aStatMonitorRZSizes[16+3];
2255	/** Missaligned access counts indexed by offset - 1. */
2256	STAMCOUNTER aStatMonitorRZMisaligned[7];
2257
2258	/** Nr of handled PT faults. */
2259	STAMCOUNTER StatMonitorRZFaultPT;
2260	/** Nr of handled PD faults. */
2261	STAMCOUNTER StatMonitorRZFaultPD;
2262	/** Nr of handled PDPT faults. */
2263	STAMCOUNTER StatMonitorRZFaultPDPT;
2264	/** Nr of handled PML4 faults. */
2265	STAMCOUNTER StatMonitorRZFaultPML4;
2266
2267	/** Profiling the R3 access handler. */
2268	STAMPROFILE StatMonitorR3;
2269	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2270	STAMPROFILE StatMonitorR3FlushPage;
2271	/** Per access size counts indexed by size minus 1, last for larger. */
2272	STAMCOUNTER aStatMonitorR3Sizes[16+3];
2273	/** Missaligned access counts indexed by offset - 1. */
2274	STAMCOUNTER aStatMonitorR3Misaligned[7];
2275	/** Nr of handled PT faults. */
2276	STAMCOUNTER StatMonitorR3FaultPT;
2277	/** Nr of handled PD faults. */
2278	STAMCOUNTER StatMonitorR3FaultPD;
2279	/** Nr of handled PDPT faults. */
2280	STAMCOUNTER StatMonitorR3FaultPDPT;
2281	/** Nr of handled PML4 faults. */
2282	STAMCOUNTER StatMonitorR3FaultPML4;
2283
2284	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2285	STAMCOUNTER StatResetDirtyPages;
2286	/** Times we've called pgmPoolAddDirtyPage. */
2287	STAMCOUNTER StatDirtyPage;
2288	/** Times we've had to flush duplicates for dirty page management. */
2289	STAMCOUNTER StatDirtyPageDupFlush;
2290	/** Times we've had to flush because of overflow. */
2291	STAMCOUNTER StatDirtyPageOverFlowFlush;
2292
2293	/** The high water mark for cModifiedPages. */
2294	uint16_t cModifiedPagesHigh;
2295	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2296
2297	/** The number of cache hits. */
2298	STAMCOUNTER StatCacheHits;
2299	/** The number of cache misses. */
2300	STAMCOUNTER StatCacheMisses;
2301	/** The number of times we've got a conflict of 'kind' in the cache. */
2302	STAMCOUNTER StatCacheKindMismatches;
2303	/** Number of times we've been out of pages. */
2304	STAMCOUNTER StatCacheFreeUpOne;
2305	/** The number of cacheable allocations. */
2306	STAMCOUNTER StatCacheCacheable;
2307	/** The number of uncacheable allocations. */
2308	STAMCOUNTER StatCacheUncacheable;
2309	#else
2310	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2311	#endif
2312	/** Profiling PGMR0PoolGrow(). */
2313	STAMPROFILE StatGrow;
2314	/** The AVL tree for looking up a page by its HC physical address. */
2315	AVLOHCPHYSTREE HCPhysTree;
2316	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2317	/** Array of pages. (cMaxPages in length)
2318	* The Id is the index into thist array.
2319	*/
2320	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2321	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2322	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2323	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2324	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2325	#ifdef VBOX_WITH_STATISTICS
2326	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2327	#endif
2328	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2329
2330
2331	/** @def PGMPOOL_PAGE_2_PTR
2332	* Maps a pool page pool into the current context.
2333	*
2334	* @returns VBox status code.
2335	* @param a_pVM Pointer to the VM.
2336	* @param a_pPage The pool page.
2337	*
2338	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2339	* small page window employeed by that function. Be careful.
2340	* @remark There is no need to assert on the result.
2341	*/
2342	#if defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2343	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2344	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2345	{
2346	RT_NOREF(pszCaller);
2347	AssertPtr(a_pPage);
2348	AssertMsg(RT_VALID_PTR(a_pPage->CTX_SUFF(pvPage)),
2349	("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp pvPageR3=%p pvPageR0=%p caller=%s\n",
2350	a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, a_pPage->pvPageR3, a_pPage->pvPageR0, pszCaller));
2351	return a_pPage->CTX_SUFF(pvPage);
2352	}
2353	#else
2354	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->CTX_SUFF(pvPage))
2355	#endif
2356
2357
2358	/** @def PGMPOOL_PAGE_2_PTR_V2
2359	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2360	*
2361	* @returns VBox status code.
2362	* @param a_pVM Pointer to the VM.
2363	* @param a_pVCpu The current CPU.
2364	* @param a_pPage The pool page.
2365	*
2366	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2367	* small page window employeed by that function. Be careful.
2368	* @remark There is no need to assert on the result.
2369	*/
2370	#define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2371
2372
2373	/** @def PGMPOOL_PAGE_IS_NESTED
2374	* Checks whether the given pool page is a nested-guest pool page.
2375	*
2376	* @returns @c true if a nested-guest pool page, @c false otherwise.
2377	* @param a_pPage The pool page.
2378	* @todo We can optimize the conditionals later.
2379	*/
2380	#define PGMPOOL_PAGE_IS_NESTED(a_pPage) PGMPOOL_PAGE_IS_KIND_NESTED((a_pPage)->enmKind)
2381	#define PGMPOOL_PAGE_IS_KIND_NESTED(a_enmKind) ( (a_enmKind) == PGMPOOLKIND_EPT_PT_FOR_EPT_PT \
2382	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PT_FOR_EPT_2MB \
2383	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PD_FOR_EPT_PD \
2384	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PDPT_FOR_EPT_PDPT \
2385	\|\| (a_enmKind) == PGMPOOLKIND_EPT_PML4_FOR_EPT_PML4)
2386
2387	/** @name Per guest page tracking data.
2388	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2389	* is to use more bits for it and split it up later on. But for now we'll play
2390	* safe and change as little as possible.
2391	*
2392	* The 16-bit word has two parts:
2393	*
2394	* The first 14-bit forms the @a idx field. It is either the index of a page in
2395	* the shadow page pool, or and index into the extent list.
2396	*
2397	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2398	* shadow page pool references to the page. If cRefs equals
2399	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2400	* (misnomer) table and not the shadow page pool.
2401	*
2402	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2403	* the 16-bit word.
2404	*
2405	* @{ */
2406	/** The shift count for getting to the cRefs part. */
2407	#define PGMPOOL_TD_CREFS_SHIFT 14
2408	/** The mask applied after shifting the tracking data down by
2409	* PGMPOOL_TD_CREFS_SHIFT. */
2410	#define PGMPOOL_TD_CREFS_MASK 0x3
2411	/** The cRefs value used to indicate that the idx is the head of a
2412	* physical cross reference list. */
2413	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2414	/** The shift used to get idx. */
2415	#define PGMPOOL_TD_IDX_SHIFT 0
2416	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2417	#define PGMPOOL_TD_IDX_MASK 0x3fff
2418	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2419	* simply too many mappings of this page. */
2420	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2421
2422	/** @def PGMPOOL_TD_MAKE
2423	* Makes a 16-bit tracking data word.
2424	*
2425	* @returns tracking data.
2426	* @param cRefs The @a cRefs field. Must be within bounds!
2427	* @param idx The @a idx field. Must also be within bounds! */
2428	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2429
2430	/** @def PGMPOOL_TD_GET_CREFS
2431	* Get the @a cRefs field from a tracking data word.
2432	*
2433	* @returns The @a cRefs field
2434	* @param u16 The tracking data word.
2435	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2436	* non-zero @a u16. */
2437	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2438
2439	/** @def PGMPOOL_TD_GET_IDX
2440	* Get the @a idx field from a tracking data word.
2441	*
2442	* @returns The @a idx field
2443	* @param u16 The tracking data word. */
2444	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2445	/** @} */
2446
2447
2448
2449	/** @name A20 gate macros
2450	* @{ */
2451	#define PGM_WITH_A20
2452	#ifdef PGM_WITH_A20
2453	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2454	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2455	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2456	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2457	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2458	#else
2459	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2460	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2461	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2462	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2463	#endif
2464	/** @} */
2465
2466
2467	/**
2468	* Guest page table walk for the AMD64 mode.
2469	*/
2470	typedef struct PGMPTWALKGSTAMD64
2471	{
2472	PX86PML4 pPml4;
2473	PX86PML4E pPml4e;
2474	X86PML4E Pml4e;
2475
2476	PX86PDPT pPdpt;
2477	PX86PDPE pPdpe;
2478	X86PDPE Pdpe;
2479
2480	PX86PDPAE pPd;
2481	PX86PDEPAE pPde;
2482	X86PDEPAE Pde;
2483
2484	PX86PTPAE pPt;
2485	PX86PTEPAE pPte;
2486	X86PTEPAE Pte;
2487	} PGMPTWALKGSTAMD64;
2488	/** Pointer to a AMD64 guest page table walk. */
2489	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2490	/** Pointer to a const AMD64 guest page table walk. */
2491	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2492
2493	/**
2494	* Guest page table walk for the EPT mode.
2495	*/
2496	typedef struct PGMPTWALKGSTEPT
2497	{
2498	PEPTPML4 pPml4;
2499	PEPTPML4E pPml4e;
2500	EPTPML4E Pml4e;
2501
2502	PEPTPDPT pPdpt;
2503	PEPTPDPTE pPdpte;
2504	EPTPDPTE Pdpte;
2505
2506	PEPTPD pPd;
2507	PEPTPDE pPde;
2508	EPTPDE Pde;
2509
2510	PEPTPT pPt;
2511	PEPTPTE pPte;
2512	EPTPTE Pte;
2513	} PGMPTWALKGSTEPT;
2514	/** Pointer to an EPT guest page table walk. */
2515	typedef PGMPTWALKGSTEPT *PPGMPTWALKGSTEPT;
2516	/** Pointer to a const EPT guest page table walk. */
2517	typedef PGMPTWALKGSTEPT const *PCPGMPTWALKGSTEPT;
2518
2519	/**
2520	* Guest page table walk for the PAE mode.
2521	*/
2522	typedef struct PGMPTWALKGSTPAE
2523	{
2524	PX86PDPT pPdpt;
2525	PX86PDPE pPdpe;
2526	X86PDPE Pdpe;
2527
2528	PX86PDPAE pPd;
2529	PX86PDEPAE pPde;
2530	X86PDEPAE Pde;
2531
2532	PX86PTPAE pPt;
2533	PX86PTEPAE pPte;
2534	X86PTEPAE Pte;
2535	} PGMPTWALKGSTPAE;
2536	/** Pointer to a PAE guest page table walk. */
2537	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2538	/** Pointer to a const AMD64 guest page table walk. */
2539	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2540
2541	/**
2542	* Guest page table walk for the 32-bit mode.
2543	*/
2544	typedef struct PGMPTWALKGST32BIT
2545	{
2546	PX86PD pPd;
2547	PX86PDE pPde;
2548	X86PDE Pde;
2549
2550	PX86PT pPt;
2551	PX86PTE pPte;
2552	X86PTE Pte;
2553	} PGMPTWALKGST32BIT;
2554	/** Pointer to a 32-bit guest page table walk. */
2555	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2556	/** Pointer to a const 32-bit guest page table walk. */
2557	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2558
2559	/**
2560	* Which part of PGMPTWALKGST that is valid.
2561	*/
2562	typedef enum PGMPTWALKGSTTYPE
2563	{
2564	/** Customary invalid 0 value. */
2565	PGMPTWALKGSTTYPE_INVALID = 0,
2566	/** PGMPTWALKGST::u.Amd64 is valid. */
2567	PGMPTWALKGSTTYPE_AMD64,
2568	/** PGMPTWALKGST::u.Pae is valid. */
2569	PGMPTWALKGSTTYPE_PAE,
2570	/** PGMPTWALKGST::u.Legacy is valid. */
2571	PGMPTWALKGSTTYPE_32BIT,
2572	/** PGMPTWALKGST::u.Ept is valid. */
2573	PGMPTWALKGSTTYPE_EPT,
2574	/** Customary 32-bit type hack. */
2575	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2576	} PGMPTWALKGSTTYPE;
2577
2578	/**
2579	* Combined guest page table walk result.
2580	*/
2581	typedef struct PGMPTWALKGST
2582	{
2583	union
2584	{
2585	/** The page walker for AMD64. */
2586	PGMPTWALKGSTAMD64 Amd64;
2587	/** The page walker for PAE (32-bit). */
2588	PGMPTWALKGSTPAE Pae;
2589	/** The page walker for 32-bit paging (called legacy due to C naming
2590	* convension). */
2591	PGMPTWALKGST32BIT Legacy;
2592	/** The page walker for EPT (SLAT). */
2593	PGMPTWALKGSTEPT Ept;
2594	} u;
2595	/** Indicates which part of the union is valid. */
2596	PGMPTWALKGSTTYPE enmType;
2597	} PGMPTWALKGST;
2598	/** Pointer to a combined guest page table walk result. */
2599	typedef PGMPTWALKGST *PPGMPTWALKGST;
2600	/** Pointer to a read-only combined guest page table walk result. */
2601	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2602
2603
2604	/** @name Paging mode macros
2605	* @{
2606	*/
2607	#ifdef IN_RING3
2608	# define PGM_CTX(a,b) a##R3##b
2609	# define PGM_CTX_STR(a,b) a "R3" b
2610	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2611	#elif defined(IN_RING0)
2612	# define PGM_CTX(a,b) a##R0##b
2613	# define PGM_CTX_STR(a,b) a "R0" b
2614	# define PGM_CTX_DECL(type) VMMDECL(type)
2615	#else
2616	# error "Not IN_RING3 or IN_RING0!"
2617	#endif
2618
2619	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2620	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2621	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2622	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2623	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2624	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2625	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2626	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2627	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2628	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2629	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2630	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2631	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2632	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2633	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2634	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2635
2636	#define PGM_GST_SLAT_NAME_EPT(name) PGM_CTX(pgm,GstSlatEpt##name)
2637	#define PGM_GST_SLAT_NAME_RC_EPT_STR(name) "pgmRCGstSlatEpt" #name
2638	#define PGM_GST_SLAT_NAME_R0_EPT_STR(name) "pgmR0GstSlatEpt" #name
2639	#define PGM_GST_SLAT_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_SLAT_NAME(name)
2640
2641	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2642	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2643	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2644	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2645	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2646	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2647	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2648	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2649	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2650	#define PGM_SHW_NAME_NESTED_32BIT(name) PGM_CTX(pgm,ShwNested32Bit##name)
2651	#define PGM_SHW_NAME_RC_NESTED_32BIT_STR(name) "pgmRCShwNested32Bit" #name
2652	#define PGM_SHW_NAME_R0_NESTED_32BIT_STR(name) "pgmR0ShwNested32Bit" #name
2653	#define PGM_SHW_NAME_NESTED_PAE(name) PGM_CTX(pgm,ShwNestedPAE##name)
2654	#define PGM_SHW_NAME_RC_NESTED_PAE_STR(name) "pgmRCShwNestedPAE" #name
2655	#define PGM_SHW_NAME_R0_NESTED_PAE_STR(name) "pgmR0ShwNestedPAE" #name
2656	#define PGM_SHW_NAME_NESTED_AMD64(name) PGM_CTX(pgm,ShwNestedAMD64##name)
2657	#define PGM_SHW_NAME_RC_NESTED_AMD64_STR(name) "pgmRCShwNestedAMD64" #name
2658	#define PGM_SHW_NAME_R0_NESTED_AMD64_STR(name) "pgmR0ShwNestedAMD64" #name
2659	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2660	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2661	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2662	#define PGM_SHW_NAME_NONE(name) PGM_CTX(pgm,ShwNone##name)
2663	#define PGM_SHW_NAME_RC_NONE_STR(name) "pgmRCShwNone" #name
2664	#define PGM_SHW_NAME_R0_NONE_STR(name) "pgmR0ShwNone" #name
2665	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2666
2667	/* Shw_Gst */
2668	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2669	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2670	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2671	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2672	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2673	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2674	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2675	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2676	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2677	#define PGM_BTH_NAME_NESTED_32BIT_REAL(name) PGM_CTX(pgm,BthNested32BitReal##name)
2678	#define PGM_BTH_NAME_NESTED_32BIT_PROT(name) PGM_CTX(pgm,BthNested32BitProt##name)
2679	#define PGM_BTH_NAME_NESTED_32BIT_32BIT(name) PGM_CTX(pgm,BthNested32Bit32Bit##name)
2680	#define PGM_BTH_NAME_NESTED_32BIT_PAE(name) PGM_CTX(pgm,BthNested32BitPAE##name)
2681	#define PGM_BTH_NAME_NESTED_32BIT_AMD64(name) PGM_CTX(pgm,BthNested32BitAMD64##name)
2682	#define PGM_BTH_NAME_NESTED_PAE_REAL(name) PGM_CTX(pgm,BthNestedPAEReal##name)
2683	#define PGM_BTH_NAME_NESTED_PAE_PROT(name) PGM_CTX(pgm,BthNestedPAEProt##name)
2684	#define PGM_BTH_NAME_NESTED_PAE_32BIT(name) PGM_CTX(pgm,BthNestedPAE32Bit##name)
2685	#define PGM_BTH_NAME_NESTED_PAE_PAE(name) PGM_CTX(pgm,BthNestedPAEPAE##name)
2686	#define PGM_BTH_NAME_NESTED_PAE_AMD64(name) PGM_CTX(pgm,BthNestedPAEAMD64##name)
2687	#define PGM_BTH_NAME_NESTED_AMD64_REAL(name) PGM_CTX(pgm,BthNestedAMD64Real##name)
2688	#define PGM_BTH_NAME_NESTED_AMD64_PROT(name) PGM_CTX(pgm,BthNestedAMD64Prot##name)
2689	#define PGM_BTH_NAME_NESTED_AMD64_32BIT(name) PGM_CTX(pgm,BthNestedAMD6432Bit##name)
2690	#define PGM_BTH_NAME_NESTED_AMD64_PAE(name) PGM_CTX(pgm,BthNestedAMD64PAE##name)
2691	#define PGM_BTH_NAME_NESTED_AMD64_AMD64(name) PGM_CTX(pgm,BthNestedAMD64AMD64##name)
2692	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2693	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2694	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2695	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2696	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2697	#define PGM_BTH_NAME_NONE_REAL(name) PGM_CTX(pgm,BthNoneReal##name)
2698	#define PGM_BTH_NAME_NONE_PROT(name) PGM_CTX(pgm,BthNoneProt##name)
2699	#define PGM_BTH_NAME_NONE_32BIT(name) PGM_CTX(pgm,BthNone32Bit##name)
2700	#define PGM_BTH_NAME_NONE_PAE(name) PGM_CTX(pgm,BthNonePAE##name)
2701	#define PGM_BTH_NAME_NONE_AMD64(name) PGM_CTX(pgm,BthNoneAMD64##name)
2702
2703	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2704	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2705	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2706	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2707	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2708	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2709	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2710	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2711	#define PGM_BTH_NAME_RC_NESTED_32BIT_REAL_STR(name) "pgmRCBthNested32BitReal" #name
2712	#define PGM_BTH_NAME_RC_NESTED_32BIT_PROT_STR(name) "pgmRCBthNested32BitProt" #name
2713	#define PGM_BTH_NAME_RC_NESTED_32BIT_32BIT_STR(name) "pgmRCBthNested32Bit32Bit" #name
2714	#define PGM_BTH_NAME_RC_NESTED_32BIT_PAE_STR(name) "pgmRCBthNested32BitPAE" #name
2715	#define PGM_BTH_NAME_RC_NESTED_32BIT_AMD64_STR(name) "pgmRCBthNested32BitAMD64" #name
2716	#define PGM_BTH_NAME_RC_NESTED_PAE_REAL_STR(name) "pgmRCBthNestedPAEReal" #name
2717	#define PGM_BTH_NAME_RC_NESTED_PAE_PROT_STR(name) "pgmRCBthNestedPAEProt" #name
2718	#define PGM_BTH_NAME_RC_NESTED_PAE_32BIT_STR(name) "pgmRCBthNestedPAE32Bit" #name
2719	#define PGM_BTH_NAME_RC_NESTED_PAE_PAE_STR(name) "pgmRCBthNestedPAEPAE" #name
2720	#define PGM_BTH_NAME_RC_NESTED_PAE_AMD64_STR(name) "pgmRCBthNestedPAEAMD64" #name
2721	#define PGM_BTH_NAME_RC_NESTED_AMD64_REAL_STR(name) "pgmRCBthNestedAMD64Real" #name
2722	#define PGM_BTH_NAME_RC_NESTED_AMD64_PROT_STR(name) "pgmRCBthNestedAMD64Prot" #name
2723	#define PGM_BTH_NAME_RC_NESTED_AMD64_32BIT_STR(name) "pgmRCBthNestedAMD6432Bit" #name
2724	#define PGM_BTH_NAME_RC_NESTED_AMD64_PAE_STR(name) "pgmRCBthNestedAMD64PAE" #name
2725	#define PGM_BTH_NAME_RC_NESTED_AMD64_AMD64_STR(name) "pgmRCBthNestedAMD64AMD64" #name
2726	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2727	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2728	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2729	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2730	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2731
2732	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2733	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2734	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2735	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2736	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2737	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2738	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2739	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2740	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2741	#define PGM_BTH_NAME_R0_NESTED_32BIT_REAL_STR(name) "pgmR0BthNested32BitReal" #name
2742	#define PGM_BTH_NAME_R0_NESTED_32BIT_PROT_STR(name) "pgmR0BthNested32BitProt" #name
2743	#define PGM_BTH_NAME_R0_NESTED_32BIT_32BIT_STR(name) "pgmR0BthNested32Bit32Bit" #name
2744	#define PGM_BTH_NAME_R0_NESTED_32BIT_PAE_STR(name) "pgmR0BthNested32BitPAE" #name
2745	#define PGM_BTH_NAME_R0_NESTED_32BIT_AMD64_STR(name) "pgmR0BthNested32BitAMD64" #name
2746	#define PGM_BTH_NAME_R0_NESTED_PAE_REAL_STR(name) "pgmR0BthNestedPAEReal" #name
2747	#define PGM_BTH_NAME_R0_NESTED_PAE_PROT_STR(name) "pgmR0BthNestedPAEProt" #name
2748	#define PGM_BTH_NAME_R0_NESTED_PAE_32BIT_STR(name) "pgmR0BthNestedPAE32Bit" #name
2749	#define PGM_BTH_NAME_R0_NESTED_PAE_PAE_STR(name) "pgmR0BthNestedPAEPAE" #name
2750	#define PGM_BTH_NAME_R0_NESTED_PAE_AMD64_STR(name) "pgmR0BthNestedPAEAMD64" #name
2751	#define PGM_BTH_NAME_R0_NESTED_AMD64_REAL_STR(name) "pgmR0BthNestedAMD64Real" #name
2752	#define PGM_BTH_NAME_R0_NESTED_AMD64_PROT_STR(name) "pgmR0BthNestedAMD64Prot" #name
2753	#define PGM_BTH_NAME_R0_NESTED_AMD64_32BIT_STR(name) "pgmR0BthNestedAMD6432Bit" #name
2754	#define PGM_BTH_NAME_R0_NESTED_AMD64_PAE_STR(name) "pgmR0BthNestedAMD64PAE" #name
2755	#define PGM_BTH_NAME_R0_NESTED_AMD64_AMD64_STR(name) "pgmR0BthNestedAMD64AMD64" #name
2756	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2757	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2758	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2759	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2760	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2761
2762	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2763	/** @} */
2764
2765
2766	/**
2767	* Function pointers for guest paging.
2768	*/
2769	typedef struct PGMMODEDATAGST
2770	{
2771	/** The guest mode type. */
2772	uint32_t uType;
2773	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk));
2774	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2775	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2776	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2777	#ifdef IN_RING3
2778	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2779	#endif
2780	} PGMMODEDATAGST;
2781
2782	/** The length of g_aPgmGuestModeData. */
2783	#if VBOX_WITH_64_BITS_GUESTS
2784	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_AMD64 + 1)
2785	#else
2786	# define PGM_GUEST_MODE_DATA_ARRAY_SIZE (PGM_TYPE_PAE + 1)
2787	#endif
2788	/** The guest mode data array. */
2789	extern PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE];
2790
2791
2792	/**
2793	* Function pointers for shadow paging.
2794	*/
2795	typedef struct PGMMODEDATASHW
2796	{
2797	/** The shadow mode type. */
2798	uint32_t uType;
2799	DECLCALLBACKMEMBER(int, pfnGetPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2800	DECLCALLBACKMEMBER(int, pfnModifyPage,(PVMCPUCC pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags,
2801	uint64_t fMask, uint32_t fOpFlags));
2802	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu));
2803	DECLCALLBACKMEMBER(int, pfnExit,(PVMCPUCC pVCpu));
2804	#ifdef IN_RING3
2805	DECLCALLBACKMEMBER(int, pfnRelocate,(PVMCPUCC pVCpu, RTGCPTR offDelta)); /*< Only in ring-3. /
2806	#endif
2807	} PGMMODEDATASHW;
2808
2809	/** The length of g_aPgmShadowModeData. */
2810	#define PGM_SHADOW_MODE_DATA_ARRAY_SIZE PGM_TYPE_END
2811	/** The shadow mode data array. */
2812	extern PGMMODEDATASHW const g_aPgmShadowModeData[PGM_SHADOW_MODE_DATA_ARRAY_SIZE];
2813
2814
2815	/**
2816	* Function pointers for guest+shadow paging.
2817	*/
2818	typedef struct PGMMODEDATABTH
2819	{
2820	/** The shadow mode type. */
2821	uint32_t uShwType;
2822	/** The guest mode type. */
2823	uint32_t uGstType;
2824
2825	DECLCALLBACKMEMBER(int, pfnInvalidatePage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2826	DECLCALLBACKMEMBER(int, pfnSyncCR3,(PVMCPUCC pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2827	DECLCALLBACKMEMBER(int, pfnPrefetchPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage));
2828	DECLCALLBACKMEMBER(int, pfnVerifyAccessSyncPage,(PVMCPUCC pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2829	DECLCALLBACKMEMBER(int, pfnMapCR3,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2830	DECLCALLBACKMEMBER(int, pfnUnmapCR3,(PVMCPUCC pVCpu));
2831	DECLCALLBACKMEMBER(int, pfnEnter,(PVMCPUCC pVCpu, RTGCPHYS GCPhysCR3));
2832	#ifndef IN_RING3
2833	DECLCALLBACKMEMBER(int, pfnTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPTR pvFault, bool *pfLockTaken));
2834	DECLCALLBACKMEMBER(int, pfnNestedTrap0eHandler,(PVMCPUCC pVCpu, RTGCUINT uErr, PCPUMCTX pCtx, RTGCPHYS GCPhysNested,
2835	bool fIsLinearAddrValid, RTGCPTR GCPtrNested, PPGMPTWALK pWalk,
2836	bool *pfLockTaken));
2837	#endif
2838	#ifdef VBOX_STRICT
2839	DECLCALLBACKMEMBER(unsigned, pfnAssertCR3,(PVMCPUCC pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2840	#endif
2841	} PGMMODEDATABTH;
2842
2843	/** The length of g_aPgmBothModeData. */
2844	#define PGM_BOTH_MODE_DATA_ARRAY_SIZE ((PGM_TYPE_END - PGM_TYPE_FIRST_SHADOW) * PGM_TYPE_END)
2845	/** The guest+shadow mode data array. */
2846	extern PGMMODEDATABTH const g_aPgmBothModeData[PGM_BOTH_MODE_DATA_ARRAY_SIZE];
2847
2848
2849	#ifdef VBOX_WITH_STATISTICS
2850	/**
2851	* PGM statistics.
2852	*/
2853	typedef struct PGMSTATS
2854	{
2855	/* R3 only: */
2856	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
2857	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
2858
2859	/* R3+RZ */
2860	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
2861	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
2862	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
2863	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
2864	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2865	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
2866	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
2867	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
2868	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
2869	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
2870	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
2871	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
2872	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
2873	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
2874	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
2875	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
2876	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
2877	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
2878	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
2879	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
2880	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
2881	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
2882	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
2883	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
2884	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
2885	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
2886
2887	/* RC only: */
2888	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
2889	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
2890
2891	STAMCOUNTER StatRZPhysRead;
2892	STAMCOUNTER StatRZPhysReadBytes;
2893	STAMCOUNTER StatRZPhysWrite;
2894	STAMCOUNTER StatRZPhysWriteBytes;
2895	STAMCOUNTER StatR3PhysRead;
2896	STAMCOUNTER StatR3PhysReadBytes;
2897	STAMCOUNTER StatR3PhysWrite;
2898	STAMCOUNTER StatR3PhysWriteBytes;
2899	STAMCOUNTER StatRCPhysRead;
2900	STAMCOUNTER StatRCPhysReadBytes;
2901	STAMCOUNTER StatRCPhysWrite;
2902	STAMCOUNTER StatRCPhysWriteBytes;
2903
2904	STAMCOUNTER StatRZPhysSimpleRead;
2905	STAMCOUNTER StatRZPhysSimpleReadBytes;
2906	STAMCOUNTER StatRZPhysSimpleWrite;
2907	STAMCOUNTER StatRZPhysSimpleWriteBytes;
2908	STAMCOUNTER StatR3PhysSimpleRead;
2909	STAMCOUNTER StatR3PhysSimpleReadBytes;
2910	STAMCOUNTER StatR3PhysSimpleWrite;
2911	STAMCOUNTER StatR3PhysSimpleWriteBytes;
2912	STAMCOUNTER StatRCPhysSimpleRead;
2913	STAMCOUNTER StatRCPhysSimpleReadBytes;
2914	STAMCOUNTER StatRCPhysSimpleWrite;
2915	STAMCOUNTER StatRCPhysSimpleWriteBytes;
2916
2917	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
2918	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
2919	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
2920	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
2921	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
2922	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
2923	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
2924
2925	STAMPROFILE StatLargePageAlloc2; /*< Time spent setting up newly allocated large pages. /
2926	STAMPROFILE StatLargePageSetup; /*< Time spent setting up newly allocated large pages. /
2927	/** pgmPhysIsValidLargePage profiling - R3 */
2928	STAMPROFILE StatR3IsValidLargePage;
2929	/** pgmPhysIsValidLargePage profiling - RZ*/
2930	STAMPROFILE StatRZIsValidLargePage;
2931
2932	STAMPROFILE StatChunkAging;
2933	STAMPROFILE StatChunkFindCandidate;
2934	STAMPROFILE StatChunkUnmap;
2935	STAMPROFILE StatChunkMap;
2936	} PGMSTATS;
2937	#endif /* VBOX_WITH_STATISTICS */
2938
2939
2940	/**
2941	* PGM Data (part of VM)
2942	*/
2943	typedef struct PGM
2944	{
2945	/** The zero page. */
2946	uint8_t abZeroPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2947	/** The MMIO placeholder page. */
2948	uint8_t abMmioPg[RT_MAX(HOST_PAGE_SIZE, GUEST_PAGE_SIZE)];
2949
2950	/** @name The zero page (abPagePg).
2951	* @{ */
2952	/** The host physical address of the zero page. */
2953	RTHCPHYS HCPhysZeroPg;
2954	/** @}*/
2955
2956	/** @name The Invalid MMIO page (abMmioPg).
2957	* This page is filled with 0xfeedface.
2958	* @{ */
2959	/** The host physical address of the invalid MMIO page. */
2960	RTHCPHYS HCPhysMmioPg;
2961	/** The host pysical address of the invalid MMIO page plus all invalid
2962	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
2963	* @remarks Check fLessThan52PhysicalAddressBits before use. */
2964	RTHCPHYS HCPhysInvMmioPg;
2965	/** @} */
2966
2967	/** @cfgm{/RamPreAlloc, boolean, false}
2968	* Indicates whether the base RAM should all be allocated before starting
2969	* the VM (default), or if it should be allocated when first written to.
2970	*/
2971	bool fRamPreAlloc;
2972	#ifdef VBOX_WITH_PGM_NEM_MODE
2973	/** Set if we're operating in NEM memory mode.
2974	*
2975	* NEM mode implies that memory is allocated in big chunks for each RAM range
2976	* rather than on demand page by page. Memory is also not locked and PGM has
2977	* therefore no physical addresses for them. Page sharing is out of the
2978	* question. Ballooning depends on the native execution engine, but probably
2979	* pointless as well. */
2980	bool fNemMode;
2981	# define PGM_IS_IN_NEM_MODE(a_pVM) ((a_pVM)->pgm.s.fNemMode)
2982	#else
2983	# define PGM_IS_IN_NEM_MODE(a_pVM) (false)
2984	#endif
2985	/** Indicates whether write monitoring is currently in use.
2986	* This is used to prevent conflicts between live saving and page sharing
2987	* detection. */
2988	bool fPhysWriteMonitoringEngaged;
2989	/** Set if the CPU has less than 52-bit physical address width.
2990	* This is used */
2991	bool fLessThan52PhysicalAddressBits;
2992	/** Set when nested paging is active.
2993	* This is meant to save calls to HMIsNestedPagingActive and let the
2994	* compilers optimize the code better. Whether we use nested paging or
2995	* not is something we find out during VMM initialization and we won't
2996	* change this later on. */
2997	bool fNestedPaging;
2998	/** We're not in a state which permits writes to guest memory.
2999	* (Only used in strict builds.) */
3000	bool fNoMorePhysWrites;
3001	/** @cfgm{/PageFusionAllowed, boolean, false}
3002	* Whether page fusion is allowed. */
3003	bool fPageFusionAllowed;
3004	/** @cfgm{/PGM/PciPassThrough, boolean, false}
3005	* Whether PCI passthrough is enabled. */
3006	bool fPciPassthrough;
3007	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3008	uint8_t cMmio2Regions;
3009	/** Restore original ROM page content when resetting after loading state.
3010	* The flag is set by pgmR3LoadRomRanges and cleared at reset. This
3011	* enables the VM to start using an updated ROM without requiring powering
3012	* down the VM, just rebooting or resetting it. */
3013	bool fRestoreRomPagesOnReset;
3014	/** Whether to automatically clear all RAM pages on reset. */
3015	bool fZeroRamPagesOnReset;
3016	/** Large page enabled flag. */
3017	bool fUseLargePages;
3018	/** Alignment padding. */
3019	#ifndef VBOX_WITH_PGM_NEM_MODE
3020	bool afAlignment3[1];
3021	#endif
3022	/** The host paging mode. (This is what SUPLib reports.) */
3023	SUPPAGINGMODE enmHostMode;
3024	bool afAlignment3b[2];
3025
3026	/** Generation ID for the RAM ranges. This member is incremented everytime
3027	* a RAM range is linked or unlinked. */
3028	uint32_t volatile idRamRangesGen;
3029
3030	/** Physical access handler type for ROM protection. */
3031	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3032	/** Physical access handler type for MMIO2 dirty page tracing. */
3033	PGMPHYSHANDLERTYPE hMmio2DirtyPhysHandlerType;
3034
3035	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3036	RTGCPHYS GCPhys4MBPSEMask;
3037	/** Mask containing the invalid bits of a guest physical address.
3038	* @remarks this does not stop at bit 52. */
3039	RTGCPHYS GCPhysInvAddrMask;
3040
3041
3042	/** RAM range TLB for R3. */
3043	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3044	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3045	* This is sorted by physical address and contains no overlapping ranges. */
3046	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3047	/** Root of the RAM range search tree for ring-3. */
3048	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3049	/** Shadow Page Pool - R3 Ptr. */
3050	R3PTRTYPE(PPGMPOOL) pPoolR3;
3051	/** Pointer to the list of ROM ranges - for R3.
3052	* This is sorted by physical address and contains no overlapping ranges. */
3053	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3054	/** Pointer to the list of MMIO2 ranges - for R3.
3055	* Registration order. */
3056	R3PTRTYPE(PPGMREGMMIO2RANGE) pRegMmioRangesR3;
3057	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3058	R3PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3059
3060	/** RAM range TLB for R0. */
3061	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3062	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3063	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3064	/** Root of the RAM range search tree for ring-0. */
3065	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3066	/** Shadow Page Pool - R0 Ptr. */
3067	R0PTRTYPE(PPGMPOOL) pPoolR0;
3068	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3069	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3070	/** MMIO2 lookup array for ring-0. Indexed by idMmio2 minus 1. */
3071	R0PTRTYPE(PPGMREGMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3072
3073	/** Hack: Number of deprecated page mapping locks taken by the current lock
3074	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3075	uint32_t cDeprecatedPageLocks;
3076
3077	/** Registered physical access handler types. */
3078	uint32_t cPhysHandlerTypes;
3079	/** Physical access handler types.
3080	* Initialized to callback causing guru meditations and invalid enmKind. */
3081	PGMPHYSHANDLERTYPEINTR3 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3082	/** Physical handler allocator, ring-3 edition. */
3083	#ifdef IN_RING3
3084	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3085	#else
3086	RTCHardAvlTreeSlabAllocatorR3_T PhysHandlerAllocator;
3087	#endif
3088	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3089	R3PTRTYPE(PPGMPHYSHANDLERTREE) pPhysHandlerTree;
3090	/** Caching the last physical handler we looked. */
3091	uint32_t idxLastPhysHandler;
3092
3093	uint32_t au64Padding3[5];
3094
3095	/** PGM critical section.
3096	* This protects the physical, ram ranges, and the page flag updating (some of
3097	* it anyway).
3098	*/
3099	PDMCRITSECT CritSectX;
3100
3101	/**
3102	* Data associated with managing the ring-3 mappings of the allocation chunks.
3103	*/
3104	struct
3105	{
3106	/** The chunk mapping TLB. */
3107	PGMCHUNKR3MAPTLB Tlb;
3108	/** The chunk tree, ordered by chunk id. */
3109	R3PTRTYPE(PAVLU32NODECORE) pTree;
3110	#if HC_ARCH_BITS == 32
3111	uint32_t u32Alignment0;
3112	#endif
3113	/** The number of mapped chunks. */
3114	uint32_t c;
3115	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3116	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3117	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3118	uint32_t cMax;
3119	/** The current time. This is incremented whenever a chunk is inserted. */
3120	uint32_t iNow;
3121	/** Alignment padding. */
3122	uint32_t au32Alignment1[3];
3123	} ChunkR3Map;
3124
3125	/** The page mapping TLB for ring-3. */
3126	PGMPAGER3MAPTLB PhysTlbR3;
3127	/** The page mapping TLB for ring-0. */
3128	PGMPAGER0MAPTLB PhysTlbR0;
3129
3130	/** The number of handy pages. */
3131	uint32_t cHandyPages;
3132
3133	/** The number of large handy pages. */
3134	uint32_t cLargeHandyPages;
3135
3136	/**
3137	* Array of handy pages.
3138	*
3139	* This array is used in a two way communication between pgmPhysAllocPage
3140	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3141	* an intermediary.
3142	*
3143	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3144	* (The current size of 32 pages, means 128 KB of handy memory.)
3145	*/
3146	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3147
3148	/**
3149	* Array of large handy pages. (currently size 1)
3150	*
3151	* This array is used in a two way communication between pgmPhysAllocLargePage
3152	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3153	* an intermediary.
3154	*/
3155	GMMPAGEDESC aLargeHandyPage[1];
3156	/** When to try allocate large pages again after a failure. */
3157	uint64_t nsLargePageRetry;
3158	/** Number of repeated long allocation times. */
3159	uint32_t cLargePageLongAllocRepeats;
3160	uint32_t uPadding5;
3161
3162	/**
3163	* Live save data.
3164	*/
3165	struct
3166	{
3167	/** Per type statistics. */
3168	struct
3169	{
3170	/** The number of ready pages. */
3171	uint32_t cReadyPages;
3172	/** The number of dirty pages. */
3173	uint32_t cDirtyPages;
3174	/** The number of ready zero pages. */
3175	uint32_t cZeroPages;
3176	/** The number of write monitored pages. */
3177	uint32_t cMonitoredPages;
3178	} Rom,
3179	Mmio2,
3180	Ram;
3181	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3182	uint32_t cIgnoredPages;
3183	/** Indicates that a live save operation is active. */
3184	bool fActive;
3185	/** Padding. */
3186	bool afReserved[2];
3187	/** The next history index. */
3188	uint8_t iDirtyPagesHistory;
3189	/** History of the total amount of dirty pages. */
3190	uint32_t acDirtyPagesHistory[64];
3191	/** Short term dirty page average. */
3192	uint32_t cDirtyPagesShort;
3193	/** Long term dirty page average. */
3194	uint32_t cDirtyPagesLong;
3195	/** The number of saved pages. This is used to get some kind of estimate of the
3196	* link speed so we can decide when we're done. It is reset after the first
3197	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3198	* zero pages. */
3199	uint64_t cSavedPages;
3200	/** The nanosecond timestamp when cSavedPages was 0. */
3201	uint64_t uSaveStartNS;
3202	/** Pages per second (for statistics). */
3203	uint32_t cPagesPerSecond;
3204	uint32_t cAlignment;
3205	} LiveSave;
3206
3207	/** @name Error injection.
3208	* @{ */
3209	/** Inject handy page allocation errors pretending we're completely out of
3210	* memory. */
3211	bool volatile fErrInjHandyPages;
3212	/** Padding. */
3213	bool afReserved[3];
3214	/** @} */
3215
3216	/** @name Release Statistics
3217	* @{ */
3218	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3219	uint32_t cPrivatePages; /*< The number of private pages. /
3220	uint32_t cSharedPages; /*< The number of shared pages. /
3221	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3222	uint32_t cZeroPages; /*< The number of zero backed pages. /
3223	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3224	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3225	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3226	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3227	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3228	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3229	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3230	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3231	uint32_t cLargePages; /*< The number of large pages. /
3232	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3233	/* uint32_t aAlignment4[1]; */
3234
3235	STAMPROFILE StatLargePageAlloc; /*< Time spent by the host OS for large page allocation. /
3236	STAMCOUNTER StatLargePageAllocFailed; /*< Count allocation failures. /
3237	STAMCOUNTER StatLargePageOverflow; /*< The number of times allocating a large pages takes more than the allowed period. /
3238	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3239	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3240	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3241	STAMCOUNTER StatLargePageTlbFlush; /*< The number of a full VCPU TLB flush was required after allocation. /
3242	STAMCOUNTER StatLargePageZeroEvict; /*< The number of zero page mappings we had to evict when allocating a large page. /
3243
3244	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3245
3246	STAMPROFILE StatMmio2QueryAndResetDirtyBitmap; /*< Profiling PGMR3PhysMmio2QueryAndResetDirtyBitmap. /
3247	/** @} */
3248
3249	#ifdef VBOX_WITH_STATISTICS
3250	/** These are optional statistics that used to be on the hyper heap. */
3251	PGMSTATS Stats;
3252	#endif
3253	} PGM;
3254	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3255	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3256	AssertCompileMemberAlignment(PGM, ChunkR3Map, 16);
3257	AssertCompileMemberAlignment(PGM, PhysTlbR3, 32); /** @todo 32 byte alignment! */
3258	AssertCompileMemberAlignment(PGM, PhysTlbR0, 32);
3259	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3260	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3261	#endif /* !IN_TSTVMSTRUCTGC */
3262	/** Pointer to the PGM instance data. */
3263	typedef PGM *PPGM;
3264
3265
3266	#ifdef VBOX_WITH_STATISTICS
3267	/**
3268	* Per CPU statistis for PGM (used to be on the heap).
3269	*/
3270	typedef struct PGMCPUSTATS
3271	{
3272	/* Common */
3273	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3274	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3275
3276	/* R0 only: */
3277	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3278	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3279
3280	/* RZ only: */
3281	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3282	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3283	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3284	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3285	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3286	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3287	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3288	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3289	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3290	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3291	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3292	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3293	STAMPROFILE StatRZTrap0eTime2PageZeroing; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a zero page that is being zeroed. /
3294	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3295	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3296	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3297	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3298	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3299	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3300	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3301	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3302	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3303	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3304	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3305	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3306	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3307	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3308	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3309	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3310	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3311	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3312	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3313	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3314	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3315	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3316	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3317	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3318	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3319	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3320	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3321	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3322	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3323	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3324	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3325	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3326	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3327	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3328	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3329	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3330	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3331	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3332	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3333	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3334	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3335	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3336	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3337	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3338	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3339	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3340	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3341	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3342	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3343	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3344	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3345	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3346	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3347	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3348	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3349	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3350	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3351
3352	/* HC - R3 and (maybe) R0: */
3353
3354	/* RZ & R3: */
3355	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3356	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3357	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3358	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3359	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3360	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3361	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3362	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3363	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3364	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3365	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3366	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3367	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3368	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3369	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3370	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3371	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3372	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault(). /
3373	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3374	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3375	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3376	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3377	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3378	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3379	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3380	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3381	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3382	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3383	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3384	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3385	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3386	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3387	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3388	STAMCOUNTER StatRZInvalidatePageSizeChanges ; /*< RC/R0: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3389	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3390	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3391	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3392	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3393	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3394	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3395	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3396	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3397	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3398	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3399	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3400	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3401	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3402
3403	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3404	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3405	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3406	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3407	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3408	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3409	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3410	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3411	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3412	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3413	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3414	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3415	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3416	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3417	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3418	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3419	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3420	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3421	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3422	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3423	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3424	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3425	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3426	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3427	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3428	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3429	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3430	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3431	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3432	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3433	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3434	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3435	STAMCOUNTER StatR3InvalidatePageSizeChanges ; /*< R3: The number of times PGMInvalidatePage() was called on a page size change (4KB <-> 2/4MB). /
3436	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3437	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3438	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3439	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3440	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3441	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3442	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3443	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3444	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3445	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3446	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3447	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3448	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3449	} PGMCPUSTATS;
3450	#endif /* VBOX_WITH_STATISTICS */
3451
3452
3453	/**
3454	* PGMCPU Data (part of VMCPU).
3455	*/
3456	typedef struct PGMCPU
3457	{
3458	/** A20 gate mask.
3459	* Our current approach to A20 emulation is to let REM do it and don't bother
3460	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3461	* But whould need arrise, we'll subject physical addresses to this mask. */
3462	RTGCPHYS GCPhysA20Mask;
3463	/** A20 gate state - boolean! */
3464	bool fA20Enabled;
3465	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3466	bool fNoExecuteEnabled;
3467	/** Whether the guest CR3 and PAE PDPEs have been mapped when guest PAE mode is
3468	* active. */
3469	bool fPaePdpesAndCr3MappedR3;
3470	bool fPaePdpesAndCr3MappedR0;
3471
3472	/** What needs syncing (PGM_SYNC_*).
3473	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3474	* PGMFlushTLB, and PGMR3Load. */
3475	uint32_t fSyncFlags;
3476
3477	/** The shadow paging mode. */
3478	PGMMODE enmShadowMode;
3479	/** The guest paging mode. */
3480	PGMMODE enmGuestMode;
3481	/** The guest second level address translation mode. */
3482	PGMSLAT enmGuestSlatMode;
3483	/** Guest mode data table index (PGM_TYPE_XXX). */
3484	uint8_t volatile idxGuestModeData;
3485	/** Shadow mode data table index (PGM_TYPE_XXX). */
3486	uint8_t volatile idxShadowModeData;
3487	/** Both mode data table index (complicated). */
3488	uint8_t volatile idxBothModeData;
3489	/** Alignment padding. */
3490	uint8_t abPadding[1];
3491
3492	/** The guest CR3.
3493	* When SLAT is active, this is the translated physical address.
3494	* When SLAT is inactive, this is the physical address in CR3. */
3495	RTGCPHYS GCPhysCR3;
3496
3497	/** The nested-guest CR3.
3498	* When SLAT is active, this is CR3 prior to translation.
3499	* When SLAT is inactive, this is unused (and NIL_RTGCPHYS). */
3500	RTGCPHYS GCPhysNstGstCR3;
3501
3502	/** The cached guest CR3 when it has been mapped in PAE mode.
3503	* This allows us to skip remapping the CR3 and PAE PDPEs
3504	* (in PGMFlushTLB or similar) when it was already done as
3505	* part of MOV CRx instruction emulation.
3506	*/
3507	RTGCPHYS GCPhysPaeCR3;
3508
3509	/** @name 32-bit Guest Paging.
3510	* @{ */
3511	/** The guest's page directory, R3 pointer. */
3512	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3513	/** The guest's page directory, R0 pointer. */
3514	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3515	/** Mask containing the MBZ bits of a big page PDE. */
3516	uint32_t fGst32BitMbzBigPdeMask;
3517	/** Set if the page size extension (PSE) is enabled. */
3518	bool fGst32BitPageSizeExtension;
3519	/** Alignment padding. */
3520	bool afAlignment2[3];
3521	/** @} */
3522
3523	/** @name PAE Guest Paging.
3524	* @{ */
3525	/** The guest's page directory pointer table, R3 pointer. */
3526	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3527	/** The guest's page directory pointer table, R0 pointer. */
3528	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3529
3530	/** The guest's page directories, R3 pointers.
3531	* These are individual pointers and don't have to be adjacent.
3532	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3533	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3534	/** The guest's page directories, R0 pointers.
3535	* Same restrictions as apGstPaePDsR3. */
3536	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3537	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3538	RTGCPHYS aGCPhysGstPaePDs[4];
3539	/** Mask containing the MBZ PTE bits. */
3540	uint64_t fGstPaeMbzPteMask;
3541	/** Mask containing the MBZ PDE bits. */
3542	uint64_t fGstPaeMbzPdeMask;
3543	/** Mask containing the MBZ big page PDE bits. */
3544	uint64_t fGstPaeMbzBigPdeMask;
3545	/** Mask containing the MBZ PDPE bits. */
3546	uint64_t fGstPaeMbzPdpeMask;
3547	/** @} */
3548
3549	/** @name AMD64 Guest Paging.
3550	* @{ */
3551	/** The guest's page directory pointer table, R3 pointer. */
3552	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3553	/** The guest's page directory pointer table, R0 pointer. */
3554	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3555	/** Mask containing the MBZ PTE bits. */
3556	uint64_t fGstAmd64MbzPteMask;
3557	/** Mask containing the MBZ PDE bits. */
3558	uint64_t fGstAmd64MbzPdeMask;
3559	/** Mask containing the MBZ big page PDE bits. */
3560	uint64_t fGstAmd64MbzBigPdeMask;
3561	/** Mask containing the MBZ PDPE bits. */
3562	uint64_t fGstAmd64MbzPdpeMask;
3563	/** Mask containing the MBZ big page PDPE bits. */
3564	uint64_t fGstAmd64MbzBigPdpeMask;
3565	/** Mask containing the MBZ PML4E bits. */
3566	uint64_t fGstAmd64MbzPml4eMask;
3567	/** Mask containing the PDPE bits that we shadow. */
3568	uint64_t fGstAmd64ShadowedPdpeMask;
3569	/** Mask containing the PML4E bits that we shadow. */
3570	uint64_t fGstAmd64ShadowedPml4eMask;
3571	/** @} */
3572
3573	/** @name PAE and AMD64 Guest Paging.
3574	* @{ */
3575	/** Mask containing the PTE bits that we shadow. */
3576	uint64_t fGst64ShadowedPteMask;
3577	/** Mask containing the PDE bits that we shadow. */
3578	uint64_t fGst64ShadowedPdeMask;
3579	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3580	uint64_t fGst64ShadowedBigPdeMask;
3581	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3582	uint64_t fGst64ShadowedBigPde4PteMask;
3583	/** @} */
3584
3585	/** @name EPT Guest Paging.
3586	* @{ */
3587	/** The guest's EPT PML4 table, R3 pointer. */
3588	R3PTRTYPE(PEPTPML4) pGstEptPml4R3;
3589	/** The guest's EPT PML4 table, R0 pointer. */
3590	R0PTRTYPE(PEPTPML4) pGstEptPml4R0;
3591	/** The guest's EPT pointer (copy of virtual VMCS). */
3592	uint64_t uEptPtr;
3593	/** Copy of the VM's IA32_VMX_EPT_VPID_CAP VPID MSR for faster access. Doesn't
3594	* change through the lifetime of the VM. */
3595	uint64_t uEptVpidCapMsr;
3596	/** Mask containing the MBZ PTE bits. */
3597	uint64_t fGstEptMbzPteMask;
3598	/** Mask containing the MBZ PDE bits. */
3599	uint64_t fGstEptMbzPdeMask;
3600	/** Mask containing the MBZ big page (2M) PDE bits. */
3601	uint64_t fGstEptMbzBigPdeMask;
3602	/** Mask containing the MBZ PDPTE bits. */
3603	uint64_t fGstEptMbzPdpteMask;
3604	/** Mask containing the MBZ big page (1G) PDPTE bits. */
3605	uint64_t fGstEptMbzBigPdpteMask;
3606	/** Mask containing the MBZ PML4E bits. */
3607	uint64_t fGstEptMbzPml4eMask;
3608	/** Mask to determine whether an entry is present. */
3609	uint64_t fGstEptPresentMask;
3610
3611	/** Mask containing the EPT PTE bits we shadow. */
3612	uint64_t fGstEptShadowedPteMask;
3613	/** Mask containing the EPT PDE bits we shadow. */
3614	uint64_t fGstEptShadowedPdeMask;
3615	/** Mask containing the EPT PDE (2M) bits we shadow. */
3616	uint64_t fGstEptShadowedBigPdeMask;
3617	/** Mask containing the EPT PDPTE bits we shadow. */
3618	uint64_t fGstEptShadowedPdpteMask;
3619	/** Mask containing the EPT PML4E bits we shadow. */
3620	uint64_t fGstEptShadowedPml4eMask;
3621	/** @} */
3622
3623	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3624	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3625	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3626	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3627
3628	/** For saving stack space, the disassembler state is allocated here instead of
3629	* on the stack. */
3630	DISSTATE Dis;
3631
3632	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
3633	uint64_t cNetwareWp0Hacks;
3634
3635	/** Count the number of pgm pool access handler calls. */
3636	uint64_t cPoolAccessHandler;
3637
3638	/** @name Release Statistics
3639	* @{ */
3640	/** The number of times the guest has switched mode since last reset or statistics reset. */
3641	STAMCOUNTER cGuestModeChanges;
3642	/** The number of times the guest has switched mode since last reset or statistics reset. */
3643	STAMCOUNTER cA20Changes;
3644	/** @} */
3645
3646	#ifdef VBOX_WITH_STATISTICS
3647	/** These are statistics that used to be on the hyper heap. */
3648	PGMCPUSTATS Stats;
3649	#endif
3650	} PGMCPU;
3651	/** Pointer to the per-cpu PGM data. */
3652	typedef PGMCPU *PPGMCPU;
3653
3654
3655	/** @name PGM::fSyncFlags Flags
3656	* @note Was part of saved state a long time ago.
3657	* @{
3658	*/
3659	/* 0 used to be PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL */
3660	/** Always sync CR3. */
3661	#define PGM_SYNC_ALWAYS RT_BIT(1)
3662	/** Check guest mapping in SyncCR3. */
3663	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3664	/** Clear the page pool (a light weight flush). */
3665	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3666	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3667	/** @} */
3668
3669
3670	#if defined(IN_RING0) \|\| defined(DOXYGEN_RUNNING)
3671
3672	/**
3673	* PGM GVMCPU instance data.
3674	*/
3675	typedef struct PGMR0PERVCPU
3676	{
3677	# ifdef VBOX_WITH_STATISTICS
3678	/** R0: Which statistic this \#PF should be attributed to. */
3679	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3680	# endif
3681	uint64_t u64Dummy;
3682	} PGMR0PERVCPU;
3683
3684
3685	/**
3686	* PGM GVM instance data.
3687	*/
3688	typedef struct PGMR0PERVM
3689	{
3690	/** @name PGM Pool related stuff.
3691	* @{ */
3692	/** Critical section for serializing pool growth. */
3693	RTCRITSECT PoolGrowCritSect;
3694	/** The memory objects for the pool pages. */
3695	RTR0MEMOBJ ahPoolMemObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3696	/** The ring-3 mapping objects for the pool pages. */
3697	RTR0MEMOBJ ahPoolMapObjs[(PGMPOOL_IDX_LAST + PGMPOOL_CFG_MAX_GROW - 1) / PGMPOOL_CFG_MAX_GROW];
3698	/** @} */
3699
3700	/** Physical access handler types for ring-0.
3701	* Initialized to callback causing return to ring-3 and invalid enmKind. */
3702	PGMPHYSHANDLERTYPEINTR0 aPhysHandlerTypes[PGMPHYSHANDLERTYPE_COUNT];
3703	/** Physical handler allocator, ring-3 edition. */
3704	PGMPHYSHANDLERALLOCATOR PhysHandlerAllocator;
3705	/** The pointer to the ring-3 mapping of the physical access handler tree. */
3706	PPGMPHYSHANDLERTREE pPhysHandlerTree;
3707	/** The allocation object for the physical access handler tree. */
3708	RTR0MEMOBJ hPhysHandlerMemObj;
3709	/** The ring-3 mapping object for the physicall access handler tree. */
3710	RTR0MEMOBJ hPhysHandlerMapObj;
3711	} PGMR0PERVM;
3712
3713	#endif /* IN_RING0 \|\| DOXYGEN_RUNNING */
3714
3715	RT_C_DECLS_BEGIN
3716
3717	#if defined(VBOX_STRICT)
3718	int pgmLockDebug(PVMCC pVM, bool fVoid, RT_SRC_POS_DECL);
3719	# define PGM_LOCK_VOID(a_pVM) pgmLockDebug((a_pVM), true, RT_SRC_POS)
3720	# define PGM_LOCK(a_pVM) pgmLockDebug((a_pVM), false, RT_SRC_POS)
3721	#else
3722	int pgmLock(PVMCC pVM, bool fVoid);
3723	# define PGM_LOCK_VOID(a_pVM) pgmLock((a_pVM), true)
3724	# define PGM_LOCK(a_pVM) pgmLock((a_pVM), false)
3725	#endif
3726	void pgmUnlock(PVMCC pVM);
3727	# define PGM_UNLOCK(a_pVM) pgmUnlock((a_pVM))
3728	/**
3729	* Asserts that the caller owns the PDM lock.
3730	* This is the internal variant of PGMIsLockOwner.
3731	* @param a_pVM Pointer to the VM.
3732	*/
3733	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner((a_pVM), &(a_pVM)->pgm.s.CritSectX))
3734	/**
3735	* Asserts that the caller owns the PDM lock.
3736	* This is the internal variant of PGMIsLockOwner.
3737	* @param a_pVM Pointer to the VM.
3738	* @param a_pVCpu The current CPU handle.
3739	*/
3740	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx((a_pVCpu), &(a_pVM)->pgm.s.CritSectX))
3741
3742	uint32_t pgmHandlerPhysicalCalcTableSizes(uint32_t pcEntries, uint32_t pcbTreeAndBitmap);
3743	int pgmHandlerPhysicalExCreate(PVMCC pVM, PGMPHYSHANDLERTYPE hType, uint64_t uUser,
3744	R3PTRTYPE(const char ) pszDesc, PPGMPHYSHANDLER ppPhysHandler);
3745	int pgmHandlerPhysicalExDup(PVMCC pVM, PPGMPHYSHANDLER pPhysHandlerSrc, PPGMPHYSHANDLER *ppPhysHandler);
3746	int pgmHandlerPhysicalExRegister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler, RTGCPHYS GCPhys, RTGCPHYS GCPhysLast);
3747	int pgmHandlerPhysicalExDeregister(PVMCC pVM, PPGMPHYSHANDLER pPhysHandler);
3748	int pgmHandlerPhysicalExDestroy(PVMCC pVM, PPGMPHYSHANDLER pHandler);
3749	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3750	bool pgmHandlerPhysicalIsAll(PVMCC pVM, RTGCPHYS GCPhys);
3751	void pgmHandlerPhysicalResetAliasedPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, PPGMRAMRANGE pRam,
3752	bool fDoAccounting, bool fFlushIemTlbs);
3753	DECLHIDDEN(int) pgmHandlerPhysicalResetMmio2WithBitmap(PVMCC pVM, RTGCPHYS GCPhys, void *pvBitmap, uint32_t offBitmap);
3754	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3755	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR3HandlerPhysicalHandlerInvalid;
3756	#ifndef IN_RING3
3757	DECLCALLBACK(FNPGMPHYSHANDLER) pgmR0HandlerPhysicalHandlerToRing3;
3758	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmR0HandlerPhysicalPfHandlerToRing3;
3759	#endif
3760
3761	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3762
3763	int pgmPhysAllocPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3764	int pgmPhysAllocLargePage(PVMCC pVM, RTGCPHYS GCPhys);
3765	#ifdef IN_RING0
3766	int pgmR0PhysAllocateHandyPages(PGVM pGVM, VMCPUID idCpu, bool fRing3);
3767	int pgmR0PhysAllocateLargePage(PGVM pGVM, VMCPUID idCpu, RTGCPHYS GCPhys);
3768	#endif
3769	int pgmPhysRecheckLargePage(PVMCC pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3770	int pgmPhysPageLoadIntoTlb(PVMCC pVM, RTGCPHYS GCPhys);
3771	int pgmPhysPageLoadIntoTlbWithPage(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3772	void pgmPhysPageMakeWriteMonitoredWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3773	int pgmPhysPageMakeWritable(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3774	int pgmPhysPageMakeWritableAndMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3775	int pgmPhysPageMap(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3776	int pgmPhysPageMapReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3777	int pgmPhysPageMapByPageID(PVMCC pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3778	int pgmPhysGCPhys2R3Ptr(PVMCC pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3779	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
3780	int pgmPhysGCPhys2CCPtrInternalDepr(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3781	int pgmPhysGCPhys2CCPtrInternal(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
3782	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVMCC pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
3783	void pgmPhysReleaseInternalPageMappingLock(PVMCC pVM, PPGMPAGEMAPLOCK pLock);
3784	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysRomWriteHandler;
3785	DECLCALLBACK(FNPGMPHYSHANDLER) pgmPhysMmio2WriteHandler;
3786	#ifndef IN_RING3
3787	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysRomWritePfHandler;
3788	DECLCALLBACK(FNPGMRZPHYSPFHANDLER) pgmPhysMmio2WritePfHandler;
3789	#endif
3790	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys,
3791	PGMPAGETYPE enmNewType);
3792	void pgmPhysInvalidRamRangeTlbs(PVMCC pVM);
3793	void pgmPhysInvalidatePageMapTLB(PVMCC pVM);
3794	void pgmPhysInvalidatePageMapTLBEntry(PVMCC pVM, RTGCPHYS GCPhys);
3795	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
3796	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
3797	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
3798	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
3799	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
3800	#ifdef VBOX_WITH_NATIVE_NEM
3801	void pgmPhysSetNemStateForPages(PPGMPAGE paPages, RTGCPHYS cPages, uint8_t u2State);
3802	#endif
3803
3804	#ifdef IN_RING3
3805	void pgmR3PhysRelinkRamRanges(PVM pVM);
3806	int pgmR3PhysRamPreAllocate(PVM pVM);
3807	int pgmR3PhysRamReset(PVM pVM);
3808	int pgmR3PhysRomReset(PVM pVM);
3809	int pgmR3PhysRamZeroAll(PVM pVM);
3810	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3811	int pgmR3PhysRamTerm(PVM pVM);
3812	void pgmR3PhysRomTerm(PVM pVM);
3813	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
3814
3815	int pgmR3PoolInit(PVM pVM);
3816	void pgmR3PoolRelocate(PVM pVM);
3817	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3818	void pgmR3PoolReset(PVM pVM);
3819	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3820	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3821	void pgmR3PoolWriteProtectPages(PVM pVM);
3822
3823	#endif /* IN_RING3 */
3824	#ifdef IN_RING0
3825	int pgmR0PoolInitVM(PGVM pGVM);
3826	#endif
3827	int pgmPoolAlloc(PVMCC pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
3828	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3829	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3830	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3831	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3832	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3833	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3834	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3835	int pgmPoolHCPhys2Ptr(PVM pVM, RTHCPHYS HCPhys, void **ppv);
3836	int pgmPoolSyncCR3(PVMCPUCC pVCpu);
3837	bool pgmPoolIsDirtyPageSlow(PVMCC pVM, RTGCPHYS GCPhys);
3838	void pgmPoolInvalidateDirtyPage(PVMCC pVM, RTGCPHYS GCPhysPT);
3839	int pgmPoolTrackUpdateGCPhys(PVMCC pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3840	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3841	uint16_t pgmPoolTrackPhysExtAddref(PVMCC pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3842	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3843	void pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3844	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3845	FNPGMPHYSHANDLER pgmPoolAccessHandler;
3846	#ifndef IN_RING3
3847	FNPGMRZPHYSPFHANDLER pgmRZPoolAccessPfHandler;
3848	#endif
3849
3850	void pgmPoolAddDirtyPage(PVMCC pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3851	void pgmPoolResetDirtyPages(PVMCC pVM);
3852	void pgmPoolResetDirtyPage(PVMCC pVM, RTGCPTR GCPtrPage);
3853
3854	/** Gets the ring-0 pointer for the given pool page. */
3855	DECLINLINE(R0PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR0(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3856	{
3857	#ifdef IN_RING3
3858	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3859	# ifdef VBOX_STRICT
3860	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3861	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR0PTR);
3862	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR0PTR);
3863	# endif
3864	return pPool->pPoolR0 + offPage;
3865	#else
3866	RT_NOREF(pPool);
3867	return pPage;
3868	#endif
3869	}
3870
3871	/** Gets the ring-3 pointer for the given pool page. */
3872	DECLINLINE(R3PTRTYPE(PPGMPOOLPAGE)) pgmPoolConvertPageToR3(PPGMPOOL pPool, PPGMPOOLPAGE pPage)
3873	{
3874	#ifdef IN_RING3
3875	RT_NOREF(pPool);
3876	return pPage;
3877	#else
3878	size_t offPage = (uintptr_t)pPage - (uintptr_t)pPool;
3879	# ifdef VBOX_STRICT
3880	size_t iPage = (offPage - RT_UOFFSETOF(PGMPOOL, aPages)) / sizeof(*pPage);
3881	AssertReturn(iPage < pPool->cMaxPages, NIL_RTR3PTR);
3882	AssertReturn(iPage * sizeof(*pPage) + RT_UOFFSETOF(PGMPOOL, aPages) == offPage, NIL_RTR3PTR);
3883	# endif
3884	return pPool->pPoolR3 + offPage;
3885	#endif
3886	}
3887
3888	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
3889	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3890	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
3891
3892	int pgmShwMakePageSupervisorAndWritable(PVMCPUCC pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
3893	int pgmShwSyncPaePDPtr(PVMCPUCC pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3894	int pgmShwSyncNestedPageLocked(PVMCPUCC pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3895
3896	int pgmGstLazyMap32BitPD(PVMCPUCC pVCpu, PX86PD *ppPd);
3897	int pgmGstLazyMapPaePDPT(PVMCPUCC pVCpu, PX86PDPT *ppPdpt);
3898	int pgmGstLazyMapPaePD(PVMCPUCC pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3899	int pgmGstLazyMapPml4(PVMCPUCC pVCpu, PX86PML4 *ppPml4);
3900	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
3901	int pgmGstLazyMapEptPml4(PVMCPUCC pVCpu, PEPTPML4 *ppPml4);
3902	#endif
3903	int pgmGstPtWalk(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3904	int pgmGstPtWalkNext(PVMCPUCC pVCpu, RTGCPTR GCPtr, PPGMPTWALK pWalk, PPGMPTWALKGST pGstWalk);
3905
3906	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
3907	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
3908	FNDBGCCMD pgmR3CmdShowSharedModules;
3909	# endif
3910
3911	void pgmLogState(PVM pVM);
3912
3913	RT_C_DECLS_END
3914
3915	/** @} */
3916
3917	#endif /* !VMM_INCLUDED_SRC_include_PGMInternal_h */
3918

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 104407

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