VirtualBox

source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 36441

Last change on this file since 36441 was 36441, checked in by vboxsync, 14 years ago

VMM: Sketched out where to do the initial I/O MMU setup. This adds a VMINITCOMPLETED_HWACCM and makes HWACCMR3InitFinalizeR0 private (invoked from HWACCMR3InitCompleted(,_RING0).
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 175.1 KB
Line 
1/* $Id: PGMInternal.h 36441 2011-03-25 21:11:56Z vboxsync $ */
2/** @file
3 * PGM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___PGMInternal_h
19#define ___PGMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/err.h>
24#include <VBox/dbg.h>
25#include <VBox/vmm/stam.h>
26#include <VBox/param.h>
27#include <VBox/vmm/vmm.h>
28#include <VBox/vmm/mm.h>
29#include <VBox/vmm/pdmcritsect.h>
30#include <VBox/vmm/pdmapi.h>
31#include <VBox/dis.h>
32#include <VBox/vmm/dbgf.h>
33#include <VBox/log.h>
34#include <VBox/vmm/gmm.h>
35#include <VBox/vmm/hwaccm.h>
36#include <VBox/vmm/hwacc_vmx.h>
37#include "internal/pgm.h"
38#include <iprt/asm.h>
39#include <iprt/assert.h>
40#include <iprt/avl.h>
41#include <iprt/critsect.h>
42#include <iprt/sha.h>
43
44
45
46/** @defgroup grp_pgm_int Internals
47 * @ingroup grp_pgm
48 * @internal
49 * @{
50 */
51
52
53/** @name PGM Compile Time Config
54 * @{
55 */
56
57/**
58 * Indicates that there are no guest mappings to care about.
59 * Currently on raw-mode related code uses mappings, i.e. RC and R3 code.
60 */
61#if defined(IN_RING0) || !defined(VBOX_WITH_RAW_MODE)
62# define PGM_WITHOUT_MAPPINGS
63#endif
64
65/**
66 * Check and skip global PDEs for non-global flushes
67 */
68#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
69
70/**
71 * Optimization for PAE page tables that are modified often
72 */
73//#if 0 /* disabled again while debugging */
74#ifndef IN_RC
75# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
76#endif
77//#endif
78
79/**
80 * Large page support enabled only on 64 bits hosts; applies to nested paging only.
81 */
82#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
83# define PGM_WITH_LARGE_PAGES
84#endif
85
86/**
87 * Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
88 * VMX_EXIT_EPT_MISCONFIG.
89 */
90#if 1 /* testing */
91# define PGM_WITH_MMIO_OPTIMIZATIONS
92#endif
93
94/**
95 * Chunk unmapping code activated on 32-bit hosts for > 1.5/2 GB guest memory support
96 */
97#if (HC_ARCH_BITS == 32) && !defined(RT_OS_DARWIN)
98# define PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
99#endif
100
101/**
102 * Sync N pages instead of a whole page table
103 */
104#define PGM_SYNC_N_PAGES
105
106/**
107 * Number of pages to sync during a page fault
108 *
109 * When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
110 * causes a lot of unnecessary extents and also is slower than taking more \#PFs.
111 *
112 * Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
113 * world switch overhead, so let's sync more.
114 */
115# ifdef IN_RING0
116/* Chose 32 based on the compile test in #4219; 64 shows worse stats.
117 * 32 again shows better results than 16; slightly more overhead in the \#PF handler,
118 * but ~5% fewer faults.
119 */
120# define PGM_SYNC_NR_PAGES 32
121#else
122# define PGM_SYNC_NR_PAGES 8
123#endif
124
125/**
126 * Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
127 */
128#define PGM_MAX_PHYSCACHE_ENTRIES 64
129#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
130
131
132/** @def PGMPOOL_CFG_MAX_GROW
133 * The maximum number of pages to add to the pool in one go.
134 */
135#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
136
137/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
138 * Enables some extra assertions for virtual handlers (mainly phys2virt related).
139 */
140#ifdef VBOX_STRICT
141# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
142#endif
143
144/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
145 * Enables the experimental lazy page allocation code. */
146/*#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC */
147
148/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
149 * Enables real write monitoring of pages, i.e. mapping them read-only and
150 * only making them writable when getting a write access #PF. */
151#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
152
153/** @} */
154
155
156/** @name PDPT and PML4 flags.
157 * These are placed in the three bits available for system programs in
158 * the PDPT and PML4 entries.
159 * @{ */
160/** The entry is a permanent one and it's must always be present.
161 * Never free such an entry. */
162#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
163/** Mapping (hypervisor allocated pagetable). */
164#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
165/** @} */
166
167/** @name Page directory flags.
168 * These are placed in the three bits available for system programs in
169 * the page directory entries.
170 * @{ */
171/** Mapping (hypervisor allocated pagetable). */
172#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
173/** Made read-only to facilitate dirty bit tracking. */
174#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
175/** @} */
176
177/** @name Page flags.
178 * These are placed in the three bits available for system programs in
179 * the page entries.
180 * @{ */
181/** Made read-only to facilitate dirty bit tracking. */
182#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
183
184#ifndef PGM_PTFLAGS_CSAM_VALIDATED
185/** Scanned and approved by CSAM (tm).
186 * NOTE: Must be identical to the one defined in CSAMInternal.h!!
187 * @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
188#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
189#endif
190
191/** @} */
192
193/** @name Defines used to indicate the shadow and guest paging in the templates.
194 * @{ */
195#define PGM_TYPE_REAL 1
196#define PGM_TYPE_PROT 2
197#define PGM_TYPE_32BIT 3
198#define PGM_TYPE_PAE 4
199#define PGM_TYPE_AMD64 5
200#define PGM_TYPE_NESTED 6
201#define PGM_TYPE_EPT 7
202#define PGM_TYPE_MAX PGM_TYPE_EPT
203/** @} */
204
205/** Macro for checking if the guest is using paging.
206 * @param uGstType PGM_TYPE_*
207 * @param uShwType PGM_TYPE_*
208 * @remark ASSUMES certain order of the PGM_TYPE_* values.
209 */
210#define PGM_WITH_PAGING(uGstType, uShwType) \
211 ( (uGstType) >= PGM_TYPE_32BIT \
212 && (uShwType) != PGM_TYPE_NESTED \
213 && (uShwType) != PGM_TYPE_EPT)
214
215/** Macro for checking if the guest supports the NX bit.
216 * @param uGstType PGM_TYPE_*
217 * @param uShwType PGM_TYPE_*
218 * @remark ASSUMES certain order of the PGM_TYPE_* values.
219 */
220#define PGM_WITH_NX(uGstType, uShwType) \
221 ( (uGstType) >= PGM_TYPE_PAE \
222 && (uShwType) != PGM_TYPE_NESTED \
223 && (uShwType) != PGM_TYPE_EPT)
224
225
226/** @def PGM_HCPHYS_2_PTR
227 * Maps a HC physical page pool address to a virtual address.
228 *
229 * @returns VBox status code.
230 * @param pVM The VM handle.
231 * @param pVCpu The current CPU.
232 * @param HCPhys The HC physical address to map to a virtual one.
233 * @param ppv Where to store the virtual address. No need to cast
234 * this.
235 *
236 * @remark Use with care as we don't have so much dynamic mapping space in
237 * ring-0 on 32-bit darwin and in RC.
238 * @remark There is no need to assert on the result.
239 */
240#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
241# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
242 pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
243#else
244# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
245 MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
246#endif
247
248/** @def PGM_GCPHYS_2_PTR_V2
249 * Maps a GC physical page address to a virtual address.
250 *
251 * @returns VBox status code.
252 * @param pVM The VM handle.
253 * @param pVCpu The current CPU.
254 * @param GCPhys The GC physical address to map to a virtual one.
255 * @param ppv Where to store the virtual address. No need to cast this.
256 *
257 * @remark Use with care as we don't have so much dynamic mapping space in
258 * ring-0 on 32-bit darwin and in RC.
259 * @remark There is no need to assert on the result.
260 */
261#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
262# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
263 pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
264#else
265# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
266 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
267#endif
268
269/** @def PGM_GCPHYS_2_PTR
270 * Maps a GC physical page address to a virtual address.
271 *
272 * @returns VBox status code.
273 * @param pVM The VM handle.
274 * @param GCPhys The GC physical address to map to a virtual one.
275 * @param ppv Where to store the virtual address. No need to cast this.
276 *
277 * @remark Use with care as we don't have so much dynamic mapping space in
278 * ring-0 on 32-bit darwin and in RC.
279 * @remark There is no need to assert on the result.
280 */
281#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
282
283/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
284 * Maps a GC physical page address to a virtual address.
285 *
286 * @returns VBox status code.
287 * @param pVCpu The current CPU.
288 * @param GCPhys The GC physical address to map to a virtual one.
289 * @param ppv Where to store the virtual address. No need to cast this.
290 *
291 * @remark Use with care as we don't have so much dynamic mapping space in
292 * ring-0 on 32-bit darwin and in RC.
293 * @remark There is no need to assert on the result.
294 */
295#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
296
297/** @def PGM_GCPHYS_2_PTR_EX
298 * Maps a unaligned GC physical page address to a virtual address.
299 *
300 * @returns VBox status code.
301 * @param pVM The VM handle.
302 * @param GCPhys The GC physical address to map to a virtual one.
303 * @param ppv Where to store the virtual address. No need to cast this.
304 *
305 * @remark Use with care as we don't have so much dynamic mapping space in
306 * ring-0 on 32-bit darwin and in RC.
307 * @remark There is no need to assert on the result.
308 */
309#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
310# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
311 pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
312#else
313# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
314 PGMPhysGCPhys2R3Ptr(pVM, GCPhys, 1 /* one page only */, (PRTR3PTR)(ppv)) /** @todo this isn't asserting, use PGMRamGCPhys2HCPtr! */
315#endif
316
317/** @def PGM_DYNMAP_UNUSED_HINT
318 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
319 * is no longer used.
320 *
321 * For best effect only apply this to the page that was mapped most recently.
322 *
323 * @param pVCpu The current CPU.
324 * @param pPage The pool page.
325 */
326#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
327# ifdef LOG_ENABLED
328# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
329# else
330# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
331# endif
332#else
333# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
334#endif
335
336/** @def PGM_DYNMAP_UNUSED_HINT_VM
337 * Hints to the dynamic mapping code in RC and R0/darwin that the specified page
338 * is no longer used.
339 *
340 * For best effect only apply this to the page that was mapped most recently.
341 *
342 * @param pVM The VM handle.
343 * @param pPage The pool page.
344 */
345#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
346
347
348/** @def PGM_INVL_PG
349 * Invalidates a page.
350 *
351 * @param pVCpu The VMCPU handle.
352 * @param GCVirt The virtual address of the page to invalidate.
353 */
354#ifdef IN_RC
355# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
356#elif defined(IN_RING0)
357# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
358#else
359# define PGM_INVL_PG(pVCpu, GCVirt) HWACCMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
360#endif
361
362/** @def PGM_INVL_PG_ALL_VCPU
363 * Invalidates a page on all VCPUs
364 *
365 * @param pVM The VM handle.
366 * @param GCVirt The virtual address of the page to invalidate.
367 */
368#ifdef IN_RC
369# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
370#elif defined(IN_RING0)
371# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
372#else
373# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HWACCMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
374#endif
375
376/** @def PGM_INVL_BIG_PG
377 * Invalidates a 4MB page directory entry.
378 *
379 * @param pVCpu The VMCPU handle.
380 * @param GCVirt The virtual address within the page directory to invalidate.
381 */
382#ifdef IN_RC
383# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
384#elif defined(IN_RING0)
385# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
386#else
387# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HWACCMFlushTLB(pVCpu)
388#endif
389
390/** @def PGM_INVL_VCPU_TLBS()
391 * Invalidates the TLBs of the specified VCPU
392 *
393 * @param pVCpu The VMCPU handle.
394 */
395#ifdef IN_RC
396# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
397#elif defined(IN_RING0)
398# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
399#else
400# define PGM_INVL_VCPU_TLBS(pVCpu) HWACCMFlushTLB(pVCpu)
401#endif
402
403/** @def PGM_INVL_ALL_VCPU_TLBS()
404 * Invalidates the TLBs of all VCPUs
405 *
406 * @param pVM The VM handle.
407 */
408#ifdef IN_RC
409# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
410#elif defined(IN_RING0)
411# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
412#else
413# define PGM_INVL_ALL_VCPU_TLBS(pVM) HWACCMFlushTLBOnAllVCpus(pVM)
414#endif
415
416
417/** @name Safer Shadow PAE PT/PTE
418 * For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
419 * present.
420 *
421 * @{
422 */
423#if 1
424/**
425 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
426 * invalid entries for present.
427 * @sa X86PTEPAE.
428 */
429typedef union PGMSHWPTEPAE
430{
431 /** Unsigned integer view */
432 X86PGPAEUINT uCareful;
433 /* Not other views. */
434} PGMSHWPTEPAE;
435
436# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
437# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
438# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
439# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
440# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
441# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
442# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P | X86_PTE_RW | X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P | X86_PTE_RW) )
443# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
444# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
445# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /**< Use with care. */
446# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
447# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
448# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
449# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
450# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
451# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful |= X86_PTE_RW; } while (0)
452
453/**
454 * For making sure that u1Present and X86_PTE_P checks doesn't mistake
455 * invalid entries for present.
456 * @sa X86PTPAE.
457 */
458typedef struct PGMSHWPTPAE
459{
460 PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
461} PGMSHWPTPAE;
462
463#else
464typedef X86PTEPAE PGMSHWPTEPAE;
465typedef X86PTPAE PGMSHWPTPAE;
466# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
467# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
468# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
469# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
470# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
471# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
472# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P | X86_PTE_RW)) == (X86_PTE_P | X86_PTE_RW) )
473# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
474# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
475# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /**< Use with care. */
476# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
477# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
478# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
479# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
480# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
481# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u |= X86_PTE_RW; } while (0)
482
483#endif
484
485/** Pointer to a shadow PAE PTE. */
486typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
487/** Pointer to a const shadow PAE PTE. */
488typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
489
490/** Pointer to a shadow PAE page table. */
491typedef PGMSHWPTPAE *PPGMSHWPTPAE;
492/** Pointer to a const shadow PAE page table. */
493typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
494/** @} */
495
496
497/** Size of the GCPtrConflict array in PGMMAPPING.
498 * @remarks Must be a power of two. */
499#define PGMMAPPING_CONFLICT_MAX 8
500
501/**
502 * Structure for tracking GC Mappings.
503 *
504 * This structure is used by linked list in both GC and HC.
505 */
506typedef struct PGMMAPPING
507{
508 /** Pointer to next entry. */
509 R3PTRTYPE(struct PGMMAPPING *) pNextR3;
510 /** Pointer to next entry. */
511 R0PTRTYPE(struct PGMMAPPING *) pNextR0;
512 /** Pointer to next entry. */
513 RCPTRTYPE(struct PGMMAPPING *) pNextRC;
514 /** Indicate whether this entry is finalized. */
515 bool fFinalized;
516 /** Start Virtual address. */
517 RTGCPTR GCPtr;
518 /** Last Virtual address (inclusive). */
519 RTGCPTR GCPtrLast;
520 /** Range size (bytes). */
521 RTGCPTR cb;
522 /** Pointer to relocation callback function. */
523 R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
524 /** User argument to the callback. */
525 R3PTRTYPE(void *) pvUser;
526 /** Mapping description / name. For easing debugging. */
527 R3PTRTYPE(const char *) pszDesc;
528 /** Last 8 addresses that caused conflicts. */
529 RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
530 /** Number of conflicts for this hypervisor mapping. */
531 uint32_t cConflicts;
532 /** Number of page tables. */
533 uint32_t cPTs;
534
535 /** Array of page table mapping data. Each entry
536 * describes one page table. The array can be longer
537 * than the declared length.
538 */
539 struct
540 {
541 /** The HC physical address of the page table. */
542 RTHCPHYS HCPhysPT;
543 /** The HC physical address of the first PAE page table. */
544 RTHCPHYS HCPhysPaePT0;
545 /** The HC physical address of the second PAE page table. */
546 RTHCPHYS HCPhysPaePT1;
547 /** The HC virtual address of the 32-bit page table. */
548 R3PTRTYPE(PX86PT) pPTR3;
549 /** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
550 R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
551 /** The RC virtual address of the 32-bit page table. */
552 RCPTRTYPE(PX86PT) pPTRC;
553 /** The RC virtual address of the two PAE page table. */
554 RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
555 /** The R0 virtual address of the 32-bit page table. */
556 R0PTRTYPE(PX86PT) pPTR0;
557 /** The R0 virtual address of the two PAE page table. */
558 R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
559 } aPTs[1];
560} PGMMAPPING;
561/** Pointer to structure for tracking GC Mappings. */
562typedef struct PGMMAPPING *PPGMMAPPING;
563
564
565/**
566 * Physical page access handler structure.
567 *
568 * This is used to keep track of physical address ranges
569 * which are being monitored in some kind of way.
570 */
571typedef struct PGMPHYSHANDLER
572{
573 AVLROGCPHYSNODECORE Core;
574 /** Access type. */
575 PGMPHYSHANDLERTYPE enmType;
576 /** Number of pages to update. */
577 uint32_t cPages;
578 /** Set if we have pages that have been aliased. */
579 uint32_t cAliasedPages;
580 /** Set if we have pages that have temporarily been disabled. */
581 uint32_t cTmpOffPages;
582 /** Pointer to R3 callback function. */
583 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
584 /** User argument for R3 handlers. */
585 R3PTRTYPE(void *) pvUserR3;
586 /** Pointer to R0 callback function. */
587 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
588 /** User argument for R0 handlers. */
589 R0PTRTYPE(void *) pvUserR0;
590 /** Pointer to RC callback function. */
591 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
592 /** User argument for RC handlers. */
593 RCPTRTYPE(void *) pvUserRC;
594 /** Description / Name. For easing debugging. */
595 R3PTRTYPE(const char *) pszDesc;
596#ifdef VBOX_WITH_STATISTICS
597 /** Profiling of this handler. */
598 STAMPROFILE Stat;
599#endif
600} PGMPHYSHANDLER;
601/** Pointer to a physical page access handler structure. */
602typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
603
604
605/**
606 * Cache node for the physical addresses covered by a virtual handler.
607 */
608typedef struct PGMPHYS2VIRTHANDLER
609{
610 /** Core node for the tree based on physical ranges. */
611 AVLROGCPHYSNODECORE Core;
612 /** Offset from this struct to the PGMVIRTHANDLER structure. */
613 int32_t offVirtHandler;
614 /** Offset of the next alias relative to this one.
615 * Bit 0 is used for indicating whether we're in the tree.
616 * Bit 1 is used for indicating that we're the head node.
617 */
618 int32_t offNextAlias;
619} PGMPHYS2VIRTHANDLER;
620/** Pointer to a phys to virtual handler structure. */
621typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
622
623/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
624 * node is in the tree. */
625#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
626/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
627 * node is in the head of an alias chain.
628 * The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
629#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
630/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
631#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
632
633
634/**
635 * Virtual page access handler structure.
636 *
637 * This is used to keep track of virtual address ranges
638 * which are being monitored in some kind of way.
639 */
640typedef struct PGMVIRTHANDLER
641{
642 /** Core node for the tree based on virtual ranges. */
643 AVLROGCPTRNODECORE Core;
644 /** Size of the range (in bytes). */
645 RTGCPTR cb;
646 /** Number of cache pages. */
647 uint32_t cPages;
648 /** Access type. */
649 PGMVIRTHANDLERTYPE enmType;
650 /** Pointer to the RC callback function. */
651 RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
652#if HC_ARCH_BITS == 64
653 RTRCPTR padding;
654#endif
655 /** Pointer to the R3 callback function for invalidation. */
656 R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
657 /** Pointer to the R3 callback function. */
658 R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
659 /** Description / Name. For easing debugging. */
660 R3PTRTYPE(const char *) pszDesc;
661#ifdef VBOX_WITH_STATISTICS
662 /** Profiling of this handler. */
663 STAMPROFILE Stat;
664#endif
665 /** Array of cached physical addresses for the monitored ranged. */
666 PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
667} PGMVIRTHANDLER;
668/** Pointer to a virtual page access handler structure. */
669typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
670
671
672/** @name Page type predicates.
673 * @{ */
674#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
675#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
676#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
677#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
678#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
679/** @} */
680
681
682/**
683 * A Physical Guest Page tracking structure.
684 *
685 * The format of this structure is complicated because we have to fit a lot
686 * of information into as few bits as possible. The format is also subject
687 * to change (there is one coming up soon). Which means that for we'll be
688 * using PGM_PAGE_GET_*, PGM_PAGE_IS_ and PGM_PAGE_SET_* macros for *all*
689 * accesses to the structure.
690 */
691typedef struct PGMPAGE
692{
693 /** The physical address and the Page ID. */
694 RTHCPHYS HCPhysAndPageID;
695 /** Combination of:
696 * - [0-7]: u2HandlerPhysStateY - the physical handler state
697 * (PGM_PAGE_HNDL_PHYS_STATE_*).
698 * - [8-9]: u2HandlerVirtStateY - the virtual handler state
699 * (PGM_PAGE_HNDL_VIRT_STATE_*).
700 * - [10]: u1FTDirty - indicator of dirty page for fault tolerance tracking
701 * - [13-14]: u2PDEType - paging structure needed to map the page (PGM_PAGE_PDE_TYPE_*)
702 * - [15]: fWrittenToY - flag indicating that a write monitored page was
703 * written to when set.
704 * - [11-13]: 3 unused bits.
705 * @remarks Warning! All accesses to the bits are hardcoded.
706 *
707 * @todo Change this to a union with both bitfields, u8 and u accessors.
708 * That'll help deal with some of the hardcoded accesses.
709 *
710 * @todo Include uStateY and uTypeY as well so it becomes 32-bit. This
711 * will make it possible to turn some of the 16-bit accesses into
712 * 32-bit ones, which may be efficient (stalls).
713 */
714 RTUINT16U u16MiscY;
715 /** The page state.
716 * Only 3 bits are really needed for this. */
717 uint16_t uStateY : 3;
718 /** The page type (PGMPAGETYPE).
719 * Only 3 bits are really needed for this. */
720 uint16_t uTypeY : 3;
721 /** PTE index for usage tracking (page pool). */
722 uint16_t uPteIdx : 10;
723 /** Usage tracking (page pool). */
724 uint16_t u16TrackingY;
725 /** The number of read locks on this page. */
726 uint8_t cReadLocksY;
727 /** The number of write locks on this page. */
728 uint8_t cWriteLocksY;
729} PGMPAGE;
730AssertCompileSize(PGMPAGE, 16);
731/** Pointer to a physical guest page. */
732typedef PGMPAGE *PPGMPAGE;
733/** Pointer to a const physical guest page. */
734typedef const PGMPAGE *PCPGMPAGE;
735/** Pointer to a physical guest page pointer. */
736typedef PPGMPAGE *PPPGMPAGE;
737
738
739/**
740 * Clears the page structure.
741 * @param pPage Pointer to the physical guest page tracking structure.
742 */
743#define PGM_PAGE_CLEAR(pPage) \
744 do { \
745 (pPage)->HCPhysAndPageID = 0; \
746 (pPage)->uStateY = 0; \
747 (pPage)->uTypeY = 0; \
748 (pPage)->uPteIdx = 0; \
749 (pPage)->u16MiscY.u = 0; \
750 (pPage)->u16TrackingY = 0; \
751 (pPage)->cReadLocksY = 0; \
752 (pPage)->cWriteLocksY = 0; \
753 } while (0)
754
755/**
756 * Initializes the page structure.
757 * @param pPage Pointer to the physical guest page tracking structure.
758 */
759#define PGM_PAGE_INIT(pPage, _HCPhys, _idPage, _uType, _uState) \
760 do { \
761 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
762 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
763 (pPage)->HCPhysAndPageID = (SetHCPhysTmp << (28-12)) | ((_idPage) & UINT32_C(0x0fffffff)); \
764 (pPage)->uStateY = (_uState); \
765 (pPage)->uTypeY = (_uType); \
766 (pPage)->uPteIdx = 0; \
767 (pPage)->u16MiscY.u = 0; \
768 (pPage)->u16TrackingY = 0; \
769 (pPage)->cReadLocksY = 0; \
770 (pPage)->cWriteLocksY = 0; \
771 } while (0)
772
773/**
774 * Initializes the page structure of a ZERO page.
775 * @param pPage Pointer to the physical guest page tracking structure.
776 * @param pVM The VM handle (for getting the zero page address).
777 * @param uType The page type (PGMPAGETYPE).
778 */
779#define PGM_PAGE_INIT_ZERO(pPage, pVM, uType) \
780 PGM_PAGE_INIT((pPage), (pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (uType), PGM_PAGE_STATE_ZERO)
781
782
783/** @name The Page state, PGMPAGE::uStateY.
784 * @{ */
785/** The zero page.
786 * This is a per-VM page that's never ever mapped writable. */
787#define PGM_PAGE_STATE_ZERO 0
788/** A allocated page.
789 * This is a per-VM page allocated from the page pool (or wherever
790 * we get MMIO2 pages from if the type is MMIO2).
791 */
792#define PGM_PAGE_STATE_ALLOCATED 1
793/** A allocated page that's being monitored for writes.
794 * The shadow page table mappings are read-only. When a write occurs, the
795 * fWrittenTo member is set, the page remapped as read-write and the state
796 * moved back to allocated. */
797#define PGM_PAGE_STATE_WRITE_MONITORED 2
798/** The page is shared, aka. copy-on-write.
799 * This is a page that's shared with other VMs. */
800#define PGM_PAGE_STATE_SHARED 3
801/** The page is ballooned, so no longer available for this VM. */
802#define PGM_PAGE_STATE_BALLOONED 4
803/** @} */
804
805
806/**
807 * Gets the page state.
808 * @returns page state (PGM_PAGE_STATE_*).
809 * @param pPage Pointer to the physical guest page tracking structure.
810 */
811#define PGM_PAGE_GET_STATE(pPage) ( (pPage)->uStateY )
812
813/**
814 * Sets the page state.
815 * @param pPage Pointer to the physical guest page tracking structure.
816 * @param _uState The new page state.
817 */
818#define PGM_PAGE_SET_STATE(pPage, _uState) do { (pPage)->uStateY = (_uState); } while (0)
819
820
821/**
822 * Gets the host physical address of the guest page.
823 * @returns host physical address (RTHCPHYS).
824 * @param pPage Pointer to the physical guest page tracking structure.
825 */
826#define PGM_PAGE_GET_HCPHYS(pPage) ( ((pPage)->HCPhysAndPageID >> 28) << 12 )
827
828/**
829 * Sets the host physical address of the guest page.
830 * @param pPage Pointer to the physical guest page tracking structure.
831 * @param _HCPhys The new host physical address.
832 */
833#define PGM_PAGE_SET_HCPHYS(pPage, _HCPhys) \
834 do { \
835 RTHCPHYS SetHCPhysTmp = (_HCPhys); \
836 AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
837 (pPage)->HCPhysAndPageID = ((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) \
838 | (SetHCPhysTmp << (28-12)); \
839 } while (0)
840
841/**
842 * Get the Page ID.
843 * @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
844 * @param pPage Pointer to the physical guest page tracking structure.
845 */
846#define PGM_PAGE_GET_PAGEID(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & UINT32_C(0x0fffffff)) )
847
848/**
849 * Sets the Page ID.
850 * @param pPage Pointer to the physical guest page tracking structure.
851 */
852#define PGM_PAGE_SET_PAGEID(pPage, _idPage) \
853 do { \
854 (pPage)->HCPhysAndPageID = (((pPage)->HCPhysAndPageID) & UINT64_C(0xfffffffff0000000)) \
855 | ((_idPage) & UINT32_C(0x0fffffff)); \
856 } while (0)
857
858/**
859 * Get the Chunk ID.
860 * @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
861 * @param pPage Pointer to the physical guest page tracking structure.
862 */
863#define PGM_PAGE_GET_CHUNKID(pPage) ( PGM_PAGE_GET_PAGEID(pPage) >> GMM_CHUNKID_SHIFT )
864
865/**
866 * Get the index of the page within the allocation chunk.
867 * @returns The page index.
868 * @param pPage Pointer to the physical guest page tracking structure.
869 */
870#define PGM_PAGE_GET_PAGE_IN_CHUNK(pPage) ( (uint32_t)((pPage)->HCPhysAndPageID & GMM_PAGEID_IDX_MASK) )
871
872/**
873 * Gets the page type.
874 * @returns The page type.
875 * @param pPage Pointer to the physical guest page tracking structure.
876 */
877#define PGM_PAGE_GET_TYPE(pPage) (pPage)->uTypeY
878
879/**
880 * Sets the page type.
881 * @param pPage Pointer to the physical guest page tracking structure.
882 * @param _enmType The new page type (PGMPAGETYPE).
883 */
884#define PGM_PAGE_SET_TYPE(pPage, _enmType) do { (pPage)->uTypeY = (_enmType); } while (0)
885
886/**
887 * Gets the page table index
888 * @returns The page table index.
889 * @param pPage Pointer to the physical guest page tracking structure.
890 */
891#define PGM_PAGE_GET_PTE_INDEX(pPage) (pPage)->uPteIdx
892
893/**
894 * Sets the page table index
895 * @param pPage Pointer to the physical guest page tracking structure.
896 * @param iPte New page table index.
897 */
898#define PGM_PAGE_SET_PTE_INDEX(pPage, _iPte) do { (pPage)->uPteIdx = (_iPte); } while (0)
899
900/**
901 * Checks if the page is marked for MMIO.
902 * @returns true/false.
903 * @param pPage Pointer to the physical guest page tracking structure.
904 */
905#define PGM_PAGE_IS_MMIO(pPage) ( (pPage)->uTypeY == PGMPAGETYPE_MMIO )
906
907/**
908 * Checks if the page is backed by the ZERO page.
909 * @returns true/false.
910 * @param pPage Pointer to the physical guest page tracking structure.
911 */
912#define PGM_PAGE_IS_ZERO(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ZERO )
913
914/**
915 * Checks if the page is backed by a SHARED page.
916 * @returns true/false.
917 * @param pPage Pointer to the physical guest page tracking structure.
918 */
919#define PGM_PAGE_IS_SHARED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_SHARED )
920
921/**
922 * Checks if the page is ballooned.
923 * @returns true/false.
924 * @param pPage Pointer to the physical guest page tracking structure.
925 */
926#define PGM_PAGE_IS_BALLOONED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_BALLOONED )
927
928/**
929 * Checks if the page is allocated.
930 * @returns true/false.
931 * @param pPage Pointer to the physical guest page tracking structure.
932 */
933#define PGM_PAGE_IS_ALLOCATED(pPage) ( (pPage)->uStateY == PGM_PAGE_STATE_ALLOCATED )
934
935/**
936 * Marks the page as written to (for GMM change monitoring).
937 * @param pPage Pointer to the physical guest page tracking structure.
938 */
939#define PGM_PAGE_SET_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x80); } while (0)
940
941/**
942 * Clears the written-to indicator.
943 * @param pPage Pointer to the physical guest page tracking structure.
944 */
945#define PGM_PAGE_CLEAR_WRITTEN_TO(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0x7f); } while (0)
946
947/**
948 * Checks if the page was marked as written-to.
949 * @returns true/false.
950 * @param pPage Pointer to the physical guest page tracking structure.
951 */
952#define PGM_PAGE_IS_WRITTEN_TO(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x80)) )
953
954/**
955 * Marks the page as dirty for FTM
956 * @param pPage Pointer to the physical guest page tracking structure.
957 */
958#define PGM_PAGE_SET_FT_DIRTY(pPage) do { (pPage)->u16MiscY.au8[1] |= UINT8_C(0x04); } while (0)
959
960/**
961 * Clears the FTM dirty indicator
962 * @param pPage Pointer to the physical guest page tracking structure.
963 */
964#define PGM_PAGE_CLEAR_FT_DIRTY(pPage) do { (pPage)->u16MiscY.au8[1] &= UINT8_C(0xfb); } while (0)
965
966/**
967 * Checks if the page was marked as dirty for FTM
968 * @returns true/false.
969 * @param pPage Pointer to the physical guest page tracking structure.
970 */
971#define PGM_PAGE_IS_FT_DIRTY(pPage) ( !!((pPage)->u16MiscY.au8[1] & UINT8_C(0x04)) )
972
973
974/** @name PT usage values (PGMPAGE::u2PDEType).
975 *
976 * @{ */
977/** Either as a PT or PDE. */
978#define PGM_PAGE_PDE_TYPE_DONTCARE 0
979/** Must use a page table to map the range. */
980#define PGM_PAGE_PDE_TYPE_PT 1
981/** Can use a page directory entry to map the continuous range. */
982#define PGM_PAGE_PDE_TYPE_PDE 2
983/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
984#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
985/** @} */
986
987/**
988 * Set the PDE type of the page
989 * @param pPage Pointer to the physical guest page tracking structure.
990 * @param uType PGM_PAGE_PDE_TYPE_*
991 */
992#define PGM_PAGE_SET_PDE_TYPE(pPage, uType) \
993 do { \
994 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0x9f)) \
995 | (((uType) & UINT8_C(0x03)) << 5); \
996 } while (0)
997
998/**
999 * Checks if the page was marked being part of a large page
1000 * @returns true/false.
1001 * @param pPage Pointer to the physical guest page tracking structure.
1002 */
1003#define PGM_PAGE_GET_PDE_TYPE(pPage) ( ((pPage)->u16MiscY.au8[1] & UINT8_C(0x60)) >> 5)
1004
1005/** Enabled optimized access handler tests.
1006 * These optimizations makes ASSUMPTIONS about the state values and the u16MiscY
1007 * layout. When enabled, the compiler should normally generate more compact
1008 * code.
1009 */
1010#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1011
1012/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1013 *
1014 * @remarks The values are assigned in order of priority, so we can calculate
1015 * the correct state for a page with different handlers installed.
1016 * @{ */
1017/** No handler installed. */
1018#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1019/** Monitoring is temporarily disabled. */
1020#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1021/** Write access is monitored. */
1022#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1023/** All access is monitored. */
1024#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1025/** @} */
1026
1027/**
1028 * Gets the physical access handler state of a page.
1029 * @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1030 * @param pPage Pointer to the physical guest page tracking structure.
1031 */
1032#define PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) \
1033 ( (pPage)->u16MiscY.au8[0] )
1034
1035/**
1036 * Sets the physical access handler state of a page.
1037 * @param pPage Pointer to the physical guest page tracking structure.
1038 * @param _uState The new state value.
1039 */
1040#define PGM_PAGE_SET_HNDL_PHYS_STATE(pPage, _uState) \
1041 do { (pPage)->u16MiscY.au8[0] = (_uState); } while (0)
1042
1043/**
1044 * Checks if the page has any physical access handlers, including temporarily disabled ones.
1045 * @returns true/false
1046 * @param pPage Pointer to the physical guest page tracking structure.
1047 */
1048#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(pPage) \
1049 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1050
1051/**
1052 * Checks if the page has any active physical access handlers.
1053 * @returns true/false
1054 * @param pPage Pointer to the physical guest page tracking structure.
1055 */
1056#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(pPage) \
1057 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1058
1059
1060/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1061 *
1062 * @remarks The values are assigned in order of priority, so we can calculate
1063 * the correct state for a page with different handlers installed.
1064 * @{ */
1065/** No handler installed. */
1066#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1067/* 1 is reserved so the lineup is identical with the physical ones. */
1068/** Write access is monitored. */
1069#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1070/** All access is monitored. */
1071#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1072/** @} */
1073
1074/**
1075 * Gets the virtual access handler state of a page.
1076 * @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1077 * @param pPage Pointer to the physical guest page tracking structure.
1078 */
1079#define PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) ((uint8_t)( (pPage)->u16MiscY.au8[1] & UINT8_C(0x03) ))
1080
1081/**
1082 * Sets the virtual access handler state of a page.
1083 * @param pPage Pointer to the physical guest page tracking structure.
1084 * @param _uState The new state value.
1085 */
1086#define PGM_PAGE_SET_HNDL_VIRT_STATE(pPage, _uState) \
1087 do { \
1088 (pPage)->u16MiscY.au8[1] = ((pPage)->u16MiscY.au8[1] & UINT8_C(0xfc)) \
1089 | ((_uState) & UINT8_C(0x03)); \
1090 } while (0)
1091
1092/**
1093 * Checks if the page has any virtual access handlers.
1094 * @returns true/false
1095 * @param pPage Pointer to the physical guest page tracking structure.
1096 */
1097#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage) \
1098 ( PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1099
1100/**
1101 * Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1102 * virtual handlers.
1103 * @returns true/false
1104 * @param pPage Pointer to the physical guest page tracking structure.
1105 */
1106#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(pPage) \
1107 PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(pPage)
1108
1109
1110/**
1111 * Checks if the page has any access handlers, including temporarily disabled ones.
1112 * @returns true/false
1113 * @param pPage Pointer to the physical guest page tracking structure.
1114 */
1115#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1116# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1117 ( ((pPage)->u16MiscY.u & UINT16_C(0x0303)) != 0 )
1118#else
1119# define PGM_PAGE_HAS_ANY_HANDLERS(pPage) \
1120 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1121 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1122#endif
1123
1124/**
1125 * Checks if the page has any active access handlers.
1126 * @returns true/false
1127 * @param pPage Pointer to the physical guest page tracking structure.
1128 */
1129#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1130# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1131 ( ((pPage)->u16MiscY.u & UINT16_C(0x0202)) != 0 )
1132#else
1133# define PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage) \
1134 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1135 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1136#endif
1137
1138/**
1139 * Checks if the page has any active access handlers catching all accesses.
1140 * @returns true/false
1141 * @param pPage Pointer to the physical guest page tracking structure.
1142 */
1143#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1144# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1145 ( ( ((pPage)->u16MiscY.au8[0] | (pPage)->u16MiscY.au8[1]) & UINT8_C(0x3) ) \
1146 == PGM_PAGE_HNDL_PHYS_STATE_ALL )
1147#else
1148# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage) \
1149 ( PGM_PAGE_GET_HNDL_PHYS_STATE(pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1150 || PGM_PAGE_GET_HNDL_VIRT_STATE(pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1151#endif
1152
1153
1154/** @def PGM_PAGE_GET_TRACKING
1155 * Gets the packed shadow page pool tracking data associated with a guest page.
1156 * @returns uint16_t containing the data.
1157 * @param pPage Pointer to the physical guest page tracking structure.
1158 */
1159#define PGM_PAGE_GET_TRACKING(pPage) ( (pPage)->u16TrackingY )
1160
1161/** @def PGM_PAGE_SET_TRACKING
1162 * Sets the packed shadow page pool tracking data associated with a guest page.
1163 * @param pPage Pointer to the physical guest page tracking structure.
1164 * @param u16TrackingData The tracking data to store.
1165 */
1166#define PGM_PAGE_SET_TRACKING(pPage, u16TrackingData) \
1167 do { (pPage)->u16TrackingY = (u16TrackingData); } while (0)
1168
1169/** @def PGM_PAGE_GET_TD_CREFS
1170 * Gets the @a cRefs tracking data member.
1171 * @returns cRefs.
1172 * @param pPage Pointer to the physical guest page tracking structure.
1173 */
1174#define PGM_PAGE_GET_TD_CREFS(pPage) \
1175 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1176
1177/** @def PGM_PAGE_GET_TD_IDX
1178 * Gets the @a idx tracking data member.
1179 * @returns idx.
1180 * @param pPage Pointer to the physical guest page tracking structure.
1181 */
1182#define PGM_PAGE_GET_TD_IDX(pPage) \
1183 ((PGM_PAGE_GET_TRACKING(pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1184
1185
1186/** Max number of locks on a page. */
1187#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1188
1189/** Get the read lock count.
1190 * @returns count.
1191 * @param pPage Pointer to the physical guest page tracking structure.
1192 */
1193#define PGM_PAGE_GET_READ_LOCKS(pPage) ( (pPage)->cReadLocksY )
1194
1195/** Get the write lock count.
1196 * @returns count.
1197 * @param pPage Pointer to the physical guest page tracking structure.
1198 */
1199#define PGM_PAGE_GET_WRITE_LOCKS(pPage) ( (pPage)->cWriteLocksY )
1200
1201/** Decrement the read lock counter.
1202 * @param pPage Pointer to the physical guest page tracking structure.
1203 */
1204#define PGM_PAGE_DEC_READ_LOCKS(pPage) do { --(pPage)->cReadLocksY; } while (0)
1205
1206/** Decrement the write lock counter.
1207 * @param pPage Pointer to the physical guest page tracking structure.
1208 */
1209#define PGM_PAGE_DEC_WRITE_LOCKS(pPage) do { --(pPage)->cWriteLocksY; } while (0)
1210
1211/** Increment the read lock counter.
1212 * @param pPage Pointer to the physical guest page tracking structure.
1213 */
1214#define PGM_PAGE_INC_READ_LOCKS(pPage) do { ++(pPage)->cReadLocksY; } while (0)
1215
1216/** Increment the write lock counter.
1217 * @param pPage Pointer to the physical guest page tracking structure.
1218 */
1219#define PGM_PAGE_INC_WRITE_LOCKS(pPage) do { ++(pPage)->cWriteLocksY; } while (0)
1220
1221
1222#if 0
1223/** Enables sanity checking of write monitoring using CRC-32. */
1224# define PGMLIVESAVERAMPAGE_WITH_CRC32
1225#endif
1226
1227/**
1228 * Per page live save tracking data.
1229 */
1230typedef struct PGMLIVESAVERAMPAGE
1231{
1232 /** Number of times it has been dirtied. */
1233 uint32_t cDirtied : 24;
1234 /** Whether it is currently dirty. */
1235 uint32_t fDirty : 1;
1236 /** Ignore the page.
1237 * This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1238 * deal with these after pausing the VM and DevPCI have said it bit about
1239 * remappings. */
1240 uint32_t fIgnore : 1;
1241 /** Was a ZERO page last time around. */
1242 uint32_t fZero : 1;
1243 /** Was a SHARED page last time around. */
1244 uint32_t fShared : 1;
1245 /** Whether the page is/was write monitored in a previous pass. */
1246 uint32_t fWriteMonitored : 1;
1247 /** Whether the page is/was write monitored earlier in this pass. */
1248 uint32_t fWriteMonitoredJustNow : 1;
1249 /** Bits reserved for future use. */
1250 uint32_t u2Reserved : 2;
1251#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1252 /** CRC-32 for the page. This is for internal consistency checks. */
1253 uint32_t u32Crc;
1254#endif
1255} PGMLIVESAVERAMPAGE;
1256#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1257AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1258#else
1259AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1260#endif
1261/** Pointer to the per page live save tracking data. */
1262typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1263
1264/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1265#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1266
1267
1268/**
1269 * Ram range for GC Phys to HC Phys conversion.
1270 *
1271 * Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1272 * conversions too, but we'll let MM handle that for now.
1273 *
1274 * This structure is used by linked lists in both GC and HC.
1275 */
1276typedef struct PGMRAMRANGE
1277{
1278 /** Start of the range. Page aligned. */
1279 RTGCPHYS GCPhys;
1280 /** Size of the range. (Page aligned of course). */
1281 RTGCPHYS cb;
1282 /** Pointer to the next RAM range - for R3. */
1283 R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1284 /** Pointer to the next RAM range - for R0. */
1285 R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1286 /** Pointer to the next RAM range - for RC. */
1287 RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1288 /** PGM_RAM_RANGE_FLAGS_* flags. */
1289 uint32_t fFlags;
1290 /** Last address in the range (inclusive). Page aligned (-1). */
1291 RTGCPHYS GCPhysLast;
1292 /** Start of the HC mapping of the range. This is only used for MMIO2. */
1293 R3PTRTYPE(void *) pvR3;
1294 /** Live save per page tracking data. */
1295 R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1296 /** The range description. */
1297 R3PTRTYPE(const char *) pszDesc;
1298 /** Pointer to self - R0 pointer. */
1299 R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1300 /** Pointer to self - RC pointer. */
1301 RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1302 /** Padding to make aPage aligned on sizeof(PGMPAGE). */
1303 uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 1 : 3];
1304 /** Array of physical guest page tracking structures. */
1305 PGMPAGE aPages[1];
1306} PGMRAMRANGE;
1307/** Pointer to Ram range for GC Phys to HC Phys conversion. */
1308typedef PGMRAMRANGE *PPGMRAMRANGE;
1309
1310/** @name PGMRAMRANGE::fFlags
1311 * @{ */
1312/** The RAM range is floating around as an independent guest mapping. */
1313#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1314/** Ad hoc RAM range for an ROM mapping. */
1315#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1316/** Ad hoc RAM range for an MMIO mapping. */
1317#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1318/** Ad hoc RAM range for an MMIO2 mapping. */
1319#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1320/** @} */
1321
1322/** Tests if a RAM range is an ad hoc one or not.
1323 * @returns true/false.
1324 * @param pRam The RAM range.
1325 */
1326#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1327 (!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO | PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1328
1329
1330/**
1331 * Per page tracking structure for ROM image.
1332 *
1333 * A ROM image may have a shadow page, in which case we may have two pages
1334 * backing it. This structure contains the PGMPAGE for both while
1335 * PGMRAMRANGE have a copy of the active one. It is important that these
1336 * aren't out of sync in any regard other than page pool tracking data.
1337 */
1338typedef struct PGMROMPAGE
1339{
1340 /** The page structure for the virgin ROM page. */
1341 PGMPAGE Virgin;
1342 /** The page structure for the shadow RAM page. */
1343 PGMPAGE Shadow;
1344 /** The current protection setting. */
1345 PGMROMPROT enmProt;
1346 /** Live save status information. Makes use of unused alignment space. */
1347 struct
1348 {
1349 /** The previous protection value. */
1350 uint8_t u8Prot;
1351 /** Written to flag set by the handler. */
1352 bool fWrittenTo;
1353 /** Whether the shadow page is dirty or not. */
1354 bool fDirty;
1355 /** Whether it was dirtied in the recently. */
1356 bool fDirtiedRecently;
1357 } LiveSave;
1358} PGMROMPAGE;
1359AssertCompileSizeAlignment(PGMROMPAGE, 8);
1360/** Pointer to a ROM page tracking structure. */
1361typedef PGMROMPAGE *PPGMROMPAGE;
1362
1363
1364/**
1365 * A registered ROM image.
1366 *
1367 * This is needed to keep track of ROM image since they generally intrude
1368 * into a PGMRAMRANGE. It also keeps track of additional info like the
1369 * two page sets (read-only virgin and read-write shadow), the current
1370 * state of each page.
1371 *
1372 * Because access handlers cannot easily be executed in a different
1373 * context, the ROM ranges needs to be accessible and in all contexts.
1374 */
1375typedef struct PGMROMRANGE
1376{
1377 /** Pointer to the next range - R3. */
1378 R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1379 /** Pointer to the next range - R0. */
1380 R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1381 /** Pointer to the next range - RC. */
1382 RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1383 /** Pointer alignment */
1384 RTRCPTR RCPtrAlignment;
1385 /** Address of the range. */
1386 RTGCPHYS GCPhys;
1387 /** Address of the last byte in the range. */
1388 RTGCPHYS GCPhysLast;
1389 /** Size of the range. */
1390 RTGCPHYS cb;
1391 /** The flags (PGMPHYS_ROM_FLAGS_*). */
1392 uint32_t fFlags;
1393 /** The saved state range ID. */
1394 uint8_t idSavedState;
1395 /** Alignment padding. */
1396 uint8_t au8Alignment[3];
1397 /** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1398 uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1399 /** The size bits pvOriginal points to. */
1400 uint32_t cbOriginal;
1401 /** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1402 * This is used for strictness checks. */
1403 R3PTRTYPE(const void *) pvOriginal;
1404 /** The ROM description. */
1405 R3PTRTYPE(const char *) pszDesc;
1406 /** The per page tracking structures. */
1407 PGMROMPAGE aPages[1];
1408} PGMROMRANGE;
1409/** Pointer to a ROM range. */
1410typedef PGMROMRANGE *PPGMROMRANGE;
1411
1412
1413/**
1414 * Live save per page data for an MMIO2 page.
1415 *
1416 * Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1417 * of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1418 * CRC-32 for detecting changes as well as special handling of zero pages. This
1419 * is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1420 * for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1421 * because of speed (2.5x and 6x slower).)
1422 *
1423 * @todo Implement dirty MMIO2 page reporting that can be enabled during live
1424 * save but normally is disabled. Since we can write monitor guest
1425 * accesses on our own, we only need this for host accesses. Shouldn't be
1426 * too difficult for DevVGA, VMMDev might be doable, the planned
1427 * networking fun will be fun since it involves ring-0.
1428 */
1429typedef struct PGMLIVESAVEMMIO2PAGE
1430{
1431 /** Set if the page is considered dirty. */
1432 bool fDirty;
1433 /** The number of scans this page has remained unchanged for.
1434 * Only updated for dirty pages. */
1435 uint8_t cUnchangedScans;
1436 /** Whether this page was zero at the last scan. */
1437 bool fZero;
1438 /** Alignment padding. */
1439 bool fReserved;
1440 /** CRC-32 for the first half of the page.
1441 * This is used together with u32CrcH2 to quickly detect changes in the page
1442 * during the non-final passes. */
1443 uint32_t u32CrcH1;
1444 /** CRC-32 for the second half of the page. */
1445 uint32_t u32CrcH2;
1446 /** SHA-1 for the saved page.
1447 * This is used in the final pass to skip pages without changes. */
1448 uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1449} PGMLIVESAVEMMIO2PAGE;
1450/** Pointer to a live save status data for an MMIO2 page. */
1451typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1452
1453/**
1454 * A registered MMIO2 (= Device RAM) range.
1455 *
1456 * There are a few reason why we need to keep track of these
1457 * registrations. One of them is the deregistration & cleanup stuff,
1458 * while another is that the PGMRAMRANGE associated with such a region may
1459 * have to be removed from the ram range list.
1460 *
1461 * Overlapping with a RAM range has to be 100% or none at all. The pages
1462 * in the existing RAM range must not be ROM nor MMIO. A guru meditation
1463 * will be raised if a partial overlap or an overlap of ROM pages is
1464 * encountered. On an overlap we will free all the existing RAM pages and
1465 * put in the ram range pages instead.
1466 */
1467typedef struct PGMMMIO2RANGE
1468{
1469 /** The owner of the range. (a device) */
1470 PPDMDEVINSR3 pDevInsR3;
1471 /** Pointer to the ring-3 mapping of the allocation. */
1472 RTR3PTR pvR3;
1473 /** Pointer to the next range - R3. */
1474 R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1475 /** Whether it's mapped or not. */
1476 bool fMapped;
1477 /** Whether it's overlapping or not. */
1478 bool fOverlapping;
1479 /** The PCI region number.
1480 * @remarks This ASSUMES that nobody will ever really need to have multiple
1481 * PCI devices with matching MMIO region numbers on a single device. */
1482 uint8_t iRegion;
1483 /** The saved state range ID. */
1484 uint8_t idSavedState;
1485 /** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1486 uint8_t abAlignemnt[HC_ARCH_BITS == 32 ? 12 : 12];
1487 /** Live save per page tracking data. */
1488 R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1489 /** The associated RAM range. */
1490 PGMRAMRANGE RamRange;
1491} PGMMMIO2RANGE;
1492/** Pointer to a MMIO2 range. */
1493typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1494
1495
1496
1497
1498/**
1499 * PGMPhysRead/Write cache entry
1500 */
1501typedef struct PGMPHYSCACHEENTRY
1502{
1503 /** R3 pointer to physical page. */
1504 R3PTRTYPE(uint8_t *) pbR3;
1505 /** GC Physical address for cache entry */
1506 RTGCPHYS GCPhys;
1507#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1508 RTGCPHYS u32Padding0; /**< alignment padding. */
1509#endif
1510} PGMPHYSCACHEENTRY;
1511
1512/**
1513 * PGMPhysRead/Write cache to reduce REM memory access overhead
1514 */
1515typedef struct PGMPHYSCACHE
1516{
1517 /** Bitmap of valid cache entries */
1518 uint64_t aEntries;
1519 /** Cache entries */
1520 PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1521} PGMPHYSCACHE;
1522
1523
1524/** Pointer to an allocation chunk ring-3 mapping. */
1525typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1526/** Pointer to an allocation chunk ring-3 mapping pointer. */
1527typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1528
1529/**
1530 * Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1531 *
1532 * The primary tree (Core) uses the chunk id as key.
1533 */
1534typedef struct PGMCHUNKR3MAP
1535{
1536 /** The key is the chunk id. */
1537 AVLU32NODECORE Core;
1538 /** The current age thingy. */
1539 uint32_t iAge;
1540 /** The current reference count. */
1541 uint32_t volatile cRefs;
1542 /** The current permanent reference count. */
1543 uint32_t volatile cPermRefs;
1544 /** The mapping address. */
1545 void *pv;
1546} PGMCHUNKR3MAP;
1547
1548/**
1549 * Allocation chunk ring-3 mapping TLB entry.
1550 */
1551typedef struct PGMCHUNKR3MAPTLBE
1552{
1553 /** The chunk id. */
1554 uint32_t volatile idChunk;
1555#if HC_ARCH_BITS == 64
1556 uint32_t u32Padding; /**< alignment padding. */
1557#endif
1558 /** The chunk map. */
1559#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1560 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1561#else
1562 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1563#endif
1564} PGMCHUNKR3MAPTLBE;
1565/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1566typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1567
1568/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1569 * @remark Must be a power of two value. */
1570#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1571
1572/**
1573 * Allocation chunk ring-3 mapping TLB.
1574 *
1575 * @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1576 * At first glance this might look kinda odd since AVL trees are
1577 * supposed to give the most optimal lookup times of all trees
1578 * due to their balancing. However, take a tree with 1023 nodes
1579 * in it, that's 10 levels, meaning that most searches has to go
1580 * down 9 levels before they find what they want. This isn't fast
1581 * compared to a TLB hit. There is the factor of cache misses,
1582 * and of course the problem with trees and branch prediction.
1583 * This is why we use TLBs in front of most of the trees.
1584 *
1585 * @todo Generalize this TLB + AVL stuff, shouldn't be all that
1586 * difficult when we switch to the new inlined AVL trees (from kStuff).
1587 */
1588typedef struct PGMCHUNKR3MAPTLB
1589{
1590 /** The TLB entries. */
1591 PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1592} PGMCHUNKR3MAPTLB;
1593
1594/**
1595 * Calculates the index of a guest page in the Ring-3 Chunk TLB.
1596 * @returns Chunk TLB index.
1597 * @param idChunk The Chunk ID.
1598 */
1599#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1600
1601
1602/**
1603 * Ring-3 guest page mapping TLB entry.
1604 * @remarks used in ring-0 as well at the moment.
1605 */
1606typedef struct PGMPAGER3MAPTLBE
1607{
1608 /** Address of the page. */
1609 RTGCPHYS volatile GCPhys;
1610 /** The guest page. */
1611#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1612 R3PTRTYPE(PPGMPAGE) volatile pPage;
1613#else
1614 R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1615#endif
1616 /** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1617#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1618 R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1619#else
1620 R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1621#endif
1622 /** The address */
1623#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1624 R3PTRTYPE(void *) volatile pv;
1625#else
1626 R3R0PTRTYPE(void *) volatile pv;
1627#endif
1628#if HC_ARCH_BITS == 32
1629 uint32_t u32Padding; /**< alignment padding. */
1630#endif
1631} PGMPAGER3MAPTLBE;
1632/** Pointer to an entry in the HC physical TLB. */
1633typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1634
1635
1636/** The number of entries in the ring-3 guest page mapping TLB.
1637 * @remarks The value must be a power of two. */
1638#define PGM_PAGER3MAPTLB_ENTRIES 256
1639
1640/**
1641 * Ring-3 guest page mapping TLB.
1642 * @remarks used in ring-0 as well at the moment.
1643 */
1644typedef struct PGMPAGER3MAPTLB
1645{
1646 /** The TLB entries. */
1647 PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1648} PGMPAGER3MAPTLB;
1649/** Pointer to the ring-3 guest page mapping TLB. */
1650typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1651
1652/**
1653 * Calculates the index of the TLB entry for the specified guest page.
1654 * @returns Physical TLB index.
1655 * @param GCPhys The guest physical address.
1656 */
1657#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1658
1659
1660/**
1661 * Raw-mode context dynamic mapping cache entry.
1662 *
1663 * Because of raw-mode context being reloctable and all relocations are applied
1664 * in ring-3, this has to be defined here and be RC specific.
1665 *
1666 * @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1667 */
1668typedef struct PGMRCDYNMAPENTRY
1669{
1670 /** The physical address of the currently mapped page.
1671 * This is duplicate for three reasons: cache locality, cache policy of the PT
1672 * mappings and sanity checks. */
1673 RTHCPHYS HCPhys;
1674 /** Pointer to the page. */
1675 RTRCPTR pvPage;
1676 /** The number of references. */
1677 int32_t volatile cRefs;
1678 /** PTE pointer union. */
1679 union PGMRCDYNMAPENTRY_PPTE
1680 {
1681 /** PTE pointer, 32-bit legacy version. */
1682 RCPTRTYPE(PX86PTE) pLegacy;
1683 /** PTE pointer, PAE version. */
1684 RCPTRTYPE(PX86PTEPAE) pPae;
1685 /** PTE pointer, the void version. */
1686 RTRCPTR pv;
1687 } uPte;
1688 /** Alignment padding. */
1689 RTRCPTR RCPtrAlignment;
1690} PGMRCDYNMAPENTRY;
1691/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1692typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1693
1694
1695/**
1696 * Dynamic mapping cache for the raw-mode context.
1697 *
1698 * This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1699 * paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1700 * so that we can perform relocations from PGMR3Relocate. This has the
1701 * consequence that we must have separate ring-0 and raw-mode context versions
1702 * of this struct even if they share the basic elements.
1703 *
1704 * @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1705 */
1706typedef struct PGMRCDYNMAP
1707{
1708 /** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1709 uint32_t u32Magic;
1710 /** Array for tracking and managing the pages. */
1711 RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1712 /** The cache size given as a number of pages. */
1713 uint32_t cPages;
1714 /** Whether it's 32-bit legacy or PAE/AMD64 paging mode. */
1715 bool fLegacyMode;
1716 /** The current load.
1717 * This does not include guard pages. */
1718 uint32_t cLoad;
1719 /** The max load ever.
1720 * This is maintained to get trigger adding of more mapping space. */
1721 uint32_t cMaxLoad;
1722 /** The number of guard pages. */
1723 uint32_t cGuardPages;
1724 /** The number of users (protected by hInitLock). */
1725 uint32_t cUsers;
1726} PGMRCDYNMAP;
1727/** Pointer to the dynamic cache for the raw-mode context. */
1728typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1729
1730
1731/**
1732 * Mapping cache usage set entry.
1733 *
1734 * @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1735 * the dynamic ring-0 and (to some extent) raw-mode context mapping
1736 * cache. If it's extended to include ring-3, well, then something
1737 * will have be changed here...
1738 */
1739typedef struct PGMMAPSETENTRY
1740{
1741 /** Pointer to the page. */
1742#ifndef IN_RC
1743 RTR0PTR pvPage;
1744#else
1745 RTRCPTR pvPage;
1746# if HC_ARCH_BITS == 64
1747 uint32_t u32Alignment2;
1748# endif
1749#endif
1750 /** The mapping cache index. */
1751 uint16_t iPage;
1752 /** The number of references.
1753 * The max is UINT16_MAX - 1. */
1754 uint16_t cRefs;
1755 /** The number inlined references.
1756 * The max is UINT16_MAX - 1. */
1757 uint16_t cInlinedRefs;
1758 /** Unreferences. */
1759 uint16_t cUnrefs;
1760
1761#if HC_ARCH_BITS == 32
1762 uint32_t u32Alignment1;
1763#endif
1764 /** The physical address for this entry. */
1765 RTHCPHYS HCPhys;
1766} PGMMAPSETENTRY;
1767AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1768AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1769/** Pointer to a mapping cache usage set entry. */
1770typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1771
1772/**
1773 * Mapping cache usage set.
1774 *
1775 * This is used in ring-0 and the raw-mode context to track dynamic mappings
1776 * done during exits / traps. The set is
1777 */
1778typedef struct PGMMAPSET
1779{
1780 /** The number of occupied entries.
1781 * This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1782 * dynamic mappings. */
1783 uint32_t cEntries;
1784 /** The start of the current subset.
1785 * This is UINT32_MAX if no subset is currently open. */
1786 uint32_t iSubset;
1787 /** The index of the current CPU, only valid if the set is open. */
1788 int32_t iCpu;
1789 uint32_t alignment;
1790 /** The entries. */
1791 PGMMAPSETENTRY aEntries[64];
1792 /** HCPhys -> iEntry fast lookup table.
1793 * Use PGMMAPSET_HASH for hashing.
1794 * The entries may or may not be valid, check against cEntries. */
1795 uint8_t aiHashTable[128];
1796} PGMMAPSET;
1797AssertCompileSizeAlignment(PGMMAPSET, 8);
1798/** Pointer to the mapping cache set. */
1799typedef PGMMAPSET *PPGMMAPSET;
1800
1801/** PGMMAPSET::cEntries value for a closed set. */
1802#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1803
1804/** Hash function for aiHashTable. */
1805#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1806
1807
1808/** @name Context neutral page mapper TLB.
1809 *
1810 * Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
1811 * code is writting in a kind of context neutral way. Time will show whether
1812 * this actually makes sense or not...
1813 *
1814 * @todo this needs to be reconsidered and dropped/redone since the ring-0
1815 * context ends up using a global mapping cache on some platforms
1816 * (darwin).
1817 *
1818 * @{ */
1819/** @typedef PPGMPAGEMAPTLB
1820 * The page mapper TLB pointer type for the current context. */
1821/** @typedef PPGMPAGEMAPTLB
1822 * The page mapper TLB entry pointer type for the current context. */
1823/** @typedef PPGMPAGEMAPTLB
1824 * The page mapper TLB entry pointer pointer type for the current context. */
1825/** @def PGM_PAGEMAPTLB_ENTRIES
1826 * The number of TLB entries in the page mapper TLB for the current context. */
1827/** @def PGM_PAGEMAPTLB_IDX
1828 * Calculate the TLB index for a guest physical address.
1829 * @returns The TLB index.
1830 * @param GCPhys The guest physical address. */
1831/** @typedef PPGMPAGEMAP
1832 * Pointer to a page mapper unit for current context. */
1833/** @typedef PPPGMPAGEMAP
1834 * Pointer to a page mapper unit pointer for current context. */
1835#ifdef IN_RC
1836// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
1837// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
1838// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
1839# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
1840# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
1841 typedef void * PPGMPAGEMAP;
1842 typedef void ** PPPGMPAGEMAP;
1843//#elif IN_RING0
1844// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
1845// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
1846// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
1847//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
1848//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
1849// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
1850// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
1851#else
1852 typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
1853 typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
1854 typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
1855# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
1856# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
1857 typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
1858 typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
1859#endif
1860/** @} */
1861
1862
1863/** @name PGM Pool Indexes.
1864 * Aka. the unique shadow page identifier.
1865 * @{ */
1866/** NIL page pool IDX. */
1867#define NIL_PGMPOOL_IDX 0
1868/** The first normal index. */
1869#define PGMPOOL_IDX_FIRST_SPECIAL 1
1870/** Page directory (32-bit root). */
1871#define PGMPOOL_IDX_PD 1
1872/** Page Directory Pointer Table (PAE root). */
1873#define PGMPOOL_IDX_PDPT 2
1874/** AMD64 CR3 level index.*/
1875#define PGMPOOL_IDX_AMD64_CR3 3
1876/** Nested paging root.*/
1877#define PGMPOOL_IDX_NESTED_ROOT 4
1878/** The first normal index. */
1879#define PGMPOOL_IDX_FIRST 5
1880/** The last valid index. (inclusive, 14 bits) */
1881#define PGMPOOL_IDX_LAST 0x3fff
1882/** @} */
1883
1884/** The NIL index for the parent chain. */
1885#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
1886#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
1887
1888/**
1889 * Node in the chain linking a shadowed page to it's parent (user).
1890 */
1891#pragma pack(1)
1892typedef struct PGMPOOLUSER
1893{
1894 /** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
1895 uint16_t iNext;
1896 /** The user page index. */
1897 uint16_t iUser;
1898 /** Index into the user table. */
1899 uint32_t iUserTable;
1900} PGMPOOLUSER, *PPGMPOOLUSER;
1901typedef const PGMPOOLUSER *PCPGMPOOLUSER;
1902#pragma pack()
1903
1904
1905/** The NIL index for the phys ext chain. */
1906#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
1907/** The NIL pte index for a phys ext chain slot. */
1908#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
1909
1910/**
1911 * Node in the chain of physical cross reference extents.
1912 * @todo Calling this an 'extent' is not quite right, find a better name.
1913 * @todo find out the optimal size of the aidx array
1914 */
1915#pragma pack(1)
1916typedef struct PGMPOOLPHYSEXT
1917{
1918 /** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
1919 uint16_t iNext;
1920 /** Alignment. */
1921 uint16_t u16Align;
1922 /** The user page index. */
1923 uint16_t aidx[3];
1924 /** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
1925 uint16_t apte[3];
1926} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
1927typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
1928#pragma pack()
1929
1930
1931/**
1932 * The kind of page that's being shadowed.
1933 */
1934typedef enum PGMPOOLKIND
1935{
1936 /** The virtual invalid 0 entry. */
1937 PGMPOOLKIND_INVALID = 0,
1938 /** The entry is free (=unused). */
1939 PGMPOOLKIND_FREE,
1940
1941 /** Shw: 32-bit page table; Gst: no paging */
1942 PGMPOOLKIND_32BIT_PT_FOR_PHYS,
1943 /** Shw: 32-bit page table; Gst: 32-bit page table. */
1944 PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
1945 /** Shw: 32-bit page table; Gst: 4MB page. */
1946 PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
1947 /** Shw: PAE page table; Gst: no paging */
1948 PGMPOOLKIND_PAE_PT_FOR_PHYS,
1949 /** Shw: PAE page table; Gst: 32-bit page table. */
1950 PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
1951 /** Shw: PAE page table; Gst: Half of a 4MB page. */
1952 PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
1953 /** Shw: PAE page table; Gst: PAE page table. */
1954 PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
1955 /** Shw: PAE page table; Gst: 2MB page. */
1956 PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
1957
1958 /** Shw: 32-bit page directory. Gst: 32-bit page directory. */
1959 PGMPOOLKIND_32BIT_PD,
1960 /** Shw: 32-bit page directory. Gst: no paging. */
1961 PGMPOOLKIND_32BIT_PD_PHYS,
1962 /** Shw: PAE page directory 0; Gst: 32-bit page directory. */
1963 PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
1964 /** Shw: PAE page directory 1; Gst: 32-bit page directory. */
1965 PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
1966 /** Shw: PAE page directory 2; Gst: 32-bit page directory. */
1967 PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
1968 /** Shw: PAE page directory 3; Gst: 32-bit page directory. */
1969 PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
1970 /** Shw: PAE page directory; Gst: PAE page directory. */
1971 PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
1972 /** Shw: PAE page directory; Gst: no paging. Note: +NP. */
1973 PGMPOOLKIND_PAE_PD_PHYS,
1974
1975 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
1976 PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
1977 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
1978 PGMPOOLKIND_PAE_PDPT,
1979 /** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
1980 PGMPOOLKIND_PAE_PDPT_PHYS,
1981
1982 /** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
1983 PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
1984 /** Shw: 64-bit page directory pointer table; Gst: no paging */
1985 PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
1986 /** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
1987 PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
1988 /** Shw: 64-bit page directory table; Gst: no paging */
1989 PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 22 */
1990
1991 /** Shw: 64-bit PML4; Gst: 64-bit PML4. */
1992 PGMPOOLKIND_64BIT_PML4,
1993
1994 /** Shw: EPT page directory pointer table; Gst: no paging */
1995 PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
1996 /** Shw: EPT page directory table; Gst: no paging */
1997 PGMPOOLKIND_EPT_PD_FOR_PHYS,
1998 /** Shw: EPT page table; Gst: no paging */
1999 PGMPOOLKIND_EPT_PT_FOR_PHYS,
2000
2001 /** Shw: Root Nested paging table. */
2002 PGMPOOLKIND_ROOT_NESTED,
2003
2004 /** The last valid entry. */
2005 PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2006} PGMPOOLKIND;
2007
2008/**
2009 * The access attributes of the page; only applies to big pages.
2010 */
2011typedef enum
2012{
2013 PGMPOOLACCESS_DONTCARE = 0,
2014 PGMPOOLACCESS_USER_RW,
2015 PGMPOOLACCESS_USER_R,
2016 PGMPOOLACCESS_USER_RW_NX,
2017 PGMPOOLACCESS_USER_R_NX,
2018 PGMPOOLACCESS_SUPERVISOR_RW,
2019 PGMPOOLACCESS_SUPERVISOR_R,
2020 PGMPOOLACCESS_SUPERVISOR_RW_NX,
2021 PGMPOOLACCESS_SUPERVISOR_R_NX
2022} PGMPOOLACCESS;
2023
2024/**
2025 * The tracking data for a page in the pool.
2026 */
2027typedef struct PGMPOOLPAGE
2028{
2029 /** AVL node code with the (R3) physical address of this page. */
2030 AVLOHCPHYSNODECORE Core;
2031 /** Pointer to the R3 mapping of the page. */
2032#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2033 R3PTRTYPE(void *) pvPageR3;
2034#else
2035 R3R0PTRTYPE(void *) pvPageR3;
2036#endif
2037 /** The guest physical address. */
2038#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2039 uint32_t Alignment0;
2040#endif
2041 RTGCPHYS GCPhys;
2042
2043 /** Access handler statistics to determine whether the guest is (re)initializing a page table. */
2044 RTGCPTR pvLastAccessHandlerRip;
2045 RTGCPTR pvLastAccessHandlerFault;
2046 uint64_t cLastAccessHandlerCount;
2047
2048 /** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2049 uint8_t enmKind;
2050 /** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2051 uint8_t enmAccess;
2052 /** The index of this page. */
2053 uint16_t idx;
2054 /** The next entry in the list this page currently resides in.
2055 * It's either in the free list or in the GCPhys hash. */
2056 uint16_t iNext;
2057 /** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2058 uint16_t iUserHead;
2059 /** The number of present entries. */
2060 uint16_t cPresent;
2061 /** The first entry in the table which is present. */
2062 uint16_t iFirstPresent;
2063 /** The number of modifications to the monitored page. */
2064 uint16_t cModifications;
2065 /** The next modified page. NIL_PGMPOOL_IDX if tail. */
2066 uint16_t iModifiedNext;
2067 /** The previous modified page. NIL_PGMPOOL_IDX if head. */
2068 uint16_t iModifiedPrev;
2069 /** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2070 uint16_t iMonitoredNext;
2071 /** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2072 uint16_t iMonitoredPrev;
2073 /** The next page in the age list. */
2074 uint16_t iAgeNext;
2075 /** The previous page in the age list. */
2076 uint16_t iAgePrev;
2077 /** Used to indicate that the page is zeroed. */
2078 bool fZeroed;
2079 /** Used to indicate that a PT has non-global entries. */
2080 bool fSeenNonGlobal;
2081 /** Used to indicate that we're monitoring writes to the guest page. */
2082 bool fMonitored;
2083 /** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2084 * (All pages are in the age list.) */
2085 bool fCached;
2086 /** This is used by the R3 access handlers when invoked by an async thread.
2087 * It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2088 bool volatile fReusedFlushPending;
2089 /** Used to mark the page as dirty (write monitoring is temporarily
2090 * off). */
2091 bool fDirty;
2092
2093 /** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages). */
2094 uint32_t cLocked;
2095 uint32_t idxDirty;
2096 RTGCPTR pvDirtyFault;
2097} PGMPOOLPAGE, *PPGMPOOLPAGE, **PPPGMPOOLPAGE;
2098/** Pointer to a const pool page. */
2099typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2100
2101
2102/** The hash table size. */
2103# define PGMPOOL_HASH_SIZE 0x40
2104/** The hash function. */
2105# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2106
2107
2108/**
2109 * The shadow page pool instance data.
2110 *
2111 * It's all one big allocation made at init time, except for the
2112 * pages that is. The user nodes follows immediately after the
2113 * page structures.
2114 */
2115typedef struct PGMPOOL
2116{
2117 /** The VM handle - R3 Ptr. */
2118 PVMR3 pVMR3;
2119 /** The VM handle - R0 Ptr. */
2120 PVMR0 pVMR0;
2121 /** The VM handle - RC Ptr. */
2122 PVMRC pVMRC;
2123 /** The max pool size. This includes the special IDs. */
2124 uint16_t cMaxPages;
2125 /** The current pool size. */
2126 uint16_t cCurPages;
2127 /** The head of the free page list. */
2128 uint16_t iFreeHead;
2129 /* Padding. */
2130 uint16_t u16Padding;
2131 /** Head of the chain of free user nodes. */
2132 uint16_t iUserFreeHead;
2133 /** The number of user nodes we've allocated. */
2134 uint16_t cMaxUsers;
2135 /** The number of present page table entries in the entire pool. */
2136 uint32_t cPresent;
2137 /** Pointer to the array of user nodes - RC pointer. */
2138 RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2139 /** Pointer to the array of user nodes - R3 pointer. */
2140 R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2141 /** Pointer to the array of user nodes - R0 pointer. */
2142 R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2143 /** Head of the chain of free phys ext nodes. */
2144 uint16_t iPhysExtFreeHead;
2145 /** The number of user nodes we've allocated. */
2146 uint16_t cMaxPhysExts;
2147 /** Pointer to the array of physical xref extent - RC pointer. */
2148 RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2149 /** Pointer to the array of physical xref extent nodes - R3 pointer. */
2150 R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2151 /** Pointer to the array of physical xref extent nodes - R0 pointer. */
2152 R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2153 /** Hash table for GCPhys addresses. */
2154 uint16_t aiHash[PGMPOOL_HASH_SIZE];
2155 /** The head of the age list. */
2156 uint16_t iAgeHead;
2157 /** The tail of the age list. */
2158 uint16_t iAgeTail;
2159 /** Set if the cache is enabled. */
2160 bool fCacheEnabled;
2161 /** Alignment padding. */
2162 bool afPadding1[3];
2163 /** Head of the list of modified pages. */
2164 uint16_t iModifiedHead;
2165 /** The current number of modified pages. */
2166 uint16_t cModifiedPages;
2167 /** Access handler, RC. */
2168 RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnAccessHandlerRC;
2169 /** Access handler, R0. */
2170 R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnAccessHandlerR0;
2171 /** Access handler, R3. */
2172 R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnAccessHandlerR3;
2173 /** The access handler description (R3 ptr). */
2174 R3PTRTYPE(const char *) pszAccessHandler;
2175# if HC_ARCH_BITS == 32
2176 /** Alignment padding. */
2177 uint32_t u32Padding2;
2178# endif
2179 /* Next available slot. */
2180 uint32_t idxFreeDirtyPage;
2181 /* Number of active dirty pages. */
2182 uint32_t cDirtyPages;
2183 /* Array of current dirty pgm pool page indices. */
2184 struct
2185 {
2186 uint16_t uIdx;
2187 uint16_t Alignment[3];
2188 uint64_t aPage[512];
2189 } aDirtyPages[16];
2190 /** The number of pages currently in use. */
2191 uint16_t cUsedPages;
2192#ifdef VBOX_WITH_STATISTICS
2193 /** The high water mark for cUsedPages. */
2194 uint16_t cUsedPagesHigh;
2195 uint32_t Alignment1; /**< Align the next member on a 64-bit boundary. */
2196 /** Profiling pgmPoolAlloc(). */
2197 STAMPROFILEADV StatAlloc;
2198 /** Profiling pgmR3PoolClearDoIt(). */
2199 STAMPROFILE StatClearAll;
2200 /** Profiling pgmR3PoolReset(). */
2201 STAMPROFILE StatR3Reset;
2202 /** Profiling pgmPoolFlushPage(). */
2203 STAMPROFILE StatFlushPage;
2204 /** Profiling pgmPoolFree(). */
2205 STAMPROFILE StatFree;
2206 /** Counting explicit flushes by PGMPoolFlushPage(). */
2207 STAMCOUNTER StatForceFlushPage;
2208 /** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2209 STAMCOUNTER StatForceFlushDirtyPage;
2210 /** Counting flushes for reused pages. */
2211 STAMCOUNTER StatForceFlushReused;
2212 /** Profiling time spent zeroing pages. */
2213 STAMPROFILE StatZeroPage;
2214 /** Profiling of pgmPoolTrackDeref. */
2215 STAMPROFILE StatTrackDeref;
2216 /** Profiling pgmTrackFlushGCPhysPT. */
2217 STAMPROFILE StatTrackFlushGCPhysPT;
2218 /** Profiling pgmTrackFlushGCPhysPTs. */
2219 STAMPROFILE StatTrackFlushGCPhysPTs;
2220 /** Profiling pgmTrackFlushGCPhysPTsSlow. */
2221 STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2222 /** Number of times we've been out of user records. */
2223 STAMCOUNTER StatTrackFreeUpOneUser;
2224 /** Nr of flushed entries. */
2225 STAMCOUNTER StatTrackFlushEntry;
2226 /** Nr of updated entries. */
2227 STAMCOUNTER StatTrackFlushEntryKeep;
2228 /** Profiling deref activity related tracking GC physical pages. */
2229 STAMPROFILE StatTrackDerefGCPhys;
2230 /** Number of linear searches for a HCPhys in the ram ranges. */
2231 STAMCOUNTER StatTrackLinearRamSearches;
2232 /** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2233 STAMCOUNTER StamTrackPhysExtAllocFailures;
2234 /** Profiling the RC/R0 access handler. */
2235 STAMPROFILE StatMonitorRZ;
2236 /** Times we've failed interpreting the instruction. */
2237 STAMCOUNTER StatMonitorRZEmulateInstr;
2238 /** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2239 STAMPROFILE StatMonitorRZFlushPage;
2240 /* Times we've detected a page table reinit. */
2241 STAMCOUNTER StatMonitorRZFlushReinit;
2242 /** Counting flushes for pages that are modified too often. */
2243 STAMCOUNTER StatMonitorRZFlushModOverflow;
2244 /** Times we've detected fork(). */
2245 STAMCOUNTER StatMonitorRZFork;
2246 /** Profiling the RC/R0 access we've handled (except REP STOSD). */
2247 STAMPROFILE StatMonitorRZHandled;
2248 /** Times we've failed interpreting a patch code instruction. */
2249 STAMCOUNTER StatMonitorRZIntrFailPatch1;
2250 /** Times we've failed interpreting a patch code instruction during flushing. */
2251 STAMCOUNTER StatMonitorRZIntrFailPatch2;
2252 /** The number of times we've seen rep prefixes we can't handle. */
2253 STAMCOUNTER StatMonitorRZRepPrefix;
2254 /** Profiling the REP STOSD cases we've handled. */
2255 STAMPROFILE StatMonitorRZRepStosd;
2256 /** Nr of handled PT faults. */
2257 STAMCOUNTER StatMonitorRZFaultPT;
2258 /** Nr of handled PD faults. */
2259 STAMCOUNTER StatMonitorRZFaultPD;
2260 /** Nr of handled PDPT faults. */
2261 STAMCOUNTER StatMonitorRZFaultPDPT;
2262 /** Nr of handled PML4 faults. */
2263 STAMCOUNTER StatMonitorRZFaultPML4;
2264
2265 /** Profiling the R3 access handler. */
2266 STAMPROFILE StatMonitorR3;
2267 /** Times we've failed interpreting the instruction. */
2268 STAMCOUNTER StatMonitorR3EmulateInstr;
2269 /** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2270 STAMPROFILE StatMonitorR3FlushPage;
2271 /* Times we've detected a page table reinit. */
2272 STAMCOUNTER StatMonitorR3FlushReinit;
2273 /** Counting flushes for pages that are modified too often. */
2274 STAMCOUNTER StatMonitorR3FlushModOverflow;
2275 /** Times we've detected fork(). */
2276 STAMCOUNTER StatMonitorR3Fork;
2277 /** Profiling the R3 access we've handled (except REP STOSD). */
2278 STAMPROFILE StatMonitorR3Handled;
2279 /** The number of times we've seen rep prefixes we can't handle. */
2280 STAMCOUNTER StatMonitorR3RepPrefix;
2281 /** Profiling the REP STOSD cases we've handled. */
2282 STAMPROFILE StatMonitorR3RepStosd;
2283 /** Nr of handled PT faults. */
2284 STAMCOUNTER StatMonitorR3FaultPT;
2285 /** Nr of handled PD faults. */
2286 STAMCOUNTER StatMonitorR3FaultPD;
2287 /** Nr of handled PDPT faults. */
2288 STAMCOUNTER StatMonitorR3FaultPDPT;
2289 /** Nr of handled PML4 faults. */
2290 STAMCOUNTER StatMonitorR3FaultPML4;
2291 /** The number of times we're called in an async thread an need to flush. */
2292 STAMCOUNTER StatMonitorR3Async;
2293 /** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2294 STAMCOUNTER StatResetDirtyPages;
2295 /** Times we've called pgmPoolAddDirtyPage. */
2296 STAMCOUNTER StatDirtyPage;
2297 /** Times we've had to flush duplicates for dirty page management. */
2298 STAMCOUNTER StatDirtyPageDupFlush;
2299 /** Times we've had to flush because of overflow. */
2300 STAMCOUNTER StatDirtyPageOverFlowFlush;
2301
2302 /** The high water mark for cModifiedPages. */
2303 uint16_t cModifiedPagesHigh;
2304 uint16_t Alignment2[3]; /**< Align the next member on a 64-bit boundary. */
2305
2306 /** The number of cache hits. */
2307 STAMCOUNTER StatCacheHits;
2308 /** The number of cache misses. */
2309 STAMCOUNTER StatCacheMisses;
2310 /** The number of times we've got a conflict of 'kind' in the cache. */
2311 STAMCOUNTER StatCacheKindMismatches;
2312 /** Number of times we've been out of pages. */
2313 STAMCOUNTER StatCacheFreeUpOne;
2314 /** The number of cacheable allocations. */
2315 STAMCOUNTER StatCacheCacheable;
2316 /** The number of uncacheable allocations. */
2317 STAMCOUNTER StatCacheUncacheable;
2318#else
2319 uint32_t Alignment3; /**< Align the next member on a 64-bit boundary. */
2320#endif
2321 /** The AVL tree for looking up a page by its HC physical address. */
2322 AVLOHCPHYSTREE HCPhysTree;
2323 uint32_t Alignment4; /**< Align the next member on a 64-bit boundary. */
2324 /** Array of pages. (cMaxPages in length)
2325 * The Id is the index into thist array.
2326 */
2327 PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2328} PGMPOOL, *PPGMPOOL, **PPPGMPOOL;
2329AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2330AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2331AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2332#ifdef VBOX_WITH_STATISTICS
2333AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2334#endif
2335AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2336
2337
2338/** @def PGMPOOL_PAGE_2_PTR
2339 * Maps a pool page pool into the current context.
2340 *
2341 * @returns VBox status code.
2342 * @param pVM The VM handle.
2343 * @param pPage The pool page.
2344 *
2345 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2346 * small page window employeed by that function. Be careful.
2347 * @remark There is no need to assert on the result.
2348 */
2349#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2350# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageInlined((pVM), (pPage) RTLOG_COMMA_SRC_POS)
2351#elif defined(VBOX_STRICT)
2352# define PGMPOOL_PAGE_2_PTR(pVM, pPage) pgmPoolMapPageStrict(pPage)
2353DECLINLINE(void *) pgmPoolMapPageStrict(PPGMPOOLPAGE pPage)
2354{
2355 Assert(pPage && pPage->pvPageR3);
2356 return pPage->pvPageR3;
2357}
2358#else
2359# define PGMPOOL_PAGE_2_PTR(pVM, pPage) ((pPage)->pvPageR3)
2360#endif
2361
2362
2363/** @def PGMPOOL_PAGE_2_PTR_V2
2364 * Maps a pool page pool into the current context, taking both VM and VMCPU.
2365 *
2366 * @returns VBox status code.
2367 * @param pVM The VM handle.
2368 * @param pVCpu The current CPU.
2369 * @param pPage The pool page.
2370 *
2371 * @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2372 * small page window employeed by that function. Be careful.
2373 * @remark There is no need to assert on the result.
2374 */
2375#if defined(IN_RC) || defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2376# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) pgmPoolMapPageV2Inlined((pVM), (pVCpu), (pPage) RTLOG_COMMA_SRC_POS)
2377#else
2378# define PGMPOOL_PAGE_2_PTR_V2(pVM, pVCpu, pPage) PGMPOOL_PAGE_2_PTR((pVM), (pPage))
2379#endif
2380
2381
2382/** @name Per guest page tracking data.
2383 * This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2384 * is to use more bits for it and split it up later on. But for now we'll play
2385 * safe and change as little as possible.
2386 *
2387 * The 16-bit word has two parts:
2388 *
2389 * The first 14-bit forms the @a idx field. It is either the index of a page in
2390 * the shadow page pool, or and index into the extent list.
2391 *
2392 * The 2 topmost bits makes up the @a cRefs field, which counts the number of
2393 * shadow page pool references to the page. If cRefs equals
2394 * PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2395 * (misnomer) table and not the shadow page pool.
2396 *
2397 * See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2398 * the 16-bit word.
2399 *
2400 * @{ */
2401/** The shift count for getting to the cRefs part. */
2402#define PGMPOOL_TD_CREFS_SHIFT 14
2403/** The mask applied after shifting the tracking data down by
2404 * PGMPOOL_TD_CREFS_SHIFT. */
2405#define PGMPOOL_TD_CREFS_MASK 0x3
2406/** The cRefs value used to indicate that the idx is the head of a
2407 * physical cross reference list. */
2408#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2409/** The shift used to get idx. */
2410#define PGMPOOL_TD_IDX_SHIFT 0
2411/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2412#define PGMPOOL_TD_IDX_MASK 0x3fff
2413/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2414 * simply too many mappings of this page. */
2415#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2416
2417/** @def PGMPOOL_TD_MAKE
2418 * Makes a 16-bit tracking data word.
2419 *
2420 * @returns tracking data.
2421 * @param cRefs The @a cRefs field. Must be within bounds!
2422 * @param idx The @a idx field. Must also be within bounds! */
2423#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) | (idx) )
2424
2425/** @def PGMPOOL_TD_GET_CREFS
2426 * Get the @a cRefs field from a tracking data word.
2427 *
2428 * @returns The @a cRefs field
2429 * @param u16 The tracking data word.
2430 * @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2431 * non-zero @a u16. */
2432#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2433
2434/** @def PGMPOOL_TD_GET_IDX
2435 * Get the @a idx field from a tracking data word.
2436 *
2437 * @returns The @a idx field
2438 * @param u16 The tracking data word. */
2439#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2440/** @} */
2441
2442
2443/**
2444 * Trees are using self relative offsets as pointers.
2445 * So, all its data, including the root pointer, must be in the heap for HC and GC
2446 * to have the same layout.
2447 */
2448typedef struct PGMTREES
2449{
2450 /** Physical access handlers (AVL range+offsetptr tree). */
2451 AVLROGCPHYSTREE PhysHandlers;
2452 /** Virtual access handlers (AVL range + GC ptr tree). */
2453 AVLROGCPTRTREE VirtHandlers;
2454 /** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2455 AVLROGCPHYSTREE PhysToVirtHandlers;
2456 /** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2457 AVLROGCPTRTREE HyperVirtHandlers;
2458} PGMTREES;
2459/** Pointer to PGM trees. */
2460typedef PGMTREES *PPGMTREES;
2461
2462
2463/**
2464 * Page fault guest state for the AMD64 paging mode.
2465 */
2466typedef struct PGMPTWALKCORE
2467{
2468 /** The guest virtual address that is being resolved by the walk
2469 * (input). */
2470 RTGCPTR GCPtr;
2471
2472 /** The guest physical address that is the result of the walk.
2473 * @remarks only valid if fSucceeded is set. */
2474 RTGCPHYS GCPhys;
2475
2476 /** Set if the walk succeeded, i.d. GCPhys is valid. */
2477 bool fSucceeded;
2478 /** The level problem arrised at.
2479 * PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2480 * level 8. This is 0 on success. */
2481 uint8_t uLevel;
2482 /** Set if the page isn't present. */
2483 bool fNotPresent;
2484 /** Encountered a bad physical address. */
2485 bool fBadPhysAddr;
2486 /** Set if there was reserved bit violations. */
2487 bool fRsvdError;
2488 /** Set if it involves a big page (2/4 MB). */
2489 bool fBigPage;
2490 /** Set if it involves a gigantic page (1 GB). */
2491 bool fGigantPage;
2492 /** The effect X86_PTE_US flag for the address. */
2493 bool fEffectiveUS;
2494 /** The effect X86_PTE_RW flag for the address. */
2495 bool fEffectiveRW;
2496 /** The effect X86_PTE_NX flag for the address. */
2497 bool fEffectiveNX;
2498} PGMPTWALKCORE;
2499
2500
2501/**
2502 * Guest page table walk for the AMD64 mode.
2503 */
2504typedef struct PGMPTWALKGSTAMD64
2505{
2506 /** The common core. */
2507 PGMPTWALKCORE Core;
2508
2509 PX86PML4 pPml4;
2510 PX86PML4E pPml4e;
2511 X86PML4E Pml4e;
2512
2513 PX86PDPT pPdpt;
2514 PX86PDPE pPdpe;
2515 X86PDPE Pdpe;
2516
2517 PX86PDPAE pPd;
2518 PX86PDEPAE pPde;
2519 X86PDEPAE Pde;
2520
2521 PX86PTPAE pPt;
2522 PX86PTEPAE pPte;
2523 X86PTEPAE Pte;
2524} PGMPTWALKGSTAMD64;
2525/** Pointer to a AMD64 guest page table walk. */
2526typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2527/** Pointer to a const AMD64 guest page table walk. */
2528typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2529
2530/**
2531 * Guest page table walk for the PAE mode.
2532 */
2533typedef struct PGMPTWALKGSTPAE
2534{
2535 /** The common core. */
2536 PGMPTWALKCORE Core;
2537
2538 PX86PDPT pPdpt;
2539 PX86PDPE pPdpe;
2540 X86PDPE Pdpe;
2541
2542 PX86PDPAE pPd;
2543 PX86PDEPAE pPde;
2544 X86PDEPAE Pde;
2545
2546 PX86PTPAE pPt;
2547 PX86PTEPAE pPte;
2548 X86PTEPAE Pte;
2549} PGMPTWALKGSTPAE;
2550/** Pointer to a PAE guest page table walk. */
2551typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2552/** Pointer to a const AMD64 guest page table walk. */
2553typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2554
2555/**
2556 * Guest page table walk for the 32-bit mode.
2557 */
2558typedef struct PGMPTWALKGST32BIT
2559{
2560 /** The common core. */
2561 PGMPTWALKCORE Core;
2562
2563 PX86PD pPd;
2564 PX86PDE pPde;
2565 X86PDE Pde;
2566
2567 PX86PT pPt;
2568 PX86PTE pPte;
2569 X86PTE Pte;
2570} PGMPTWALKGST32BIT;
2571/** Pointer to a 32-bit guest page table walk. */
2572typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2573/** Pointer to a const 32-bit guest page table walk. */
2574typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2575
2576
2577/** @name Paging mode macros
2578 * @{
2579 */
2580#ifdef IN_RC
2581# define PGM_CTX(a,b) a##RC##b
2582# define PGM_CTX_STR(a,b) a "GC" b
2583# define PGM_CTX_DECL(type) VMMRCDECL(type)
2584#else
2585# ifdef IN_RING3
2586# define PGM_CTX(a,b) a##R3##b
2587# define PGM_CTX_STR(a,b) a "R3" b
2588# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2589# else
2590# define PGM_CTX(a,b) a##R0##b
2591# define PGM_CTX_STR(a,b) a "R0" b
2592# define PGM_CTX_DECL(type) VMMDECL(type)
2593# endif
2594#endif
2595
2596#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2597#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2598#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2599#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2600#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2601#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2602#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2603#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2604#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2605#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2606#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2607#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2608#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2609#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2610#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2611#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2612#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2613
2614#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2615#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2616#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2617#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2618#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2619#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2620#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2621#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2622#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2623#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2624#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2625#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2626#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2627#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2628#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2629#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2630#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2631
2632/* Shw_Gst */
2633#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2634#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2635#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2636#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2637#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2638#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2639#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2640#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2641#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2642#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2643#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2644#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2645#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2646#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2647#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2648#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2649#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2650#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2651#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2652
2653#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2654#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2655#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2656#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2657#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2658#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2659#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2660#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2661#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2662#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2663#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2664#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2665#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2666#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2667#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2668#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2669#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2670#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2671#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2672#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2673#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2674#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2675#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2676#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2677#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2678#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2679#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2680#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2681#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2682#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2683#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2684#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2685#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2686#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2687#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2688#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2689#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2690
2691#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2692#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2693/** @} */
2694
2695/**
2696 * Data for each paging mode.
2697 */
2698typedef struct PGMMODEDATA
2699{
2700 /** The guest mode type. */
2701 uint32_t uGstType;
2702 /** The shadow mode type. */
2703 uint32_t uShwType;
2704
2705 /** @name Function pointers for Shadow paging.
2706 * @{
2707 */
2708 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2709 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2710 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2711 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2712
2713 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2714 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2715
2716 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2717 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2718 /** @} */
2719
2720 /** @name Function pointers for Guest paging.
2721 * @{
2722 */
2723 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2724 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2725 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2726 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2727 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2728 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2729 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2730 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2731 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2732 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2733 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2734 /** @} */
2735
2736 /** @name Function pointers for Both Shadow and Guest paging.
2737 * @{
2738 */
2739 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2740 /* no pfnR3BthTrap0eHandler */
2741 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2742 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2743 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2744 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2745#ifdef VBOX_STRICT
2746 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2747#endif
2748 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2749 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
2750
2751 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2752 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2753 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2754 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2755 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2756#ifdef VBOX_STRICT
2757 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2758#endif
2759 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2760 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
2761
2762 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
2763 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2764 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2765 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2766 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
2767#ifdef VBOX_STRICT
2768 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
2769#endif
2770 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
2771 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
2772 /** @} */
2773} PGMMODEDATA, *PPGMMODEDATA;
2774
2775
2776#ifdef VBOX_WITH_STATISTICS
2777/**
2778 * PGM statistics.
2779 *
2780 * These lives on the heap when compiled in as they would otherwise waste
2781 * unnecessary space in release builds.
2782 */
2783typedef struct PGMSTATS
2784{
2785 /* R3 only: */
2786 STAMCOUNTER StatR3DetectedConflicts; /**< R3: Number of times PGMR3MapHasConflicts() detected a conflict. */
2787 STAMPROFILE StatR3ResolveConflict; /**< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). */
2788
2789 /* R3+RZ */
2790 STAMCOUNTER StatRZChunkR3MapTlbHits; /**< RC/R0: Ring-3/0 chunk mapper TLB hits. */
2791 STAMCOUNTER StatRZChunkR3MapTlbMisses; /**< RC/R0: Ring-3/0 chunk mapper TLB misses. */
2792 STAMCOUNTER StatRZPageMapTlbHits; /**< RC/R0: Ring-3/0 page mapper TLB hits. */
2793 STAMCOUNTER StatRZPageMapTlbMisses; /**< RC/R0: Ring-3/0 page mapper TLB misses. */
2794 STAMCOUNTER StatPageMapTlbFlushes; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2795 STAMCOUNTER StatPageMapTlbFlushEntry; /**< ALL: Ring-3/0 page mapper TLB flushes. */
2796 STAMCOUNTER StatR3ChunkR3MapTlbHits; /**< R3: Ring-3/0 chunk mapper TLB hits. */
2797 STAMCOUNTER StatR3ChunkR3MapTlbMisses; /**< R3: Ring-3/0 chunk mapper TLB misses. */
2798 STAMCOUNTER StatR3PageMapTlbHits; /**< R3: Ring-3/0 page mapper TLB hits. */
2799 STAMCOUNTER StatR3PageMapTlbMisses; /**< R3: Ring-3/0 page mapper TLB misses. */
2800 STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /**< RC/R0: Profiling of the virtual handler resets. */
2801 STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /**< RC/R0: Profiling of the virtual handler updates. */
2802 STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /**< R3: Profiling of the virtual handler resets. */
2803 STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /**< R3: Profiling of the virtual handler updates. */
2804 STAMCOUNTER StatR3PhysHandlerReset; /**< R3: The number of times PGMHandlerPhysicalReset is called. */
2805 STAMCOUNTER StatRZPhysHandlerReset; /**< RC/R0: The number of times PGMHandlerPhysicalReset is called. */
2806 STAMCOUNTER StatR3PhysHandlerLookupHits; /**< R3: Number of cache hits when looking up physical handlers. */
2807 STAMCOUNTER StatR3PhysHandlerLookupMisses; /**< R3: Number of cache misses when looking up physical handlers. */
2808 STAMCOUNTER StatRZPhysHandlerLookupHits; /**< RC/R0: Number of cache hits when lookup up physical handlers. */
2809 STAMCOUNTER StatRZPhysHandlerLookupMisses; /**< RC/R0: Number of cache misses when looking up physical handlers */
2810 STAMPROFILE StatRZVirtHandlerSearchByPhys; /**< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2811 STAMPROFILE StatR3VirtHandlerSearchByPhys; /**< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. */
2812 STAMCOUNTER StatRZPageReplaceShared; /**< RC/R0: Times a shared page has been replaced by a private one. */
2813 STAMCOUNTER StatRZPageReplaceZero; /**< RC/R0: Times the zero page has been replaced by a private one. */
2814/// @todo STAMCOUNTER StatRZPageHandyAllocs; /**< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. */
2815 STAMCOUNTER StatR3PageReplaceShared; /**< R3: Times a shared page has been replaced by a private one. */
2816 STAMCOUNTER StatR3PageReplaceZero; /**< R3: Times the zero page has been replaced by a private one. */
2817/// @todo STAMCOUNTER StatR3PageHandyAllocs; /**< R3: The number of times we've executed GMMR3AllocateHandyPages. */
2818
2819 /* RC only: */
2820 STAMCOUNTER StatRCInvlPgConflict; /**< RC: Number of times PGMInvalidatePage() detected a mapping conflict. */
2821 STAMCOUNTER StatRCInvlPgSyncMonCR3; /**< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. */
2822
2823 STAMCOUNTER StatRZPhysRead;
2824 STAMCOUNTER StatRZPhysReadBytes;
2825 STAMCOUNTER StatRZPhysWrite;
2826 STAMCOUNTER StatRZPhysWriteBytes;
2827 STAMCOUNTER StatR3PhysRead;
2828 STAMCOUNTER StatR3PhysReadBytes;
2829 STAMCOUNTER StatR3PhysWrite;
2830 STAMCOUNTER StatR3PhysWriteBytes;
2831 STAMCOUNTER StatRCPhysRead;
2832 STAMCOUNTER StatRCPhysReadBytes;
2833 STAMCOUNTER StatRCPhysWrite;
2834 STAMCOUNTER StatRCPhysWriteBytes;
2835
2836 STAMCOUNTER StatRZPhysSimpleRead;
2837 STAMCOUNTER StatRZPhysSimpleReadBytes;
2838 STAMCOUNTER StatRZPhysSimpleWrite;
2839 STAMCOUNTER StatRZPhysSimpleWriteBytes;
2840 STAMCOUNTER StatR3PhysSimpleRead;
2841 STAMCOUNTER StatR3PhysSimpleReadBytes;
2842 STAMCOUNTER StatR3PhysSimpleWrite;
2843 STAMCOUNTER StatR3PhysSimpleWriteBytes;
2844 STAMCOUNTER StatRCPhysSimpleRead;
2845 STAMCOUNTER StatRCPhysSimpleReadBytes;
2846 STAMCOUNTER StatRCPhysSimpleWrite;
2847 STAMCOUNTER StatRCPhysSimpleWriteBytes;
2848
2849 STAMCOUNTER StatTrackVirgin; /**< The number of first time shadowings. */
2850 STAMCOUNTER StatTrackAliased; /**< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. */
2851 STAMCOUNTER StatTrackAliasedMany; /**< The number of times we're tracking using cRef2. */
2852 STAMCOUNTER StatTrackAliasedLots; /**< The number of times we're hitting pages which has overflowed cRef2. */
2853 STAMCOUNTER StatTrackNoExtentsLeft; /**< The number of times the extent list was exhausted. */
2854 STAMCOUNTER StatTrackOverflows; /**< The number of times the extent list grows to long. */
2855 STAMPROFILE StatTrackDeref; /**< Profiling of SyncPageWorkerTrackDeref (expensive). */
2856
2857 /** Time spent by the host OS for large page allocation. */
2858 STAMPROFILE StatAllocLargePage;
2859 /** Time spent clearing the newly allocated large pages. */
2860 STAMPROFILE StatClearLargePage;
2861 /** The number of times allocating a large pages takes more than the allowed period. */
2862 STAMCOUNTER StatLargePageOverflow;
2863 /** pgmPhysIsValidLargePage profiling - R3 */
2864 STAMPROFILE StatR3IsValidLargePage;
2865 /** pgmPhysIsValidLargePage profiling - RZ*/
2866 STAMPROFILE StatRZIsValidLargePage;
2867
2868 STAMPROFILE StatChunkAging;
2869 STAMPROFILE StatChunkFindCandidate;
2870 STAMPROFILE StatChunkUnmap;
2871 STAMPROFILE StatChunkMap;
2872} PGMSTATS;
2873#endif /* VBOX_WITH_STATISTICS */
2874
2875
2876/**
2877 * Converts a PGM pointer into a VM pointer.
2878 * @returns Pointer to the VM structure the PGM is part of.
2879 * @param pPGM Pointer to PGM instance data.
2880 */
2881#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
2882
2883/**
2884 * PGM Data (part of VM)
2885 */
2886typedef struct PGM
2887{
2888 /** Offset to the VM structure. */
2889 int32_t offVM;
2890 /** Offset of the PGMCPU structure relative to VMCPU. */
2891 int32_t offVCpuPGM;
2892
2893 /** @cfgm{RamPreAlloc, boolean, false}
2894 * Indicates whether the base RAM should all be allocated before starting
2895 * the VM (default), or if it should be allocated when first written to.
2896 */
2897 bool fRamPreAlloc;
2898 /** Indicates whether write monitoring is currently in use.
2899 * This is used to prevent conflicts between live saving and page sharing
2900 * detection. */
2901 bool fPhysWriteMonitoringEngaged;
2902 /** Set if the CPU has less than 52-bit physical address width.
2903 * This is used */
2904 bool fLessThan52PhysicalAddressBits;
2905 /** Set when nested paging is active.
2906 * This is meant to save calls to HWACCMIsNestedPagingActive and let the
2907 * compilers optimize the code better. Whether we use nested paging or
2908 * not is something we find out during VMM initialization and we won't
2909 * change this later on. */
2910 bool fNestedPaging;
2911 /** The host paging mode. (This is what SUPLib reports.) */
2912 SUPPAGINGMODE enmHostMode;
2913 /** We're not in a state which permits writes to guest memory.
2914 * (Only used in strict builds.) */
2915 bool fNoMorePhysWrites;
2916 /** Set if PCI passthrough is enabled. */
2917 bool fPciPassthrough;
2918 /** Alignment padding that makes the next member start on a 8 byte boundary. */
2919 bool afAlignment1[2];
2920
2921 /** Indicates that PGMR3FinalizeMappings has been called and that further
2922 * PGMR3MapIntermediate calls will be rejected. */
2923 bool fFinalizedMappings;
2924 /** If set no conflict checks are required. */
2925 bool fMappingsFixed;
2926 /** If set if restored as fixed but we were unable to re-fixate at the old
2927 * location because of room or address incompatibilities. */
2928 bool fMappingsFixedRestored;
2929 /** If set, then no mappings are put into the shadow page table.
2930 * Use pgmMapAreMappingsEnabled() instead of direct access. */
2931 bool fMappingsDisabled;
2932 /** Size of fixed mapping.
2933 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2934 uint32_t cbMappingFixed;
2935 /** Generation ID for the RAM ranges. This member is incremented everytime
2936 * a RAM range is linked or unlinked. */
2937 uint32_t volatile idRamRangesGen;
2938
2939 /** Base address (GC) of fixed mapping.
2940 * This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
2941 RTGCPTR GCPtrMappingFixed;
2942 /** The address of the previous RAM range mapping. */
2943 RTGCPTR GCPtrPrevRamRangeMapping;
2944
2945 /** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
2946 RTGCPHYS GCPhys4MBPSEMask;
2947 /** Mask containing the invalid bits of a guest physical address.
2948 * @remarks this does not stop at bit 52. */
2949 RTGCPHYS GCPhysInvAddrMask;
2950
2951
2952 /** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
2953 * This is sorted by physical address and contains no overlapping ranges. */
2954 R3PTRTYPE(PPGMRAMRANGE) pRamRangesR3;
2955 /** PGM offset based trees - R3 Ptr. */
2956 R3PTRTYPE(PPGMTREES) pTreesR3;
2957 /** Caching the last physical handler we looked up in R3. */
2958 R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
2959 /** Shadow Page Pool - R3 Ptr. */
2960 R3PTRTYPE(PPGMPOOL) pPoolR3;
2961 /** Linked list of GC mappings - for HC.
2962 * The list is sorted ascending on address. */
2963 R3PTRTYPE(PPGMMAPPING) pMappingsR3;
2964 /** Pointer to the list of ROM ranges - for R3.
2965 * This is sorted by physical address and contains no overlapping ranges. */
2966 R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
2967 /** Pointer to the list of MMIO2 ranges - for R3.
2968 * Registration order. */
2969 R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
2970 /** Pointer to SHW+GST mode data (function pointers).
2971 * The index into this table is made up from */
2972 R3PTRTYPE(PPGMMODEDATA) paModeData;
2973 /*RTR3PTR R3PtrAlignment0;*/
2974
2975
2976 /** R0 pointer corresponding to PGM::pRamRangesR3. */
2977 R0PTRTYPE(PPGMRAMRANGE) pRamRangesR0;
2978 /** PGM offset based trees - R0 Ptr. */
2979 R0PTRTYPE(PPGMTREES) pTreesR0;
2980 /** Caching the last physical handler we looked up in R0. */
2981 R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
2982 /** Shadow Page Pool - R0 Ptr. */
2983 R0PTRTYPE(PPGMPOOL) pPoolR0;
2984 /** Linked list of GC mappings - for R0.
2985 * The list is sorted ascending on address. */
2986 R0PTRTYPE(PPGMMAPPING) pMappingsR0;
2987 /** R0 pointer corresponding to PGM::pRomRangesR3. */
2988 R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
2989 /*RTR0PTR R0PtrAlignment0;*/
2990
2991
2992 /** RC pointer corresponding to PGM::pRamRangesR3. */
2993 RCPTRTYPE(PPGMRAMRANGE) pRamRangesRC;
2994 /** PGM offset based trees - RC Ptr. */
2995 RCPTRTYPE(PPGMTREES) pTreesRC;
2996 /** Caching the last physical handler we looked up in RC. */
2997 RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
2998 /** Shadow Page Pool - RC Ptr. */
2999 RCPTRTYPE(PPGMPOOL) pPoolRC;
3000 /** Linked list of GC mappings - for RC.
3001 * The list is sorted ascending on address. */
3002 RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3003 /** RC pointer corresponding to PGM::pRomRangesR3. */
3004 RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3005 /*RTRCPTR RCPtrAlignment0;*/
3006 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3007 RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3008 /** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3009 RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3010
3011
3012 /** Pointer to the 5 page CR3 content mapping.
3013 * The first page is always the CR3 (in some form) while the 4 other pages
3014 * are used of the PDs in PAE mode. */
3015 RTGCPTR GCPtrCR3Mapping;
3016
3017 /** @name Intermediate Context
3018 * @{ */
3019 /** Pointer to the intermediate page directory - Normal. */
3020 R3PTRTYPE(PX86PD) pInterPD;
3021 /** Pointer to the intermediate page tables - Normal.
3022 * There are two page tables, one for the identity mapping and one for
3023 * the host context mapping (of the core code). */
3024 R3PTRTYPE(PX86PT) apInterPTs[2];
3025 /** Pointer to the intermediate page tables - PAE. */
3026 R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3027 /** Pointer to the intermediate page directory - PAE. */
3028 R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3029 /** Pointer to the intermediate page directory - PAE. */
3030 R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3031 /** Pointer to the intermediate page-map level 4 - AMD64. */
3032 R3PTRTYPE(PX86PML4) pInterPaePML4;
3033 /** Pointer to the intermediate page directory - AMD64. */
3034 R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3035 /** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3036 RTHCPHYS HCPhysInterPD;
3037 /** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3038 RTHCPHYS HCPhysInterPaePDPT;
3039 /** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3040 RTHCPHYS HCPhysInterPaePML4;
3041 /** @} */
3042
3043 /** Base address of the dynamic page mapping area.
3044 * The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3045 *
3046 * @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3047 * work out. Some cleaning up of the initialization that would
3048 * remove this memory is yet to be done...
3049 */
3050 RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3051 /** The address of the raw-mode context mapping cache. */
3052 RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3053 /** The address of the ring-0 mapping cache if we're making use of it. */
3054 RTR0PTR pvR0DynMapUsed;
3055#if HC_ARCH_BITS == 32
3056 /** Alignment padding that makes the next member start on a 8 byte boundary. */
3057 uint32_t u32Alignment2;
3058#endif
3059
3060 /** PGM critical section.
3061 * This protects the physical & virtual access handlers, ram ranges,
3062 * and the page flag updating (some of it anyway).
3063 */
3064 PDMCRITSECT CritSect;
3065
3066 /**
3067 * Data associated with managing the ring-3 mappings of the allocation chunks.
3068 */
3069 struct
3070 {
3071 /** The chunk tree, ordered by chunk id. */
3072#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3073 R3PTRTYPE(PAVLU32NODECORE) pTree;
3074#else
3075 R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3076#endif
3077#if HC_ARCH_BITS == 32
3078 uint32_t u32Alignment;
3079#endif
3080 /** The chunk mapping TLB. */
3081 PGMCHUNKR3MAPTLB Tlb;
3082 /** The number of mapped chunks. */
3083 uint32_t c;
3084 /** The maximum number of mapped chunks.
3085 * @cfgm PGM/MaxRing3Chunks */
3086 uint32_t cMax;
3087 /** The current time. */
3088 uint32_t iNow;
3089 /** Number of pgmR3PhysChunkFindUnmapCandidate calls left to the next ageing. */
3090 uint32_t AgeingCountdown;
3091 } ChunkR3Map;
3092
3093 /**
3094 * The page mapping TLB for ring-3 and (for the time being) ring-0.
3095 */
3096 PGMPAGER3MAPTLB PhysTlbHC;
3097
3098 /** @name The zero page.
3099 * @{ */
3100 /** The host physical address of the zero page. */
3101 RTHCPHYS HCPhysZeroPg;
3102 /** The ring-3 mapping of the zero page. */
3103 RTR3PTR pvZeroPgR3;
3104 /** The ring-0 mapping of the zero page. */
3105 RTR0PTR pvZeroPgR0;
3106 /** The GC mapping of the zero page. */
3107 RTRCPTR pvZeroPgRC;
3108 RTRCPTR RCPtrAlignment3;
3109 /** @}*/
3110
3111 /** @name The Invalid MMIO page.
3112 * This page is filled with 0xfeedface.
3113 * @{ */
3114 /** The host physical address of the invalid MMIO page. */
3115 RTHCPHYS HCPhysMmioPg;
3116 /** The host pysical address of the invalid MMIO page plus all invalid
3117 * physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3118 * @remarks Check fLessThan52PhysicalAddressBits before use. */
3119 RTHCPHYS HCPhysInvMmioPg;
3120 /** The ring-3 mapping of the invalid MMIO page. */
3121 RTR3PTR pvMmioPgR3;
3122#if HC_ARCH_BITS == 32
3123 RTR3PTR R3PtrAlignment4;
3124#endif
3125 /** @} */
3126
3127
3128 /** The number of handy pages. */
3129 uint32_t cHandyPages;
3130
3131 /** The number of large handy pages. */
3132 uint32_t cLargeHandyPages;
3133
3134 /**
3135 * Array of handy pages.
3136 *
3137 * This array is used in a two way communication between pgmPhysAllocPage
3138 * and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3139 * an intermediary.
3140 *
3141 * The size of this array is important, see pgmPhysEnsureHandyPage for details.
3142 * (The current size of 32 pages, means 128 KB of handy memory.)
3143 */
3144 GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3145
3146 /**
3147 * Array of large handy pages. (currently size 1)
3148 *
3149 * This array is used in a two way communication between pgmPhysAllocLargePage
3150 * and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3151 * an intermediary.
3152 */
3153 GMMPAGEDESC aLargeHandyPage[1];
3154
3155 /**
3156 * Live save data.
3157 */
3158 struct
3159 {
3160 /** Per type statistics. */
3161 struct
3162 {
3163 /** The number of ready pages. */
3164 uint32_t cReadyPages;
3165 /** The number of dirty pages. */
3166 uint32_t cDirtyPages;
3167 /** The number of ready zero pages. */
3168 uint32_t cZeroPages;
3169 /** The number of write monitored pages. */
3170 uint32_t cMonitoredPages;
3171 } Rom,
3172 Mmio2,
3173 Ram;
3174 /** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3175 uint32_t cIgnoredPages;
3176 /** Indicates that a live save operation is active. */
3177 bool fActive;
3178 /** Padding. */
3179 bool afReserved[2];
3180 /** The next history index. */
3181 uint8_t iDirtyPagesHistory;
3182 /** History of the total amount of dirty pages. */
3183 uint32_t acDirtyPagesHistory[64];
3184 /** Short term dirty page average. */
3185 uint32_t cDirtyPagesShort;
3186 /** Long term dirty page average. */
3187 uint32_t cDirtyPagesLong;
3188 /** The number of saved pages. This is used to get some kind of estimate of the
3189 * link speed so we can decide when we're done. It is reset after the first
3190 * 7 passes so the speed estimate doesn't get inflated by the initial set of
3191 * zero pages. */
3192 uint64_t cSavedPages;
3193 /** The nanosecond timestamp when cSavedPages was 0. */
3194 uint64_t uSaveStartNS;
3195 /** Pages per second (for statistics). */
3196 uint32_t cPagesPerSecond;
3197 uint32_t cAlignment;
3198 } LiveSave;
3199
3200 /** @name Error injection.
3201 * @{ */
3202 /** Inject handy page allocation errors pretending we're completely out of
3203 * memory. */
3204 bool volatile fErrInjHandyPages;
3205 /** Padding. */
3206 bool afReserved[3];
3207 /** @} */
3208
3209 /** @name Release Statistics
3210 * @{ */
3211 uint32_t cAllPages; /**< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) */
3212 uint32_t cPrivatePages; /**< The number of private pages. */
3213 uint32_t cSharedPages; /**< The number of shared pages. */
3214 uint32_t cReusedSharedPages; /**< The number of reused shared pages. */
3215 uint32_t cZeroPages; /**< The number of zero backed pages. */
3216 uint32_t cPureMmioPages; /**< The number of pure MMIO pages. */
3217 uint32_t cMonitoredPages; /**< The number of write monitored pages. */
3218 uint32_t cWrittenToPages; /**< The number of previously write monitored pages. */
3219 uint32_t cWriteLockedPages; /**< The number of write locked pages. */
3220 uint32_t cReadLockedPages; /**< The number of read locked pages. */
3221 uint32_t cBalloonedPages; /**< The number of ballooned pages. */
3222 uint32_t cMappedChunks; /**< Number of times we mapped a chunk. */
3223 uint32_t cUnmappedChunks; /**< Number of times we unmapped a chunk. */
3224 uint32_t cLargePages; /**< The number of large pages. */
3225 uint32_t cLargePagesDisabled;/**< The number of disabled large pages. */
3226/* uint32_t aAlignment4[1]; */
3227
3228 /** The number of times we were forced to change the hypervisor region location. */
3229 STAMCOUNTER cRelocations;
3230
3231 STAMCOUNTER StatLargePageReused; /**< The number of large pages we've reused.*/
3232 STAMCOUNTER StatLargePageRefused; /**< The number of times we couldn't use a large page.*/
3233 STAMCOUNTER StatLargePageRecheck; /**< The number of times we rechecked a disabled large page.*/
3234 /** @} */
3235
3236#ifdef VBOX_WITH_STATISTICS
3237 /** @name Statistics on the heap.
3238 * @{ */
3239 R3PTRTYPE(PGMSTATS *) pStatsR3;
3240 R0PTRTYPE(PGMSTATS *) pStatsR0;
3241 RCPTRTYPE(PGMSTATS *) pStatsRC;
3242 RTRCPTR RCPtrAlignment;
3243 /** @} */
3244#endif
3245} PGM;
3246#ifndef IN_TSTVMSTRUCTGC /* HACK */
3247AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3248AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3249AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3250AssertCompileMemberAlignment(PGM, CritSect, 8);
3251AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3252AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3253AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3254AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3255AssertCompileMemberAlignment(PGM, cRelocations, 8);
3256#endif /* !IN_TSTVMSTRUCTGC */
3257/** Pointer to the PGM instance data. */
3258typedef PGM *PPGM;
3259
3260
3261
3262typedef struct PGMCPUSTATS
3263{
3264 /* Common */
3265 STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /**< SyncPT - PD distribution. */
3266 STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /**< SyncPage - PD distribution. */
3267
3268 /* R0 only: */
3269 STAMPROFILE StatR0NpMiscfg; /**< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. */
3270 STAMCOUNTER StatR0NpMiscfgSyncPage; /**< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). */
3271
3272 /* RZ only: */
3273 STAMPROFILE StatRZTrap0e; /**< RC/R0: PGMTrap0eHandler() profiling. */
3274 STAMPROFILE StatRZTrap0eTime2Ballooned; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. */
3275 STAMPROFILE StatRZTrap0eTime2CSAM; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. */
3276 STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. */
3277 STAMPROFILE StatRZTrap0eTime2GuestTrap; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. */
3278 STAMPROFILE StatRZTrap0eTime2HndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. */
3279 STAMPROFILE StatRZTrap0eTime2HndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. */
3280 STAMPROFILE StatRZTrap0eTime2HndUnhandled; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. */
3281 STAMPROFILE StatRZTrap0eTime2InvalidPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. */
3282 STAMPROFILE StatRZTrap0eTime2MakeWritable; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. */
3283 STAMPROFILE StatRZTrap0eTime2Mapping; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. */
3284 STAMPROFILE StatRZTrap0eTime2Misc; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. */
3285 STAMPROFILE StatRZTrap0eTime2OutOfSync; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. */
3286 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. */
3287 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. */
3288 STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. */
3289 STAMPROFILE StatRZTrap0eTime2SyncPT; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. */
3290 STAMPROFILE StatRZTrap0eTime2WPEmulation; /**< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. */
3291 STAMCOUNTER StatRZTrap0eConflicts; /**< RC/R0: The number of times \#PF was caused by an undetected conflict. */
3292 STAMCOUNTER StatRZTrap0eHandlersMapping; /**< RC/R0: Number of traps due to access handlers in mappings. */
3293 STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /**< RC/R0: Number of out-of-sync handled pages. */
3294 STAMCOUNTER StatRZTrap0eHandlersPhysAll; /**< RC/R0: Number of traps due to physical all-access handlers. */
3295 STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /**< RC/R0: Number of the physical all-access handler traps using the optimization. */
3296 STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /**< RC/R0: Number of traps due to write-physical access handlers. */
3297 STAMCOUNTER StatRZTrap0eHandlersVirtual; /**< RC/R0: Number of traps due to virtual access handlers. */
3298 STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /**< RC/R0: Number of traps due to virtual access handlers found by physical address. */
3299 STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/**< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). */
3300 STAMCOUNTER StatRZTrap0eHandlersUnhandled; /**< RC/R0: Number of traps due to access outside range of monitored page(s). */
3301 STAMCOUNTER StatRZTrap0eHandlersInvalid; /**< RC/R0: Number of traps due to access to invalid physical memory. */
3302 STAMCOUNTER StatRZTrap0eUSNotPresentRead; /**< RC/R0: \#PF err kind */
3303 STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /**< RC/R0: \#PF err kind */
3304 STAMCOUNTER StatRZTrap0eUSWrite; /**< RC/R0: \#PF err kind */
3305 STAMCOUNTER StatRZTrap0eUSReserved; /**< RC/R0: \#PF err kind */
3306 STAMCOUNTER StatRZTrap0eUSNXE; /**< RC/R0: \#PF err kind */
3307 STAMCOUNTER StatRZTrap0eUSRead; /**< RC/R0: \#PF err kind */
3308 STAMCOUNTER StatRZTrap0eSVNotPresentRead; /**< RC/R0: \#PF err kind */
3309 STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /**< RC/R0: \#PF err kind */
3310 STAMCOUNTER StatRZTrap0eSVWrite; /**< RC/R0: \#PF err kind */
3311 STAMCOUNTER StatRZTrap0eSVReserved; /**< RC/R0: \#PF err kind */
3312 STAMCOUNTER StatRZTrap0eSNXE; /**< RC/R0: \#PF err kind */
3313 STAMCOUNTER StatRZTrap0eGuestPF; /**< RC/R0: Real guest \#PFs. */
3314 STAMCOUNTER StatRZTrap0eGuestPFMapping; /**< RC/R0: Real guest \#PF to HMA or other mapping. */
3315 STAMCOUNTER StatRZTrap0eWPEmulInRZ; /**< RC/R0: WP=0 virtualization trap, handled. */
3316 STAMCOUNTER StatRZTrap0eWPEmulToR3; /**< RC/R0: WP=0 virtualization trap, chickened out. */
3317 STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /**< RC/R0: PD distribution of the \#PFs. */
3318 STAMCOUNTER StatRZGuestCR3WriteHandled; /**< RC/R0: The number of times WriteHandlerCR3() was successfully called. */
3319 STAMCOUNTER StatRZGuestCR3WriteUnhandled; /**< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. */
3320 STAMCOUNTER StatRZGuestCR3WriteConflict; /**< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. */
3321 STAMCOUNTER StatRZGuestROMWriteHandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. */
3322 STAMCOUNTER StatRZGuestROMWriteUnhandled; /**< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler */
3323 STAMCOUNTER StatRZDynMapMigrateInvlPg; /**< RZ: invlpg in PGMR0DynMapMigrateAutoSet. */
3324 STAMPROFILE StatRZDynMapGCPageInl; /**< RZ: Calls to pgmRZDynMapGCPageInlined. */
3325 STAMCOUNTER StatRZDynMapGCPageInlHits; /**< RZ: Hash table lookup hits. */
3326 STAMCOUNTER StatRZDynMapGCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3327 STAMCOUNTER StatRZDynMapGCPageInlRamHits; /**< RZ: 1st ram range hits. */
3328 STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /**< RZ: 1st ram range misses, takes slow path. */
3329 STAMPROFILE StatRZDynMapHCPageInl; /**< RZ: Calls to pgmRZDynMapHCPageInlined. */
3330 STAMCOUNTER StatRZDynMapHCPageInlHits; /**< RZ: Hash table lookup hits. */
3331 STAMCOUNTER StatRZDynMapHCPageInlMisses; /**< RZ: Misses that falls back to the code common. */
3332 STAMPROFILE StatRZDynMapHCPage; /**< RZ: Calls to pgmRZDynMapHCPageCommon. */
3333 STAMCOUNTER StatRZDynMapSetOptimize; /**< RZ: Calls to pgmRZDynMapOptimizeAutoSet. */
3334 STAMCOUNTER StatRZDynMapSetSearchFlushes; /**< RZ: Set search restoring to subset flushes. */
3335 STAMCOUNTER StatRZDynMapSetSearchHits; /**< RZ: Set search hits. */
3336 STAMCOUNTER StatRZDynMapSetSearchMisses; /**< RZ: Set search misses. */
3337 STAMCOUNTER StatRZDynMapPage; /**< RZ: Calls to pgmR0DynMapPage. */
3338 STAMCOUNTER StatRZDynMapPageHits0; /**< RZ: Hits at iPage+0. */
3339 STAMCOUNTER StatRZDynMapPageHits1; /**< RZ: Hits at iPage+1. */
3340 STAMCOUNTER StatRZDynMapPageHits2; /**< RZ: Hits at iPage+2. */
3341 STAMCOUNTER StatRZDynMapPageInvlPg; /**< RZ: invlpg. */
3342 STAMCOUNTER StatRZDynMapPageSlow; /**< RZ: Calls to pgmR0DynMapPageSlow. */
3343 STAMCOUNTER StatRZDynMapPageSlowLoopHits; /**< RZ: Hits in the pgmR0DynMapPageSlow search loop. */
3344 STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /**< RZ: Misses in the pgmR0DynMapPageSlow search loop. */
3345 //STAMCOUNTER StatRZDynMapPageSlowLostHits; /**< RZ: Lost hits. */
3346 STAMCOUNTER StatRZDynMapSubsets; /**< RZ: Times PGMDynMapPushAutoSubset was called. */
3347 STAMCOUNTER StatRZDynMapPopFlushes; /**< RZ: Times PGMDynMapPopAutoSubset flushes the subset. */
3348 STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /**< RZ: Set fill distribution, percent. */
3349
3350 /* HC - R3 and (maybe) R0: */
3351
3352 /* RZ & R3: */
3353 STAMPROFILE StatRZSyncCR3; /**< RC/R0: PGMSyncCR3() profiling. */
3354 STAMPROFILE StatRZSyncCR3Handlers; /**< RC/R0: Profiling of the PGMSyncCR3() update handler section. */
3355 STAMCOUNTER StatRZSyncCR3Global; /**< RC/R0: The number of global CR3 syncs. */
3356 STAMCOUNTER StatRZSyncCR3NotGlobal; /**< RC/R0: The number of non-global CR3 syncs. */
3357 STAMCOUNTER StatRZSyncCR3DstCacheHit; /**< RC/R0: The number of times we got some kind of cache hit on a page table. */
3358 STAMCOUNTER StatRZSyncCR3DstFreed; /**< RC/R0: The number of times we've had to free a shadow entry. */
3359 STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /**< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. */
3360 STAMCOUNTER StatRZSyncCR3DstNotPresent; /**< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. */
3361 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /**< RC/R0: The number of times a global page directory wasn't flushed. */
3362 STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /**< RC/R0: The number of times a page table with only global entries wasn't flushed. */
3363 STAMPROFILE StatRZSyncPT; /**< RC/R0: PGMSyncPT() profiling. */
3364 STAMCOUNTER StatRZSyncPTFailed; /**< RC/R0: The number of times PGMSyncPT() failed. */
3365 STAMCOUNTER StatRZSyncPT4K; /**< RC/R0: Number of 4KB syncs. */
3366 STAMCOUNTER StatRZSyncPT4M; /**< RC/R0: Number of 4MB syncs. */
3367 STAMCOUNTER StatRZSyncPagePDNAs; /**< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3368 STAMCOUNTER StatRZSyncPagePDOutOfSync; /**< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. */
3369 STAMCOUNTER StatRZAccessedPage; /**< RC/R0: The number of pages marked not present for accessed bit emulation. */
3370 STAMPROFILE StatRZDirtyBitTracking; /**< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. */
3371 STAMCOUNTER StatRZDirtyPage; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3372 STAMCOUNTER StatRZDirtyPageBig; /**< RC/R0: The number of pages marked read-only for dirty bit tracking. */
3373 STAMCOUNTER StatRZDirtyPageSkipped; /**< RC/R0: The number of pages already dirty or readonly. */
3374 STAMCOUNTER StatRZDirtyPageTrap; /**< RC/R0: The number of traps generated for dirty bit tracking. */
3375 STAMCOUNTER StatRZDirtyPageStale; /**< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) */
3376 STAMCOUNTER StatRZDirtyTrackRealPF; /**< RC/R0: The number of real pages faults during dirty bit tracking. */
3377 STAMCOUNTER StatRZDirtiedPage; /**< RC/R0: The number of pages marked dirty because of write accesses. */
3378 STAMCOUNTER StatRZPageAlreadyDirty; /**< RC/R0: The number of pages already marked dirty because of write accesses. */
3379 STAMPROFILE StatRZInvalidatePage; /**< RC/R0: PGMInvalidatePage() profiling. */
3380 STAMCOUNTER StatRZInvalidatePage4KBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. */
3381 STAMCOUNTER StatRZInvalidatePage4MBPages; /**< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. */
3382 STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /**< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. */
3383 STAMCOUNTER StatRZInvalidatePagePDMappings; /**< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3384 STAMCOUNTER StatRZInvalidatePagePDNAs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3385 STAMCOUNTER StatRZInvalidatePagePDNPs; /**< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. */
3386 STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /**< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3387 STAMCOUNTER StatRZInvalidatePageSkipped; /**< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3388 STAMCOUNTER StatRZPageOutOfSyncUser; /**< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3389 STAMCOUNTER StatRZPageOutOfSyncSupervisor; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3390 STAMCOUNTER StatRZPageOutOfSyncUserWrite; /**< RC/R0: The number of times user page is out of sync was detected in \#PF. */
3391 STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /**< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. */
3392 STAMCOUNTER StatRZPageOutOfSyncBallloon; /**< RC/R0: The number of times a ballooned page was accessed (read). */
3393 STAMPROFILE StatRZPrefetch; /**< RC/R0: PGMPrefetchPage. */
3394 STAMPROFILE StatRZFlushTLB; /**< RC/R0: Profiling of the PGMFlushTLB() body. */
3395 STAMCOUNTER StatRZFlushTLBNewCR3; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3396 STAMCOUNTER StatRZFlushTLBNewCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3397 STAMCOUNTER StatRZFlushTLBSameCR3; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3398 STAMCOUNTER StatRZFlushTLBSameCR3Global; /**< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3399 STAMPROFILE StatRZGstModifyPage; /**< RC/R0: Profiling of the PGMGstModifyPage() body */
3400
3401 STAMPROFILE StatR3SyncCR3; /**< R3: PGMSyncCR3() profiling. */
3402 STAMPROFILE StatR3SyncCR3Handlers; /**< R3: Profiling of the PGMSyncCR3() update handler section. */
3403 STAMCOUNTER StatR3SyncCR3Global; /**< R3: The number of global CR3 syncs. */
3404 STAMCOUNTER StatR3SyncCR3NotGlobal; /**< R3: The number of non-global CR3 syncs. */
3405 STAMCOUNTER StatR3SyncCR3DstFreed; /**< R3: The number of times we've had to free a shadow entry. */
3406 STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /**< R3: The number of times we've had to free a shadow entry for which the source entry was not present. */
3407 STAMCOUNTER StatR3SyncCR3DstNotPresent; /**< R3: The number of times we've encountered a not present shadow entry for a present guest entry. */
3408 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /**< R3: The number of times a global page directory wasn't flushed. */
3409 STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /**< R3: The number of times a page table with only global entries wasn't flushed. */
3410 STAMCOUNTER StatR3SyncCR3DstCacheHit; /**< R3: The number of times we got some kind of cache hit on a page table. */
3411 STAMPROFILE StatR3SyncPT; /**< R3: PGMSyncPT() profiling. */
3412 STAMCOUNTER StatR3SyncPTFailed; /**< R3: The number of times PGMSyncPT() failed. */
3413 STAMCOUNTER StatR3SyncPT4K; /**< R3: Number of 4KB syncs. */
3414 STAMCOUNTER StatR3SyncPT4M; /**< R3: Number of 4MB syncs. */
3415 STAMCOUNTER StatR3SyncPagePDNAs; /**< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. */
3416 STAMCOUNTER StatR3SyncPagePDOutOfSync; /**< R3: The number of time we've encountered an out-of-sync PD in SyncPage. */
3417 STAMCOUNTER StatR3AccessedPage; /**< R3: The number of pages marked not present for accessed bit emulation. */
3418 STAMPROFILE StatR3DirtyBitTracking; /**< R3: Profiling the dirty bit tracking in CheckPageFault(). */
3419 STAMCOUNTER StatR3DirtyPage; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3420 STAMCOUNTER StatR3DirtyPageBig; /**< R3: The number of pages marked read-only for dirty bit tracking. */
3421 STAMCOUNTER StatR3DirtyPageSkipped; /**< R3: The number of pages already dirty or readonly. */
3422 STAMCOUNTER StatR3DirtyPageTrap; /**< R3: The number of traps generated for dirty bit tracking. */
3423 STAMCOUNTER StatR3DirtyTrackRealPF; /**< R3: The number of real pages faults during dirty bit tracking. */
3424 STAMCOUNTER StatR3DirtiedPage; /**< R3: The number of pages marked dirty because of write accesses. */
3425 STAMCOUNTER StatR3PageAlreadyDirty; /**< R3: The number of pages already marked dirty because of write accesses. */
3426 STAMPROFILE StatR3InvalidatePage; /**< R3: PGMInvalidatePage() profiling. */
3427 STAMCOUNTER StatR3InvalidatePage4KBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4KB page. */
3428 STAMCOUNTER StatR3InvalidatePage4MBPages; /**< R3: The number of times PGMInvalidatePage() was called for a 4MB page. */
3429 STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /**< R3: The number of times PGMInvalidatePage() skipped a 4MB page. */
3430 STAMCOUNTER StatR3InvalidatePagePDNAs; /**< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. */
3431 STAMCOUNTER StatR3InvalidatePagePDNPs; /**< R3: The number of times PGMInvalidatePage() was called for a not present page directory. */
3432 STAMCOUNTER StatR3InvalidatePagePDMappings; /**< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). */
3433 STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /**< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. */
3434 STAMCOUNTER StatR3InvalidatePageSkipped; /**< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. */
3435 STAMCOUNTER StatR3PageOutOfSyncUser; /**< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. */
3436 STAMCOUNTER StatR3PageOutOfSyncSupervisor; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. */
3437 STAMCOUNTER StatR3PageOutOfSyncUserWrite; /**< R3: The number of times user page is out of sync was detected in \#PF. */
3438 STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /**< R3: The number of times supervisor page is out of sync was detected in in \#PF. */
3439 STAMCOUNTER StatR3PageOutOfSyncBallloon; /**< R3: The number of times a ballooned page was accessed (read). */
3440 STAMPROFILE StatR3Prefetch; /**< R3: PGMPrefetchPage. */
3441 STAMPROFILE StatR3FlushTLB; /**< R3: Profiling of the PGMFlushTLB() body. */
3442 STAMCOUNTER StatR3FlushTLBNewCR3; /**< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) */
3443 STAMCOUNTER StatR3FlushTLBNewCR3Global; /**< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) */
3444 STAMCOUNTER StatR3FlushTLBSameCR3; /**< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) */
3445 STAMCOUNTER StatR3FlushTLBSameCR3Global; /**< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) */
3446 STAMPROFILE StatR3GstModifyPage; /**< R3: Profiling of the PGMGstModifyPage() body */
3447 /** @} */
3448} PGMCPUSTATS;
3449
3450
3451/**
3452 * Converts a PGMCPU pointer into a VM pointer.
3453 * @returns Pointer to the VM structure the PGM is part of.
3454 * @param pPGM Pointer to PGMCPU instance data.
3455 */
3456#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3457
3458/**
3459 * Converts a PGMCPU pointer into a PGM pointer.
3460 * @returns Pointer to the VM structure the PGM is part of.
3461 * @param pPGM Pointer to PGMCPU instance data.
3462 */
3463#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3464
3465/**
3466 * PGMCPU Data (part of VMCPU).
3467 */
3468typedef struct PGMCPU
3469{
3470 /** Offset to the VM structure. */
3471 int32_t offVM;
3472 /** Offset to the VMCPU structure. */
3473 int32_t offVCpu;
3474 /** Offset of the PGM structure relative to VMCPU. */
3475 int32_t offPGM;
3476 uint32_t uPadding0; /**< structure size alignment. */
3477
3478#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) || defined(VBOX_WITH_RAW_MODE)
3479 /** Automatically tracked physical memory mapping set.
3480 * Ring-0 and strict raw-mode builds. */
3481 PGMMAPSET AutoSet;
3482#endif
3483
3484 /** A20 gate mask.
3485 * Our current approach to A20 emulation is to let REM do it and don't bother
3486 * anywhere else. The interesting Guests will be operating with it enabled anyway.
3487 * But whould need arrise, we'll subject physical addresses to this mask. */
3488 RTGCPHYS GCPhysA20Mask;
3489 /** A20 gate state - boolean! */
3490 bool fA20Enabled;
3491 /** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3492 bool fNoExecuteEnabled;
3493 /** Unused bits. */
3494 bool afUnused[2];
3495
3496 /** What needs syncing (PGM_SYNC_*).
3497 * This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3498 * PGMFlushTLB, and PGMR3Load. */
3499 RTUINT fSyncFlags;
3500
3501 /** The shadow paging mode. */
3502 PGMMODE enmShadowMode;
3503 /** The guest paging mode. */
3504 PGMMODE enmGuestMode;
3505
3506 /** The current physical address representing in the guest CR3 register. */
3507 RTGCPHYS GCPhysCR3;
3508
3509 /** @name 32-bit Guest Paging.
3510 * @{ */
3511 /** The guest's page directory, R3 pointer. */
3512 R3PTRTYPE(PX86PD) pGst32BitPdR3;
3513#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3514 /** The guest's page directory, R0 pointer. */
3515 R0PTRTYPE(PX86PD) pGst32BitPdR0;
3516#endif
3517 /** The guest's page directory, static RC mapping. */
3518 RCPTRTYPE(PX86PD) pGst32BitPdRC;
3519 /** Mask containing the MBZ bits of a big page PDE. */
3520 uint32_t fGst32BitMbzBigPdeMask;
3521 /** Set if the page size extension (PSE) is enabled. */
3522 bool fGst32BitPageSizeExtension;
3523 /** Alignment padding. */
3524 bool afAlignment2[3];
3525 /** @} */
3526
3527 /** @name PAE Guest Paging.
3528 * @{ */
3529 /** The guest's page directory pointer table, static RC mapping. */
3530 RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3531 /** The guest's page directory pointer table, R3 pointer. */
3532 R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3533#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3534 /** The guest's page directory pointer table, R0 pointer. */
3535 R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3536#endif
3537
3538 /** The guest's page directories, R3 pointers.
3539 * These are individual pointers and don't have to be adjacent.
3540 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3541 R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3542 /** The guest's page directories, R0 pointers.
3543 * Same restrictions as apGstPaePDsR3. */
3544#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3545 R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3546#endif
3547 /** The guest's page directories, static GC mapping.
3548 * Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3549 * These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3550 RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3551 /** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC. */
3552 RTGCPHYS aGCPhysGstPaePDs[4];
3553 /** The physical addresses of the monitored guest page directories (PAE). */
3554 RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3555 /** Mask containing the MBZ PTE bits. */
3556 uint64_t fGstPaeMbzPteMask;
3557 /** Mask containing the MBZ PDE bits. */
3558 uint64_t fGstPaeMbzPdeMask;
3559 /** Mask containing the MBZ big page PDE bits. */
3560 uint64_t fGstPaeMbzBigPdeMask;
3561 /** Mask containing the MBZ PDPE bits. */
3562 uint64_t fGstPaeMbzPdpeMask;
3563 /** @} */
3564
3565 /** @name AMD64 Guest Paging.
3566 * @{ */
3567 /** The guest's page directory pointer table, R3 pointer. */
3568 R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3569#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3570 /** The guest's page directory pointer table, R0 pointer. */
3571 R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3572#else
3573 RTR0PTR alignment6b; /**< alignment equalizer. */
3574#endif
3575 /** Mask containing the MBZ PTE bits. */
3576 uint64_t fGstAmd64MbzPteMask;
3577 /** Mask containing the MBZ PDE bits. */
3578 uint64_t fGstAmd64MbzPdeMask;
3579 /** Mask containing the MBZ big page PDE bits. */
3580 uint64_t fGstAmd64MbzBigPdeMask;
3581 /** Mask containing the MBZ PDPE bits. */
3582 uint64_t fGstAmd64MbzPdpeMask;
3583 /** Mask containing the MBZ big page PDPE bits. */
3584 uint64_t fGstAmd64MbzBigPdpeMask;
3585 /** Mask containing the MBZ PML4E bits. */
3586 uint64_t fGstAmd64MbzPml4eMask;
3587 /** Mask containing the PDPE bits that we shadow. */
3588 uint64_t fGstAmd64ShadowedPdpeMask;
3589 /** Mask containing the PML4E bits that we shadow. */
3590 uint64_t fGstAmd64ShadowedPml4eMask;
3591 /** @} */
3592
3593 /** @name PAE and AMD64 Guest Paging.
3594 * @{ */
3595 /** Mask containing the PTE bits that we shadow. */
3596 uint64_t fGst64ShadowedPteMask;
3597 /** Mask containing the PDE bits that we shadow. */
3598 uint64_t fGst64ShadowedPdeMask;
3599 /** Mask containing the big page PDE bits that we shadow in the PDE. */
3600 uint64_t fGst64ShadowedBigPdeMask;
3601 /** Mask containing the big page PDE bits that we shadow in the PTE. */
3602 uint64_t fGst64ShadowedBigPde4PteMask;
3603 /** @} */
3604
3605 /** Pointer to the page of the current active CR3 - R3 Ptr. */
3606 R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3607 /** Pointer to the page of the current active CR3 - R0 Ptr. */
3608 R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3609 /** Pointer to the page of the current active CR3 - RC Ptr. */
3610 RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3611 /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
3612 uint32_t iShwUser;
3613 /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
3614 uint32_t iShwUserTable;
3615# if HC_ARCH_BITS == 64
3616 RTRCPTR alignment6; /**< structure size alignment. */
3617# endif
3618 /** @} */
3619
3620 /** @name Function pointers for Shadow paging.
3621 * @{
3622 */
3623 DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3624 DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3625 DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3626 DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3627
3628 DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3629 DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3630
3631 DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3632 DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3633
3634 /** @} */
3635
3636 /** @name Function pointers for Guest paging.
3637 * @{
3638 */
3639 DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3640 DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3641 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3642 DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3643 DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3644 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3645 DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3646 DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3647#if HC_ARCH_BITS == 64
3648 RTRCPTR alignment3; /**< structure size alignment. */
3649#endif
3650
3651 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3652 DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3653 DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3654 /** @} */
3655
3656 /** @name Function pointers for Both Shadow and Guest paging.
3657 * @{
3658 */
3659 DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3660 /* no pfnR3BthTrap0eHandler */
3661 DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3662 DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3663 DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3664 DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3665 DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3666 DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3667 DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3668
3669 DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3670 DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3671 DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3672 DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3673 DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3674 DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3675 DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3676 DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3677
3678 DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3679 DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3680 DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3681 DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3682 DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3683 DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3684 DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3685 DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3686#if 0
3687 RTRCPTR alignment2; /**< structure size alignment. */
3688#endif
3689 /** @} */
3690
3691 /** For saving stack space, the disassembler state is allocated here instead of
3692 * on the stack.
3693 * @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
3694 union
3695 {
3696 /** The disassembler scratch space. */
3697 DISCPUSTATE DisState;
3698 /** Padding. */
3699 uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
3700 };
3701
3702 /** Count the number of pgm pool access handler calls. */
3703 uint64_t cPoolAccessHandler;
3704
3705 /** @name Release Statistics
3706 * @{ */
3707 /** The number of times the guest has switched mode since last reset or statistics reset. */
3708 STAMCOUNTER cGuestModeChanges;
3709 /** @} */
3710
3711#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3712 /** @name Statistics
3713 * @{ */
3714 /** RC: Pointer to the statistics. */
3715 RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
3716 /** RC: Which statistic this \#PF should be attributed to. */
3717 RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
3718 /** R0: Pointer to the statistics. */
3719 R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
3720 /** R0: Which statistic this \#PF should be attributed to. */
3721 R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
3722 /** R3: Pointer to the statistics. */
3723 R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
3724 /** Alignment padding. */
3725 RTR3PTR pPaddingR3;
3726 /** @} */
3727#endif /* VBOX_WITH_STATISTICS */
3728} PGMCPU;
3729/** Pointer to the per-cpu PGM data. */
3730typedef PGMCPU *PPGMCPU;
3731
3732
3733/** @name PGM::fSyncFlags Flags
3734 * @{
3735 */
3736/** Updates the virtual access handler state bit in PGMPAGE. */
3737#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
3738/** Always sync CR3. */
3739#define PGM_SYNC_ALWAYS RT_BIT(1)
3740/** Check monitoring on next CR3 (re)load and invalidate page.
3741 * @todo This is obsolete now. Remove after 2.2.0 is branched off. */
3742#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
3743/** Check guest mapping in SyncCR3. */
3744#define PGM_SYNC_MAP_CR3 RT_BIT(3)
3745/** Clear the page pool (a light weight flush). */
3746#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
3747#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
3748/** @} */
3749
3750
3751RT_C_DECLS_BEGIN
3752
3753int pgmLock(PVM pVM);
3754void pgmUnlock(PVM pVM);
3755
3756int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
3757int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
3758int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
3759PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
3760int pgmMapResolveConflicts(PVM pVM);
3761DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3762
3763void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
3764bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
3765void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
3766int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER *ppVirt, unsigned *piPage);
3767DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
3768#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
3769void pgmHandlerVirtualDumpPhysPages(PVM pVM);
3770#else
3771# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
3772#endif
3773DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
3774int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
3775
3776int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3777int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
3778int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
3779int pgmPhysPageLoadIntoTlb(PPGM pPGM, RTGCPHYS GCPhys);
3780int pgmPhysPageLoadIntoTlbWithPage(PPGM pPGM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3781void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
3782int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
3783int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3784int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3785int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
3786int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
3787int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
3788int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv);
3789VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3790VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
3791int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
3792
3793#ifdef IN_RING3
3794void pgmR3PhysRelinkRamRanges(PVM pVM);
3795int pgmR3PhysRamPreAllocate(PVM pVM);
3796int pgmR3PhysRamReset(PVM pVM);
3797int pgmR3PhysRomReset(PVM pVM);
3798int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
3799int pgmR3PhysRamTerm(PVM pVM);
3800void pgmR3PhysRomTerm(PVM pVM);
3801
3802int pgmR3PoolInit(PVM pVM);
3803void pgmR3PoolRelocate(PVM pVM);
3804void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
3805void pgmR3PoolReset(PVM pVM);
3806void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
3807DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
3808void pgmR3PoolWriteProtectPages(PVM pVM);
3809
3810#endif /* IN_RING3 */
3811#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) || defined(IN_RC)
3812int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3813int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
3814# ifdef LOG_ENABLED
3815void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
3816# else
3817void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
3818# endif
3819#endif
3820int pgmPoolAllocEx(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, uint16_t iUser,
3821 uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
3822
3823DECLINLINE(int) pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, uint16_t iUser, uint32_t iUserTable,
3824 PPPGMPOOLPAGE ppPage)
3825{
3826 return pgmPoolAllocEx(pVM, GCPhys, enmKind, PGMPOOLACCESS_DONTCARE, iUser, iUserTable, false, ppPage);
3827}
3828
3829void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
3830void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
3831int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
3832void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
3833PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
3834PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
3835int pgmPoolSyncCR3(PVMCPU pVCpu);
3836bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
3837void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
3838int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
3839void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
3840uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
3841void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
3842void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
3843int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3844void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3845
3846void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
3847void pgmPoolResetDirtyPages(PVM pVM);
3848void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
3849
3850int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu);
3851int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
3852
3853void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
3854void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
3855int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3856int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
3857
3858int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
3859int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
3860
3861int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
3862int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
3863int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
3864int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
3865
3866# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64
3867DECLCALLBACK(int) pgmR3CmdCheckDuplicatePages(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
3868DECLCALLBACK(int) pgmR3CmdShowSharedModules(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs);
3869# endif
3870
3871RT_C_DECLS_END
3872
3873/** @} */
3874
3875#endif
3876
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette